1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*****************************************************************************
6 * $Date: 2005/06/21 18:29:47 $ *
8 * part of the Chelsio 10Gb Ethernet Driver. *
11 * http://www.chelsio.com *
13 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
14 * All rights reserved. *
16 * Maintainers: maintainers@chelsio.com *
18 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
19 * Tina Yang <tainay@chelsio.com> *
20 * Felix Marti <felix@chelsio.com> *
21 * Scott Bardone <sbardone@chelsio.com> *
22 * Kurt Ottaway <kottaway@chelsio.com> *
23 * Frank DiMambro <frank@chelsio.com> *
27 ****************************************************************************/
29 #ifndef _CXGB_CPL5_CMD_H_
30 #define _CXGB_CPL5_CMD_H_
32 #include <asm/byteorder.h>
34 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
35 #error "Adjust your <asm/byteorder.h> defines"
39 CPL_PASS_OPEN_REQ = 0x1,
40 CPL_PASS_OPEN_RPL = 0x2,
41 CPL_PASS_ESTABLISH = 0x3,
42 CPL_PASS_ACCEPT_REQ = 0xE,
43 CPL_PASS_ACCEPT_RPL = 0x4,
44 CPL_ACT_OPEN_REQ = 0x5,
45 CPL_ACT_OPEN_RPL = 0x6,
46 CPL_CLOSE_CON_REQ = 0x7,
47 CPL_CLOSE_CON_RPL = 0x8,
48 CPL_CLOSE_LISTSRV_REQ = 0x9,
49 CPL_CLOSE_LISTSRV_RPL = 0xA,
53 CPL_ACT_ESTABLISH = 0x17,
56 CPL_GET_TCB_RPL = 0x25,
58 CPL_SET_TCB_FIELD = 0x27,
59 CPL_SET_TCB_RPL = 0x28,
63 CPL_PCMD_READ_RPL = 0x32,
67 CPL_RX_DATA_DDP = 0xA1,
68 CPL_RX_DATA_ACK = 0xA3,
70 CPL_RX_ISCSI_HDR = 0xAF,
71 CPL_TX_DATA_ACK = 0xB0,
74 CPL_TX_PKT_LSO = 0xB6,
76 CPL_RTE_DELETE_REQ = 0xC0,
77 CPL_RTE_DELETE_RPL = 0xC1,
78 CPL_RTE_WRITE_REQ = 0xC2,
79 CPL_RTE_WRITE_RPL = 0xD3,
80 CPL_RTE_READ_REQ = 0xC3,
81 CPL_RTE_READ_RPL = 0xC4,
82 CPL_L2T_WRITE_REQ = 0xC5,
83 CPL_L2T_WRITE_RPL = 0xD4,
84 CPL_L2T_READ_REQ = 0xC6,
85 CPL_L2T_READ_RPL = 0xC7,
86 CPL_SMT_WRITE_REQ = 0xC8,
87 CPL_SMT_WRITE_RPL = 0xD5,
88 CPL_SMT_READ_REQ = 0xC9,
89 CPL_SMT_READ_RPL = 0xCA,
90 CPL_ARP_MISS_REQ = 0xCD,
91 CPL_ARP_MISS_RPL = 0xCE,
92 CPL_MIGRATE_C2T_REQ = 0xDC,
93 CPL_MIGRATE_C2T_RPL = 0xDD,
96 /* internal: driver -> TOM */
100 #define NUM_CPL_CMDS 256
104 CPL_ERR_TCAM_PARITY = 1,
105 CPL_ERR_TCAM_FULL = 3,
106 CPL_ERR_CONN_RESET = 20,
107 CPL_ERR_CONN_EXIST = 22,
108 CPL_ERR_ARP_MISS = 23,
109 CPL_ERR_BAD_SYN = 24,
110 CPL_ERR_CONN_TIMEDOUT = 30,
111 CPL_ERR_XMIT_TIMEDOUT = 31,
112 CPL_ERR_PERSIST_TIMEDOUT = 32,
113 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
114 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
115 CPL_ERR_ABORT_FAILED = 42,
120 CPL_CONN_POLICY_AUTO = 0,
121 CPL_CONN_POLICY_ASK = 1,
122 CPL_CONN_POLICY_DENY = 3
134 CPL_PASS_OPEN_ACCEPT,
139 CPL_ABORT_SEND_RST = 0,
141 CPL_ABORT_POST_CLOSE_REQ = 2
144 enum { // TX_PKT_LSO ethernet types
157 #define V_OPCODE(x) ((x) << S_OPCODE)
158 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
159 #define G_TID(x) ((x) & 0xFFFFFF)
161 /* tid is assumed to be 24-bits */
162 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
164 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
166 /* extract the TID from a CPL command */
167 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
172 #if defined(__LITTLE_ENDIAN_BITFIELD)
185 struct cpl_pass_open_req {
197 struct cpl_pass_open_rpl {
207 struct cpl_pass_establish {
220 struct cpl_pass_accept_req {
227 struct tcp_options tcp_options;
233 u32 unknown_tcp_options;
236 struct cpl_pass_accept_rpl {
251 struct cpl_act_open_req {
263 struct cpl_act_open_rpl {
274 struct cpl_act_establish {
291 struct cpl_get_tcb_rpl {
304 struct cpl_set_tcb_field {
312 struct cpl_set_tcb_rpl {
325 struct cpl_pcmd_read {
333 struct cpl_pcmd_read_rpl {
338 struct cpl_close_con_req {
343 struct cpl_close_con_rpl {
351 struct cpl_close_listserv_req {
356 struct cpl_close_listserv_rpl {
362 struct cpl_abort_req {
370 struct cpl_abort_rpl {
378 struct cpl_peer_close {
391 struct cpl_tx_data_ack {
405 struct cpl_rx_data_ack {
410 struct cpl_rx_data_ddp {
422 * We want this header's alignment to be no more stringent than 2-byte aligned.
423 * All fields are u8 or u16 except for the length. However that field is not
424 * used so we break it into 2 16-bit parts to easily meet our alignment needs.
428 #if defined(__LITTLE_ENDIAN_BITFIELD)
446 struct cpl_tx_pkt_lso {
448 #if defined(__LITTLE_ENDIAN_BITFIELD)
465 #if defined(__LITTLE_ENDIAN_BITFIELD)
477 #if defined(__LITTLE_ENDIAN_BITFIELD)
495 struct cpl_l2t_write_req {
502 struct cpl_l2t_write_rpl {
508 struct cpl_l2t_read_req {
514 struct cpl_l2t_read_rpl {
521 struct cpl_smt_write_req {
524 #if defined(__LITTLE_ENDIAN_BITFIELD)
540 struct cpl_smt_write_rpl {
546 struct cpl_smt_read_req {
549 #if defined(__LITTLE_ENDIAN_BITFIELD)
559 struct cpl_smt_read_rpl {
562 #if defined(__LITTLE_ENDIAN_BITFIELD)
578 struct cpl_rte_delete_req {
583 struct cpl_rte_delete_rpl {
589 struct cpl_rte_write_req {
596 struct cpl_rte_write_rpl {
602 struct cpl_rte_read_req {
607 struct cpl_rte_read_rpl {
612 #if defined(__LITTLE_ENDIAN_BITFIELD)
623 struct cpl_mss_change {
628 #endif /* _CXGB_CPL5_CMD_H_ */