1 /*****************************************************************************
5 * $Date: 2005/06/21 18:29:47 $ *
7 * part of the Chelsio 10Gb Ethernet Driver. *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, see <http://www.gnu.org/licenses/>. *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
17 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * http://www.chelsio.com *
22 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
23 * All rights reserved. *
25 * Maintainers: maintainers@chelsio.com *
27 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
28 * Tina Yang <tainay@chelsio.com> *
29 * Felix Marti <felix@chelsio.com> *
30 * Scott Bardone <sbardone@chelsio.com> *
31 * Kurt Ottaway <kottaway@chelsio.com> *
32 * Frank DiMambro <frank@chelsio.com> *
36 ****************************************************************************/
38 #ifndef _CXGB_CPL5_CMD_H_
39 #define _CXGB_CPL5_CMD_H_
41 #include <asm/byteorder.h>
43 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
44 #error "Adjust your <asm/byteorder.h> defines"
48 CPL_PASS_OPEN_REQ = 0x1,
49 CPL_PASS_OPEN_RPL = 0x2,
50 CPL_PASS_ESTABLISH = 0x3,
51 CPL_PASS_ACCEPT_REQ = 0xE,
52 CPL_PASS_ACCEPT_RPL = 0x4,
53 CPL_ACT_OPEN_REQ = 0x5,
54 CPL_ACT_OPEN_RPL = 0x6,
55 CPL_CLOSE_CON_REQ = 0x7,
56 CPL_CLOSE_CON_RPL = 0x8,
57 CPL_CLOSE_LISTSRV_REQ = 0x9,
58 CPL_CLOSE_LISTSRV_RPL = 0xA,
62 CPL_ACT_ESTABLISH = 0x17,
65 CPL_GET_TCB_RPL = 0x25,
67 CPL_SET_TCB_FIELD = 0x27,
68 CPL_SET_TCB_RPL = 0x28,
72 CPL_PCMD_READ_RPL = 0x32,
76 CPL_RX_DATA_DDP = 0xA1,
77 CPL_RX_DATA_ACK = 0xA3,
79 CPL_RX_ISCSI_HDR = 0xAF,
80 CPL_TX_DATA_ACK = 0xB0,
83 CPL_TX_PKT_LSO = 0xB6,
85 CPL_RTE_DELETE_REQ = 0xC0,
86 CPL_RTE_DELETE_RPL = 0xC1,
87 CPL_RTE_WRITE_REQ = 0xC2,
88 CPL_RTE_WRITE_RPL = 0xD3,
89 CPL_RTE_READ_REQ = 0xC3,
90 CPL_RTE_READ_RPL = 0xC4,
91 CPL_L2T_WRITE_REQ = 0xC5,
92 CPL_L2T_WRITE_RPL = 0xD4,
93 CPL_L2T_READ_REQ = 0xC6,
94 CPL_L2T_READ_RPL = 0xC7,
95 CPL_SMT_WRITE_REQ = 0xC8,
96 CPL_SMT_WRITE_RPL = 0xD5,
97 CPL_SMT_READ_REQ = 0xC9,
98 CPL_SMT_READ_RPL = 0xCA,
99 CPL_ARP_MISS_REQ = 0xCD,
100 CPL_ARP_MISS_RPL = 0xCE,
101 CPL_MIGRATE_C2T_REQ = 0xDC,
102 CPL_MIGRATE_C2T_RPL = 0xDD,
105 /* internal: driver -> TOM */
106 CPL_MSS_CHANGE = 0xE1
109 #define NUM_CPL_CMDS 256
113 CPL_ERR_TCAM_PARITY = 1,
114 CPL_ERR_TCAM_FULL = 3,
115 CPL_ERR_CONN_RESET = 20,
116 CPL_ERR_CONN_EXIST = 22,
117 CPL_ERR_ARP_MISS = 23,
118 CPL_ERR_BAD_SYN = 24,
119 CPL_ERR_CONN_TIMEDOUT = 30,
120 CPL_ERR_XMIT_TIMEDOUT = 31,
121 CPL_ERR_PERSIST_TIMEDOUT = 32,
122 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
123 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
124 CPL_ERR_ABORT_FAILED = 42,
129 CPL_CONN_POLICY_AUTO = 0,
130 CPL_CONN_POLICY_ASK = 1,
131 CPL_CONN_POLICY_DENY = 3
143 CPL_PASS_OPEN_ACCEPT,
148 CPL_ABORT_SEND_RST = 0,
150 CPL_ABORT_POST_CLOSE_REQ = 2
153 enum { // TX_PKT_LSO ethernet types
166 #define V_OPCODE(x) ((x) << S_OPCODE)
167 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
168 #define G_TID(x) ((x) & 0xFFFFFF)
170 /* tid is assumed to be 24-bits */
171 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
173 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
175 /* extract the TID from a CPL command */
176 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
181 #if defined(__LITTLE_ENDIAN_BITFIELD)
194 struct cpl_pass_open_req {
206 struct cpl_pass_open_rpl {
216 struct cpl_pass_establish {
229 struct cpl_pass_accept_req {
236 struct tcp_options tcp_options;
242 u32 unknown_tcp_options;
245 struct cpl_pass_accept_rpl {
260 struct cpl_act_open_req {
272 struct cpl_act_open_rpl {
283 struct cpl_act_establish {
300 struct cpl_get_tcb_rpl {
313 struct cpl_set_tcb_field {
321 struct cpl_set_tcb_rpl {
334 struct cpl_pcmd_read {
342 struct cpl_pcmd_read_rpl {
347 struct cpl_close_con_req {
352 struct cpl_close_con_rpl {
360 struct cpl_close_listserv_req {
365 struct cpl_close_listserv_rpl {
371 struct cpl_abort_req {
379 struct cpl_abort_rpl {
387 struct cpl_peer_close {
400 struct cpl_tx_data_ack {
414 struct cpl_rx_data_ack {
419 struct cpl_rx_data_ddp {
431 * We want this header's alignment to be no more stringent than 2-byte aligned.
432 * All fields are u8 or u16 except for the length. However that field is not
433 * used so we break it into 2 16-bit parts to easily meet our alignment needs.
437 #if defined(__LITTLE_ENDIAN_BITFIELD)
455 struct cpl_tx_pkt_lso {
457 #if defined(__LITTLE_ENDIAN_BITFIELD)
474 #if defined(__LITTLE_ENDIAN_BITFIELD)
486 #if defined(__LITTLE_ENDIAN_BITFIELD)
504 struct cpl_l2t_write_req {
511 struct cpl_l2t_write_rpl {
517 struct cpl_l2t_read_req {
523 struct cpl_l2t_read_rpl {
530 struct cpl_smt_write_req {
533 #if defined(__LITTLE_ENDIAN_BITFIELD)
549 struct cpl_smt_write_rpl {
555 struct cpl_smt_read_req {
558 #if defined(__LITTLE_ENDIAN_BITFIELD)
568 struct cpl_smt_read_rpl {
571 #if defined(__LITTLE_ENDIAN_BITFIELD)
587 struct cpl_rte_delete_req {
592 struct cpl_rte_delete_rpl {
598 struct cpl_rte_write_req {
605 struct cpl_rte_write_rpl {
611 struct cpl_rte_read_req {
616 struct cpl_rte_read_rpl {
621 #if defined(__LITTLE_ENDIAN_BITFIELD)
632 struct cpl_mss_change {
637 #endif /* _CXGB_CPL5_CMD_H_ */