2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
36 int lmacid; /* ID within BGX */
37 int lmacid_bd; /* ID on board */
38 struct net_device netdev;
39 struct phy_device *phydev;
40 unsigned int last_duplex;
41 unsigned int last_link;
42 unsigned int last_speed;
44 struct delayed_work dwork;
45 struct workqueue_struct *check_link;
50 struct lmac lmac[MAX_LMAC_PER_BGX];
54 void __iomem *reg_base;
60 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
61 static int lmac_count; /* Total no of LMACs in system */
63 static int bgx_xaui_check_link(struct lmac *lmac);
65 /* Supported devices */
66 static const struct pci_device_id bgx_id_table[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
69 { 0, } /* end of table */
72 MODULE_AUTHOR("Cavium Inc");
73 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
74 MODULE_LICENSE("GPL v2");
75 MODULE_VERSION(DRV_VERSION);
76 MODULE_DEVICE_TABLE(pci, bgx_id_table);
78 /* The Cavium ThunderX network controller can *only* be found in SoCs
79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
80 * registers on this platform are implicitly strongly ordered with respect
81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
82 * with no memory barriers in this driver. The readq()/writeq() functions add
83 * explicit ordering operation which in this case are redundant, and only
87 /* Register read/write APIs */
88 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
90 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
92 return readq_relaxed(addr);
95 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
97 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
99 writeq_relaxed(val, addr);
102 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
104 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
106 writeq_relaxed(val | readq_relaxed(addr), addr);
109 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
115 reg_val = bgx_reg_read(bgx, lmac, reg);
116 if (zero && !(reg_val & mask))
118 if (!zero && (reg_val & mask))
120 usleep_range(1000, 2000);
126 /* Return number of BGX present in HW */
127 unsigned bgx_get_map(int node)
132 for (i = 0; i < MAX_BGX_PER_NODE; i++) {
133 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
139 EXPORT_SYMBOL(bgx_get_map);
141 /* Return number of LMAC configured for this BGX */
142 int bgx_get_lmac_count(int node, int bgx_idx)
146 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
148 return bgx->lmac_count;
152 EXPORT_SYMBOL(bgx_get_lmac_count);
154 /* Returns the current link status of LMAC */
155 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
157 struct bgx_link_status *link = (struct bgx_link_status *)status;
161 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
165 lmac = &bgx->lmac[lmacid];
166 link->link_up = lmac->link_up;
167 link->duplex = lmac->last_duplex;
168 link->speed = lmac->last_speed;
170 EXPORT_SYMBOL(bgx_get_lmac_link_state);
172 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
174 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
177 return bgx->lmac[lmacid].mac;
181 EXPORT_SYMBOL(bgx_get_lmac_mac);
183 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
185 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
190 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
192 EXPORT_SYMBOL(bgx_set_lmac_mac);
194 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
196 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
202 lmac = &bgx->lmac[lmacid];
204 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
206 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
208 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
209 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
212 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
214 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
216 static void bgx_sgmii_change_link_state(struct lmac *lmac)
218 struct bgx *bgx = lmac->bgx;
223 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
225 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
227 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
228 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
231 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
232 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
233 port_cfg |= (lmac->last_duplex << 2);
235 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
238 switch (lmac->last_speed) {
240 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
241 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
242 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
243 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
244 misc_ctl |= 50; /* samp_pt */
245 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
246 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
249 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
250 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
251 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
252 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
253 misc_ctl |= 5; /* samp_pt */
254 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
255 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
258 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
259 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
260 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
261 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
262 misc_ctl |= 1; /* samp_pt */
263 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
264 if (lmac->last_duplex)
265 bgx_reg_write(bgx, lmac->lmacid,
266 BGX_GMP_GMI_TXX_BURST, 0);
268 bgx_reg_write(bgx, lmac->lmacid,
269 BGX_GMP_GMI_TXX_BURST, 8192);
274 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
275 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
277 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
281 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
283 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
284 xcv_setup_link(lmac->link_up, lmac->last_speed);
287 static void bgx_lmac_handler(struct net_device *netdev)
289 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
290 struct phy_device *phydev;
291 int link_changed = 0;
296 phydev = lmac->phydev;
298 if (!phydev->link && lmac->last_link)
302 (lmac->last_duplex != phydev->duplex ||
303 lmac->last_link != phydev->link ||
304 lmac->last_speed != phydev->speed)) {
308 lmac->last_link = phydev->link;
309 lmac->last_speed = phydev->speed;
310 lmac->last_duplex = phydev->duplex;
315 if (link_changed > 0)
316 lmac->link_up = true;
318 lmac->link_up = false;
321 bgx_sgmii_change_link_state(lmac);
323 bgx_xaui_check_link(lmac);
326 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
330 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
336 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
338 EXPORT_SYMBOL(bgx_get_rx_stats);
340 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
344 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
348 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
350 EXPORT_SYMBOL(bgx_get_tx_stats);
352 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
356 while (bgx->lmac[lmac].dmac > 0) {
357 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
358 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
359 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
360 bgx->lmac[lmac].dmac--;
364 /* Configure BGX LMAC in internal loopback mode */
365 void bgx_lmac_internal_loopback(int node, int bgx_idx,
366 int lmac_idx, bool enable)
372 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
376 lmac = &bgx->lmac[lmac_idx];
377 if (lmac->is_sgmii) {
378 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
380 cfg |= PCS_MRX_CTL_LOOPBACK1;
382 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
383 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
385 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
387 cfg |= SPU_CTL_LOOPBACK;
389 cfg &= ~SPU_CTL_LOOPBACK;
390 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
393 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
395 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
397 int lmacid = lmac->lmacid;
400 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
401 /* max packet size */
402 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
404 /* Disable frame alignment if using preamble */
405 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
407 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
410 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
413 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
414 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
415 PCS_MRX_CTL_RESET, true)) {
416 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
420 /* power down, reset autoneg, autoneg enable */
421 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
422 cfg &= ~PCS_MRX_CTL_PWR_DN;
423 cfg |= PCS_MRX_CTL_RST_AN;
425 cfg |= PCS_MRX_CTL_AN_EN;
427 /* In scenarios where PHY driver is not present or it's a
428 * non-standard PHY, FW sets AN_EN to inform Linux driver
429 * to do auto-neg and link polling or not.
431 if (cfg & PCS_MRX_CTL_AN_EN)
432 lmac->autoneg = true;
434 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
436 if (lmac->lmac_type == BGX_MODE_QSGMII) {
437 /* Disable disparity check for QSGMII */
438 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
439 cfg &= ~PCS_MISC_CTL_DISP_EN;
440 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
444 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
445 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
446 PCS_MRX_STATUS_AN_CPT, false)) {
447 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
455 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
458 int lmacid = lmac->lmacid;
461 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
462 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
463 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
468 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
470 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
472 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
473 /* Set interleaved running disparity for RXAUI */
474 if (lmac->lmac_type == BGX_MODE_RXAUI)
475 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
476 SPU_MISC_CTL_INTLV_RDISP);
478 /* Clear receive packet disable */
479 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
480 cfg &= ~SPU_MISC_CTL_RX_DIS;
481 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
483 /* clear all interrupts */
484 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
485 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
486 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
487 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
488 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
489 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
491 if (lmac->use_training) {
492 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
493 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
494 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
495 /* training enable */
496 bgx_reg_modify(bgx, lmacid,
497 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
500 /* Append FCS to each packet */
501 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
503 /* Disable forward error correction */
504 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
505 cfg &= ~SPU_FEC_CTL_FEC_EN;
506 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
508 /* Disable autoneg */
509 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
510 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
511 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
513 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
514 if (lmac->lmac_type == BGX_MODE_10G_KR)
516 else if (lmac->lmac_type == BGX_MODE_40G_KR)
519 cfg &= ~((1 << 23) | (1 << 24));
520 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
521 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
523 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
524 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
525 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
528 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
530 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
531 cfg &= ~SPU_CTL_LOW_POWER;
532 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
534 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
535 cfg &= ~SMU_TX_CTL_UNI_EN;
536 cfg |= SMU_TX_CTL_DIC_EN;
537 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
539 /* take lmac_count into account */
540 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
541 /* max packet size */
542 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
547 static int bgx_xaui_check_link(struct lmac *lmac)
549 struct bgx *bgx = lmac->bgx;
550 int lmacid = lmac->lmacid;
551 int lmac_type = lmac->lmac_type;
554 if (lmac->use_training) {
555 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
556 if (!(cfg & (1ull << 13))) {
557 cfg = (1ull << 13) | (1ull << 14);
558 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
559 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
561 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
566 /* wait for PCS to come out of reset */
567 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
568 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
572 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
573 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
574 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
575 SPU_BR_STATUS_BLK_LOCK, false)) {
576 dev_err(&bgx->pdev->dev,
577 "SPU_BR_STATUS_BLK_LOCK not completed\n");
581 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
582 SPU_BX_STATUS_RX_ALIGN, false)) {
583 dev_err(&bgx->pdev->dev,
584 "SPU_BX_STATUS_RX_ALIGN not completed\n");
589 /* Clear rcvflt bit (latching high) and read it back */
590 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
591 bgx_reg_modify(bgx, lmacid,
592 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
593 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
594 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
595 if (lmac->use_training) {
596 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
597 if (!(cfg & (1ull << 13))) {
598 cfg = (1ull << 13) | (1ull << 14);
599 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
600 cfg = bgx_reg_read(bgx, lmacid,
601 BGX_SPUX_BR_PMD_CRTL);
603 bgx_reg_write(bgx, lmacid,
604 BGX_SPUX_BR_PMD_CRTL, cfg);
611 /* Wait for BGX RX to be idle */
612 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
613 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
617 /* Wait for BGX TX to be idle */
618 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
619 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
623 /* Check for MAC RX faults */
624 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
625 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
626 cfg &= SMU_RX_CTL_STATUS;
630 /* Rx local/remote fault seen.
631 * Do lmac reinit to see if condition recovers
633 bgx_lmac_xaui_init(bgx, lmac);
638 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
640 u64 pcs_link, an_result;
643 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
644 BGX_GMP_PCS_MRX_STATUS);
646 /*Link state bit is sticky, read it again*/
647 if (!(pcs_link & PCS_MRX_STATUS_LINK))
648 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
649 BGX_GMP_PCS_MRX_STATUS);
651 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
652 PCS_MRX_STATUS_AN_CPT, false)) {
653 lmac->link_up = false;
654 lmac->last_speed = SPEED_UNKNOWN;
655 lmac->last_duplex = DUPLEX_UNKNOWN;
659 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
660 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
661 BGX_GMP_PCS_ANX_AN_RESULTS);
663 speed = (an_result >> 3) & 0x3;
664 lmac->last_duplex = (an_result >> 1) & 0x1;
667 lmac->last_speed = 10;
670 lmac->last_speed = 100;
673 lmac->last_speed = 1000;
676 lmac->link_up = false;
677 lmac->last_speed = SPEED_UNKNOWN;
678 lmac->last_duplex = DUPLEX_UNKNOWN;
684 if (lmac->last_link != lmac->link_up) {
686 bgx_sgmii_change_link_state(lmac);
687 lmac->last_link = lmac->link_up;
690 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
693 static void bgx_poll_for_link(struct work_struct *work)
696 u64 spu_link, smu_link;
698 lmac = container_of(work, struct lmac, dwork.work);
699 if (lmac->is_sgmii) {
700 bgx_poll_for_sgmii_link(lmac);
704 /* Receive link is latching low. Force it high and verify it */
705 bgx_reg_modify(lmac->bgx, lmac->lmacid,
706 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
707 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
708 SPU_STATUS1_RCV_LNK, false);
710 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
711 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
713 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
714 !(smu_link & SMU_RX_CTL_STATUS)) {
716 if (lmac->lmac_type == BGX_MODE_XLAUI)
717 lmac->last_speed = 40000;
719 lmac->last_speed = 10000;
720 lmac->last_duplex = 1;
723 lmac->last_speed = SPEED_UNKNOWN;
724 lmac->last_duplex = DUPLEX_UNKNOWN;
727 if (lmac->last_link != lmac->link_up) {
729 if (bgx_xaui_check_link(lmac)) {
730 /* Errors, clear link_up state */
732 lmac->last_speed = SPEED_UNKNOWN;
733 lmac->last_duplex = DUPLEX_UNKNOWN;
736 lmac->last_link = lmac->link_up;
739 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
742 static int phy_interface_mode(u8 lmac_type)
744 if (lmac_type == BGX_MODE_QSGMII)
745 return PHY_INTERFACE_MODE_QSGMII;
746 if (lmac_type == BGX_MODE_RGMII)
747 return PHY_INTERFACE_MODE_RGMII;
749 return PHY_INTERFACE_MODE_SGMII;
752 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
757 lmac = &bgx->lmac[lmacid];
760 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
761 (lmac->lmac_type == BGX_MODE_QSGMII) ||
762 (lmac->lmac_type == BGX_MODE_RGMII)) {
764 if (bgx_lmac_sgmii_init(bgx, lmac))
768 if (bgx_lmac_xaui_init(bgx, lmac))
772 if (lmac->is_sgmii) {
773 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
774 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
775 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
776 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
778 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
779 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
780 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
781 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
785 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
787 /* Restore default cfg, incase low level firmware changed it */
788 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
790 if ((lmac->lmac_type != BGX_MODE_XFI) &&
791 (lmac->lmac_type != BGX_MODE_XLAUI) &&
792 (lmac->lmac_type != BGX_MODE_40G_KR) &&
793 (lmac->lmac_type != BGX_MODE_10G_KR)) {
796 bgx_reg_write(bgx, lmacid,
797 BGX_GMP_PCS_LINKX_TIMER,
798 PCS_LINKX_TIMER_COUNT);
801 /* Default to below link speed and duplex */
802 lmac->link_up = true;
803 lmac->last_speed = 1000;
804 lmac->last_duplex = 1;
805 bgx_sgmii_change_link_state(lmac);
809 lmac->phydev->dev_flags = 0;
811 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
813 phy_interface_mode(lmac->lmac_type)))
816 phy_start_aneg(lmac->phydev);
821 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
823 if (!lmac->check_link)
825 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
826 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
831 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
836 lmac = &bgx->lmac[lmacid];
837 if (lmac->check_link) {
838 /* Destroy work queue */
839 cancel_delayed_work_sync(&lmac->dwork);
840 destroy_workqueue(lmac->check_link);
843 /* Disable packet reception */
844 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
845 cfg &= ~CMR_PKT_RX_EN;
846 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
848 /* Give chance for Rx/Tx FIFO to get drained */
849 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
850 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
852 /* Disable packet transmission */
853 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
854 cfg &= ~CMR_PKT_TX_EN;
855 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
857 /* Disable serdes lanes */
859 bgx_reg_modify(bgx, lmacid,
860 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
862 bgx_reg_modify(bgx, lmacid,
863 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
866 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
868 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
870 bgx_flush_dmac_addrs(bgx, lmacid);
872 if ((lmac->lmac_type != BGX_MODE_XFI) &&
873 (lmac->lmac_type != BGX_MODE_XLAUI) &&
874 (lmac->lmac_type != BGX_MODE_40G_KR) &&
875 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
876 phy_disconnect(lmac->phydev);
881 static void bgx_init_hw(struct bgx *bgx)
886 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
887 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
888 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
890 /* Set lmac type and lane2serdes mapping */
891 for (i = 0; i < bgx->lmac_count; i++) {
892 lmac = &bgx->lmac[i];
893 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
894 (lmac->lmac_type << 8) | lmac->lane_to_sds);
895 bgx->lmac[i].lmacid_bd = lmac_count;
899 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
900 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
902 /* Set the backpressure AND mask */
903 for (i = 0; i < bgx->lmac_count; i++)
904 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
905 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
906 (i * MAX_BGX_CHANS_PER_LMAC));
908 /* Disable all MAC filtering */
909 for (i = 0; i < RX_DMAC_COUNT; i++)
910 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
912 /* Disable MAC steering (NCSI traffic) */
913 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
914 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
917 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
919 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
922 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
924 struct device *dev = &bgx->pdev->dev;
929 if (lmacid > bgx->max_lmac)
932 lmac = &bgx->lmac[lmacid];
933 dlm = (lmacid / 2) + (bgx->bgx_id * 2);
935 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
937 sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
939 switch (lmac->lmac_type) {
941 dev_info(dev, "%s: SGMII\n", (char *)str);
944 dev_info(dev, "%s: XAUI\n", (char *)str);
947 dev_info(dev, "%s: RXAUI\n", (char *)str);
950 if (!lmac->use_training)
951 dev_info(dev, "%s: XFI\n", (char *)str);
953 dev_info(dev, "%s: 10G_KR\n", (char *)str);
956 if (!lmac->use_training)
957 dev_info(dev, "%s: XLAUI\n", (char *)str);
959 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
961 case BGX_MODE_QSGMII:
963 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
966 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
968 dev_info(dev, "%s: QSGMII\n", (char *)str);
971 dev_info(dev, "%s: RGMII\n", (char *)str);
973 case BGX_MODE_INVALID:
979 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
981 switch (lmac->lmac_type) {
984 lmac->lane_to_sds = lmac->lmacid;
989 lmac->lane_to_sds = 0xE4;
992 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
994 case BGX_MODE_QSGMII:
995 /* There is no way to determine if DLM0/2 is QSGMII or
996 * DLM1/3 is configured to QSGMII as bootloader will
997 * configure all LMACs, so take whatever is configured
998 * by low level firmware.
1000 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1003 lmac->lane_to_sds = 0;
1008 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1010 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1011 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1012 lmac->use_training = 0;
1016 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1017 SPU_PMD_CRTL_TRAIN_EN;
1020 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1028 lmac = &bgx->lmac[idx];
1030 if (!bgx->is_dlm || bgx->is_rgx) {
1031 /* Read LMAC0 type to figure out QLM mode
1032 * This is configured by low level firmware
1034 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1035 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1037 lmac->lmac_type = BGX_MODE_RGMII;
1038 lmac_set_training(bgx, lmac, 0);
1039 lmac_set_lane2sds(bgx, lmac);
1043 /* On 81xx BGX can be split across 2 DLMs
1044 * firmware programs lmac_type of LMAC0 and LMAC2
1046 if ((idx == 0) || (idx == 2)) {
1047 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1048 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1049 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1050 /* Check if config is not reset value */
1051 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1052 lmac->lmac_type = BGX_MODE_INVALID;
1054 lmac->lmac_type = lmac_type;
1055 lmac_set_training(bgx, lmac, lmac->lmacid);
1056 lmac_set_lane2sds(bgx, lmac);
1058 /* Set LMAC type of other lmac on same DLM i.e LMAC 1/3 */
1059 olmac = &bgx->lmac[idx + 1];
1060 olmac->lmac_type = lmac->lmac_type;
1061 lmac_set_training(bgx, olmac, olmac->lmacid);
1062 lmac_set_lane2sds(bgx, olmac);
1066 static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
1073 lmac = &bgx->lmac[0];
1074 if (lmac->lmac_type == BGX_MODE_INVALID)
1080 static void bgx_get_qlm_mode(struct bgx *bgx)
1083 struct lmac *lmac01;
1084 struct lmac *lmac23;
1087 /* Init all LMAC's type to invalid */
1088 for (idx = 0; idx < bgx->max_lmac; idx++) {
1089 lmac = &bgx->lmac[idx];
1091 lmac->lmac_type = BGX_MODE_INVALID;
1092 lmac->use_training = false;
1095 /* It is assumed that low level firmware sets this value */
1096 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1097 if (bgx->lmac_count > bgx->max_lmac)
1098 bgx->lmac_count = bgx->max_lmac;
1100 for (idx = 0; idx < bgx->max_lmac; idx++)
1101 bgx_set_lmac_config(bgx, idx);
1103 if (!bgx->is_dlm || bgx->is_rgx) {
1104 bgx_print_qlm_mode(bgx, 0);
1108 if (bgx->lmac_count) {
1109 bgx_print_qlm_mode(bgx, 0);
1110 bgx_print_qlm_mode(bgx, 2);
1113 /* If DLM0 is not in BGX mode then LMAC0/1 have
1114 * to be configured with serdes lanes of DLM1
1116 if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
1118 for (idx = 0; idx < bgx->lmac_count; idx++) {
1119 lmac01 = &bgx->lmac[idx];
1120 lmac23 = &bgx->lmac[idx + 2];
1121 lmac01->lmac_type = lmac23->lmac_type;
1122 lmac01->lane_to_sds = lmac23->lane_to_sds;
1128 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1134 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1135 "mac-address", mac, ETH_ALEN);
1139 if (!is_valid_ether_addr(mac)) {
1140 dev_err(dev, "MAC address invalid: %pM\n", mac);
1145 dev_info(dev, "MAC address set to: %pM\n", mac);
1147 memcpy(dst, mac, ETH_ALEN);
1152 /* Currently only sets the MAC address. */
1153 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1154 u32 lvl, void *context, void **rv)
1156 struct bgx *bgx = context;
1157 struct device *dev = &bgx->pdev->dev;
1158 struct acpi_device *adev;
1160 if (acpi_bus_get_device(handle, &adev))
1163 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1165 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1167 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1168 bgx->acpi_lmac_idx++; /* move to next LMAC */
1173 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1174 void *context, void **ret_val)
1176 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1177 struct bgx *bgx = context;
1180 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1181 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1182 pr_warn("Invalid link device\n");
1186 if (strncmp(string.pointer, bgx_sel, 4))
1189 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1190 bgx_acpi_register_phy, NULL, bgx, NULL);
1192 kfree(string.pointer);
1193 return AE_CTRL_TERMINATE;
1196 static int bgx_init_acpi_phy(struct bgx *bgx)
1198 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1204 static int bgx_init_acpi_phy(struct bgx *bgx)
1209 #endif /* CONFIG_ACPI */
1211 #if IS_ENABLED(CONFIG_OF_MDIO)
1213 static int bgx_init_of_phy(struct bgx *bgx)
1215 struct fwnode_handle *fwn;
1216 struct device_node *node = NULL;
1219 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1220 struct phy_device *pd;
1221 struct device_node *phy_np;
1224 /* Should always be an OF node. But if it is not, we
1225 * cannot handle it, so exit the loop.
1227 node = to_of_node(fwn);
1231 mac = of_get_mac_address(node);
1233 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1235 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1236 bgx->lmac[lmac].lmacid = lmac;
1238 phy_np = of_parse_phandle(node, "phy-handle", 0);
1239 /* If there is no phy or defective firmware presents
1240 * this cortina phy, for which there is no driver
1241 * support, ignore it.
1244 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1245 /* Wait until the phy drivers are available */
1246 pd = of_phy_find_device(phy_np);
1249 bgx->lmac[lmac].phydev = pd;
1253 if (lmac == bgx->max_lmac) {
1261 /* We are bailing out, try not to leak device reference counts
1262 * for phy devices we may have already found.
1265 if (bgx->lmac[lmac].phydev) {
1266 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1267 bgx->lmac[lmac].phydev = NULL;
1272 return -EPROBE_DEFER;
1277 static int bgx_init_of_phy(struct bgx *bgx)
1282 #endif /* CONFIG_OF_MDIO */
1284 static int bgx_init_phy(struct bgx *bgx)
1287 return bgx_init_acpi_phy(bgx);
1289 return bgx_init_of_phy(bgx);
1292 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1295 struct device *dev = &pdev->dev;
1296 struct bgx *bgx = NULL;
1300 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1305 pci_set_drvdata(pdev, bgx);
1307 err = pci_enable_device(pdev);
1309 dev_err(dev, "Failed to enable PCI device\n");
1310 pci_set_drvdata(pdev, NULL);
1314 err = pci_request_regions(pdev, DRV_NAME);
1316 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1317 goto err_disable_device;
1320 /* MAP configuration registers */
1321 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1322 if (!bgx->reg_base) {
1323 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1325 goto err_release_regions;
1328 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1329 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1330 bgx->bgx_id = (pci_resource_start(pdev,
1331 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1332 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
1333 bgx->max_lmac = MAX_LMAC_PER_BGX;
1334 bgx_vnic[bgx->bgx_id] = bgx;
1338 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1339 bgx_vnic[bgx->bgx_id] = bgx;
1343 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1344 * BGX i.e BGX2 can be split across 2 DLMs.
1346 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1347 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1348 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1351 bgx_get_qlm_mode(bgx);
1353 err = bgx_init_phy(bgx);
1359 /* Enable all LMACs */
1360 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1361 err = bgx_lmac_enable(bgx, lmac);
1363 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1366 bgx_lmac_disable(bgx, --lmac);
1374 bgx_vnic[bgx->bgx_id] = NULL;
1375 err_release_regions:
1376 pci_release_regions(pdev);
1378 pci_disable_device(pdev);
1379 pci_set_drvdata(pdev, NULL);
1383 static void bgx_remove(struct pci_dev *pdev)
1385 struct bgx *bgx = pci_get_drvdata(pdev);
1388 /* Disable all LMACs */
1389 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1390 bgx_lmac_disable(bgx, lmac);
1392 bgx_vnic[bgx->bgx_id] = NULL;
1393 pci_release_regions(pdev);
1394 pci_disable_device(pdev);
1395 pci_set_drvdata(pdev, NULL);
1398 static struct pci_driver bgx_driver = {
1400 .id_table = bgx_id_table,
1402 .remove = bgx_remove,
1405 static int __init bgx_init_module(void)
1407 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1409 return pci_register_driver(&bgx_driver);
1412 static void __exit bgx_cleanup_module(void)
1414 pci_unregister_driver(&bgx_driver);
1417 module_init(bgx_init_module);
1418 module_exit(bgx_cleanup_module);