2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
36 int lmacid; /* ID within BGX */
37 int lmacid_bd; /* ID on board */
38 struct net_device netdev;
39 struct phy_device *phydev;
40 unsigned int last_duplex;
41 unsigned int last_link;
42 unsigned int last_speed;
44 struct delayed_work dwork;
45 struct workqueue_struct *check_link;
50 struct lmac lmac[MAX_LMAC_PER_BGX];
54 void __iomem *reg_base;
60 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
61 static int lmac_count; /* Total no of LMACs in system */
63 static int bgx_xaui_check_link(struct lmac *lmac);
65 /* Supported devices */
66 static const struct pci_device_id bgx_id_table[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
69 { 0, } /* end of table */
72 MODULE_AUTHOR("Cavium Inc");
73 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
74 MODULE_LICENSE("GPL v2");
75 MODULE_VERSION(DRV_VERSION);
76 MODULE_DEVICE_TABLE(pci, bgx_id_table);
78 /* The Cavium ThunderX network controller can *only* be found in SoCs
79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
80 * registers on this platform are implicitly strongly ordered with respect
81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
82 * with no memory barriers in this driver. The readq()/writeq() functions add
83 * explicit ordering operation which in this case are redundant, and only
87 /* Register read/write APIs */
88 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
90 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
92 return readq_relaxed(addr);
95 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
97 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
99 writeq_relaxed(val, addr);
102 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
104 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
106 writeq_relaxed(val | readq_relaxed(addr), addr);
109 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
115 reg_val = bgx_reg_read(bgx, lmac, reg);
116 if (zero && !(reg_val & mask))
118 if (!zero && (reg_val & mask))
120 usleep_range(1000, 2000);
126 static int max_bgx_per_node;
127 static void set_max_bgx_per_node(struct pci_dev *pdev)
131 if (max_bgx_per_node)
134 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
136 case PCI_SUBSYS_DEVID_81XX_BGX:
137 case PCI_SUBSYS_DEVID_81XX_RGX:
138 max_bgx_per_node = MAX_BGX_PER_CN81XX;
140 case PCI_SUBSYS_DEVID_83XX_BGX:
141 max_bgx_per_node = MAX_BGX_PER_CN83XX;
143 case PCI_SUBSYS_DEVID_88XX_BGX:
145 max_bgx_per_node = MAX_BGX_PER_CN88XX;
150 static struct bgx *get_bgx(int node, int bgx_idx)
152 int idx = (node * max_bgx_per_node) + bgx_idx;
154 return bgx_vnic[idx];
157 /* Return number of BGX present in HW */
158 unsigned bgx_get_map(int node)
163 for (i = 0; i < max_bgx_per_node; i++) {
164 if (bgx_vnic[(node * max_bgx_per_node) + i])
170 EXPORT_SYMBOL(bgx_get_map);
172 /* Return number of LMAC configured for this BGX */
173 int bgx_get_lmac_count(int node, int bgx_idx)
177 bgx = get_bgx(node, bgx_idx);
179 return bgx->lmac_count;
183 EXPORT_SYMBOL(bgx_get_lmac_count);
185 /* Returns the current link status of LMAC */
186 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
188 struct bgx_link_status *link = (struct bgx_link_status *)status;
192 bgx = get_bgx(node, bgx_idx);
196 lmac = &bgx->lmac[lmacid];
197 link->mac_type = lmac->lmac_type;
198 link->link_up = lmac->link_up;
199 link->duplex = lmac->last_duplex;
200 link->speed = lmac->last_speed;
202 EXPORT_SYMBOL(bgx_get_lmac_link_state);
204 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
206 struct bgx *bgx = get_bgx(node, bgx_idx);
209 return bgx->lmac[lmacid].mac;
213 EXPORT_SYMBOL(bgx_get_lmac_mac);
215 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
217 struct bgx *bgx = get_bgx(node, bgx_idx);
222 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
224 EXPORT_SYMBOL(bgx_set_lmac_mac);
226 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
228 struct bgx *bgx = get_bgx(node, bgx_idx);
234 lmac = &bgx->lmac[lmacid];
236 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
238 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
240 /* enable TX FIFO Underflow interrupt */
241 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1S,
244 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
246 /* Disable TX FIFO Underflow interrupt */
247 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1C,
250 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
253 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
255 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
257 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
259 struct pfc *pfc = (struct pfc *)pause;
260 struct bgx *bgx = get_bgx(node, bgx_idx);
266 lmac = &bgx->lmac[lmacid];
270 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
271 pfc->fc_rx = cfg & RX_EN;
272 pfc->fc_tx = cfg & TX_EN;
275 EXPORT_SYMBOL(bgx_lmac_get_pfc);
277 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
279 struct pfc *pfc = (struct pfc *)pause;
280 struct bgx *bgx = get_bgx(node, bgx_idx);
286 lmac = &bgx->lmac[lmacid];
290 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
291 cfg &= ~(RX_EN | TX_EN);
292 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
293 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
294 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
296 EXPORT_SYMBOL(bgx_lmac_set_pfc);
298 static void bgx_sgmii_change_link_state(struct lmac *lmac)
300 struct bgx *bgx = lmac->bgx;
306 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
307 tx_en = cmr_cfg & CMR_PKT_TX_EN;
308 rx_en = cmr_cfg & CMR_PKT_RX_EN;
309 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
310 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
312 /* Wait for BGX RX to be idle */
313 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
314 GMI_PORT_CFG_RX_IDLE, false)) {
315 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
316 bgx->bgx_id, lmac->lmacid);
320 /* Wait for BGX TX to be idle */
321 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
322 GMI_PORT_CFG_TX_IDLE, false)) {
323 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
324 bgx->bgx_id, lmac->lmacid);
328 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
329 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
332 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
333 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
334 port_cfg |= (lmac->last_duplex << 2);
336 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
339 switch (lmac->last_speed) {
341 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
342 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
343 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
344 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
345 misc_ctl |= 50; /* samp_pt */
346 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
347 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
350 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
351 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
352 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
353 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
354 misc_ctl |= 5; /* samp_pt */
355 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
356 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
359 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
360 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
361 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
362 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
363 misc_ctl |= 1; /* samp_pt */
364 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
365 if (lmac->last_duplex)
366 bgx_reg_write(bgx, lmac->lmacid,
367 BGX_GMP_GMI_TXX_BURST, 0);
369 bgx_reg_write(bgx, lmac->lmacid,
370 BGX_GMP_GMI_TXX_BURST, 8192);
375 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
376 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
378 /* Restore CMR config settings */
379 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
380 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
382 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
383 xcv_setup_link(lmac->link_up, lmac->last_speed);
386 static void bgx_lmac_handler(struct net_device *netdev)
388 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
389 struct phy_device *phydev;
390 int link_changed = 0;
395 phydev = lmac->phydev;
397 if (!phydev->link && lmac->last_link)
401 (lmac->last_duplex != phydev->duplex ||
402 lmac->last_link != phydev->link ||
403 lmac->last_speed != phydev->speed)) {
407 lmac->last_link = phydev->link;
408 lmac->last_speed = phydev->speed;
409 lmac->last_duplex = phydev->duplex;
414 if (link_changed > 0)
415 lmac->link_up = true;
417 lmac->link_up = false;
420 bgx_sgmii_change_link_state(lmac);
422 bgx_xaui_check_link(lmac);
425 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
429 bgx = get_bgx(node, bgx_idx);
435 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
437 EXPORT_SYMBOL(bgx_get_rx_stats);
439 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
443 bgx = get_bgx(node, bgx_idx);
447 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
449 EXPORT_SYMBOL(bgx_get_tx_stats);
451 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
455 while (bgx->lmac[lmac].dmac > 0) {
456 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
457 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
458 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
459 bgx->lmac[lmac].dmac--;
463 /* Configure BGX LMAC in internal loopback mode */
464 void bgx_lmac_internal_loopback(int node, int bgx_idx,
465 int lmac_idx, bool enable)
471 bgx = get_bgx(node, bgx_idx);
475 lmac = &bgx->lmac[lmac_idx];
476 if (lmac->is_sgmii) {
477 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
479 cfg |= PCS_MRX_CTL_LOOPBACK1;
481 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
482 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
484 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
486 cfg |= SPU_CTL_LOOPBACK;
488 cfg &= ~SPU_CTL_LOOPBACK;
489 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
492 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
494 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
496 int lmacid = lmac->lmacid;
499 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
500 /* max packet size */
501 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
503 /* Disable frame alignment if using preamble */
504 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
506 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
509 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
512 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
513 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
514 PCS_MRX_CTL_RESET, true)) {
515 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
519 /* power down, reset autoneg, autoneg enable */
520 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
521 cfg &= ~PCS_MRX_CTL_PWR_DN;
522 cfg |= PCS_MRX_CTL_RST_AN;
524 cfg |= PCS_MRX_CTL_AN_EN;
526 /* In scenarios where PHY driver is not present or it's a
527 * non-standard PHY, FW sets AN_EN to inform Linux driver
528 * to do auto-neg and link polling or not.
530 if (cfg & PCS_MRX_CTL_AN_EN)
531 lmac->autoneg = true;
533 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
535 if (lmac->lmac_type == BGX_MODE_QSGMII) {
536 /* Disable disparity check for QSGMII */
537 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
538 cfg &= ~PCS_MISC_CTL_DISP_EN;
539 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
543 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
544 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
545 PCS_MRX_STATUS_AN_CPT, false)) {
546 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
554 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
557 int lmacid = lmac->lmacid;
560 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
561 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
562 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
567 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
569 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
571 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
572 /* Set interleaved running disparity for RXAUI */
573 if (lmac->lmac_type == BGX_MODE_RXAUI)
574 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
575 SPU_MISC_CTL_INTLV_RDISP);
577 /* Clear receive packet disable */
578 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
579 cfg &= ~SPU_MISC_CTL_RX_DIS;
580 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
582 /* clear all interrupts */
583 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
584 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
585 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
586 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
587 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
588 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
590 if (lmac->use_training) {
591 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
592 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
593 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
594 /* training enable */
595 bgx_reg_modify(bgx, lmacid,
596 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
599 /* Append FCS to each packet */
600 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
602 /* Disable forward error correction */
603 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
604 cfg &= ~SPU_FEC_CTL_FEC_EN;
605 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
607 /* Disable autoneg */
608 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
609 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
610 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
612 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
613 if (lmac->lmac_type == BGX_MODE_10G_KR)
615 else if (lmac->lmac_type == BGX_MODE_40G_KR)
618 cfg &= ~((1 << 23) | (1 << 24));
619 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
620 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
622 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
623 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
624 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
627 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
629 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
630 cfg &= ~SPU_CTL_LOW_POWER;
631 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
633 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
634 cfg &= ~SMU_TX_CTL_UNI_EN;
635 cfg |= SMU_TX_CTL_DIC_EN;
636 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
638 /* Enable receive and transmission of pause frames */
639 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
640 BCK_EN | DRP_EN | TX_EN | RX_EN));
641 /* Configure pause time and interval */
642 bgx_reg_write(bgx, lmacid,
643 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
644 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
646 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
647 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
648 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
650 /* take lmac_count into account */
651 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
652 /* max packet size */
653 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
658 static int bgx_xaui_check_link(struct lmac *lmac)
660 struct bgx *bgx = lmac->bgx;
661 int lmacid = lmac->lmacid;
662 int lmac_type = lmac->lmac_type;
665 if (lmac->use_training) {
666 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
667 if (!(cfg & (1ull << 13))) {
668 cfg = (1ull << 13) | (1ull << 14);
669 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
670 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
672 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
677 /* wait for PCS to come out of reset */
678 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
679 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
683 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
684 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
685 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
686 SPU_BR_STATUS_BLK_LOCK, false)) {
687 dev_err(&bgx->pdev->dev,
688 "SPU_BR_STATUS_BLK_LOCK not completed\n");
692 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
693 SPU_BX_STATUS_RX_ALIGN, false)) {
694 dev_err(&bgx->pdev->dev,
695 "SPU_BX_STATUS_RX_ALIGN not completed\n");
700 /* Clear rcvflt bit (latching high) and read it back */
701 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
702 bgx_reg_modify(bgx, lmacid,
703 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
704 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
705 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
706 if (lmac->use_training) {
707 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
708 if (!(cfg & (1ull << 13))) {
709 cfg = (1ull << 13) | (1ull << 14);
710 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
711 cfg = bgx_reg_read(bgx, lmacid,
712 BGX_SPUX_BR_PMD_CRTL);
714 bgx_reg_write(bgx, lmacid,
715 BGX_SPUX_BR_PMD_CRTL, cfg);
722 /* Wait for BGX RX to be idle */
723 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
724 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
728 /* Wait for BGX TX to be idle */
729 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
730 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
734 /* Check for MAC RX faults */
735 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
736 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
737 cfg &= SMU_RX_CTL_STATUS;
741 /* Rx local/remote fault seen.
742 * Do lmac reinit to see if condition recovers
744 bgx_lmac_xaui_init(bgx, lmac);
749 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
751 u64 pcs_link, an_result;
754 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
755 BGX_GMP_PCS_MRX_STATUS);
757 /*Link state bit is sticky, read it again*/
758 if (!(pcs_link & PCS_MRX_STATUS_LINK))
759 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
760 BGX_GMP_PCS_MRX_STATUS);
762 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
763 PCS_MRX_STATUS_AN_CPT, false)) {
764 lmac->link_up = false;
765 lmac->last_speed = SPEED_UNKNOWN;
766 lmac->last_duplex = DUPLEX_UNKNOWN;
770 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
771 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
772 BGX_GMP_PCS_ANX_AN_RESULTS);
774 speed = (an_result >> 3) & 0x3;
775 lmac->last_duplex = (an_result >> 1) & 0x1;
778 lmac->last_speed = 10;
781 lmac->last_speed = 100;
784 lmac->last_speed = 1000;
787 lmac->link_up = false;
788 lmac->last_speed = SPEED_UNKNOWN;
789 lmac->last_duplex = DUPLEX_UNKNOWN;
795 if (lmac->last_link != lmac->link_up) {
797 bgx_sgmii_change_link_state(lmac);
798 lmac->last_link = lmac->link_up;
801 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
804 static void bgx_poll_for_link(struct work_struct *work)
807 u64 spu_link, smu_link;
809 lmac = container_of(work, struct lmac, dwork.work);
810 if (lmac->is_sgmii) {
811 bgx_poll_for_sgmii_link(lmac);
815 /* Receive link is latching low. Force it high and verify it */
816 bgx_reg_modify(lmac->bgx, lmac->lmacid,
817 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
818 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
819 SPU_STATUS1_RCV_LNK, false);
821 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
822 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
824 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
825 !(smu_link & SMU_RX_CTL_STATUS)) {
827 if (lmac->lmac_type == BGX_MODE_XLAUI)
828 lmac->last_speed = 40000;
830 lmac->last_speed = 10000;
831 lmac->last_duplex = 1;
834 lmac->last_speed = SPEED_UNKNOWN;
835 lmac->last_duplex = DUPLEX_UNKNOWN;
838 if (lmac->last_link != lmac->link_up) {
840 if (bgx_xaui_check_link(lmac)) {
841 /* Errors, clear link_up state */
843 lmac->last_speed = SPEED_UNKNOWN;
844 lmac->last_duplex = DUPLEX_UNKNOWN;
847 lmac->last_link = lmac->link_up;
850 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
853 static int phy_interface_mode(u8 lmac_type)
855 if (lmac_type == BGX_MODE_QSGMII)
856 return PHY_INTERFACE_MODE_QSGMII;
857 if (lmac_type == BGX_MODE_RGMII)
858 return PHY_INTERFACE_MODE_RGMII;
860 return PHY_INTERFACE_MODE_SGMII;
863 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
868 lmac = &bgx->lmac[lmacid];
871 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
872 (lmac->lmac_type == BGX_MODE_QSGMII) ||
873 (lmac->lmac_type == BGX_MODE_RGMII)) {
875 if (bgx_lmac_sgmii_init(bgx, lmac))
879 if (bgx_lmac_xaui_init(bgx, lmac))
883 if (lmac->is_sgmii) {
884 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
885 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
886 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
887 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
889 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
890 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
891 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
892 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
896 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
898 /* Restore default cfg, incase low level firmware changed it */
899 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
901 if ((lmac->lmac_type != BGX_MODE_XFI) &&
902 (lmac->lmac_type != BGX_MODE_XLAUI) &&
903 (lmac->lmac_type != BGX_MODE_40G_KR) &&
904 (lmac->lmac_type != BGX_MODE_10G_KR)) {
907 bgx_reg_write(bgx, lmacid,
908 BGX_GMP_PCS_LINKX_TIMER,
909 PCS_LINKX_TIMER_COUNT);
912 /* Default to below link speed and duplex */
913 lmac->link_up = true;
914 lmac->last_speed = 1000;
915 lmac->last_duplex = 1;
916 bgx_sgmii_change_link_state(lmac);
920 lmac->phydev->dev_flags = 0;
922 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
924 phy_interface_mode(lmac->lmac_type)))
927 phy_start(lmac->phydev);
932 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
934 if (!lmac->check_link)
936 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
937 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
942 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
947 lmac = &bgx->lmac[lmacid];
948 if (lmac->check_link) {
949 /* Destroy work queue */
950 cancel_delayed_work_sync(&lmac->dwork);
951 destroy_workqueue(lmac->check_link);
954 /* Disable packet reception */
955 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
956 cfg &= ~CMR_PKT_RX_EN;
957 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
959 /* Give chance for Rx/Tx FIFO to get drained */
960 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
961 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
963 /* Disable packet transmission */
964 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
965 cfg &= ~CMR_PKT_TX_EN;
966 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
968 /* Disable serdes lanes */
970 bgx_reg_modify(bgx, lmacid,
971 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
973 bgx_reg_modify(bgx, lmacid,
974 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
977 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
979 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
981 bgx_flush_dmac_addrs(bgx, lmacid);
983 if ((lmac->lmac_type != BGX_MODE_XFI) &&
984 (lmac->lmac_type != BGX_MODE_XLAUI) &&
985 (lmac->lmac_type != BGX_MODE_40G_KR) &&
986 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
987 phy_disconnect(lmac->phydev);
992 static void bgx_init_hw(struct bgx *bgx)
997 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
998 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
999 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
1001 /* Set lmac type and lane2serdes mapping */
1002 for (i = 0; i < bgx->lmac_count; i++) {
1003 lmac = &bgx->lmac[i];
1004 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
1005 (lmac->lmac_type << 8) | lmac->lane_to_sds);
1006 bgx->lmac[i].lmacid_bd = lmac_count;
1010 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1011 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1013 /* Set the backpressure AND mask */
1014 for (i = 0; i < bgx->lmac_count; i++)
1015 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1016 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1017 (i * MAX_BGX_CHANS_PER_LMAC));
1019 /* Disable all MAC filtering */
1020 for (i = 0; i < RX_DMAC_COUNT; i++)
1021 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1023 /* Disable MAC steering (NCSI traffic) */
1024 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
1025 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
1028 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1030 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1033 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
1035 struct device *dev = &bgx->pdev->dev;
1039 if (!bgx->is_dlm && lmacid)
1042 lmac = &bgx->lmac[lmacid];
1044 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1046 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
1048 switch (lmac->lmac_type) {
1049 case BGX_MODE_SGMII:
1050 dev_info(dev, "%s: SGMII\n", (char *)str);
1053 dev_info(dev, "%s: XAUI\n", (char *)str);
1055 case BGX_MODE_RXAUI:
1056 dev_info(dev, "%s: RXAUI\n", (char *)str);
1059 if (!lmac->use_training)
1060 dev_info(dev, "%s: XFI\n", (char *)str);
1062 dev_info(dev, "%s: 10G_KR\n", (char *)str);
1064 case BGX_MODE_XLAUI:
1065 if (!lmac->use_training)
1066 dev_info(dev, "%s: XLAUI\n", (char *)str);
1068 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
1070 case BGX_MODE_QSGMII:
1071 dev_info(dev, "%s: QSGMII\n", (char *)str);
1073 case BGX_MODE_RGMII:
1074 dev_info(dev, "%s: RGMII\n", (char *)str);
1076 case BGX_MODE_INVALID:
1082 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
1084 switch (lmac->lmac_type) {
1085 case BGX_MODE_SGMII:
1087 lmac->lane_to_sds = lmac->lmacid;
1090 case BGX_MODE_XLAUI:
1091 case BGX_MODE_RGMII:
1092 lmac->lane_to_sds = 0xE4;
1094 case BGX_MODE_RXAUI:
1095 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1097 case BGX_MODE_QSGMII:
1098 /* There is no way to determine if DLM0/2 is QSGMII or
1099 * DLM1/3 is configured to QSGMII as bootloader will
1100 * configure all LMACs, so take whatever is configured
1101 * by low level firmware.
1103 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1106 lmac->lane_to_sds = 0;
1111 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1113 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1114 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1115 lmac->use_training = 0;
1119 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1120 SPU_PMD_CRTL_TRAIN_EN;
1123 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1130 lmac = &bgx->lmac[idx];
1132 if (!bgx->is_dlm || bgx->is_rgx) {
1133 /* Read LMAC0 type to figure out QLM mode
1134 * This is configured by low level firmware
1136 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1137 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1139 lmac->lmac_type = BGX_MODE_RGMII;
1140 lmac_set_training(bgx, lmac, 0);
1141 lmac_set_lane2sds(bgx, lmac);
1145 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1146 * are possible and vary across boards. Also Kernel doesn't have
1147 * any way to identify board type/info and since firmware does,
1148 * just take lmac type and serdes lane config as is.
1150 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1151 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1152 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1153 /* Check if config is reset value */
1154 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1155 lmac->lmac_type = BGX_MODE_INVALID;
1157 lmac->lmac_type = lmac_type;
1158 lmac->lane_to_sds = lane_to_sds;
1159 lmac_set_training(bgx, lmac, lmac->lmacid);
1162 static void bgx_get_qlm_mode(struct bgx *bgx)
1167 /* Init all LMAC's type to invalid */
1168 for (idx = 0; idx < bgx->max_lmac; idx++) {
1169 lmac = &bgx->lmac[idx];
1171 lmac->lmac_type = BGX_MODE_INVALID;
1172 lmac->use_training = false;
1175 /* It is assumed that low level firmware sets this value */
1176 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1177 if (bgx->lmac_count > bgx->max_lmac)
1178 bgx->lmac_count = bgx->max_lmac;
1180 for (idx = 0; idx < bgx->lmac_count; idx++) {
1181 bgx_set_lmac_config(bgx, idx);
1182 bgx_print_qlm_mode(bgx, idx);
1188 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1194 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1195 "mac-address", mac, ETH_ALEN);
1199 if (!is_valid_ether_addr(mac)) {
1200 dev_err(dev, "MAC address invalid: %pM\n", mac);
1205 dev_info(dev, "MAC address set to: %pM\n", mac);
1207 memcpy(dst, mac, ETH_ALEN);
1212 /* Currently only sets the MAC address. */
1213 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1214 u32 lvl, void *context, void **rv)
1216 struct bgx *bgx = context;
1217 struct device *dev = &bgx->pdev->dev;
1218 struct acpi_device *adev;
1220 if (acpi_bus_get_device(handle, &adev))
1223 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1225 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1227 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1228 bgx->acpi_lmac_idx++; /* move to next LMAC */
1233 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1234 void *context, void **ret_val)
1236 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1237 struct bgx *bgx = context;
1240 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1241 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1242 pr_warn("Invalid link device\n");
1246 if (strncmp(string.pointer, bgx_sel, 4)) {
1247 kfree(string.pointer);
1251 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1252 bgx_acpi_register_phy, NULL, bgx, NULL);
1254 kfree(string.pointer);
1255 return AE_CTRL_TERMINATE;
1258 static int bgx_init_acpi_phy(struct bgx *bgx)
1260 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1266 static int bgx_init_acpi_phy(struct bgx *bgx)
1271 #endif /* CONFIG_ACPI */
1273 #if IS_ENABLED(CONFIG_OF_MDIO)
1275 static int bgx_init_of_phy(struct bgx *bgx)
1277 struct fwnode_handle *fwn;
1278 struct device_node *node = NULL;
1281 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1282 struct phy_device *pd;
1283 struct device_node *phy_np;
1286 /* Should always be an OF node. But if it is not, we
1287 * cannot handle it, so exit the loop.
1289 node = to_of_node(fwn);
1293 mac = of_get_mac_address(node);
1295 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1297 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1298 bgx->lmac[lmac].lmacid = lmac;
1300 phy_np = of_parse_phandle(node, "phy-handle", 0);
1301 /* If there is no phy or defective firmware presents
1302 * this cortina phy, for which there is no driver
1303 * support, ignore it.
1306 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1307 /* Wait until the phy drivers are available */
1308 pd = of_phy_find_device(phy_np);
1311 bgx->lmac[lmac].phydev = pd;
1315 if (lmac == bgx->max_lmac) {
1323 /* We are bailing out, try not to leak device reference counts
1324 * for phy devices we may have already found.
1327 if (bgx->lmac[lmac].phydev) {
1328 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1329 bgx->lmac[lmac].phydev = NULL;
1334 return -EPROBE_DEFER;
1339 static int bgx_init_of_phy(struct bgx *bgx)
1344 #endif /* CONFIG_OF_MDIO */
1346 static int bgx_init_phy(struct bgx *bgx)
1349 return bgx_init_acpi_phy(bgx);
1351 return bgx_init_of_phy(bgx);
1354 static irqreturn_t bgx_intr_handler(int irq, void *data)
1356 struct bgx *bgx = (struct bgx *)data;
1360 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1361 status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
1362 if (status & GMI_TXX_INT_UNDFLW) {
1363 pci_err(bgx->pdev, "BGX%d lmac%d UNDFLW\n",
1365 val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
1367 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1369 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1371 /* clear interrupts */
1372 bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
1378 static void bgx_register_intr(struct pci_dev *pdev)
1380 struct bgx *bgx = pci_get_drvdata(pdev);
1383 ret = pci_alloc_irq_vectors(pdev, BGX_LMAC_VEC_OFFSET,
1384 BGX_LMAC_VEC_OFFSET, PCI_IRQ_ALL_TYPES);
1386 pci_err(pdev, "Req for #%d msix vectors failed\n",
1387 BGX_LMAC_VEC_OFFSET);
1390 ret = pci_request_irq(pdev, GMPX_GMI_TX_INT, bgx_intr_handler, NULL,
1391 bgx, "BGX%d", bgx->bgx_id);
1393 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1396 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1399 struct device *dev = &pdev->dev;
1400 struct bgx *bgx = NULL;
1404 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1409 pci_set_drvdata(pdev, bgx);
1411 err = pcim_enable_device(pdev);
1413 dev_err(dev, "Failed to enable PCI device\n");
1414 pci_set_drvdata(pdev, NULL);
1418 err = pci_request_regions(pdev, DRV_NAME);
1420 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1421 goto err_disable_device;
1424 /* MAP configuration registers */
1425 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1426 if (!bgx->reg_base) {
1427 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1429 goto err_release_regions;
1432 set_max_bgx_per_node(pdev);
1434 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1435 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1436 bgx->bgx_id = (pci_resource_start(pdev,
1437 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1438 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
1439 bgx->max_lmac = MAX_LMAC_PER_BGX;
1440 bgx_vnic[bgx->bgx_id] = bgx;
1444 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1445 bgx_vnic[bgx->bgx_id] = bgx;
1449 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1450 * BGX i.e BGX2 can be split across 2 DLMs.
1452 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1453 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1454 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1457 bgx_get_qlm_mode(bgx);
1459 err = bgx_init_phy(bgx);
1465 bgx_register_intr(pdev);
1467 /* Enable all LMACs */
1468 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1469 err = bgx_lmac_enable(bgx, lmac);
1471 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1474 bgx_lmac_disable(bgx, --lmac);
1482 bgx_vnic[bgx->bgx_id] = NULL;
1483 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1484 err_release_regions:
1485 pci_release_regions(pdev);
1487 pci_disable_device(pdev);
1488 pci_set_drvdata(pdev, NULL);
1492 static void bgx_remove(struct pci_dev *pdev)
1494 struct bgx *bgx = pci_get_drvdata(pdev);
1497 /* Disable all LMACs */
1498 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1499 bgx_lmac_disable(bgx, lmac);
1501 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1503 bgx_vnic[bgx->bgx_id] = NULL;
1504 pci_release_regions(pdev);
1505 pci_disable_device(pdev);
1506 pci_set_drvdata(pdev, NULL);
1509 static struct pci_driver bgx_driver = {
1511 .id_table = bgx_id_table,
1513 .remove = bgx_remove,
1516 static int __init bgx_init_module(void)
1518 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1520 return pci_register_driver(&bgx_driver);
1523 static void __exit bgx_cleanup_module(void)
1525 pci_unregister_driver(&bgx_driver);
1528 module_init(bgx_init_module);
1529 module_exit(bgx_cleanup_module);