drivers/net/ethernet/cavium/thunder/q_struct.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * This file contains HW queue descriptor formats, config register
   4  * structures etc
   5  *
   6  * Copyright (C) 2015 Cavium, Inc.
   7  */
   8
   9 #ifndef Q_STRUCT_H
  10 #define Q_STRUCT_H
  11
  12 /* Load transaction types for reading segment bytes specified by
  13  * NIC_SEND_GATHER_S[LD_TYPE].
  14  */
  15 enum nic_send_ld_type_e {
  16         NIC_SEND_LD_TYPE_E_LDD = 0x0,
  17         NIC_SEND_LD_TYPE_E_LDT = 0x1,
  18         NIC_SEND_LD_TYPE_E_LDWB = 0x2,
  19         NIC_SEND_LD_TYPE_E_ENUM_LAST = 0x3,
  20 };
  21
  22 enum ether_type_algorithm {
  23         ETYPE_ALG_NONE = 0x0,
  24         ETYPE_ALG_SKIP = 0x1,
  25         ETYPE_ALG_ENDPARSE = 0x2,
  26         ETYPE_ALG_VLAN = 0x3,
  27         ETYPE_ALG_VLAN_STRIP = 0x4,
  28 };
  29
  30 enum layer3_type {
  31         L3TYPE_NONE = 0x00,
  32         L3TYPE_GRH = 0x01,
  33         L3TYPE_IPV4 = 0x04,
  34         L3TYPE_IPV4_OPTIONS = 0x05,
  35         L3TYPE_IPV6 = 0x06,
  36         L3TYPE_IPV6_OPTIONS = 0x07,
  37         L3TYPE_ET_STOP = 0x0D,
  38         L3TYPE_OTHER = 0x0E,
  39 };
  40
  41 enum layer4_type {
  42         L4TYPE_NONE = 0x00,
  43         L4TYPE_IPSEC_ESP = 0x01,
  44         L4TYPE_IPFRAG = 0x02,
  45         L4TYPE_IPCOMP = 0x03,
  46         L4TYPE_TCP = 0x04,
  47         L4TYPE_UDP = 0x05,
  48         L4TYPE_SCTP = 0x06,
  49         L4TYPE_GRE = 0x07,
  50         L4TYPE_ROCE_BTH = 0x08,
  51         L4TYPE_OTHER = 0x0E,
  52 };
  53
  54 /* CPI and RSSI configuration */
  55 enum cpi_algorithm_type {
  56         CPI_ALG_NONE = 0x0,
  57         CPI_ALG_VLAN = 0x1,
  58         CPI_ALG_VLAN16 = 0x2,
  59         CPI_ALG_DIFF = 0x3,
  60 };
  61
  62 enum rss_algorithm_type {
  63         RSS_ALG_NONE = 0x00,
  64         RSS_ALG_PORT = 0x01,
  65         RSS_ALG_IP = 0x02,
  66         RSS_ALG_TCP_IP = 0x03,
  67         RSS_ALG_UDP_IP = 0x04,
  68         RSS_ALG_SCTP_IP = 0x05,
  69         RSS_ALG_GRE_IP = 0x06,
  70         RSS_ALG_ROCE = 0x07,
  71 };
  72
  73 enum rss_hash_cfg {
  74         RSS_HASH_L2ETC = 0x00,
  75         RSS_HASH_IP = 0x01,
  76         RSS_HASH_TCP = 0x02,
  77         RSS_HASH_TCP_SYN_DIS = 0x03,
  78         RSS_HASH_UDP = 0x04,
  79         RSS_HASH_L4ETC = 0x05,
  80         RSS_HASH_ROCE = 0x06,
  81         RSS_L3_BIDI = 0x07,
  82         RSS_L4_BIDI = 0x08,
  83 };
  84
  85 /* Completion queue entry types */
  86 enum cqe_type {
  87         CQE_TYPE_INVALID = 0x0,
  88         CQE_TYPE_RX = 0x2,
  89         CQE_TYPE_RX_SPLIT = 0x3,
  90         CQE_TYPE_RX_TCP = 0x4,
  91         CQE_TYPE_SEND = 0x8,
  92         CQE_TYPE_SEND_PTP = 0x9,
  93 };
  94
  95 enum cqe_rx_tcp_status {
  96         CQE_RX_STATUS_VALID_TCP_CNXT = 0x00,
  97         CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
  98 };
  99
 100 enum cqe_send_status {
 101         CQE_SEND_STATUS_GOOD = 0x00,
 102         CQE_SEND_STATUS_DESC_FAULT = 0x01,
 103         CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
 104         CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
 105         CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
 106         CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
 107         CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
 108         CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
 109         CQE_SEND_STATUS_LOCK_VIOL = 0x84,
 110         CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
 111         CQE_SEND_STATUS_DATA_FAULT = 0x86,
 112         CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
 113         CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
 114         CQE_SEND_STATUS_MEM_FAULT = 0x89,
 115         CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
 116         CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
 117 };
 118
 119 enum cqe_rx_tcp_end_reason {
 120         CQE_RX_TCP_END_FIN_FLAG_DET = 0,
 121         CQE_RX_TCP_END_INVALID_FLAG = 1,
 122         CQE_RX_TCP_END_TIMEOUT = 2,
 123         CQE_RX_TCP_END_OUT_OF_SEQ = 3,
 124         CQE_RX_TCP_END_PKT_ERR = 4,
 125         CQE_RX_TCP_END_QS_DISABLED = 0x0F,
 126 };
 127
 128 /* Packet protocol level error enumeration */
 129 enum cqe_rx_err_level {
 130         CQE_RX_ERRLVL_RE = 0x0,
 131         CQE_RX_ERRLVL_L2 = 0x1,
 132         CQE_RX_ERRLVL_L3 = 0x2,
 133         CQE_RX_ERRLVL_L4 = 0x3,
 134 };
 135
 136 /* Packet protocol level error type enumeration */
 137 enum cqe_rx_err_opcode {
 138         CQE_RX_ERR_RE_NONE = 0x0,
 139         CQE_RX_ERR_RE_PARTIAL = 0x1,
 140         CQE_RX_ERR_RE_JABBER = 0x2,
 141         CQE_RX_ERR_RE_FCS = 0x7,
 142         CQE_RX_ERR_RE_TERMINATE = 0x9,
 143         CQE_RX_ERR_RE_RX_CTL = 0xb,
 144         CQE_RX_ERR_PREL2_ERR = 0x1f,
 145         CQE_RX_ERR_L2_FRAGMENT = 0x20,
 146         CQE_RX_ERR_L2_OVERRUN = 0x21,
 147         CQE_RX_ERR_L2_PFCS = 0x22,
 148         CQE_RX_ERR_L2_PUNY = 0x23,
 149         CQE_RX_ERR_L2_MAL = 0x24,
 150         CQE_RX_ERR_L2_OVERSIZE = 0x25,
 151         CQE_RX_ERR_L2_UNDERSIZE = 0x26,
 152         CQE_RX_ERR_L2_LENMISM = 0x27,
 153         CQE_RX_ERR_L2_PCLP = 0x28,
 154         CQE_RX_ERR_IP_NOT = 0x41,
 155         CQE_RX_ERR_IP_CHK = 0x42,
 156         CQE_RX_ERR_IP_MAL = 0x43,
 157         CQE_RX_ERR_IP_MALD = 0x44,
 158         CQE_RX_ERR_IP_HOP = 0x45,
 159         CQE_RX_ERR_L3_ICRC = 0x46,
 160         CQE_RX_ERR_L3_PCLP = 0x47,
 161         CQE_RX_ERR_L4_MAL = 0x61,
 162         CQE_RX_ERR_L4_CHK = 0x62,
 163         CQE_RX_ERR_UDP_LEN = 0x63,
 164         CQE_RX_ERR_L4_PORT = 0x64,
 165         CQE_RX_ERR_TCP_FLAG = 0x65,
 166         CQE_RX_ERR_TCP_OFFSET = 0x66,
 167         CQE_RX_ERR_L4_PCLP = 0x67,
 168         CQE_RX_ERR_RBDR_TRUNC = 0x70,
 169 };
 170
 171 struct cqe_rx_t {
 172 #if defined(__BIG_ENDIAN_BITFIELD)
 173         u64   cqe_type:4; /* W0 */
 174         u64   stdn_fault:1;
 175         u64   rsvd0:1;
 176         u64   rq_qs:7;
 177         u64   rq_idx:3;
 178         u64   rsvd1:12;
 179         u64   rss_alg:4;
 180         u64   rsvd2:4;
 181         u64   rb_cnt:4;
 182         u64   vlan_found:1;
 183         u64   vlan_stripped:1;
 184         u64   vlan2_found:1;
 185         u64   vlan2_stripped:1;
 186         u64   l4_type:4;
 187         u64   l3_type:4;
 188         u64   l2_present:1;
 189         u64   err_level:3;
 190         u64   err_opcode:8;
 191
 192         u64   pkt_len:16; /* W1 */
 193         u64   l2_ptr:8;
 194         u64   l3_ptr:8;
 195         u64   l4_ptr:8;
 196         u64   cq_pkt_len:8;
 197         u64   align_pad:3;
 198         u64   rsvd3:1;
 199         u64   chan:12;
 200
 201         u64   rss_tag:32; /* W2 */
 202         u64   vlan_tci:16;
 203         u64   vlan_ptr:8;
 204         u64   vlan2_ptr:8;
 205
 206         u64   rb3_sz:16; /* W3 */
 207         u64   rb2_sz:16;
 208         u64   rb1_sz:16;
 209         u64   rb0_sz:16;
 210
 211         u64   rb7_sz:16; /* W4 */
 212         u64   rb6_sz:16;
 213         u64   rb5_sz:16;
 214         u64   rb4_sz:16;
 215
 216         u64   rb11_sz:16; /* W5 */
 217         u64   rb10_sz:16;
 218         u64   rb9_sz:16;
 219         u64   rb8_sz:16;
 220 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 221         u64   err_opcode:8;
 222         u64   err_level:3;
 223         u64   l2_present:1;
 224         u64   l3_type:4;
 225         u64   l4_type:4;
 226         u64   vlan2_stripped:1;
 227         u64   vlan2_found:1;
 228         u64   vlan_stripped:1;
 229         u64   vlan_found:1;
 230         u64   rb_cnt:4;
 231         u64   rsvd2:4;
 232         u64   rss_alg:4;
 233         u64   rsvd1:12;
 234         u64   rq_idx:3;
 235         u64   rq_qs:7;
 236         u64   rsvd0:1;
 237         u64   stdn_fault:1;
 238         u64   cqe_type:4; /* W0 */
 239         u64   chan:12;
 240         u64   rsvd3:1;
 241         u64   align_pad:3;
 242         u64   cq_pkt_len:8;
 243         u64   l4_ptr:8;
 244         u64   l3_ptr:8;
 245         u64   l2_ptr:8;
 246         u64   pkt_len:16; /* W1 */
 247         u64   vlan2_ptr:8;
 248         u64   vlan_ptr:8;
 249         u64   vlan_tci:16;
 250         u64   rss_tag:32; /* W2 */
 251         u64   rb0_sz:16;
 252         u64   rb1_sz:16;
 253         u64   rb2_sz:16;
 254         u64   rb3_sz:16; /* W3 */
 255         u64   rb4_sz:16;
 256         u64   rb5_sz:16;
 257         u64   rb6_sz:16;
 258         u64   rb7_sz:16; /* W4 */
 259         u64   rb8_sz:16;
 260         u64   rb9_sz:16;
 261         u64   rb10_sz:16;
 262         u64   rb11_sz:16; /* W5 */
 263 #endif
 264         u64   rb0_ptr:64;
 265         u64   rb1_ptr:64;
 266         u64   rb2_ptr:64;
 267         u64   rb3_ptr:64;
 268         u64   rb4_ptr:64;
 269         u64   rb5_ptr:64;
 270         u64   rb6_ptr:64;
 271         u64   rb7_ptr:64;
 272         u64   rb8_ptr:64;
 273         u64   rb9_ptr:64;
 274         u64   rb10_ptr:64;
 275         u64   rb11_ptr:64;
 276 };
 277
 278 struct cqe_rx_tcp_err_t {
 279 #if defined(__BIG_ENDIAN_BITFIELD)
 280         u64   cqe_type:4; /* W0 */
 281         u64   rsvd0:60;
 282
 283         u64   rsvd1:4; /* W1 */
 284         u64   partial_first:1;
 285         u64   rsvd2:27;
 286         u64   rbdr_bytes:8;
 287         u64   rsvd3:24;
 288 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 289         u64   rsvd0:60;
 290         u64   cqe_type:4;
 291
 292         u64   rsvd3:24;
 293         u64   rbdr_bytes:8;
 294         u64   rsvd2:27;
 295         u64   partial_first:1;
 296         u64   rsvd1:4;
 297 #endif
 298 };
 299
 300 struct cqe_rx_tcp_t {
 301 #if defined(__BIG_ENDIAN_BITFIELD)
 302         u64   cqe_type:4; /* W0 */
 303         u64   rsvd0:52;
 304         u64   cq_tcp_status:8;
 305
 306         u64   rsvd1:32; /* W1 */
 307         u64   tcp_cntx_bytes:8;
 308         u64   rsvd2:8;
 309         u64   tcp_err_bytes:16;
 310 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 311         u64   cq_tcp_status:8;
 312         u64   rsvd0:52;
 313         u64   cqe_type:4; /* W0 */
 314
 315         u64   tcp_err_bytes:16;
 316         u64   rsvd2:8;
 317         u64   tcp_cntx_bytes:8;
 318         u64   rsvd1:32; /* W1 */
 319 #endif
 320 };
 321
 322 struct cqe_send_t {
 323 #if defined(__BIG_ENDIAN_BITFIELD)
 324         u64   cqe_type:4; /* W0 */
 325         u64   rsvd0:4;
 326         u64   sqe_ptr:16;
 327         u64   rsvd1:4;
 328         u64   rsvd2:10;
 329         u64   sq_qs:7;
 330         u64   sq_idx:3;
 331         u64   rsvd3:8;
 332         u64   send_status:8;
 333
 334         u64   ptp_timestamp:64; /* W1 */
 335 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 336         u64   send_status:8;
 337         u64   rsvd3:8;
 338         u64   sq_idx:3;
 339         u64   sq_qs:7;
 340         u64   rsvd2:10;
 341         u64   rsvd1:4;
 342         u64   sqe_ptr:16;
 343         u64   rsvd0:4;
 344         u64   cqe_type:4; /* W0 */
 345
 346         u64   ptp_timestamp:64; /* W1 */
 347 #endif
 348 };
 349
 350 union cq_desc_t {
 351         u64    u[64];
 352         struct cqe_send_t snd_hdr;
 353         struct cqe_rx_t rx_hdr;
 354         struct cqe_rx_tcp_t rx_tcp_hdr;
 355         struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
 356 };
 357
 358 struct rbdr_entry_t {
 359         u64   buf_addr;
 360 };
 361
 362 /* TCP reassembly context */
 363 struct rbe_tcp_cnxt_t {
 364 #if defined(__BIG_ENDIAN_BITFIELD)
 365         u64   tcp_pkt_cnt:12;
 366         u64   rsvd1:4;
 367         u64   align_hdr_bytes:4;
 368         u64   align_ptr_bytes:4;
 369         u64   ptr_bytes:16;
 370         u64   rsvd2:24;
 371         u64   cqe_type:4;
 372         u64   rsvd0:54;
 373         u64   tcp_end_reason:2;
 374         u64   tcp_status:4;
 375 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 376         u64   tcp_status:4;
 377         u64   tcp_end_reason:2;
 378         u64   rsvd0:54;
 379         u64   cqe_type:4;
 380         u64   rsvd2:24;
 381         u64   ptr_bytes:16;
 382         u64   align_ptr_bytes:4;
 383         u64   align_hdr_bytes:4;
 384         u64   rsvd1:4;
 385         u64   tcp_pkt_cnt:12;
 386 #endif
 387 };
 388
 389 /* Always Big endian */
 390 struct rx_hdr_t {
 391         u64   opaque:32;
 392         u64   rss_flow:8;
 393         u64   skip_length:6;
 394         u64   disable_rss:1;
 395         u64   disable_tcp_reassembly:1;
 396         u64   nodrop:1;
 397         u64   dest_alg:2;
 398         u64   rsvd0:2;
 399         u64   dest_rq:11;
 400 };
 401
 402 enum send_l4_csum_type {
 403         SEND_L4_CSUM_DISABLE = 0x00,
 404         SEND_L4_CSUM_UDP = 0x01,
 405         SEND_L4_CSUM_TCP = 0x02,
 406         SEND_L4_CSUM_SCTP = 0x03,
 407 };
 408
 409 enum send_crc_alg {
 410         SEND_CRCALG_CRC32 = 0x00,
 411         SEND_CRCALG_CRC32C = 0x01,
 412         SEND_CRCALG_ICRC = 0x02,
 413 };
 414
 415 enum send_load_type {
 416         SEND_LD_TYPE_LDD = 0x00,
 417         SEND_LD_TYPE_LDT = 0x01,
 418         SEND_LD_TYPE_LDWB = 0x02,
 419 };
 420
 421 enum send_mem_alg_type {
 422         SEND_MEMALG_SET = 0x00,
 423         SEND_MEMALG_ADD = 0x08,
 424         SEND_MEMALG_SUB = 0x09,
 425         SEND_MEMALG_ADDLEN = 0x0A,
 426         SEND_MEMALG_SUBLEN = 0x0B,
 427 };
 428
 429 enum send_mem_dsz_type {
 430         SEND_MEMDSZ_B64 = 0x00,
 431         SEND_MEMDSZ_B32 = 0x01,
 432         SEND_MEMDSZ_B8 = 0x03,
 433 };
 434
 435 enum sq_subdesc_type {
 436         SQ_DESC_TYPE_INVALID = 0x00,
 437         SQ_DESC_TYPE_HEADER = 0x01,
 438         SQ_DESC_TYPE_CRC = 0x02,
 439         SQ_DESC_TYPE_IMMEDIATE = 0x03,
 440         SQ_DESC_TYPE_GATHER = 0x04,
 441         SQ_DESC_TYPE_MEMORY = 0x05,
 442 };
 443
 444 struct sq_crc_subdesc {
 445 #if defined(__BIG_ENDIAN_BITFIELD)
 446         u64    rsvd1:32;
 447         u64    crc_ival:32;
 448         u64    subdesc_type:4;
 449         u64    crc_alg:2;
 450         u64    rsvd0:10;
 451         u64    crc_insert_pos:16;
 452         u64    hdr_start:16;
 453         u64    crc_len:16;
 454 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 455         u64    crc_len:16;
 456         u64    hdr_start:16;
 457         u64    crc_insert_pos:16;
 458         u64    rsvd0:10;
 459         u64    crc_alg:2;
 460         u64    subdesc_type:4;
 461         u64    crc_ival:32;
 462         u64    rsvd1:32;
 463 #endif
 464 };
 465
 466 struct sq_gather_subdesc {
 467 #if defined(__BIG_ENDIAN_BITFIELD)
 468         u64    subdesc_type:4; /* W0 */
 469         u64    ld_type:2;
 470         u64    rsvd0:42;
 471         u64    size:16;
 472
 473         u64    rsvd1:15; /* W1 */
 474         u64    addr:49;
 475 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 476         u64    size:16;
 477         u64    rsvd0:42;
 478         u64    ld_type:2;
 479         u64    subdesc_type:4; /* W0 */
 480
 481         u64    addr:49;
 482         u64    rsvd1:15; /* W1 */
 483 #endif
 484 };
 485
 486 /* SQ immediate subdescriptor */
 487 struct sq_imm_subdesc {
 488 #if defined(__BIG_ENDIAN_BITFIELD)
 489         u64    subdesc_type:4; /* W0 */
 490         u64    rsvd0:46;
 491         u64    len:14;
 492
 493         u64    data:64; /* W1 */
 494 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 495         u64    len:14;
 496         u64    rsvd0:46;
 497         u64    subdesc_type:4; /* W0 */
 498
 499         u64    data:64; /* W1 */
 500 #endif
 501 };
 502
 503 struct sq_mem_subdesc {
 504 #if defined(__BIG_ENDIAN_BITFIELD)
 505         u64    subdesc_type:4; /* W0 */
 506         u64    mem_alg:4;
 507         u64    mem_dsz:2;
 508         u64    wmem:1;
 509         u64    rsvd0:21;
 510         u64    offset:32;
 511
 512         u64    rsvd1:15; /* W1 */
 513         u64    addr:49;
 514 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 515         u64    offset:32;
 516         u64    rsvd0:21;
 517         u64    wmem:1;
 518         u64    mem_dsz:2;
 519         u64    mem_alg:4;
 520         u64    subdesc_type:4; /* W0 */
 521
 522         u64    addr:49;
 523         u64    rsvd1:15; /* W1 */
 524 #endif
 525 };
 526
 527 struct sq_hdr_subdesc {
 528 #if defined(__BIG_ENDIAN_BITFIELD)
 529         u64    subdesc_type:4;
 530         u64    tso:1;
 531         u64    post_cqe:1; /* Post CQE on no error also */
 532         u64    dont_send:1;
 533         u64    tstmp:1;
 534         u64    subdesc_cnt:8;
 535         u64    csum_l4:2;
 536         u64    csum_l3:1;
 537         u64    csum_inner_l4:2;
 538         u64    csum_inner_l3:1;
 539         u64    rsvd0:2;
 540         u64    l4_offset:8;
 541         u64    l3_offset:8;
 542         u64    rsvd1:4;
 543         u64    tot_len:20; /* W0 */
 544
 545         u64    rsvd2:24;
 546         u64    inner_l4_offset:8;
 547         u64    inner_l3_offset:8;
 548         u64    tso_start:8;
 549         u64    rsvd3:2;
 550         u64    tso_max_paysize:14; /* W1 */
 551 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 552         u64    tot_len:20;
 553         u64    rsvd1:4;
 554         u64    l3_offset:8;
 555         u64    l4_offset:8;
 556         u64    rsvd0:2;
 557         u64    csum_inner_l3:1;
 558         u64    csum_inner_l4:2;
 559         u64    csum_l3:1;
 560         u64    csum_l4:2;
 561         u64    subdesc_cnt:8;
 562         u64    tstmp:1;
 563         u64    dont_send:1;
 564         u64    post_cqe:1; /* Post CQE on no error also */
 565         u64    tso:1;
 566         u64    subdesc_type:4; /* W0 */
 567
 568         u64    tso_max_paysize:14;
 569         u64    rsvd3:2;
 570         u64    tso_start:8;
 571         u64    inner_l3_offset:8;
 572         u64    inner_l4_offset:8;
 573         u64    rsvd2:24; /* W1 */
 574 #endif
 575 };
 576
 577 /* Queue config register formats */
 578 struct rq_cfg {
 579 #if defined(__BIG_ENDIAN_BITFIELD)
 580         u64 reserved_2_63:62;
 581         u64 ena:1;
 582         u64 tcp_ena:1;
 583 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 584         u64 tcp_ena:1;
 585         u64 ena:1;
 586         u64 reserved_2_63:62;
 587 #endif
 588 };
 589
 590 struct cq_cfg {
 591 #if defined(__BIG_ENDIAN_BITFIELD)
 592         u64 reserved_43_63:21;
 593         u64 ena:1;
 594         u64 reset:1;
 595         u64 caching:1;
 596         u64 reserved_35_39:5;
 597         u64 qsize:3;
 598         u64 reserved_25_31:7;
 599         u64 avg_con:9;
 600         u64 reserved_0_15:16;
 601 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 602         u64 reserved_0_15:16;
 603         u64 avg_con:9;
 604         u64 reserved_25_31:7;
 605         u64 qsize:3;
 606         u64 reserved_35_39:5;
 607         u64 caching:1;
 608         u64 reset:1;
 609         u64 ena:1;
 610         u64 reserved_43_63:21;
 611 #endif
 612 };
 613
 614 struct sq_cfg {
 615 #if defined(__BIG_ENDIAN_BITFIELD)
 616         u64 reserved_32_63:32;
 617         u64 cq_limit:8;
 618         u64 reserved_20_23:4;
 619         u64 ena:1;
 620         u64 reserved_18_18:1;
 621         u64 reset:1;
 622         u64 ldwb:1;
 623         u64 reserved_11_15:5;
 624         u64 qsize:3;
 625         u64 reserved_3_7:5;
 626         u64 tstmp_bgx_intf:3;
 627 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 628         u64 tstmp_bgx_intf:3;
 629         u64 reserved_3_7:5;
 630         u64 qsize:3;
 631         u64 reserved_11_15:5;
 632         u64 ldwb:1;
 633         u64 reset:1;
 634         u64 reserved_18_18:1;
 635         u64 ena:1;
 636         u64 reserved_20_23:4;
 637         u64 cq_limit:8;
 638         u64 reserved_32_63:32;
 639 #endif
 640 };
 641
 642 struct rbdr_cfg {
 643 #if defined(__BIG_ENDIAN_BITFIELD)
 644         u64 reserved_45_63:19;
 645         u64 ena:1;
 646         u64 reset:1;
 647         u64 ldwb:1;
 648         u64 reserved_36_41:6;
 649         u64 qsize:4;
 650         u64 reserved_25_31:7;
 651         u64 avg_con:9;
 652         u64 reserved_12_15:4;
 653         u64 lines:12;
 654 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 655         u64 lines:12;
 656         u64 reserved_12_15:4;
 657         u64 avg_con:9;
 658         u64 reserved_25_31:7;
 659         u64 qsize:4;
 660         u64 reserved_36_41:6;
 661         u64 ldwb:1;
 662         u64 reset:1;
 663         u64 ena: 1;
 664         u64 reserved_45_63:19;
 665 #endif
 666 };
 667
 668 struct qs_cfg {
 669 #if defined(__BIG_ENDIAN_BITFIELD)
 670         u64 reserved_32_63:32;
 671         u64 ena:1;
 672         u64 reserved_27_30:4;
 673         u64 sq_ins_ena:1;
 674         u64 sq_ins_pos:6;
 675         u64 lock_ena:1;
 676         u64 lock_viol_cqe_ena:1;
 677         u64 send_tstmp_ena:1;
 678         u64 be:1;
 679         u64 reserved_7_15:9;
 680         u64 vnic:7;
 681 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 682         u64 vnic:7;
 683         u64 reserved_7_15:9;
 684         u64 be:1;
 685         u64 send_tstmp_ena:1;
 686         u64 lock_viol_cqe_ena:1;
 687         u64 lock_ena:1;
 688         u64 sq_ins_pos:6;
 689         u64 sq_ins_ena:1;
 690         u64 reserved_27_30:4;
 691         u64 ena:1;
 692         u64 reserved_32_63:32;
 693 #endif
 694 };
 695
 696 #endif /* Q_STRUCT_H */