1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
22 #include <linux/version.h>
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/kthread.h>
28 #include <linux/netdevice.h>
29 #include "octeon_config.h"
30 #include "liquidio_common.h"
31 #include "octeon_droq.h"
32 #include "octeon_iq.h"
33 #include "response_manager.h"
34 #include "octeon_device.h"
35 #include "octeon_nic.h"
36 #include "octeon_main.h"
37 #include "octeon_network.h"
38 #include "cn66xx_regs.h"
39 #include "cn66xx_device.h"
40 #include "cn68xx_regs.h"
41 #include "cn68xx_device.h"
42 #include "liquidio_image.h"
43 #include "octeon_mem_ops.h"
45 #define MEMOPS_IDX MAX_BAR1_MAP_INDEX
48 octeon_toggle_bar1_swapmode(struct octeon_device *oct __attribute__((unused)),
49 u32 idx __attribute__((unused)))
51 #ifdef __BIG_ENDIAN_BITFIELD
54 mask = oct->fn_list.bar1_idx_read(oct, idx);
55 mask = (mask & 0x2) ? (mask & ~2) : (mask | 2);
56 oct->fn_list.bar1_idx_write(oct, idx, mask);
61 octeon_pci_fastwrite(struct octeon_device *oct, u8 __iomem *mapped_addr,
64 while ((len) && ((unsigned long)mapped_addr) & 7) {
65 writeb(*(hostbuf++), mapped_addr++);
69 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
72 writeq(*((u64 *)hostbuf), mapped_addr);
78 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
81 writeb(*(hostbuf++), mapped_addr++);
85 octeon_pci_fastread(struct octeon_device *oct, u8 __iomem *mapped_addr,
88 while ((len) && ((unsigned long)mapped_addr) & 7) {
89 *(hostbuf++) = readb(mapped_addr++);
93 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
96 *((u64 *)hostbuf) = readq(mapped_addr);
102 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
105 *(hostbuf++) = readb(mapped_addr++);
108 /* Core mem read/write with temporary bar1 settings. */
109 /* op = 1 to read, op = 0 to write. */
111 __octeon_pci_rw_core_mem(struct octeon_device *oct, u64 addr,
112 u8 *hostbuf, u32 len, u32 op)
114 u32 copy_len = 0, index_reg_val = 0;
116 u8 __iomem *mapped_addr;
118 spin_lock_irqsave(&oct->mem_access_lock, flags);
120 /* Save the original index reg value. */
121 index_reg_val = oct->fn_list.bar1_idx_read(oct, MEMOPS_IDX);
123 oct->fn_list.bar1_idx_setup(oct, addr, MEMOPS_IDX, 1);
124 mapped_addr = oct->mmio[1].hw_addr
125 + (MEMOPS_IDX << 22) + (addr & 0x3fffff);
127 /* If operation crosses a 4MB boundary, split the transfer
131 if (((addr + len - 1) & ~(0x3fffff)) != (addr & ~(0x3fffff))) {
132 copy_len = (u32)(((addr & ~(0x3fffff)) +
133 (MEMOPS_IDX << 22)) - addr);
138 if (op) { /* read from core */
139 octeon_pci_fastread(oct, mapped_addr, hostbuf,
142 octeon_pci_fastwrite(oct, mapped_addr, hostbuf,
152 oct->fn_list.bar1_idx_write(oct, MEMOPS_IDX, index_reg_val);
154 spin_unlock_irqrestore(&oct->mem_access_lock, flags);
158 octeon_pci_read_core_mem(struct octeon_device *oct,
163 __octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 1);
167 octeon_pci_write_core_mem(struct octeon_device *oct,
172 __octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 0);
175 u64 octeon_read_device_mem64(struct octeon_device *oct, u64 coreaddr)
179 __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 8, 1);
181 return be64_to_cpu(ret);
184 u32 octeon_read_device_mem32(struct octeon_device *oct, u64 coreaddr)
188 __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 4, 1);
190 return be32_to_cpu(ret);
193 void octeon_write_device_mem32(struct octeon_device *oct, u64 coreaddr,
196 __be32 t = cpu_to_be32(val);
198 __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&t, 4, 0);