1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2016 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file octeon_device.h
19 * \brief Host Driver: This file defines the octeon device structure.
22 #ifndef _OCTEON_DEVICE_H_
23 #define _OCTEON_DEVICE_H_
25 #include <linux/interrupt.h>
26 #include <net/devlink.h>
28 /** PCI VendorId Device Id */
29 #define OCTEON_CN68XX_PCIID 0x91177d
30 #define OCTEON_CN66XX_PCIID 0x92177d
31 #define OCTEON_CN23XX_PCIID_PF 0x9702177d
32 /** Driver identifies chips by these Ids, created by clubbing together
33 * DeviceId+RevisionId; Where Revision Id is not used to distinguish
34 * between chips, a value of 0 is used for revision id.
36 #define OCTEON_CN68XX 0x0091
37 #define OCTEON_CN66XX 0x0092
38 #define OCTEON_CN23XX_PF_VID 0x9702
39 #define OCTEON_CN23XX_VF_VID 0x9712
41 /**RevisionId for the chips */
42 #define OCTEON_CN23XX_REV_1_0 0x00
43 #define OCTEON_CN23XX_REV_1_1 0x01
44 #define OCTEON_CN23XX_REV_2_0 0x80
46 /**SubsystemId for the chips */
47 #define OCTEON_CN2350_10GB_SUBSYS_ID_1 0X3177d
48 #define OCTEON_CN2350_10GB_SUBSYS_ID_2 0X4177d
49 #define OCTEON_CN2360_10GB_SUBSYS_ID 0X5177d
50 #define OCTEON_CN2350_25GB_SUBSYS_ID 0X7177d
51 #define OCTEON_CN2360_25GB_SUBSYS_ID 0X6177d
53 /** Endian-swap modes supported by Octeon. */
54 enum octeon_pci_swap_mode {
55 OCTEON_PCI_PASSTHROUGH = 0,
56 OCTEON_PCI_64BIT_SWAP = 1,
57 OCTEON_PCI_32BIT_BYTE_SWAP = 2,
58 OCTEON_PCI_32BIT_LW_SWAP = 3
63 FW_NEEDS_TO_BE_LOADED = 1,
64 FW_IS_BEING_LOADED = 2,
65 FW_HAS_BEEN_LOADED = 3,
69 OCTEON_CONFIG_TYPE_DEFAULT = 0,
73 #define OCTEON_INPUT_INTR (1)
74 #define OCTEON_OUTPUT_INTR (2)
75 #define OCTEON_MBOX_INTR (4)
76 #define OCTEON_ALL_INTR 0xff
78 /*--------------- PCI BAR1 index registers -------------*/
81 #define PCI_BAR1_ENABLE_CA 1
82 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP
83 #define PCI_BAR1_ENTRY_VALID 1
84 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \
85 | (PCI_BAR1_ENDIAN_MODE << 1) \
86 | PCI_BAR1_ENTRY_VALID)
88 /** Octeon Device state.
89 * Each octeon device goes through each of these states
90 * as it is initialized.
92 #define OCT_DEV_BEGIN_STATE 0x0
93 #define OCT_DEV_PCI_ENABLE_DONE 0x1
94 #define OCT_DEV_PCI_MAP_DONE 0x2
95 #define OCT_DEV_DISPATCH_INIT_DONE 0x3
96 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4
97 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5
98 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6
99 #define OCT_DEV_DROQ_INIT_DONE 0x7
100 #define OCT_DEV_MBOX_SETUP_DONE 0x8
101 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9
102 #define OCT_DEV_INTR_SET_DONE 0xa
103 #define OCT_DEV_IO_QUEUES_DONE 0xb
104 #define OCT_DEV_CONSOLE_INIT_DONE 0xc
105 #define OCT_DEV_HOST_OK 0xd
106 #define OCT_DEV_CORE_OK 0xe
107 #define OCT_DEV_RUNNING 0xf
108 #define OCT_DEV_IN_RESET 0x10
109 #define OCT_DEV_STATE_INVALID 0x11
111 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID
113 /** Octeon Device interrupts
114 * These interrupt bits are set in int_status filed of
115 * octeon_device structure
117 #define OCT_DEV_INTR_DMA0_FORCE 0x01
118 #define OCT_DEV_INTR_DMA1_FORCE 0x02
119 #define OCT_DEV_INTR_PKT_DATA 0x04
121 #define LIO_RESET_SECS (3)
123 /*---------------------------DISPATCH LIST-------------------------------*/
125 /** The dispatch list entry.
126 * The driver keeps a record of functions registered for each
127 * response header opcode in this structure. Since the opcode is
128 * hashed to index into the driver's list, more than one opcode
129 * can hash to the same entry, in which case the list field points
130 * to a linked list with the other entries.
132 struct octeon_dispatch {
133 /** List head for this entry */
134 struct list_head list;
136 /** The opcode for which the dispatch function & arg should be used */
139 /** The function to be called for a packet received by the driver */
140 octeon_dispatch_fn_t dispatch_fn;
142 /* The application specified argument to be passed to the above
143 * function along with the received packet
148 /** The dispatch list structure. */
149 struct octeon_dispatch_list {
150 /** access to dispatch list must be atomic */
153 /** Count of dispatch functions currently registered */
156 /** The list of dispatch functions */
157 struct octeon_dispatch *dlist;
160 /*----------------------- THE OCTEON DEVICE ---------------------------*/
162 #define OCT_MEM_REGIONS 3
163 /** PCI address space mapping information.
164 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
165 * Octeon gets mapped to different physical address spaces in
169 /** PCI address to which the BAR is mapped. */
172 /** Length of this PCI address space. */
175 /** Length that has been mapped to phys. address space. */
178 /** The physical address to which the PCI address space is mapped. */
181 /** Flag indicating the mapping was successful. */
185 #define MAX_OCTEON_MAPS 32
187 struct octeon_io_enable {
193 struct octeon_reg_list {
194 u32 __iomem *pci_win_wr_addr_hi;
195 u32 __iomem *pci_win_wr_addr_lo;
196 u64 __iomem *pci_win_wr_addr;
198 u32 __iomem *pci_win_rd_addr_hi;
199 u32 __iomem *pci_win_rd_addr_lo;
200 u64 __iomem *pci_win_rd_addr;
202 u32 __iomem *pci_win_wr_data_hi;
203 u32 __iomem *pci_win_wr_data_lo;
204 u64 __iomem *pci_win_wr_data;
206 u32 __iomem *pci_win_rd_data_hi;
207 u32 __iomem *pci_win_rd_data_lo;
208 u64 __iomem *pci_win_rd_data;
211 #define OCTEON_CONSOLE_MAX_READ_BYTES 512
212 typedef int (*octeon_console_print_fn)(struct octeon_device *oct,
213 u32 num, char *pre, char *suf);
214 struct octeon_console {
220 u64 output_base_addr;
221 octeon_console_print_fn print;
222 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
225 struct octeon_board_info {
226 char name[OCT_BOARD_NAME];
227 char serial_number[OCT_SERIAL_LEN];
232 struct octeon_fn_list {
233 void (*setup_iq_regs)(struct octeon_device *, u32);
234 void (*setup_oq_regs)(struct octeon_device *, u32);
236 irqreturn_t (*process_interrupt_regs)(void *);
237 u64 (*msix_interrupt_handler)(void *);
239 int (*setup_mbox)(struct octeon_device *);
240 int (*free_mbox)(struct octeon_device *);
242 int (*soft_reset)(struct octeon_device *);
243 int (*setup_device_regs)(struct octeon_device *);
244 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
245 void (*bar1_idx_write)(struct octeon_device *, u32, u32);
246 u32 (*bar1_idx_read)(struct octeon_device *, u32);
247 u32 (*update_iq_read_idx)(struct octeon_instr_queue *);
249 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
250 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
252 void (*enable_interrupt)(struct octeon_device *, u8);
253 void (*disable_interrupt)(struct octeon_device *, u8);
255 int (*enable_io_queues)(struct octeon_device *);
256 void (*disable_io_queues)(struct octeon_device *);
259 /* Must be multiple of 8, changing breaks ABI */
260 #define CVMX_BOOTMEM_NAME_LEN 128
262 /* Structure for named memory blocks
263 * Number of descriptors
264 * available can be changed without affecting compatibility,
265 * but name length changes require a bump in the bootmem
267 * Note: This structure must be naturally 64 bit aligned, as a single
268 * memory image will be used by both 32 and 64 bit programs.
270 struct cvmx_bootmem_named_block_desc {
271 /** Base address of named block */
274 /** Size actually allocated for named block */
277 /** name of named block */
278 char name[CVMX_BOOTMEM_NAME_LEN];
282 u32 max_nic_ports; /** max nic ports for the device */
283 u32 num_gmx_ports; /** num gmx ports */
284 u64 app_cap_flags; /** firmware cap flags */
286 /** The core application is running in this mode.
287 * See octeon-drv-opcodes.h for values.
290 char liquidio_firmware_version[32];
291 /* Fields extracted from legacy string 'liquidio_firmware_version' */
299 #define OCT_FW_VER(maj, min, rev) \
300 (((u32)(maj) << 16) | ((u32)(min) << 8) | ((u32)(rev)))
302 /* wrappers around work structs */
304 struct delayed_work work;
310 struct workqueue_struct *wq;
314 struct octdev_props {
315 /* Each interface in the Octeon device has a network
316 * device pointer (used for OS specific calls).
323 struct net_device *netdev;
326 #define LIO_FLAG_MSIX_ENABLED 0x1
327 #define MSIX_PO_INT 0x1
328 #define MSIX_PI_INT 0x2
329 #define MSIX_MBOX_INT 0x4
331 struct octeon_pf_vf_hs_word {
332 #ifdef __LITTLE_ENDIAN_BITFIELD
333 /** PKIND value assigned for the DPI interface */
336 /** OCTEON core clock multiplier */
337 u64 core_tics_per_us : 16;
339 /** OCTEON coprocessor clock multiplier */
340 u64 coproc_tics_per_us : 16;
342 /** app that currently running on OCTEON */
353 /** app that currently running on OCTEON */
356 /** OCTEON coprocessor clock multiplier */
357 u64 coproc_tics_per_us : 16;
359 /** OCTEON core clock multiplier */
360 u64 core_tics_per_us : 16;
362 /** PKIND value assigned for the DPI interface */
367 struct octeon_sriov_info {
368 /* Number of rings assigned to VF */
371 /** Max Number of VF devices that can be enabled. This variable can
372 * specified during load time or it will be derived after allocating
373 * PF queues. When max_vfs is derived then each VF will get one queue
377 /** Number of VF devices enabled using sysfs. */
380 /* Actual rings left for PF device */
383 /* SRN of PF usable IO queues */
391 struct lio_trusted_vf trusted_vf;
393 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/
394 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS];
396 u64 vf_macaddr[MAX_POSSIBLE_VFS];
398 u16 vf_vlantci[MAX_POSSIBLE_VFS];
400 int vf_linkstate[MAX_POSSIBLE_VFS];
402 bool vf_spoofchk[MAX_POSSIBLE_VFS];
404 u64 vf_drv_loaded_mask;
407 struct octeon_ioq_vector {
408 struct octeon_device *oct_dev;
412 struct octeon_mbox *mbox;
413 struct cpumask affinity_mask;
417 struct lio_vf_rep_list {
419 struct net_device *ndev[CN23XX_MAX_VFS_PER_PF];
422 struct lio_devlink_priv {
423 struct octeon_device *oct;
426 /** The Octeon device.
427 * Each Octeon device has this structure to represent all its
430 struct octeon_device {
431 /** Lock for PCI window configuration accesses */
432 spinlock_t pci_win_lock;
434 /** Lock for memory accesses */
435 spinlock_t mem_access_lock;
437 /** PCI device pointer */
438 struct pci_dev *pci_dev;
440 /** Chip specific information. */
443 /** Number of interfaces detected in this octeon device. */
446 struct octdev_props props[MAX_OCTEON_LINKS];
448 /** Octeon Chip type. */
459 /** This device's id - set by the driver. */
462 /** This device's PCIe port used for traffic. */
466 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1)
468 /** The state of this device */
471 /** memory mapped io range */
472 struct octeon_mmio mmio[OCT_MEM_REGIONS];
474 struct octeon_reg_list reg_list;
476 struct octeon_fn_list fn_list;
478 struct octeon_board_info boardinfo;
482 /* The pool containing pre allocated buffers used for soft commands */
483 struct octeon_sc_buffer_pool sc_buf_pool;
485 /** The input instruction queues */
486 struct octeon_instr_queue *instr_queue
487 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
489 /** The doubly-linked list of instruction response */
490 struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
494 /** The DROQ output queues */
495 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES];
497 struct octeon_io_enable io_qmask;
499 /** List of dispatch functions */
500 struct octeon_dispatch_list dispatch;
506 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */
507 u64 bootmem_desc_addr;
509 /** Placeholder memory for named blocks.
510 * Assumes single-threaded access
512 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
514 /** Address of consoles descriptor */
515 u64 console_desc_addr;
517 /** Number of consoles available. 0 means they are inaccessible */
521 struct octeon_console console[MAX_OCTEON_MAPS];
523 /* Console named block info */
525 u64 dram_region_base;
529 /* Coprocessor clock rate. */
530 u64 coproc_clock_rate;
532 /** The core application is running in this mode. See liquidio_common.h
537 struct oct_fw_info fw_info;
539 /** The name given to this device. */
540 char device_name[32];
542 /** Application Context */
545 struct cavium_wq dma_comp_wq;
547 /** Lock for dma response list */
548 spinlock_t cmd_resp_wqlock;
551 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
553 struct cavium_wk nic_poll_work;
555 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
563 /* when requesting IRQs, the names are stored here */
564 void *irq_name_storage;
566 struct octeon_sriov_info sriov_info;
568 struct octeon_pf_vf_hs_word pfvf_hsword;
572 /** Mail Box details of each octeon queue. */
573 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS];
575 /** IOq information of it's corresponding MSI-X interrupt. */
576 struct octeon_ioq_vector *ioq_vector;
581 struct oct_link_stats link_stats; /*stastics from firmware*/
583 /* private flags to control driver-specific features through ethtool */
588 u32 rx_coalesce_usecs;
589 u32 rx_max_coalesced_frames;
590 u32 tx_max_coalesced_frames;
600 atomic_t *adapter_refcount; /* reference count of adapter */
602 atomic_t *adapter_fw_state; /* per-adapter, lio_fw_state */
606 struct lio_vf_rep_list vf_rep_list;
607 struct devlink *devlink;
608 enum devlink_eswitch_mode eswitch_mode;
610 /* for 25G NIC speed change */
616 #define LIO_VFSTATS_POLL 10
619 #define OCT_DRV_ONLINE 1
620 #define OCT_DRV_OFFLINE 2
621 #define OCTEON_CN6XXX(oct) ({ \
622 typeof(oct) _oct = (oct); \
623 ((_oct->chip_id == OCTEON_CN66XX) || \
624 (_oct->chip_id == OCTEON_CN68XX)); })
625 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID)
626 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID)
627 #define CHIP_CONF(oct, TYPE) \
628 (((struct octeon_ ## TYPE *)((oct)->chip))->conf)
630 #define MAX_IO_PENDING_PKT_COUNT 100
632 /*------------------ Function Prototypes ----------------------*/
634 /** Initialize device list memory */
635 void octeon_init_device_list(int conf_type);
637 /** Free memory for Input and Output queue structures for a octeon device */
638 void octeon_free_device_mem(struct octeon_device *oct);
640 /* Look up a free entry in the octeon_device table and allocate resources
641 * for the octeon_device structure for an octeon device. Called at init
644 struct octeon_device *octeon_allocate_device(u32 pci_id,
647 /** Register a device's bus location at initialization time.
648 * @param octeon_dev - pointer to the octeon device structure.
649 * @param bus - PCIe bus #
650 * @param dev - PCIe device #
651 * @param func - PCIe function #
652 * @param is_pf - TRUE for PF, FALSE for VF
653 * @return reference count of device's adapter
655 int octeon_register_device(struct octeon_device *oct,
656 int bus, int dev, int func, int is_pf);
658 /** Deregister a device at de-initialization time.
659 * @param octeon_dev - pointer to the octeon device structure.
660 * @return reference count of device's adapter
662 int octeon_deregister_device(struct octeon_device *oct);
664 /** Initialize the driver's dispatch list which is a mix of a hash table
665 * and a linked list. This is done at driver load time.
666 * @param octeon_dev - pointer to the octeon device structure.
667 * @return 0 on success, else -ve error value
669 int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
671 /** Delete the driver's dispatch list and all registered entries.
672 * This is done at driver unload time.
673 * @param octeon_dev - pointer to the octeon device structure.
675 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
677 /** Initialize the core device fields with the info returned by the FW.
678 * @param recv_info - Receive info structure
679 * @param buf - Receive buffer
681 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
683 /** Gets the dispatch function registered to receive packets with a
684 * given opcode/subcode.
685 * @param octeon_dev - the octeon device pointer.
686 * @param opcode - the opcode for which the dispatch function
688 * @param subcode - the subcode for which the dispatch function
691 * @return Success: octeon_dispatch_fn_t (dispatch function pointer)
692 * @return Failure: NULL
694 * Looks up the dispatch list to get the dispatch function for a
698 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
701 /** Get the octeon device pointer.
702 * @param octeon_id - The id for which the octeon device pointer is required.
703 * @return Success: Octeon device pointer.
704 * @return Failure: NULL.
706 struct octeon_device *lio_get_device(u32 octeon_id);
708 /** Get the octeon id assigned to the octeon device passed as argument.
709 * This function is exported to other modules.
710 * @param dev - octeon device pointer passed as a void *.
711 * @return octeon device id
713 int lio_get_device_id(void *dev);
715 /** Read windowed register.
716 * @param oct - pointer to the Octeon device.
717 * @param addr - Address of the register to read.
719 * This routine is called to read from the indirectly accessed
720 * Octeon registers that are visible through a PCI BAR0 mapped window
722 * @return - 64 bit value read from the register.
725 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
727 /** Write windowed register.
728 * @param oct - pointer to the Octeon device.
729 * @param val - Value to write
730 * @param addr - Address of the register to write
732 * This routine is called to write to the indirectly accessed
733 * Octeon registers that are visible through a PCI BAR0 mapped window
737 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
739 /* Routines for reading and writing CSRs */
740 #define octeon_write_csr(oct_dev, reg_off, value) \
741 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
743 #define octeon_write_csr64(oct_dev, reg_off, val64) \
744 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
746 #define octeon_read_csr(oct_dev, reg_off) \
747 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
749 #define octeon_read_csr64(oct_dev, reg_off) \
750 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
753 * Checks if memory access is okay
755 * @param oct which octeon to send to
756 * @return Zero on success, negative on failure.
758 int octeon_mem_access_ok(struct octeon_device *oct);
761 * Waits for DDR initialization.
763 * @param oct which octeon to send to
764 * @param timeout_in_ms pointer to how long to wait until DDR is initialized
766 * If contents are 0, it waits until contents are non-zero
767 * before starting to check.
768 * @return Zero on success, negative on failure.
770 int octeon_wait_for_ddr_init(struct octeon_device *oct,
774 * Wait for u-boot to boot and be waiting for a command.
776 * @param wait_time_hundredths
777 * Maximum time to wait
779 * @return Zero on success, negative on failure.
781 int octeon_wait_for_bootloader(struct octeon_device *oct,
782 u32 wait_time_hundredths);
785 * Initialize console access
787 * @param oct which octeon initialize
788 * @return Zero on success, negative on failure.
790 int octeon_init_consoles(struct octeon_device *oct);
793 * Adds access to a console to the device.
795 * @param oct: which octeon to add to
796 * @param console_num: which console
797 * @param dbg_enb: ptr to debug enablement string, one of:
798 * * NULL for no debug output (i.e. disabled)
799 * * empty string enables debug output (via default method)
800 * * specific string to enable debug console output
802 * @return Zero on success, negative on failure.
804 int octeon_add_console(struct octeon_device *oct, u32 console_num,
807 /** write or read from a console */
808 int octeon_console_write(struct octeon_device *oct, u32 console_num,
809 char *buffer, u32 write_request_size, u32 flags);
810 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
812 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
814 /** Removes all attached consoles. */
815 void octeon_remove_consoles(struct octeon_device *oct);
818 * Send a string to u-boot on console 0 as a command.
820 * @param oct which octeon to send to
821 * @param cmd_str String to send
822 * @param wait_hundredths Time to wait for u-boot to accept the command.
824 * @return Zero on success, negative on failure.
826 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
827 u32 wait_hundredths);
829 /** Parses, validates, and downloads firmware, then boots associated cores.
830 * @param oct which octeon to download firmware to
831 * @param data - The complete firmware file image
832 * @param size - The size of the data
834 * @return 0 if success.
835 * -EINVAL if file is incompatible or badly formatted.
836 * -ENODEV if no handler was found for the application type or an
837 * invalid octeon id was passed.
839 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
842 char *lio_get_state_string(atomic_t *state_ptr);
844 /** Sets up instruction queues for the device
845 * @param oct which octeon to setup
847 * @return 0 if success. 1 if fails
849 int octeon_setup_instr_queues(struct octeon_device *oct);
851 /** Sets up output queues for the device
852 * @param oct which octeon to setup
854 * @return 0 if success. 1 if fails
856 int octeon_setup_output_queues(struct octeon_device *oct);
858 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
860 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
862 /** Turns off the input and output queues for the device
863 * @param oct which octeon to disable
865 int octeon_set_io_queues_off(struct octeon_device *oct);
867 /** Turns on or off the given output queue for the device
868 * @param oct which octeon to change
869 * @param q_no which queue
870 * @param enable 1 to enable, 0 to disable
872 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
874 /** Retrieve the config for the device
875 * @param oct which octeon
876 * @param card_type type of card
878 * @returns pointer to configuration
880 void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
882 /** Gets the octeon device configuration
883 * @return - pointer to the octeon configuration struture
885 struct octeon_config *octeon_get_conf(struct octeon_device *oct);
887 void octeon_free_ioq_vector(struct octeon_device *oct);
888 int octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs);
889 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq);
891 /* LiquidIO driver pivate flags */
893 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */
896 #define OCT_PRIV_FLAG_DEFAULT 0x0
898 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag)
900 return !!(octdev->priv_flags & (0x1 << flag));
903 static inline void lio_set_priv_flag(struct octeon_device *octdev,
907 octdev->priv_flags |= (0x1 << flag);
909 octdev->priv_flags &= ~(0x1 << flag);