1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2016 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file liquidio_common.h
19 * \brief Common: Structures and macros used in PCI-NIC package by core and
23 #ifndef __LIQUIDIO_COMMON_H__
24 #define __LIQUIDIO_COMMON_H__
26 #include "octeon_config.h"
28 #define LIQUIDIO_PACKAGE ""
29 #define LIQUIDIO_BASE_MAJOR_VERSION 1
30 #define LIQUIDIO_BASE_MINOR_VERSION 6
31 #define LIQUIDIO_BASE_MICRO_VERSION 1
32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
33 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
48 /** Tag types used by Octeon cores in its work. */
49 enum octeon_tag_type {
56 /* pre-defined host->NIC tag values */
57 #define LIO_CONTROL (0x11111110)
58 #define LIO_DATA(i) (0x11111111 + (i))
60 /* Opcodes used by host driver/apps to perform operations on the core.
61 * These are used to identify the major subsystem that the operation
64 #define OPCODE_CORE 0 /* used for generic core operations */
65 #define OPCODE_NIC 1 /* used for NIC operations */
66 /* Subcodes are used by host driver/apps to identify the sub-operation
67 * for the core. They only need to by unique for a given subsystem.
69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
71 /** OPCODE_CORE subcodes. For future use. */
73 /** OPCODE_NIC subcodes */
75 /* This subcode is sent by core PCI driver to indicate cores are ready. */
76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
78 #define OPCODE_NIC_CMD 0x03
79 #define OPCODE_NIC_INFO 0x04
80 #define OPCODE_NIC_PORT_STATS 0x05
81 #define OPCODE_NIC_MDIO45 0x06
82 #define OPCODE_NIC_TIMESTAMP 0x07
83 #define OPCODE_NIC_INTRMOD_CFG 0x08
84 #define OPCODE_NIC_IF_CFG 0x09
85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A
86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B
87 #define VF_DRV_LOADED 1
88 #define VF_DRV_REMOVED -1
89 #define VF_DRV_MACADDR_CHANGED 2
91 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
93 /* Application codes advertised by the core driver initialization packet. */
94 #define CVM_DRV_APP_START 0x0
95 #define CVM_DRV_NO_APP 0
96 #define CVM_DRV_APP_COUNT 0x2
97 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
98 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
99 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
100 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
102 #define BYTES_PER_DHLEN_UNIT 8
103 #define MAX_REG_CNT 2000000U
104 #define INTRNAMSIZ 32
105 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
106 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2)
107 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2)
109 #define SCR2_BIT_FW_LOADED 63
111 static inline u32 incr_index(u32 index, u32 count, u32 max)
113 if ((index + count) >= max)
114 index = index + count - max;
121 #define OCT_BOARD_NAME 32
122 #define OCT_SERIAL_LEN 64
124 /* Structure used by core driver to send indication that the Octeon
125 * application is ready.
127 struct octeon_core_setup {
130 char boardname[OCT_BOARD_NAME];
132 char board_serial_number[OCT_SERIAL_LEN];
140 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
142 /* The Scatter-Gather List Entry. The scatter or gather component used with
143 * a Octeon input instruction has this format.
145 struct octeon_sg_entry {
146 /** The first 64 bit gives the size of data in each dptr.*/
152 /** The 4 dptr pointers for this entry. */
157 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
159 /* \brief Add size to gather list
160 * @param sg_entry scatter/gather entry
161 * @param size size to add
162 * @param pos position to add it.
164 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
168 #ifdef __BIG_ENDIAN_BITFIELD
169 sg_entry->u.size[pos] = size;
171 sg_entry->u.size[3 - pos] = size;
175 /*------------------------- End Scatter/Gather ---------------------------*/
177 #define OCTNET_FRM_LENGTH_SIZE 8
179 #define OCTNET_FRM_PTP_HEADER_SIZE 8
181 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
183 #define OCTNET_MIN_FRM_SIZE 64
185 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
187 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
189 /** NIC Commands are sent using this Octeon Input Queue */
190 #define OCTNET_CMD_Q 0
192 /* NIC Command types */
193 #define OCTNET_CMD_CHANGE_MTU 0x1
194 #define OCTNET_CMD_CHANGE_MACADDR 0x2
195 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
196 #define OCTNET_CMD_RX_CTL 0x4
198 #define OCTNET_CMD_SET_MULTI_LIST 0x5
199 #define OCTNET_CMD_CLEAR_STATS 0x6
201 /* command for setting the speed, duplex & autoneg */
202 #define OCTNET_CMD_SET_SETTINGS 0x7
203 #define OCTNET_CMD_SET_FLOW_CTL 0x8
205 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
206 #define OCTNET_CMD_GPIO_ACCESS 0xA
207 #define OCTNET_CMD_LRO_ENABLE 0xB
208 #define OCTNET_CMD_LRO_DISABLE 0xC
209 #define OCTNET_CMD_SET_RSS 0xD
210 #define OCTNET_CMD_WRITE_SA 0xE
211 #define OCTNET_CMD_DELETE_SA 0xF
212 #define OCTNET_CMD_UPDATE_SA 0x12
214 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
215 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
216 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
217 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
218 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
220 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16
221 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
222 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
223 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
225 #define OCTNET_CMD_ID_ACTIVE 0x1a
227 #define OCTNET_CMD_SET_UC_LIST 0x1b
228 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
230 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f
232 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
233 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
234 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
235 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
236 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
237 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
238 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1
239 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0
241 #define LIO_CMD_WAIT_TM 100
243 /* RX(packets coming from wire) Checksum verification flags */
245 #define CNNIC_L4SUM_VERIFIED 0x1
246 #define CNNIC_IPSUM_VERIFIED 0x2
247 #define CNNIC_TUN_CSUM_VERIFIED 0x4
248 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
250 /*LROIPV4 and LROIPV6 Flags*/
251 #define OCTNIC_LROIPV4 0x1
252 #define OCTNIC_LROIPV6 0x2
254 /* Interface flags communicated between host driver and core app. */
255 enum octnet_ifflags {
256 OCTNET_IFFLAG_PROMISC = 0x01,
257 OCTNET_IFFLAG_ALLMULTI = 0x02,
258 OCTNET_IFFLAG_MULTICAST = 0x04,
259 OCTNET_IFFLAG_BROADCAST = 0x08,
260 OCTNET_IFFLAG_UNICAST = 0x10
284 #ifdef __BIG_ENDIAN_BITFIELD
287 u64 more:6; /* How many udd words follow the command */
312 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
314 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
315 #define LIO_SOFTCMDRESP_IH2 40
316 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
318 #define LIO_PCICMD_O2 24
319 #define LIO_PCICMD_O3 (24 + 8)
321 /* Instruction Header(DPI) - for OCTEON-III models */
322 struct octeon_instr_ih3 {
323 #ifdef __BIG_ENDIAN_BITFIELD
328 /** Gather indicator 1=gather*/
331 /** Data length OR no. of entries in gather list */
334 /** Front Data size */
340 /** PKI port kind - PKIND */
350 /** PKI port kind - PKIND */
356 /** Front Data size */
359 /** Data length OR no. of entries in gather list */
362 /** Gather indicator 1=gather*/
371 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
372 /** BIG ENDIAN format. */
373 struct octeon_instr_pki_ih3 {
374 #ifdef __BIG_ENDIAN_BITFIELD
379 /** Raw mode indicator 1 = RAW */
444 /** Raw mode indicator 1 = RAW */
453 /** Instruction Header */
454 struct octeon_instr_ih2 {
455 #ifdef __BIG_ENDIAN_BITFIELD
456 /** Raw mode indicator 1 = RAW */
459 /** Gather indicator 1=gather*/
462 /** Data length OR no. of entries in gather list */
465 /** Front Data size */
468 /** Packet Order / Work Unit selection (1 of 8)*/
471 /** Core group selection (1 of 16) */
474 /** Short Raw Packet Indicator 1=short raw pkt */
489 /** Short Raw Packet Indicator 1=short raw pkt */
492 /** Core group selection (1 of 16) */
495 /** Packet Order / Work Unit selection (1 of 8)*/
498 /** Front Data size */
501 /** Data length OR no. of entries in gather list */
504 /** Gather indicator 1=gather*/
507 /** Raw mode indicator 1 = RAW */
512 /** Input Request Header */
513 struct octeon_instr_irh {
514 #ifdef __BIG_ENDIAN_BITFIELD
521 u64 ossp:32; /* opcode/subcode specific parameters */
523 u64 ossp:32; /* opcode/subcode specific parameters */
533 /** Return Data Parameters */
534 struct octeon_instr_rdp {
535 #ifdef __BIG_ENDIAN_BITFIELD
546 /** Receive Header */
548 #ifdef __BIG_ENDIAN_BITFIELD
553 u64 len:3; /** additional 64-bit words */
555 u64 ossp:32; /** opcode/subcode specific parameters */
560 u64 len:3; /** additional 64-bit words */
564 u64 csum_verified:3; /** checksum verified. */
565 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
567 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
572 u64 len:3; /** additional 64-bit words */
575 u64 max_nic_ports:10;
583 u64 len:3; /** additional 64-bit words */
591 u64 ossp:32; /** opcode/subcode specific parameters */
593 u64 len:3; /** additional 64-bit words */
598 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
600 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
601 u64 csum_verified:3; /** checksum verified. */
605 u64 len:3; /** additional 64-bit words */
613 u64 max_nic_ports:10;
616 u64 len:3; /** additional 64-bit words */
624 u64 len:3; /** additional 64-bit words */
631 #define OCT_RH_SIZE (sizeof(union octeon_rh))
633 union octnic_packet_params {
636 #ifdef __BIG_ENDIAN_BITFIELD
638 u32 ip_csum:1; /* Perform IP header checksum(s) */
639 /* Perform Outer transport header checksum */
640 u32 transport_csum:1;
641 /* Find tunnel, and perform transport csum. */
643 u32 tsflag:1; /* Timestamp this packet */
644 u32 ipsec_ops:4; /* IPsec operation */
649 u32 transport_csum:1;
656 /** Status of a RGMII Link on Octeon as seen by core driver. */
657 union oct_link_status {
661 #ifdef __BIG_ENDIAN_BITFIELD
685 /** The txpciq info passed to host from the firmware */
691 #ifdef __BIG_ENDIAN_BITFIELD
709 /** The rxpciq info passed to host from the firmware */
715 #ifdef __BIG_ENDIAN_BITFIELD
725 /** Information for a OCTEON ethernet interface shared between core & host. */
726 struct oct_link_info {
727 union oct_link_status link;
730 #ifdef __BIG_ENDIAN_BITFIELD
732 u64 macaddr_is_admin_asgnd:1;
740 u64 macaddr_is_admin_asgnd:1;
744 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
745 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
748 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
750 struct liquidio_if_cfg_info {
751 u64 iqmask; /** mask for IQs enabled for the port */
752 u64 oqmask; /** mask for OQs enabled for the port */
753 struct oct_link_info linfo; /** initial link information */
754 char liquidio_firmware_version[32];
757 /** Stats for each NIC port in RX direction. */
758 struct nic_rx_stats {
759 /* link-level stats */
766 u64 fifo_err; /* Accounts for over/under-run of buffers */
776 u64 fw_total_fwd_bytes;
784 u64 fw_lro_pkts; /* Number of packets that are LROed */
785 u64 fw_lro_octs; /* Number of octets that are LROed */
786 u64 fw_total_lro; /* Number of LRO packets formed */
787 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
788 u64 fw_lro_aborts_port;
789 u64 fw_lro_aborts_seq;
790 u64 fw_lro_aborts_tsval;
791 u64 fw_lro_aborts_timer;
792 /* intrmod: packet forward rate */
796 /** Stats for each NIC port in RX direction. */
797 struct nic_tx_stats {
798 /* link-level stats */
800 u64 total_bytes_sent;
804 u64 one_collision_sent; /* Packets sent after one collision*/
805 u64 multi_collision_sent; /* Packets sent after multiple collision*/
806 u64 max_collision_fail; /* Packets not sent due to max collisions */
807 u64 max_deferral_fail; /* Packets not sent due to max deferrals */
808 u64 fifo_err; /* Accounts for over/under-run of buffers */
810 u64 total_collisions; /* Total number of collisions detected */
815 u64 fw_total_fwd_bytes;
820 u64 fw_tso; /* number of tso requests */
821 u64 fw_tso_fwd; /* number of packets segmented in tso */
826 struct oct_link_stats {
827 struct nic_rx_stats fromwire;
828 struct nic_tx_stats fromhost;
832 static inline int opcode_slow_path(union octeon_rh *rh)
834 u16 subcode1, subcode2;
836 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
837 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA);
839 return (subcode2 != subcode1);
842 #define LIO68XX_LED_CTRL_ADDR 0x3501
843 #define LIO68XX_LED_CTRL_CFGON 0x1f
844 #define LIO68XX_LED_CTRL_CFGOFF 0x100
845 #define LIO68XX_LED_BEACON_ADDR 0x3508
846 #define LIO68XX_LED_BEACON_CFGON 0x47fd
847 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
848 #define VITESSE_PHY_GPIO_DRIVEON 0x1
849 #define VITESSE_PHY_GPIO_CFG 0x8
850 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
851 #define VITESSE_PHY_GPIO_HIGH 0x2
852 #define VITESSE_PHY_GPIO_LOW 0x3
853 #define LED_IDENTIFICATION_ON 0x1
854 #define LED_IDENTIFICATION_OFF 0x0
856 struct oct_mdio_cmd {
864 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
866 struct oct_intrmod_cfg {
872 u64 rx_maxcnt_trigger;
873 u64 rx_mincnt_trigger;
874 u64 rx_maxtmr_trigger;
875 u64 rx_mintmr_trigger;
876 u64 tx_mincnt_trigger;
877 u64 tx_maxcnt_trigger;
883 #define BASE_QUEUE_NOT_REQUESTED 65535
885 union oct_nic_if_cfg {
888 #ifdef __BIG_ENDIAN_BITFIELD