1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2016 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 #include <linux/pci.h>
19 #include <linux/netdevice.h>
20 #include <linux/vmalloc.h>
21 #include "liquidio_common.h"
22 #include "octeon_droq.h"
23 #include "octeon_iq.h"
24 #include "response_manager.h"
25 #include "octeon_device.h"
26 #include "cn23xx_vf_device.h"
27 #include "octeon_main.h"
28 #include "octeon_mailbox.h"
30 u32 cn23xx_vf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)
32 /* This gives the SLI clock per microsec */
33 u32 oqticks_per_us = (u32)oct->pfvf_hsword.coproc_tics_per_us;
35 /* This gives the clock cycles per millisecond */
36 oqticks_per_us *= 1000;
38 /* This gives the oq ticks (1024 core clock cycles) per millisecond */
39 oqticks_per_us /= 1024;
41 /* time_intr is in microseconds. The next 2 steps gives the oq ticks
42 * corressponding to time_intr.
44 oqticks_per_us *= time_intr_in_us;
45 oqticks_per_us /= 1000;
47 return oqticks_per_us;
50 static int cn23xx_vf_reset_io_queues(struct octeon_device *oct, u32 num_queues)
52 u32 loop = BUSY_READING_REG_VF_LOOP_COUNT;
57 for (q_no = 0; q_no < num_queues; q_no++) {
58 /* set RST bit to 1. This bit applies to both IQ and OQ */
59 d64 = octeon_read_csr64(oct,
60 CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
61 d64 |= CN23XX_PKT_INPUT_CTL_RST;
62 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
66 /* wait until the RST bit is clear or the RST and QUIET bits are set */
67 for (q_no = 0; q_no < num_queues; q_no++) {
68 u64 reg_val = octeon_read_csr64(oct,
69 CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
73 WRITE_ONCE(reg_val, octeon_read_csr64(
74 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)));
78 dev_err(&oct->pci_dev->dev,
79 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
84 ~CN23XX_PKT_INPUT_CTL_RST);
85 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
88 WRITE_ONCE(reg_val, octeon_read_csr64(
89 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)));
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
91 dev_err(&oct->pci_dev->dev,
92 "clearing the reset failed for qno: %u\n",
101 static int cn23xx_vf_setup_global_input_regs(struct octeon_device *oct)
103 struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
104 struct octeon_instr_queue *iq;
105 u64 q_no, intr_threshold;
108 if (cn23xx_vf_reset_io_queues(oct, oct->sriov_info.rings_per_vf))
111 for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) {
112 void __iomem *inst_cnt_reg;
114 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_DOORBELL(q_no),
116 iq = oct->instr_queue[q_no];
119 inst_cnt_reg = iq->inst_cnt_reg;
121 inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +
122 CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no);
124 d64 = octeon_read_csr64(oct,
125 CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no));
127 d64 &= 0xEFFFFFFFFFFFFFFFL;
129 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
132 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
135 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
136 CN23XX_PKT_INPUT_CTL_MASK);
138 /* set the wmark level to trigger PI_INT */
139 intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) &
140 CN23XX_PKT_IN_DONE_WMARK_MASK;
142 writeq((readq(inst_cnt_reg) &
143 ~(CN23XX_PKT_IN_DONE_WMARK_MASK <<
144 CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
145 (intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS),
151 static void cn23xx_vf_setup_global_output_regs(struct octeon_device *oct)
156 for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) {
157 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKTS_CREDIT(q_no),
161 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no));
163 reg_val &= 0xEFFFFFFFFFFFFFFFL;
166 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no));
169 reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR;
172 reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;
175 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
177 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
178 * for Output Queue ScatterList reset ROR_P, NSR_P
180 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
181 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
183 #ifdef __LITTLE_ENDIAN_BITFIELD
184 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
186 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
188 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
189 * for Output Queue Data reset ROR, NSR
191 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
192 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
194 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
196 /* write all the selected settings */
197 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no),
202 static int cn23xx_setup_vf_device_regs(struct octeon_device *oct)
204 if (cn23xx_vf_setup_global_input_regs(oct))
207 cn23xx_vf_setup_global_output_regs(oct);
212 static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no)
214 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
217 /* Write the start of the input queue's ring and its size */
218 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(iq_no),
220 octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count);
222 /* Remember the doorbell & instruction count register addr
226 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_DOORBELL(iq_no);
228 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq_no);
229 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
230 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
232 /* Store the current instruction counter (used in flush_iq
235 pkt_in_done = readq(iq->inst_cnt_reg);
238 /* Set CINT_ENB to enable IQ interrupt */
239 writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),
242 iq->reset_instr_cnt = 0;
245 static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no)
247 struct octeon_droq *droq = oct->droq[oq_no];
249 octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no),
250 droq->desc_ring_dma);
251 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count);
253 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no),
256 /* Get the mapped address of the pkt_sent and pkts_credit regs */
257 droq->pkts_sent_reg =
258 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no);
259 droq->pkts_credit_reg =
260 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no);
263 static void cn23xx_vf_mbox_thread(struct work_struct *work)
265 struct cavium_wk *wk = (struct cavium_wk *)work;
266 struct octeon_mbox *mbox = (struct octeon_mbox *)wk->ctxptr;
268 octeon_mbox_process_message(mbox);
271 static int cn23xx_free_vf_mbox(struct octeon_device *oct)
273 cancel_delayed_work_sync(&oct->mbox[0]->mbox_poll_wk.work);
278 static int cn23xx_setup_vf_mbox(struct octeon_device *oct)
280 struct octeon_mbox *mbox = NULL;
282 mbox = vmalloc(sizeof(*mbox));
286 memset(mbox, 0, sizeof(struct octeon_mbox));
288 spin_lock_init(&mbox->lock);
294 mbox->state = OCTEON_MBOX_STATE_IDLE;
296 /* VF mbox interrupt reg */
298 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_PKT_MBOX_INT(0);
299 /* VF reads from SIG0 reg */
300 mbox->mbox_read_reg =
301 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0);
302 /* VF writes into SIG1 reg */
303 mbox->mbox_write_reg =
304 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1);
306 INIT_DELAYED_WORK(&mbox->mbox_poll_wk.work,
307 cn23xx_vf_mbox_thread);
309 mbox->mbox_poll_wk.ctxptr = mbox;
313 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
318 static int cn23xx_enable_vf_io_queues(struct octeon_device *oct)
322 for (q_no = 0; q_no < oct->num_iqs; q_no++) {
325 /* set the corresponding IQ IS_64B bit */
326 if (oct->io_qmask.iq64B & BIT_ULL(q_no)) {
327 reg_val = octeon_read_csr64(
328 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
329 reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B;
331 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
334 /* set the corresponding IQ ENB bit */
335 if (oct->io_qmask.iq & BIT_ULL(q_no)) {
336 reg_val = octeon_read_csr64(
337 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
338 reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB;
340 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
343 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
346 /* set the corresponding OQ ENB bit */
347 if (oct->io_qmask.oq & BIT_ULL(q_no)) {
348 reg_val = octeon_read_csr(
349 oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no));
350 reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB;
352 oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val);
359 static void cn23xx_disable_vf_io_queues(struct octeon_device *oct)
361 u32 num_queues = oct->num_iqs;
363 /* per HRM, rings can only be disabled via reset operation,
364 * NOT via SLI_PKT()_INPUT/OUTPUT_CONTROL[ENB]
366 if (num_queues < oct->num_oqs)
367 num_queues = oct->num_oqs;
369 cn23xx_vf_reset_io_queues(oct, num_queues);
372 void cn23xx_vf_ask_pf_to_do_flr(struct octeon_device *oct)
374 struct octeon_mbox_cmd mbox_cmd;
376 mbox_cmd.msg.u64 = 0;
377 mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
378 mbox_cmd.msg.s.resp_needed = 0;
379 mbox_cmd.msg.s.cmd = OCTEON_VF_FLR_REQUEST;
380 mbox_cmd.msg.s.len = 1;
382 mbox_cmd.recv_len = 0;
383 mbox_cmd.recv_status = 0;
387 octeon_mbox_write(oct, &mbox_cmd);
390 static void octeon_pfvf_hs_callback(struct octeon_device *oct,
391 struct octeon_mbox_cmd *cmd,
396 memcpy((uint8_t *)&oct->pfvf_hsword, cmd->msg.s.params,
397 CN23XX_MAILBOX_MSGPARAM_SIZE);
398 if (cmd->recv_len > 1) {
399 major = ((struct lio_version *)(cmd->data))->major;
403 atomic_set((atomic_t *)arg, major | 1);
406 int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct)
408 struct octeon_mbox_cmd mbox_cmd;
415 /* Sending VF_ACTIVE indication to the PF driver */
416 dev_dbg(&oct->pci_dev->dev, "requesting info from pf\n");
418 mbox_cmd.msg.u64 = 0;
419 mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
420 mbox_cmd.msg.s.resp_needed = 1;
421 mbox_cmd.msg.s.cmd = OCTEON_VF_ACTIVE;
422 mbox_cmd.msg.s.len = 2;
423 mbox_cmd.data[0] = 0;
424 ((struct lio_version *)&mbox_cmd.data[0])->major =
425 LIQUIDIO_BASE_MAJOR_VERSION;
426 ((struct lio_version *)&mbox_cmd.data[0])->minor =
427 LIQUIDIO_BASE_MINOR_VERSION;
428 ((struct lio_version *)&mbox_cmd.data[0])->micro =
429 LIQUIDIO_BASE_MICRO_VERSION;
431 mbox_cmd.recv_len = 0;
432 mbox_cmd.recv_status = 0;
433 mbox_cmd.fn = (octeon_mbox_callback_t)octeon_pfvf_hs_callback;
434 mbox_cmd.fn_arg = &status;
436 octeon_mbox_write(oct, &mbox_cmd);
438 atomic_set(&status, 0);
441 schedule_timeout_uninterruptible(1);
442 } while ((!atomic_read(&status)) && (count++ < 100000));
444 ret = atomic_read(&status);
446 dev_err(&oct->pci_dev->dev, "octeon_pfvf_handshake timeout\n");
450 for (q_no = 0 ; q_no < oct->num_iqs ; q_no++)
451 oct->instr_queue[q_no]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
453 vfmajor = LIQUIDIO_BASE_MAJOR_VERSION;
455 if (pfmajor != vfmajor) {
456 dev_err(&oct->pci_dev->dev,
457 "VF Liquidio driver (major version %d) is not compatible with Liquidio PF driver (major version %d)\n",
462 dev_dbg(&oct->pci_dev->dev,
463 "VF Liquidio driver (major version %d), Liquidio PF driver (major version %d)\n",
466 dev_dbg(&oct->pci_dev->dev, "got data from pf pkind is %d\n",
467 oct->pfvf_hsword.pkind);
472 static void cn23xx_handle_vf_mbox_intr(struct octeon_ioq_vector *ioq_vector)
474 struct octeon_device *oct = ioq_vector->oct_dev;
477 if (!ioq_vector->droq_index) {
478 /* read and clear by writing 1 */
479 mbox_int_val = readq(oct->mbox[0]->mbox_int_reg);
480 writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg);
481 if (octeon_mbox_read(oct->mbox[0]))
482 schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work,
483 msecs_to_jiffies(0));
487 static u64 cn23xx_vf_msix_interrupt_handler(void *dev)
489 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
490 struct octeon_device *oct = ioq_vector->oct_dev;
491 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
495 dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);
496 pkts_sent = readq(droq->pkts_sent_reg);
498 /* If our device has interrupted, then proceed. Also check
499 * for all f's if interrupt was triggered on an error
500 * and the PCI read fails.
502 if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL))
505 /* Write count reg in sli_pkt_cnts to clear these int. */
506 if ((pkts_sent & CN23XX_INTR_PO_INT) ||
507 (pkts_sent & CN23XX_INTR_PI_INT)) {
508 if (pkts_sent & CN23XX_INTR_PO_INT)
512 if (pkts_sent & CN23XX_INTR_PI_INT)
513 /* We will clear the count when we update the read_index. */
516 if (pkts_sent & CN23XX_INTR_MBOX_INT) {
517 cn23xx_handle_vf_mbox_intr(ioq_vector);
518 ret |= MSIX_MBOX_INT;
524 static u32 cn23xx_update_read_index(struct octeon_instr_queue *iq)
526 u32 pkt_in_done = readl(iq->inst_cnt_reg);
530 last_done = pkt_in_done - iq->pkt_in_done;
531 iq->pkt_in_done = pkt_in_done;
533 /* Modulo of the new index with the IQ size will give us
534 * the new index. The iq->reset_instr_cnt is always zero for
535 * cn23xx, so no extra adjustments are needed.
537 new_idx = (iq->octeon_read_index +
538 (u32)(last_done & CN23XX_PKT_IN_DONE_CNT_MASK)) %
544 static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag)
546 struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
547 u32 q_no, time_threshold;
549 if (intr_flag & OCTEON_OUTPUT_INTR) {
550 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
551 /* Set up interrupt packet and time thresholds
554 time_threshold = cn23xx_vf_get_oq_ticks(
555 oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
558 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
559 (CFG_GET_OQ_INTR_PKT(cn23xx->conf) |
560 ((u64)time_threshold << 32)));
564 if (intr_flag & OCTEON_INPUT_INTR) {
565 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
566 /* Set CINT_ENB to enable IQ interrupt */
568 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
570 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) &
571 ~CN23XX_PKT_IN_DONE_CNT_MASK) |
572 CN23XX_INTR_CINT_ENB));
576 /* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */
577 if (intr_flag & OCTEON_MBOX_INTR) {
579 oct, CN23XX_VF_SLI_PKT_MBOX_INT(0),
580 (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) |
581 CN23XX_INTR_MBOX_ENB));
585 static void cn23xx_disable_vf_interrupt(struct octeon_device *oct, u8 intr_flag)
589 if (intr_flag & OCTEON_OUTPUT_INTR) {
590 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
591 /* Write all 1's in INT_LEVEL reg to disable PO_INT */
593 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
597 if (intr_flag & OCTEON_INPUT_INTR) {
598 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
600 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
602 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) &
603 ~(CN23XX_INTR_CINT_ENB |
604 CN23XX_PKT_IN_DONE_CNT_MASK)));
608 if (intr_flag & OCTEON_MBOX_INTR) {
610 oct, CN23XX_VF_SLI_PKT_MBOX_INT(0),
611 (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) &
612 ~CN23XX_INTR_MBOX_ENB));
616 int cn23xx_setup_octeon_vf_device(struct octeon_device *oct)
618 struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
619 u32 rings_per_vf, ring_flag;
622 if (octeon_map_pci_barx(oct, 0, 0))
625 /* INPUT_CONTROL[RPVF] gives the VF IOq count */
626 reg_val = octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(0));
628 oct->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
629 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
630 oct->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
631 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
633 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
635 rings_per_vf = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
639 cn23xx->conf = oct_get_config_info(oct, LIO_23XX);
641 dev_err(&oct->pci_dev->dev, "%s No Config found for CN23XX\n",
643 octeon_unmap_pci_barx(oct, 0);
647 if (oct->sriov_info.rings_per_vf > rings_per_vf) {
648 dev_warn(&oct->pci_dev->dev,
649 "num_queues:%d greater than PF configured rings_per_vf:%d. Reducing to %d.\n",
650 oct->sriov_info.rings_per_vf, rings_per_vf,
652 oct->sriov_info.rings_per_vf = rings_per_vf;
654 if (rings_per_vf > num_present_cpus()) {
655 dev_warn(&oct->pci_dev->dev,
656 "PF configured rings_per_vf:%d greater than num_cpu:%d. Using rings_per_vf:%d equal to num cpus\n",
660 oct->sriov_info.rings_per_vf =
663 oct->sriov_info.rings_per_vf = rings_per_vf;
667 oct->fn_list.setup_iq_regs = cn23xx_setup_vf_iq_regs;
668 oct->fn_list.setup_oq_regs = cn23xx_setup_vf_oq_regs;
669 oct->fn_list.setup_mbox = cn23xx_setup_vf_mbox;
670 oct->fn_list.free_mbox = cn23xx_free_vf_mbox;
672 oct->fn_list.msix_interrupt_handler = cn23xx_vf_msix_interrupt_handler;
674 oct->fn_list.setup_device_regs = cn23xx_setup_vf_device_regs;
675 oct->fn_list.update_iq_read_idx = cn23xx_update_read_index;
677 oct->fn_list.enable_interrupt = cn23xx_enable_vf_interrupt;
678 oct->fn_list.disable_interrupt = cn23xx_disable_vf_interrupt;
680 oct->fn_list.enable_io_queues = cn23xx_enable_vf_io_queues;
681 oct->fn_list.disable_io_queues = cn23xx_disable_vf_io_queues;
686 void cn23xx_dump_vf_iq_regs(struct octeon_device *oct)
690 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n",
691 CN23XX_VF_SLI_IQ_DOORBELL(0),
692 CVM_CAST64(octeon_read_csr64(
693 oct, CN23XX_VF_SLI_IQ_DOORBELL(0))));
695 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n",
696 CN23XX_VF_SLI_IQ_BASE_ADDR64(0),
697 CVM_CAST64(octeon_read_csr64(
698 oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(0))));
700 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n",
701 CN23XX_VF_SLI_IQ_SIZE(0),
702 CVM_CAST64(octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_SIZE(0))));
704 for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
705 dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n",
706 q_no, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
707 CVM_CAST64(octeon_read_csr64(
708 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))));
711 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val);
712 dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n",
713 CN23XX_CONFIG_PCIE_DEVCTL, regval);