1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
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14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
23 /*! \file cn23xx_regs.h
24 * \brief Host Driver: Register Address and Register Mask values for
25 * Octeon CN23XX devices.
28 #ifndef __CN23XX_PF_REGS_H__
29 #define __CN23XX_PF_REGS_H__
31 #define CN23XX_CONFIG_VENDOR_ID 0x00
32 #define CN23XX_CONFIG_DEVICE_ID 0x02
34 #define CN23XX_CONFIG_XPANSION_BAR 0x38
36 #define CN23XX_CONFIG_MSIX_CAP 0x50
37 #define CN23XX_CONFIG_MSIX_LMSI 0x54
38 #define CN23XX_CONFIG_MSIX_UMSI 0x58
39 #define CN23XX_CONFIG_MSIX_MSIMD 0x5C
40 #define CN23XX_CONFIG_MSIX_MSIMM 0x60
41 #define CN23XX_CONFIG_MSIX_MSIMP 0x64
43 #define CN23XX_CONFIG_PCIE_CAP 0x70
44 #define CN23XX_CONFIG_PCIE_DEVCAP 0x74
45 #define CN23XX_CONFIG_PCIE_DEVCTL 0x78
46 #define CN23XX_CONFIG_PCIE_LINKCAP 0x7C
47 #define CN23XX_CONFIG_PCIE_LINKCTL 0x80
48 #define CN23XX_CONFIG_PCIE_SLOTCAP 0x84
49 #define CN23XX_CONFIG_PCIE_SLOTCTL 0x88
50 #define CN23XX_CONFIG_PCIE_DEVCTL2 0x98
51 #define CN23XX_CONFIG_PCIE_LINKCTL2 0xA0
52 #define CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK 0x108
53 #define CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS 0x110
54 #define CN23XX_CONFIG_PCIE_DEVCTL_MASK 0x00040000
56 #define CN23XX_PCIE_SRIOV_FDL 0x188
57 #define CN23XX_PCIE_SRIOV_FDL_BIT_POS 0x10
58 #define CN23XX_PCIE_SRIOV_FDL_MASK 0xFF
60 #define CN23XX_CONFIG_PCIE_FLTMSK 0x720
62 #define CN23XX_CONFIG_SRIOV_VFDEVID 0x190
64 #define CN23XX_CONFIG_SRIOV_BAR_START 0x19C
65 #define CN23XX_CONFIG_SRIOV_BARX(i) \
66 (CN23XX_CONFIG_SRIOV_BAR_START + (i * 4))
67 #define CN23XX_CONFIG_SRIOV_BAR_PF 0x08
68 #define CN23XX_CONFIG_SRIOV_BAR_64BIT 0x04
69 #define CN23XX_CONFIG_SRIOV_BAR_IO 0x01
71 /* ############## BAR0 Registers ################ */
73 #define CN23XX_SLI_CTL_PORT_START 0x286E0
74 #define CN23XX_PORT_OFFSET 0x10
76 #define CN23XX_SLI_CTL_PORT(p) \
77 (CN23XX_SLI_CTL_PORT_START + ((p) * CN23XX_PORT_OFFSET))
79 /* 2 scatch registers (64-bit) */
80 #define CN23XX_SLI_WINDOW_CTL 0x282E0
81 #define CN23XX_SLI_SCRATCH1 0x283C0
82 #define CN23XX_SLI_SCRATCH2 0x283D0
83 #define CN23XX_SLI_WINDOW_CTL_DEFAULT 0x200000ULL
85 /* 1 registers (64-bit) - SLI_CTL_STATUS */
86 #define CN23XX_SLI_CTL_STATUS 0x28570
88 /* SLI Packet Input Jabber Register (64 bit register)
89 * <31:0> for Byte count for limiting sizes of packet sizes
90 * that are allowed for sli packet inbound packets.
91 * the default value is 0xFA00(=64000).
93 #define CN23XX_SLI_PKT_IN_JABBER 0x29170
94 /* The input jabber is used to determine the TSO max size.
95 * Due to H/W limitation, this need to be reduced to 60000
96 * in order to to H/W TSO and avoid the WQE malfarmation
97 * PKO_BUG_24989_WQE_LEN
99 #define CN23XX_DEFAULT_INPUT_JABBER 0xEA60 /*60000*/
101 #define CN23XX_WIN_WR_ADDR_LO 0x20000
102 #define CN23XX_WIN_WR_ADDR_HI 0x20004
103 #define CN23XX_WIN_WR_ADDR64 CN23XX_WIN_WR_ADDR_LO
105 #define CN23XX_WIN_RD_ADDR_LO 0x20010
106 #define CN23XX_WIN_RD_ADDR_HI 0x20014
107 #define CN23XX_WIN_RD_ADDR64 CN23XX_WIN_RD_ADDR_LO
109 #define CN23XX_WIN_WR_DATA_LO 0x20020
110 #define CN23XX_WIN_WR_DATA_HI 0x20024
111 #define CN23XX_WIN_WR_DATA64 CN23XX_WIN_WR_DATA_LO
113 #define CN23XX_WIN_RD_DATA_LO 0x20040
114 #define CN23XX_WIN_RD_DATA_HI 0x20044
115 #define CN23XX_WIN_RD_DATA64 CN23XX_WIN_RD_DATA_LO
117 #define CN23XX_WIN_WR_MASK_LO 0x20030
118 #define CN23XX_WIN_WR_MASK_HI 0x20034
119 #define CN23XX_WIN_WR_MASK_REG CN23XX_WIN_WR_MASK_LO
120 #define CN23XX_SLI_MAC_CREDIT_CNT 0x23D70
122 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
123 * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO
125 #define CN23XX_SLI_PKT_MAC_RINFO_START64 0x29030
127 /*1 register (64-bit) to determine whether IOQs are in reset. */
128 #define CN23XX_SLI_PKT_IOQ_RING_RST 0x291E0
130 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
131 #define CN23XX_IQ_OFFSET 0x20000
133 #define CN23XX_MAC_RINFO_OFFSET 0x20
134 #define CN23XX_PF_RINFO_OFFSET 0x10
136 #define CN23XX_SLI_PKT_MAC_RINFO64(mac, pf) \
137 (CN23XX_SLI_PKT_MAC_RINFO_START64 + \
138 ((mac) * CN23XX_MAC_RINFO_OFFSET) + \
139 ((pf) * CN23XX_PF_RINFO_OFFSET))
141 /** mask for total rings, setting TRS to base */
142 #define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)
143 /** mask for starting ring number: setting SRN <6:0> = 0x7F */
144 #define CN23XX_PKT_MAC_CTL_RINFO_SRN (0x7F)
146 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
147 #define CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS 16
148 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
149 #define CN23XX_PKT_MAC_CTL_RINFO_SRN_BIT_POS 0
150 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
151 #define CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS 32
152 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
153 #define CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS 48
155 /*###################### REQUEST QUEUE #########################*/
157 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
158 #define CN23XX_SLI_IQ_INSTR_COUNT_START64 0x10040
160 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
161 #define CN23XX_SLI_IQ_BASE_ADDR_START64 0x10010
163 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
164 #define CN23XX_SLI_IQ_DOORBELL_START 0x10020
166 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
167 #define CN23XX_SLI_IQ_SIZE_START 0x10030
169 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
170 * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL.
172 #define CN23XX_SLI_IQ_PKT_CONTROL_START64 0x10000
174 /*------- Request Queue Macros ---------*/
175 #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) \
176 (CN23XX_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET))
178 #define CN23XX_SLI_IQ_BASE_ADDR64(iq) \
179 (CN23XX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_IQ_OFFSET))
181 #define CN23XX_SLI_IQ_SIZE(iq) \
182 (CN23XX_SLI_IQ_SIZE_START + ((iq) * CN23XX_IQ_OFFSET))
184 #define CN23XX_SLI_IQ_DOORBELL(iq) \
185 (CN23XX_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_IQ_OFFSET))
187 #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) \
188 (CN23XX_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_IQ_OFFSET))
190 /*------------------ Masks ----------------*/
191 #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
192 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
193 /* Number of instructions to be read in one MAC read request.
194 * setting to Max value(4)
196 #define CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25)
197 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
198 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
199 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
200 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
201 #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8)
202 #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)
203 #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5)
204 #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4)
205 #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3)
206 #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2)
207 #define CN23XX_PKT_INPUT_CTL_GATHER_RO (1)
209 /** Rings per Virtual Function **/
210 #define CN23XX_PKT_INPUT_CTL_RPVF_MASK (0x3F)
211 #define CN23XX_PKT_INPUT_CTL_RPVF_POS (48)
212 /** These bits[47:44] select the Physical function number within the MAC */
213 #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK (0x7)
214 #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45)
215 /** These bits[43:32] select the function number within the PF */
216 #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK (0x1FFF)
217 #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS (32)
218 #define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK (0x3)
219 #define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29)
220 #define CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL)
221 #define CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32)
222 #define CN23XX_PKT_IN_DONE_CNT_MASK (0x00000000FFFFFFFFULL)
224 #ifdef __LITTLE_ENDIAN_BITFIELD
225 #define CN23XX_PKT_INPUT_CTL_MASK \
226 (CN23XX_PKT_INPUT_CTL_RDSIZE | \
227 CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \
228 CN23XX_PKT_INPUT_CTL_USE_CSR)
230 #define CN23XX_PKT_INPUT_CTL_MASK \
231 (CN23XX_PKT_INPUT_CTL_RDSIZE | \
232 CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \
233 CN23XX_PKT_INPUT_CTL_USE_CSR | \
234 CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP)
237 /** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */
238 #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
239 #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
241 /*############################ OUTPUT QUEUE #########################*/
243 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
244 #define CN23XX_SLI_OQ_PKT_CONTROL_START 0x10050
246 /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
247 #define CN23XX_SLI_OQ0_BUFF_INFO_SIZE 0x10060
249 /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
250 #define CN23XX_SLI_OQ_BASE_ADDR_START64 0x10070
252 /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
253 #define CN23XX_SLI_OQ_PKT_CREDITS_START 0x10080
255 /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
256 #define CN23XX_SLI_OQ_SIZE_START 0x10090
258 /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
259 #define CN23XX_SLI_OQ_PKT_SENT_START 0x100B0
261 /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */
262 #define CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 0x100A0
264 /* Each Output Queue register is at a 16-byte Offset in BAR0 */
265 #define CN23XX_OQ_OFFSET 0x20000
267 /* 1 (64-bit register) for Output Queue backpressure across all rings. */
268 #define CN23XX_SLI_OQ_WMARK 0x29180
270 /* Global pkt control register */
271 #define CN23XX_SLI_GBL_CONTROL 0x29210
273 /* Backpressure enable register for PF0 */
274 #define CN23XX_SLI_OUT_BP_EN_W1S 0x29260
276 /* Backpressure enable register for PF1 */
277 #define CN23XX_SLI_OUT_BP_EN2_W1S 0x29270
279 /* Backpressure disable register for PF0 */
280 #define CN23XX_SLI_OUT_BP_EN_W1C 0x29280
282 /* Backpressure disable register for PF1 */
283 #define CN23XX_SLI_OUT_BP_EN2_W1C 0x29290
285 /*------- Output Queue Macros ---------*/
287 #define CN23XX_SLI_OQ_PKT_CONTROL(oq) \
288 (CN23XX_SLI_OQ_PKT_CONTROL_START + ((oq) * CN23XX_OQ_OFFSET))
290 #define CN23XX_SLI_OQ_BASE_ADDR64(oq) \
291 (CN23XX_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN23XX_OQ_OFFSET))
293 #define CN23XX_SLI_OQ_SIZE(oq) \
294 (CN23XX_SLI_OQ_SIZE_START + ((oq) * CN23XX_OQ_OFFSET))
296 #define CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq) \
297 (CN23XX_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN23XX_OQ_OFFSET))
299 #define CN23XX_SLI_OQ_PKTS_SENT(oq) \
300 (CN23XX_SLI_OQ_PKT_SENT_START + ((oq) * CN23XX_OQ_OFFSET))
302 #define CN23XX_SLI_OQ_PKTS_CREDIT(oq) \
303 (CN23XX_SLI_OQ_PKT_CREDITS_START + ((oq) * CN23XX_OQ_OFFSET))
305 #define CN23XX_SLI_OQ_PKT_INT_LEVELS(oq) \
306 (CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \
307 ((oq) * CN23XX_OQ_OFFSET))
309 /*Macro's for accessing CNT and TIME separately from INT_LEVELS*/
310 #define CN23XX_SLI_OQ_PKT_INT_LEVELS_CNT(oq) \
311 (CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \
312 ((oq) * CN23XX_OQ_OFFSET))
314 #define CN23XX_SLI_OQ_PKT_INT_LEVELS_TIME(oq) \
315 (CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \
316 ((oq) * CN23XX_OQ_OFFSET) + 4)
318 /*------------------ Masks ----------------*/
319 #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13)
320 #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12)
321 #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11)
322 #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9)
323 #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8)
324 #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7)
325 #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6)
326 #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5)
327 #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3)
328 #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2)
329 #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1)
330 #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0)
332 /*######################### Mailbox Reg Macros ########################*/
333 #define CN23XX_SLI_PKT_MBOX_INT_START 0x10210
334 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START 0x10200
335 #define CN23XX_SLI_MAC_PF_MBOX_INT_START 0x27380
337 #define CN23XX_SLI_MBOX_OFFSET 0x20000
338 #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET 0x8
340 #define CN23XX_SLI_PKT_MBOX_INT(q) \
341 (CN23XX_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET))
343 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) \
344 (CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START + \
345 ((q) * CN23XX_SLI_MBOX_OFFSET + \
346 (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET))
348 #define CN23XX_SLI_MAC_PF_MBOX_INT(mac, pf) \
349 (CN23XX_SLI_MAC_PF_MBOX_INT_START + \
350 ((mac) * CN23XX_MAC_INT_OFFSET + \
351 (pf) * CN23XX_PF_INT_OFFSET))
353 /*######################### DMA Counters #########################*/
355 /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */
356 #define CN23XX_DMA_CNT_START 0x28400
358 /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values */
360 #define CN23XX_DMA_TIM_START 0x28420
362 /* 2 registers (64-bit) - DMA count & Time Interrupt threshold -
363 * SLI_DMA_0_INT_LEVEL
365 #define CN23XX_DMA_INT_LEVEL_START 0x283E0
367 /* Each DMA register is at a 16-byte Offset in BAR0 */
368 #define CN23XX_DMA_OFFSET 0x10
370 /*---------- DMA Counter Macros ---------*/
371 #define CN23XX_DMA_CNT(dq) \
372 (CN23XX_DMA_CNT_START + ((dq) * CN23XX_DMA_OFFSET))
374 #define CN23XX_DMA_INT_LEVEL(dq) \
375 (CN23XX_DMA_INT_LEVEL_START + ((dq) * CN23XX_DMA_OFFSET))
377 #define CN23XX_DMA_PKT_INT_LEVEL(dq) \
378 (CN23XX_DMA_INT_LEVEL_START + ((dq) * CN23XX_DMA_OFFSET))
380 #define CN23XX_DMA_TIME_INT_LEVEL(dq) \
381 (CN23XX_DMA_INT_LEVEL_START + 4 + ((dq) * CN23XX_DMA_OFFSET))
383 #define CN23XX_DMA_TIM(dq) \
384 (CN23XX_DMA_TIM_START + ((dq) * CN23XX_DMA_OFFSET))
386 /*######################## MSIX TABLE #########################*/
388 #define CN23XX_MSIX_TABLE_ADDR_START 0x0
389 #define CN23XX_MSIX_TABLE_DATA_START 0x8
391 #define CN23XX_MSIX_TABLE_SIZE 0x10
392 #define CN23XX_MSIX_TABLE_ENTRIES 0x41
394 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
396 #define CN23XX_MSIX_TABLE_ADDR(idx) \
397 (CN23XX_MSIX_TABLE_ADDR_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
399 #define CN23XX_MSIX_TABLE_DATA(idx) \
400 (CN23XX_MSIX_TABLE_DATA_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
402 /*######################## INTERRUPTS #########################*/
403 #define CN23XX_MAC_INT_OFFSET 0x20
404 #define CN23XX_PF_INT_OFFSET 0x10
406 /* 1 register (64-bit) for Interrupt Summary */
407 #define CN23XX_SLI_INT_SUM64 0x27000
409 /* 4 registers (64-bit) for Interrupt Enable for each Port */
410 #define CN23XX_SLI_INT_ENB64 0x27080
412 #define CN23XX_SLI_MAC_PF_INT_SUM64(mac, pf) \
413 (CN23XX_SLI_INT_SUM64 + \
414 ((mac) * CN23XX_MAC_INT_OFFSET) + \
415 ((pf) * CN23XX_PF_INT_OFFSET))
417 #define CN23XX_SLI_MAC_PF_INT_ENB64(mac, pf) \
418 (CN23XX_SLI_INT_ENB64 + \
419 ((mac) * CN23XX_MAC_INT_OFFSET) + \
420 ((pf) * CN23XX_PF_INT_OFFSET))
422 /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */
423 #define CN23XX_SLI_PKT_CNT_INT 0x29130
425 /* 1 register (64-bit) to indicate which Output Queue reached time threshold */
426 #define CN23XX_SLI_PKT_TIME_INT 0x29140
428 /*------------------ Interrupt Masks ----------------*/
430 #define CN23XX_INTR_PO_INT BIT_ULL(63)
431 #define CN23XX_INTR_PI_INT BIT_ULL(62)
432 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
433 #define CN23XX_INTR_RESEND BIT_ULL(60)
435 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
436 #define CN23XX_INTR_MBOX_ENB BIT(0)
438 #define CN23XX_INTR_RML_TIMEOUT_ERR (1)
440 #define CN23XX_INTR_MIO_INT BIT(1)
442 #define CN23XX_INTR_RESERVED1 (3 << 2)
444 #define CN23XX_INTR_PKT_COUNT BIT(4)
445 #define CN23XX_INTR_PKT_TIME BIT(5)
447 #define CN23XX_INTR_RESERVED2 (3 << 6)
449 #define CN23XX_INTR_M0UPB0_ERR BIT(8)
450 #define CN23XX_INTR_M0UPWI_ERR BIT(9)
451 #define CN23XX_INTR_M0UNB0_ERR BIT(10)
452 #define CN23XX_INTR_M0UNWI_ERR BIT(11)
454 #define CN23XX_INTR_RESERVED3 (0xFFFFFULL << 12)
456 #define CN23XX_INTR_DMA0_FORCE BIT_ULL(32)
457 #define CN23XX_INTR_DMA1_FORCE BIT_ULL(33)
459 #define CN23XX_INTR_DMA0_COUNT BIT_ULL(34)
460 #define CN23XX_INTR_DMA1_COUNT BIT_ULL(35)
462 #define CN23XX_INTR_DMA0_TIME BIT_ULL(36)
463 #define CN23XX_INTR_DMA1_TIME BIT_ULL(37)
465 #define CN23XX_INTR_RESERVED4 (0x7FFFFULL << 38)
467 #define CN23XX_INTR_VF_MBOX BIT_ULL(57)
468 #define CN23XX_INTR_DMAVF_ERR BIT_ULL(58)
469 #define CN23XX_INTR_DMAPF_ERR BIT_ULL(59)
471 #define CN23XX_INTR_PKTVF_ERR BIT_ULL(60)
472 #define CN23XX_INTR_PKTPF_ERR BIT_ULL(61)
473 #define CN23XX_INTR_PPVF_ERR BIT_ULL(62)
474 #define CN23XX_INTR_PPPF_ERR BIT_ULL(63)
476 #define CN23XX_INTR_DMA0_DATA (CN23XX_INTR_DMA0_TIME)
477 #define CN23XX_INTR_DMA1_DATA (CN23XX_INTR_DMA1_TIME)
479 #define CN23XX_INTR_DMA_DATA \
480 (CN23XX_INTR_DMA0_DATA | CN23XX_INTR_DMA1_DATA)
482 /* By fault only TIME based */
483 #define CN23XX_INTR_PKT_DATA (CN23XX_INTR_PKT_TIME)
484 /* For both COUNT and TIME based */
485 /* #define CN23XX_INTR_PKT_DATA \
486 * (CN23XX_INTR_PKT_COUNT | CN23XX_INTR_PKT_TIME)
489 /* Sum of interrupts for all PCI-Express Data Interrupts */
490 #define CN23XX_INTR_PCIE_DATA \
491 (CN23XX_INTR_DMA_DATA | CN23XX_INTR_PKT_DAT)
493 /* Sum of interrupts for error events */
494 #define CN23XX_INTR_ERR \
495 (CN23XX_INTR_M0UPB0_ERR | \
496 CN23XX_INTR_M0UPWI_ERR | \
497 CN23XX_INTR_M0UNB0_ERR | \
498 CN23XX_INTR_M0UNWI_ERR | \
499 CN23XX_INTR_DMAVF_ERR | \
500 CN23XX_INTR_DMAPF_ERR | \
501 CN23XX_INTR_PKTPF_ERR | \
502 CN23XX_INTR_PPPF_ERR | \
503 CN23XX_INTR_PPVF_ERR)
505 /* Programmed Mask for Interrupt Sum */
506 #define CN23XX_INTR_MASK \
507 (CN23XX_INTR_DMA_DATA | \
508 CN23XX_INTR_DMA0_FORCE | \
509 CN23XX_INTR_DMA1_FORCE | \
510 CN23XX_INTR_MIO_INT | \
513 /* 4 Registers (64 - bit) */
514 #define CN23XX_SLI_S2M_PORT_CTL_START 0x23D80
515 #define CN23XX_SLI_S2M_PORTX_CTL(port) \
516 (CN23XX_SLI_S2M_PORT_CTL_START + (port * 0x10))
518 #define CN23XX_SLI_MAC_NUMBER 0x20050
520 /** PEM(0..3)_BAR1_INDEX(0..15)address is defined as
521 * addr = (0x00011800C0000100 |port <<24 |idx <<3 )
522 * Here, port is PEM(0..3) & idx is INDEX(0..15)
524 #define CN23XX_PEM_BAR1_INDEX_START 0x00011800C0000100ULL
525 #define CN23XX_PEM_OFFSET 24
526 #define CN23XX_BAR1_INDEX_OFFSET 3
528 #define CN23XX_PEM_BAR1_INDEX_REG(port, idx) \
529 (CN23XX_PEM_BAR1_INDEX_START + (((u64)port) << CN23XX_PEM_OFFSET) + \
530 ((idx) << CN23XX_BAR1_INDEX_OFFSET))
532 /*############################ DPI #########################*/
534 /* 1 register (64-bit) - provides DMA Enable */
535 #define CN23XX_DPI_CTL 0x0001df0000000040ULL
537 /* 1 register (64-bit) - Controls the DMA IO Operation */
538 #define CN23XX_DPI_DMA_CONTROL 0x0001df0000000048ULL
540 /* 1 register (64-bit) - Provides DMA Instr'n Queue Enable */
541 #define CN23XX_DPI_REQ_GBL_ENB 0x0001df0000000050ULL
543 /* 1 register (64-bit) - DPI_REQ_ERR_RSP
544 * Indicates which Instr'n Queue received error response from the IO sub-system
546 #define CN23XX_DPI_REQ_ERR_RSP 0x0001df0000000058ULL
548 /* 1 register (64-bit) - DPI_REQ_ERR_RST
549 * Indicates which Instr'n Queue dropped an Instr'n
551 #define CN23XX_DPI_REQ_ERR_RST 0x0001df0000000060ULL
553 /* 6 register (64-bit) - DPI_DMA_ENG(0..5)_EN
554 * Provides DMA Engine Queue Enable
556 #define CN23XX_DPI_DMA_ENG0_ENB 0x0001df0000000080ULL
557 #define CN23XX_DPI_DMA_ENG_ENB(eng) (CN23XX_DPI_DMA_ENG0_ENB + (eng * 8))
559 /* 8 register (64-bit) - DPI_DMA(0..7)_REQQ_CTL
560 * Provides control bits for transaction on 8 Queues
562 #define CN23XX_DPI_DMA_REQQ0_CTL 0x0001df0000000180ULL
563 #define CN23XX_DPI_DMA_REQQ_CTL(q_no) \
564 (CN23XX_DPI_DMA_REQQ0_CTL + (q_no * 8))
566 /* 6 register (64-bit) - DPI_ENG(0..5)_BUF
567 * Provides DMA Engine FIFO (Queue) Size
569 #define CN23XX_DPI_DMA_ENG0_BUF 0x0001df0000000880ULL
570 #define CN23XX_DPI_DMA_ENG_BUF(eng) \
571 (CN23XX_DPI_DMA_ENG0_BUF + (eng * 8))
573 /* 4 Registers (64-bit) */
574 #define CN23XX_DPI_SLI_PRT_CFG_START 0x0001df0000000900ULL
575 #define CN23XX_DPI_SLI_PRTX_CFG(port) \
576 (CN23XX_DPI_SLI_PRT_CFG_START + (port * 0x8))
578 /* Masks for DPI_DMA_CONTROL Register */
579 #define CN23XX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
580 #define CN23XX_DPI_DMA_PKT_EN BIT_ULL(56)
581 #define CN23XX_DPI_DMA_ENB (0x0FULL << 48)
582 /* Set the DMA Control, to update packet count not byte count sent by DMA,
583 * when we use Interrupt Coalescing (CA mode)
585 #define CN23XX_DPI_DMA_O_ADD1 BIT(19)
586 /*selecting 64-bit Byte Swap Mode */
587 #define CN23XX_DPI_DMA_O_ES BIT(15)
588 #define CN23XX_DPI_DMA_O_MODE BIT(14)
590 #define CN23XX_DPI_DMA_CTL_MASK \
591 (CN23XX_DPI_DMA_COMMIT_MODE | \
592 CN23XX_DPI_DMA_PKT_EN | \
593 CN23XX_DPI_DMA_O_ES | \
594 CN23XX_DPI_DMA_O_MODE)
596 /*############################ RST #########################*/
598 #define CN23XX_RST_BOOT 0x0001180006001600ULL
599 #define CN23XX_RST_SOFT_RST 0x0001180006001680ULL
601 #define CN23XX_LMC0_RESET_CTL 0x0001180088000180ULL
602 #define CN23XX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL