2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
36 #include <linux/udp.h>
37 #include <linux/tcp.h>
40 #define MACB_RX_BUFFER_SIZE 128
41 #define RX_BUFFER_MULTIPLE 64 /* bytes */
43 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
44 #define MIN_RX_RING_SIZE 64
45 #define MAX_RX_RING_SIZE 8192
46 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
49 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
50 #define MIN_TX_RING_SIZE 64
51 #define MAX_TX_RING_SIZE 4096
52 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
55 /* level of occupied TX descriptors under which we wake up TX process */
56 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
58 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
60 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
63 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
66 /* Max length of transmit frame must be a multiple of 8 bytes */
67 #define MACB_TX_LEN_ALIGN 8
68 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
70 * false amba_error in TX path from the DMA assuming there is not enough
71 * space in the SRAM (16KB) even when there is.
73 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
75 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
76 #define MACB_NETIF_LSO NETIF_F_TSO
78 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
79 #define MACB_WOL_ENABLED (0x1 << 1)
81 /* Graceful stop timeouts in us. We should allow up to
82 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
84 #define MACB_HALT_TIMEOUT 1230
86 /* DMA buffer descriptor might be different size
87 * depends on hardware configuration:
89 * 1. dma address width 32 bits:
90 * word 1: 32 bit address of Data Buffer
93 * 2. dma address width 64 bits:
94 * word 1: 32 bit address of Data Buffer
96 * word 3: upper 32 bit address of Data Buffer
99 * 3. dma address width 32 bits with hardware timestamping:
100 * word 1: 32 bit address of Data Buffer
102 * word 3: timestamp word 1
103 * word 4: timestamp word 2
105 * 4. dma address width 64 bits with hardware timestamping:
106 * word 1: 32 bit address of Data Buffer
108 * word 3: upper 32 bit address of Data Buffer
110 * word 5: timestamp word 1
111 * word 6: timestamp word 2
113 static unsigned int macb_dma_desc_get_size(struct macb *bp)
116 unsigned int desc_size;
118 switch (bp->hw_dma_cap) {
120 desc_size = sizeof(struct macb_dma_desc)
121 + sizeof(struct macb_dma_desc_64);
124 desc_size = sizeof(struct macb_dma_desc)
125 + sizeof(struct macb_dma_desc_ptp);
127 case HW_DMA_CAP_64B_PTP:
128 desc_size = sizeof(struct macb_dma_desc)
129 + sizeof(struct macb_dma_desc_64)
130 + sizeof(struct macb_dma_desc_ptp);
133 desc_size = sizeof(struct macb_dma_desc);
137 return sizeof(struct macb_dma_desc);
140 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
143 switch (bp->hw_dma_cap) {
148 case HW_DMA_CAP_64B_PTP:
158 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
159 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
161 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
162 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
167 /* Ring buffer accessors */
168 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
170 return index & (bp->tx_ring_size - 1);
173 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
176 index = macb_tx_ring_wrap(queue->bp, index);
177 index = macb_adj_dma_desc_idx(queue->bp, index);
178 return &queue->tx_ring[index];
181 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
184 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
187 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
191 offset = macb_tx_ring_wrap(queue->bp, index) *
192 macb_dma_desc_get_size(queue->bp);
194 return queue->tx_ring_dma + offset;
197 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
199 return index & (bp->rx_ring_size - 1);
202 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
204 index = macb_rx_ring_wrap(bp, index);
205 index = macb_adj_dma_desc_idx(bp, index);
206 return &bp->rx_ring[index];
209 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
211 return bp->rx_buffers + bp->rx_buffer_size *
212 macb_rx_ring_wrap(bp, index);
216 static u32 hw_readl_native(struct macb *bp, int offset)
218 return __raw_readl(bp->regs + offset);
221 static void hw_writel_native(struct macb *bp, int offset, u32 value)
223 __raw_writel(value, bp->regs + offset);
226 static u32 hw_readl(struct macb *bp, int offset)
228 return readl_relaxed(bp->regs + offset);
231 static void hw_writel(struct macb *bp, int offset, u32 value)
233 writel_relaxed(value, bp->regs + offset);
236 /* Find the CPU endianness by using the loopback bit of NCR register. When the
237 * CPU is in big endian we need to program swapped mode for management
240 static bool hw_is_native_io(void __iomem *addr)
242 u32 value = MACB_BIT(LLB);
244 __raw_writel(value, addr + MACB_NCR);
245 value = __raw_readl(addr + MACB_NCR);
247 /* Write 0 back to disable everything */
248 __raw_writel(0, addr + MACB_NCR);
250 return value == MACB_BIT(LLB);
253 static bool hw_is_gem(void __iomem *addr, bool native_io)
258 id = __raw_readl(addr + MACB_MID);
260 id = readl_relaxed(addr + MACB_MID);
262 return MACB_BFEXT(IDNUM, id) >= 0x2;
265 static void macb_set_hwaddr(struct macb *bp)
270 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
271 macb_or_gem_writel(bp, SA1B, bottom);
272 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
273 macb_or_gem_writel(bp, SA1T, top);
275 /* Clear unused address register sets */
276 macb_or_gem_writel(bp, SA2B, 0);
277 macb_or_gem_writel(bp, SA2T, 0);
278 macb_or_gem_writel(bp, SA3B, 0);
279 macb_or_gem_writel(bp, SA3T, 0);
280 macb_or_gem_writel(bp, SA4B, 0);
281 macb_or_gem_writel(bp, SA4T, 0);
284 static void macb_get_hwaddr(struct macb *bp)
286 struct macb_platform_data *pdata;
292 pdata = dev_get_platdata(&bp->pdev->dev);
294 /* Check all 4 address register for valid address */
295 for (i = 0; i < 4; i++) {
296 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
297 top = macb_or_gem_readl(bp, SA1T + i * 8);
299 if (pdata && pdata->rev_eth_addr) {
300 addr[5] = bottom & 0xff;
301 addr[4] = (bottom >> 8) & 0xff;
302 addr[3] = (bottom >> 16) & 0xff;
303 addr[2] = (bottom >> 24) & 0xff;
304 addr[1] = top & 0xff;
305 addr[0] = (top & 0xff00) >> 8;
307 addr[0] = bottom & 0xff;
308 addr[1] = (bottom >> 8) & 0xff;
309 addr[2] = (bottom >> 16) & 0xff;
310 addr[3] = (bottom >> 24) & 0xff;
311 addr[4] = top & 0xff;
312 addr[5] = (top >> 8) & 0xff;
315 if (is_valid_ether_addr(addr)) {
316 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
321 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
322 eth_hw_addr_random(bp->dev);
325 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
327 struct macb *bp = bus->priv;
330 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
331 | MACB_BF(RW, MACB_MAN_READ)
332 | MACB_BF(PHYA, mii_id)
333 | MACB_BF(REGA, regnum)
334 | MACB_BF(CODE, MACB_MAN_CODE)));
336 /* wait for end of transfer */
337 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
340 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
345 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
348 struct macb *bp = bus->priv;
350 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
351 | MACB_BF(RW, MACB_MAN_WRITE)
352 | MACB_BF(PHYA, mii_id)
353 | MACB_BF(REGA, regnum)
354 | MACB_BF(CODE, MACB_MAN_CODE)
355 | MACB_BF(DATA, value)));
357 /* wait for end of transfer */
358 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
365 * macb_set_tx_clk() - Set a clock to a new frequency
366 * @clk Pointer to the clock to change
367 * @rate New frequency in Hz
368 * @dev Pointer to the struct net_device
370 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
372 long ferr, rate, rate_rounded;
391 rate_rounded = clk_round_rate(clk, rate);
392 if (rate_rounded < 0)
395 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
398 ferr = abs(rate_rounded - rate);
399 ferr = DIV_ROUND_UP(ferr, rate / 100000);
401 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
404 if (clk_set_rate(clk, rate_rounded))
405 netdev_err(dev, "adjusting tx_clk failed.\n");
408 static void macb_handle_link_change(struct net_device *dev)
410 struct macb *bp = netdev_priv(dev);
411 struct phy_device *phydev = dev->phydev;
413 int status_change = 0;
415 spin_lock_irqsave(&bp->lock, flags);
418 if ((bp->speed != phydev->speed) ||
419 (bp->duplex != phydev->duplex)) {
422 reg = macb_readl(bp, NCFGR);
423 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
425 reg &= ~GEM_BIT(GBE);
429 if (phydev->speed == SPEED_100)
430 reg |= MACB_BIT(SPD);
431 if (phydev->speed == SPEED_1000 &&
432 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
435 macb_or_gem_writel(bp, NCFGR, reg);
437 bp->speed = phydev->speed;
438 bp->duplex = phydev->duplex;
443 if (phydev->link != bp->link) {
448 bp->link = phydev->link;
453 spin_unlock_irqrestore(&bp->lock, flags);
457 /* Update the TX clock rate if and only if the link is
458 * up and there has been a link change.
460 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
462 netif_carrier_on(dev);
463 netdev_info(dev, "link up (%d/%s)\n",
465 phydev->duplex == DUPLEX_FULL ?
468 netif_carrier_off(dev);
469 netdev_info(dev, "link down\n");
474 /* based on au1000_eth. c*/
475 static int macb_mii_probe(struct net_device *dev)
477 struct macb *bp = netdev_priv(dev);
478 struct macb_platform_data *pdata;
479 struct phy_device *phydev;
484 phydev = of_phy_connect(dev, bp->phy_node,
485 &macb_handle_link_change, 0,
490 phydev = phy_find_first(bp->mii_bus);
492 netdev_err(dev, "no PHY found\n");
496 pdata = dev_get_platdata(&bp->pdev->dev);
498 if (gpio_is_valid(pdata->phy_irq_pin)) {
499 ret = devm_gpio_request(&bp->pdev->dev,
500 pdata->phy_irq_pin, "phy int");
502 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
503 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
506 phydev->irq = PHY_POLL;
510 /* attach the mac to the phy */
511 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
514 netdev_err(dev, "Could not attach to PHY\n");
519 /* mask with MAC supported features */
520 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
521 phydev->supported &= PHY_GBIT_FEATURES;
523 phydev->supported &= PHY_BASIC_FEATURES;
525 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
526 phydev->supported &= ~SUPPORTED_1000baseT_Half;
528 phydev->advertising = phydev->supported;
537 static int macb_mii_init(struct macb *bp)
539 struct macb_platform_data *pdata;
540 struct device_node *np;
543 /* Enable management port */
544 macb_writel(bp, NCR, MACB_BIT(MPE));
546 bp->mii_bus = mdiobus_alloc();
552 bp->mii_bus->name = "MACB_mii_bus";
553 bp->mii_bus->read = &macb_mdio_read;
554 bp->mii_bus->write = &macb_mdio_write;
555 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
556 bp->pdev->name, bp->pdev->id);
557 bp->mii_bus->priv = bp;
558 bp->mii_bus->parent = &bp->pdev->dev;
559 pdata = dev_get_platdata(&bp->pdev->dev);
561 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
563 np = bp->pdev->dev.of_node;
565 if (of_phy_is_fixed_link(np)) {
566 if (of_phy_register_fixed_link(np) < 0) {
567 dev_err(&bp->pdev->dev,
568 "broken fixed-link specification\n");
569 goto err_out_unregister_bus;
571 bp->phy_node = of_node_get(np);
573 err = mdiobus_register(bp->mii_bus);
575 /* try dt phy registration */
576 err = of_mdiobus_register(bp->mii_bus, np);
578 /* fallback to standard phy registration if no phy were
579 * found during dt phy registration
581 if (!err && !phy_find_first(bp->mii_bus)) {
582 for (i = 0; i < PHY_MAX_ADDR; i++) {
583 struct phy_device *phydev;
585 phydev = mdiobus_scan(bp->mii_bus, i);
586 if (IS_ERR(phydev) &&
587 PTR_ERR(phydev) != -ENODEV) {
588 err = PTR_ERR(phydev);
594 goto err_out_unregister_bus;
598 for (i = 0; i < PHY_MAX_ADDR; i++)
599 bp->mii_bus->irq[i] = PHY_POLL;
602 bp->mii_bus->phy_mask = pdata->phy_mask;
604 err = mdiobus_register(bp->mii_bus);
608 goto err_out_free_mdiobus;
610 err = macb_mii_probe(bp->dev);
612 goto err_out_unregister_bus;
616 err_out_unregister_bus:
617 mdiobus_unregister(bp->mii_bus);
618 err_out_free_mdiobus:
619 mdiobus_free(bp->mii_bus);
624 static void macb_update_stats(struct macb *bp)
626 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
627 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
628 int offset = MACB_PFR;
630 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
632 for (; p < end; p++, offset += 4)
633 *p += bp->macb_reg_readl(bp, offset);
636 static int macb_halt_tx(struct macb *bp)
638 unsigned long halt_time, timeout;
641 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
643 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
646 status = macb_readl(bp, TSR);
647 if (!(status & MACB_BIT(TGO)))
651 } while (time_before(halt_time, timeout));
656 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
658 if (tx_skb->mapping) {
659 if (tx_skb->mapped_as_page)
660 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
661 tx_skb->size, DMA_TO_DEVICE);
663 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
664 tx_skb->size, DMA_TO_DEVICE);
669 dev_kfree_skb_any(tx_skb->skb);
674 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
676 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
677 struct macb_dma_desc_64 *desc_64;
679 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
680 desc_64 = macb_64b_desc(bp, desc);
681 desc_64->addrh = upper_32_bits(addr);
682 /* The low bits of RX address contain the RX_USED bit, clearing
683 * of which allows packet RX. Make sure the high bits are also
684 * visible to HW at that point.
689 desc->addr = lower_32_bits(addr);
692 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
695 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
696 struct macb_dma_desc_64 *desc_64;
698 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
699 desc_64 = macb_64b_desc(bp, desc);
700 addr = ((u64)(desc_64->addrh) << 32);
703 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
707 static void macb_tx_error_task(struct work_struct *work)
709 struct macb_queue *queue = container_of(work, struct macb_queue,
711 struct macb *bp = queue->bp;
712 struct macb_tx_skb *tx_skb;
713 struct macb_dma_desc *desc;
718 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
719 (unsigned int)(queue - bp->queues),
720 queue->tx_tail, queue->tx_head);
722 /* Prevent the queue IRQ handlers from running: each of them may call
723 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
724 * As explained below, we have to halt the transmission before updating
725 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
726 * network engine about the macb/gem being halted.
728 spin_lock_irqsave(&bp->lock, flags);
730 /* Make sure nobody is trying to queue up new packets */
731 netif_tx_stop_all_queues(bp->dev);
733 /* Stop transmission now
734 * (in case we have just queued new packets)
735 * macb/gem must be halted to write TBQP register
737 if (macb_halt_tx(bp))
738 /* Just complain for now, reinitializing TX path can be good */
739 netdev_err(bp->dev, "BUG: halt tx timed out\n");
741 /* Treat frames in TX queue including the ones that caused the error.
742 * Free transmit buffers in upper layer.
744 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
747 desc = macb_tx_desc(queue, tail);
749 tx_skb = macb_tx_skb(queue, tail);
752 if (ctrl & MACB_BIT(TX_USED)) {
753 /* skb is set for the last buffer of the frame */
755 macb_tx_unmap(bp, tx_skb);
757 tx_skb = macb_tx_skb(queue, tail);
761 /* ctrl still refers to the first buffer descriptor
762 * since it's the only one written back by the hardware
764 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
765 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
766 macb_tx_ring_wrap(bp, tail),
768 bp->dev->stats.tx_packets++;
769 bp->dev->stats.tx_bytes += skb->len;
772 /* "Buffers exhausted mid-frame" errors may only happen
773 * if the driver is buggy, so complain loudly about
774 * those. Statistics are updated by hardware.
776 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
778 "BUG: TX buffers exhausted mid-frame\n");
780 desc->ctrl = ctrl | MACB_BIT(TX_USED);
783 macb_tx_unmap(bp, tx_skb);
786 /* Set end of TX queue */
787 desc = macb_tx_desc(queue, 0);
788 macb_set_addr(bp, desc, 0);
789 desc->ctrl = MACB_BIT(TX_USED);
791 /* Make descriptor updates visible to hardware */
794 /* Reinitialize the TX desc queue */
795 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
796 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
797 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
798 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
800 /* Make TX ring reflect state of hardware */
804 /* Housework before enabling TX IRQ */
805 macb_writel(bp, TSR, macb_readl(bp, TSR));
806 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
808 /* Now we are ready to start transmission again */
809 netif_tx_start_all_queues(bp->dev);
810 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
812 spin_unlock_irqrestore(&bp->lock, flags);
815 static void macb_tx_interrupt(struct macb_queue *queue)
820 struct macb *bp = queue->bp;
821 u16 queue_index = queue - bp->queues;
823 status = macb_readl(bp, TSR);
824 macb_writel(bp, TSR, status);
826 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
827 queue_writel(queue, ISR, MACB_BIT(TCOMP));
829 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
830 (unsigned long)status);
832 head = queue->tx_head;
833 for (tail = queue->tx_tail; tail != head; tail++) {
834 struct macb_tx_skb *tx_skb;
836 struct macb_dma_desc *desc;
839 desc = macb_tx_desc(queue, tail);
841 /* Make hw descriptor updates visible to CPU */
846 /* TX_USED bit is only set by hardware on the very first buffer
847 * descriptor of the transmitted frame.
849 if (!(ctrl & MACB_BIT(TX_USED)))
852 /* Process all buffers of the current transmitted frame */
854 tx_skb = macb_tx_skb(queue, tail);
857 /* First, update TX stats if needed */
859 if (unlikely(skb_shinfo(skb)->tx_flags &
861 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
862 /* skb now belongs to timestamp buffer
863 * and will be removed later
867 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
868 macb_tx_ring_wrap(bp, tail),
870 bp->dev->stats.tx_packets++;
871 bp->dev->stats.tx_bytes += skb->len;
874 /* Now we can safely release resources */
875 macb_tx_unmap(bp, tx_skb);
877 /* skb is set only for the last buffer of the frame.
878 * WARNING: at this point skb has been freed by
886 queue->tx_tail = tail;
887 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
888 CIRC_CNT(queue->tx_head, queue->tx_tail,
889 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
890 netif_wake_subqueue(bp->dev, queue_index);
893 static void gem_rx_refill(struct macb *bp)
898 struct macb_dma_desc *desc;
900 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
901 bp->rx_ring_size) > 0) {
902 entry = macb_rx_ring_wrap(bp, bp->rx_prepared_head);
904 /* Make hw descriptor updates visible to CPU */
907 bp->rx_prepared_head++;
908 desc = macb_rx_desc(bp, entry);
910 if (!bp->rx_skbuff[entry]) {
911 /* allocate sk_buff for this free entry in ring */
912 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
913 if (unlikely(!skb)) {
915 "Unable to allocate sk_buff\n");
919 /* now fill corresponding descriptor entry */
920 paddr = dma_map_single(&bp->pdev->dev, skb->data,
923 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
928 bp->rx_skbuff[entry] = skb;
930 if (entry == bp->rx_ring_size - 1)
931 paddr |= MACB_BIT(RX_WRAP);
933 /* Setting addr clears RX_USED and allows reception,
934 * make sure ctrl is cleared first to avoid a race.
937 macb_set_addr(bp, desc, paddr);
939 /* properly align Ethernet header */
940 skb_reserve(skb, NET_IP_ALIGN);
944 desc->addr &= ~MACB_BIT(RX_USED);
948 /* Make descriptor updates visible to hardware */
951 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
952 bp->rx_prepared_head, bp->rx_tail);
955 /* Mark DMA descriptors from begin up to and not including end as unused */
956 static void discard_partial_frame(struct macb *bp, unsigned int begin,
961 for (frag = begin; frag != end; frag++) {
962 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
964 desc->addr &= ~MACB_BIT(RX_USED);
967 /* Make descriptor updates visible to hardware */
970 /* When this happens, the hardware stats registers for
971 * whatever caused this is updated, so we don't have to record
976 static int gem_rx(struct macb *bp, int budget)
981 struct macb_dma_desc *desc;
984 while (count < budget) {
989 entry = macb_rx_ring_wrap(bp, bp->rx_tail);
990 desc = macb_rx_desc(bp, entry);
992 /* Make hw descriptor updates visible to CPU */
995 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
996 addr = macb_get_addr(bp, desc);
1005 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1007 "not whole frame pointed by descriptor\n");
1008 bp->dev->stats.rx_dropped++;
1011 skb = bp->rx_skbuff[entry];
1012 if (unlikely(!skb)) {
1014 "inconsistent Rx descriptor chain\n");
1015 bp->dev->stats.rx_dropped++;
1018 /* now everything is ready for receiving packet */
1019 bp->rx_skbuff[entry] = NULL;
1020 len = ctrl & bp->rx_frm_len_mask;
1022 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1025 dma_unmap_single(&bp->pdev->dev, addr,
1026 bp->rx_buffer_size, DMA_FROM_DEVICE);
1028 skb->protocol = eth_type_trans(skb, bp->dev);
1029 skb_checksum_none_assert(skb);
1030 if (bp->dev->features & NETIF_F_RXCSUM &&
1031 !(bp->dev->flags & IFF_PROMISC) &&
1032 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1033 skb->ip_summed = CHECKSUM_UNNECESSARY;
1035 bp->dev->stats.rx_packets++;
1036 bp->dev->stats.rx_bytes += skb->len;
1038 gem_ptp_do_rxstamp(bp, skb, desc);
1040 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1041 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1042 skb->len, skb->csum);
1043 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1044 skb_mac_header(skb), 16, true);
1045 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1046 skb->data, 32, true);
1049 netif_receive_skb(skb);
1057 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
1058 unsigned int last_frag)
1062 unsigned int offset;
1063 struct sk_buff *skb;
1064 struct macb_dma_desc *desc;
1066 desc = macb_rx_desc(bp, last_frag);
1067 len = desc->ctrl & bp->rx_frm_len_mask;
1069 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1070 macb_rx_ring_wrap(bp, first_frag),
1071 macb_rx_ring_wrap(bp, last_frag), len);
1073 /* The ethernet header starts NET_IP_ALIGN bytes into the
1074 * first buffer. Since the header is 14 bytes, this makes the
1075 * payload word-aligned.
1077 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1078 * the two padding bytes into the skb so that we avoid hitting
1079 * the slowpath in memcpy(), and pull them off afterwards.
1081 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1083 bp->dev->stats.rx_dropped++;
1084 for (frag = first_frag; ; frag++) {
1085 desc = macb_rx_desc(bp, frag);
1086 desc->addr &= ~MACB_BIT(RX_USED);
1087 if (frag == last_frag)
1091 /* Make descriptor updates visible to hardware */
1098 len += NET_IP_ALIGN;
1099 skb_checksum_none_assert(skb);
1102 for (frag = first_frag; ; frag++) {
1103 unsigned int frag_len = bp->rx_buffer_size;
1105 if (offset + frag_len > len) {
1106 if (unlikely(frag != last_frag)) {
1107 dev_kfree_skb_any(skb);
1110 frag_len = len - offset;
1112 skb_copy_to_linear_data_offset(skb, offset,
1113 macb_rx_buffer(bp, frag),
1115 offset += bp->rx_buffer_size;
1116 desc = macb_rx_desc(bp, frag);
1117 desc->addr &= ~MACB_BIT(RX_USED);
1119 if (frag == last_frag)
1123 /* Make descriptor updates visible to hardware */
1126 __skb_pull(skb, NET_IP_ALIGN);
1127 skb->protocol = eth_type_trans(skb, bp->dev);
1129 bp->dev->stats.rx_packets++;
1130 bp->dev->stats.rx_bytes += skb->len;
1131 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1132 skb->len, skb->csum);
1133 netif_receive_skb(skb);
1138 static inline void macb_init_rx_ring(struct macb *bp)
1141 struct macb_dma_desc *desc = NULL;
1144 addr = bp->rx_buffers_dma;
1145 for (i = 0; i < bp->rx_ring_size; i++) {
1146 desc = macb_rx_desc(bp, i);
1147 macb_set_addr(bp, desc, addr);
1149 addr += bp->rx_buffer_size;
1151 desc->addr |= MACB_BIT(RX_WRAP);
1155 static int macb_rx(struct macb *bp, int budget)
1157 bool reset_rx_queue = false;
1160 int first_frag = -1;
1162 for (tail = bp->rx_tail; budget > 0; tail++) {
1163 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
1166 /* Make hw descriptor updates visible to CPU */
1171 if (!(desc->addr & MACB_BIT(RX_USED)))
1174 if (ctrl & MACB_BIT(RX_SOF)) {
1175 if (first_frag != -1)
1176 discard_partial_frame(bp, first_frag, tail);
1180 if (ctrl & MACB_BIT(RX_EOF)) {
1183 if (unlikely(first_frag == -1)) {
1184 reset_rx_queue = true;
1188 dropped = macb_rx_frame(bp, first_frag, tail);
1190 if (unlikely(dropped < 0)) {
1191 reset_rx_queue = true;
1201 if (unlikely(reset_rx_queue)) {
1202 unsigned long flags;
1205 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1207 spin_lock_irqsave(&bp->lock, flags);
1209 ctrl = macb_readl(bp, NCR);
1210 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1212 macb_init_rx_ring(bp);
1213 macb_writel(bp, RBQP, bp->rx_ring_dma);
1215 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1217 spin_unlock_irqrestore(&bp->lock, flags);
1221 if (first_frag != -1)
1222 bp->rx_tail = first_frag;
1229 static int macb_poll(struct napi_struct *napi, int budget)
1231 struct macb *bp = container_of(napi, struct macb, napi);
1235 status = macb_readl(bp, RSR);
1236 macb_writel(bp, RSR, status);
1240 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1241 (unsigned long)status, budget);
1243 work_done = bp->macbgem_ops.mog_rx(bp, budget);
1244 if (work_done < budget) {
1245 napi_complete_done(napi, work_done);
1247 /* Packets received while interrupts were disabled */
1248 status = macb_readl(bp, RSR);
1250 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1251 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1252 napi_reschedule(napi);
1254 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1258 /* TODO: Handle errors */
1263 static void macb_tx_restart(struct macb_queue *queue)
1265 unsigned int head = queue->tx_head;
1266 unsigned int tail = queue->tx_tail;
1267 struct macb *bp = queue->bp;
1269 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1270 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1275 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1278 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1280 struct macb_queue *queue = dev_id;
1281 struct macb *bp = queue->bp;
1282 struct net_device *dev = bp->dev;
1285 status = queue_readl(queue, ISR);
1287 if (unlikely(!status))
1290 spin_lock(&bp->lock);
1293 /* close possible race with dev_close */
1294 if (unlikely(!netif_running(dev))) {
1295 queue_writel(queue, IDR, -1);
1296 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1297 queue_writel(queue, ISR, -1);
1301 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1302 (unsigned int)(queue - bp->queues),
1303 (unsigned long)status);
1305 if (status & MACB_RX_INT_FLAGS) {
1306 /* There's no point taking any more interrupts
1307 * until we have processed the buffers. The
1308 * scheduling call may fail if the poll routine
1309 * is already scheduled, so disable interrupts
1312 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1313 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1314 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1316 if (napi_schedule_prep(&bp->napi)) {
1317 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1318 __napi_schedule(&bp->napi);
1322 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1323 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1324 schedule_work(&queue->tx_error_task);
1326 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1327 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1332 if (status & MACB_BIT(TCOMP))
1333 macb_tx_interrupt(queue);
1335 if (status & MACB_BIT(TXUBR))
1336 macb_tx_restart(queue);
1338 /* Link change detection isn't possible with RMII, so we'll
1339 * add that if/when we get our hands on a full-blown MII PHY.
1342 /* There is a hardware issue under heavy load where DMA can
1343 * stop, this causes endless "used buffer descriptor read"
1344 * interrupts but it can be cleared by re-enabling RX. See
1345 * the at91 manual, section 41.3.1 or the Zynq manual
1346 * section 16.7.4 for details.
1348 if (status & MACB_BIT(RXUBR)) {
1349 ctrl = macb_readl(bp, NCR);
1350 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1352 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1354 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1355 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1358 if (status & MACB_BIT(ISR_ROVR)) {
1359 /* We missed at least one packet */
1360 if (macb_is_gem(bp))
1361 bp->hw_stats.gem.rx_overruns++;
1363 bp->hw_stats.macb.rx_overruns++;
1365 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1366 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1369 if (status & MACB_BIT(HRESP)) {
1370 /* TODO: Reset the hardware, and maybe move the
1371 * netdev_err to a lower-priority context as well
1374 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1376 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1377 queue_writel(queue, ISR, MACB_BIT(HRESP));
1379 status = queue_readl(queue, ISR);
1382 spin_unlock(&bp->lock);
1387 #ifdef CONFIG_NET_POLL_CONTROLLER
1388 /* Polling receive - used by netconsole and other diagnostic tools
1389 * to allow network i/o with interrupts disabled.
1391 static void macb_poll_controller(struct net_device *dev)
1393 struct macb *bp = netdev_priv(dev);
1394 struct macb_queue *queue;
1395 unsigned long flags;
1398 local_irq_save(flags);
1399 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1400 macb_interrupt(dev->irq, queue);
1401 local_irq_restore(flags);
1405 static unsigned int macb_tx_map(struct macb *bp,
1406 struct macb_queue *queue,
1407 struct sk_buff *skb,
1408 unsigned int hdrlen)
1411 unsigned int len, entry, i, tx_head = queue->tx_head;
1412 struct macb_tx_skb *tx_skb = NULL;
1413 struct macb_dma_desc *desc;
1414 unsigned int offset, size, count = 0;
1415 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1416 unsigned int eof = 1, mss_mfs = 0;
1417 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1420 if (skb_shinfo(skb)->gso_size != 0) {
1421 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1423 lso_ctrl = MACB_LSO_UFO_ENABLE;
1426 lso_ctrl = MACB_LSO_TSO_ENABLE;
1429 /* First, map non-paged data */
1430 len = skb_headlen(skb);
1432 /* first buffer length */
1437 entry = macb_tx_ring_wrap(bp, tx_head);
1438 tx_skb = &queue->tx_skb[entry];
1440 mapping = dma_map_single(&bp->pdev->dev,
1442 size, DMA_TO_DEVICE);
1443 if (dma_mapping_error(&bp->pdev->dev, mapping))
1446 /* Save info to properly release resources */
1448 tx_skb->mapping = mapping;
1449 tx_skb->size = size;
1450 tx_skb->mapped_as_page = false;
1457 size = min(len, bp->max_tx_length);
1460 /* Then, map paged data from fragments */
1461 for (f = 0; f < nr_frags; f++) {
1462 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1464 len = skb_frag_size(frag);
1467 size = min(len, bp->max_tx_length);
1468 entry = macb_tx_ring_wrap(bp, tx_head);
1469 tx_skb = &queue->tx_skb[entry];
1471 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1472 offset, size, DMA_TO_DEVICE);
1473 if (dma_mapping_error(&bp->pdev->dev, mapping))
1476 /* Save info to properly release resources */
1478 tx_skb->mapping = mapping;
1479 tx_skb->size = size;
1480 tx_skb->mapped_as_page = true;
1489 /* Should never happen */
1490 if (unlikely(!tx_skb)) {
1491 netdev_err(bp->dev, "BUG! empty skb!\n");
1495 /* This is the last buffer of the frame: save socket buffer */
1498 /* Update TX ring: update buffer descriptors in reverse order
1499 * to avoid race condition
1502 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1503 * to set the end of TX queue
1506 entry = macb_tx_ring_wrap(bp, i);
1507 ctrl = MACB_BIT(TX_USED);
1508 desc = macb_tx_desc(queue, entry);
1512 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1513 /* include header and FCS in value given to h/w */
1514 mss_mfs = skb_shinfo(skb)->gso_size +
1515 skb_transport_offset(skb) +
1518 mss_mfs = skb_shinfo(skb)->gso_size;
1519 /* TCP Sequence Number Source Select
1520 * can be set only for TSO
1528 entry = macb_tx_ring_wrap(bp, i);
1529 tx_skb = &queue->tx_skb[entry];
1530 desc = macb_tx_desc(queue, entry);
1532 ctrl = (u32)tx_skb->size;
1534 ctrl |= MACB_BIT(TX_LAST);
1537 if (unlikely(entry == (bp->tx_ring_size - 1)))
1538 ctrl |= MACB_BIT(TX_WRAP);
1540 /* First descriptor is header descriptor */
1541 if (i == queue->tx_head) {
1542 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1543 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1545 /* Only set MSS/MFS on payload descriptors
1546 * (second or later descriptor)
1548 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1550 /* Set TX buffer descriptor */
1551 macb_set_addr(bp, desc, tx_skb->mapping);
1552 /* desc->addr must be visible to hardware before clearing
1553 * 'TX_USED' bit in desc->ctrl.
1557 } while (i != queue->tx_head);
1559 queue->tx_head = tx_head;
1564 netdev_err(bp->dev, "TX DMA map failed\n");
1566 for (i = queue->tx_head; i != tx_head; i++) {
1567 tx_skb = macb_tx_skb(queue, i);
1569 macb_tx_unmap(bp, tx_skb);
1575 static netdev_features_t macb_features_check(struct sk_buff *skb,
1576 struct net_device *dev,
1577 netdev_features_t features)
1579 unsigned int nr_frags, f;
1580 unsigned int hdrlen;
1582 /* Validate LSO compatibility */
1584 /* there is only one buffer or protocol is not UDP */
1585 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1588 /* length of header */
1589 hdrlen = skb_transport_offset(skb);
1592 * When software supplies two or more payload buffers all payload buffers
1593 * apart from the last must be a multiple of 8 bytes in size.
1595 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1596 return features & ~MACB_NETIF_LSO;
1598 nr_frags = skb_shinfo(skb)->nr_frags;
1599 /* No need to check last fragment */
1601 for (f = 0; f < nr_frags; f++) {
1602 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1604 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1605 return features & ~MACB_NETIF_LSO;
1610 static inline int macb_clear_csum(struct sk_buff *skb)
1612 /* no change for packets without checksum offloading */
1613 if (skb->ip_summed != CHECKSUM_PARTIAL)
1616 /* make sure we can modify the header */
1617 if (unlikely(skb_cow_head(skb, 0)))
1620 /* initialize checksum field
1621 * This is required - at least for Zynq, which otherwise calculates
1622 * wrong UDP header checksums for UDP packets with UDP data len <=2
1624 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1628 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1630 u16 queue_index = skb_get_queue_mapping(skb);
1631 struct macb *bp = netdev_priv(dev);
1632 struct macb_queue *queue = &bp->queues[queue_index];
1633 unsigned long flags;
1634 unsigned int desc_cnt, nr_frags, frag_size, f;
1635 unsigned int hdrlen;
1636 bool is_lso, is_udp = 0;
1638 is_lso = (skb_shinfo(skb)->gso_size != 0);
1641 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1643 /* length of headers */
1645 /* only queue eth + ip headers separately for UDP */
1646 hdrlen = skb_transport_offset(skb);
1648 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1649 if (skb_headlen(skb) < hdrlen) {
1650 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1651 /* if this is required, would need to copy to single buffer */
1652 return NETDEV_TX_BUSY;
1655 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1657 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1658 netdev_vdbg(bp->dev,
1659 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1660 queue_index, skb->len, skb->head, skb->data,
1661 skb_tail_pointer(skb), skb_end_pointer(skb));
1662 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1663 skb->data, 16, true);
1666 /* Count how many TX buffer descriptors are needed to send this
1667 * socket buffer: skb fragments of jumbo frames may need to be
1668 * split into many buffer descriptors.
1670 if (is_lso && (skb_headlen(skb) > hdrlen))
1671 /* extra header descriptor if also payload in first buffer */
1672 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1674 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1675 nr_frags = skb_shinfo(skb)->nr_frags;
1676 for (f = 0; f < nr_frags; f++) {
1677 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1678 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1681 spin_lock_irqsave(&bp->lock, flags);
1683 /* This is a hard error, log it. */
1684 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1685 bp->tx_ring_size) < desc_cnt) {
1686 netif_stop_subqueue(dev, queue_index);
1687 spin_unlock_irqrestore(&bp->lock, flags);
1688 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1689 queue->tx_head, queue->tx_tail);
1690 return NETDEV_TX_BUSY;
1693 if (macb_clear_csum(skb)) {
1694 dev_kfree_skb_any(skb);
1698 /* Map socket buffer for DMA transfer */
1699 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1700 dev_kfree_skb_any(skb);
1704 /* Make newly initialized descriptor visible to hardware */
1706 skb_tx_timestamp(skb);
1708 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1710 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1711 netif_stop_subqueue(dev, queue_index);
1714 spin_unlock_irqrestore(&bp->lock, flags);
1716 return NETDEV_TX_OK;
1719 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1721 if (!macb_is_gem(bp)) {
1722 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1724 bp->rx_buffer_size = size;
1726 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1728 "RX buffer must be multiple of %d bytes, expanding\n",
1729 RX_BUFFER_MULTIPLE);
1730 bp->rx_buffer_size =
1731 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1735 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1736 bp->dev->mtu, bp->rx_buffer_size);
1739 static void gem_free_rx_buffers(struct macb *bp)
1741 struct sk_buff *skb;
1742 struct macb_dma_desc *desc;
1749 for (i = 0; i < bp->rx_ring_size; i++) {
1750 skb = bp->rx_skbuff[i];
1755 desc = macb_rx_desc(bp, i);
1756 addr = macb_get_addr(bp, desc);
1758 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1760 dev_kfree_skb_any(skb);
1764 kfree(bp->rx_skbuff);
1765 bp->rx_skbuff = NULL;
1768 static void macb_free_rx_buffers(struct macb *bp)
1770 if (bp->rx_buffers) {
1771 dma_free_coherent(&bp->pdev->dev,
1772 bp->rx_ring_size * bp->rx_buffer_size,
1773 bp->rx_buffers, bp->rx_buffers_dma);
1774 bp->rx_buffers = NULL;
1778 static void macb_free_consistent(struct macb *bp)
1780 struct macb_queue *queue;
1783 bp->macbgem_ops.mog_free_rx_buffers(bp);
1785 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES(bp),
1786 bp->rx_ring, bp->rx_ring_dma);
1790 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1791 kfree(queue->tx_skb);
1792 queue->tx_skb = NULL;
1793 if (queue->tx_ring) {
1794 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES(bp),
1795 queue->tx_ring, queue->tx_ring_dma);
1796 queue->tx_ring = NULL;
1801 static int gem_alloc_rx_buffers(struct macb *bp)
1805 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1806 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1811 "Allocated %d RX struct sk_buff entries at %p\n",
1812 bp->rx_ring_size, bp->rx_skbuff);
1816 static int macb_alloc_rx_buffers(struct macb *bp)
1820 size = bp->rx_ring_size * bp->rx_buffer_size;
1821 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1822 &bp->rx_buffers_dma, GFP_KERNEL);
1823 if (!bp->rx_buffers)
1827 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1828 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1832 static int macb_alloc_consistent(struct macb *bp)
1834 struct macb_queue *queue;
1838 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1839 size = TX_RING_BYTES(bp);
1840 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1841 &queue->tx_ring_dma,
1843 if (!queue->tx_ring)
1846 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1847 q, size, (unsigned long)queue->tx_ring_dma,
1850 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
1851 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1856 size = RX_RING_BYTES(bp);
1857 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1858 &bp->rx_ring_dma, GFP_KERNEL);
1862 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1863 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1865 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1871 macb_free_consistent(bp);
1875 static void gem_init_rings(struct macb *bp)
1877 struct macb_queue *queue;
1878 struct macb_dma_desc *desc = NULL;
1882 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1883 for (i = 0; i < bp->tx_ring_size; i++) {
1884 desc = macb_tx_desc(queue, i);
1885 macb_set_addr(bp, desc, 0);
1886 desc->ctrl = MACB_BIT(TX_USED);
1888 desc->ctrl |= MACB_BIT(TX_WRAP);
1894 bp->rx_prepared_head = 0;
1899 static void macb_init_rings(struct macb *bp)
1902 struct macb_dma_desc *desc = NULL;
1904 macb_init_rx_ring(bp);
1906 for (i = 0; i < bp->tx_ring_size; i++) {
1907 desc = macb_tx_desc(&bp->queues[0], i);
1908 macb_set_addr(bp, desc, 0);
1909 desc->ctrl = MACB_BIT(TX_USED);
1911 bp->queues[0].tx_head = 0;
1912 bp->queues[0].tx_tail = 0;
1913 desc->ctrl |= MACB_BIT(TX_WRAP);
1916 static void macb_reset_hw(struct macb *bp)
1918 struct macb_queue *queue;
1920 u32 ctrl = macb_readl(bp, NCR);
1922 /* Disable RX and TX (XXX: Should we halt the transmission
1925 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1927 /* Clear the stats registers (XXX: Update stats first?) */
1928 ctrl |= MACB_BIT(CLRSTAT);
1930 macb_writel(bp, NCR, ctrl);
1932 /* Clear all status flags */
1933 macb_writel(bp, TSR, -1);
1934 macb_writel(bp, RSR, -1);
1936 /* Disable all interrupts */
1937 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1938 queue_writel(queue, IDR, -1);
1939 queue_readl(queue, ISR);
1940 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1941 queue_writel(queue, ISR, -1);
1945 static u32 gem_mdc_clk_div(struct macb *bp)
1948 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1950 if (pclk_hz <= 20000000)
1951 config = GEM_BF(CLK, GEM_CLK_DIV8);
1952 else if (pclk_hz <= 40000000)
1953 config = GEM_BF(CLK, GEM_CLK_DIV16);
1954 else if (pclk_hz <= 80000000)
1955 config = GEM_BF(CLK, GEM_CLK_DIV32);
1956 else if (pclk_hz <= 120000000)
1957 config = GEM_BF(CLK, GEM_CLK_DIV48);
1958 else if (pclk_hz <= 160000000)
1959 config = GEM_BF(CLK, GEM_CLK_DIV64);
1961 config = GEM_BF(CLK, GEM_CLK_DIV96);
1966 static u32 macb_mdc_clk_div(struct macb *bp)
1969 unsigned long pclk_hz;
1971 if (macb_is_gem(bp))
1972 return gem_mdc_clk_div(bp);
1974 pclk_hz = clk_get_rate(bp->pclk);
1975 if (pclk_hz <= 20000000)
1976 config = MACB_BF(CLK, MACB_CLK_DIV8);
1977 else if (pclk_hz <= 40000000)
1978 config = MACB_BF(CLK, MACB_CLK_DIV16);
1979 else if (pclk_hz <= 80000000)
1980 config = MACB_BF(CLK, MACB_CLK_DIV32);
1982 config = MACB_BF(CLK, MACB_CLK_DIV64);
1987 /* Get the DMA bus width field of the network configuration register that we
1988 * should program. We find the width from decoding the design configuration
1989 * register to find the maximum supported data bus width.
1991 static u32 macb_dbw(struct macb *bp)
1993 if (!macb_is_gem(bp))
1996 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1998 return GEM_BF(DBW, GEM_DBW128);
2000 return GEM_BF(DBW, GEM_DBW64);
2003 return GEM_BF(DBW, GEM_DBW32);
2007 /* Configure the receive DMA engine
2008 * - use the correct receive buffer size
2009 * - set best burst length for DMA operations
2010 * (if not supported by FIFO, it will fallback to default)
2011 * - set both rx/tx packet buffers to full memory size
2012 * These are configurable parameters for GEM.
2014 static void macb_configure_dma(struct macb *bp)
2018 if (macb_is_gem(bp)) {
2019 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2020 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
2021 if (bp->dma_burst_length)
2022 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2023 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2024 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2027 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2029 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2031 if (bp->dev->features & NETIF_F_HW_CSUM)
2032 dmacfg |= GEM_BIT(TXCOEN);
2034 dmacfg &= ~GEM_BIT(TXCOEN);
2036 dmacfg &= ~GEM_BIT(ADDR64);
2037 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2038 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2039 dmacfg |= GEM_BIT(ADDR64);
2041 #ifdef CONFIG_MACB_USE_HWSTAMP
2042 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2043 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2045 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2047 gem_writel(bp, DMACFG, dmacfg);
2051 static void macb_init_hw(struct macb *bp)
2053 struct macb_queue *queue;
2059 macb_set_hwaddr(bp);
2061 config = macb_mdc_clk_div(bp);
2062 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2063 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2064 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2065 config |= MACB_BIT(PAE); /* PAuse Enable */
2066 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2067 if (bp->caps & MACB_CAPS_JUMBO)
2068 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2070 config |= MACB_BIT(BIG); /* Receive oversized frames */
2071 if (bp->dev->flags & IFF_PROMISC)
2072 config |= MACB_BIT(CAF); /* Copy All Frames */
2073 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2074 config |= GEM_BIT(RXCOEN);
2075 if (!(bp->dev->flags & IFF_BROADCAST))
2076 config |= MACB_BIT(NBC); /* No BroadCast */
2077 config |= macb_dbw(bp);
2078 macb_writel(bp, NCFGR, config);
2079 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2080 gem_writel(bp, JML, bp->jumbo_max_len);
2081 bp->speed = SPEED_10;
2082 bp->duplex = DUPLEX_HALF;
2083 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2084 if (bp->caps & MACB_CAPS_JUMBO)
2085 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2087 macb_configure_dma(bp);
2089 /* Initialize TX and RX buffers */
2090 macb_writel(bp, RBQP, lower_32_bits(bp->rx_ring_dma));
2091 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2092 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2093 macb_writel(bp, RBQPH, upper_32_bits(bp->rx_ring_dma));
2095 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2096 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2097 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2098 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2099 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2102 /* Enable interrupts */
2103 queue_writel(queue, IER,
2109 /* Enable TX and RX */
2110 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
2113 /* The hash address register is 64 bits long and takes up two
2114 * locations in the memory map. The least significant bits are stored
2115 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2117 * The unicast hash enable and the multicast hash enable bits in the
2118 * network configuration register enable the reception of hash matched
2119 * frames. The destination address is reduced to a 6 bit index into
2120 * the 64 bit hash register using the following hash function. The
2121 * hash function is an exclusive or of every sixth bit of the
2122 * destination address.
2124 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2125 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2126 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2127 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2128 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2129 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2131 * da[0] represents the least significant bit of the first byte
2132 * received, that is, the multicast/unicast indicator, and da[47]
2133 * represents the most significant bit of the last byte received. If
2134 * the hash index, hi[n], points to a bit that is set in the hash
2135 * register then the frame will be matched according to whether the
2136 * frame is multicast or unicast. A multicast match will be signalled
2137 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2138 * index points to a bit set in the hash register. A unicast match
2139 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2140 * and the hash index points to a bit set in the hash register. To
2141 * receive all multicast frames, the hash register should be set with
2142 * all ones and the multicast hash enable bit should be set in the
2143 * network configuration register.
2146 static inline int hash_bit_value(int bitnr, __u8 *addr)
2148 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2153 /* Return the hash index value for the specified address. */
2154 static int hash_get_index(__u8 *addr)
2159 for (j = 0; j < 6; j++) {
2160 for (i = 0, bitval = 0; i < 8; i++)
2161 bitval ^= hash_bit_value(i * 6 + j, addr);
2163 hash_index |= (bitval << j);
2169 /* Add multicast addresses to the internal multicast-hash table. */
2170 static void macb_sethashtable(struct net_device *dev)
2172 struct netdev_hw_addr *ha;
2173 unsigned long mc_filter[2];
2175 struct macb *bp = netdev_priv(dev);
2180 netdev_for_each_mc_addr(ha, dev) {
2181 bitnr = hash_get_index(ha->addr);
2182 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2185 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2186 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2189 /* Enable/Disable promiscuous and multicast modes. */
2190 static void macb_set_rx_mode(struct net_device *dev)
2193 struct macb *bp = netdev_priv(dev);
2195 cfg = macb_readl(bp, NCFGR);
2197 if (dev->flags & IFF_PROMISC) {
2198 /* Enable promiscuous mode */
2199 cfg |= MACB_BIT(CAF);
2201 /* Disable RX checksum offload */
2202 if (macb_is_gem(bp))
2203 cfg &= ~GEM_BIT(RXCOEN);
2205 /* Disable promiscuous mode */
2206 cfg &= ~MACB_BIT(CAF);
2208 /* Enable RX checksum offload only if requested */
2209 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2210 cfg |= GEM_BIT(RXCOEN);
2213 if (dev->flags & IFF_ALLMULTI) {
2214 /* Enable all multicast mode */
2215 macb_or_gem_writel(bp, HRB, -1);
2216 macb_or_gem_writel(bp, HRT, -1);
2217 cfg |= MACB_BIT(NCFGR_MTI);
2218 } else if (!netdev_mc_empty(dev)) {
2219 /* Enable specific multicasts */
2220 macb_sethashtable(dev);
2221 cfg |= MACB_BIT(NCFGR_MTI);
2222 } else if (dev->flags & (~IFF_ALLMULTI)) {
2223 /* Disable all multicast mode */
2224 macb_or_gem_writel(bp, HRB, 0);
2225 macb_or_gem_writel(bp, HRT, 0);
2226 cfg &= ~MACB_BIT(NCFGR_MTI);
2229 macb_writel(bp, NCFGR, cfg);
2232 static int macb_open(struct net_device *dev)
2234 struct macb *bp = netdev_priv(dev);
2235 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2238 netdev_dbg(bp->dev, "open\n");
2240 /* carrier starts down */
2241 netif_carrier_off(dev);
2243 /* if the phy is not yet register, retry later*/
2247 /* RX buffers initialization */
2248 macb_init_rx_buffer_size(bp, bufsz);
2250 err = macb_alloc_consistent(bp);
2252 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2257 napi_enable(&bp->napi);
2259 bp->macbgem_ops.mog_init_rings(bp);
2262 /* schedule a link state check */
2263 phy_start(dev->phydev);
2265 netif_tx_start_all_queues(dev);
2268 bp->ptp_info->ptp_init(dev);
2273 static int macb_close(struct net_device *dev)
2275 struct macb *bp = netdev_priv(dev);
2276 unsigned long flags;
2278 netif_tx_stop_all_queues(dev);
2279 napi_disable(&bp->napi);
2282 phy_stop(dev->phydev);
2284 spin_lock_irqsave(&bp->lock, flags);
2286 netif_carrier_off(dev);
2287 spin_unlock_irqrestore(&bp->lock, flags);
2289 macb_free_consistent(bp);
2292 bp->ptp_info->ptp_remove(dev);
2297 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2299 if (netif_running(dev))
2307 static void gem_update_stats(struct macb *bp)
2310 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2312 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2313 u32 offset = gem_statistics[i].offset;
2314 u64 val = bp->macb_reg_readl(bp, offset);
2316 bp->ethtool_stats[i] += val;
2319 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2320 /* Add GEM_OCTTXH, GEM_OCTRXH */
2321 val = bp->macb_reg_readl(bp, offset + 4);
2322 bp->ethtool_stats[i] += ((u64)val) << 32;
2328 static struct net_device_stats *gem_get_stats(struct macb *bp)
2330 struct gem_stats *hwstat = &bp->hw_stats.gem;
2331 struct net_device_stats *nstat = &bp->dev->stats;
2333 if (!netif_running(bp->dev))
2336 gem_update_stats(bp);
2338 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2339 hwstat->rx_alignment_errors +
2340 hwstat->rx_resource_errors +
2341 hwstat->rx_overruns +
2342 hwstat->rx_oversize_frames +
2343 hwstat->rx_jabbers +
2344 hwstat->rx_undersized_frames +
2345 hwstat->rx_length_field_frame_errors);
2346 nstat->tx_errors = (hwstat->tx_late_collisions +
2347 hwstat->tx_excessive_collisions +
2348 hwstat->tx_underrun +
2349 hwstat->tx_carrier_sense_errors);
2350 nstat->multicast = hwstat->rx_multicast_frames;
2351 nstat->collisions = (hwstat->tx_single_collision_frames +
2352 hwstat->tx_multiple_collision_frames +
2353 hwstat->tx_excessive_collisions);
2354 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2355 hwstat->rx_jabbers +
2356 hwstat->rx_undersized_frames +
2357 hwstat->rx_length_field_frame_errors);
2358 nstat->rx_over_errors = hwstat->rx_resource_errors;
2359 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2360 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2361 nstat->rx_fifo_errors = hwstat->rx_overruns;
2362 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2363 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2364 nstat->tx_fifo_errors = hwstat->tx_underrun;
2369 static void gem_get_ethtool_stats(struct net_device *dev,
2370 struct ethtool_stats *stats, u64 *data)
2374 bp = netdev_priv(dev);
2375 gem_update_stats(bp);
2376 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
2379 static int gem_get_sset_count(struct net_device *dev, int sset)
2383 return GEM_STATS_LEN;
2389 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2395 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2396 memcpy(p, gem_statistics[i].stat_string,
2402 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2404 struct macb *bp = netdev_priv(dev);
2405 struct net_device_stats *nstat = &bp->dev->stats;
2406 struct macb_stats *hwstat = &bp->hw_stats.macb;
2408 if (macb_is_gem(bp))
2409 return gem_get_stats(bp);
2411 /* read stats from hardware */
2412 macb_update_stats(bp);
2414 /* Convert HW stats into netdevice stats */
2415 nstat->rx_errors = (hwstat->rx_fcs_errors +
2416 hwstat->rx_align_errors +
2417 hwstat->rx_resource_errors +
2418 hwstat->rx_overruns +
2419 hwstat->rx_oversize_pkts +
2420 hwstat->rx_jabbers +
2421 hwstat->rx_undersize_pkts +
2422 hwstat->rx_length_mismatch);
2423 nstat->tx_errors = (hwstat->tx_late_cols +
2424 hwstat->tx_excessive_cols +
2425 hwstat->tx_underruns +
2426 hwstat->tx_carrier_errors +
2427 hwstat->sqe_test_errors);
2428 nstat->collisions = (hwstat->tx_single_cols +
2429 hwstat->tx_multiple_cols +
2430 hwstat->tx_excessive_cols);
2431 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2432 hwstat->rx_jabbers +
2433 hwstat->rx_undersize_pkts +
2434 hwstat->rx_length_mismatch);
2435 nstat->rx_over_errors = hwstat->rx_resource_errors +
2436 hwstat->rx_overruns;
2437 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2438 nstat->rx_frame_errors = hwstat->rx_align_errors;
2439 nstat->rx_fifo_errors = hwstat->rx_overruns;
2440 /* XXX: What does "missed" mean? */
2441 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2442 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2443 nstat->tx_fifo_errors = hwstat->tx_underruns;
2444 /* Don't know about heartbeat or window errors... */
2449 static int macb_get_regs_len(struct net_device *netdev)
2451 return MACB_GREGS_NBR * sizeof(u32);
2454 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2457 struct macb *bp = netdev_priv(dev);
2458 unsigned int tail, head;
2461 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2462 | MACB_GREGS_VERSION;
2464 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2465 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2467 regs_buff[0] = macb_readl(bp, NCR);
2468 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2469 regs_buff[2] = macb_readl(bp, NSR);
2470 regs_buff[3] = macb_readl(bp, TSR);
2471 regs_buff[4] = macb_readl(bp, RBQP);
2472 regs_buff[5] = macb_readl(bp, TBQP);
2473 regs_buff[6] = macb_readl(bp, RSR);
2474 regs_buff[7] = macb_readl(bp, IMR);
2476 regs_buff[8] = tail;
2477 regs_buff[9] = head;
2478 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2479 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2481 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2482 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2483 if (macb_is_gem(bp))
2484 regs_buff[13] = gem_readl(bp, DMACFG);
2487 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2489 struct macb *bp = netdev_priv(netdev);
2494 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2495 wol->supported = WAKE_MAGIC;
2497 if (bp->wol & MACB_WOL_ENABLED)
2498 wol->wolopts |= WAKE_MAGIC;
2502 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2504 struct macb *bp = netdev_priv(netdev);
2506 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2507 (wol->wolopts & ~WAKE_MAGIC))
2510 if (wol->wolopts & WAKE_MAGIC)
2511 bp->wol |= MACB_WOL_ENABLED;
2513 bp->wol &= ~MACB_WOL_ENABLED;
2515 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2520 static void macb_get_ringparam(struct net_device *netdev,
2521 struct ethtool_ringparam *ring)
2523 struct macb *bp = netdev_priv(netdev);
2525 ring->rx_max_pending = MAX_RX_RING_SIZE;
2526 ring->tx_max_pending = MAX_TX_RING_SIZE;
2528 ring->rx_pending = bp->rx_ring_size;
2529 ring->tx_pending = bp->tx_ring_size;
2532 static int macb_set_ringparam(struct net_device *netdev,
2533 struct ethtool_ringparam *ring)
2535 struct macb *bp = netdev_priv(netdev);
2536 u32 new_rx_size, new_tx_size;
2537 unsigned int reset = 0;
2539 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2542 new_rx_size = clamp_t(u32, ring->rx_pending,
2543 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2544 new_rx_size = roundup_pow_of_two(new_rx_size);
2546 new_tx_size = clamp_t(u32, ring->tx_pending,
2547 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2548 new_tx_size = roundup_pow_of_two(new_tx_size);
2550 if ((new_tx_size == bp->tx_ring_size) &&
2551 (new_rx_size == bp->rx_ring_size)) {
2556 if (netif_running(bp->dev)) {
2558 macb_close(bp->dev);
2561 bp->rx_ring_size = new_rx_size;
2562 bp->tx_ring_size = new_tx_size;
2570 #ifdef CONFIG_MACB_USE_HWSTAMP
2571 static unsigned int gem_get_tsu_rate(struct macb *bp)
2573 struct clk *tsu_clk;
2574 unsigned int tsu_rate;
2576 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2577 if (!IS_ERR(tsu_clk))
2578 tsu_rate = clk_get_rate(tsu_clk);
2579 /* try pclk instead */
2580 else if (!IS_ERR(bp->pclk)) {
2582 tsu_rate = clk_get_rate(tsu_clk);
2588 static s32 gem_get_ptp_max_adj(void)
2593 static int gem_get_ts_info(struct net_device *dev,
2594 struct ethtool_ts_info *info)
2596 struct macb *bp = netdev_priv(dev);
2598 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2599 ethtool_op_get_ts_info(dev, info);
2603 info->so_timestamping =
2604 SOF_TIMESTAMPING_TX_SOFTWARE |
2605 SOF_TIMESTAMPING_RX_SOFTWARE |
2606 SOF_TIMESTAMPING_SOFTWARE |
2607 SOF_TIMESTAMPING_TX_HARDWARE |
2608 SOF_TIMESTAMPING_RX_HARDWARE |
2609 SOF_TIMESTAMPING_RAW_HARDWARE;
2611 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2612 (1 << HWTSTAMP_TX_OFF) |
2613 (1 << HWTSTAMP_TX_ON);
2615 (1 << HWTSTAMP_FILTER_NONE) |
2616 (1 << HWTSTAMP_FILTER_ALL);
2618 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2623 static struct macb_ptp_info gem_ptp_info = {
2624 .ptp_init = gem_ptp_init,
2625 .ptp_remove = gem_ptp_remove,
2626 .get_ptp_max_adj = gem_get_ptp_max_adj,
2627 .get_tsu_rate = gem_get_tsu_rate,
2628 .get_ts_info = gem_get_ts_info,
2629 .get_hwtst = gem_get_hwtst,
2630 .set_hwtst = gem_set_hwtst,
2634 static int macb_get_ts_info(struct net_device *netdev,
2635 struct ethtool_ts_info *info)
2637 struct macb *bp = netdev_priv(netdev);
2640 return bp->ptp_info->get_ts_info(netdev, info);
2642 return ethtool_op_get_ts_info(netdev, info);
2645 static const struct ethtool_ops macb_ethtool_ops = {
2646 .get_regs_len = macb_get_regs_len,
2647 .get_regs = macb_get_regs,
2648 .get_link = ethtool_op_get_link,
2649 .get_ts_info = ethtool_op_get_ts_info,
2650 .get_wol = macb_get_wol,
2651 .set_wol = macb_set_wol,
2652 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2653 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2654 .get_ringparam = macb_get_ringparam,
2655 .set_ringparam = macb_set_ringparam,
2658 static const struct ethtool_ops gem_ethtool_ops = {
2659 .get_regs_len = macb_get_regs_len,
2660 .get_regs = macb_get_regs,
2661 .get_link = ethtool_op_get_link,
2662 .get_ts_info = macb_get_ts_info,
2663 .get_ethtool_stats = gem_get_ethtool_stats,
2664 .get_strings = gem_get_ethtool_strings,
2665 .get_sset_count = gem_get_sset_count,
2666 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2667 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2668 .get_ringparam = macb_get_ringparam,
2669 .set_ringparam = macb_set_ringparam,
2672 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2674 struct phy_device *phydev = dev->phydev;
2675 struct macb *bp = netdev_priv(dev);
2677 if (!netif_running(dev))
2684 return phy_mii_ioctl(phydev, rq, cmd);
2688 return bp->ptp_info->set_hwtst(dev, rq, cmd);
2690 return bp->ptp_info->get_hwtst(dev, rq);
2692 return phy_mii_ioctl(phydev, rq, cmd);
2696 static int macb_set_features(struct net_device *netdev,
2697 netdev_features_t features)
2699 struct macb *bp = netdev_priv(netdev);
2700 netdev_features_t changed = features ^ netdev->features;
2702 /* TX checksum offload */
2703 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2706 dmacfg = gem_readl(bp, DMACFG);
2707 if (features & NETIF_F_HW_CSUM)
2708 dmacfg |= GEM_BIT(TXCOEN);
2710 dmacfg &= ~GEM_BIT(TXCOEN);
2711 gem_writel(bp, DMACFG, dmacfg);
2714 /* RX checksum offload */
2715 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2718 netcfg = gem_readl(bp, NCFGR);
2719 if (features & NETIF_F_RXCSUM &&
2720 !(netdev->flags & IFF_PROMISC))
2721 netcfg |= GEM_BIT(RXCOEN);
2723 netcfg &= ~GEM_BIT(RXCOEN);
2724 gem_writel(bp, NCFGR, netcfg);
2730 static const struct net_device_ops macb_netdev_ops = {
2731 .ndo_open = macb_open,
2732 .ndo_stop = macb_close,
2733 .ndo_start_xmit = macb_start_xmit,
2734 .ndo_set_rx_mode = macb_set_rx_mode,
2735 .ndo_get_stats = macb_get_stats,
2736 .ndo_do_ioctl = macb_ioctl,
2737 .ndo_validate_addr = eth_validate_addr,
2738 .ndo_change_mtu = macb_change_mtu,
2739 .ndo_set_mac_address = eth_mac_addr,
2740 #ifdef CONFIG_NET_POLL_CONTROLLER
2741 .ndo_poll_controller = macb_poll_controller,
2743 .ndo_set_features = macb_set_features,
2744 .ndo_features_check = macb_features_check,
2747 /* Configure peripheral capabilities according to device tree
2748 * and integration options used
2750 static void macb_configure_caps(struct macb *bp,
2751 const struct macb_config *dt_conf)
2756 bp->caps = dt_conf->caps;
2758 if (hw_is_gem(bp->regs, bp->native_io)) {
2759 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2761 dcfg = gem_readl(bp, DCFG1);
2762 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2763 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2764 dcfg = gem_readl(bp, DCFG2);
2765 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2766 bp->caps |= MACB_CAPS_FIFO_MODE;
2767 #ifdef CONFIG_MACB_USE_HWSTAMP
2768 if (gem_has_ptp(bp)) {
2769 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
2770 pr_err("GEM doesn't support hardware ptp.\n");
2772 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
2773 bp->ptp_info = &gem_ptp_info;
2779 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2782 static void macb_probe_queues(void __iomem *mem,
2784 unsigned int *queue_mask,
2785 unsigned int *num_queues)
2792 /* is it macb or gem ?
2794 * We need to read directly from the hardware here because
2795 * we are early in the probe process and don't have the
2796 * MACB_CAPS_MACB_IS_GEM flag positioned
2798 if (!hw_is_gem(mem, native_io))
2801 /* bit 0 is never set but queue 0 always exists */
2802 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2806 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2807 if (*queue_mask & (1 << hw_q))
2811 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2812 struct clk **hclk, struct clk **tx_clk,
2813 struct clk **rx_clk)
2815 struct macb_platform_data *pdata;
2818 pdata = dev_get_platdata(&pdev->dev);
2820 *pclk = pdata->pclk;
2821 *hclk = pdata->hclk;
2823 *pclk = devm_clk_get(&pdev->dev, "pclk");
2824 *hclk = devm_clk_get(&pdev->dev, "hclk");
2827 if (IS_ERR_OR_NULL(*pclk)) {
2828 err = PTR_ERR(*pclk);
2832 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
2836 if (IS_ERR_OR_NULL(*hclk)) {
2837 err = PTR_ERR(*hclk);
2841 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
2845 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2846 if (IS_ERR(*tx_clk))
2849 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
2850 if (IS_ERR(*rx_clk))
2853 err = clk_prepare_enable(*pclk);
2855 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
2859 err = clk_prepare_enable(*hclk);
2861 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
2862 goto err_disable_pclk;
2865 err = clk_prepare_enable(*tx_clk);
2867 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2868 goto err_disable_hclk;
2871 err = clk_prepare_enable(*rx_clk);
2873 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2874 goto err_disable_txclk;
2880 clk_disable_unprepare(*tx_clk);
2883 clk_disable_unprepare(*hclk);
2886 clk_disable_unprepare(*pclk);
2891 static int macb_init(struct platform_device *pdev)
2893 struct net_device *dev = platform_get_drvdata(pdev);
2894 unsigned int hw_q, q;
2895 struct macb *bp = netdev_priv(dev);
2896 struct macb_queue *queue;
2900 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
2901 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
2903 /* set the queue register mapping once for all: queue0 has a special
2904 * register mapping but we don't want to test the queue index then
2905 * compute the corresponding register offset at run time.
2907 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2908 if (!(bp->queue_mask & (1 << hw_q)))
2911 queue = &bp->queues[q];
2914 queue->ISR = GEM_ISR(hw_q - 1);
2915 queue->IER = GEM_IER(hw_q - 1);
2916 queue->IDR = GEM_IDR(hw_q - 1);
2917 queue->IMR = GEM_IMR(hw_q - 1);
2918 queue->TBQP = GEM_TBQP(hw_q - 1);
2919 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2920 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2921 queue->TBQPH = GEM_TBQPH(hw_q - 1);
2924 /* queue0 uses legacy registers */
2925 queue->ISR = MACB_ISR;
2926 queue->IER = MACB_IER;
2927 queue->IDR = MACB_IDR;
2928 queue->IMR = MACB_IMR;
2929 queue->TBQP = MACB_TBQP;
2930 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2931 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2932 queue->TBQPH = MACB_TBQPH;
2936 /* get irq: here we use the linux queue index, not the hardware
2937 * queue index. the queue irq definitions in the device tree
2938 * must remove the optional gaps that could exist in the
2939 * hardware queue mask.
2941 queue->irq = platform_get_irq(pdev, q);
2942 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2943 IRQF_SHARED, dev->name, queue);
2946 "Unable to request IRQ %d (error %d)\n",
2951 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2955 dev->netdev_ops = &macb_netdev_ops;
2956 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2958 /* setup appropriated routines according to adapter type */
2959 if (macb_is_gem(bp)) {
2960 bp->max_tx_length = GEM_MAX_TX_LEN;
2961 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2962 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2963 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2964 bp->macbgem_ops.mog_rx = gem_rx;
2965 dev->ethtool_ops = &gem_ethtool_ops;
2967 bp->max_tx_length = MACB_MAX_TX_LEN;
2968 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2969 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2970 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2971 bp->macbgem_ops.mog_rx = macb_rx;
2972 dev->ethtool_ops = &macb_ethtool_ops;
2976 dev->hw_features = NETIF_F_SG;
2978 /* Check LSO capability */
2979 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
2980 dev->hw_features |= MACB_NETIF_LSO;
2982 /* Checksum offload is only available on gem with packet buffer */
2983 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2984 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2985 if (bp->caps & MACB_CAPS_SG_DISABLED)
2986 dev->hw_features &= ~NETIF_F_SG;
2987 dev->features = dev->hw_features;
2989 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2991 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2992 val = GEM_BIT(RGMII);
2993 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2994 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2995 val = MACB_BIT(RMII);
2996 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2997 val = MACB_BIT(MII);
2999 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3000 val |= MACB_BIT(CLKEN);
3002 macb_or_gem_writel(bp, USRIO, val);
3005 /* Set MII management clock divider */
3006 val = macb_mdc_clk_div(bp);
3007 val |= macb_dbw(bp);
3008 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3009 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3010 macb_writel(bp, NCFGR, val);
3015 #if defined(CONFIG_OF)
3016 /* 1518 rounded up */
3017 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3018 /* max number of receive buffers */
3019 #define AT91ETHER_MAX_RX_DESCR 9
3021 /* Initialize and start the Receiver and Transmit subsystems */
3022 static int at91ether_start(struct net_device *dev)
3024 struct macb *lp = netdev_priv(dev);
3025 struct macb_dma_desc *desc;
3030 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3031 (AT91ETHER_MAX_RX_DESCR *
3032 macb_dma_desc_get_size(lp)),
3033 &lp->rx_ring_dma, GFP_KERNEL);
3037 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3038 AT91ETHER_MAX_RX_DESCR *
3039 AT91ETHER_MAX_RBUFF_SZ,
3040 &lp->rx_buffers_dma, GFP_KERNEL);
3041 if (!lp->rx_buffers) {
3042 dma_free_coherent(&lp->pdev->dev,
3043 AT91ETHER_MAX_RX_DESCR *
3044 macb_dma_desc_get_size(lp),
3045 lp->rx_ring, lp->rx_ring_dma);
3050 addr = lp->rx_buffers_dma;
3051 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3052 desc = macb_rx_desc(lp, i);
3053 macb_set_addr(lp, desc, addr);
3055 addr += AT91ETHER_MAX_RBUFF_SZ;
3058 /* Set the Wrap bit on the last descriptor */
3059 desc->addr |= MACB_BIT(RX_WRAP);
3061 /* Reset buffer index */
3064 /* Program address of descriptor list in Rx Buffer Queue register */
3065 macb_writel(lp, RBQP, lp->rx_ring_dma);
3067 /* Enable Receive and Transmit */
3068 ctl = macb_readl(lp, NCR);
3069 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3074 /* Open the ethernet interface */
3075 static int at91ether_open(struct net_device *dev)
3077 struct macb *lp = netdev_priv(dev);
3081 /* Clear internal statistics */
3082 ctl = macb_readl(lp, NCR);
3083 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3085 macb_set_hwaddr(lp);
3087 ret = at91ether_start(dev);
3091 /* Enable MAC interrupts */
3092 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3094 MACB_BIT(ISR_TUND) |
3097 MACB_BIT(ISR_ROVR) |
3100 /* schedule a link state check */
3101 phy_start(dev->phydev);
3103 netif_start_queue(dev);
3108 /* Close the interface */
3109 static int at91ether_close(struct net_device *dev)
3111 struct macb *lp = netdev_priv(dev);
3114 /* Disable Receiver and Transmitter */
3115 ctl = macb_readl(lp, NCR);
3116 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3118 /* Disable MAC interrupts */
3119 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3121 MACB_BIT(ISR_TUND) |
3124 MACB_BIT(ISR_ROVR) |
3127 netif_stop_queue(dev);
3129 dma_free_coherent(&lp->pdev->dev,
3130 AT91ETHER_MAX_RX_DESCR *
3131 macb_dma_desc_get_size(lp),
3132 lp->rx_ring, lp->rx_ring_dma);
3135 dma_free_coherent(&lp->pdev->dev,
3136 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3137 lp->rx_buffers, lp->rx_buffers_dma);
3138 lp->rx_buffers = NULL;
3143 /* Transmit packet */
3144 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
3146 struct macb *lp = netdev_priv(dev);
3148 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3149 netif_stop_queue(dev);
3151 /* Store packet information (to free when Tx completed) */
3153 lp->skb_length = skb->len;
3154 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3156 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3157 dev_kfree_skb_any(skb);
3158 dev->stats.tx_dropped++;
3159 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3160 return NETDEV_TX_OK;
3163 /* Set address of the data in the Transmit Address register */
3164 macb_writel(lp, TAR, lp->skb_physaddr);
3165 /* Set length of the packet in the Transmit Control register */
3166 macb_writel(lp, TCR, skb->len);
3169 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3170 return NETDEV_TX_BUSY;
3173 return NETDEV_TX_OK;
3176 /* Extract received frame from buffer descriptors and sent to upper layers.
3177 * (Called from interrupt context)
3179 static void at91ether_rx(struct net_device *dev)
3181 struct macb *lp = netdev_priv(dev);
3182 struct macb_dma_desc *desc;
3183 unsigned char *p_recv;
3184 struct sk_buff *skb;
3185 unsigned int pktlen;
3187 desc = macb_rx_desc(lp, lp->rx_tail);
3188 while (desc->addr & MACB_BIT(RX_USED)) {
3189 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3190 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3191 skb = netdev_alloc_skb(dev, pktlen + 2);
3193 skb_reserve(skb, 2);
3194 skb_put_data(skb, p_recv, pktlen);
3196 skb->protocol = eth_type_trans(skb, dev);
3197 dev->stats.rx_packets++;
3198 dev->stats.rx_bytes += pktlen;
3201 dev->stats.rx_dropped++;
3204 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3205 dev->stats.multicast++;
3207 /* reset ownership bit */
3208 desc->addr &= ~MACB_BIT(RX_USED);
3210 /* wrap after last buffer */
3211 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3216 desc = macb_rx_desc(lp, lp->rx_tail);
3220 /* MAC interrupt handler */
3221 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3223 struct net_device *dev = dev_id;
3224 struct macb *lp = netdev_priv(dev);
3227 /* MAC Interrupt Status register indicates what interrupts are pending.
3228 * It is automatically cleared once read.
3230 intstatus = macb_readl(lp, ISR);
3232 /* Receive complete */
3233 if (intstatus & MACB_BIT(RCOMP))
3236 /* Transmit complete */
3237 if (intstatus & MACB_BIT(TCOMP)) {
3238 /* The TCOM bit is set even if the transmission failed */
3239 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3240 dev->stats.tx_errors++;
3243 dev_kfree_skb_irq(lp->skb);
3245 dma_unmap_single(NULL, lp->skb_physaddr,
3246 lp->skb_length, DMA_TO_DEVICE);
3247 dev->stats.tx_packets++;
3248 dev->stats.tx_bytes += lp->skb_length;
3250 netif_wake_queue(dev);
3253 /* Work-around for EMAC Errata section 41.3.1 */
3254 if (intstatus & MACB_BIT(RXUBR)) {
3255 ctl = macb_readl(lp, NCR);
3256 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3258 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3261 if (intstatus & MACB_BIT(ISR_ROVR))
3262 netdev_err(dev, "ROVR error\n");
3267 #ifdef CONFIG_NET_POLL_CONTROLLER
3268 static void at91ether_poll_controller(struct net_device *dev)
3270 unsigned long flags;
3272 local_irq_save(flags);
3273 at91ether_interrupt(dev->irq, dev);
3274 local_irq_restore(flags);
3278 static const struct net_device_ops at91ether_netdev_ops = {
3279 .ndo_open = at91ether_open,
3280 .ndo_stop = at91ether_close,
3281 .ndo_start_xmit = at91ether_start_xmit,
3282 .ndo_get_stats = macb_get_stats,
3283 .ndo_set_rx_mode = macb_set_rx_mode,
3284 .ndo_set_mac_address = eth_mac_addr,
3285 .ndo_do_ioctl = macb_ioctl,
3286 .ndo_validate_addr = eth_validate_addr,
3287 #ifdef CONFIG_NET_POLL_CONTROLLER
3288 .ndo_poll_controller = at91ether_poll_controller,
3292 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3293 struct clk **hclk, struct clk **tx_clk,
3294 struct clk **rx_clk)
3302 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3304 return PTR_ERR(*pclk);
3306 err = clk_prepare_enable(*pclk);
3308 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3315 static int at91ether_init(struct platform_device *pdev)
3317 struct net_device *dev = platform_get_drvdata(pdev);
3318 struct macb *bp = netdev_priv(dev);
3322 dev->netdev_ops = &at91ether_netdev_ops;
3323 dev->ethtool_ops = &macb_ethtool_ops;
3325 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3330 macb_writel(bp, NCR, 0);
3332 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3333 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3334 reg |= MACB_BIT(RM9200_RMII);
3336 macb_writel(bp, NCFGR, reg);
3341 static const struct macb_config at91sam9260_config = {
3342 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3343 .clk_init = macb_clk_init,
3347 static const struct macb_config sama5d3macb_config = {
3348 .caps = MACB_CAPS_SG_DISABLED
3349 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3350 .clk_init = macb_clk_init,
3354 static const struct macb_config pc302gem_config = {
3355 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3356 .dma_burst_length = 16,
3357 .clk_init = macb_clk_init,
3361 static const struct macb_config sama5d2_config = {
3362 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3363 .dma_burst_length = 16,
3364 .clk_init = macb_clk_init,
3368 static const struct macb_config sama5d3_config = {
3369 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3370 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3371 .dma_burst_length = 16,
3372 .clk_init = macb_clk_init,
3374 .jumbo_max_len = 10240,
3377 static const struct macb_config sama5d4_config = {
3378 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3379 .dma_burst_length = 4,
3380 .clk_init = macb_clk_init,
3384 static const struct macb_config emac_config = {
3385 .clk_init = at91ether_clk_init,
3386 .init = at91ether_init,
3389 static const struct macb_config np4_config = {
3390 .caps = MACB_CAPS_USRIO_DISABLED,
3391 .clk_init = macb_clk_init,
3395 static const struct macb_config zynqmp_config = {
3396 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3398 MACB_CAPS_GEM_HAS_PTP,
3399 .dma_burst_length = 16,
3400 .clk_init = macb_clk_init,
3402 .jumbo_max_len = 10240,
3405 static const struct macb_config zynq_config = {
3406 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
3407 .dma_burst_length = 16,
3408 .clk_init = macb_clk_init,
3412 static const struct of_device_id macb_dt_ids[] = {
3413 { .compatible = "cdns,at32ap7000-macb" },
3414 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3415 { .compatible = "cdns,macb" },
3416 { .compatible = "cdns,np4-macb", .data = &np4_config },
3417 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3418 { .compatible = "cdns,gem", .data = &pc302gem_config },
3419 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3420 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3421 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
3422 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3423 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3424 { .compatible = "cdns,emac", .data = &emac_config },
3425 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3426 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3429 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3430 #endif /* CONFIG_OF */
3432 static const struct macb_config default_gem_config = {
3433 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3435 MACB_CAPS_GEM_HAS_PTP,
3436 .dma_burst_length = 16,
3437 .clk_init = macb_clk_init,
3439 .jumbo_max_len = 10240,
3442 static int macb_probe(struct platform_device *pdev)
3444 const struct macb_config *macb_config = &default_gem_config;
3445 int (*clk_init)(struct platform_device *, struct clk **,
3446 struct clk **, struct clk **, struct clk **)
3447 = macb_config->clk_init;
3448 int (*init)(struct platform_device *) = macb_config->init;
3449 struct device_node *np = pdev->dev.of_node;
3450 struct device_node *phy_node;
3451 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3452 unsigned int queue_mask, num_queues;
3453 struct macb_platform_data *pdata;
3455 struct phy_device *phydev;
3456 struct net_device *dev;
3457 struct resource *regs;
3463 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3464 mem = devm_ioremap_resource(&pdev->dev, regs);
3466 return PTR_ERR(mem);
3469 const struct of_device_id *match;
3471 match = of_match_node(macb_dt_ids, np);
3472 if (match && match->data) {
3473 macb_config = match->data;
3474 clk_init = macb_config->clk_init;
3475 init = macb_config->init;
3479 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
3483 native_io = hw_is_native_io(mem);
3485 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
3486 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
3489 goto err_disable_clocks;
3492 dev->base_addr = regs->start;
3494 SET_NETDEV_DEV(dev, &pdev->dev);
3496 bp = netdev_priv(dev);
3500 bp->native_io = native_io;
3502 bp->macb_reg_readl = hw_readl_native;
3503 bp->macb_reg_writel = hw_writel_native;
3505 bp->macb_reg_readl = hw_readl;
3506 bp->macb_reg_writel = hw_writel;
3508 bp->num_queues = num_queues;
3509 bp->queue_mask = queue_mask;
3511 bp->dma_burst_length = macb_config->dma_burst_length;
3514 bp->tx_clk = tx_clk;
3515 bp->rx_clk = rx_clk;
3517 bp->jumbo_max_len = macb_config->jumbo_max_len;
3520 if (of_get_property(np, "magic-packet", NULL))
3521 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3522 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3524 spin_lock_init(&bp->lock);
3526 /* setup capabilities */
3527 macb_configure_caps(bp, macb_config);
3529 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3530 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
3531 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
3532 bp->hw_dma_cap |= HW_DMA_CAP_64B;
3535 platform_set_drvdata(pdev, dev);
3537 dev->irq = platform_get_irq(pdev, 0);
3540 goto err_out_free_netdev;
3543 /* MTU range: 68 - 1500 or 10240 */
3544 dev->min_mtu = GEM_MTU_MIN_SIZE;
3545 if (bp->caps & MACB_CAPS_JUMBO)
3546 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
3548 dev->max_mtu = ETH_DATA_LEN;
3550 mac = of_get_mac_address(np);
3552 ether_addr_copy(bp->dev->dev_addr, mac);
3554 macb_get_hwaddr(bp);
3556 /* Power up the PHY if there is a GPIO reset */
3557 phy_node = of_get_next_available_child(np, NULL);
3559 int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
3561 if (gpio_is_valid(gpio)) {
3562 bp->reset_gpio = gpio_to_desc(gpio);
3563 gpiod_direction_output(bp->reset_gpio, 1);
3566 of_node_put(phy_node);
3568 err = of_get_phy_mode(np);
3570 pdata = dev_get_platdata(&pdev->dev);
3571 if (pdata && pdata->is_rmii)
3572 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3574 bp->phy_interface = PHY_INTERFACE_MODE_MII;
3576 bp->phy_interface = err;
3579 /* IP specific init */
3582 goto err_out_free_netdev;
3584 err = macb_mii_init(bp);
3586 goto err_out_free_netdev;
3588 phydev = dev->phydev;
3590 netif_carrier_off(dev);
3592 err = register_netdev(dev);
3594 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
3595 goto err_out_unregister_mdio;
3598 phy_attached_info(phydev);
3600 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3601 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
3602 dev->base_addr, dev->irq, dev->dev_addr);
3606 err_out_unregister_mdio:
3607 phy_disconnect(dev->phydev);
3608 mdiobus_unregister(bp->mii_bus);
3609 mdiobus_free(bp->mii_bus);
3611 /* Shutdown the PHY if there is a GPIO reset */
3613 gpiod_set_value(bp->reset_gpio, 0);
3615 err_out_free_netdev:
3619 clk_disable_unprepare(tx_clk);
3620 clk_disable_unprepare(hclk);
3621 clk_disable_unprepare(pclk);
3622 clk_disable_unprepare(rx_clk);
3627 static int macb_remove(struct platform_device *pdev)
3629 struct net_device *dev;
3632 dev = platform_get_drvdata(pdev);
3635 bp = netdev_priv(dev);
3637 phy_disconnect(dev->phydev);
3638 mdiobus_unregister(bp->mii_bus);
3640 mdiobus_free(bp->mii_bus);
3642 /* Shutdown the PHY if there is a GPIO reset */
3644 gpiod_set_value(bp->reset_gpio, 0);
3646 unregister_netdev(dev);
3647 clk_disable_unprepare(bp->tx_clk);
3648 clk_disable_unprepare(bp->hclk);
3649 clk_disable_unprepare(bp->pclk);
3650 clk_disable_unprepare(bp->rx_clk);
3651 of_node_put(bp->phy_node);
3658 static int __maybe_unused macb_suspend(struct device *dev)
3660 struct platform_device *pdev = to_platform_device(dev);
3661 struct net_device *netdev = platform_get_drvdata(pdev);
3662 struct macb *bp = netdev_priv(netdev);
3664 netif_carrier_off(netdev);
3665 netif_device_detach(netdev);
3667 if (bp->wol & MACB_WOL_ENABLED) {
3668 macb_writel(bp, IER, MACB_BIT(WOL));
3669 macb_writel(bp, WOL, MACB_BIT(MAG));
3670 enable_irq_wake(bp->queues[0].irq);
3672 clk_disable_unprepare(bp->tx_clk);
3673 clk_disable_unprepare(bp->hclk);
3674 clk_disable_unprepare(bp->pclk);
3675 clk_disable_unprepare(bp->rx_clk);
3681 static int __maybe_unused macb_resume(struct device *dev)
3683 struct platform_device *pdev = to_platform_device(dev);
3684 struct net_device *netdev = platform_get_drvdata(pdev);
3685 struct macb *bp = netdev_priv(netdev);
3687 if (bp->wol & MACB_WOL_ENABLED) {
3688 macb_writel(bp, IDR, MACB_BIT(WOL));
3689 macb_writel(bp, WOL, 0);
3690 disable_irq_wake(bp->queues[0].irq);
3692 clk_prepare_enable(bp->pclk);
3693 clk_prepare_enable(bp->hclk);
3694 clk_prepare_enable(bp->tx_clk);
3695 clk_prepare_enable(bp->rx_clk);
3698 netif_device_attach(netdev);
3703 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3705 static struct platform_driver macb_driver = {
3706 .probe = macb_probe,
3707 .remove = macb_remove,
3710 .of_match_table = of_match_ptr(macb_dt_ids),
3715 module_platform_driver(macb_driver);
3717 MODULE_LICENSE("GPL");
3718 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3719 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3720 MODULE_ALIAS("platform:macb");