1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/pm_runtime.h>
40 /* This structure is only used for MACB on SiFive FU540 devices */
41 struct sifive_fu540_macb_mgmt {
47 #define MACB_RX_BUFFER_SIZE 128
48 #define RX_BUFFER_MULTIPLE 64 /* bytes */
50 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_RX_RING_SIZE 64
52 #define MAX_RX_RING_SIZE 8192
53 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
57 #define MIN_TX_RING_SIZE 64
58 #define MAX_TX_RING_SIZE 4096
59 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
62 /* level of occupied TX descriptors under which we wake up TX process */
63 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
66 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
69 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
72 /* Max length of transmit frame must be a multiple of 8 bytes */
73 #define MACB_TX_LEN_ALIGN 8
74 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
75 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
76 * false amba_error in TX path from the DMA assuming there is not enough
77 * space in the SRAM (16KB) even when there is.
79 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
82 #define MACB_NETIF_LSO NETIF_F_TSO
84 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
85 #define MACB_WOL_ENABLED (0x1 << 1)
87 /* Graceful stop timeouts in us. We should allow up to
88 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
90 #define MACB_HALT_TIMEOUT 1230
92 #define MACB_PM_TIMEOUT 100 /* ms */
94 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
96 /* DMA buffer descriptor might be different size
97 * depends on hardware configuration:
99 * 1. dma address width 32 bits:
100 * word 1: 32 bit address of Data Buffer
103 * 2. dma address width 64 bits:
104 * word 1: 32 bit address of Data Buffer
106 * word 3: upper 32 bit address of Data Buffer
109 * 3. dma address width 32 bits with hardware timestamping:
110 * word 1: 32 bit address of Data Buffer
112 * word 3: timestamp word 1
113 * word 4: timestamp word 2
115 * 4. dma address width 64 bits with hardware timestamping:
116 * word 1: 32 bit address of Data Buffer
118 * word 3: upper 32 bit address of Data Buffer
120 * word 5: timestamp word 1
121 * word 6: timestamp word 2
123 static unsigned int macb_dma_desc_get_size(struct macb *bp)
126 unsigned int desc_size;
128 switch (bp->hw_dma_cap) {
130 desc_size = sizeof(struct macb_dma_desc)
131 + sizeof(struct macb_dma_desc_64);
134 desc_size = sizeof(struct macb_dma_desc)
135 + sizeof(struct macb_dma_desc_ptp);
137 case HW_DMA_CAP_64B_PTP:
138 desc_size = sizeof(struct macb_dma_desc)
139 + sizeof(struct macb_dma_desc_64)
140 + sizeof(struct macb_dma_desc_ptp);
143 desc_size = sizeof(struct macb_dma_desc);
147 return sizeof(struct macb_dma_desc);
150 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
153 switch (bp->hw_dma_cap) {
158 case HW_DMA_CAP_64B_PTP:
168 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
169 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
171 return (struct macb_dma_desc_64 *)((void *)desc
172 + sizeof(struct macb_dma_desc));
176 /* Ring buffer accessors */
177 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
179 return index & (bp->tx_ring_size - 1);
182 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
185 index = macb_tx_ring_wrap(queue->bp, index);
186 index = macb_adj_dma_desc_idx(queue->bp, index);
187 return &queue->tx_ring[index];
190 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
193 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
196 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
200 offset = macb_tx_ring_wrap(queue->bp, index) *
201 macb_dma_desc_get_size(queue->bp);
203 return queue->tx_ring_dma + offset;
206 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
208 return index & (bp->rx_ring_size - 1);
211 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
213 index = macb_rx_ring_wrap(queue->bp, index);
214 index = macb_adj_dma_desc_idx(queue->bp, index);
215 return &queue->rx_ring[index];
218 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
220 return queue->rx_buffers + queue->bp->rx_buffer_size *
221 macb_rx_ring_wrap(queue->bp, index);
225 static u32 hw_readl_native(struct macb *bp, int offset)
227 return __raw_readl(bp->regs + offset);
230 static void hw_writel_native(struct macb *bp, int offset, u32 value)
232 __raw_writel(value, bp->regs + offset);
235 static u32 hw_readl(struct macb *bp, int offset)
237 return readl_relaxed(bp->regs + offset);
240 static void hw_writel(struct macb *bp, int offset, u32 value)
242 writel_relaxed(value, bp->regs + offset);
245 /* Find the CPU endianness by using the loopback bit of NCR register. When the
246 * CPU is in big endian we need to program swapped mode for management
249 static bool hw_is_native_io(void __iomem *addr)
251 u32 value = MACB_BIT(LLB);
253 __raw_writel(value, addr + MACB_NCR);
254 value = __raw_readl(addr + MACB_NCR);
256 /* Write 0 back to disable everything */
257 __raw_writel(0, addr + MACB_NCR);
259 return value == MACB_BIT(LLB);
262 static bool hw_is_gem(void __iomem *addr, bool native_io)
267 id = __raw_readl(addr + MACB_MID);
269 id = readl_relaxed(addr + MACB_MID);
271 return MACB_BFEXT(IDNUM, id) >= 0x2;
274 static void macb_set_hwaddr(struct macb *bp)
279 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
280 macb_or_gem_writel(bp, SA1B, bottom);
281 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
282 macb_or_gem_writel(bp, SA1T, top);
284 /* Clear unused address register sets */
285 macb_or_gem_writel(bp, SA2B, 0);
286 macb_or_gem_writel(bp, SA2T, 0);
287 macb_or_gem_writel(bp, SA3B, 0);
288 macb_or_gem_writel(bp, SA3T, 0);
289 macb_or_gem_writel(bp, SA4B, 0);
290 macb_or_gem_writel(bp, SA4T, 0);
293 static void macb_get_hwaddr(struct macb *bp)
300 /* Check all 4 address register for valid address */
301 for (i = 0; i < 4; i++) {
302 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
303 top = macb_or_gem_readl(bp, SA1T + i * 8);
305 addr[0] = bottom & 0xff;
306 addr[1] = (bottom >> 8) & 0xff;
307 addr[2] = (bottom >> 16) & 0xff;
308 addr[3] = (bottom >> 24) & 0xff;
309 addr[4] = top & 0xff;
310 addr[5] = (top >> 8) & 0xff;
312 if (is_valid_ether_addr(addr)) {
313 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
318 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
319 eth_hw_addr_random(bp->dev);
322 static int macb_mdio_wait_for_idle(struct macb *bp)
326 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
327 1, MACB_MDIO_TIMEOUT);
330 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
332 struct macb *bp = bus->priv;
335 status = pm_runtime_get_sync(&bp->pdev->dev);
337 pm_runtime_put_noidle(&bp->pdev->dev);
341 status = macb_mdio_wait_for_idle(bp);
345 if (regnum & MII_ADDR_C45) {
346 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
347 | MACB_BF(RW, MACB_MAN_C45_ADDR)
348 | MACB_BF(PHYA, mii_id)
349 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
350 | MACB_BF(DATA, regnum & 0xFFFF)
351 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
353 status = macb_mdio_wait_for_idle(bp);
357 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
358 | MACB_BF(RW, MACB_MAN_C45_READ)
359 | MACB_BF(PHYA, mii_id)
360 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
361 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
363 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
364 | MACB_BF(RW, MACB_MAN_C22_READ)
365 | MACB_BF(PHYA, mii_id)
366 | MACB_BF(REGA, regnum)
367 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
370 status = macb_mdio_wait_for_idle(bp);
374 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
377 pm_runtime_mark_last_busy(&bp->pdev->dev);
378 pm_runtime_put_autosuspend(&bp->pdev->dev);
383 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
386 struct macb *bp = bus->priv;
389 status = pm_runtime_get_sync(&bp->pdev->dev);
391 pm_runtime_put_noidle(&bp->pdev->dev);
395 status = macb_mdio_wait_for_idle(bp);
397 goto mdio_write_exit;
399 if (regnum & MII_ADDR_C45) {
400 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
401 | MACB_BF(RW, MACB_MAN_C45_ADDR)
402 | MACB_BF(PHYA, mii_id)
403 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
404 | MACB_BF(DATA, regnum & 0xFFFF)
405 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
407 status = macb_mdio_wait_for_idle(bp);
409 goto mdio_write_exit;
411 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
412 | MACB_BF(RW, MACB_MAN_C45_WRITE)
413 | MACB_BF(PHYA, mii_id)
414 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
415 | MACB_BF(CODE, MACB_MAN_C45_CODE)
416 | MACB_BF(DATA, value)));
418 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
419 | MACB_BF(RW, MACB_MAN_C22_WRITE)
420 | MACB_BF(PHYA, mii_id)
421 | MACB_BF(REGA, regnum)
422 | MACB_BF(CODE, MACB_MAN_C22_CODE)
423 | MACB_BF(DATA, value)));
426 status = macb_mdio_wait_for_idle(bp);
428 goto mdio_write_exit;
431 pm_runtime_mark_last_busy(&bp->pdev->dev);
432 pm_runtime_put_autosuspend(&bp->pdev->dev);
437 static void macb_init_buffers(struct macb *bp)
439 struct macb_queue *queue;
442 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
443 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
444 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
445 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
446 queue_writel(queue, RBQPH,
447 upper_32_bits(queue->rx_ring_dma));
449 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
450 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
451 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
452 queue_writel(queue, TBQPH,
453 upper_32_bits(queue->tx_ring_dma));
459 * macb_set_tx_clk() - Set a clock to a new frequency
460 * @clk: Pointer to the clock to change
461 * @speed: New frequency in Hz
462 * @dev: Pointer to the struct net_device
464 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
466 long ferr, rate, rate_rounded;
485 rate_rounded = clk_round_rate(clk, rate);
486 if (rate_rounded < 0)
489 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
492 ferr = abs(rate_rounded - rate);
493 ferr = DIV_ROUND_UP(ferr, rate / 100000);
495 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
498 if (clk_set_rate(clk, rate_rounded))
499 netdev_err(dev, "adjusting tx_clk failed.\n");
502 static void macb_validate(struct phylink_config *config,
503 unsigned long *supported,
504 struct phylink_link_state *state)
506 struct net_device *ndev = to_net_dev(config->dev);
507 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
508 struct macb *bp = netdev_priv(ndev);
510 /* We only support MII, RMII, GMII, RGMII & SGMII. */
511 if (state->interface != PHY_INTERFACE_MODE_NA &&
512 state->interface != PHY_INTERFACE_MODE_MII &&
513 state->interface != PHY_INTERFACE_MODE_RMII &&
514 state->interface != PHY_INTERFACE_MODE_GMII &&
515 state->interface != PHY_INTERFACE_MODE_SGMII &&
516 !phy_interface_mode_is_rgmii(state->interface)) {
517 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
521 if (!macb_is_gem(bp) &&
522 (state->interface == PHY_INTERFACE_MODE_GMII ||
523 phy_interface_mode_is_rgmii(state->interface))) {
524 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
528 phylink_set_port_modes(mask);
529 phylink_set(mask, Autoneg);
530 phylink_set(mask, Asym_Pause);
532 phylink_set(mask, 10baseT_Half);
533 phylink_set(mask, 10baseT_Full);
534 phylink_set(mask, 100baseT_Half);
535 phylink_set(mask, 100baseT_Full);
537 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
538 (state->interface == PHY_INTERFACE_MODE_NA ||
539 state->interface == PHY_INTERFACE_MODE_GMII ||
540 state->interface == PHY_INTERFACE_MODE_SGMII ||
541 phy_interface_mode_is_rgmii(state->interface))) {
542 phylink_set(mask, 1000baseT_Full);
543 phylink_set(mask, 1000baseX_Full);
545 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
546 phylink_set(mask, 1000baseT_Half);
549 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
550 bitmap_and(state->advertising, state->advertising, mask,
551 __ETHTOOL_LINK_MODE_MASK_NBITS);
554 static void macb_mac_pcs_get_state(struct phylink_config *config,
555 struct phylink_link_state *state)
560 static void macb_mac_an_restart(struct phylink_config *config)
565 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
566 const struct phylink_link_state *state)
568 struct net_device *ndev = to_net_dev(config->dev);
569 struct macb *bp = netdev_priv(ndev);
573 spin_lock_irqsave(&bp->lock, flags);
575 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
577 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
578 if (state->interface == PHY_INTERFACE_MODE_RMII)
579 ctrl |= MACB_BIT(RM9200_RMII);
580 } else if (macb_is_gem(bp)) {
581 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
583 if (state->interface == PHY_INTERFACE_MODE_SGMII)
584 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
587 /* Apply the new configuration, if any */
589 macb_or_gem_writel(bp, NCFGR, ctrl);
591 spin_unlock_irqrestore(&bp->lock, flags);
594 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
595 phy_interface_t interface)
597 struct net_device *ndev = to_net_dev(config->dev);
598 struct macb *bp = netdev_priv(ndev);
599 struct macb_queue *queue;
603 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
604 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
605 queue_writel(queue, IDR,
606 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
608 /* Disable Rx and Tx */
609 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
610 macb_writel(bp, NCR, ctrl);
612 netif_tx_stop_all_queues(ndev);
615 static void macb_mac_link_up(struct phylink_config *config,
616 struct phy_device *phy,
617 unsigned int mode, phy_interface_t interface,
618 int speed, int duplex,
619 bool tx_pause, bool rx_pause)
621 struct net_device *ndev = to_net_dev(config->dev);
622 struct macb *bp = netdev_priv(ndev);
623 struct macb_queue *queue;
628 spin_lock_irqsave(&bp->lock, flags);
630 ctrl = macb_or_gem_readl(bp, NCFGR);
632 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
634 if (speed == SPEED_100)
635 ctrl |= MACB_BIT(SPD);
638 ctrl |= MACB_BIT(FD);
640 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
641 ctrl &= ~MACB_BIT(PAE);
642 if (macb_is_gem(bp)) {
643 ctrl &= ~GEM_BIT(GBE);
645 if (speed == SPEED_1000)
646 ctrl |= GEM_BIT(GBE);
650 ctrl |= MACB_BIT(PAE);
652 macb_set_tx_clk(bp->tx_clk, speed, ndev);
654 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
655 * cleared the pipeline and control registers.
657 bp->macbgem_ops.mog_init_rings(bp);
658 macb_init_buffers(bp);
660 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
661 queue_writel(queue, IER,
662 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
665 macb_or_gem_writel(bp, NCFGR, ctrl);
667 spin_unlock_irqrestore(&bp->lock, flags);
669 /* Enable Rx and Tx */
670 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
672 netif_tx_wake_all_queues(ndev);
675 static const struct phylink_mac_ops macb_phylink_ops = {
676 .validate = macb_validate,
677 .mac_pcs_get_state = macb_mac_pcs_get_state,
678 .mac_an_restart = macb_mac_an_restart,
679 .mac_config = macb_mac_config,
680 .mac_link_down = macb_mac_link_down,
681 .mac_link_up = macb_mac_link_up,
684 static bool macb_phy_handle_exists(struct device_node *dn)
686 dn = of_parse_phandle(dn, "phy-handle", 0);
691 static int macb_phylink_connect(struct macb *bp)
693 struct device_node *dn = bp->pdev->dev.of_node;
694 struct net_device *dev = bp->dev;
695 struct phy_device *phydev;
699 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
701 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
702 phydev = phy_find_first(bp->mii_bus);
704 netdev_err(dev, "no PHY found\n");
708 /* attach the mac to the phy */
709 ret = phylink_connect_phy(bp->phylink, phydev);
713 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
717 phylink_start(bp->phylink);
722 /* based on au1000_eth. c*/
723 static int macb_mii_probe(struct net_device *dev)
725 struct macb *bp = netdev_priv(dev);
727 bp->phylink_config.dev = &dev->dev;
728 bp->phylink_config.type = PHYLINK_NETDEV;
730 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
731 bp->phy_interface, &macb_phylink_ops);
732 if (IS_ERR(bp->phylink)) {
733 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
734 PTR_ERR(bp->phylink));
735 return PTR_ERR(bp->phylink);
741 static int macb_mdiobus_register(struct macb *bp)
743 struct device_node *child, *np = bp->pdev->dev.of_node;
745 if (of_phy_is_fixed_link(np))
746 return mdiobus_register(bp->mii_bus);
748 /* Only create the PHY from the device tree if at least one PHY is
749 * described. Otherwise scan the entire MDIO bus. We do this to support
750 * old device tree that did not follow the best practices and did not
751 * describe their network PHYs.
753 for_each_available_child_of_node(np, child)
754 if (of_mdiobus_child_is_phy(child)) {
755 /* The loop increments the child refcount,
756 * decrement it before returning.
760 return of_mdiobus_register(bp->mii_bus, np);
763 return mdiobus_register(bp->mii_bus);
766 static int macb_mii_init(struct macb *bp)
770 /* Enable management port */
771 macb_writel(bp, NCR, MACB_BIT(MPE));
773 bp->mii_bus = mdiobus_alloc();
779 bp->mii_bus->name = "MACB_mii_bus";
780 bp->mii_bus->read = &macb_mdio_read;
781 bp->mii_bus->write = &macb_mdio_write;
782 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
783 bp->pdev->name, bp->pdev->id);
784 bp->mii_bus->priv = bp;
785 bp->mii_bus->parent = &bp->pdev->dev;
787 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
789 err = macb_mdiobus_register(bp);
791 goto err_out_free_mdiobus;
793 err = macb_mii_probe(bp->dev);
795 goto err_out_unregister_bus;
799 err_out_unregister_bus:
800 mdiobus_unregister(bp->mii_bus);
801 err_out_free_mdiobus:
802 mdiobus_free(bp->mii_bus);
807 static void macb_update_stats(struct macb *bp)
809 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
810 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
811 int offset = MACB_PFR;
813 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
815 for (; p < end; p++, offset += 4)
816 *p += bp->macb_reg_readl(bp, offset);
819 static int macb_halt_tx(struct macb *bp)
821 unsigned long halt_time, timeout;
824 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
826 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
829 status = macb_readl(bp, TSR);
830 if (!(status & MACB_BIT(TGO)))
834 } while (time_before(halt_time, timeout));
839 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
841 if (tx_skb->mapping) {
842 if (tx_skb->mapped_as_page)
843 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
844 tx_skb->size, DMA_TO_DEVICE);
846 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
847 tx_skb->size, DMA_TO_DEVICE);
852 dev_kfree_skb_any(tx_skb->skb);
857 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
859 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
860 struct macb_dma_desc_64 *desc_64;
862 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
863 desc_64 = macb_64b_desc(bp, desc);
864 desc_64->addrh = upper_32_bits(addr);
865 /* The low bits of RX address contain the RX_USED bit, clearing
866 * of which allows packet RX. Make sure the high bits are also
867 * visible to HW at that point.
872 desc->addr = lower_32_bits(addr);
875 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
878 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
879 struct macb_dma_desc_64 *desc_64;
881 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
882 desc_64 = macb_64b_desc(bp, desc);
883 addr = ((u64)(desc_64->addrh) << 32);
886 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
887 #ifdef CONFIG_MACB_USE_HWSTAMP
888 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
889 addr &= ~GEM_BIT(DMA_RXVALID);
894 static void macb_tx_error_task(struct work_struct *work)
896 struct macb_queue *queue = container_of(work, struct macb_queue,
898 struct macb *bp = queue->bp;
899 struct macb_tx_skb *tx_skb;
900 struct macb_dma_desc *desc;
905 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
906 (unsigned int)(queue - bp->queues),
907 queue->tx_tail, queue->tx_head);
909 /* Prevent the queue IRQ handlers from running: each of them may call
910 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
911 * As explained below, we have to halt the transmission before updating
912 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
913 * network engine about the macb/gem being halted.
915 spin_lock_irqsave(&bp->lock, flags);
917 /* Make sure nobody is trying to queue up new packets */
918 netif_tx_stop_all_queues(bp->dev);
920 /* Stop transmission now
921 * (in case we have just queued new packets)
922 * macb/gem must be halted to write TBQP register
924 if (macb_halt_tx(bp))
925 /* Just complain for now, reinitializing TX path can be good */
926 netdev_err(bp->dev, "BUG: halt tx timed out\n");
928 /* Treat frames in TX queue including the ones that caused the error.
929 * Free transmit buffers in upper layer.
931 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
934 desc = macb_tx_desc(queue, tail);
936 tx_skb = macb_tx_skb(queue, tail);
939 if (ctrl & MACB_BIT(TX_USED)) {
940 /* skb is set for the last buffer of the frame */
942 macb_tx_unmap(bp, tx_skb);
944 tx_skb = macb_tx_skb(queue, tail);
948 /* ctrl still refers to the first buffer descriptor
949 * since it's the only one written back by the hardware
951 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
952 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
953 macb_tx_ring_wrap(bp, tail),
955 bp->dev->stats.tx_packets++;
956 queue->stats.tx_packets++;
957 bp->dev->stats.tx_bytes += skb->len;
958 queue->stats.tx_bytes += skb->len;
961 /* "Buffers exhausted mid-frame" errors may only happen
962 * if the driver is buggy, so complain loudly about
963 * those. Statistics are updated by hardware.
965 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
967 "BUG: TX buffers exhausted mid-frame\n");
969 desc->ctrl = ctrl | MACB_BIT(TX_USED);
972 macb_tx_unmap(bp, tx_skb);
975 /* Set end of TX queue */
976 desc = macb_tx_desc(queue, 0);
977 macb_set_addr(bp, desc, 0);
978 desc->ctrl = MACB_BIT(TX_USED);
980 /* Make descriptor updates visible to hardware */
983 /* Reinitialize the TX desc queue */
984 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
985 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
986 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
987 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
989 /* Make TX ring reflect state of hardware */
993 /* Housework before enabling TX IRQ */
994 macb_writel(bp, TSR, macb_readl(bp, TSR));
995 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
997 /* Now we are ready to start transmission again */
998 netif_tx_start_all_queues(bp->dev);
999 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1001 spin_unlock_irqrestore(&bp->lock, flags);
1004 static void macb_tx_interrupt(struct macb_queue *queue)
1009 struct macb *bp = queue->bp;
1010 u16 queue_index = queue - bp->queues;
1012 status = macb_readl(bp, TSR);
1013 macb_writel(bp, TSR, status);
1015 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1016 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1018 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1019 (unsigned long)status);
1021 head = queue->tx_head;
1022 for (tail = queue->tx_tail; tail != head; tail++) {
1023 struct macb_tx_skb *tx_skb;
1024 struct sk_buff *skb;
1025 struct macb_dma_desc *desc;
1028 desc = macb_tx_desc(queue, tail);
1030 /* Make hw descriptor updates visible to CPU */
1035 /* TX_USED bit is only set by hardware on the very first buffer
1036 * descriptor of the transmitted frame.
1038 if (!(ctrl & MACB_BIT(TX_USED)))
1041 /* Process all buffers of the current transmitted frame */
1043 tx_skb = macb_tx_skb(queue, tail);
1046 /* First, update TX stats if needed */
1048 if (unlikely(skb_shinfo(skb)->tx_flags &
1050 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1051 /* skb now belongs to timestamp buffer
1052 * and will be removed later
1056 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1057 macb_tx_ring_wrap(bp, tail),
1059 bp->dev->stats.tx_packets++;
1060 queue->stats.tx_packets++;
1061 bp->dev->stats.tx_bytes += skb->len;
1062 queue->stats.tx_bytes += skb->len;
1065 /* Now we can safely release resources */
1066 macb_tx_unmap(bp, tx_skb);
1068 /* skb is set only for the last buffer of the frame.
1069 * WARNING: at this point skb has been freed by
1077 queue->tx_tail = tail;
1078 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1079 CIRC_CNT(queue->tx_head, queue->tx_tail,
1080 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1081 netif_wake_subqueue(bp->dev, queue_index);
1084 static void gem_rx_refill(struct macb_queue *queue)
1087 struct sk_buff *skb;
1089 struct macb *bp = queue->bp;
1090 struct macb_dma_desc *desc;
1092 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1093 bp->rx_ring_size) > 0) {
1094 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1096 /* Make hw descriptor updates visible to CPU */
1099 desc = macb_rx_desc(queue, entry);
1101 if (!queue->rx_skbuff[entry]) {
1102 /* allocate sk_buff for this free entry in ring */
1103 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1104 if (unlikely(!skb)) {
1106 "Unable to allocate sk_buff\n");
1110 /* now fill corresponding descriptor entry */
1111 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1114 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1119 queue->rx_skbuff[entry] = skb;
1121 if (entry == bp->rx_ring_size - 1)
1122 paddr |= MACB_BIT(RX_WRAP);
1124 /* Setting addr clears RX_USED and allows reception,
1125 * make sure ctrl is cleared first to avoid a race.
1128 macb_set_addr(bp, desc, paddr);
1130 /* properly align Ethernet header */
1131 skb_reserve(skb, NET_IP_ALIGN);
1135 desc->addr &= ~MACB_BIT(RX_USED);
1137 queue->rx_prepared_head++;
1140 /* Make descriptor updates visible to hardware */
1143 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1144 queue, queue->rx_prepared_head, queue->rx_tail);
1147 /* Mark DMA descriptors from begin up to and not including end as unused */
1148 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1153 for (frag = begin; frag != end; frag++) {
1154 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1156 desc->addr &= ~MACB_BIT(RX_USED);
1159 /* Make descriptor updates visible to hardware */
1162 /* When this happens, the hardware stats registers for
1163 * whatever caused this is updated, so we don't have to record
1168 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1171 struct macb *bp = queue->bp;
1174 struct sk_buff *skb;
1175 struct macb_dma_desc *desc;
1178 while (count < budget) {
1183 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1184 desc = macb_rx_desc(queue, entry);
1186 /* Make hw descriptor updates visible to CPU */
1189 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1190 addr = macb_get_addr(bp, desc);
1195 /* Ensure ctrl is at least as up-to-date as rxused */
1203 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1205 "not whole frame pointed by descriptor\n");
1206 bp->dev->stats.rx_dropped++;
1207 queue->stats.rx_dropped++;
1210 skb = queue->rx_skbuff[entry];
1211 if (unlikely(!skb)) {
1213 "inconsistent Rx descriptor chain\n");
1214 bp->dev->stats.rx_dropped++;
1215 queue->stats.rx_dropped++;
1218 /* now everything is ready for receiving packet */
1219 queue->rx_skbuff[entry] = NULL;
1220 len = ctrl & bp->rx_frm_len_mask;
1222 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1225 dma_unmap_single(&bp->pdev->dev, addr,
1226 bp->rx_buffer_size, DMA_FROM_DEVICE);
1228 skb->protocol = eth_type_trans(skb, bp->dev);
1229 skb_checksum_none_assert(skb);
1230 if (bp->dev->features & NETIF_F_RXCSUM &&
1231 !(bp->dev->flags & IFF_PROMISC) &&
1232 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1233 skb->ip_summed = CHECKSUM_UNNECESSARY;
1235 bp->dev->stats.rx_packets++;
1236 queue->stats.rx_packets++;
1237 bp->dev->stats.rx_bytes += skb->len;
1238 queue->stats.rx_bytes += skb->len;
1240 gem_ptp_do_rxstamp(bp, skb, desc);
1242 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1243 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1244 skb->len, skb->csum);
1245 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1246 skb_mac_header(skb), 16, true);
1247 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1248 skb->data, 32, true);
1251 napi_gro_receive(napi, skb);
1254 gem_rx_refill(queue);
1259 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1260 unsigned int first_frag, unsigned int last_frag)
1264 unsigned int offset;
1265 struct sk_buff *skb;
1266 struct macb_dma_desc *desc;
1267 struct macb *bp = queue->bp;
1269 desc = macb_rx_desc(queue, last_frag);
1270 len = desc->ctrl & bp->rx_frm_len_mask;
1272 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1273 macb_rx_ring_wrap(bp, first_frag),
1274 macb_rx_ring_wrap(bp, last_frag), len);
1276 /* The ethernet header starts NET_IP_ALIGN bytes into the
1277 * first buffer. Since the header is 14 bytes, this makes the
1278 * payload word-aligned.
1280 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1281 * the two padding bytes into the skb so that we avoid hitting
1282 * the slowpath in memcpy(), and pull them off afterwards.
1284 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1286 bp->dev->stats.rx_dropped++;
1287 for (frag = first_frag; ; frag++) {
1288 desc = macb_rx_desc(queue, frag);
1289 desc->addr &= ~MACB_BIT(RX_USED);
1290 if (frag == last_frag)
1294 /* Make descriptor updates visible to hardware */
1301 len += NET_IP_ALIGN;
1302 skb_checksum_none_assert(skb);
1305 for (frag = first_frag; ; frag++) {
1306 unsigned int frag_len = bp->rx_buffer_size;
1308 if (offset + frag_len > len) {
1309 if (unlikely(frag != last_frag)) {
1310 dev_kfree_skb_any(skb);
1313 frag_len = len - offset;
1315 skb_copy_to_linear_data_offset(skb, offset,
1316 macb_rx_buffer(queue, frag),
1318 offset += bp->rx_buffer_size;
1319 desc = macb_rx_desc(queue, frag);
1320 desc->addr &= ~MACB_BIT(RX_USED);
1322 if (frag == last_frag)
1326 /* Make descriptor updates visible to hardware */
1329 __skb_pull(skb, NET_IP_ALIGN);
1330 skb->protocol = eth_type_trans(skb, bp->dev);
1332 bp->dev->stats.rx_packets++;
1333 bp->dev->stats.rx_bytes += skb->len;
1334 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1335 skb->len, skb->csum);
1336 napi_gro_receive(napi, skb);
1341 static inline void macb_init_rx_ring(struct macb_queue *queue)
1343 struct macb *bp = queue->bp;
1345 struct macb_dma_desc *desc = NULL;
1348 addr = queue->rx_buffers_dma;
1349 for (i = 0; i < bp->rx_ring_size; i++) {
1350 desc = macb_rx_desc(queue, i);
1351 macb_set_addr(bp, desc, addr);
1353 addr += bp->rx_buffer_size;
1355 desc->addr |= MACB_BIT(RX_WRAP);
1359 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1362 struct macb *bp = queue->bp;
1363 bool reset_rx_queue = false;
1366 int first_frag = -1;
1368 for (tail = queue->rx_tail; budget > 0; tail++) {
1369 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1372 /* Make hw descriptor updates visible to CPU */
1375 if (!(desc->addr & MACB_BIT(RX_USED)))
1378 /* Ensure ctrl is at least as up-to-date as addr */
1383 if (ctrl & MACB_BIT(RX_SOF)) {
1384 if (first_frag != -1)
1385 discard_partial_frame(queue, first_frag, tail);
1389 if (ctrl & MACB_BIT(RX_EOF)) {
1392 if (unlikely(first_frag == -1)) {
1393 reset_rx_queue = true;
1397 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1399 if (unlikely(dropped < 0)) {
1400 reset_rx_queue = true;
1410 if (unlikely(reset_rx_queue)) {
1411 unsigned long flags;
1414 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1416 spin_lock_irqsave(&bp->lock, flags);
1418 ctrl = macb_readl(bp, NCR);
1419 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1421 macb_init_rx_ring(queue);
1422 queue_writel(queue, RBQP, queue->rx_ring_dma);
1424 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1426 spin_unlock_irqrestore(&bp->lock, flags);
1430 if (first_frag != -1)
1431 queue->rx_tail = first_frag;
1433 queue->rx_tail = tail;
1438 static int macb_poll(struct napi_struct *napi, int budget)
1440 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1441 struct macb *bp = queue->bp;
1445 status = macb_readl(bp, RSR);
1446 macb_writel(bp, RSR, status);
1448 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1449 (unsigned long)status, budget);
1451 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1452 if (work_done < budget) {
1453 napi_complete_done(napi, work_done);
1455 /* RSR bits only seem to propagate to raise interrupts when
1456 * interrupts are enabled at the time, so if bits are already
1457 * set due to packets received while interrupts were disabled,
1458 * they will not cause another interrupt to be generated when
1459 * interrupts are re-enabled.
1460 * Check for this case here. This has been seen to happen
1461 * around 30% of the time under heavy network load.
1463 status = macb_readl(bp, RSR);
1465 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1466 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1467 napi_reschedule(napi);
1469 queue_writel(queue, IER, bp->rx_intr_mask);
1471 /* In rare cases, packets could have been received in
1472 * the window between the check above and re-enabling
1473 * interrupts. Therefore, a double-check is required
1474 * to avoid losing a wakeup. This can potentially race
1475 * with the interrupt handler doing the same actions
1476 * if an interrupt is raised just after enabling them,
1477 * but this should be harmless.
1479 status = macb_readl(bp, RSR);
1480 if (unlikely(status)) {
1481 queue_writel(queue, IDR, bp->rx_intr_mask);
1482 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1483 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1484 napi_schedule(napi);
1489 /* TODO: Handle errors */
1494 static void macb_hresp_error_task(struct tasklet_struct *t)
1496 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1497 struct net_device *dev = bp->dev;
1498 struct macb_queue *queue;
1502 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1503 queue_writel(queue, IDR, bp->rx_intr_mask |
1507 ctrl = macb_readl(bp, NCR);
1508 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1509 macb_writel(bp, NCR, ctrl);
1511 netif_tx_stop_all_queues(dev);
1512 netif_carrier_off(dev);
1514 bp->macbgem_ops.mog_init_rings(bp);
1516 /* Initialize TX and RX buffers */
1517 macb_init_buffers(bp);
1519 /* Enable interrupts */
1520 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1521 queue_writel(queue, IER,
1526 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1527 macb_writel(bp, NCR, ctrl);
1529 netif_carrier_on(dev);
1530 netif_tx_start_all_queues(dev);
1533 static void macb_tx_restart(struct macb_queue *queue)
1535 unsigned int head = queue->tx_head;
1536 unsigned int tail = queue->tx_tail;
1537 struct macb *bp = queue->bp;
1538 unsigned int head_idx, tbqp;
1540 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1541 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1546 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1547 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1548 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, head));
1550 if (tbqp == head_idx)
1553 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1556 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1558 struct macb_queue *queue = dev_id;
1559 struct macb *bp = queue->bp;
1562 status = queue_readl(queue, ISR);
1564 if (unlikely(!status))
1567 spin_lock(&bp->lock);
1569 if (status & MACB_BIT(WOL)) {
1570 queue_writel(queue, IDR, MACB_BIT(WOL));
1571 macb_writel(bp, WOL, 0);
1572 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1573 (unsigned int)(queue - bp->queues),
1574 (unsigned long)status);
1575 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1576 queue_writel(queue, ISR, MACB_BIT(WOL));
1577 pm_wakeup_event(&bp->pdev->dev, 0);
1580 spin_unlock(&bp->lock);
1585 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1587 struct macb_queue *queue = dev_id;
1588 struct macb *bp = queue->bp;
1591 status = queue_readl(queue, ISR);
1593 if (unlikely(!status))
1596 spin_lock(&bp->lock);
1598 if (status & GEM_BIT(WOL)) {
1599 queue_writel(queue, IDR, GEM_BIT(WOL));
1600 gem_writel(bp, WOL, 0);
1601 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1602 (unsigned int)(queue - bp->queues),
1603 (unsigned long)status);
1604 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1605 queue_writel(queue, ISR, GEM_BIT(WOL));
1606 pm_wakeup_event(&bp->pdev->dev, 0);
1609 spin_unlock(&bp->lock);
1614 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1616 struct macb_queue *queue = dev_id;
1617 struct macb *bp = queue->bp;
1618 struct net_device *dev = bp->dev;
1621 status = queue_readl(queue, ISR);
1623 if (unlikely(!status))
1626 spin_lock(&bp->lock);
1629 /* close possible race with dev_close */
1630 if (unlikely(!netif_running(dev))) {
1631 queue_writel(queue, IDR, -1);
1632 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1633 queue_writel(queue, ISR, -1);
1637 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1638 (unsigned int)(queue - bp->queues),
1639 (unsigned long)status);
1641 if (status & bp->rx_intr_mask) {
1642 /* There's no point taking any more interrupts
1643 * until we have processed the buffers. The
1644 * scheduling call may fail if the poll routine
1645 * is already scheduled, so disable interrupts
1648 queue_writel(queue, IDR, bp->rx_intr_mask);
1649 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1650 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1652 if (napi_schedule_prep(&queue->napi)) {
1653 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1654 __napi_schedule(&queue->napi);
1658 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1659 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1660 schedule_work(&queue->tx_error_task);
1662 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1663 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1668 if (status & MACB_BIT(TCOMP))
1669 macb_tx_interrupt(queue);
1671 if (status & MACB_BIT(TXUBR))
1672 macb_tx_restart(queue);
1674 /* Link change detection isn't possible with RMII, so we'll
1675 * add that if/when we get our hands on a full-blown MII PHY.
1678 /* There is a hardware issue under heavy load where DMA can
1679 * stop, this causes endless "used buffer descriptor read"
1680 * interrupts but it can be cleared by re-enabling RX. See
1681 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1682 * section 16.7.4 for details. RXUBR is only enabled for
1683 * these two versions.
1685 if (status & MACB_BIT(RXUBR)) {
1686 ctrl = macb_readl(bp, NCR);
1687 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1689 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1691 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1692 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1695 if (status & MACB_BIT(ISR_ROVR)) {
1696 /* We missed at least one packet */
1697 if (macb_is_gem(bp))
1698 bp->hw_stats.gem.rx_overruns++;
1700 bp->hw_stats.macb.rx_overruns++;
1702 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1703 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1706 if (status & MACB_BIT(HRESP)) {
1707 tasklet_schedule(&bp->hresp_err_tasklet);
1708 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1710 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1711 queue_writel(queue, ISR, MACB_BIT(HRESP));
1713 status = queue_readl(queue, ISR);
1716 spin_unlock(&bp->lock);
1721 #ifdef CONFIG_NET_POLL_CONTROLLER
1722 /* Polling receive - used by netconsole and other diagnostic tools
1723 * to allow network i/o with interrupts disabled.
1725 static void macb_poll_controller(struct net_device *dev)
1727 struct macb *bp = netdev_priv(dev);
1728 struct macb_queue *queue;
1729 unsigned long flags;
1732 local_irq_save(flags);
1733 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1734 macb_interrupt(dev->irq, queue);
1735 local_irq_restore(flags);
1739 static unsigned int macb_tx_map(struct macb *bp,
1740 struct macb_queue *queue,
1741 struct sk_buff *skb,
1742 unsigned int hdrlen)
1745 unsigned int len, entry, i, tx_head = queue->tx_head;
1746 struct macb_tx_skb *tx_skb = NULL;
1747 struct macb_dma_desc *desc;
1748 unsigned int offset, size, count = 0;
1749 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1750 unsigned int eof = 1, mss_mfs = 0;
1751 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1754 if (skb_shinfo(skb)->gso_size != 0) {
1755 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1757 lso_ctrl = MACB_LSO_UFO_ENABLE;
1760 lso_ctrl = MACB_LSO_TSO_ENABLE;
1763 /* First, map non-paged data */
1764 len = skb_headlen(skb);
1766 /* first buffer length */
1771 entry = macb_tx_ring_wrap(bp, tx_head);
1772 tx_skb = &queue->tx_skb[entry];
1774 mapping = dma_map_single(&bp->pdev->dev,
1776 size, DMA_TO_DEVICE);
1777 if (dma_mapping_error(&bp->pdev->dev, mapping))
1780 /* Save info to properly release resources */
1782 tx_skb->mapping = mapping;
1783 tx_skb->size = size;
1784 tx_skb->mapped_as_page = false;
1791 size = min(len, bp->max_tx_length);
1794 /* Then, map paged data from fragments */
1795 for (f = 0; f < nr_frags; f++) {
1796 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1798 len = skb_frag_size(frag);
1801 size = min(len, bp->max_tx_length);
1802 entry = macb_tx_ring_wrap(bp, tx_head);
1803 tx_skb = &queue->tx_skb[entry];
1805 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1806 offset, size, DMA_TO_DEVICE);
1807 if (dma_mapping_error(&bp->pdev->dev, mapping))
1810 /* Save info to properly release resources */
1812 tx_skb->mapping = mapping;
1813 tx_skb->size = size;
1814 tx_skb->mapped_as_page = true;
1823 /* Should never happen */
1824 if (unlikely(!tx_skb)) {
1825 netdev_err(bp->dev, "BUG! empty skb!\n");
1829 /* This is the last buffer of the frame: save socket buffer */
1832 /* Update TX ring: update buffer descriptors in reverse order
1833 * to avoid race condition
1836 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1837 * to set the end of TX queue
1840 entry = macb_tx_ring_wrap(bp, i);
1841 ctrl = MACB_BIT(TX_USED);
1842 desc = macb_tx_desc(queue, entry);
1846 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1847 /* include header and FCS in value given to h/w */
1848 mss_mfs = skb_shinfo(skb)->gso_size +
1849 skb_transport_offset(skb) +
1852 mss_mfs = skb_shinfo(skb)->gso_size;
1853 /* TCP Sequence Number Source Select
1854 * can be set only for TSO
1862 entry = macb_tx_ring_wrap(bp, i);
1863 tx_skb = &queue->tx_skb[entry];
1864 desc = macb_tx_desc(queue, entry);
1866 ctrl = (u32)tx_skb->size;
1868 ctrl |= MACB_BIT(TX_LAST);
1871 if (unlikely(entry == (bp->tx_ring_size - 1)))
1872 ctrl |= MACB_BIT(TX_WRAP);
1874 /* First descriptor is header descriptor */
1875 if (i == queue->tx_head) {
1876 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1877 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1878 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1879 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1880 ctrl |= MACB_BIT(TX_NOCRC);
1882 /* Only set MSS/MFS on payload descriptors
1883 * (second or later descriptor)
1885 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1887 /* Set TX buffer descriptor */
1888 macb_set_addr(bp, desc, tx_skb->mapping);
1889 /* desc->addr must be visible to hardware before clearing
1890 * 'TX_USED' bit in desc->ctrl.
1894 } while (i != queue->tx_head);
1896 queue->tx_head = tx_head;
1901 netdev_err(bp->dev, "TX DMA map failed\n");
1903 for (i = queue->tx_head; i != tx_head; i++) {
1904 tx_skb = macb_tx_skb(queue, i);
1906 macb_tx_unmap(bp, tx_skb);
1912 static netdev_features_t macb_features_check(struct sk_buff *skb,
1913 struct net_device *dev,
1914 netdev_features_t features)
1916 unsigned int nr_frags, f;
1917 unsigned int hdrlen;
1919 /* Validate LSO compatibility */
1921 /* there is only one buffer or protocol is not UDP */
1922 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1925 /* length of header */
1926 hdrlen = skb_transport_offset(skb);
1929 * When software supplies two or more payload buffers all payload buffers
1930 * apart from the last must be a multiple of 8 bytes in size.
1932 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1933 return features & ~MACB_NETIF_LSO;
1935 nr_frags = skb_shinfo(skb)->nr_frags;
1936 /* No need to check last fragment */
1938 for (f = 0; f < nr_frags; f++) {
1939 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1941 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1942 return features & ~MACB_NETIF_LSO;
1947 static inline int macb_clear_csum(struct sk_buff *skb)
1949 /* no change for packets without checksum offloading */
1950 if (skb->ip_summed != CHECKSUM_PARTIAL)
1953 /* make sure we can modify the header */
1954 if (unlikely(skb_cow_head(skb, 0)))
1957 /* initialize checksum field
1958 * This is required - at least for Zynq, which otherwise calculates
1959 * wrong UDP header checksums for UDP packets with UDP data len <=2
1961 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1965 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1967 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
1968 skb_is_nonlinear(*skb);
1969 int padlen = ETH_ZLEN - (*skb)->len;
1970 int tailroom = skb_tailroom(*skb);
1971 struct sk_buff *nskb;
1974 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1975 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1976 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1980 /* FCS could be appeded to tailroom. */
1981 if (tailroom >= ETH_FCS_LEN)
1983 /* No room for FCS, need to reallocate skb. */
1985 padlen = ETH_FCS_LEN;
1987 /* Add room for FCS. */
1988 padlen += ETH_FCS_LEN;
1991 if (cloned || tailroom < padlen) {
1992 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1996 dev_consume_skb_any(*skb);
2000 if (padlen > ETH_FCS_LEN)
2001 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2004 /* set FCS to packet */
2005 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2008 skb_put_u8(*skb, fcs & 0xff);
2009 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2010 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2011 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2016 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2018 u16 queue_index = skb_get_queue_mapping(skb);
2019 struct macb *bp = netdev_priv(dev);
2020 struct macb_queue *queue = &bp->queues[queue_index];
2021 unsigned long flags;
2022 unsigned int desc_cnt, nr_frags, frag_size, f;
2023 unsigned int hdrlen;
2025 netdev_tx_t ret = NETDEV_TX_OK;
2027 if (macb_clear_csum(skb)) {
2028 dev_kfree_skb_any(skb);
2032 if (macb_pad_and_fcs(&skb, dev)) {
2033 dev_kfree_skb_any(skb);
2037 is_lso = (skb_shinfo(skb)->gso_size != 0);
2040 /* length of headers */
2041 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2042 /* only queue eth + ip headers separately for UDP */
2043 hdrlen = skb_transport_offset(skb);
2045 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2046 if (skb_headlen(skb) < hdrlen) {
2047 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2048 /* if this is required, would need to copy to single buffer */
2049 return NETDEV_TX_BUSY;
2052 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2054 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2055 netdev_vdbg(bp->dev,
2056 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2057 queue_index, skb->len, skb->head, skb->data,
2058 skb_tail_pointer(skb), skb_end_pointer(skb));
2059 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2060 skb->data, 16, true);
2063 /* Count how many TX buffer descriptors are needed to send this
2064 * socket buffer: skb fragments of jumbo frames may need to be
2065 * split into many buffer descriptors.
2067 if (is_lso && (skb_headlen(skb) > hdrlen))
2068 /* extra header descriptor if also payload in first buffer */
2069 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2071 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2072 nr_frags = skb_shinfo(skb)->nr_frags;
2073 for (f = 0; f < nr_frags; f++) {
2074 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2075 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2078 spin_lock_irqsave(&bp->lock, flags);
2080 /* This is a hard error, log it. */
2081 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2082 bp->tx_ring_size) < desc_cnt) {
2083 netif_stop_subqueue(dev, queue_index);
2084 spin_unlock_irqrestore(&bp->lock, flags);
2085 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2086 queue->tx_head, queue->tx_tail);
2087 return NETDEV_TX_BUSY;
2090 /* Map socket buffer for DMA transfer */
2091 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2092 dev_kfree_skb_any(skb);
2096 /* Make newly initialized descriptor visible to hardware */
2098 skb_tx_timestamp(skb);
2100 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2102 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2103 netif_stop_subqueue(dev, queue_index);
2106 spin_unlock_irqrestore(&bp->lock, flags);
2111 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2113 if (!macb_is_gem(bp)) {
2114 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2116 bp->rx_buffer_size = size;
2118 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2120 "RX buffer must be multiple of %d bytes, expanding\n",
2121 RX_BUFFER_MULTIPLE);
2122 bp->rx_buffer_size =
2123 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2127 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2128 bp->dev->mtu, bp->rx_buffer_size);
2131 static void gem_free_rx_buffers(struct macb *bp)
2133 struct sk_buff *skb;
2134 struct macb_dma_desc *desc;
2135 struct macb_queue *queue;
2140 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2141 if (!queue->rx_skbuff)
2144 for (i = 0; i < bp->rx_ring_size; i++) {
2145 skb = queue->rx_skbuff[i];
2150 desc = macb_rx_desc(queue, i);
2151 addr = macb_get_addr(bp, desc);
2153 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2155 dev_kfree_skb_any(skb);
2159 kfree(queue->rx_skbuff);
2160 queue->rx_skbuff = NULL;
2164 static void macb_free_rx_buffers(struct macb *bp)
2166 struct macb_queue *queue = &bp->queues[0];
2168 if (queue->rx_buffers) {
2169 dma_free_coherent(&bp->pdev->dev,
2170 bp->rx_ring_size * bp->rx_buffer_size,
2171 queue->rx_buffers, queue->rx_buffers_dma);
2172 queue->rx_buffers = NULL;
2176 static void macb_free_consistent(struct macb *bp)
2178 struct macb_queue *queue;
2182 bp->macbgem_ops.mog_free_rx_buffers(bp);
2184 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2185 kfree(queue->tx_skb);
2186 queue->tx_skb = NULL;
2187 if (queue->tx_ring) {
2188 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2189 dma_free_coherent(&bp->pdev->dev, size,
2190 queue->tx_ring, queue->tx_ring_dma);
2191 queue->tx_ring = NULL;
2193 if (queue->rx_ring) {
2194 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2195 dma_free_coherent(&bp->pdev->dev, size,
2196 queue->rx_ring, queue->rx_ring_dma);
2197 queue->rx_ring = NULL;
2202 static int gem_alloc_rx_buffers(struct macb *bp)
2204 struct macb_queue *queue;
2208 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2209 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2210 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2211 if (!queue->rx_skbuff)
2215 "Allocated %d RX struct sk_buff entries at %p\n",
2216 bp->rx_ring_size, queue->rx_skbuff);
2221 static int macb_alloc_rx_buffers(struct macb *bp)
2223 struct macb_queue *queue = &bp->queues[0];
2226 size = bp->rx_ring_size * bp->rx_buffer_size;
2227 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2228 &queue->rx_buffers_dma, GFP_KERNEL);
2229 if (!queue->rx_buffers)
2233 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2234 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2238 static int macb_alloc_consistent(struct macb *bp)
2240 struct macb_queue *queue;
2244 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2245 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2246 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2247 &queue->tx_ring_dma,
2249 if (!queue->tx_ring)
2252 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2253 q, size, (unsigned long)queue->tx_ring_dma,
2256 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2257 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2261 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2262 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2263 &queue->rx_ring_dma, GFP_KERNEL);
2264 if (!queue->rx_ring)
2267 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2268 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2270 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2276 macb_free_consistent(bp);
2280 static void gem_init_rings(struct macb *bp)
2282 struct macb_queue *queue;
2283 struct macb_dma_desc *desc = NULL;
2287 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2288 for (i = 0; i < bp->tx_ring_size; i++) {
2289 desc = macb_tx_desc(queue, i);
2290 macb_set_addr(bp, desc, 0);
2291 desc->ctrl = MACB_BIT(TX_USED);
2293 desc->ctrl |= MACB_BIT(TX_WRAP);
2298 queue->rx_prepared_head = 0;
2300 gem_rx_refill(queue);
2305 static void macb_init_rings(struct macb *bp)
2308 struct macb_dma_desc *desc = NULL;
2310 macb_init_rx_ring(&bp->queues[0]);
2312 for (i = 0; i < bp->tx_ring_size; i++) {
2313 desc = macb_tx_desc(&bp->queues[0], i);
2314 macb_set_addr(bp, desc, 0);
2315 desc->ctrl = MACB_BIT(TX_USED);
2317 bp->queues[0].tx_head = 0;
2318 bp->queues[0].tx_tail = 0;
2319 desc->ctrl |= MACB_BIT(TX_WRAP);
2322 static void macb_reset_hw(struct macb *bp)
2324 struct macb_queue *queue;
2326 u32 ctrl = macb_readl(bp, NCR);
2328 /* Disable RX and TX (XXX: Should we halt the transmission
2331 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2333 /* Clear the stats registers (XXX: Update stats first?) */
2334 ctrl |= MACB_BIT(CLRSTAT);
2336 macb_writel(bp, NCR, ctrl);
2338 /* Clear all status flags */
2339 macb_writel(bp, TSR, -1);
2340 macb_writel(bp, RSR, -1);
2342 /* Disable all interrupts */
2343 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2344 queue_writel(queue, IDR, -1);
2345 queue_readl(queue, ISR);
2346 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2347 queue_writel(queue, ISR, -1);
2351 static u32 gem_mdc_clk_div(struct macb *bp)
2354 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2356 if (pclk_hz <= 20000000)
2357 config = GEM_BF(CLK, GEM_CLK_DIV8);
2358 else if (pclk_hz <= 40000000)
2359 config = GEM_BF(CLK, GEM_CLK_DIV16);
2360 else if (pclk_hz <= 80000000)
2361 config = GEM_BF(CLK, GEM_CLK_DIV32);
2362 else if (pclk_hz <= 120000000)
2363 config = GEM_BF(CLK, GEM_CLK_DIV48);
2364 else if (pclk_hz <= 160000000)
2365 config = GEM_BF(CLK, GEM_CLK_DIV64);
2367 config = GEM_BF(CLK, GEM_CLK_DIV96);
2372 static u32 macb_mdc_clk_div(struct macb *bp)
2375 unsigned long pclk_hz;
2377 if (macb_is_gem(bp))
2378 return gem_mdc_clk_div(bp);
2380 pclk_hz = clk_get_rate(bp->pclk);
2381 if (pclk_hz <= 20000000)
2382 config = MACB_BF(CLK, MACB_CLK_DIV8);
2383 else if (pclk_hz <= 40000000)
2384 config = MACB_BF(CLK, MACB_CLK_DIV16);
2385 else if (pclk_hz <= 80000000)
2386 config = MACB_BF(CLK, MACB_CLK_DIV32);
2388 config = MACB_BF(CLK, MACB_CLK_DIV64);
2393 /* Get the DMA bus width field of the network configuration register that we
2394 * should program. We find the width from decoding the design configuration
2395 * register to find the maximum supported data bus width.
2397 static u32 macb_dbw(struct macb *bp)
2399 if (!macb_is_gem(bp))
2402 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2404 return GEM_BF(DBW, GEM_DBW128);
2406 return GEM_BF(DBW, GEM_DBW64);
2409 return GEM_BF(DBW, GEM_DBW32);
2413 /* Configure the receive DMA engine
2414 * - use the correct receive buffer size
2415 * - set best burst length for DMA operations
2416 * (if not supported by FIFO, it will fallback to default)
2417 * - set both rx/tx packet buffers to full memory size
2418 * These are configurable parameters for GEM.
2420 static void macb_configure_dma(struct macb *bp)
2422 struct macb_queue *queue;
2427 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2428 if (macb_is_gem(bp)) {
2429 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2430 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2432 queue_writel(queue, RBQS, buffer_size);
2434 dmacfg |= GEM_BF(RXBS, buffer_size);
2436 if (bp->dma_burst_length)
2437 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2438 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2439 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2442 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2444 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2446 if (bp->dev->features & NETIF_F_HW_CSUM)
2447 dmacfg |= GEM_BIT(TXCOEN);
2449 dmacfg &= ~GEM_BIT(TXCOEN);
2451 dmacfg &= ~GEM_BIT(ADDR64);
2452 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2453 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2454 dmacfg |= GEM_BIT(ADDR64);
2456 #ifdef CONFIG_MACB_USE_HWSTAMP
2457 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2458 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2460 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2462 gem_writel(bp, DMACFG, dmacfg);
2466 static void macb_init_hw(struct macb *bp)
2471 macb_set_hwaddr(bp);
2473 config = macb_mdc_clk_div(bp);
2474 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2475 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2476 if (bp->caps & MACB_CAPS_JUMBO)
2477 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2479 config |= MACB_BIT(BIG); /* Receive oversized frames */
2480 if (bp->dev->flags & IFF_PROMISC)
2481 config |= MACB_BIT(CAF); /* Copy All Frames */
2482 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2483 config |= GEM_BIT(RXCOEN);
2484 if (!(bp->dev->flags & IFF_BROADCAST))
2485 config |= MACB_BIT(NBC); /* No BroadCast */
2486 config |= macb_dbw(bp);
2487 macb_writel(bp, NCFGR, config);
2488 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2489 gem_writel(bp, JML, bp->jumbo_max_len);
2490 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2491 if (bp->caps & MACB_CAPS_JUMBO)
2492 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2494 macb_configure_dma(bp);
2497 /* The hash address register is 64 bits long and takes up two
2498 * locations in the memory map. The least significant bits are stored
2499 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2501 * The unicast hash enable and the multicast hash enable bits in the
2502 * network configuration register enable the reception of hash matched
2503 * frames. The destination address is reduced to a 6 bit index into
2504 * the 64 bit hash register using the following hash function. The
2505 * hash function is an exclusive or of every sixth bit of the
2506 * destination address.
2508 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2509 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2510 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2511 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2512 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2513 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2515 * da[0] represents the least significant bit of the first byte
2516 * received, that is, the multicast/unicast indicator, and da[47]
2517 * represents the most significant bit of the last byte received. If
2518 * the hash index, hi[n], points to a bit that is set in the hash
2519 * register then the frame will be matched according to whether the
2520 * frame is multicast or unicast. A multicast match will be signalled
2521 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2522 * index points to a bit set in the hash register. A unicast match
2523 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2524 * and the hash index points to a bit set in the hash register. To
2525 * receive all multicast frames, the hash register should be set with
2526 * all ones and the multicast hash enable bit should be set in the
2527 * network configuration register.
2530 static inline int hash_bit_value(int bitnr, __u8 *addr)
2532 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2537 /* Return the hash index value for the specified address. */
2538 static int hash_get_index(__u8 *addr)
2543 for (j = 0; j < 6; j++) {
2544 for (i = 0, bitval = 0; i < 8; i++)
2545 bitval ^= hash_bit_value(i * 6 + j, addr);
2547 hash_index |= (bitval << j);
2553 /* Add multicast addresses to the internal multicast-hash table. */
2554 static void macb_sethashtable(struct net_device *dev)
2556 struct netdev_hw_addr *ha;
2557 unsigned long mc_filter[2];
2559 struct macb *bp = netdev_priv(dev);
2564 netdev_for_each_mc_addr(ha, dev) {
2565 bitnr = hash_get_index(ha->addr);
2566 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2569 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2570 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2573 /* Enable/Disable promiscuous and multicast modes. */
2574 static void macb_set_rx_mode(struct net_device *dev)
2577 struct macb *bp = netdev_priv(dev);
2579 cfg = macb_readl(bp, NCFGR);
2581 if (dev->flags & IFF_PROMISC) {
2582 /* Enable promiscuous mode */
2583 cfg |= MACB_BIT(CAF);
2585 /* Disable RX checksum offload */
2586 if (macb_is_gem(bp))
2587 cfg &= ~GEM_BIT(RXCOEN);
2589 /* Disable promiscuous mode */
2590 cfg &= ~MACB_BIT(CAF);
2592 /* Enable RX checksum offload only if requested */
2593 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2594 cfg |= GEM_BIT(RXCOEN);
2597 if (dev->flags & IFF_ALLMULTI) {
2598 /* Enable all multicast mode */
2599 macb_or_gem_writel(bp, HRB, -1);
2600 macb_or_gem_writel(bp, HRT, -1);
2601 cfg |= MACB_BIT(NCFGR_MTI);
2602 } else if (!netdev_mc_empty(dev)) {
2603 /* Enable specific multicasts */
2604 macb_sethashtable(dev);
2605 cfg |= MACB_BIT(NCFGR_MTI);
2606 } else if (dev->flags & (~IFF_ALLMULTI)) {
2607 /* Disable all multicast mode */
2608 macb_or_gem_writel(bp, HRB, 0);
2609 macb_or_gem_writel(bp, HRT, 0);
2610 cfg &= ~MACB_BIT(NCFGR_MTI);
2613 macb_writel(bp, NCFGR, cfg);
2616 static int macb_open(struct net_device *dev)
2618 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2619 struct macb *bp = netdev_priv(dev);
2620 struct macb_queue *queue;
2624 netdev_dbg(bp->dev, "open\n");
2626 err = pm_runtime_get_sync(&bp->pdev->dev);
2630 /* RX buffers initialization */
2631 macb_init_rx_buffer_size(bp, bufsz);
2633 err = macb_alloc_consistent(bp);
2635 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2640 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2641 napi_enable(&queue->napi);
2645 err = macb_phylink_connect(bp);
2649 netif_tx_start_all_queues(dev);
2652 bp->ptp_info->ptp_init(dev);
2658 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2659 napi_disable(&queue->napi);
2660 macb_free_consistent(bp);
2662 pm_runtime_put_sync(&bp->pdev->dev);
2666 static int macb_close(struct net_device *dev)
2668 struct macb *bp = netdev_priv(dev);
2669 struct macb_queue *queue;
2670 unsigned long flags;
2673 netif_tx_stop_all_queues(dev);
2675 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2676 napi_disable(&queue->napi);
2678 phylink_stop(bp->phylink);
2679 phylink_disconnect_phy(bp->phylink);
2681 spin_lock_irqsave(&bp->lock, flags);
2683 netif_carrier_off(dev);
2684 spin_unlock_irqrestore(&bp->lock, flags);
2686 macb_free_consistent(bp);
2689 bp->ptp_info->ptp_remove(dev);
2691 pm_runtime_put(&bp->pdev->dev);
2696 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2698 if (netif_running(dev))
2706 static void gem_update_stats(struct macb *bp)
2708 struct macb_queue *queue;
2709 unsigned int i, q, idx;
2710 unsigned long *stat;
2712 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2714 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2715 u32 offset = gem_statistics[i].offset;
2716 u64 val = bp->macb_reg_readl(bp, offset);
2718 bp->ethtool_stats[i] += val;
2721 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2722 /* Add GEM_OCTTXH, GEM_OCTRXH */
2723 val = bp->macb_reg_readl(bp, offset + 4);
2724 bp->ethtool_stats[i] += ((u64)val) << 32;
2729 idx = GEM_STATS_LEN;
2730 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2731 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2732 bp->ethtool_stats[idx++] = *stat;
2735 static struct net_device_stats *gem_get_stats(struct macb *bp)
2737 struct gem_stats *hwstat = &bp->hw_stats.gem;
2738 struct net_device_stats *nstat = &bp->dev->stats;
2740 if (!netif_running(bp->dev))
2743 gem_update_stats(bp);
2745 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2746 hwstat->rx_alignment_errors +
2747 hwstat->rx_resource_errors +
2748 hwstat->rx_overruns +
2749 hwstat->rx_oversize_frames +
2750 hwstat->rx_jabbers +
2751 hwstat->rx_undersized_frames +
2752 hwstat->rx_length_field_frame_errors);
2753 nstat->tx_errors = (hwstat->tx_late_collisions +
2754 hwstat->tx_excessive_collisions +
2755 hwstat->tx_underrun +
2756 hwstat->tx_carrier_sense_errors);
2757 nstat->multicast = hwstat->rx_multicast_frames;
2758 nstat->collisions = (hwstat->tx_single_collision_frames +
2759 hwstat->tx_multiple_collision_frames +
2760 hwstat->tx_excessive_collisions);
2761 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2762 hwstat->rx_jabbers +
2763 hwstat->rx_undersized_frames +
2764 hwstat->rx_length_field_frame_errors);
2765 nstat->rx_over_errors = hwstat->rx_resource_errors;
2766 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2767 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2768 nstat->rx_fifo_errors = hwstat->rx_overruns;
2769 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2770 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2771 nstat->tx_fifo_errors = hwstat->tx_underrun;
2776 static void gem_get_ethtool_stats(struct net_device *dev,
2777 struct ethtool_stats *stats, u64 *data)
2781 bp = netdev_priv(dev);
2782 gem_update_stats(bp);
2783 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2784 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2787 static int gem_get_sset_count(struct net_device *dev, int sset)
2789 struct macb *bp = netdev_priv(dev);
2793 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2799 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2801 char stat_string[ETH_GSTRING_LEN];
2802 struct macb *bp = netdev_priv(dev);
2803 struct macb_queue *queue;
2809 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2810 memcpy(p, gem_statistics[i].stat_string,
2813 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2814 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2815 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2816 q, queue_statistics[i].stat_string);
2817 memcpy(p, stat_string, ETH_GSTRING_LEN);
2824 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2826 struct macb *bp = netdev_priv(dev);
2827 struct net_device_stats *nstat = &bp->dev->stats;
2828 struct macb_stats *hwstat = &bp->hw_stats.macb;
2830 if (macb_is_gem(bp))
2831 return gem_get_stats(bp);
2833 /* read stats from hardware */
2834 macb_update_stats(bp);
2836 /* Convert HW stats into netdevice stats */
2837 nstat->rx_errors = (hwstat->rx_fcs_errors +
2838 hwstat->rx_align_errors +
2839 hwstat->rx_resource_errors +
2840 hwstat->rx_overruns +
2841 hwstat->rx_oversize_pkts +
2842 hwstat->rx_jabbers +
2843 hwstat->rx_undersize_pkts +
2844 hwstat->rx_length_mismatch);
2845 nstat->tx_errors = (hwstat->tx_late_cols +
2846 hwstat->tx_excessive_cols +
2847 hwstat->tx_underruns +
2848 hwstat->tx_carrier_errors +
2849 hwstat->sqe_test_errors);
2850 nstat->collisions = (hwstat->tx_single_cols +
2851 hwstat->tx_multiple_cols +
2852 hwstat->tx_excessive_cols);
2853 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2854 hwstat->rx_jabbers +
2855 hwstat->rx_undersize_pkts +
2856 hwstat->rx_length_mismatch);
2857 nstat->rx_over_errors = hwstat->rx_resource_errors +
2858 hwstat->rx_overruns;
2859 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2860 nstat->rx_frame_errors = hwstat->rx_align_errors;
2861 nstat->rx_fifo_errors = hwstat->rx_overruns;
2862 /* XXX: What does "missed" mean? */
2863 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2864 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2865 nstat->tx_fifo_errors = hwstat->tx_underruns;
2866 /* Don't know about heartbeat or window errors... */
2871 static int macb_get_regs_len(struct net_device *netdev)
2873 return MACB_GREGS_NBR * sizeof(u32);
2876 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2879 struct macb *bp = netdev_priv(dev);
2880 unsigned int tail, head;
2883 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2884 | MACB_GREGS_VERSION;
2886 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2887 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2889 regs_buff[0] = macb_readl(bp, NCR);
2890 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2891 regs_buff[2] = macb_readl(bp, NSR);
2892 regs_buff[3] = macb_readl(bp, TSR);
2893 regs_buff[4] = macb_readl(bp, RBQP);
2894 regs_buff[5] = macb_readl(bp, TBQP);
2895 regs_buff[6] = macb_readl(bp, RSR);
2896 regs_buff[7] = macb_readl(bp, IMR);
2898 regs_buff[8] = tail;
2899 regs_buff[9] = head;
2900 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2901 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2903 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2904 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2905 if (macb_is_gem(bp))
2906 regs_buff[13] = gem_readl(bp, DMACFG);
2909 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2911 struct macb *bp = netdev_priv(netdev);
2913 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2914 phylink_ethtool_get_wol(bp->phylink, wol);
2915 wol->supported |= WAKE_MAGIC;
2917 if (bp->wol & MACB_WOL_ENABLED)
2918 wol->wolopts |= WAKE_MAGIC;
2922 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2924 struct macb *bp = netdev_priv(netdev);
2927 /* Pass the order to phylink layer */
2928 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2929 /* Don't manage WoL on MAC if handled by the PHY
2930 * or if there's a failure in talking to the PHY
2932 if (!ret || ret != -EOPNOTSUPP)
2935 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2936 (wol->wolopts & ~WAKE_MAGIC))
2939 if (wol->wolopts & WAKE_MAGIC)
2940 bp->wol |= MACB_WOL_ENABLED;
2942 bp->wol &= ~MACB_WOL_ENABLED;
2944 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2949 static int macb_get_link_ksettings(struct net_device *netdev,
2950 struct ethtool_link_ksettings *kset)
2952 struct macb *bp = netdev_priv(netdev);
2954 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2957 static int macb_set_link_ksettings(struct net_device *netdev,
2958 const struct ethtool_link_ksettings *kset)
2960 struct macb *bp = netdev_priv(netdev);
2962 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2965 static void macb_get_ringparam(struct net_device *netdev,
2966 struct ethtool_ringparam *ring)
2968 struct macb *bp = netdev_priv(netdev);
2970 ring->rx_max_pending = MAX_RX_RING_SIZE;
2971 ring->tx_max_pending = MAX_TX_RING_SIZE;
2973 ring->rx_pending = bp->rx_ring_size;
2974 ring->tx_pending = bp->tx_ring_size;
2977 static int macb_set_ringparam(struct net_device *netdev,
2978 struct ethtool_ringparam *ring)
2980 struct macb *bp = netdev_priv(netdev);
2981 u32 new_rx_size, new_tx_size;
2982 unsigned int reset = 0;
2984 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2987 new_rx_size = clamp_t(u32, ring->rx_pending,
2988 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2989 new_rx_size = roundup_pow_of_two(new_rx_size);
2991 new_tx_size = clamp_t(u32, ring->tx_pending,
2992 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2993 new_tx_size = roundup_pow_of_two(new_tx_size);
2995 if ((new_tx_size == bp->tx_ring_size) &&
2996 (new_rx_size == bp->rx_ring_size)) {
3001 if (netif_running(bp->dev)) {
3003 macb_close(bp->dev);
3006 bp->rx_ring_size = new_rx_size;
3007 bp->tx_ring_size = new_tx_size;
3015 #ifdef CONFIG_MACB_USE_HWSTAMP
3016 static unsigned int gem_get_tsu_rate(struct macb *bp)
3018 struct clk *tsu_clk;
3019 unsigned int tsu_rate;
3021 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3022 if (!IS_ERR(tsu_clk))
3023 tsu_rate = clk_get_rate(tsu_clk);
3024 /* try pclk instead */
3025 else if (!IS_ERR(bp->pclk)) {
3027 tsu_rate = clk_get_rate(tsu_clk);
3033 static s32 gem_get_ptp_max_adj(void)
3038 static int gem_get_ts_info(struct net_device *dev,
3039 struct ethtool_ts_info *info)
3041 struct macb *bp = netdev_priv(dev);
3043 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3044 ethtool_op_get_ts_info(dev, info);
3048 info->so_timestamping =
3049 SOF_TIMESTAMPING_TX_SOFTWARE |
3050 SOF_TIMESTAMPING_RX_SOFTWARE |
3051 SOF_TIMESTAMPING_SOFTWARE |
3052 SOF_TIMESTAMPING_TX_HARDWARE |
3053 SOF_TIMESTAMPING_RX_HARDWARE |
3054 SOF_TIMESTAMPING_RAW_HARDWARE;
3056 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3057 (1 << HWTSTAMP_TX_OFF) |
3058 (1 << HWTSTAMP_TX_ON);
3060 (1 << HWTSTAMP_FILTER_NONE) |
3061 (1 << HWTSTAMP_FILTER_ALL);
3063 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3068 static struct macb_ptp_info gem_ptp_info = {
3069 .ptp_init = gem_ptp_init,
3070 .ptp_remove = gem_ptp_remove,
3071 .get_ptp_max_adj = gem_get_ptp_max_adj,
3072 .get_tsu_rate = gem_get_tsu_rate,
3073 .get_ts_info = gem_get_ts_info,
3074 .get_hwtst = gem_get_hwtst,
3075 .set_hwtst = gem_set_hwtst,
3079 static int macb_get_ts_info(struct net_device *netdev,
3080 struct ethtool_ts_info *info)
3082 struct macb *bp = netdev_priv(netdev);
3085 return bp->ptp_info->get_ts_info(netdev, info);
3087 return ethtool_op_get_ts_info(netdev, info);
3090 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3092 struct net_device *netdev = bp->dev;
3093 struct ethtool_rx_fs_item *item;
3097 if (!(netdev->features & NETIF_F_NTUPLE))
3100 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3102 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3103 struct ethtool_rx_flow_spec *fs = &item->fs;
3104 struct ethtool_tcpip4_spec *tp4sp_m;
3106 if (fs->location >= num_t2_scr)
3109 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3111 /* enable/disable screener regs for the flow entry */
3112 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3114 /* only enable fields with no masking */
3115 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3117 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3118 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3120 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3122 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3123 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3125 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3127 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3128 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3130 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3132 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3136 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3138 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3139 uint16_t index = fs->location;
3145 if (!macb_is_gem(bp))
3148 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3149 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3151 /* ignore field if any masking set */
3152 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3153 /* 1st compare reg - IP source address */
3156 w0 = tp4sp_v->ip4src;
3157 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3158 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3159 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3160 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3161 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3165 /* ignore field if any masking set */
3166 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3167 /* 2nd compare reg - IP destination address */
3170 w0 = tp4sp_v->ip4dst;
3171 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3172 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3173 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3174 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3175 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3179 /* ignore both port fields if masking set in both */
3180 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3181 /* 3rd compare reg - source port, destination port */
3184 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3185 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3186 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3187 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3188 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3189 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3191 /* only one port definition */
3192 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3193 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3194 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3195 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3196 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3197 } else { /* dst port */
3198 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3199 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3202 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3203 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3208 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3209 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3211 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3213 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3215 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3216 gem_writel_n(bp, SCRT2, index, t2_scr);
3219 static int gem_add_flow_filter(struct net_device *netdev,
3220 struct ethtool_rxnfc *cmd)
3222 struct macb *bp = netdev_priv(netdev);
3223 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3224 struct ethtool_rx_fs_item *item, *newfs;
3225 unsigned long flags;
3229 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3232 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3235 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3236 fs->flow_type, (int)fs->ring_cookie, fs->location,
3237 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3238 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3239 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3241 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3243 /* find correct place to add in list */
3244 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3245 if (item->fs.location > newfs->fs.location) {
3246 list_add_tail(&newfs->list, &item->list);
3249 } else if (item->fs.location == fs->location) {
3250 netdev_err(netdev, "Rule not added: location %d not free!\n",
3257 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3259 gem_prog_cmp_regs(bp, fs);
3260 bp->rx_fs_list.count++;
3261 /* enable filtering if NTUPLE on */
3262 gem_enable_flow_filters(bp, 1);
3264 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3268 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3273 static int gem_del_flow_filter(struct net_device *netdev,
3274 struct ethtool_rxnfc *cmd)
3276 struct macb *bp = netdev_priv(netdev);
3277 struct ethtool_rx_fs_item *item;
3278 struct ethtool_rx_flow_spec *fs;
3279 unsigned long flags;
3281 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3283 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3284 if (item->fs.location == cmd->fs.location) {
3285 /* disable screener regs for the flow entry */
3288 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3289 fs->flow_type, (int)fs->ring_cookie, fs->location,
3290 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3291 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3292 htons(fs->h_u.tcp_ip4_spec.psrc),
3293 htons(fs->h_u.tcp_ip4_spec.pdst));
3295 gem_writel_n(bp, SCRT2, fs->location, 0);
3297 list_del(&item->list);
3298 bp->rx_fs_list.count--;
3299 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3305 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3309 static int gem_get_flow_entry(struct net_device *netdev,
3310 struct ethtool_rxnfc *cmd)
3312 struct macb *bp = netdev_priv(netdev);
3313 struct ethtool_rx_fs_item *item;
3315 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3316 if (item->fs.location == cmd->fs.location) {
3317 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3324 static int gem_get_all_flow_entries(struct net_device *netdev,
3325 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3327 struct macb *bp = netdev_priv(netdev);
3328 struct ethtool_rx_fs_item *item;
3331 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3332 if (cnt == cmd->rule_cnt)
3334 rule_locs[cnt] = item->fs.location;
3337 cmd->data = bp->max_tuples;
3338 cmd->rule_cnt = cnt;
3343 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3346 struct macb *bp = netdev_priv(netdev);
3350 case ETHTOOL_GRXRINGS:
3351 cmd->data = bp->num_queues;
3353 case ETHTOOL_GRXCLSRLCNT:
3354 cmd->rule_cnt = bp->rx_fs_list.count;
3356 case ETHTOOL_GRXCLSRULE:
3357 ret = gem_get_flow_entry(netdev, cmd);
3359 case ETHTOOL_GRXCLSRLALL:
3360 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3364 "Command parameter %d is not supported\n", cmd->cmd);
3371 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3373 struct macb *bp = netdev_priv(netdev);
3377 case ETHTOOL_SRXCLSRLINS:
3378 if ((cmd->fs.location >= bp->max_tuples)
3379 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3383 ret = gem_add_flow_filter(netdev, cmd);
3385 case ETHTOOL_SRXCLSRLDEL:
3386 ret = gem_del_flow_filter(netdev, cmd);
3390 "Command parameter %d is not supported\n", cmd->cmd);
3397 static const struct ethtool_ops macb_ethtool_ops = {
3398 .get_regs_len = macb_get_regs_len,
3399 .get_regs = macb_get_regs,
3400 .get_link = ethtool_op_get_link,
3401 .get_ts_info = ethtool_op_get_ts_info,
3402 .get_wol = macb_get_wol,
3403 .set_wol = macb_set_wol,
3404 .get_link_ksettings = macb_get_link_ksettings,
3405 .set_link_ksettings = macb_set_link_ksettings,
3406 .get_ringparam = macb_get_ringparam,
3407 .set_ringparam = macb_set_ringparam,
3410 static const struct ethtool_ops gem_ethtool_ops = {
3411 .get_regs_len = macb_get_regs_len,
3412 .get_regs = macb_get_regs,
3413 .get_wol = macb_get_wol,
3414 .set_wol = macb_set_wol,
3415 .get_link = ethtool_op_get_link,
3416 .get_ts_info = macb_get_ts_info,
3417 .get_ethtool_stats = gem_get_ethtool_stats,
3418 .get_strings = gem_get_ethtool_strings,
3419 .get_sset_count = gem_get_sset_count,
3420 .get_link_ksettings = macb_get_link_ksettings,
3421 .set_link_ksettings = macb_set_link_ksettings,
3422 .get_ringparam = macb_get_ringparam,
3423 .set_ringparam = macb_set_ringparam,
3424 .get_rxnfc = gem_get_rxnfc,
3425 .set_rxnfc = gem_set_rxnfc,
3428 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3430 struct macb *bp = netdev_priv(dev);
3432 if (!netif_running(dev))
3438 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3440 return bp->ptp_info->get_hwtst(dev, rq);
3444 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3447 static inline void macb_set_txcsum_feature(struct macb *bp,
3448 netdev_features_t features)
3452 if (!macb_is_gem(bp))
3455 val = gem_readl(bp, DMACFG);
3456 if (features & NETIF_F_HW_CSUM)
3457 val |= GEM_BIT(TXCOEN);
3459 val &= ~GEM_BIT(TXCOEN);
3461 gem_writel(bp, DMACFG, val);
3464 static inline void macb_set_rxcsum_feature(struct macb *bp,
3465 netdev_features_t features)
3467 struct net_device *netdev = bp->dev;
3470 if (!macb_is_gem(bp))
3473 val = gem_readl(bp, NCFGR);
3474 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3475 val |= GEM_BIT(RXCOEN);
3477 val &= ~GEM_BIT(RXCOEN);
3479 gem_writel(bp, NCFGR, val);
3482 static inline void macb_set_rxflow_feature(struct macb *bp,
3483 netdev_features_t features)
3485 if (!macb_is_gem(bp))
3488 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3491 static int macb_set_features(struct net_device *netdev,
3492 netdev_features_t features)
3494 struct macb *bp = netdev_priv(netdev);
3495 netdev_features_t changed = features ^ netdev->features;
3497 /* TX checksum offload */
3498 if (changed & NETIF_F_HW_CSUM)
3499 macb_set_txcsum_feature(bp, features);
3501 /* RX checksum offload */
3502 if (changed & NETIF_F_RXCSUM)
3503 macb_set_rxcsum_feature(bp, features);
3505 /* RX Flow Filters */
3506 if (changed & NETIF_F_NTUPLE)
3507 macb_set_rxflow_feature(bp, features);
3512 static void macb_restore_features(struct macb *bp)
3514 struct net_device *netdev = bp->dev;
3515 netdev_features_t features = netdev->features;
3516 struct ethtool_rx_fs_item *item;
3518 /* TX checksum offload */
3519 macb_set_txcsum_feature(bp, features);
3521 /* RX checksum offload */
3522 macb_set_rxcsum_feature(bp, features);
3524 /* RX Flow Filters */
3525 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3526 gem_prog_cmp_regs(bp, &item->fs);
3528 macb_set_rxflow_feature(bp, features);
3531 static const struct net_device_ops macb_netdev_ops = {
3532 .ndo_open = macb_open,
3533 .ndo_stop = macb_close,
3534 .ndo_start_xmit = macb_start_xmit,
3535 .ndo_set_rx_mode = macb_set_rx_mode,
3536 .ndo_get_stats = macb_get_stats,
3537 .ndo_do_ioctl = macb_ioctl,
3538 .ndo_validate_addr = eth_validate_addr,
3539 .ndo_change_mtu = macb_change_mtu,
3540 .ndo_set_mac_address = eth_mac_addr,
3541 #ifdef CONFIG_NET_POLL_CONTROLLER
3542 .ndo_poll_controller = macb_poll_controller,
3544 .ndo_set_features = macb_set_features,
3545 .ndo_features_check = macb_features_check,
3548 /* Configure peripheral capabilities according to device tree
3549 * and integration options used
3551 static void macb_configure_caps(struct macb *bp,
3552 const struct macb_config *dt_conf)
3557 bp->caps = dt_conf->caps;
3559 if (hw_is_gem(bp->regs, bp->native_io)) {
3560 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3562 dcfg = gem_readl(bp, DCFG1);
3563 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3564 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3565 dcfg = gem_readl(bp, DCFG2);
3566 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3567 bp->caps |= MACB_CAPS_FIFO_MODE;
3568 #ifdef CONFIG_MACB_USE_HWSTAMP
3569 if (gem_has_ptp(bp)) {
3570 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3571 dev_err(&bp->pdev->dev,
3572 "GEM doesn't support hardware ptp.\n");
3574 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3575 bp->ptp_info = &gem_ptp_info;
3581 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3584 static void macb_probe_queues(void __iomem *mem,
3586 unsigned int *queue_mask,
3587 unsigned int *num_queues)
3592 /* is it macb or gem ?
3594 * We need to read directly from the hardware here because
3595 * we are early in the probe process and don't have the
3596 * MACB_CAPS_MACB_IS_GEM flag positioned
3598 if (!hw_is_gem(mem, native_io))
3601 /* bit 0 is never set but queue 0 always exists */
3602 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3603 *num_queues = hweight32(*queue_mask);
3606 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3607 struct clk **hclk, struct clk **tx_clk,
3608 struct clk **rx_clk, struct clk **tsu_clk)
3610 struct macb_platform_data *pdata;
3613 pdata = dev_get_platdata(&pdev->dev);
3615 *pclk = pdata->pclk;
3616 *hclk = pdata->hclk;
3618 *pclk = devm_clk_get(&pdev->dev, "pclk");
3619 *hclk = devm_clk_get(&pdev->dev, "hclk");
3622 if (IS_ERR_OR_NULL(*pclk)) {
3623 err = PTR_ERR(*pclk);
3627 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3631 if (IS_ERR_OR_NULL(*hclk)) {
3632 err = PTR_ERR(*hclk);
3636 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3640 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3641 if (IS_ERR(*tx_clk))
3642 return PTR_ERR(*tx_clk);
3644 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3645 if (IS_ERR(*rx_clk))
3646 return PTR_ERR(*rx_clk);
3648 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3649 if (IS_ERR(*tsu_clk))
3650 return PTR_ERR(*tsu_clk);
3652 err = clk_prepare_enable(*pclk);
3654 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3658 err = clk_prepare_enable(*hclk);
3660 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3661 goto err_disable_pclk;
3664 err = clk_prepare_enable(*tx_clk);
3666 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3667 goto err_disable_hclk;
3670 err = clk_prepare_enable(*rx_clk);
3672 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3673 goto err_disable_txclk;
3676 err = clk_prepare_enable(*tsu_clk);
3678 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3679 goto err_disable_rxclk;
3685 clk_disable_unprepare(*rx_clk);
3688 clk_disable_unprepare(*tx_clk);
3691 clk_disable_unprepare(*hclk);
3694 clk_disable_unprepare(*pclk);
3699 static int macb_init(struct platform_device *pdev)
3701 struct net_device *dev = platform_get_drvdata(pdev);
3702 unsigned int hw_q, q;
3703 struct macb *bp = netdev_priv(dev);
3704 struct macb_queue *queue;
3708 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3709 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3711 /* set the queue register mapping once for all: queue0 has a special
3712 * register mapping but we don't want to test the queue index then
3713 * compute the corresponding register offset at run time.
3715 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3716 if (!(bp->queue_mask & (1 << hw_q)))
3719 queue = &bp->queues[q];
3721 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3723 queue->ISR = GEM_ISR(hw_q - 1);
3724 queue->IER = GEM_IER(hw_q - 1);
3725 queue->IDR = GEM_IDR(hw_q - 1);
3726 queue->IMR = GEM_IMR(hw_q - 1);
3727 queue->TBQP = GEM_TBQP(hw_q - 1);
3728 queue->RBQP = GEM_RBQP(hw_q - 1);
3729 queue->RBQS = GEM_RBQS(hw_q - 1);
3730 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3731 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3732 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3733 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3737 /* queue0 uses legacy registers */
3738 queue->ISR = MACB_ISR;
3739 queue->IER = MACB_IER;
3740 queue->IDR = MACB_IDR;
3741 queue->IMR = MACB_IMR;
3742 queue->TBQP = MACB_TBQP;
3743 queue->RBQP = MACB_RBQP;
3744 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3745 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3746 queue->TBQPH = MACB_TBQPH;
3747 queue->RBQPH = MACB_RBQPH;
3752 /* get irq: here we use the linux queue index, not the hardware
3753 * queue index. the queue irq definitions in the device tree
3754 * must remove the optional gaps that could exist in the
3755 * hardware queue mask.
3757 queue->irq = platform_get_irq(pdev, q);
3758 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3759 IRQF_SHARED, dev->name, queue);
3762 "Unable to request IRQ %d (error %d)\n",
3767 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3771 dev->netdev_ops = &macb_netdev_ops;
3773 /* setup appropriated routines according to adapter type */
3774 if (macb_is_gem(bp)) {
3775 bp->max_tx_length = GEM_MAX_TX_LEN;
3776 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3777 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3778 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3779 bp->macbgem_ops.mog_rx = gem_rx;
3780 dev->ethtool_ops = &gem_ethtool_ops;
3782 bp->max_tx_length = MACB_MAX_TX_LEN;
3783 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3784 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3785 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3786 bp->macbgem_ops.mog_rx = macb_rx;
3787 dev->ethtool_ops = &macb_ethtool_ops;
3791 dev->hw_features = NETIF_F_SG;
3793 /* Check LSO capability */
3794 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3795 dev->hw_features |= MACB_NETIF_LSO;
3797 /* Checksum offload is only available on gem with packet buffer */
3798 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3799 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3800 if (bp->caps & MACB_CAPS_SG_DISABLED)
3801 dev->hw_features &= ~NETIF_F_SG;
3802 dev->features = dev->hw_features;
3804 /* Check RX Flow Filters support.
3805 * Max Rx flows set by availability of screeners & compare regs:
3806 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3808 reg = gem_readl(bp, DCFG8);
3809 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3810 GEM_BFEXT(T2SCR, reg));
3811 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3812 if (bp->max_tuples > 0) {
3813 /* also needs one ethtype match to check IPv4 */
3814 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3815 /* program this reg now */
3817 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3818 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3819 /* Filtering is supported in hw but don't enable it in kernel now */
3820 dev->hw_features |= NETIF_F_NTUPLE;
3821 /* init Rx flow definitions */
3822 bp->rx_fs_list.count = 0;
3823 spin_lock_init(&bp->rx_fs_lock);
3828 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3830 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3831 val = GEM_BIT(RGMII);
3832 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3833 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3834 val = MACB_BIT(RMII);
3835 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3836 val = MACB_BIT(MII);
3838 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3839 val |= MACB_BIT(CLKEN);
3841 macb_or_gem_writel(bp, USRIO, val);
3844 /* Set MII management clock divider */
3845 val = macb_mdc_clk_div(bp);
3846 val |= macb_dbw(bp);
3847 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3848 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3849 macb_writel(bp, NCFGR, val);
3854 #if defined(CONFIG_OF)
3855 /* 1518 rounded up */
3856 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3857 /* max number of receive buffers */
3858 #define AT91ETHER_MAX_RX_DESCR 9
3860 static struct sifive_fu540_macb_mgmt *mgmt;
3862 static int at91ether_alloc_coherent(struct macb *lp)
3864 struct macb_queue *q = &lp->queues[0];
3866 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3867 (AT91ETHER_MAX_RX_DESCR *
3868 macb_dma_desc_get_size(lp)),
3869 &q->rx_ring_dma, GFP_KERNEL);
3873 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3874 AT91ETHER_MAX_RX_DESCR *
3875 AT91ETHER_MAX_RBUFF_SZ,
3876 &q->rx_buffers_dma, GFP_KERNEL);
3877 if (!q->rx_buffers) {
3878 dma_free_coherent(&lp->pdev->dev,
3879 AT91ETHER_MAX_RX_DESCR *
3880 macb_dma_desc_get_size(lp),
3881 q->rx_ring, q->rx_ring_dma);
3889 static void at91ether_free_coherent(struct macb *lp)
3891 struct macb_queue *q = &lp->queues[0];
3894 dma_free_coherent(&lp->pdev->dev,
3895 AT91ETHER_MAX_RX_DESCR *
3896 macb_dma_desc_get_size(lp),
3897 q->rx_ring, q->rx_ring_dma);
3901 if (q->rx_buffers) {
3902 dma_free_coherent(&lp->pdev->dev,
3903 AT91ETHER_MAX_RX_DESCR *
3904 AT91ETHER_MAX_RBUFF_SZ,
3905 q->rx_buffers, q->rx_buffers_dma);
3906 q->rx_buffers = NULL;
3910 /* Initialize and start the Receiver and Transmit subsystems */
3911 static int at91ether_start(struct macb *lp)
3913 struct macb_queue *q = &lp->queues[0];
3914 struct macb_dma_desc *desc;
3919 ret = at91ether_alloc_coherent(lp);
3923 addr = q->rx_buffers_dma;
3924 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3925 desc = macb_rx_desc(q, i);
3926 macb_set_addr(lp, desc, addr);
3928 addr += AT91ETHER_MAX_RBUFF_SZ;
3931 /* Set the Wrap bit on the last descriptor */
3932 desc->addr |= MACB_BIT(RX_WRAP);
3934 /* Reset buffer index */
3937 /* Program address of descriptor list in Rx Buffer Queue register */
3938 macb_writel(lp, RBQP, q->rx_ring_dma);
3940 /* Enable Receive and Transmit */
3941 ctl = macb_readl(lp, NCR);
3942 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3944 /* Enable MAC interrupts */
3945 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3947 MACB_BIT(ISR_TUND) |
3950 MACB_BIT(RM9200_TBRE) |
3951 MACB_BIT(ISR_ROVR) |
3957 static void at91ether_stop(struct macb *lp)
3961 /* Disable MAC interrupts */
3962 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3964 MACB_BIT(ISR_TUND) |
3967 MACB_BIT(RM9200_TBRE) |
3968 MACB_BIT(ISR_ROVR) |
3971 /* Disable Receiver and Transmitter */
3972 ctl = macb_readl(lp, NCR);
3973 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3975 /* Free resources. */
3976 at91ether_free_coherent(lp);
3979 /* Open the ethernet interface */
3980 static int at91ether_open(struct net_device *dev)
3982 struct macb *lp = netdev_priv(dev);
3986 ret = pm_runtime_get_sync(&lp->pdev->dev);
3988 pm_runtime_put_noidle(&lp->pdev->dev);
3992 /* Clear internal statistics */
3993 ctl = macb_readl(lp, NCR);
3994 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3996 macb_set_hwaddr(lp);
3998 ret = at91ether_start(lp);
4002 ret = macb_phylink_connect(lp);
4006 netif_start_queue(dev);
4013 pm_runtime_put_sync(&lp->pdev->dev);
4017 /* Close the interface */
4018 static int at91ether_close(struct net_device *dev)
4020 struct macb *lp = netdev_priv(dev);
4022 netif_stop_queue(dev);
4024 phylink_stop(lp->phylink);
4025 phylink_disconnect_phy(lp->phylink);
4029 return pm_runtime_put(&lp->pdev->dev);
4032 /* Transmit packet */
4033 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4034 struct net_device *dev)
4036 struct macb *lp = netdev_priv(dev);
4037 unsigned long flags;
4039 if (lp->rm9200_tx_len < 2) {
4040 int desc = lp->rm9200_tx_tail;
4042 /* Store packet information (to free when Tx completed) */
4043 lp->rm9200_txq[desc].skb = skb;
4044 lp->rm9200_txq[desc].size = skb->len;
4045 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4046 skb->len, DMA_TO_DEVICE);
4047 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4048 dev_kfree_skb_any(skb);
4049 dev->stats.tx_dropped++;
4050 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4051 return NETDEV_TX_OK;
4054 spin_lock_irqsave(&lp->lock, flags);
4056 lp->rm9200_tx_tail = (desc + 1) & 1;
4057 lp->rm9200_tx_len++;
4058 if (lp->rm9200_tx_len > 1)
4059 netif_stop_queue(dev);
4061 spin_unlock_irqrestore(&lp->lock, flags);
4063 /* Set address of the data in the Transmit Address register */
4064 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4065 /* Set length of the packet in the Transmit Control register */
4066 macb_writel(lp, TCR, skb->len);
4069 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4070 return NETDEV_TX_BUSY;
4073 return NETDEV_TX_OK;
4076 /* Extract received frame from buffer descriptors and sent to upper layers.
4077 * (Called from interrupt context)
4079 static void at91ether_rx(struct net_device *dev)
4081 struct macb *lp = netdev_priv(dev);
4082 struct macb_queue *q = &lp->queues[0];
4083 struct macb_dma_desc *desc;
4084 unsigned char *p_recv;
4085 struct sk_buff *skb;
4086 unsigned int pktlen;
4088 desc = macb_rx_desc(q, q->rx_tail);
4089 while (desc->addr & MACB_BIT(RX_USED)) {
4090 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4091 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4092 skb = netdev_alloc_skb(dev, pktlen + 2);
4094 skb_reserve(skb, 2);
4095 skb_put_data(skb, p_recv, pktlen);
4097 skb->protocol = eth_type_trans(skb, dev);
4098 dev->stats.rx_packets++;
4099 dev->stats.rx_bytes += pktlen;
4102 dev->stats.rx_dropped++;
4105 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4106 dev->stats.multicast++;
4108 /* reset ownership bit */
4109 desc->addr &= ~MACB_BIT(RX_USED);
4111 /* wrap after last buffer */
4112 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4117 desc = macb_rx_desc(q, q->rx_tail);
4121 /* MAC interrupt handler */
4122 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4124 struct net_device *dev = dev_id;
4125 struct macb *lp = netdev_priv(dev);
4131 /* MAC Interrupt Status register indicates what interrupts are pending.
4132 * It is automatically cleared once read.
4134 intstatus = macb_readl(lp, ISR);
4136 /* Receive complete */
4137 if (intstatus & MACB_BIT(RCOMP))
4140 /* Transmit complete */
4141 if (intstatus & (MACB_BIT(TCOMP) | MACB_BIT(RM9200_TBRE))) {
4142 /* The TCOM bit is set even if the transmission failed */
4143 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4144 dev->stats.tx_errors++;
4146 spin_lock(&lp->lock);
4148 tsr = macb_readl(lp, TSR);
4150 /* we have three possibilities here:
4151 * - all pending packets transmitted (TGO, implies BNQ)
4152 * - only first packet transmitted (!TGO && BNQ)
4153 * - two frames pending (!TGO && !BNQ)
4154 * Note that TGO ("transmit go") is called "IDLE" on RM9200.
4156 qlen = (tsr & MACB_BIT(TGO)) ? 0 :
4157 (tsr & MACB_BIT(RM9200_BNQ)) ? 1 : 2;
4159 while (lp->rm9200_tx_len > qlen) {
4160 desc = (lp->rm9200_tx_tail - lp->rm9200_tx_len) & 1;
4161 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4162 lp->rm9200_txq[desc].skb = NULL;
4163 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4164 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4165 dev->stats.tx_packets++;
4166 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4167 lp->rm9200_tx_len--;
4170 if (lp->rm9200_tx_len < 2 && netif_queue_stopped(dev))
4171 netif_wake_queue(dev);
4173 spin_unlock(&lp->lock);
4176 /* Work-around for EMAC Errata section 41.3.1 */
4177 if (intstatus & MACB_BIT(RXUBR)) {
4178 ctl = macb_readl(lp, NCR);
4179 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4181 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4184 if (intstatus & MACB_BIT(ISR_ROVR))
4185 netdev_err(dev, "ROVR error\n");
4190 #ifdef CONFIG_NET_POLL_CONTROLLER
4191 static void at91ether_poll_controller(struct net_device *dev)
4193 unsigned long flags;
4195 local_irq_save(flags);
4196 at91ether_interrupt(dev->irq, dev);
4197 local_irq_restore(flags);
4201 static const struct net_device_ops at91ether_netdev_ops = {
4202 .ndo_open = at91ether_open,
4203 .ndo_stop = at91ether_close,
4204 .ndo_start_xmit = at91ether_start_xmit,
4205 .ndo_get_stats = macb_get_stats,
4206 .ndo_set_rx_mode = macb_set_rx_mode,
4207 .ndo_set_mac_address = eth_mac_addr,
4208 .ndo_do_ioctl = macb_ioctl,
4209 .ndo_validate_addr = eth_validate_addr,
4210 #ifdef CONFIG_NET_POLL_CONTROLLER
4211 .ndo_poll_controller = at91ether_poll_controller,
4215 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4216 struct clk **hclk, struct clk **tx_clk,
4217 struct clk **rx_clk, struct clk **tsu_clk)
4226 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4228 return PTR_ERR(*pclk);
4230 err = clk_prepare_enable(*pclk);
4232 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4239 static int at91ether_init(struct platform_device *pdev)
4241 struct net_device *dev = platform_get_drvdata(pdev);
4242 struct macb *bp = netdev_priv(dev);
4245 bp->queues[0].bp = bp;
4247 dev->netdev_ops = &at91ether_netdev_ops;
4248 dev->ethtool_ops = &macb_ethtool_ops;
4250 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4255 macb_writel(bp, NCR, 0);
4257 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4262 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4263 unsigned long parent_rate)
4268 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4269 unsigned long *parent_rate)
4271 if (WARN_ON(rate < 2500000))
4273 else if (rate == 2500000)
4275 else if (WARN_ON(rate < 13750000))
4277 else if (WARN_ON(rate < 25000000))
4279 else if (rate == 25000000)
4281 else if (WARN_ON(rate < 75000000))
4283 else if (WARN_ON(rate < 125000000))
4285 else if (rate == 125000000)
4288 WARN_ON(rate > 125000000);
4293 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4294 unsigned long parent_rate)
4296 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4297 if (rate != 125000000)
4298 iowrite32(1, mgmt->reg);
4300 iowrite32(0, mgmt->reg);
4306 static const struct clk_ops fu540_c000_ops = {
4307 .recalc_rate = fu540_macb_tx_recalc_rate,
4308 .round_rate = fu540_macb_tx_round_rate,
4309 .set_rate = fu540_macb_tx_set_rate,
4312 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4313 struct clk **hclk, struct clk **tx_clk,
4314 struct clk **rx_clk, struct clk **tsu_clk)
4316 struct clk_init_data init;
4319 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4323 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4327 init.name = "sifive-gemgxl-mgmt";
4328 init.ops = &fu540_c000_ops;
4330 init.num_parents = 0;
4333 mgmt->hw.init = &init;
4335 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4336 if (IS_ERR(*tx_clk))
4337 return PTR_ERR(*tx_clk);
4339 err = clk_prepare_enable(*tx_clk);
4341 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4343 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4348 static int fu540_c000_init(struct platform_device *pdev)
4350 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4351 if (IS_ERR(mgmt->reg))
4352 return PTR_ERR(mgmt->reg);
4354 return macb_init(pdev);
4357 static const struct macb_config fu540_c000_config = {
4358 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4359 MACB_CAPS_GEM_HAS_PTP,
4360 .dma_burst_length = 16,
4361 .clk_init = fu540_c000_clk_init,
4362 .init = fu540_c000_init,
4363 .jumbo_max_len = 10240,
4366 static const struct macb_config at91sam9260_config = {
4367 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4368 .clk_init = macb_clk_init,
4372 static const struct macb_config sama5d3macb_config = {
4373 .caps = MACB_CAPS_SG_DISABLED
4374 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4375 .clk_init = macb_clk_init,
4379 static const struct macb_config pc302gem_config = {
4380 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4381 .dma_burst_length = 16,
4382 .clk_init = macb_clk_init,
4386 static const struct macb_config sama5d2_config = {
4387 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4388 .dma_burst_length = 16,
4389 .clk_init = macb_clk_init,
4393 static const struct macb_config sama5d3_config = {
4394 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4395 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4396 .dma_burst_length = 16,
4397 .clk_init = macb_clk_init,
4399 .jumbo_max_len = 10240,
4402 static const struct macb_config sama5d4_config = {
4403 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4404 .dma_burst_length = 4,
4405 .clk_init = macb_clk_init,
4409 static const struct macb_config emac_config = {
4410 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4411 .clk_init = at91ether_clk_init,
4412 .init = at91ether_init,
4415 static const struct macb_config np4_config = {
4416 .caps = MACB_CAPS_USRIO_DISABLED,
4417 .clk_init = macb_clk_init,
4421 static const struct macb_config zynqmp_config = {
4422 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4424 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4425 .dma_burst_length = 16,
4426 .clk_init = macb_clk_init,
4428 .jumbo_max_len = 10240,
4431 static const struct macb_config zynq_config = {
4432 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4433 MACB_CAPS_NEEDS_RSTONUBR,
4434 .dma_burst_length = 16,
4435 .clk_init = macb_clk_init,
4439 static const struct of_device_id macb_dt_ids[] = {
4440 { .compatible = "cdns,at32ap7000-macb" },
4441 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4442 { .compatible = "cdns,macb" },
4443 { .compatible = "cdns,np4-macb", .data = &np4_config },
4444 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4445 { .compatible = "cdns,gem", .data = &pc302gem_config },
4446 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4447 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4448 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4449 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4450 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4451 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4452 { .compatible = "cdns,emac", .data = &emac_config },
4453 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4454 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4455 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4458 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4459 #endif /* CONFIG_OF */
4461 static const struct macb_config default_gem_config = {
4462 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4464 MACB_CAPS_GEM_HAS_PTP,
4465 .dma_burst_length = 16,
4466 .clk_init = macb_clk_init,
4468 .jumbo_max_len = 10240,
4471 static int macb_probe(struct platform_device *pdev)
4473 const struct macb_config *macb_config = &default_gem_config;
4474 int (*clk_init)(struct platform_device *, struct clk **,
4475 struct clk **, struct clk **, struct clk **,
4476 struct clk **) = macb_config->clk_init;
4477 int (*init)(struct platform_device *) = macb_config->init;
4478 struct device_node *np = pdev->dev.of_node;
4479 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4480 struct clk *tsu_clk = NULL;
4481 unsigned int queue_mask, num_queues;
4483 phy_interface_t interface;
4484 struct net_device *dev;
4485 struct resource *regs;
4491 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4492 mem = devm_ioremap_resource(&pdev->dev, regs);
4494 return PTR_ERR(mem);
4497 const struct of_device_id *match;
4499 match = of_match_node(macb_dt_ids, np);
4500 if (match && match->data) {
4501 macb_config = match->data;
4502 clk_init = macb_config->clk_init;
4503 init = macb_config->init;
4507 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4511 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4512 pm_runtime_use_autosuspend(&pdev->dev);
4513 pm_runtime_get_noresume(&pdev->dev);
4514 pm_runtime_set_active(&pdev->dev);
4515 pm_runtime_enable(&pdev->dev);
4516 native_io = hw_is_native_io(mem);
4518 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4519 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4522 goto err_disable_clocks;
4525 dev->base_addr = regs->start;
4527 SET_NETDEV_DEV(dev, &pdev->dev);
4529 bp = netdev_priv(dev);
4533 bp->native_io = native_io;
4535 bp->macb_reg_readl = hw_readl_native;
4536 bp->macb_reg_writel = hw_writel_native;
4538 bp->macb_reg_readl = hw_readl;
4539 bp->macb_reg_writel = hw_writel;
4541 bp->num_queues = num_queues;
4542 bp->queue_mask = queue_mask;
4544 bp->dma_burst_length = macb_config->dma_burst_length;
4547 bp->tx_clk = tx_clk;
4548 bp->rx_clk = rx_clk;
4549 bp->tsu_clk = tsu_clk;
4551 bp->jumbo_max_len = macb_config->jumbo_max_len;
4554 if (of_get_property(np, "magic-packet", NULL))
4555 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4556 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4558 spin_lock_init(&bp->lock);
4560 /* setup capabilities */
4561 macb_configure_caps(bp, macb_config);
4563 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4564 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4565 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4566 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4569 platform_set_drvdata(pdev, dev);
4571 dev->irq = platform_get_irq(pdev, 0);
4574 goto err_out_free_netdev;
4577 /* MTU range: 68 - 1500 or 10240 */
4578 dev->min_mtu = GEM_MTU_MIN_SIZE;
4579 if (bp->caps & MACB_CAPS_JUMBO)
4580 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4582 dev->max_mtu = ETH_DATA_LEN;
4584 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4585 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4587 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4588 macb_dma_desc_get_size(bp);
4590 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4592 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4593 macb_dma_desc_get_size(bp);
4596 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4597 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4598 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4600 mac = of_get_mac_address(np);
4601 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4602 err = -EPROBE_DEFER;
4603 goto err_out_free_netdev;
4604 } else if (!IS_ERR_OR_NULL(mac)) {
4605 ether_addr_copy(bp->dev->dev_addr, mac);
4607 macb_get_hwaddr(bp);
4610 err = of_get_phy_mode(np, &interface);
4612 /* not found in DT, MII by default */
4613 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4615 bp->phy_interface = interface;
4617 /* IP specific init */
4620 goto err_out_free_netdev;
4622 err = macb_mii_init(bp);
4624 goto err_out_free_netdev;
4626 netif_carrier_off(dev);
4628 err = register_netdev(dev);
4630 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4631 goto err_out_unregister_mdio;
4634 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4636 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4637 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4638 dev->base_addr, dev->irq, dev->dev_addr);
4640 pm_runtime_mark_last_busy(&bp->pdev->dev);
4641 pm_runtime_put_autosuspend(&bp->pdev->dev);
4645 err_out_unregister_mdio:
4646 mdiobus_unregister(bp->mii_bus);
4647 mdiobus_free(bp->mii_bus);
4649 err_out_free_netdev:
4653 clk_disable_unprepare(tx_clk);
4654 clk_disable_unprepare(hclk);
4655 clk_disable_unprepare(pclk);
4656 clk_disable_unprepare(rx_clk);
4657 clk_disable_unprepare(tsu_clk);
4658 pm_runtime_disable(&pdev->dev);
4659 pm_runtime_set_suspended(&pdev->dev);
4660 pm_runtime_dont_use_autosuspend(&pdev->dev);
4665 static int macb_remove(struct platform_device *pdev)
4667 struct net_device *dev;
4670 dev = platform_get_drvdata(pdev);
4673 bp = netdev_priv(dev);
4674 mdiobus_unregister(bp->mii_bus);
4675 mdiobus_free(bp->mii_bus);
4677 unregister_netdev(dev);
4678 tasklet_kill(&bp->hresp_err_tasklet);
4679 pm_runtime_disable(&pdev->dev);
4680 pm_runtime_dont_use_autosuspend(&pdev->dev);
4681 if (!pm_runtime_suspended(&pdev->dev)) {
4682 clk_disable_unprepare(bp->tx_clk);
4683 clk_disable_unprepare(bp->hclk);
4684 clk_disable_unprepare(bp->pclk);
4685 clk_disable_unprepare(bp->rx_clk);
4686 clk_disable_unprepare(bp->tsu_clk);
4687 pm_runtime_set_suspended(&pdev->dev);
4689 phylink_destroy(bp->phylink);
4696 static int __maybe_unused macb_suspend(struct device *dev)
4698 struct net_device *netdev = dev_get_drvdata(dev);
4699 struct macb *bp = netdev_priv(netdev);
4700 struct macb_queue *queue = bp->queues;
4701 unsigned long flags;
4705 if (!netif_running(netdev))
4708 if (bp->wol & MACB_WOL_ENABLED) {
4709 spin_lock_irqsave(&bp->lock, flags);
4710 /* Flush all status bits */
4711 macb_writel(bp, TSR, -1);
4712 macb_writel(bp, RSR, -1);
4713 for (q = 0, queue = bp->queues; q < bp->num_queues;
4715 /* Disable all interrupts */
4716 queue_writel(queue, IDR, -1);
4717 queue_readl(queue, ISR);
4718 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4719 queue_writel(queue, ISR, -1);
4721 /* Change interrupt handler and
4722 * Enable WoL IRQ on queue 0
4724 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4725 if (macb_is_gem(bp)) {
4726 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4727 IRQF_SHARED, netdev->name, bp->queues);
4730 "Unable to request IRQ %d (error %d)\n",
4731 bp->queues[0].irq, err);
4732 spin_unlock_irqrestore(&bp->lock, flags);
4735 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4736 gem_writel(bp, WOL, MACB_BIT(MAG));
4738 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4739 IRQF_SHARED, netdev->name, bp->queues);
4742 "Unable to request IRQ %d (error %d)\n",
4743 bp->queues[0].irq, err);
4744 spin_unlock_irqrestore(&bp->lock, flags);
4747 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4748 macb_writel(bp, WOL, MACB_BIT(MAG));
4750 spin_unlock_irqrestore(&bp->lock, flags);
4752 enable_irq_wake(bp->queues[0].irq);
4755 netif_device_detach(netdev);
4756 for (q = 0, queue = bp->queues; q < bp->num_queues;
4758 napi_disable(&queue->napi);
4760 if (!(bp->wol & MACB_WOL_ENABLED)) {
4762 phylink_stop(bp->phylink);
4764 spin_lock_irqsave(&bp->lock, flags);
4766 spin_unlock_irqrestore(&bp->lock, flags);
4769 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4770 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4772 if (netdev->hw_features & NETIF_F_NTUPLE)
4773 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4776 bp->ptp_info->ptp_remove(netdev);
4777 if (!device_may_wakeup(dev))
4778 pm_runtime_force_suspend(dev);
4783 static int __maybe_unused macb_resume(struct device *dev)
4785 struct net_device *netdev = dev_get_drvdata(dev);
4786 struct macb *bp = netdev_priv(netdev);
4787 struct macb_queue *queue = bp->queues;
4788 unsigned long flags;
4792 if (!netif_running(netdev))
4795 if (!device_may_wakeup(dev))
4796 pm_runtime_force_resume(dev);
4798 if (bp->wol & MACB_WOL_ENABLED) {
4799 spin_lock_irqsave(&bp->lock, flags);
4801 if (macb_is_gem(bp)) {
4802 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4803 gem_writel(bp, WOL, 0);
4805 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4806 macb_writel(bp, WOL, 0);
4808 /* Clear ISR on queue 0 */
4809 queue_readl(bp->queues, ISR);
4810 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4811 queue_writel(bp->queues, ISR, -1);
4812 /* Replace interrupt handler on queue 0 */
4813 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4814 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4815 IRQF_SHARED, netdev->name, bp->queues);
4818 "Unable to request IRQ %d (error %d)\n",
4819 bp->queues[0].irq, err);
4820 spin_unlock_irqrestore(&bp->lock, flags);
4823 spin_unlock_irqrestore(&bp->lock, flags);
4825 disable_irq_wake(bp->queues[0].irq);
4827 /* Now make sure we disable phy before moving
4828 * to common restore path
4831 phylink_stop(bp->phylink);
4835 for (q = 0, queue = bp->queues; q < bp->num_queues;
4837 napi_enable(&queue->napi);
4839 if (netdev->hw_features & NETIF_F_NTUPLE)
4840 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4842 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4843 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4845 macb_writel(bp, NCR, MACB_BIT(MPE));
4847 macb_set_rx_mode(netdev);
4848 macb_restore_features(bp);
4850 phylink_start(bp->phylink);
4853 netif_device_attach(netdev);
4855 bp->ptp_info->ptp_init(netdev);
4860 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4862 struct net_device *netdev = dev_get_drvdata(dev);
4863 struct macb *bp = netdev_priv(netdev);
4865 if (!(device_may_wakeup(dev))) {
4866 clk_disable_unprepare(bp->tx_clk);
4867 clk_disable_unprepare(bp->hclk);
4868 clk_disable_unprepare(bp->pclk);
4869 clk_disable_unprepare(bp->rx_clk);
4871 clk_disable_unprepare(bp->tsu_clk);
4876 static int __maybe_unused macb_runtime_resume(struct device *dev)
4878 struct net_device *netdev = dev_get_drvdata(dev);
4879 struct macb *bp = netdev_priv(netdev);
4881 if (!(device_may_wakeup(dev))) {
4882 clk_prepare_enable(bp->pclk);
4883 clk_prepare_enable(bp->hclk);
4884 clk_prepare_enable(bp->tx_clk);
4885 clk_prepare_enable(bp->rx_clk);
4887 clk_prepare_enable(bp->tsu_clk);
4892 static const struct dev_pm_ops macb_pm_ops = {
4893 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4894 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4897 static struct platform_driver macb_driver = {
4898 .probe = macb_probe,
4899 .remove = macb_remove,
4902 .of_match_table = of_match_ptr(macb_dt_ids),
4907 module_platform_driver(macb_driver);
4909 MODULE_LICENSE("GPL");
4910 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4911 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4912 MODULE_ALIAS("platform:macb");