2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/crc32.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/circ_buf.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/macb.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
37 #include <linux/udp.h>
38 #include <linux/tcp.h>
41 #define MACB_RX_BUFFER_SIZE 128
42 #define RX_BUFFER_MULTIPLE 64 /* bytes */
44 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
45 #define MIN_RX_RING_SIZE 64
46 #define MAX_RX_RING_SIZE 8192
47 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
50 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_TX_RING_SIZE 64
52 #define MAX_TX_RING_SIZE 4096
53 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 /* level of occupied TX descriptors under which we wake up TX process */
57 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
59 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
60 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
63 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
66 /* Max length of transmit frame must be a multiple of 8 bytes */
67 #define MACB_TX_LEN_ALIGN 8
68 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
70 * false amba_error in TX path from the DMA assuming there is not enough
71 * space in the SRAM (16KB) even when there is.
73 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
75 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
76 #define MACB_NETIF_LSO NETIF_F_TSO
78 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
79 #define MACB_WOL_ENABLED (0x1 << 1)
81 /* Graceful stop timeouts in us. We should allow up to
82 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
84 #define MACB_HALT_TIMEOUT 1230
86 /* DMA buffer descriptor might be different size
87 * depends on hardware configuration:
89 * 1. dma address width 32 bits:
90 * word 1: 32 bit address of Data Buffer
93 * 2. dma address width 64 bits:
94 * word 1: 32 bit address of Data Buffer
96 * word 3: upper 32 bit address of Data Buffer
99 * 3. dma address width 32 bits with hardware timestamping:
100 * word 1: 32 bit address of Data Buffer
102 * word 3: timestamp word 1
103 * word 4: timestamp word 2
105 * 4. dma address width 64 bits with hardware timestamping:
106 * word 1: 32 bit address of Data Buffer
108 * word 3: upper 32 bit address of Data Buffer
110 * word 5: timestamp word 1
111 * word 6: timestamp word 2
113 static unsigned int macb_dma_desc_get_size(struct macb *bp)
116 unsigned int desc_size;
118 switch (bp->hw_dma_cap) {
120 desc_size = sizeof(struct macb_dma_desc)
121 + sizeof(struct macb_dma_desc_64);
124 desc_size = sizeof(struct macb_dma_desc)
125 + sizeof(struct macb_dma_desc_ptp);
127 case HW_DMA_CAP_64B_PTP:
128 desc_size = sizeof(struct macb_dma_desc)
129 + sizeof(struct macb_dma_desc_64)
130 + sizeof(struct macb_dma_desc_ptp);
133 desc_size = sizeof(struct macb_dma_desc);
137 return sizeof(struct macb_dma_desc);
140 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
143 switch (bp->hw_dma_cap) {
148 case HW_DMA_CAP_64B_PTP:
158 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
159 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
161 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
162 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
167 /* Ring buffer accessors */
168 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
170 return index & (bp->tx_ring_size - 1);
173 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
176 index = macb_tx_ring_wrap(queue->bp, index);
177 index = macb_adj_dma_desc_idx(queue->bp, index);
178 return &queue->tx_ring[index];
181 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
184 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
187 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
191 offset = macb_tx_ring_wrap(queue->bp, index) *
192 macb_dma_desc_get_size(queue->bp);
194 return queue->tx_ring_dma + offset;
197 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
199 return index & (bp->rx_ring_size - 1);
202 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
204 index = macb_rx_ring_wrap(queue->bp, index);
205 index = macb_adj_dma_desc_idx(queue->bp, index);
206 return &queue->rx_ring[index];
209 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
211 return queue->rx_buffers + queue->bp->rx_buffer_size *
212 macb_rx_ring_wrap(queue->bp, index);
216 static u32 hw_readl_native(struct macb *bp, int offset)
218 return __raw_readl(bp->regs + offset);
221 static void hw_writel_native(struct macb *bp, int offset, u32 value)
223 __raw_writel(value, bp->regs + offset);
226 static u32 hw_readl(struct macb *bp, int offset)
228 return readl_relaxed(bp->regs + offset);
231 static void hw_writel(struct macb *bp, int offset, u32 value)
233 writel_relaxed(value, bp->regs + offset);
236 /* Find the CPU endianness by using the loopback bit of NCR register. When the
237 * CPU is in big endian we need to program swapped mode for management
240 static bool hw_is_native_io(void __iomem *addr)
242 u32 value = MACB_BIT(LLB);
244 __raw_writel(value, addr + MACB_NCR);
245 value = __raw_readl(addr + MACB_NCR);
247 /* Write 0 back to disable everything */
248 __raw_writel(0, addr + MACB_NCR);
250 return value == MACB_BIT(LLB);
253 static bool hw_is_gem(void __iomem *addr, bool native_io)
258 id = __raw_readl(addr + MACB_MID);
260 id = readl_relaxed(addr + MACB_MID);
262 return MACB_BFEXT(IDNUM, id) >= 0x2;
265 static void macb_set_hwaddr(struct macb *bp)
270 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
271 macb_or_gem_writel(bp, SA1B, bottom);
272 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
273 macb_or_gem_writel(bp, SA1T, top);
275 /* Clear unused address register sets */
276 macb_or_gem_writel(bp, SA2B, 0);
277 macb_or_gem_writel(bp, SA2T, 0);
278 macb_or_gem_writel(bp, SA3B, 0);
279 macb_or_gem_writel(bp, SA3T, 0);
280 macb_or_gem_writel(bp, SA4B, 0);
281 macb_or_gem_writel(bp, SA4T, 0);
284 static void macb_get_hwaddr(struct macb *bp)
286 struct macb_platform_data *pdata;
292 pdata = dev_get_platdata(&bp->pdev->dev);
294 /* Check all 4 address register for valid address */
295 for (i = 0; i < 4; i++) {
296 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
297 top = macb_or_gem_readl(bp, SA1T + i * 8);
299 if (pdata && pdata->rev_eth_addr) {
300 addr[5] = bottom & 0xff;
301 addr[4] = (bottom >> 8) & 0xff;
302 addr[3] = (bottom >> 16) & 0xff;
303 addr[2] = (bottom >> 24) & 0xff;
304 addr[1] = top & 0xff;
305 addr[0] = (top & 0xff00) >> 8;
307 addr[0] = bottom & 0xff;
308 addr[1] = (bottom >> 8) & 0xff;
309 addr[2] = (bottom >> 16) & 0xff;
310 addr[3] = (bottom >> 24) & 0xff;
311 addr[4] = top & 0xff;
312 addr[5] = (top >> 8) & 0xff;
315 if (is_valid_ether_addr(addr)) {
316 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
321 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
322 eth_hw_addr_random(bp->dev);
325 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
327 struct macb *bp = bus->priv;
330 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
331 | MACB_BF(RW, MACB_MAN_READ)
332 | MACB_BF(PHYA, mii_id)
333 | MACB_BF(REGA, regnum)
334 | MACB_BF(CODE, MACB_MAN_CODE)));
336 /* wait for end of transfer */
337 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
340 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
345 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
348 struct macb *bp = bus->priv;
350 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
351 | MACB_BF(RW, MACB_MAN_WRITE)
352 | MACB_BF(PHYA, mii_id)
353 | MACB_BF(REGA, regnum)
354 | MACB_BF(CODE, MACB_MAN_CODE)
355 | MACB_BF(DATA, value)));
357 /* wait for end of transfer */
358 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
365 * macb_set_tx_clk() - Set a clock to a new frequency
366 * @clk Pointer to the clock to change
367 * @rate New frequency in Hz
368 * @dev Pointer to the struct net_device
370 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
372 long ferr, rate, rate_rounded;
391 rate_rounded = clk_round_rate(clk, rate);
392 if (rate_rounded < 0)
395 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
398 ferr = abs(rate_rounded - rate);
399 ferr = DIV_ROUND_UP(ferr, rate / 100000);
401 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
404 if (clk_set_rate(clk, rate_rounded))
405 netdev_err(dev, "adjusting tx_clk failed.\n");
408 static void macb_handle_link_change(struct net_device *dev)
410 struct macb *bp = netdev_priv(dev);
411 struct phy_device *phydev = dev->phydev;
413 int status_change = 0;
415 spin_lock_irqsave(&bp->lock, flags);
418 if ((bp->speed != phydev->speed) ||
419 (bp->duplex != phydev->duplex)) {
422 reg = macb_readl(bp, NCFGR);
423 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
425 reg &= ~GEM_BIT(GBE);
429 if (phydev->speed == SPEED_100)
430 reg |= MACB_BIT(SPD);
431 if (phydev->speed == SPEED_1000 &&
432 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
435 macb_or_gem_writel(bp, NCFGR, reg);
437 bp->speed = phydev->speed;
438 bp->duplex = phydev->duplex;
443 if (phydev->link != bp->link) {
448 bp->link = phydev->link;
453 spin_unlock_irqrestore(&bp->lock, flags);
457 /* Update the TX clock rate if and only if the link is
458 * up and there has been a link change.
460 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
462 netif_carrier_on(dev);
463 netdev_info(dev, "link up (%d/%s)\n",
465 phydev->duplex == DUPLEX_FULL ?
468 netif_carrier_off(dev);
469 netdev_info(dev, "link down\n");
474 /* based on au1000_eth. c*/
475 static int macb_mii_probe(struct net_device *dev)
477 struct macb *bp = netdev_priv(dev);
478 struct macb_platform_data *pdata;
479 struct phy_device *phydev;
480 struct device_node *np;
483 pdata = dev_get_platdata(&bp->pdev->dev);
484 np = bp->pdev->dev.of_node;
488 if (of_phy_is_fixed_link(np)) {
489 bp->phy_node = of_node_get(np);
491 bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
492 /* fallback to standard phy registration if no
493 * phy-handle was found nor any phy found during
494 * dt phy registration
496 if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
497 for (i = 0; i < PHY_MAX_ADDR; i++) {
498 struct phy_device *phydev;
500 phydev = mdiobus_scan(bp->mii_bus, i);
501 if (IS_ERR(phydev) &&
502 PTR_ERR(phydev) != -ENODEV) {
503 ret = PTR_ERR(phydev);
515 phydev = of_phy_connect(dev, bp->phy_node,
516 &macb_handle_link_change, 0,
521 phydev = phy_find_first(bp->mii_bus);
523 netdev_err(dev, "no PHY found\n");
528 if (gpio_is_valid(pdata->phy_irq_pin)) {
529 ret = devm_gpio_request(&bp->pdev->dev,
530 pdata->phy_irq_pin, "phy int");
532 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
533 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
536 phydev->irq = PHY_POLL;
540 /* attach the mac to the phy */
541 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
544 netdev_err(dev, "Could not attach to PHY\n");
549 /* mask with MAC supported features */
550 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
551 phydev->supported &= PHY_GBIT_FEATURES;
553 phydev->supported &= PHY_BASIC_FEATURES;
555 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
556 phydev->supported &= ~SUPPORTED_1000baseT_Half;
558 phydev->advertising = phydev->supported;
567 static int macb_mii_init(struct macb *bp)
569 struct macb_platform_data *pdata;
570 struct device_node *np;
573 /* Enable management port */
574 macb_writel(bp, NCR, MACB_BIT(MPE));
576 bp->mii_bus = mdiobus_alloc();
582 bp->mii_bus->name = "MACB_mii_bus";
583 bp->mii_bus->read = &macb_mdio_read;
584 bp->mii_bus->write = &macb_mdio_write;
585 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
586 bp->pdev->name, bp->pdev->id);
587 bp->mii_bus->priv = bp;
588 bp->mii_bus->parent = &bp->pdev->dev;
589 pdata = dev_get_platdata(&bp->pdev->dev);
591 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
593 np = bp->pdev->dev.of_node;
594 if (np && of_phy_is_fixed_link(np)) {
595 if (of_phy_register_fixed_link(np) < 0) {
596 dev_err(&bp->pdev->dev,
597 "broken fixed-link specification %pOF\n", np);
598 goto err_out_free_mdiobus;
601 err = mdiobus_register(bp->mii_bus);
604 bp->mii_bus->phy_mask = pdata->phy_mask;
606 err = of_mdiobus_register(bp->mii_bus, np);
610 goto err_out_free_fixed_link;
612 err = macb_mii_probe(bp->dev);
614 goto err_out_unregister_bus;
618 err_out_unregister_bus:
619 mdiobus_unregister(bp->mii_bus);
620 err_out_free_fixed_link:
621 if (np && of_phy_is_fixed_link(np))
622 of_phy_deregister_fixed_link(np);
623 err_out_free_mdiobus:
624 of_node_put(bp->phy_node);
625 mdiobus_free(bp->mii_bus);
630 static void macb_update_stats(struct macb *bp)
632 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
633 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
634 int offset = MACB_PFR;
636 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
638 for (; p < end; p++, offset += 4)
639 *p += bp->macb_reg_readl(bp, offset);
642 static int macb_halt_tx(struct macb *bp)
644 unsigned long halt_time, timeout;
647 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
649 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
652 status = macb_readl(bp, TSR);
653 if (!(status & MACB_BIT(TGO)))
657 } while (time_before(halt_time, timeout));
662 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
664 if (tx_skb->mapping) {
665 if (tx_skb->mapped_as_page)
666 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
667 tx_skb->size, DMA_TO_DEVICE);
669 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
670 tx_skb->size, DMA_TO_DEVICE);
675 dev_kfree_skb_any(tx_skb->skb);
680 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
682 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
683 struct macb_dma_desc_64 *desc_64;
685 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
686 desc_64 = macb_64b_desc(bp, desc);
687 desc_64->addrh = upper_32_bits(addr);
688 /* The low bits of RX address contain the RX_USED bit, clearing
689 * of which allows packet RX. Make sure the high bits are also
690 * visible to HW at that point.
695 desc->addr = lower_32_bits(addr);
698 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
701 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
702 struct macb_dma_desc_64 *desc_64;
704 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
705 desc_64 = macb_64b_desc(bp, desc);
706 addr = ((u64)(desc_64->addrh) << 32);
709 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
713 static void macb_tx_error_task(struct work_struct *work)
715 struct macb_queue *queue = container_of(work, struct macb_queue,
717 struct macb *bp = queue->bp;
718 struct macb_tx_skb *tx_skb;
719 struct macb_dma_desc *desc;
724 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
725 (unsigned int)(queue - bp->queues),
726 queue->tx_tail, queue->tx_head);
728 /* Prevent the queue IRQ handlers from running: each of them may call
729 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
730 * As explained below, we have to halt the transmission before updating
731 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
732 * network engine about the macb/gem being halted.
734 spin_lock_irqsave(&bp->lock, flags);
736 /* Make sure nobody is trying to queue up new packets */
737 netif_tx_stop_all_queues(bp->dev);
739 /* Stop transmission now
740 * (in case we have just queued new packets)
741 * macb/gem must be halted to write TBQP register
743 if (macb_halt_tx(bp))
744 /* Just complain for now, reinitializing TX path can be good */
745 netdev_err(bp->dev, "BUG: halt tx timed out\n");
747 /* Treat frames in TX queue including the ones that caused the error.
748 * Free transmit buffers in upper layer.
750 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
753 desc = macb_tx_desc(queue, tail);
755 tx_skb = macb_tx_skb(queue, tail);
758 if (ctrl & MACB_BIT(TX_USED)) {
759 /* skb is set for the last buffer of the frame */
761 macb_tx_unmap(bp, tx_skb);
763 tx_skb = macb_tx_skb(queue, tail);
767 /* ctrl still refers to the first buffer descriptor
768 * since it's the only one written back by the hardware
770 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
771 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
772 macb_tx_ring_wrap(bp, tail),
774 bp->dev->stats.tx_packets++;
775 queue->stats.tx_packets++;
776 bp->dev->stats.tx_bytes += skb->len;
777 queue->stats.tx_bytes += skb->len;
780 /* "Buffers exhausted mid-frame" errors may only happen
781 * if the driver is buggy, so complain loudly about
782 * those. Statistics are updated by hardware.
784 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
786 "BUG: TX buffers exhausted mid-frame\n");
788 desc->ctrl = ctrl | MACB_BIT(TX_USED);
791 macb_tx_unmap(bp, tx_skb);
794 /* Set end of TX queue */
795 desc = macb_tx_desc(queue, 0);
796 macb_set_addr(bp, desc, 0);
797 desc->ctrl = MACB_BIT(TX_USED);
799 /* Make descriptor updates visible to hardware */
802 /* Reinitialize the TX desc queue */
803 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
804 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
805 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
806 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
808 /* Make TX ring reflect state of hardware */
812 /* Housework before enabling TX IRQ */
813 macb_writel(bp, TSR, macb_readl(bp, TSR));
814 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
816 /* Now we are ready to start transmission again */
817 netif_tx_start_all_queues(bp->dev);
818 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
820 spin_unlock_irqrestore(&bp->lock, flags);
823 static void macb_tx_interrupt(struct macb_queue *queue)
828 struct macb *bp = queue->bp;
829 u16 queue_index = queue - bp->queues;
831 status = macb_readl(bp, TSR);
832 macb_writel(bp, TSR, status);
834 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
835 queue_writel(queue, ISR, MACB_BIT(TCOMP));
837 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
838 (unsigned long)status);
840 head = queue->tx_head;
841 for (tail = queue->tx_tail; tail != head; tail++) {
842 struct macb_tx_skb *tx_skb;
844 struct macb_dma_desc *desc;
847 desc = macb_tx_desc(queue, tail);
849 /* Make hw descriptor updates visible to CPU */
854 /* TX_USED bit is only set by hardware on the very first buffer
855 * descriptor of the transmitted frame.
857 if (!(ctrl & MACB_BIT(TX_USED)))
860 /* Process all buffers of the current transmitted frame */
862 tx_skb = macb_tx_skb(queue, tail);
865 /* First, update TX stats if needed */
867 if (unlikely(skb_shinfo(skb)->tx_flags &
869 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
870 /* skb now belongs to timestamp buffer
871 * and will be removed later
875 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
876 macb_tx_ring_wrap(bp, tail),
878 bp->dev->stats.tx_packets++;
879 queue->stats.tx_packets++;
880 bp->dev->stats.tx_bytes += skb->len;
881 queue->stats.tx_bytes += skb->len;
884 /* Now we can safely release resources */
885 macb_tx_unmap(bp, tx_skb);
887 /* skb is set only for the last buffer of the frame.
888 * WARNING: at this point skb has been freed by
896 queue->tx_tail = tail;
897 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
898 CIRC_CNT(queue->tx_head, queue->tx_tail,
899 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
900 netif_wake_subqueue(bp->dev, queue_index);
903 static void gem_rx_refill(struct macb_queue *queue)
908 struct macb *bp = queue->bp;
909 struct macb_dma_desc *desc;
911 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
912 bp->rx_ring_size) > 0) {
913 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
915 /* Make hw descriptor updates visible to CPU */
918 desc = macb_rx_desc(queue, entry);
920 if (!queue->rx_skbuff[entry]) {
921 /* allocate sk_buff for this free entry in ring */
922 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
923 if (unlikely(!skb)) {
925 "Unable to allocate sk_buff\n");
929 /* now fill corresponding descriptor entry */
930 paddr = dma_map_single(&bp->pdev->dev, skb->data,
933 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
938 queue->rx_skbuff[entry] = skb;
940 if (entry == bp->rx_ring_size - 1)
941 paddr |= MACB_BIT(RX_WRAP);
943 /* Setting addr clears RX_USED and allows reception,
944 * make sure ctrl is cleared first to avoid a race.
947 macb_set_addr(bp, desc, paddr);
949 /* properly align Ethernet header */
950 skb_reserve(skb, NET_IP_ALIGN);
954 desc->addr &= ~MACB_BIT(RX_USED);
956 queue->rx_prepared_head++;
959 /* Make descriptor updates visible to hardware */
962 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
963 queue, queue->rx_prepared_head, queue->rx_tail);
966 /* Mark DMA descriptors from begin up to and not including end as unused */
967 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
972 for (frag = begin; frag != end; frag++) {
973 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
975 desc->addr &= ~MACB_BIT(RX_USED);
978 /* Make descriptor updates visible to hardware */
981 /* When this happens, the hardware stats registers for
982 * whatever caused this is updated, so we don't have to record
987 static int gem_rx(struct macb_queue *queue, int budget)
989 struct macb *bp = queue->bp;
993 struct macb_dma_desc *desc;
996 while (count < budget) {
1001 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1002 desc = macb_rx_desc(queue, entry);
1004 /* Make hw descriptor updates visible to CPU */
1007 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1008 addr = macb_get_addr(bp, desc);
1013 /* Ensure ctrl is at least as up-to-date as rxused */
1021 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1023 "not whole frame pointed by descriptor\n");
1024 bp->dev->stats.rx_dropped++;
1025 queue->stats.rx_dropped++;
1028 skb = queue->rx_skbuff[entry];
1029 if (unlikely(!skb)) {
1031 "inconsistent Rx descriptor chain\n");
1032 bp->dev->stats.rx_dropped++;
1033 queue->stats.rx_dropped++;
1036 /* now everything is ready for receiving packet */
1037 queue->rx_skbuff[entry] = NULL;
1038 len = ctrl & bp->rx_frm_len_mask;
1040 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1043 dma_unmap_single(&bp->pdev->dev, addr,
1044 bp->rx_buffer_size, DMA_FROM_DEVICE);
1046 skb->protocol = eth_type_trans(skb, bp->dev);
1047 skb_checksum_none_assert(skb);
1048 if (bp->dev->features & NETIF_F_RXCSUM &&
1049 !(bp->dev->flags & IFF_PROMISC) &&
1050 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1051 skb->ip_summed = CHECKSUM_UNNECESSARY;
1053 bp->dev->stats.rx_packets++;
1054 queue->stats.rx_packets++;
1055 bp->dev->stats.rx_bytes += skb->len;
1056 queue->stats.rx_bytes += skb->len;
1058 gem_ptp_do_rxstamp(bp, skb, desc);
1060 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1061 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1062 skb->len, skb->csum);
1063 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1064 skb_mac_header(skb), 16, true);
1065 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1066 skb->data, 32, true);
1069 netif_receive_skb(skb);
1072 gem_rx_refill(queue);
1077 static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag,
1078 unsigned int last_frag)
1082 unsigned int offset;
1083 struct sk_buff *skb;
1084 struct macb_dma_desc *desc;
1085 struct macb *bp = queue->bp;
1087 desc = macb_rx_desc(queue, last_frag);
1088 len = desc->ctrl & bp->rx_frm_len_mask;
1090 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1091 macb_rx_ring_wrap(bp, first_frag),
1092 macb_rx_ring_wrap(bp, last_frag), len);
1094 /* The ethernet header starts NET_IP_ALIGN bytes into the
1095 * first buffer. Since the header is 14 bytes, this makes the
1096 * payload word-aligned.
1098 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1099 * the two padding bytes into the skb so that we avoid hitting
1100 * the slowpath in memcpy(), and pull them off afterwards.
1102 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1104 bp->dev->stats.rx_dropped++;
1105 for (frag = first_frag; ; frag++) {
1106 desc = macb_rx_desc(queue, frag);
1107 desc->addr &= ~MACB_BIT(RX_USED);
1108 if (frag == last_frag)
1112 /* Make descriptor updates visible to hardware */
1119 len += NET_IP_ALIGN;
1120 skb_checksum_none_assert(skb);
1123 for (frag = first_frag; ; frag++) {
1124 unsigned int frag_len = bp->rx_buffer_size;
1126 if (offset + frag_len > len) {
1127 if (unlikely(frag != last_frag)) {
1128 dev_kfree_skb_any(skb);
1131 frag_len = len - offset;
1133 skb_copy_to_linear_data_offset(skb, offset,
1134 macb_rx_buffer(queue, frag),
1136 offset += bp->rx_buffer_size;
1137 desc = macb_rx_desc(queue, frag);
1138 desc->addr &= ~MACB_BIT(RX_USED);
1140 if (frag == last_frag)
1144 /* Make descriptor updates visible to hardware */
1147 __skb_pull(skb, NET_IP_ALIGN);
1148 skb->protocol = eth_type_trans(skb, bp->dev);
1150 bp->dev->stats.rx_packets++;
1151 bp->dev->stats.rx_bytes += skb->len;
1152 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1153 skb->len, skb->csum);
1154 netif_receive_skb(skb);
1159 static inline void macb_init_rx_ring(struct macb_queue *queue)
1161 struct macb *bp = queue->bp;
1163 struct macb_dma_desc *desc = NULL;
1166 addr = queue->rx_buffers_dma;
1167 for (i = 0; i < bp->rx_ring_size; i++) {
1168 desc = macb_rx_desc(queue, i);
1169 macb_set_addr(bp, desc, addr);
1171 addr += bp->rx_buffer_size;
1173 desc->addr |= MACB_BIT(RX_WRAP);
1177 static int macb_rx(struct macb_queue *queue, int budget)
1179 struct macb *bp = queue->bp;
1180 bool reset_rx_queue = false;
1183 int first_frag = -1;
1185 for (tail = queue->rx_tail; budget > 0; tail++) {
1186 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1189 /* Make hw descriptor updates visible to CPU */
1192 if (!(desc->addr & MACB_BIT(RX_USED)))
1195 /* Ensure ctrl is at least as up-to-date as addr */
1200 if (ctrl & MACB_BIT(RX_SOF)) {
1201 if (first_frag != -1)
1202 discard_partial_frame(queue, first_frag, tail);
1206 if (ctrl & MACB_BIT(RX_EOF)) {
1209 if (unlikely(first_frag == -1)) {
1210 reset_rx_queue = true;
1214 dropped = macb_rx_frame(queue, first_frag, tail);
1216 if (unlikely(dropped < 0)) {
1217 reset_rx_queue = true;
1227 if (unlikely(reset_rx_queue)) {
1228 unsigned long flags;
1231 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1233 spin_lock_irqsave(&bp->lock, flags);
1235 ctrl = macb_readl(bp, NCR);
1236 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1238 macb_init_rx_ring(queue);
1239 queue_writel(queue, RBQP, queue->rx_ring_dma);
1241 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1243 spin_unlock_irqrestore(&bp->lock, flags);
1247 if (first_frag != -1)
1248 queue->rx_tail = first_frag;
1250 queue->rx_tail = tail;
1255 static int macb_poll(struct napi_struct *napi, int budget)
1257 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1258 struct macb *bp = queue->bp;
1262 status = macb_readl(bp, RSR);
1263 macb_writel(bp, RSR, status);
1265 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1266 (unsigned long)status, budget);
1268 work_done = bp->macbgem_ops.mog_rx(queue, budget);
1269 if (work_done < budget) {
1270 napi_complete_done(napi, work_done);
1272 /* RSR bits only seem to propagate to raise interrupts when
1273 * interrupts are enabled at the time, so if bits are already
1274 * set due to packets received while interrupts were disabled,
1275 * they will not cause another interrupt to be generated when
1276 * interrupts are re-enabled.
1277 * Check for this case here. This has been seen to happen
1278 * around 30% of the time under heavy network load.
1280 status = macb_readl(bp, RSR);
1282 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1283 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1284 napi_reschedule(napi);
1286 queue_writel(queue, IER, bp->rx_intr_mask);
1288 /* In rare cases, packets could have been received in
1289 * the window between the check above and re-enabling
1290 * interrupts. Therefore, a double-check is required
1291 * to avoid losing a wakeup. This can potentially race
1292 * with the interrupt handler doing the same actions
1293 * if an interrupt is raised just after enabling them,
1294 * but this should be harmless.
1296 status = macb_readl(bp, RSR);
1297 if (unlikely(status)) {
1298 queue_writel(queue, IDR, bp->rx_intr_mask);
1299 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1300 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1301 napi_schedule(napi);
1306 /* TODO: Handle errors */
1311 static void macb_hresp_error_task(unsigned long data)
1313 struct macb *bp = (struct macb *)data;
1314 struct net_device *dev = bp->dev;
1315 struct macb_queue *queue = bp->queues;
1319 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1320 queue_writel(queue, IDR, bp->rx_intr_mask |
1324 ctrl = macb_readl(bp, NCR);
1325 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1326 macb_writel(bp, NCR, ctrl);
1328 netif_tx_stop_all_queues(dev);
1329 netif_carrier_off(dev);
1331 bp->macbgem_ops.mog_init_rings(bp);
1333 /* Initialize TX and RX buffers */
1334 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1335 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1336 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1337 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1338 queue_writel(queue, RBQPH,
1339 upper_32_bits(queue->rx_ring_dma));
1341 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1342 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1343 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1344 queue_writel(queue, TBQPH,
1345 upper_32_bits(queue->tx_ring_dma));
1348 /* Enable interrupts */
1349 queue_writel(queue, IER,
1355 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1356 macb_writel(bp, NCR, ctrl);
1358 netif_carrier_on(dev);
1359 netif_tx_start_all_queues(dev);
1362 static void macb_tx_restart(struct macb_queue *queue)
1364 unsigned int head = queue->tx_head;
1365 unsigned int tail = queue->tx_tail;
1366 struct macb *bp = queue->bp;
1367 unsigned int head_idx, tbqp;
1369 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1370 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1375 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1376 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1377 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, head));
1379 if (tbqp == head_idx)
1382 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1385 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1387 struct macb_queue *queue = dev_id;
1388 struct macb *bp = queue->bp;
1389 struct net_device *dev = bp->dev;
1392 status = queue_readl(queue, ISR);
1394 if (unlikely(!status))
1397 spin_lock(&bp->lock);
1400 /* close possible race with dev_close */
1401 if (unlikely(!netif_running(dev))) {
1402 queue_writel(queue, IDR, -1);
1403 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1404 queue_writel(queue, ISR, -1);
1408 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1409 (unsigned int)(queue - bp->queues),
1410 (unsigned long)status);
1412 if (status & bp->rx_intr_mask) {
1413 /* There's no point taking any more interrupts
1414 * until we have processed the buffers. The
1415 * scheduling call may fail if the poll routine
1416 * is already scheduled, so disable interrupts
1419 queue_writel(queue, IDR, bp->rx_intr_mask);
1420 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1421 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1423 if (napi_schedule_prep(&queue->napi)) {
1424 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1425 __napi_schedule(&queue->napi);
1429 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1430 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1431 schedule_work(&queue->tx_error_task);
1433 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1434 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1439 if (status & MACB_BIT(TCOMP))
1440 macb_tx_interrupt(queue);
1442 if (status & MACB_BIT(TXUBR))
1443 macb_tx_restart(queue);
1445 /* Link change detection isn't possible with RMII, so we'll
1446 * add that if/when we get our hands on a full-blown MII PHY.
1449 /* There is a hardware issue under heavy load where DMA can
1450 * stop, this causes endless "used buffer descriptor read"
1451 * interrupts but it can be cleared by re-enabling RX. See
1452 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1453 * section 16.7.4 for details. RXUBR is only enabled for
1454 * these two versions.
1456 if (status & MACB_BIT(RXUBR)) {
1457 ctrl = macb_readl(bp, NCR);
1458 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1460 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1462 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1463 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1466 if (status & MACB_BIT(ISR_ROVR)) {
1467 /* We missed at least one packet */
1468 if (macb_is_gem(bp))
1469 bp->hw_stats.gem.rx_overruns++;
1471 bp->hw_stats.macb.rx_overruns++;
1473 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1474 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1477 if (status & MACB_BIT(HRESP)) {
1478 tasklet_schedule(&bp->hresp_err_tasklet);
1479 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1481 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1482 queue_writel(queue, ISR, MACB_BIT(HRESP));
1484 status = queue_readl(queue, ISR);
1487 spin_unlock(&bp->lock);
1492 #ifdef CONFIG_NET_POLL_CONTROLLER
1493 /* Polling receive - used by netconsole and other diagnostic tools
1494 * to allow network i/o with interrupts disabled.
1496 static void macb_poll_controller(struct net_device *dev)
1498 struct macb *bp = netdev_priv(dev);
1499 struct macb_queue *queue;
1500 unsigned long flags;
1503 local_irq_save(flags);
1504 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1505 macb_interrupt(dev->irq, queue);
1506 local_irq_restore(flags);
1510 static unsigned int macb_tx_map(struct macb *bp,
1511 struct macb_queue *queue,
1512 struct sk_buff *skb,
1513 unsigned int hdrlen)
1516 unsigned int len, entry, i, tx_head = queue->tx_head;
1517 struct macb_tx_skb *tx_skb = NULL;
1518 struct macb_dma_desc *desc;
1519 unsigned int offset, size, count = 0;
1520 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1521 unsigned int eof = 1, mss_mfs = 0;
1522 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1525 if (skb_shinfo(skb)->gso_size != 0) {
1526 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1528 lso_ctrl = MACB_LSO_UFO_ENABLE;
1531 lso_ctrl = MACB_LSO_TSO_ENABLE;
1534 /* First, map non-paged data */
1535 len = skb_headlen(skb);
1537 /* first buffer length */
1542 entry = macb_tx_ring_wrap(bp, tx_head);
1543 tx_skb = &queue->tx_skb[entry];
1545 mapping = dma_map_single(&bp->pdev->dev,
1547 size, DMA_TO_DEVICE);
1548 if (dma_mapping_error(&bp->pdev->dev, mapping))
1551 /* Save info to properly release resources */
1553 tx_skb->mapping = mapping;
1554 tx_skb->size = size;
1555 tx_skb->mapped_as_page = false;
1562 size = min(len, bp->max_tx_length);
1565 /* Then, map paged data from fragments */
1566 for (f = 0; f < nr_frags; f++) {
1567 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1569 len = skb_frag_size(frag);
1572 size = min(len, bp->max_tx_length);
1573 entry = macb_tx_ring_wrap(bp, tx_head);
1574 tx_skb = &queue->tx_skb[entry];
1576 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1577 offset, size, DMA_TO_DEVICE);
1578 if (dma_mapping_error(&bp->pdev->dev, mapping))
1581 /* Save info to properly release resources */
1583 tx_skb->mapping = mapping;
1584 tx_skb->size = size;
1585 tx_skb->mapped_as_page = true;
1594 /* Should never happen */
1595 if (unlikely(!tx_skb)) {
1596 netdev_err(bp->dev, "BUG! empty skb!\n");
1600 /* This is the last buffer of the frame: save socket buffer */
1603 /* Update TX ring: update buffer descriptors in reverse order
1604 * to avoid race condition
1607 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1608 * to set the end of TX queue
1611 entry = macb_tx_ring_wrap(bp, i);
1612 ctrl = MACB_BIT(TX_USED);
1613 desc = macb_tx_desc(queue, entry);
1617 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1618 /* include header and FCS in value given to h/w */
1619 mss_mfs = skb_shinfo(skb)->gso_size +
1620 skb_transport_offset(skb) +
1623 mss_mfs = skb_shinfo(skb)->gso_size;
1624 /* TCP Sequence Number Source Select
1625 * can be set only for TSO
1633 entry = macb_tx_ring_wrap(bp, i);
1634 tx_skb = &queue->tx_skb[entry];
1635 desc = macb_tx_desc(queue, entry);
1637 ctrl = (u32)tx_skb->size;
1639 ctrl |= MACB_BIT(TX_LAST);
1642 if (unlikely(entry == (bp->tx_ring_size - 1)))
1643 ctrl |= MACB_BIT(TX_WRAP);
1645 /* First descriptor is header descriptor */
1646 if (i == queue->tx_head) {
1647 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1648 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1649 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1650 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1651 ctrl |= MACB_BIT(TX_NOCRC);
1653 /* Only set MSS/MFS on payload descriptors
1654 * (second or later descriptor)
1656 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1658 /* Set TX buffer descriptor */
1659 macb_set_addr(bp, desc, tx_skb->mapping);
1660 /* desc->addr must be visible to hardware before clearing
1661 * 'TX_USED' bit in desc->ctrl.
1665 } while (i != queue->tx_head);
1667 queue->tx_head = tx_head;
1672 netdev_err(bp->dev, "TX DMA map failed\n");
1674 for (i = queue->tx_head; i != tx_head; i++) {
1675 tx_skb = macb_tx_skb(queue, i);
1677 macb_tx_unmap(bp, tx_skb);
1683 static netdev_features_t macb_features_check(struct sk_buff *skb,
1684 struct net_device *dev,
1685 netdev_features_t features)
1687 unsigned int nr_frags, f;
1688 unsigned int hdrlen;
1690 /* Validate LSO compatibility */
1692 /* there is only one buffer or protocol is not UDP */
1693 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1696 /* length of header */
1697 hdrlen = skb_transport_offset(skb);
1700 * When software supplies two or more payload buffers all payload buffers
1701 * apart from the last must be a multiple of 8 bytes in size.
1703 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1704 return features & ~MACB_NETIF_LSO;
1706 nr_frags = skb_shinfo(skb)->nr_frags;
1707 /* No need to check last fragment */
1709 for (f = 0; f < nr_frags; f++) {
1710 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1712 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1713 return features & ~MACB_NETIF_LSO;
1718 static inline int macb_clear_csum(struct sk_buff *skb)
1720 /* no change for packets without checksum offloading */
1721 if (skb->ip_summed != CHECKSUM_PARTIAL)
1724 /* make sure we can modify the header */
1725 if (unlikely(skb_cow_head(skb, 0)))
1728 /* initialize checksum field
1729 * This is required - at least for Zynq, which otherwise calculates
1730 * wrong UDP header checksums for UDP packets with UDP data len <=2
1732 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1736 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1738 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
1739 skb_is_nonlinear(*skb);
1740 int padlen = ETH_ZLEN - (*skb)->len;
1741 int headroom = skb_headroom(*skb);
1742 int tailroom = skb_tailroom(*skb);
1743 struct sk_buff *nskb;
1746 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1747 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1748 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1752 /* FCS could be appeded to tailroom. */
1753 if (tailroom >= ETH_FCS_LEN)
1755 /* FCS could be appeded by moving data to headroom. */
1756 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1758 /* No room for FCS, need to reallocate skb. */
1760 padlen = ETH_FCS_LEN;
1762 /* Add room for FCS. */
1763 padlen += ETH_FCS_LEN;
1766 if (!cloned && headroom + tailroom >= padlen) {
1767 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1768 skb_set_tail_pointer(*skb, (*skb)->len);
1770 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1774 dev_kfree_skb_any(*skb);
1779 if (padlen >= ETH_FCS_LEN)
1780 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1782 skb_trim(*skb, ETH_FCS_LEN - padlen);
1786 /* set FCS to packet */
1787 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1790 skb_put_u8(*skb, fcs & 0xff);
1791 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1792 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1793 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1798 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1800 u16 queue_index = skb_get_queue_mapping(skb);
1801 struct macb *bp = netdev_priv(dev);
1802 struct macb_queue *queue = &bp->queues[queue_index];
1803 unsigned long flags;
1804 unsigned int desc_cnt, nr_frags, frag_size, f;
1805 unsigned int hdrlen;
1806 bool is_lso, is_udp = 0;
1807 netdev_tx_t ret = NETDEV_TX_OK;
1809 if (macb_clear_csum(skb)) {
1810 dev_kfree_skb_any(skb);
1814 if (macb_pad_and_fcs(&skb, dev)) {
1815 dev_kfree_skb_any(skb);
1819 is_lso = (skb_shinfo(skb)->gso_size != 0);
1822 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1824 /* length of headers */
1826 /* only queue eth + ip headers separately for UDP */
1827 hdrlen = skb_transport_offset(skb);
1829 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1830 if (skb_headlen(skb) < hdrlen) {
1831 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1832 /* if this is required, would need to copy to single buffer */
1833 return NETDEV_TX_BUSY;
1836 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1838 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1839 netdev_vdbg(bp->dev,
1840 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1841 queue_index, skb->len, skb->head, skb->data,
1842 skb_tail_pointer(skb), skb_end_pointer(skb));
1843 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1844 skb->data, 16, true);
1847 /* Count how many TX buffer descriptors are needed to send this
1848 * socket buffer: skb fragments of jumbo frames may need to be
1849 * split into many buffer descriptors.
1851 if (is_lso && (skb_headlen(skb) > hdrlen))
1852 /* extra header descriptor if also payload in first buffer */
1853 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1855 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1856 nr_frags = skb_shinfo(skb)->nr_frags;
1857 for (f = 0; f < nr_frags; f++) {
1858 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1859 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1862 spin_lock_irqsave(&bp->lock, flags);
1864 /* This is a hard error, log it. */
1865 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1866 bp->tx_ring_size) < desc_cnt) {
1867 netif_stop_subqueue(dev, queue_index);
1868 spin_unlock_irqrestore(&bp->lock, flags);
1869 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1870 queue->tx_head, queue->tx_tail);
1871 return NETDEV_TX_BUSY;
1874 /* Map socket buffer for DMA transfer */
1875 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1876 dev_kfree_skb_any(skb);
1880 /* Make newly initialized descriptor visible to hardware */
1882 skb_tx_timestamp(skb);
1884 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1886 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1887 netif_stop_subqueue(dev, queue_index);
1890 spin_unlock_irqrestore(&bp->lock, flags);
1895 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1897 if (!macb_is_gem(bp)) {
1898 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1900 bp->rx_buffer_size = size;
1902 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1904 "RX buffer must be multiple of %d bytes, expanding\n",
1905 RX_BUFFER_MULTIPLE);
1906 bp->rx_buffer_size =
1907 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1911 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1912 bp->dev->mtu, bp->rx_buffer_size);
1915 static void gem_free_rx_buffers(struct macb *bp)
1917 struct sk_buff *skb;
1918 struct macb_dma_desc *desc;
1919 struct macb_queue *queue;
1924 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1925 if (!queue->rx_skbuff)
1928 for (i = 0; i < bp->rx_ring_size; i++) {
1929 skb = queue->rx_skbuff[i];
1934 desc = macb_rx_desc(queue, i);
1935 addr = macb_get_addr(bp, desc);
1937 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1939 dev_kfree_skb_any(skb);
1943 kfree(queue->rx_skbuff);
1944 queue->rx_skbuff = NULL;
1948 static void macb_free_rx_buffers(struct macb *bp)
1950 struct macb_queue *queue = &bp->queues[0];
1952 if (queue->rx_buffers) {
1953 dma_free_coherent(&bp->pdev->dev,
1954 bp->rx_ring_size * bp->rx_buffer_size,
1955 queue->rx_buffers, queue->rx_buffers_dma);
1956 queue->rx_buffers = NULL;
1960 static void macb_free_consistent(struct macb *bp)
1962 struct macb_queue *queue;
1966 bp->macbgem_ops.mog_free_rx_buffers(bp);
1968 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1969 kfree(queue->tx_skb);
1970 queue->tx_skb = NULL;
1971 if (queue->tx_ring) {
1972 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1973 dma_free_coherent(&bp->pdev->dev, size,
1974 queue->tx_ring, queue->tx_ring_dma);
1975 queue->tx_ring = NULL;
1977 if (queue->rx_ring) {
1978 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
1979 dma_free_coherent(&bp->pdev->dev, size,
1980 queue->rx_ring, queue->rx_ring_dma);
1981 queue->rx_ring = NULL;
1986 static int gem_alloc_rx_buffers(struct macb *bp)
1988 struct macb_queue *queue;
1992 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1993 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1994 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
1995 if (!queue->rx_skbuff)
1999 "Allocated %d RX struct sk_buff entries at %p\n",
2000 bp->rx_ring_size, queue->rx_skbuff);
2005 static int macb_alloc_rx_buffers(struct macb *bp)
2007 struct macb_queue *queue = &bp->queues[0];
2010 size = bp->rx_ring_size * bp->rx_buffer_size;
2011 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2012 &queue->rx_buffers_dma, GFP_KERNEL);
2013 if (!queue->rx_buffers)
2017 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2018 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2022 static int macb_alloc_consistent(struct macb *bp)
2024 struct macb_queue *queue;
2028 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2029 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2030 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2031 &queue->tx_ring_dma,
2033 if (!queue->tx_ring)
2036 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2037 q, size, (unsigned long)queue->tx_ring_dma,
2040 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2041 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2045 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2046 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2047 &queue->rx_ring_dma, GFP_KERNEL);
2048 if (!queue->rx_ring)
2051 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2052 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2054 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2060 macb_free_consistent(bp);
2064 static void gem_init_rings(struct macb *bp)
2066 struct macb_queue *queue;
2067 struct macb_dma_desc *desc = NULL;
2071 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2072 for (i = 0; i < bp->tx_ring_size; i++) {
2073 desc = macb_tx_desc(queue, i);
2074 macb_set_addr(bp, desc, 0);
2075 desc->ctrl = MACB_BIT(TX_USED);
2077 desc->ctrl |= MACB_BIT(TX_WRAP);
2082 queue->rx_prepared_head = 0;
2084 gem_rx_refill(queue);
2089 static void macb_init_rings(struct macb *bp)
2092 struct macb_dma_desc *desc = NULL;
2094 macb_init_rx_ring(&bp->queues[0]);
2096 for (i = 0; i < bp->tx_ring_size; i++) {
2097 desc = macb_tx_desc(&bp->queues[0], i);
2098 macb_set_addr(bp, desc, 0);
2099 desc->ctrl = MACB_BIT(TX_USED);
2101 bp->queues[0].tx_head = 0;
2102 bp->queues[0].tx_tail = 0;
2103 desc->ctrl |= MACB_BIT(TX_WRAP);
2106 static void macb_reset_hw(struct macb *bp)
2108 struct macb_queue *queue;
2110 u32 ctrl = macb_readl(bp, NCR);
2112 /* Disable RX and TX (XXX: Should we halt the transmission
2115 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2117 /* Clear the stats registers (XXX: Update stats first?) */
2118 ctrl |= MACB_BIT(CLRSTAT);
2120 macb_writel(bp, NCR, ctrl);
2122 /* Clear all status flags */
2123 macb_writel(bp, TSR, -1);
2124 macb_writel(bp, RSR, -1);
2126 /* Disable all interrupts */
2127 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2128 queue_writel(queue, IDR, -1);
2129 queue_readl(queue, ISR);
2130 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2131 queue_writel(queue, ISR, -1);
2135 static u32 gem_mdc_clk_div(struct macb *bp)
2138 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2140 if (pclk_hz <= 20000000)
2141 config = GEM_BF(CLK, GEM_CLK_DIV8);
2142 else if (pclk_hz <= 40000000)
2143 config = GEM_BF(CLK, GEM_CLK_DIV16);
2144 else if (pclk_hz <= 80000000)
2145 config = GEM_BF(CLK, GEM_CLK_DIV32);
2146 else if (pclk_hz <= 120000000)
2147 config = GEM_BF(CLK, GEM_CLK_DIV48);
2148 else if (pclk_hz <= 160000000)
2149 config = GEM_BF(CLK, GEM_CLK_DIV64);
2151 config = GEM_BF(CLK, GEM_CLK_DIV96);
2156 static u32 macb_mdc_clk_div(struct macb *bp)
2159 unsigned long pclk_hz;
2161 if (macb_is_gem(bp))
2162 return gem_mdc_clk_div(bp);
2164 pclk_hz = clk_get_rate(bp->pclk);
2165 if (pclk_hz <= 20000000)
2166 config = MACB_BF(CLK, MACB_CLK_DIV8);
2167 else if (pclk_hz <= 40000000)
2168 config = MACB_BF(CLK, MACB_CLK_DIV16);
2169 else if (pclk_hz <= 80000000)
2170 config = MACB_BF(CLK, MACB_CLK_DIV32);
2172 config = MACB_BF(CLK, MACB_CLK_DIV64);
2177 /* Get the DMA bus width field of the network configuration register that we
2178 * should program. We find the width from decoding the design configuration
2179 * register to find the maximum supported data bus width.
2181 static u32 macb_dbw(struct macb *bp)
2183 if (!macb_is_gem(bp))
2186 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2188 return GEM_BF(DBW, GEM_DBW128);
2190 return GEM_BF(DBW, GEM_DBW64);
2193 return GEM_BF(DBW, GEM_DBW32);
2197 /* Configure the receive DMA engine
2198 * - use the correct receive buffer size
2199 * - set best burst length for DMA operations
2200 * (if not supported by FIFO, it will fallback to default)
2201 * - set both rx/tx packet buffers to full memory size
2202 * These are configurable parameters for GEM.
2204 static void macb_configure_dma(struct macb *bp)
2206 struct macb_queue *queue;
2211 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2212 if (macb_is_gem(bp)) {
2213 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2214 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2216 queue_writel(queue, RBQS, buffer_size);
2218 dmacfg |= GEM_BF(RXBS, buffer_size);
2220 if (bp->dma_burst_length)
2221 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2222 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2223 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2226 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2228 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2230 if (bp->dev->features & NETIF_F_HW_CSUM)
2231 dmacfg |= GEM_BIT(TXCOEN);
2233 dmacfg &= ~GEM_BIT(TXCOEN);
2235 dmacfg &= ~GEM_BIT(ADDR64);
2236 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2237 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2238 dmacfg |= GEM_BIT(ADDR64);
2240 #ifdef CONFIG_MACB_USE_HWSTAMP
2241 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2242 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2244 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2246 gem_writel(bp, DMACFG, dmacfg);
2250 static void macb_init_hw(struct macb *bp)
2252 struct macb_queue *queue;
2258 macb_set_hwaddr(bp);
2260 config = macb_mdc_clk_div(bp);
2261 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2262 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2263 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2264 config |= MACB_BIT(PAE); /* PAuse Enable */
2265 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2266 if (bp->caps & MACB_CAPS_JUMBO)
2267 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2269 config |= MACB_BIT(BIG); /* Receive oversized frames */
2270 if (bp->dev->flags & IFF_PROMISC)
2271 config |= MACB_BIT(CAF); /* Copy All Frames */
2272 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2273 config |= GEM_BIT(RXCOEN);
2274 if (!(bp->dev->flags & IFF_BROADCAST))
2275 config |= MACB_BIT(NBC); /* No BroadCast */
2276 config |= macb_dbw(bp);
2277 macb_writel(bp, NCFGR, config);
2278 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2279 gem_writel(bp, JML, bp->jumbo_max_len);
2280 bp->speed = SPEED_10;
2281 bp->duplex = DUPLEX_HALF;
2282 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2283 if (bp->caps & MACB_CAPS_JUMBO)
2284 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2286 macb_configure_dma(bp);
2288 /* Initialize TX and RX buffers */
2289 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2290 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
2291 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2292 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2293 queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma));
2295 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2296 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2297 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2298 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2301 /* Enable interrupts */
2302 queue_writel(queue, IER,
2308 /* Enable TX and RX */
2309 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
2312 /* The hash address register is 64 bits long and takes up two
2313 * locations in the memory map. The least significant bits are stored
2314 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2316 * The unicast hash enable and the multicast hash enable bits in the
2317 * network configuration register enable the reception of hash matched
2318 * frames. The destination address is reduced to a 6 bit index into
2319 * the 64 bit hash register using the following hash function. The
2320 * hash function is an exclusive or of every sixth bit of the
2321 * destination address.
2323 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2324 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2325 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2326 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2327 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2328 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2330 * da[0] represents the least significant bit of the first byte
2331 * received, that is, the multicast/unicast indicator, and da[47]
2332 * represents the most significant bit of the last byte received. If
2333 * the hash index, hi[n], points to a bit that is set in the hash
2334 * register then the frame will be matched according to whether the
2335 * frame is multicast or unicast. A multicast match will be signalled
2336 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2337 * index points to a bit set in the hash register. A unicast match
2338 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2339 * and the hash index points to a bit set in the hash register. To
2340 * receive all multicast frames, the hash register should be set with
2341 * all ones and the multicast hash enable bit should be set in the
2342 * network configuration register.
2345 static inline int hash_bit_value(int bitnr, __u8 *addr)
2347 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2352 /* Return the hash index value for the specified address. */
2353 static int hash_get_index(__u8 *addr)
2358 for (j = 0; j < 6; j++) {
2359 for (i = 0, bitval = 0; i < 8; i++)
2360 bitval ^= hash_bit_value(i * 6 + j, addr);
2362 hash_index |= (bitval << j);
2368 /* Add multicast addresses to the internal multicast-hash table. */
2369 static void macb_sethashtable(struct net_device *dev)
2371 struct netdev_hw_addr *ha;
2372 unsigned long mc_filter[2];
2374 struct macb *bp = netdev_priv(dev);
2379 netdev_for_each_mc_addr(ha, dev) {
2380 bitnr = hash_get_index(ha->addr);
2381 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2384 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2385 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2388 /* Enable/Disable promiscuous and multicast modes. */
2389 static void macb_set_rx_mode(struct net_device *dev)
2392 struct macb *bp = netdev_priv(dev);
2394 cfg = macb_readl(bp, NCFGR);
2396 if (dev->flags & IFF_PROMISC) {
2397 /* Enable promiscuous mode */
2398 cfg |= MACB_BIT(CAF);
2400 /* Disable RX checksum offload */
2401 if (macb_is_gem(bp))
2402 cfg &= ~GEM_BIT(RXCOEN);
2404 /* Disable promiscuous mode */
2405 cfg &= ~MACB_BIT(CAF);
2407 /* Enable RX checksum offload only if requested */
2408 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2409 cfg |= GEM_BIT(RXCOEN);
2412 if (dev->flags & IFF_ALLMULTI) {
2413 /* Enable all multicast mode */
2414 macb_or_gem_writel(bp, HRB, -1);
2415 macb_or_gem_writel(bp, HRT, -1);
2416 cfg |= MACB_BIT(NCFGR_MTI);
2417 } else if (!netdev_mc_empty(dev)) {
2418 /* Enable specific multicasts */
2419 macb_sethashtable(dev);
2420 cfg |= MACB_BIT(NCFGR_MTI);
2421 } else if (dev->flags & (~IFF_ALLMULTI)) {
2422 /* Disable all multicast mode */
2423 macb_or_gem_writel(bp, HRB, 0);
2424 macb_or_gem_writel(bp, HRT, 0);
2425 cfg &= ~MACB_BIT(NCFGR_MTI);
2428 macb_writel(bp, NCFGR, cfg);
2431 static int macb_open(struct net_device *dev)
2433 struct macb *bp = netdev_priv(dev);
2434 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2435 struct macb_queue *queue;
2439 netdev_dbg(bp->dev, "open\n");
2441 /* carrier starts down */
2442 netif_carrier_off(dev);
2444 /* if the phy is not yet register, retry later*/
2448 /* RX buffers initialization */
2449 macb_init_rx_buffer_size(bp, bufsz);
2451 err = macb_alloc_consistent(bp);
2453 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2458 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2459 napi_enable(&queue->napi);
2461 bp->macbgem_ops.mog_init_rings(bp);
2464 /* schedule a link state check */
2465 phy_start(dev->phydev);
2467 netif_tx_start_all_queues(dev);
2470 bp->ptp_info->ptp_init(dev);
2475 static int macb_close(struct net_device *dev)
2477 struct macb *bp = netdev_priv(dev);
2478 struct macb_queue *queue;
2479 unsigned long flags;
2482 netif_tx_stop_all_queues(dev);
2484 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2485 napi_disable(&queue->napi);
2488 phy_stop(dev->phydev);
2490 spin_lock_irqsave(&bp->lock, flags);
2492 netif_carrier_off(dev);
2493 spin_unlock_irqrestore(&bp->lock, flags);
2495 macb_free_consistent(bp);
2498 bp->ptp_info->ptp_remove(dev);
2503 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2505 if (netif_running(dev))
2513 static void gem_update_stats(struct macb *bp)
2515 struct macb_queue *queue;
2516 unsigned int i, q, idx;
2517 unsigned long *stat;
2519 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2521 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2522 u32 offset = gem_statistics[i].offset;
2523 u64 val = bp->macb_reg_readl(bp, offset);
2525 bp->ethtool_stats[i] += val;
2528 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2529 /* Add GEM_OCTTXH, GEM_OCTRXH */
2530 val = bp->macb_reg_readl(bp, offset + 4);
2531 bp->ethtool_stats[i] += ((u64)val) << 32;
2536 idx = GEM_STATS_LEN;
2537 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2538 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2539 bp->ethtool_stats[idx++] = *stat;
2542 static struct net_device_stats *gem_get_stats(struct macb *bp)
2544 struct gem_stats *hwstat = &bp->hw_stats.gem;
2545 struct net_device_stats *nstat = &bp->dev->stats;
2547 if (!netif_running(bp->dev))
2550 gem_update_stats(bp);
2552 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2553 hwstat->rx_alignment_errors +
2554 hwstat->rx_resource_errors +
2555 hwstat->rx_overruns +
2556 hwstat->rx_oversize_frames +
2557 hwstat->rx_jabbers +
2558 hwstat->rx_undersized_frames +
2559 hwstat->rx_length_field_frame_errors);
2560 nstat->tx_errors = (hwstat->tx_late_collisions +
2561 hwstat->tx_excessive_collisions +
2562 hwstat->tx_underrun +
2563 hwstat->tx_carrier_sense_errors);
2564 nstat->multicast = hwstat->rx_multicast_frames;
2565 nstat->collisions = (hwstat->tx_single_collision_frames +
2566 hwstat->tx_multiple_collision_frames +
2567 hwstat->tx_excessive_collisions);
2568 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2569 hwstat->rx_jabbers +
2570 hwstat->rx_undersized_frames +
2571 hwstat->rx_length_field_frame_errors);
2572 nstat->rx_over_errors = hwstat->rx_resource_errors;
2573 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2574 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2575 nstat->rx_fifo_errors = hwstat->rx_overruns;
2576 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2577 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2578 nstat->tx_fifo_errors = hwstat->tx_underrun;
2583 static void gem_get_ethtool_stats(struct net_device *dev,
2584 struct ethtool_stats *stats, u64 *data)
2588 bp = netdev_priv(dev);
2589 gem_update_stats(bp);
2590 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2591 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2594 static int gem_get_sset_count(struct net_device *dev, int sset)
2596 struct macb *bp = netdev_priv(dev);
2600 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2606 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2608 char stat_string[ETH_GSTRING_LEN];
2609 struct macb *bp = netdev_priv(dev);
2610 struct macb_queue *queue;
2616 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2617 memcpy(p, gem_statistics[i].stat_string,
2620 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2621 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2622 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2623 q, queue_statistics[i].stat_string);
2624 memcpy(p, stat_string, ETH_GSTRING_LEN);
2631 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2633 struct macb *bp = netdev_priv(dev);
2634 struct net_device_stats *nstat = &bp->dev->stats;
2635 struct macb_stats *hwstat = &bp->hw_stats.macb;
2637 if (macb_is_gem(bp))
2638 return gem_get_stats(bp);
2640 /* read stats from hardware */
2641 macb_update_stats(bp);
2643 /* Convert HW stats into netdevice stats */
2644 nstat->rx_errors = (hwstat->rx_fcs_errors +
2645 hwstat->rx_align_errors +
2646 hwstat->rx_resource_errors +
2647 hwstat->rx_overruns +
2648 hwstat->rx_oversize_pkts +
2649 hwstat->rx_jabbers +
2650 hwstat->rx_undersize_pkts +
2651 hwstat->rx_length_mismatch);
2652 nstat->tx_errors = (hwstat->tx_late_cols +
2653 hwstat->tx_excessive_cols +
2654 hwstat->tx_underruns +
2655 hwstat->tx_carrier_errors +
2656 hwstat->sqe_test_errors);
2657 nstat->collisions = (hwstat->tx_single_cols +
2658 hwstat->tx_multiple_cols +
2659 hwstat->tx_excessive_cols);
2660 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2661 hwstat->rx_jabbers +
2662 hwstat->rx_undersize_pkts +
2663 hwstat->rx_length_mismatch);
2664 nstat->rx_over_errors = hwstat->rx_resource_errors +
2665 hwstat->rx_overruns;
2666 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2667 nstat->rx_frame_errors = hwstat->rx_align_errors;
2668 nstat->rx_fifo_errors = hwstat->rx_overruns;
2669 /* XXX: What does "missed" mean? */
2670 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2671 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2672 nstat->tx_fifo_errors = hwstat->tx_underruns;
2673 /* Don't know about heartbeat or window errors... */
2678 static int macb_get_regs_len(struct net_device *netdev)
2680 return MACB_GREGS_NBR * sizeof(u32);
2683 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2686 struct macb *bp = netdev_priv(dev);
2687 unsigned int tail, head;
2690 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2691 | MACB_GREGS_VERSION;
2693 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2694 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2696 regs_buff[0] = macb_readl(bp, NCR);
2697 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2698 regs_buff[2] = macb_readl(bp, NSR);
2699 regs_buff[3] = macb_readl(bp, TSR);
2700 regs_buff[4] = macb_readl(bp, RBQP);
2701 regs_buff[5] = macb_readl(bp, TBQP);
2702 regs_buff[6] = macb_readl(bp, RSR);
2703 regs_buff[7] = macb_readl(bp, IMR);
2705 regs_buff[8] = tail;
2706 regs_buff[9] = head;
2707 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2708 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2710 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2711 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2712 if (macb_is_gem(bp))
2713 regs_buff[13] = gem_readl(bp, DMACFG);
2716 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2718 struct macb *bp = netdev_priv(netdev);
2723 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2724 wol->supported = WAKE_MAGIC;
2726 if (bp->wol & MACB_WOL_ENABLED)
2727 wol->wolopts |= WAKE_MAGIC;
2731 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2733 struct macb *bp = netdev_priv(netdev);
2735 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2736 (wol->wolopts & ~WAKE_MAGIC))
2739 if (wol->wolopts & WAKE_MAGIC)
2740 bp->wol |= MACB_WOL_ENABLED;
2742 bp->wol &= ~MACB_WOL_ENABLED;
2744 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2749 static void macb_get_ringparam(struct net_device *netdev,
2750 struct ethtool_ringparam *ring)
2752 struct macb *bp = netdev_priv(netdev);
2754 ring->rx_max_pending = MAX_RX_RING_SIZE;
2755 ring->tx_max_pending = MAX_TX_RING_SIZE;
2757 ring->rx_pending = bp->rx_ring_size;
2758 ring->tx_pending = bp->tx_ring_size;
2761 static int macb_set_ringparam(struct net_device *netdev,
2762 struct ethtool_ringparam *ring)
2764 struct macb *bp = netdev_priv(netdev);
2765 u32 new_rx_size, new_tx_size;
2766 unsigned int reset = 0;
2768 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2771 new_rx_size = clamp_t(u32, ring->rx_pending,
2772 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2773 new_rx_size = roundup_pow_of_two(new_rx_size);
2775 new_tx_size = clamp_t(u32, ring->tx_pending,
2776 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2777 new_tx_size = roundup_pow_of_two(new_tx_size);
2779 if ((new_tx_size == bp->tx_ring_size) &&
2780 (new_rx_size == bp->rx_ring_size)) {
2785 if (netif_running(bp->dev)) {
2787 macb_close(bp->dev);
2790 bp->rx_ring_size = new_rx_size;
2791 bp->tx_ring_size = new_tx_size;
2799 #ifdef CONFIG_MACB_USE_HWSTAMP
2800 static unsigned int gem_get_tsu_rate(struct macb *bp)
2802 struct clk *tsu_clk;
2803 unsigned int tsu_rate;
2805 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2806 if (!IS_ERR(tsu_clk))
2807 tsu_rate = clk_get_rate(tsu_clk);
2808 /* try pclk instead */
2809 else if (!IS_ERR(bp->pclk)) {
2811 tsu_rate = clk_get_rate(tsu_clk);
2817 static s32 gem_get_ptp_max_adj(void)
2822 static int gem_get_ts_info(struct net_device *dev,
2823 struct ethtool_ts_info *info)
2825 struct macb *bp = netdev_priv(dev);
2827 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2828 ethtool_op_get_ts_info(dev, info);
2832 info->so_timestamping =
2833 SOF_TIMESTAMPING_TX_SOFTWARE |
2834 SOF_TIMESTAMPING_RX_SOFTWARE |
2835 SOF_TIMESTAMPING_SOFTWARE |
2836 SOF_TIMESTAMPING_TX_HARDWARE |
2837 SOF_TIMESTAMPING_RX_HARDWARE |
2838 SOF_TIMESTAMPING_RAW_HARDWARE;
2840 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2841 (1 << HWTSTAMP_TX_OFF) |
2842 (1 << HWTSTAMP_TX_ON);
2844 (1 << HWTSTAMP_FILTER_NONE) |
2845 (1 << HWTSTAMP_FILTER_ALL);
2847 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2852 static struct macb_ptp_info gem_ptp_info = {
2853 .ptp_init = gem_ptp_init,
2854 .ptp_remove = gem_ptp_remove,
2855 .get_ptp_max_adj = gem_get_ptp_max_adj,
2856 .get_tsu_rate = gem_get_tsu_rate,
2857 .get_ts_info = gem_get_ts_info,
2858 .get_hwtst = gem_get_hwtst,
2859 .set_hwtst = gem_set_hwtst,
2863 static int macb_get_ts_info(struct net_device *netdev,
2864 struct ethtool_ts_info *info)
2866 struct macb *bp = netdev_priv(netdev);
2869 return bp->ptp_info->get_ts_info(netdev, info);
2871 return ethtool_op_get_ts_info(netdev, info);
2874 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2876 struct ethtool_rx_fs_item *item;
2880 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2882 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2883 struct ethtool_rx_flow_spec *fs = &item->fs;
2884 struct ethtool_tcpip4_spec *tp4sp_m;
2886 if (fs->location >= num_t2_scr)
2889 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2891 /* enable/disable screener regs for the flow entry */
2892 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2894 /* only enable fields with no masking */
2895 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2897 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2898 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2900 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2902 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2903 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2905 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2907 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2908 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2910 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2912 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2916 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2918 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2919 uint16_t index = fs->location;
2925 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2926 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2928 /* ignore field if any masking set */
2929 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2930 /* 1st compare reg - IP source address */
2933 w0 = tp4sp_v->ip4src;
2934 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2935 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2936 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2937 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2938 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2942 /* ignore field if any masking set */
2943 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2944 /* 2nd compare reg - IP destination address */
2947 w0 = tp4sp_v->ip4dst;
2948 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2949 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2950 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2951 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2952 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
2956 /* ignore both port fields if masking set in both */
2957 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
2958 /* 3rd compare reg - source port, destination port */
2961 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
2962 if (tp4sp_m->psrc == tp4sp_m->pdst) {
2963 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
2964 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2965 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2966 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2968 /* only one port definition */
2969 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
2970 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
2971 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
2972 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
2973 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2974 } else { /* dst port */
2975 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2976 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
2979 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
2980 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
2985 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
2986 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
2988 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
2990 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
2992 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
2993 gem_writel_n(bp, SCRT2, index, t2_scr);
2996 static int gem_add_flow_filter(struct net_device *netdev,
2997 struct ethtool_rxnfc *cmd)
2999 struct macb *bp = netdev_priv(netdev);
3000 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3001 struct ethtool_rx_fs_item *item, *newfs;
3002 unsigned long flags;
3006 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3009 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3012 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3013 fs->flow_type, (int)fs->ring_cookie, fs->location,
3014 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3015 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3016 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3018 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3020 /* find correct place to add in list */
3021 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3022 if (item->fs.location > newfs->fs.location) {
3023 list_add_tail(&newfs->list, &item->list);
3026 } else if (item->fs.location == fs->location) {
3027 netdev_err(netdev, "Rule not added: location %d not free!\n",
3034 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3036 gem_prog_cmp_regs(bp, fs);
3037 bp->rx_fs_list.count++;
3038 /* enable filtering if NTUPLE on */
3039 if (netdev->features & NETIF_F_NTUPLE)
3040 gem_enable_flow_filters(bp, 1);
3042 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3046 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3051 static int gem_del_flow_filter(struct net_device *netdev,
3052 struct ethtool_rxnfc *cmd)
3054 struct macb *bp = netdev_priv(netdev);
3055 struct ethtool_rx_fs_item *item;
3056 struct ethtool_rx_flow_spec *fs;
3057 unsigned long flags;
3059 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3061 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3062 if (item->fs.location == cmd->fs.location) {
3063 /* disable screener regs for the flow entry */
3066 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3067 fs->flow_type, (int)fs->ring_cookie, fs->location,
3068 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3069 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3070 htons(fs->h_u.tcp_ip4_spec.psrc),
3071 htons(fs->h_u.tcp_ip4_spec.pdst));
3073 gem_writel_n(bp, SCRT2, fs->location, 0);
3075 list_del(&item->list);
3076 bp->rx_fs_list.count--;
3077 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3083 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3087 static int gem_get_flow_entry(struct net_device *netdev,
3088 struct ethtool_rxnfc *cmd)
3090 struct macb *bp = netdev_priv(netdev);
3091 struct ethtool_rx_fs_item *item;
3093 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3094 if (item->fs.location == cmd->fs.location) {
3095 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3102 static int gem_get_all_flow_entries(struct net_device *netdev,
3103 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3105 struct macb *bp = netdev_priv(netdev);
3106 struct ethtool_rx_fs_item *item;
3109 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3110 if (cnt == cmd->rule_cnt)
3112 rule_locs[cnt] = item->fs.location;
3115 cmd->data = bp->max_tuples;
3116 cmd->rule_cnt = cnt;
3121 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3124 struct macb *bp = netdev_priv(netdev);
3128 case ETHTOOL_GRXRINGS:
3129 cmd->data = bp->num_queues;
3131 case ETHTOOL_GRXCLSRLCNT:
3132 cmd->rule_cnt = bp->rx_fs_list.count;
3134 case ETHTOOL_GRXCLSRULE:
3135 ret = gem_get_flow_entry(netdev, cmd);
3137 case ETHTOOL_GRXCLSRLALL:
3138 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3142 "Command parameter %d is not supported\n", cmd->cmd);
3149 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3151 struct macb *bp = netdev_priv(netdev);
3155 case ETHTOOL_SRXCLSRLINS:
3156 if ((cmd->fs.location >= bp->max_tuples)
3157 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3161 ret = gem_add_flow_filter(netdev, cmd);
3163 case ETHTOOL_SRXCLSRLDEL:
3164 ret = gem_del_flow_filter(netdev, cmd);
3168 "Command parameter %d is not supported\n", cmd->cmd);
3175 static const struct ethtool_ops macb_ethtool_ops = {
3176 .get_regs_len = macb_get_regs_len,
3177 .get_regs = macb_get_regs,
3178 .get_link = ethtool_op_get_link,
3179 .get_ts_info = ethtool_op_get_ts_info,
3180 .get_wol = macb_get_wol,
3181 .set_wol = macb_set_wol,
3182 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3183 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3184 .get_ringparam = macb_get_ringparam,
3185 .set_ringparam = macb_set_ringparam,
3188 static const struct ethtool_ops gem_ethtool_ops = {
3189 .get_regs_len = macb_get_regs_len,
3190 .get_regs = macb_get_regs,
3191 .get_link = ethtool_op_get_link,
3192 .get_ts_info = macb_get_ts_info,
3193 .get_ethtool_stats = gem_get_ethtool_stats,
3194 .get_strings = gem_get_ethtool_strings,
3195 .get_sset_count = gem_get_sset_count,
3196 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3197 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3198 .get_ringparam = macb_get_ringparam,
3199 .set_ringparam = macb_set_ringparam,
3200 .get_rxnfc = gem_get_rxnfc,
3201 .set_rxnfc = gem_set_rxnfc,
3204 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3206 struct phy_device *phydev = dev->phydev;
3207 struct macb *bp = netdev_priv(dev);
3209 if (!netif_running(dev))
3216 return phy_mii_ioctl(phydev, rq, cmd);
3220 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3222 return bp->ptp_info->get_hwtst(dev, rq);
3224 return phy_mii_ioctl(phydev, rq, cmd);
3228 static int macb_set_features(struct net_device *netdev,
3229 netdev_features_t features)
3231 struct macb *bp = netdev_priv(netdev);
3232 netdev_features_t changed = features ^ netdev->features;
3234 /* TX checksum offload */
3235 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
3238 dmacfg = gem_readl(bp, DMACFG);
3239 if (features & NETIF_F_HW_CSUM)
3240 dmacfg |= GEM_BIT(TXCOEN);
3242 dmacfg &= ~GEM_BIT(TXCOEN);
3243 gem_writel(bp, DMACFG, dmacfg);
3246 /* RX checksum offload */
3247 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
3250 netcfg = gem_readl(bp, NCFGR);
3251 if (features & NETIF_F_RXCSUM &&
3252 !(netdev->flags & IFF_PROMISC))
3253 netcfg |= GEM_BIT(RXCOEN);
3255 netcfg &= ~GEM_BIT(RXCOEN);
3256 gem_writel(bp, NCFGR, netcfg);
3259 /* RX Flow Filters */
3260 if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) {
3261 bool turn_on = features & NETIF_F_NTUPLE;
3263 gem_enable_flow_filters(bp, turn_on);
3268 static const struct net_device_ops macb_netdev_ops = {
3269 .ndo_open = macb_open,
3270 .ndo_stop = macb_close,
3271 .ndo_start_xmit = macb_start_xmit,
3272 .ndo_set_rx_mode = macb_set_rx_mode,
3273 .ndo_get_stats = macb_get_stats,
3274 .ndo_do_ioctl = macb_ioctl,
3275 .ndo_validate_addr = eth_validate_addr,
3276 .ndo_change_mtu = macb_change_mtu,
3277 .ndo_set_mac_address = eth_mac_addr,
3278 #ifdef CONFIG_NET_POLL_CONTROLLER
3279 .ndo_poll_controller = macb_poll_controller,
3281 .ndo_set_features = macb_set_features,
3282 .ndo_features_check = macb_features_check,
3285 /* Configure peripheral capabilities according to device tree
3286 * and integration options used
3288 static void macb_configure_caps(struct macb *bp,
3289 const struct macb_config *dt_conf)
3294 bp->caps = dt_conf->caps;
3296 if (hw_is_gem(bp->regs, bp->native_io)) {
3297 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3299 dcfg = gem_readl(bp, DCFG1);
3300 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3301 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3302 dcfg = gem_readl(bp, DCFG2);
3303 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3304 bp->caps |= MACB_CAPS_FIFO_MODE;
3305 #ifdef CONFIG_MACB_USE_HWSTAMP
3306 if (gem_has_ptp(bp)) {
3307 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3308 pr_err("GEM doesn't support hardware ptp.\n");
3310 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3311 bp->ptp_info = &gem_ptp_info;
3317 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3320 static void macb_probe_queues(void __iomem *mem,
3322 unsigned int *queue_mask,
3323 unsigned int *num_queues)
3330 /* is it macb or gem ?
3332 * We need to read directly from the hardware here because
3333 * we are early in the probe process and don't have the
3334 * MACB_CAPS_MACB_IS_GEM flag positioned
3336 if (!hw_is_gem(mem, native_io))
3339 /* bit 0 is never set but queue 0 always exists */
3340 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3344 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3345 if (*queue_mask & (1 << hw_q))
3349 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3350 struct clk **hclk, struct clk **tx_clk,
3351 struct clk **rx_clk)
3353 struct macb_platform_data *pdata;
3356 pdata = dev_get_platdata(&pdev->dev);
3358 *pclk = pdata->pclk;
3359 *hclk = pdata->hclk;
3361 *pclk = devm_clk_get(&pdev->dev, "pclk");
3362 *hclk = devm_clk_get(&pdev->dev, "hclk");
3365 if (IS_ERR_OR_NULL(*pclk)) {
3366 err = PTR_ERR(*pclk);
3370 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3374 if (IS_ERR_OR_NULL(*hclk)) {
3375 err = PTR_ERR(*hclk);
3379 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3383 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
3384 if (IS_ERR(*tx_clk))
3387 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
3388 if (IS_ERR(*rx_clk))
3391 err = clk_prepare_enable(*pclk);
3393 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3397 err = clk_prepare_enable(*hclk);
3399 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3400 goto err_disable_pclk;
3403 err = clk_prepare_enable(*tx_clk);
3405 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3406 goto err_disable_hclk;
3409 err = clk_prepare_enable(*rx_clk);
3411 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3412 goto err_disable_txclk;
3418 clk_disable_unprepare(*tx_clk);
3421 clk_disable_unprepare(*hclk);
3424 clk_disable_unprepare(*pclk);
3429 static int macb_init(struct platform_device *pdev)
3431 struct net_device *dev = platform_get_drvdata(pdev);
3432 unsigned int hw_q, q;
3433 struct macb *bp = netdev_priv(dev);
3434 struct macb_queue *queue;
3438 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3439 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3441 /* set the queue register mapping once for all: queue0 has a special
3442 * register mapping but we don't want to test the queue index then
3443 * compute the corresponding register offset at run time.
3445 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3446 if (!(bp->queue_mask & (1 << hw_q)))
3449 queue = &bp->queues[q];
3451 netif_napi_add(dev, &queue->napi, macb_poll, 64);
3453 queue->ISR = GEM_ISR(hw_q - 1);
3454 queue->IER = GEM_IER(hw_q - 1);
3455 queue->IDR = GEM_IDR(hw_q - 1);
3456 queue->IMR = GEM_IMR(hw_q - 1);
3457 queue->TBQP = GEM_TBQP(hw_q - 1);
3458 queue->RBQP = GEM_RBQP(hw_q - 1);
3459 queue->RBQS = GEM_RBQS(hw_q - 1);
3460 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3461 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3462 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3463 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3467 /* queue0 uses legacy registers */
3468 queue->ISR = MACB_ISR;
3469 queue->IER = MACB_IER;
3470 queue->IDR = MACB_IDR;
3471 queue->IMR = MACB_IMR;
3472 queue->TBQP = MACB_TBQP;
3473 queue->RBQP = MACB_RBQP;
3474 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3475 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3476 queue->TBQPH = MACB_TBQPH;
3477 queue->RBQPH = MACB_RBQPH;
3482 /* get irq: here we use the linux queue index, not the hardware
3483 * queue index. the queue irq definitions in the device tree
3484 * must remove the optional gaps that could exist in the
3485 * hardware queue mask.
3487 queue->irq = platform_get_irq(pdev, q);
3488 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3489 IRQF_SHARED, dev->name, queue);
3492 "Unable to request IRQ %d (error %d)\n",
3497 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3501 dev->netdev_ops = &macb_netdev_ops;
3503 /* setup appropriated routines according to adapter type */
3504 if (macb_is_gem(bp)) {
3505 bp->max_tx_length = GEM_MAX_TX_LEN;
3506 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3507 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3508 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3509 bp->macbgem_ops.mog_rx = gem_rx;
3510 dev->ethtool_ops = &gem_ethtool_ops;
3512 bp->max_tx_length = MACB_MAX_TX_LEN;
3513 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3514 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3515 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3516 bp->macbgem_ops.mog_rx = macb_rx;
3517 dev->ethtool_ops = &macb_ethtool_ops;
3521 dev->hw_features = NETIF_F_SG;
3523 /* Check LSO capability */
3524 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3525 dev->hw_features |= MACB_NETIF_LSO;
3527 /* Checksum offload is only available on gem with packet buffer */
3528 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3529 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3530 if (bp->caps & MACB_CAPS_SG_DISABLED)
3531 dev->hw_features &= ~NETIF_F_SG;
3532 dev->features = dev->hw_features;
3534 /* Check RX Flow Filters support.
3535 * Max Rx flows set by availability of screeners & compare regs:
3536 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3538 reg = gem_readl(bp, DCFG8);
3539 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3540 GEM_BFEXT(T2SCR, reg));
3541 if (bp->max_tuples > 0) {
3542 /* also needs one ethtype match to check IPv4 */
3543 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3544 /* program this reg now */
3546 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3547 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3548 /* Filtering is supported in hw but don't enable it in kernel now */
3549 dev->hw_features |= NETIF_F_NTUPLE;
3550 /* init Rx flow definitions */
3551 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3552 bp->rx_fs_list.count = 0;
3553 spin_lock_init(&bp->rx_fs_lock);
3558 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3560 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3561 val = GEM_BIT(RGMII);
3562 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3563 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3564 val = MACB_BIT(RMII);
3565 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3566 val = MACB_BIT(MII);
3568 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3569 val |= MACB_BIT(CLKEN);
3571 macb_or_gem_writel(bp, USRIO, val);
3574 /* Set MII management clock divider */
3575 val = macb_mdc_clk_div(bp);
3576 val |= macb_dbw(bp);
3577 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3578 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3579 macb_writel(bp, NCFGR, val);
3584 #if defined(CONFIG_OF)
3585 /* 1518 rounded up */
3586 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3587 /* max number of receive buffers */
3588 #define AT91ETHER_MAX_RX_DESCR 9
3590 /* Initialize and start the Receiver and Transmit subsystems */
3591 static int at91ether_start(struct net_device *dev)
3593 struct macb *lp = netdev_priv(dev);
3594 struct macb_queue *q = &lp->queues[0];
3595 struct macb_dma_desc *desc;
3600 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3601 (AT91ETHER_MAX_RX_DESCR *
3602 macb_dma_desc_get_size(lp)),
3603 &q->rx_ring_dma, GFP_KERNEL);
3607 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3608 AT91ETHER_MAX_RX_DESCR *
3609 AT91ETHER_MAX_RBUFF_SZ,
3610 &q->rx_buffers_dma, GFP_KERNEL);
3611 if (!q->rx_buffers) {
3612 dma_free_coherent(&lp->pdev->dev,
3613 AT91ETHER_MAX_RX_DESCR *
3614 macb_dma_desc_get_size(lp),
3615 q->rx_ring, q->rx_ring_dma);
3620 addr = q->rx_buffers_dma;
3621 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3622 desc = macb_rx_desc(q, i);
3623 macb_set_addr(lp, desc, addr);
3625 addr += AT91ETHER_MAX_RBUFF_SZ;
3628 /* Set the Wrap bit on the last descriptor */
3629 desc->addr |= MACB_BIT(RX_WRAP);
3631 /* Reset buffer index */
3634 /* Program address of descriptor list in Rx Buffer Queue register */
3635 macb_writel(lp, RBQP, q->rx_ring_dma);
3637 /* Enable Receive and Transmit */
3638 ctl = macb_readl(lp, NCR);
3639 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3644 /* Open the ethernet interface */
3645 static int at91ether_open(struct net_device *dev)
3647 struct macb *lp = netdev_priv(dev);
3651 /* Clear internal statistics */
3652 ctl = macb_readl(lp, NCR);
3653 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3655 macb_set_hwaddr(lp);
3657 ret = at91ether_start(dev);
3661 /* Enable MAC interrupts */
3662 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3664 MACB_BIT(ISR_TUND) |
3667 MACB_BIT(ISR_ROVR) |
3670 /* schedule a link state check */
3671 phy_start(dev->phydev);
3673 netif_start_queue(dev);
3678 /* Close the interface */
3679 static int at91ether_close(struct net_device *dev)
3681 struct macb *lp = netdev_priv(dev);
3682 struct macb_queue *q = &lp->queues[0];
3685 /* Disable Receiver and Transmitter */
3686 ctl = macb_readl(lp, NCR);
3687 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3689 /* Disable MAC interrupts */
3690 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3692 MACB_BIT(ISR_TUND) |
3695 MACB_BIT(ISR_ROVR) |
3698 netif_stop_queue(dev);
3700 dma_free_coherent(&lp->pdev->dev,
3701 AT91ETHER_MAX_RX_DESCR *
3702 macb_dma_desc_get_size(lp),
3703 q->rx_ring, q->rx_ring_dma);
3706 dma_free_coherent(&lp->pdev->dev,
3707 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3708 q->rx_buffers, q->rx_buffers_dma);
3709 q->rx_buffers = NULL;
3714 /* Transmit packet */
3715 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3716 struct net_device *dev)
3718 struct macb *lp = netdev_priv(dev);
3720 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3721 netif_stop_queue(dev);
3723 /* Store packet information (to free when Tx completed) */
3725 lp->skb_length = skb->len;
3726 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3728 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3729 dev_kfree_skb_any(skb);
3730 dev->stats.tx_dropped++;
3731 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3732 return NETDEV_TX_OK;
3735 /* Set address of the data in the Transmit Address register */
3736 macb_writel(lp, TAR, lp->skb_physaddr);
3737 /* Set length of the packet in the Transmit Control register */
3738 macb_writel(lp, TCR, skb->len);
3741 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3742 return NETDEV_TX_BUSY;
3745 return NETDEV_TX_OK;
3748 /* Extract received frame from buffer descriptors and sent to upper layers.
3749 * (Called from interrupt context)
3751 static void at91ether_rx(struct net_device *dev)
3753 struct macb *lp = netdev_priv(dev);
3754 struct macb_queue *q = &lp->queues[0];
3755 struct macb_dma_desc *desc;
3756 unsigned char *p_recv;
3757 struct sk_buff *skb;
3758 unsigned int pktlen;
3760 desc = macb_rx_desc(q, q->rx_tail);
3761 while (desc->addr & MACB_BIT(RX_USED)) {
3762 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3763 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3764 skb = netdev_alloc_skb(dev, pktlen + 2);
3766 skb_reserve(skb, 2);
3767 skb_put_data(skb, p_recv, pktlen);
3769 skb->protocol = eth_type_trans(skb, dev);
3770 dev->stats.rx_packets++;
3771 dev->stats.rx_bytes += pktlen;
3774 dev->stats.rx_dropped++;
3777 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3778 dev->stats.multicast++;
3780 /* reset ownership bit */
3781 desc->addr &= ~MACB_BIT(RX_USED);
3783 /* wrap after last buffer */
3784 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3789 desc = macb_rx_desc(q, q->rx_tail);
3793 /* MAC interrupt handler */
3794 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3796 struct net_device *dev = dev_id;
3797 struct macb *lp = netdev_priv(dev);
3800 /* MAC Interrupt Status register indicates what interrupts are pending.
3801 * It is automatically cleared once read.
3803 intstatus = macb_readl(lp, ISR);
3805 /* Receive complete */
3806 if (intstatus & MACB_BIT(RCOMP))
3809 /* Transmit complete */
3810 if (intstatus & MACB_BIT(TCOMP)) {
3811 /* The TCOM bit is set even if the transmission failed */
3812 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3813 dev->stats.tx_errors++;
3816 dev_kfree_skb_irq(lp->skb);
3818 dma_unmap_single(NULL, lp->skb_physaddr,
3819 lp->skb_length, DMA_TO_DEVICE);
3820 dev->stats.tx_packets++;
3821 dev->stats.tx_bytes += lp->skb_length;
3823 netif_wake_queue(dev);
3826 /* Work-around for EMAC Errata section 41.3.1 */
3827 if (intstatus & MACB_BIT(RXUBR)) {
3828 ctl = macb_readl(lp, NCR);
3829 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3831 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3834 if (intstatus & MACB_BIT(ISR_ROVR))
3835 netdev_err(dev, "ROVR error\n");
3840 #ifdef CONFIG_NET_POLL_CONTROLLER
3841 static void at91ether_poll_controller(struct net_device *dev)
3843 unsigned long flags;
3845 local_irq_save(flags);
3846 at91ether_interrupt(dev->irq, dev);
3847 local_irq_restore(flags);
3851 static const struct net_device_ops at91ether_netdev_ops = {
3852 .ndo_open = at91ether_open,
3853 .ndo_stop = at91ether_close,
3854 .ndo_start_xmit = at91ether_start_xmit,
3855 .ndo_get_stats = macb_get_stats,
3856 .ndo_set_rx_mode = macb_set_rx_mode,
3857 .ndo_set_mac_address = eth_mac_addr,
3858 .ndo_do_ioctl = macb_ioctl,
3859 .ndo_validate_addr = eth_validate_addr,
3860 #ifdef CONFIG_NET_POLL_CONTROLLER
3861 .ndo_poll_controller = at91ether_poll_controller,
3865 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3866 struct clk **hclk, struct clk **tx_clk,
3867 struct clk **rx_clk)
3875 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3877 return PTR_ERR(*pclk);
3879 err = clk_prepare_enable(*pclk);
3881 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3888 static int at91ether_init(struct platform_device *pdev)
3890 struct net_device *dev = platform_get_drvdata(pdev);
3891 struct macb *bp = netdev_priv(dev);
3895 bp->queues[0].bp = bp;
3897 dev->netdev_ops = &at91ether_netdev_ops;
3898 dev->ethtool_ops = &macb_ethtool_ops;
3900 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3905 macb_writel(bp, NCR, 0);
3907 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3908 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3909 reg |= MACB_BIT(RM9200_RMII);
3911 macb_writel(bp, NCFGR, reg);
3916 static const struct macb_config at91sam9260_config = {
3917 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3918 .clk_init = macb_clk_init,
3922 static const struct macb_config sama5d3macb_config = {
3923 .caps = MACB_CAPS_SG_DISABLED
3924 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3925 .clk_init = macb_clk_init,
3929 static const struct macb_config pc302gem_config = {
3930 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3931 .dma_burst_length = 16,
3932 .clk_init = macb_clk_init,
3936 static const struct macb_config sama5d2_config = {
3937 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3938 .dma_burst_length = 16,
3939 .clk_init = macb_clk_init,
3943 static const struct macb_config sama5d3_config = {
3944 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3945 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3946 .dma_burst_length = 16,
3947 .clk_init = macb_clk_init,
3949 .jumbo_max_len = 10240,
3952 static const struct macb_config sama5d4_config = {
3953 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3954 .dma_burst_length = 4,
3955 .clk_init = macb_clk_init,
3959 static const struct macb_config emac_config = {
3960 .caps = MACB_CAPS_NEEDS_RSTONUBR,
3961 .clk_init = at91ether_clk_init,
3962 .init = at91ether_init,
3965 static const struct macb_config np4_config = {
3966 .caps = MACB_CAPS_USRIO_DISABLED,
3967 .clk_init = macb_clk_init,
3971 static const struct macb_config zynqmp_config = {
3972 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3974 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
3975 .dma_burst_length = 16,
3976 .clk_init = macb_clk_init,
3978 .jumbo_max_len = 10240,
3981 static const struct macb_config zynq_config = {
3982 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
3983 MACB_CAPS_NEEDS_RSTONUBR,
3984 .dma_burst_length = 16,
3985 .clk_init = macb_clk_init,
3989 static const struct of_device_id macb_dt_ids[] = {
3990 { .compatible = "cdns,at32ap7000-macb" },
3991 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3992 { .compatible = "cdns,macb" },
3993 { .compatible = "cdns,np4-macb", .data = &np4_config },
3994 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3995 { .compatible = "cdns,gem", .data = &pc302gem_config },
3996 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3997 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3998 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
3999 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4000 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4001 { .compatible = "cdns,emac", .data = &emac_config },
4002 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4003 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4006 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4007 #endif /* CONFIG_OF */
4009 static const struct macb_config default_gem_config = {
4010 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4012 MACB_CAPS_GEM_HAS_PTP,
4013 .dma_burst_length = 16,
4014 .clk_init = macb_clk_init,
4016 .jumbo_max_len = 10240,
4019 static int macb_probe(struct platform_device *pdev)
4021 const struct macb_config *macb_config = &default_gem_config;
4022 int (*clk_init)(struct platform_device *, struct clk **,
4023 struct clk **, struct clk **, struct clk **)
4024 = macb_config->clk_init;
4025 int (*init)(struct platform_device *) = macb_config->init;
4026 struct device_node *np = pdev->dev.of_node;
4027 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4028 unsigned int queue_mask, num_queues;
4029 struct macb_platform_data *pdata;
4031 struct phy_device *phydev;
4032 struct net_device *dev;
4033 struct resource *regs;
4039 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4040 mem = devm_ioremap_resource(&pdev->dev, regs);
4042 return PTR_ERR(mem);
4045 const struct of_device_id *match;
4047 match = of_match_node(macb_dt_ids, np);
4048 if (match && match->data) {
4049 macb_config = match->data;
4050 clk_init = macb_config->clk_init;
4051 init = macb_config->init;
4055 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
4059 native_io = hw_is_native_io(mem);
4061 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4062 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4065 goto err_disable_clocks;
4068 dev->base_addr = regs->start;
4070 SET_NETDEV_DEV(dev, &pdev->dev);
4072 bp = netdev_priv(dev);
4076 bp->native_io = native_io;
4078 bp->macb_reg_readl = hw_readl_native;
4079 bp->macb_reg_writel = hw_writel_native;
4081 bp->macb_reg_readl = hw_readl;
4082 bp->macb_reg_writel = hw_writel;
4084 bp->num_queues = num_queues;
4085 bp->queue_mask = queue_mask;
4087 bp->dma_burst_length = macb_config->dma_burst_length;
4090 bp->tx_clk = tx_clk;
4091 bp->rx_clk = rx_clk;
4093 bp->jumbo_max_len = macb_config->jumbo_max_len;
4096 if (of_get_property(np, "magic-packet", NULL))
4097 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4098 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4100 spin_lock_init(&bp->lock);
4102 /* setup capabilities */
4103 macb_configure_caps(bp, macb_config);
4105 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4106 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4107 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4108 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4111 platform_set_drvdata(pdev, dev);
4113 dev->irq = platform_get_irq(pdev, 0);
4116 goto err_out_free_netdev;
4119 /* MTU range: 68 - 1500 or 10240 */
4120 dev->min_mtu = GEM_MTU_MIN_SIZE;
4121 if (bp->caps & MACB_CAPS_JUMBO)
4122 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4124 dev->max_mtu = ETH_DATA_LEN;
4126 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4127 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4129 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4130 macb_dma_desc_get_size(bp);
4132 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4134 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4135 macb_dma_desc_get_size(bp);
4138 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4139 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4140 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4142 mac = of_get_mac_address(np);
4144 ether_addr_copy(bp->dev->dev_addr, mac);
4146 err = of_get_nvmem_mac_address(np, bp->dev->dev_addr);
4148 if (err == -EPROBE_DEFER)
4149 goto err_out_free_netdev;
4150 macb_get_hwaddr(bp);
4154 err = of_get_phy_mode(np);
4156 pdata = dev_get_platdata(&pdev->dev);
4157 if (pdata && pdata->is_rmii)
4158 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
4160 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4162 bp->phy_interface = err;
4165 /* IP specific init */
4168 goto err_out_free_netdev;
4170 err = macb_mii_init(bp);
4172 goto err_out_free_netdev;
4174 phydev = dev->phydev;
4176 netif_carrier_off(dev);
4178 err = register_netdev(dev);
4180 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4181 goto err_out_unregister_mdio;
4184 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4187 phy_attached_info(phydev);
4189 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4190 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4191 dev->base_addr, dev->irq, dev->dev_addr);
4195 err_out_unregister_mdio:
4196 phy_disconnect(dev->phydev);
4197 mdiobus_unregister(bp->mii_bus);
4198 of_node_put(bp->phy_node);
4199 if (np && of_phy_is_fixed_link(np))
4200 of_phy_deregister_fixed_link(np);
4201 mdiobus_free(bp->mii_bus);
4203 err_out_free_netdev:
4207 clk_disable_unprepare(tx_clk);
4208 clk_disable_unprepare(hclk);
4209 clk_disable_unprepare(pclk);
4210 clk_disable_unprepare(rx_clk);
4215 static int macb_remove(struct platform_device *pdev)
4217 struct net_device *dev;
4219 struct device_node *np = pdev->dev.of_node;
4221 dev = platform_get_drvdata(pdev);
4224 bp = netdev_priv(dev);
4226 phy_disconnect(dev->phydev);
4227 mdiobus_unregister(bp->mii_bus);
4228 if (np && of_phy_is_fixed_link(np))
4229 of_phy_deregister_fixed_link(np);
4231 mdiobus_free(bp->mii_bus);
4233 unregister_netdev(dev);
4234 tasklet_kill(&bp->hresp_err_tasklet);
4235 clk_disable_unprepare(bp->tx_clk);
4236 clk_disable_unprepare(bp->hclk);
4237 clk_disable_unprepare(bp->pclk);
4238 clk_disable_unprepare(bp->rx_clk);
4239 of_node_put(bp->phy_node);
4246 static int __maybe_unused macb_suspend(struct device *dev)
4248 struct platform_device *pdev = to_platform_device(dev);
4249 struct net_device *netdev = platform_get_drvdata(pdev);
4250 struct macb *bp = netdev_priv(netdev);
4252 netif_carrier_off(netdev);
4253 netif_device_detach(netdev);
4255 if (bp->wol & MACB_WOL_ENABLED) {
4256 macb_writel(bp, IER, MACB_BIT(WOL));
4257 macb_writel(bp, WOL, MACB_BIT(MAG));
4258 enable_irq_wake(bp->queues[0].irq);
4260 clk_disable_unprepare(bp->tx_clk);
4261 clk_disable_unprepare(bp->hclk);
4262 clk_disable_unprepare(bp->pclk);
4263 clk_disable_unprepare(bp->rx_clk);
4269 static int __maybe_unused macb_resume(struct device *dev)
4271 struct platform_device *pdev = to_platform_device(dev);
4272 struct net_device *netdev = platform_get_drvdata(pdev);
4273 struct macb *bp = netdev_priv(netdev);
4275 if (bp->wol & MACB_WOL_ENABLED) {
4276 macb_writel(bp, IDR, MACB_BIT(WOL));
4277 macb_writel(bp, WOL, 0);
4278 disable_irq_wake(bp->queues[0].irq);
4280 clk_prepare_enable(bp->pclk);
4281 clk_prepare_enable(bp->hclk);
4282 clk_prepare_enable(bp->tx_clk);
4283 clk_prepare_enable(bp->rx_clk);
4286 netif_device_attach(netdev);
4291 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
4293 static struct platform_driver macb_driver = {
4294 .probe = macb_probe,
4295 .remove = macb_remove,
4298 .of_match_table = of_match_ptr(macb_dt_ids),
4303 module_platform_driver(macb_driver);
4305 MODULE_LICENSE("GPL");
4306 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4307 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4308 MODULE_ALIAS("platform:macb");