2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
38 #define MACB_RX_BUFFER_SIZE 128
39 #define RX_BUFFER_MULTIPLE 64 /* bytes */
40 #define RX_RING_SIZE 512 /* must be power of 2 */
41 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
43 #define TX_RING_SIZE 128 /* must be power of 2 */
44 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
46 /* level of occupied TX descriptors under which we wake up TX process */
47 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
49 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
51 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
54 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
59 #define GEM_MTU_MIN_SIZE 68
61 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
62 #define MACB_WOL_ENABLED (0x1 << 1)
64 /* Graceful stop timeouts in us. We should allow up to
65 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
67 #define MACB_HALT_TIMEOUT 1230
69 /* Ring buffer accessors */
70 static unsigned int macb_tx_ring_wrap(unsigned int index)
72 return index & (TX_RING_SIZE - 1);
75 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
78 return &queue->tx_ring[macb_tx_ring_wrap(index)];
81 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
84 return &queue->tx_skb[macb_tx_ring_wrap(index)];
87 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
91 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
93 return queue->tx_ring_dma + offset;
96 static unsigned int macb_rx_ring_wrap(unsigned int index)
98 return index & (RX_RING_SIZE - 1);
101 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
103 return &bp->rx_ring[macb_rx_ring_wrap(index)];
106 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
108 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
112 static u32 hw_readl_native(struct macb *bp, int offset)
114 return __raw_readl(bp->regs + offset);
117 static void hw_writel_native(struct macb *bp, int offset, u32 value)
119 __raw_writel(value, bp->regs + offset);
122 static u32 hw_readl(struct macb *bp, int offset)
124 return readl_relaxed(bp->regs + offset);
127 static void hw_writel(struct macb *bp, int offset, u32 value)
129 writel_relaxed(value, bp->regs + offset);
132 /* Find the CPU endianness by using the loopback bit of NCR register. When the
133 * CPU is in big endian we need to program swapped mode for management
136 static bool hw_is_native_io(void __iomem *addr)
138 u32 value = MACB_BIT(LLB);
140 __raw_writel(value, addr + MACB_NCR);
141 value = __raw_readl(addr + MACB_NCR);
143 /* Write 0 back to disable everything */
144 __raw_writel(0, addr + MACB_NCR);
146 return value == MACB_BIT(LLB);
149 static bool hw_is_gem(void __iomem *addr, bool native_io)
154 id = __raw_readl(addr + MACB_MID);
156 id = readl_relaxed(addr + MACB_MID);
158 return MACB_BFEXT(IDNUM, id) >= 0x2;
161 static void macb_set_hwaddr(struct macb *bp)
166 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
167 macb_or_gem_writel(bp, SA1B, bottom);
168 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
169 macb_or_gem_writel(bp, SA1T, top);
171 /* Clear unused address register sets */
172 macb_or_gem_writel(bp, SA2B, 0);
173 macb_or_gem_writel(bp, SA2T, 0);
174 macb_or_gem_writel(bp, SA3B, 0);
175 macb_or_gem_writel(bp, SA3T, 0);
176 macb_or_gem_writel(bp, SA4B, 0);
177 macb_or_gem_writel(bp, SA4T, 0);
180 static void macb_get_hwaddr(struct macb *bp)
182 struct macb_platform_data *pdata;
188 pdata = dev_get_platdata(&bp->pdev->dev);
190 /* Check all 4 address register for valid address */
191 for (i = 0; i < 4; i++) {
192 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
193 top = macb_or_gem_readl(bp, SA1T + i * 8);
195 if (pdata && pdata->rev_eth_addr) {
196 addr[5] = bottom & 0xff;
197 addr[4] = (bottom >> 8) & 0xff;
198 addr[3] = (bottom >> 16) & 0xff;
199 addr[2] = (bottom >> 24) & 0xff;
200 addr[1] = top & 0xff;
201 addr[0] = (top & 0xff00) >> 8;
203 addr[0] = bottom & 0xff;
204 addr[1] = (bottom >> 8) & 0xff;
205 addr[2] = (bottom >> 16) & 0xff;
206 addr[3] = (bottom >> 24) & 0xff;
207 addr[4] = top & 0xff;
208 addr[5] = (top >> 8) & 0xff;
211 if (is_valid_ether_addr(addr)) {
212 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
217 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
218 eth_hw_addr_random(bp->dev);
221 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
223 struct macb *bp = bus->priv;
226 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
227 | MACB_BF(RW, MACB_MAN_READ)
228 | MACB_BF(PHYA, mii_id)
229 | MACB_BF(REGA, regnum)
230 | MACB_BF(CODE, MACB_MAN_CODE)));
232 /* wait for end of transfer */
233 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
236 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
241 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
244 struct macb *bp = bus->priv;
246 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
247 | MACB_BF(RW, MACB_MAN_WRITE)
248 | MACB_BF(PHYA, mii_id)
249 | MACB_BF(REGA, regnum)
250 | MACB_BF(CODE, MACB_MAN_CODE)
251 | MACB_BF(DATA, value)));
253 /* wait for end of transfer */
254 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
261 * macb_set_tx_clk() - Set a clock to a new frequency
262 * @clk Pointer to the clock to change
263 * @rate New frequency in Hz
264 * @dev Pointer to the struct net_device
266 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
268 long ferr, rate, rate_rounded;
287 rate_rounded = clk_round_rate(clk, rate);
288 if (rate_rounded < 0)
291 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
294 ferr = abs(rate_rounded - rate);
295 ferr = DIV_ROUND_UP(ferr, rate / 100000);
297 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
300 if (clk_set_rate(clk, rate_rounded))
301 netdev_err(dev, "adjusting tx_clk failed.\n");
304 static void macb_handle_link_change(struct net_device *dev)
306 struct macb *bp = netdev_priv(dev);
307 struct phy_device *phydev = dev->phydev;
309 int status_change = 0;
311 spin_lock_irqsave(&bp->lock, flags);
314 if ((bp->speed != phydev->speed) ||
315 (bp->duplex != phydev->duplex)) {
318 reg = macb_readl(bp, NCFGR);
319 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
321 reg &= ~GEM_BIT(GBE);
325 if (phydev->speed == SPEED_100)
326 reg |= MACB_BIT(SPD);
327 if (phydev->speed == SPEED_1000 &&
328 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
331 macb_or_gem_writel(bp, NCFGR, reg);
333 bp->speed = phydev->speed;
334 bp->duplex = phydev->duplex;
339 if (phydev->link != bp->link) {
344 bp->link = phydev->link;
349 spin_unlock_irqrestore(&bp->lock, flags);
353 /* Update the TX clock rate if and only if the link is
354 * up and there has been a link change.
356 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
358 netif_carrier_on(dev);
359 netdev_info(dev, "link up (%d/%s)\n",
361 phydev->duplex == DUPLEX_FULL ?
364 netif_carrier_off(dev);
365 netdev_info(dev, "link down\n");
370 /* based on au1000_eth. c*/
371 static int macb_mii_probe(struct net_device *dev)
373 struct macb *bp = netdev_priv(dev);
374 struct macb_platform_data *pdata;
375 struct phy_device *phydev;
379 phydev = phy_find_first(bp->mii_bus);
381 netdev_err(dev, "no PHY found\n");
385 pdata = dev_get_platdata(&bp->pdev->dev);
386 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
387 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin,
390 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
391 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
395 /* attach the mac to the phy */
396 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
399 netdev_err(dev, "Could not attach to PHY\n");
403 /* mask with MAC supported features */
404 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
405 phydev->supported &= PHY_GBIT_FEATURES;
407 phydev->supported &= PHY_BASIC_FEATURES;
409 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
410 phydev->supported &= ~SUPPORTED_1000baseT_Half;
412 phydev->advertising = phydev->supported;
421 static int macb_mii_init(struct macb *bp)
423 struct macb_platform_data *pdata;
424 struct device_node *np;
427 /* Enable management port */
428 macb_writel(bp, NCR, MACB_BIT(MPE));
430 bp->mii_bus = mdiobus_alloc();
436 bp->mii_bus->name = "MACB_mii_bus";
437 bp->mii_bus->read = &macb_mdio_read;
438 bp->mii_bus->write = &macb_mdio_write;
439 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
440 bp->pdev->name, bp->pdev->id);
441 bp->mii_bus->priv = bp;
442 bp->mii_bus->parent = &bp->pdev->dev;
443 pdata = dev_get_platdata(&bp->pdev->dev);
445 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
447 np = bp->pdev->dev.of_node;
449 /* try dt phy registration */
450 err = of_mdiobus_register(bp->mii_bus, np);
452 /* fallback to standard phy registration if no phy were
453 * found during dt phy registration
455 if (!err && !phy_find_first(bp->mii_bus)) {
456 for (i = 0; i < PHY_MAX_ADDR; i++) {
457 struct phy_device *phydev;
459 phydev = mdiobus_scan(bp->mii_bus, i);
460 if (IS_ERR(phydev) &&
461 PTR_ERR(phydev) != -ENODEV) {
462 err = PTR_ERR(phydev);
468 goto err_out_unregister_bus;
472 bp->mii_bus->phy_mask = pdata->phy_mask;
474 err = mdiobus_register(bp->mii_bus);
478 goto err_out_free_mdiobus;
480 err = macb_mii_probe(bp->dev);
482 goto err_out_unregister_bus;
486 err_out_unregister_bus:
487 mdiobus_unregister(bp->mii_bus);
488 err_out_free_mdiobus:
489 mdiobus_free(bp->mii_bus);
494 static void macb_update_stats(struct macb *bp)
496 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
497 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
498 int offset = MACB_PFR;
500 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
502 for (; p < end; p++, offset += 4)
503 *p += bp->macb_reg_readl(bp, offset);
506 static int macb_halt_tx(struct macb *bp)
508 unsigned long halt_time, timeout;
511 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
513 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
516 status = macb_readl(bp, TSR);
517 if (!(status & MACB_BIT(TGO)))
521 } while (time_before(halt_time, timeout));
526 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
528 if (tx_skb->mapping) {
529 if (tx_skb->mapped_as_page)
530 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
531 tx_skb->size, DMA_TO_DEVICE);
533 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
534 tx_skb->size, DMA_TO_DEVICE);
539 dev_kfree_skb_any(tx_skb->skb);
544 static inline void macb_set_addr(struct macb_dma_desc *desc, dma_addr_t addr)
546 desc->addr = (u32)addr;
547 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
548 desc->addrh = (u32)(addr >> 32);
552 static void macb_tx_error_task(struct work_struct *work)
554 struct macb_queue *queue = container_of(work, struct macb_queue,
556 struct macb *bp = queue->bp;
557 struct macb_tx_skb *tx_skb;
558 struct macb_dma_desc *desc;
563 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
564 (unsigned int)(queue - bp->queues),
565 queue->tx_tail, queue->tx_head);
567 /* Prevent the queue IRQ handlers from running: each of them may call
568 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
569 * As explained below, we have to halt the transmission before updating
570 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
571 * network engine about the macb/gem being halted.
573 spin_lock_irqsave(&bp->lock, flags);
575 /* Make sure nobody is trying to queue up new packets */
576 netif_tx_stop_all_queues(bp->dev);
578 /* Stop transmission now
579 * (in case we have just queued new packets)
580 * macb/gem must be halted to write TBQP register
582 if (macb_halt_tx(bp))
583 /* Just complain for now, reinitializing TX path can be good */
584 netdev_err(bp->dev, "BUG: halt tx timed out\n");
586 /* Treat frames in TX queue including the ones that caused the error.
587 * Free transmit buffers in upper layer.
589 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
592 desc = macb_tx_desc(queue, tail);
594 tx_skb = macb_tx_skb(queue, tail);
597 if (ctrl & MACB_BIT(TX_USED)) {
598 /* skb is set for the last buffer of the frame */
600 macb_tx_unmap(bp, tx_skb);
602 tx_skb = macb_tx_skb(queue, tail);
606 /* ctrl still refers to the first buffer descriptor
607 * since it's the only one written back by the hardware
609 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
610 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
611 macb_tx_ring_wrap(tail), skb->data);
612 bp->stats.tx_packets++;
613 bp->stats.tx_bytes += skb->len;
616 /* "Buffers exhausted mid-frame" errors may only happen
617 * if the driver is buggy, so complain loudly about
618 * those. Statistics are updated by hardware.
620 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
622 "BUG: TX buffers exhausted mid-frame\n");
624 desc->ctrl = ctrl | MACB_BIT(TX_USED);
627 macb_tx_unmap(bp, tx_skb);
630 /* Set end of TX queue */
631 desc = macb_tx_desc(queue, 0);
632 macb_set_addr(desc, 0);
633 desc->ctrl = MACB_BIT(TX_USED);
635 /* Make descriptor updates visible to hardware */
638 /* Reinitialize the TX desc queue */
639 queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma));
640 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
641 queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32));
643 /* Make TX ring reflect state of hardware */
647 /* Housework before enabling TX IRQ */
648 macb_writel(bp, TSR, macb_readl(bp, TSR));
649 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
651 /* Now we are ready to start transmission again */
652 netif_tx_start_all_queues(bp->dev);
653 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
655 spin_unlock_irqrestore(&bp->lock, flags);
658 static void macb_tx_interrupt(struct macb_queue *queue)
663 struct macb *bp = queue->bp;
664 u16 queue_index = queue - bp->queues;
666 status = macb_readl(bp, TSR);
667 macb_writel(bp, TSR, status);
669 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
670 queue_writel(queue, ISR, MACB_BIT(TCOMP));
672 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
673 (unsigned long)status);
675 head = queue->tx_head;
676 for (tail = queue->tx_tail; tail != head; tail++) {
677 struct macb_tx_skb *tx_skb;
679 struct macb_dma_desc *desc;
682 desc = macb_tx_desc(queue, tail);
684 /* Make hw descriptor updates visible to CPU */
689 /* TX_USED bit is only set by hardware on the very first buffer
690 * descriptor of the transmitted frame.
692 if (!(ctrl & MACB_BIT(TX_USED)))
695 /* Process all buffers of the current transmitted frame */
697 tx_skb = macb_tx_skb(queue, tail);
700 /* First, update TX stats if needed */
702 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
703 macb_tx_ring_wrap(tail), skb->data);
704 bp->stats.tx_packets++;
705 bp->stats.tx_bytes += skb->len;
708 /* Now we can safely release resources */
709 macb_tx_unmap(bp, tx_skb);
711 /* skb is set only for the last buffer of the frame.
712 * WARNING: at this point skb has been freed by
720 queue->tx_tail = tail;
721 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
722 CIRC_CNT(queue->tx_head, queue->tx_tail,
723 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
724 netif_wake_subqueue(bp->dev, queue_index);
727 static void gem_rx_refill(struct macb *bp)
733 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
735 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
737 /* Make hw descriptor updates visible to CPU */
740 bp->rx_prepared_head++;
742 if (!bp->rx_skbuff[entry]) {
743 /* allocate sk_buff for this free entry in ring */
744 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
745 if (unlikely(!skb)) {
747 "Unable to allocate sk_buff\n");
751 /* now fill corresponding descriptor entry */
752 paddr = dma_map_single(&bp->pdev->dev, skb->data,
755 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
760 bp->rx_skbuff[entry] = skb;
762 if (entry == RX_RING_SIZE - 1)
763 paddr |= MACB_BIT(RX_WRAP);
764 macb_set_addr(&(bp->rx_ring[entry]), paddr);
765 bp->rx_ring[entry].ctrl = 0;
767 /* properly align Ethernet header */
768 skb_reserve(skb, NET_IP_ALIGN);
770 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
771 bp->rx_ring[entry].ctrl = 0;
775 /* Make descriptor updates visible to hardware */
778 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
779 bp->rx_prepared_head, bp->rx_tail);
782 /* Mark DMA descriptors from begin up to and not including end as unused */
783 static void discard_partial_frame(struct macb *bp, unsigned int begin,
788 for (frag = begin; frag != end; frag++) {
789 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
791 desc->addr &= ~MACB_BIT(RX_USED);
794 /* Make descriptor updates visible to hardware */
797 /* When this happens, the hardware stats registers for
798 * whatever caused this is updated, so we don't have to record
803 static int gem_rx(struct macb *bp, int budget)
808 struct macb_dma_desc *desc;
811 while (count < budget) {
816 entry = macb_rx_ring_wrap(bp->rx_tail);
817 desc = &bp->rx_ring[entry];
819 /* Make hw descriptor updates visible to CPU */
822 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
823 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
824 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
825 addr |= ((u64)(desc->addrh) << 32);
835 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
837 "not whole frame pointed by descriptor\n");
838 bp->stats.rx_dropped++;
841 skb = bp->rx_skbuff[entry];
842 if (unlikely(!skb)) {
844 "inconsistent Rx descriptor chain\n");
845 bp->stats.rx_dropped++;
848 /* now everything is ready for receiving packet */
849 bp->rx_skbuff[entry] = NULL;
850 len = ctrl & bp->rx_frm_len_mask;
852 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
855 dma_unmap_single(&bp->pdev->dev, addr,
856 bp->rx_buffer_size, DMA_FROM_DEVICE);
858 skb->protocol = eth_type_trans(skb, bp->dev);
859 skb_checksum_none_assert(skb);
860 if (bp->dev->features & NETIF_F_RXCSUM &&
861 !(bp->dev->flags & IFF_PROMISC) &&
862 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
863 skb->ip_summed = CHECKSUM_UNNECESSARY;
865 bp->stats.rx_packets++;
866 bp->stats.rx_bytes += skb->len;
868 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
869 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
870 skb->len, skb->csum);
871 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
872 skb_mac_header(skb), 16, true);
873 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
874 skb->data, 32, true);
877 netif_receive_skb(skb);
885 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
886 unsigned int last_frag)
892 struct macb_dma_desc *desc;
894 desc = macb_rx_desc(bp, last_frag);
895 len = desc->ctrl & bp->rx_frm_len_mask;
897 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
898 macb_rx_ring_wrap(first_frag),
899 macb_rx_ring_wrap(last_frag), len);
901 /* The ethernet header starts NET_IP_ALIGN bytes into the
902 * first buffer. Since the header is 14 bytes, this makes the
903 * payload word-aligned.
905 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
906 * the two padding bytes into the skb so that we avoid hitting
907 * the slowpath in memcpy(), and pull them off afterwards.
909 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
911 bp->stats.rx_dropped++;
912 for (frag = first_frag; ; frag++) {
913 desc = macb_rx_desc(bp, frag);
914 desc->addr &= ~MACB_BIT(RX_USED);
915 if (frag == last_frag)
919 /* Make descriptor updates visible to hardware */
927 skb_checksum_none_assert(skb);
930 for (frag = first_frag; ; frag++) {
931 unsigned int frag_len = bp->rx_buffer_size;
933 if (offset + frag_len > len) {
934 if (unlikely(frag != last_frag)) {
935 dev_kfree_skb_any(skb);
938 frag_len = len - offset;
940 skb_copy_to_linear_data_offset(skb, offset,
941 macb_rx_buffer(bp, frag),
943 offset += bp->rx_buffer_size;
944 desc = macb_rx_desc(bp, frag);
945 desc->addr &= ~MACB_BIT(RX_USED);
947 if (frag == last_frag)
951 /* Make descriptor updates visible to hardware */
954 __skb_pull(skb, NET_IP_ALIGN);
955 skb->protocol = eth_type_trans(skb, bp->dev);
957 bp->stats.rx_packets++;
958 bp->stats.rx_bytes += skb->len;
959 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
960 skb->len, skb->csum);
961 netif_receive_skb(skb);
966 static inline void macb_init_rx_ring(struct macb *bp)
971 addr = bp->rx_buffers_dma;
972 for (i = 0; i < RX_RING_SIZE; i++) {
973 bp->rx_ring[i].addr = addr;
974 bp->rx_ring[i].ctrl = 0;
975 addr += bp->rx_buffer_size;
977 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
981 static int macb_rx(struct macb *bp, int budget)
983 bool reset_rx_queue = false;
988 for (tail = bp->rx_tail; budget > 0; tail++) {
989 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
992 /* Make hw descriptor updates visible to CPU */
998 if (!(addr & MACB_BIT(RX_USED)))
1001 if (ctrl & MACB_BIT(RX_SOF)) {
1002 if (first_frag != -1)
1003 discard_partial_frame(bp, first_frag, tail);
1007 if (ctrl & MACB_BIT(RX_EOF)) {
1010 if (unlikely(first_frag == -1)) {
1011 reset_rx_queue = true;
1015 dropped = macb_rx_frame(bp, first_frag, tail);
1017 if (unlikely(dropped < 0)) {
1018 reset_rx_queue = true;
1028 if (unlikely(reset_rx_queue)) {
1029 unsigned long flags;
1032 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1034 spin_lock_irqsave(&bp->lock, flags);
1036 ctrl = macb_readl(bp, NCR);
1037 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1039 macb_init_rx_ring(bp);
1040 macb_writel(bp, RBQP, bp->rx_ring_dma);
1042 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1044 spin_unlock_irqrestore(&bp->lock, flags);
1048 if (first_frag != -1)
1049 bp->rx_tail = first_frag;
1056 static int macb_poll(struct napi_struct *napi, int budget)
1058 struct macb *bp = container_of(napi, struct macb, napi);
1062 status = macb_readl(bp, RSR);
1063 macb_writel(bp, RSR, status);
1067 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1068 (unsigned long)status, budget);
1070 work_done = bp->macbgem_ops.mog_rx(bp, budget);
1071 if (work_done < budget) {
1072 napi_complete(napi);
1074 /* Packets received while interrupts were disabled */
1075 status = macb_readl(bp, RSR);
1077 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1078 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1079 napi_reschedule(napi);
1081 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1085 /* TODO: Handle errors */
1090 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1092 struct macb_queue *queue = dev_id;
1093 struct macb *bp = queue->bp;
1094 struct net_device *dev = bp->dev;
1097 status = queue_readl(queue, ISR);
1099 if (unlikely(!status))
1102 spin_lock(&bp->lock);
1105 /* close possible race with dev_close */
1106 if (unlikely(!netif_running(dev))) {
1107 queue_writel(queue, IDR, -1);
1108 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1109 queue_writel(queue, ISR, -1);
1113 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1114 (unsigned int)(queue - bp->queues),
1115 (unsigned long)status);
1117 if (status & MACB_RX_INT_FLAGS) {
1118 /* There's no point taking any more interrupts
1119 * until we have processed the buffers. The
1120 * scheduling call may fail if the poll routine
1121 * is already scheduled, so disable interrupts
1124 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1125 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1126 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1128 if (napi_schedule_prep(&bp->napi)) {
1129 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1130 __napi_schedule(&bp->napi);
1134 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1135 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1136 schedule_work(&queue->tx_error_task);
1138 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1139 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1144 if (status & MACB_BIT(TCOMP))
1145 macb_tx_interrupt(queue);
1147 /* Link change detection isn't possible with RMII, so we'll
1148 * add that if/when we get our hands on a full-blown MII PHY.
1151 /* There is a hardware issue under heavy load where DMA can
1152 * stop, this causes endless "used buffer descriptor read"
1153 * interrupts but it can be cleared by re-enabling RX. See
1154 * the at91 manual, section 41.3.1 or the Zynq manual
1155 * section 16.7.4 for details.
1157 if (status & MACB_BIT(RXUBR)) {
1158 ctrl = macb_readl(bp, NCR);
1159 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1161 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1163 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1164 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1167 if (status & MACB_BIT(ISR_ROVR)) {
1168 /* We missed at least one packet */
1169 if (macb_is_gem(bp))
1170 bp->hw_stats.gem.rx_overruns++;
1172 bp->hw_stats.macb.rx_overruns++;
1174 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1175 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1178 if (status & MACB_BIT(HRESP)) {
1179 /* TODO: Reset the hardware, and maybe move the
1180 * netdev_err to a lower-priority context as well
1183 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1185 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1186 queue_writel(queue, ISR, MACB_BIT(HRESP));
1189 status = queue_readl(queue, ISR);
1192 spin_unlock(&bp->lock);
1197 #ifdef CONFIG_NET_POLL_CONTROLLER
1198 /* Polling receive - used by netconsole and other diagnostic tools
1199 * to allow network i/o with interrupts disabled.
1201 static void macb_poll_controller(struct net_device *dev)
1203 struct macb *bp = netdev_priv(dev);
1204 struct macb_queue *queue;
1205 unsigned long flags;
1208 local_irq_save(flags);
1209 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1210 macb_interrupt(dev->irq, queue);
1211 local_irq_restore(flags);
1215 static unsigned int macb_tx_map(struct macb *bp,
1216 struct macb_queue *queue,
1217 struct sk_buff *skb)
1220 unsigned int len, entry, i, tx_head = queue->tx_head;
1221 struct macb_tx_skb *tx_skb = NULL;
1222 struct macb_dma_desc *desc;
1223 unsigned int offset, size, count = 0;
1224 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1225 unsigned int eof = 1;
1228 /* First, map non-paged data */
1229 len = skb_headlen(skb);
1232 size = min(len, bp->max_tx_length);
1233 entry = macb_tx_ring_wrap(tx_head);
1234 tx_skb = &queue->tx_skb[entry];
1236 mapping = dma_map_single(&bp->pdev->dev,
1238 size, DMA_TO_DEVICE);
1239 if (dma_mapping_error(&bp->pdev->dev, mapping))
1242 /* Save info to properly release resources */
1244 tx_skb->mapping = mapping;
1245 tx_skb->size = size;
1246 tx_skb->mapped_as_page = false;
1254 /* Then, map paged data from fragments */
1255 for (f = 0; f < nr_frags; f++) {
1256 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1258 len = skb_frag_size(frag);
1261 size = min(len, bp->max_tx_length);
1262 entry = macb_tx_ring_wrap(tx_head);
1263 tx_skb = &queue->tx_skb[entry];
1265 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1266 offset, size, DMA_TO_DEVICE);
1267 if (dma_mapping_error(&bp->pdev->dev, mapping))
1270 /* Save info to properly release resources */
1272 tx_skb->mapping = mapping;
1273 tx_skb->size = size;
1274 tx_skb->mapped_as_page = true;
1283 /* Should never happen */
1284 if (unlikely(!tx_skb)) {
1285 netdev_err(bp->dev, "BUG! empty skb!\n");
1289 /* This is the last buffer of the frame: save socket buffer */
1292 /* Update TX ring: update buffer descriptors in reverse order
1293 * to avoid race condition
1296 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1297 * to set the end of TX queue
1300 entry = macb_tx_ring_wrap(i);
1301 ctrl = MACB_BIT(TX_USED);
1302 desc = &queue->tx_ring[entry];
1307 entry = macb_tx_ring_wrap(i);
1308 tx_skb = &queue->tx_skb[entry];
1309 desc = &queue->tx_ring[entry];
1311 ctrl = (u32)tx_skb->size;
1313 ctrl |= MACB_BIT(TX_LAST);
1316 if (unlikely(entry == (TX_RING_SIZE - 1)))
1317 ctrl |= MACB_BIT(TX_WRAP);
1319 /* Set TX buffer descriptor */
1320 macb_set_addr(desc, tx_skb->mapping);
1321 /* desc->addr must be visible to hardware before clearing
1322 * 'TX_USED' bit in desc->ctrl.
1326 } while (i != queue->tx_head);
1328 queue->tx_head = tx_head;
1333 netdev_err(bp->dev, "TX DMA map failed\n");
1335 for (i = queue->tx_head; i != tx_head; i++) {
1336 tx_skb = macb_tx_skb(queue, i);
1338 macb_tx_unmap(bp, tx_skb);
1344 static inline int macb_clear_csum(struct sk_buff *skb)
1346 /* no change for packets without checksum offloading */
1347 if (skb->ip_summed != CHECKSUM_PARTIAL)
1350 /* make sure we can modify the header */
1351 if (unlikely(skb_cow_head(skb, 0)))
1354 /* initialize checksum field
1355 * This is required - at least for Zynq, which otherwise calculates
1356 * wrong UDP header checksums for UDP packets with UDP data len <=2
1358 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1362 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1364 u16 queue_index = skb_get_queue_mapping(skb);
1365 struct macb *bp = netdev_priv(dev);
1366 struct macb_queue *queue = &bp->queues[queue_index];
1367 unsigned long flags;
1368 unsigned int count, nr_frags, frag_size, f;
1370 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1371 netdev_vdbg(bp->dev,
1372 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1373 queue_index, skb->len, skb->head, skb->data,
1374 skb_tail_pointer(skb), skb_end_pointer(skb));
1375 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1376 skb->data, 16, true);
1379 /* Count how many TX buffer descriptors are needed to send this
1380 * socket buffer: skb fragments of jumbo frames may need to be
1381 * split into many buffer descriptors.
1383 count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1384 nr_frags = skb_shinfo(skb)->nr_frags;
1385 for (f = 0; f < nr_frags; f++) {
1386 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1387 count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1390 spin_lock_irqsave(&bp->lock, flags);
1392 /* This is a hard error, log it. */
1393 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1394 netif_stop_subqueue(dev, queue_index);
1395 spin_unlock_irqrestore(&bp->lock, flags);
1396 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1397 queue->tx_head, queue->tx_tail);
1398 return NETDEV_TX_BUSY;
1401 if (macb_clear_csum(skb)) {
1402 dev_kfree_skb_any(skb);
1406 /* Map socket buffer for DMA transfer */
1407 if (!macb_tx_map(bp, queue, skb)) {
1408 dev_kfree_skb_any(skb);
1412 /* Make newly initialized descriptor visible to hardware */
1415 skb_tx_timestamp(skb);
1417 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1419 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1420 netif_stop_subqueue(dev, queue_index);
1423 spin_unlock_irqrestore(&bp->lock, flags);
1425 return NETDEV_TX_OK;
1428 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1430 if (!macb_is_gem(bp)) {
1431 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1433 bp->rx_buffer_size = size;
1435 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1437 "RX buffer must be multiple of %d bytes, expanding\n",
1438 RX_BUFFER_MULTIPLE);
1439 bp->rx_buffer_size =
1440 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1444 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1445 bp->dev->mtu, bp->rx_buffer_size);
1448 static void gem_free_rx_buffers(struct macb *bp)
1450 struct sk_buff *skb;
1451 struct macb_dma_desc *desc;
1458 for (i = 0; i < RX_RING_SIZE; i++) {
1459 skb = bp->rx_skbuff[i];
1464 desc = &bp->rx_ring[i];
1465 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1466 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1467 addr |= ((u64)(desc->addrh) << 32);
1469 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1471 dev_kfree_skb_any(skb);
1475 kfree(bp->rx_skbuff);
1476 bp->rx_skbuff = NULL;
1479 static void macb_free_rx_buffers(struct macb *bp)
1481 if (bp->rx_buffers) {
1482 dma_free_coherent(&bp->pdev->dev,
1483 RX_RING_SIZE * bp->rx_buffer_size,
1484 bp->rx_buffers, bp->rx_buffers_dma);
1485 bp->rx_buffers = NULL;
1489 static void macb_free_consistent(struct macb *bp)
1491 struct macb_queue *queue;
1494 bp->macbgem_ops.mog_free_rx_buffers(bp);
1496 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1497 bp->rx_ring, bp->rx_ring_dma);
1501 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1502 kfree(queue->tx_skb);
1503 queue->tx_skb = NULL;
1504 if (queue->tx_ring) {
1505 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1506 queue->tx_ring, queue->tx_ring_dma);
1507 queue->tx_ring = NULL;
1512 static int gem_alloc_rx_buffers(struct macb *bp)
1516 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1517 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1522 "Allocated %d RX struct sk_buff entries at %p\n",
1523 RX_RING_SIZE, bp->rx_skbuff);
1527 static int macb_alloc_rx_buffers(struct macb *bp)
1531 size = RX_RING_SIZE * bp->rx_buffer_size;
1532 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1533 &bp->rx_buffers_dma, GFP_KERNEL);
1534 if (!bp->rx_buffers)
1538 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1539 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1543 static int macb_alloc_consistent(struct macb *bp)
1545 struct macb_queue *queue;
1549 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1550 size = TX_RING_BYTES;
1551 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1552 &queue->tx_ring_dma,
1554 if (!queue->tx_ring)
1557 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1558 q, size, (unsigned long)queue->tx_ring_dma,
1561 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1562 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1567 size = RX_RING_BYTES;
1568 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1569 &bp->rx_ring_dma, GFP_KERNEL);
1573 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1574 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1576 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1582 macb_free_consistent(bp);
1586 static void gem_init_rings(struct macb *bp)
1588 struct macb_queue *queue;
1592 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1593 for (i = 0; i < TX_RING_SIZE; i++) {
1594 macb_set_addr(&(queue->tx_ring[i]), 0);
1595 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1597 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1603 bp->rx_prepared_head = 0;
1608 static void macb_init_rings(struct macb *bp)
1612 macb_init_rx_ring(bp);
1614 for (i = 0; i < TX_RING_SIZE; i++) {
1615 bp->queues[0].tx_ring[i].addr = 0;
1616 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1618 bp->queues[0].tx_head = 0;
1619 bp->queues[0].tx_tail = 0;
1620 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1623 static void macb_reset_hw(struct macb *bp)
1625 struct macb_queue *queue;
1628 /* Disable RX and TX (XXX: Should we halt the transmission
1631 macb_writel(bp, NCR, 0);
1633 /* Clear the stats registers (XXX: Update stats first?) */
1634 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1636 /* Clear all status flags */
1637 macb_writel(bp, TSR, -1);
1638 macb_writel(bp, RSR, -1);
1640 /* Disable all interrupts */
1641 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1642 queue_writel(queue, IDR, -1);
1643 queue_readl(queue, ISR);
1644 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1645 queue_writel(queue, ISR, -1);
1649 static u32 gem_mdc_clk_div(struct macb *bp)
1652 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1654 if (pclk_hz <= 20000000)
1655 config = GEM_BF(CLK, GEM_CLK_DIV8);
1656 else if (pclk_hz <= 40000000)
1657 config = GEM_BF(CLK, GEM_CLK_DIV16);
1658 else if (pclk_hz <= 80000000)
1659 config = GEM_BF(CLK, GEM_CLK_DIV32);
1660 else if (pclk_hz <= 120000000)
1661 config = GEM_BF(CLK, GEM_CLK_DIV48);
1662 else if (pclk_hz <= 160000000)
1663 config = GEM_BF(CLK, GEM_CLK_DIV64);
1665 config = GEM_BF(CLK, GEM_CLK_DIV96);
1670 static u32 macb_mdc_clk_div(struct macb *bp)
1673 unsigned long pclk_hz;
1675 if (macb_is_gem(bp))
1676 return gem_mdc_clk_div(bp);
1678 pclk_hz = clk_get_rate(bp->pclk);
1679 if (pclk_hz <= 20000000)
1680 config = MACB_BF(CLK, MACB_CLK_DIV8);
1681 else if (pclk_hz <= 40000000)
1682 config = MACB_BF(CLK, MACB_CLK_DIV16);
1683 else if (pclk_hz <= 80000000)
1684 config = MACB_BF(CLK, MACB_CLK_DIV32);
1686 config = MACB_BF(CLK, MACB_CLK_DIV64);
1691 /* Get the DMA bus width field of the network configuration register that we
1692 * should program. We find the width from decoding the design configuration
1693 * register to find the maximum supported data bus width.
1695 static u32 macb_dbw(struct macb *bp)
1697 if (!macb_is_gem(bp))
1700 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1702 return GEM_BF(DBW, GEM_DBW128);
1704 return GEM_BF(DBW, GEM_DBW64);
1707 return GEM_BF(DBW, GEM_DBW32);
1711 /* Configure the receive DMA engine
1712 * - use the correct receive buffer size
1713 * - set best burst length for DMA operations
1714 * (if not supported by FIFO, it will fallback to default)
1715 * - set both rx/tx packet buffers to full memory size
1716 * These are configurable parameters for GEM.
1718 static void macb_configure_dma(struct macb *bp)
1722 if (macb_is_gem(bp)) {
1723 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1724 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1725 if (bp->dma_burst_length)
1726 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1727 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1728 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1731 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1733 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1735 if (bp->dev->features & NETIF_F_HW_CSUM)
1736 dmacfg |= GEM_BIT(TXCOEN);
1738 dmacfg &= ~GEM_BIT(TXCOEN);
1740 dmacfg &= ~GEM_BIT(ADDR64);
1741 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1742 dmacfg |= GEM_BIT(ADDR64);
1744 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1746 gem_writel(bp, DMACFG, dmacfg);
1750 static void macb_init_hw(struct macb *bp)
1752 struct macb_queue *queue;
1758 macb_set_hwaddr(bp);
1760 config = macb_mdc_clk_div(bp);
1761 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
1762 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
1763 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1764 config |= MACB_BIT(PAE); /* PAuse Enable */
1765 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1766 if (bp->caps & MACB_CAPS_JUMBO)
1767 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1769 config |= MACB_BIT(BIG); /* Receive oversized frames */
1770 if (bp->dev->flags & IFF_PROMISC)
1771 config |= MACB_BIT(CAF); /* Copy All Frames */
1772 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1773 config |= GEM_BIT(RXCOEN);
1774 if (!(bp->dev->flags & IFF_BROADCAST))
1775 config |= MACB_BIT(NBC); /* No BroadCast */
1776 config |= macb_dbw(bp);
1777 macb_writel(bp, NCFGR, config);
1778 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1779 gem_writel(bp, JML, bp->jumbo_max_len);
1780 bp->speed = SPEED_10;
1781 bp->duplex = DUPLEX_HALF;
1782 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1783 if (bp->caps & MACB_CAPS_JUMBO)
1784 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1786 macb_configure_dma(bp);
1788 /* Initialize TX and RX buffers */
1789 macb_writel(bp, RBQP, (u32)(bp->rx_ring_dma));
1790 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1791 macb_writel(bp, RBQPH, (u32)(bp->rx_ring_dma >> 32));
1793 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1794 queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma));
1795 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1796 queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32));
1799 /* Enable interrupts */
1800 queue_writel(queue, IER,
1806 /* Enable TX and RX */
1807 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1810 /* The hash address register is 64 bits long and takes up two
1811 * locations in the memory map. The least significant bits are stored
1812 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1814 * The unicast hash enable and the multicast hash enable bits in the
1815 * network configuration register enable the reception of hash matched
1816 * frames. The destination address is reduced to a 6 bit index into
1817 * the 64 bit hash register using the following hash function. The
1818 * hash function is an exclusive or of every sixth bit of the
1819 * destination address.
1821 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1822 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1823 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1824 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1825 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1826 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1828 * da[0] represents the least significant bit of the first byte
1829 * received, that is, the multicast/unicast indicator, and da[47]
1830 * represents the most significant bit of the last byte received. If
1831 * the hash index, hi[n], points to a bit that is set in the hash
1832 * register then the frame will be matched according to whether the
1833 * frame is multicast or unicast. A multicast match will be signalled
1834 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1835 * index points to a bit set in the hash register. A unicast match
1836 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1837 * and the hash index points to a bit set in the hash register. To
1838 * receive all multicast frames, the hash register should be set with
1839 * all ones and the multicast hash enable bit should be set in the
1840 * network configuration register.
1843 static inline int hash_bit_value(int bitnr, __u8 *addr)
1845 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1850 /* Return the hash index value for the specified address. */
1851 static int hash_get_index(__u8 *addr)
1856 for (j = 0; j < 6; j++) {
1857 for (i = 0, bitval = 0; i < 8; i++)
1858 bitval ^= hash_bit_value(i * 6 + j, addr);
1860 hash_index |= (bitval << j);
1866 /* Add multicast addresses to the internal multicast-hash table. */
1867 static void macb_sethashtable(struct net_device *dev)
1869 struct netdev_hw_addr *ha;
1870 unsigned long mc_filter[2];
1872 struct macb *bp = netdev_priv(dev);
1877 netdev_for_each_mc_addr(ha, dev) {
1878 bitnr = hash_get_index(ha->addr);
1879 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1882 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1883 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1886 /* Enable/Disable promiscuous and multicast modes. */
1887 static void macb_set_rx_mode(struct net_device *dev)
1890 struct macb *bp = netdev_priv(dev);
1892 cfg = macb_readl(bp, NCFGR);
1894 if (dev->flags & IFF_PROMISC) {
1895 /* Enable promiscuous mode */
1896 cfg |= MACB_BIT(CAF);
1898 /* Disable RX checksum offload */
1899 if (macb_is_gem(bp))
1900 cfg &= ~GEM_BIT(RXCOEN);
1902 /* Disable promiscuous mode */
1903 cfg &= ~MACB_BIT(CAF);
1905 /* Enable RX checksum offload only if requested */
1906 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1907 cfg |= GEM_BIT(RXCOEN);
1910 if (dev->flags & IFF_ALLMULTI) {
1911 /* Enable all multicast mode */
1912 macb_or_gem_writel(bp, HRB, -1);
1913 macb_or_gem_writel(bp, HRT, -1);
1914 cfg |= MACB_BIT(NCFGR_MTI);
1915 } else if (!netdev_mc_empty(dev)) {
1916 /* Enable specific multicasts */
1917 macb_sethashtable(dev);
1918 cfg |= MACB_BIT(NCFGR_MTI);
1919 } else if (dev->flags & (~IFF_ALLMULTI)) {
1920 /* Disable all multicast mode */
1921 macb_or_gem_writel(bp, HRB, 0);
1922 macb_or_gem_writel(bp, HRT, 0);
1923 cfg &= ~MACB_BIT(NCFGR_MTI);
1926 macb_writel(bp, NCFGR, cfg);
1929 static int macb_open(struct net_device *dev)
1931 struct macb *bp = netdev_priv(dev);
1932 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1935 netdev_dbg(bp->dev, "open\n");
1937 /* carrier starts down */
1938 netif_carrier_off(dev);
1940 /* if the phy is not yet register, retry later*/
1944 /* RX buffers initialization */
1945 macb_init_rx_buffer_size(bp, bufsz);
1947 err = macb_alloc_consistent(bp);
1949 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1954 napi_enable(&bp->napi);
1956 bp->macbgem_ops.mog_init_rings(bp);
1959 /* schedule a link state check */
1960 phy_start(dev->phydev);
1962 netif_tx_start_all_queues(dev);
1967 static int macb_close(struct net_device *dev)
1969 struct macb *bp = netdev_priv(dev);
1970 unsigned long flags;
1972 netif_tx_stop_all_queues(dev);
1973 napi_disable(&bp->napi);
1976 phy_stop(dev->phydev);
1978 spin_lock_irqsave(&bp->lock, flags);
1980 netif_carrier_off(dev);
1981 spin_unlock_irqrestore(&bp->lock, flags);
1983 macb_free_consistent(bp);
1988 static int macb_change_mtu(struct net_device *dev, int new_mtu)
1990 struct macb *bp = netdev_priv(dev);
1993 if (netif_running(dev))
1996 max_mtu = ETH_DATA_LEN;
1997 if (bp->caps & MACB_CAPS_JUMBO)
1998 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
2000 if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
2008 static void gem_update_stats(struct macb *bp)
2011 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2013 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2014 u32 offset = gem_statistics[i].offset;
2015 u64 val = bp->macb_reg_readl(bp, offset);
2017 bp->ethtool_stats[i] += val;
2020 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2021 /* Add GEM_OCTTXH, GEM_OCTRXH */
2022 val = bp->macb_reg_readl(bp, offset + 4);
2023 bp->ethtool_stats[i] += ((u64)val) << 32;
2029 static struct net_device_stats *gem_get_stats(struct macb *bp)
2031 struct gem_stats *hwstat = &bp->hw_stats.gem;
2032 struct net_device_stats *nstat = &bp->stats;
2034 if (!netif_running(bp->dev))
2037 gem_update_stats(bp);
2039 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2040 hwstat->rx_alignment_errors +
2041 hwstat->rx_resource_errors +
2042 hwstat->rx_overruns +
2043 hwstat->rx_oversize_frames +
2044 hwstat->rx_jabbers +
2045 hwstat->rx_undersized_frames +
2046 hwstat->rx_length_field_frame_errors);
2047 nstat->tx_errors = (hwstat->tx_late_collisions +
2048 hwstat->tx_excessive_collisions +
2049 hwstat->tx_underrun +
2050 hwstat->tx_carrier_sense_errors);
2051 nstat->multicast = hwstat->rx_multicast_frames;
2052 nstat->collisions = (hwstat->tx_single_collision_frames +
2053 hwstat->tx_multiple_collision_frames +
2054 hwstat->tx_excessive_collisions);
2055 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2056 hwstat->rx_jabbers +
2057 hwstat->rx_undersized_frames +
2058 hwstat->rx_length_field_frame_errors);
2059 nstat->rx_over_errors = hwstat->rx_resource_errors;
2060 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2061 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2062 nstat->rx_fifo_errors = hwstat->rx_overruns;
2063 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2064 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2065 nstat->tx_fifo_errors = hwstat->tx_underrun;
2070 static void gem_get_ethtool_stats(struct net_device *dev,
2071 struct ethtool_stats *stats, u64 *data)
2075 bp = netdev_priv(dev);
2076 gem_update_stats(bp);
2077 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
2080 static int gem_get_sset_count(struct net_device *dev, int sset)
2084 return GEM_STATS_LEN;
2090 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2096 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2097 memcpy(p, gem_statistics[i].stat_string,
2103 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2105 struct macb *bp = netdev_priv(dev);
2106 struct net_device_stats *nstat = &bp->stats;
2107 struct macb_stats *hwstat = &bp->hw_stats.macb;
2109 if (macb_is_gem(bp))
2110 return gem_get_stats(bp);
2112 /* read stats from hardware */
2113 macb_update_stats(bp);
2115 /* Convert HW stats into netdevice stats */
2116 nstat->rx_errors = (hwstat->rx_fcs_errors +
2117 hwstat->rx_align_errors +
2118 hwstat->rx_resource_errors +
2119 hwstat->rx_overruns +
2120 hwstat->rx_oversize_pkts +
2121 hwstat->rx_jabbers +
2122 hwstat->rx_undersize_pkts +
2123 hwstat->rx_length_mismatch);
2124 nstat->tx_errors = (hwstat->tx_late_cols +
2125 hwstat->tx_excessive_cols +
2126 hwstat->tx_underruns +
2127 hwstat->tx_carrier_errors +
2128 hwstat->sqe_test_errors);
2129 nstat->collisions = (hwstat->tx_single_cols +
2130 hwstat->tx_multiple_cols +
2131 hwstat->tx_excessive_cols);
2132 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2133 hwstat->rx_jabbers +
2134 hwstat->rx_undersize_pkts +
2135 hwstat->rx_length_mismatch);
2136 nstat->rx_over_errors = hwstat->rx_resource_errors +
2137 hwstat->rx_overruns;
2138 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2139 nstat->rx_frame_errors = hwstat->rx_align_errors;
2140 nstat->rx_fifo_errors = hwstat->rx_overruns;
2141 /* XXX: What does "missed" mean? */
2142 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2143 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2144 nstat->tx_fifo_errors = hwstat->tx_underruns;
2145 /* Don't know about heartbeat or window errors... */
2150 static int macb_get_regs_len(struct net_device *netdev)
2152 return MACB_GREGS_NBR * sizeof(u32);
2155 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2158 struct macb *bp = netdev_priv(dev);
2159 unsigned int tail, head;
2162 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2163 | MACB_GREGS_VERSION;
2165 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2166 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2168 regs_buff[0] = macb_readl(bp, NCR);
2169 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2170 regs_buff[2] = macb_readl(bp, NSR);
2171 regs_buff[3] = macb_readl(bp, TSR);
2172 regs_buff[4] = macb_readl(bp, RBQP);
2173 regs_buff[5] = macb_readl(bp, TBQP);
2174 regs_buff[6] = macb_readl(bp, RSR);
2175 regs_buff[7] = macb_readl(bp, IMR);
2177 regs_buff[8] = tail;
2178 regs_buff[9] = head;
2179 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2180 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2182 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2183 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2184 if (macb_is_gem(bp))
2185 regs_buff[13] = gem_readl(bp, DMACFG);
2188 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2190 struct macb *bp = netdev_priv(netdev);
2195 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2196 wol->supported = WAKE_MAGIC;
2198 if (bp->wol & MACB_WOL_ENABLED)
2199 wol->wolopts |= WAKE_MAGIC;
2203 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2205 struct macb *bp = netdev_priv(netdev);
2207 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2208 (wol->wolopts & ~WAKE_MAGIC))
2211 if (wol->wolopts & WAKE_MAGIC)
2212 bp->wol |= MACB_WOL_ENABLED;
2214 bp->wol &= ~MACB_WOL_ENABLED;
2216 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2221 static const struct ethtool_ops macb_ethtool_ops = {
2222 .get_regs_len = macb_get_regs_len,
2223 .get_regs = macb_get_regs,
2224 .get_link = ethtool_op_get_link,
2225 .get_ts_info = ethtool_op_get_ts_info,
2226 .get_wol = macb_get_wol,
2227 .set_wol = macb_set_wol,
2228 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2229 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2232 static const struct ethtool_ops gem_ethtool_ops = {
2233 .get_regs_len = macb_get_regs_len,
2234 .get_regs = macb_get_regs,
2235 .get_link = ethtool_op_get_link,
2236 .get_ts_info = ethtool_op_get_ts_info,
2237 .get_ethtool_stats = gem_get_ethtool_stats,
2238 .get_strings = gem_get_ethtool_strings,
2239 .get_sset_count = gem_get_sset_count,
2240 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2241 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2244 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2246 struct phy_device *phydev = dev->phydev;
2248 if (!netif_running(dev))
2254 return phy_mii_ioctl(phydev, rq, cmd);
2257 static int macb_set_features(struct net_device *netdev,
2258 netdev_features_t features)
2260 struct macb *bp = netdev_priv(netdev);
2261 netdev_features_t changed = features ^ netdev->features;
2263 /* TX checksum offload */
2264 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2267 dmacfg = gem_readl(bp, DMACFG);
2268 if (features & NETIF_F_HW_CSUM)
2269 dmacfg |= GEM_BIT(TXCOEN);
2271 dmacfg &= ~GEM_BIT(TXCOEN);
2272 gem_writel(bp, DMACFG, dmacfg);
2275 /* RX checksum offload */
2276 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2279 netcfg = gem_readl(bp, NCFGR);
2280 if (features & NETIF_F_RXCSUM &&
2281 !(netdev->flags & IFF_PROMISC))
2282 netcfg |= GEM_BIT(RXCOEN);
2284 netcfg &= ~GEM_BIT(RXCOEN);
2285 gem_writel(bp, NCFGR, netcfg);
2291 static const struct net_device_ops macb_netdev_ops = {
2292 .ndo_open = macb_open,
2293 .ndo_stop = macb_close,
2294 .ndo_start_xmit = macb_start_xmit,
2295 .ndo_set_rx_mode = macb_set_rx_mode,
2296 .ndo_get_stats = macb_get_stats,
2297 .ndo_do_ioctl = macb_ioctl,
2298 .ndo_validate_addr = eth_validate_addr,
2299 .ndo_change_mtu = macb_change_mtu,
2300 .ndo_set_mac_address = eth_mac_addr,
2301 #ifdef CONFIG_NET_POLL_CONTROLLER
2302 .ndo_poll_controller = macb_poll_controller,
2304 .ndo_set_features = macb_set_features,
2307 /* Configure peripheral capabilities according to device tree
2308 * and integration options used
2310 static void macb_configure_caps(struct macb *bp,
2311 const struct macb_config *dt_conf)
2316 bp->caps = dt_conf->caps;
2318 if (hw_is_gem(bp->regs, bp->native_io)) {
2319 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2321 dcfg = gem_readl(bp, DCFG1);
2322 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2323 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2324 dcfg = gem_readl(bp, DCFG2);
2325 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2326 bp->caps |= MACB_CAPS_FIFO_MODE;
2329 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2332 static void macb_probe_queues(void __iomem *mem,
2334 unsigned int *queue_mask,
2335 unsigned int *num_queues)
2342 /* is it macb or gem ?
2344 * We need to read directly from the hardware here because
2345 * we are early in the probe process and don't have the
2346 * MACB_CAPS_MACB_IS_GEM flag positioned
2348 if (!hw_is_gem(mem, native_io))
2351 /* bit 0 is never set but queue 0 always exists */
2352 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2356 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2357 if (*queue_mask & (1 << hw_q))
2361 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2362 struct clk **hclk, struct clk **tx_clk,
2363 struct clk **rx_clk)
2367 *pclk = devm_clk_get(&pdev->dev, "pclk");
2368 if (IS_ERR(*pclk)) {
2369 err = PTR_ERR(*pclk);
2370 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
2374 *hclk = devm_clk_get(&pdev->dev, "hclk");
2375 if (IS_ERR(*hclk)) {
2376 err = PTR_ERR(*hclk);
2377 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
2381 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2382 if (IS_ERR(*tx_clk))
2385 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
2386 if (IS_ERR(*rx_clk))
2389 err = clk_prepare_enable(*pclk);
2391 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
2395 err = clk_prepare_enable(*hclk);
2397 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
2398 goto err_disable_pclk;
2401 err = clk_prepare_enable(*tx_clk);
2403 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2404 goto err_disable_hclk;
2407 err = clk_prepare_enable(*rx_clk);
2409 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2410 goto err_disable_txclk;
2416 clk_disable_unprepare(*tx_clk);
2419 clk_disable_unprepare(*hclk);
2422 clk_disable_unprepare(*pclk);
2427 static int macb_init(struct platform_device *pdev)
2429 struct net_device *dev = platform_get_drvdata(pdev);
2430 unsigned int hw_q, q;
2431 struct macb *bp = netdev_priv(dev);
2432 struct macb_queue *queue;
2436 /* set the queue register mapping once for all: queue0 has a special
2437 * register mapping but we don't want to test the queue index then
2438 * compute the corresponding register offset at run time.
2440 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2441 if (!(bp->queue_mask & (1 << hw_q)))
2444 queue = &bp->queues[q];
2447 queue->ISR = GEM_ISR(hw_q - 1);
2448 queue->IER = GEM_IER(hw_q - 1);
2449 queue->IDR = GEM_IDR(hw_q - 1);
2450 queue->IMR = GEM_IMR(hw_q - 1);
2451 queue->TBQP = GEM_TBQP(hw_q - 1);
2452 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2453 queue->TBQPH = GEM_TBQPH(hw_q -1);
2456 /* queue0 uses legacy registers */
2457 queue->ISR = MACB_ISR;
2458 queue->IER = MACB_IER;
2459 queue->IDR = MACB_IDR;
2460 queue->IMR = MACB_IMR;
2461 queue->TBQP = MACB_TBQP;
2462 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2463 queue->TBQPH = MACB_TBQPH;
2467 /* get irq: here we use the linux queue index, not the hardware
2468 * queue index. the queue irq definitions in the device tree
2469 * must remove the optional gaps that could exist in the
2470 * hardware queue mask.
2472 queue->irq = platform_get_irq(pdev, q);
2473 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2474 IRQF_SHARED, dev->name, queue);
2477 "Unable to request IRQ %d (error %d)\n",
2482 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2486 dev->netdev_ops = &macb_netdev_ops;
2487 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2489 /* setup appropriated routines according to adapter type */
2490 if (macb_is_gem(bp)) {
2491 bp->max_tx_length = GEM_MAX_TX_LEN;
2492 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2493 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2494 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2495 bp->macbgem_ops.mog_rx = gem_rx;
2496 dev->ethtool_ops = &gem_ethtool_ops;
2498 bp->max_tx_length = MACB_MAX_TX_LEN;
2499 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2500 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2501 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2502 bp->macbgem_ops.mog_rx = macb_rx;
2503 dev->ethtool_ops = &macb_ethtool_ops;
2507 dev->hw_features = NETIF_F_SG;
2508 /* Checksum offload is only available on gem with packet buffer */
2509 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2510 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2511 if (bp->caps & MACB_CAPS_SG_DISABLED)
2512 dev->hw_features &= ~NETIF_F_SG;
2513 dev->features = dev->hw_features;
2515 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2517 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2518 val = GEM_BIT(RGMII);
2519 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2520 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2521 val = MACB_BIT(RMII);
2522 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2523 val = MACB_BIT(MII);
2525 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2526 val |= MACB_BIT(CLKEN);
2528 macb_or_gem_writel(bp, USRIO, val);
2531 /* Set MII management clock divider */
2532 val = macb_mdc_clk_div(bp);
2533 val |= macb_dbw(bp);
2534 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2535 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2536 macb_writel(bp, NCFGR, val);
2541 #if defined(CONFIG_OF)
2542 /* 1518 rounded up */
2543 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2544 /* max number of receive buffers */
2545 #define AT91ETHER_MAX_RX_DESCR 9
2547 /* Initialize and start the Receiver and Transmit subsystems */
2548 static int at91ether_start(struct net_device *dev)
2550 struct macb *lp = netdev_priv(dev);
2555 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2556 (AT91ETHER_MAX_RX_DESCR *
2557 sizeof(struct macb_dma_desc)),
2558 &lp->rx_ring_dma, GFP_KERNEL);
2562 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2563 AT91ETHER_MAX_RX_DESCR *
2564 AT91ETHER_MAX_RBUFF_SZ,
2565 &lp->rx_buffers_dma, GFP_KERNEL);
2566 if (!lp->rx_buffers) {
2567 dma_free_coherent(&lp->pdev->dev,
2568 AT91ETHER_MAX_RX_DESCR *
2569 sizeof(struct macb_dma_desc),
2570 lp->rx_ring, lp->rx_ring_dma);
2575 addr = lp->rx_buffers_dma;
2576 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2577 lp->rx_ring[i].addr = addr;
2578 lp->rx_ring[i].ctrl = 0;
2579 addr += AT91ETHER_MAX_RBUFF_SZ;
2582 /* Set the Wrap bit on the last descriptor */
2583 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2585 /* Reset buffer index */
2588 /* Program address of descriptor list in Rx Buffer Queue register */
2589 macb_writel(lp, RBQP, lp->rx_ring_dma);
2591 /* Enable Receive and Transmit */
2592 ctl = macb_readl(lp, NCR);
2593 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2598 /* Open the ethernet interface */
2599 static int at91ether_open(struct net_device *dev)
2601 struct macb *lp = netdev_priv(dev);
2605 /* Clear internal statistics */
2606 ctl = macb_readl(lp, NCR);
2607 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2609 macb_set_hwaddr(lp);
2611 ret = at91ether_start(dev);
2615 /* Enable MAC interrupts */
2616 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2618 MACB_BIT(ISR_TUND) |
2621 MACB_BIT(ISR_ROVR) |
2624 /* schedule a link state check */
2625 phy_start(dev->phydev);
2627 netif_start_queue(dev);
2632 /* Close the interface */
2633 static int at91ether_close(struct net_device *dev)
2635 struct macb *lp = netdev_priv(dev);
2638 /* Disable Receiver and Transmitter */
2639 ctl = macb_readl(lp, NCR);
2640 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2642 /* Disable MAC interrupts */
2643 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2645 MACB_BIT(ISR_TUND) |
2648 MACB_BIT(ISR_ROVR) |
2651 netif_stop_queue(dev);
2653 dma_free_coherent(&lp->pdev->dev,
2654 AT91ETHER_MAX_RX_DESCR *
2655 sizeof(struct macb_dma_desc),
2656 lp->rx_ring, lp->rx_ring_dma);
2659 dma_free_coherent(&lp->pdev->dev,
2660 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2661 lp->rx_buffers, lp->rx_buffers_dma);
2662 lp->rx_buffers = NULL;
2667 /* Transmit packet */
2668 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2670 struct macb *lp = netdev_priv(dev);
2672 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2673 netif_stop_queue(dev);
2675 /* Store packet information (to free when Tx completed) */
2677 lp->skb_length = skb->len;
2678 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2680 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
2681 dev_kfree_skb_any(skb);
2682 dev->stats.tx_dropped++;
2683 netdev_err(dev, "%s: DMA mapping error\n", __func__);
2684 return NETDEV_TX_OK;
2687 /* Set address of the data in the Transmit Address register */
2688 macb_writel(lp, TAR, lp->skb_physaddr);
2689 /* Set length of the packet in the Transmit Control register */
2690 macb_writel(lp, TCR, skb->len);
2693 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2694 return NETDEV_TX_BUSY;
2697 return NETDEV_TX_OK;
2700 /* Extract received frame from buffer descriptors and sent to upper layers.
2701 * (Called from interrupt context)
2703 static void at91ether_rx(struct net_device *dev)
2705 struct macb *lp = netdev_priv(dev);
2706 unsigned char *p_recv;
2707 struct sk_buff *skb;
2708 unsigned int pktlen;
2710 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2711 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2712 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2713 skb = netdev_alloc_skb(dev, pktlen + 2);
2715 skb_reserve(skb, 2);
2716 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2718 skb->protocol = eth_type_trans(skb, dev);
2719 lp->stats.rx_packets++;
2720 lp->stats.rx_bytes += pktlen;
2723 lp->stats.rx_dropped++;
2726 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2727 lp->stats.multicast++;
2729 /* reset ownership bit */
2730 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2732 /* wrap after last buffer */
2733 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2740 /* MAC interrupt handler */
2741 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2743 struct net_device *dev = dev_id;
2744 struct macb *lp = netdev_priv(dev);
2747 /* MAC Interrupt Status register indicates what interrupts are pending.
2748 * It is automatically cleared once read.
2750 intstatus = macb_readl(lp, ISR);
2752 /* Receive complete */
2753 if (intstatus & MACB_BIT(RCOMP))
2756 /* Transmit complete */
2757 if (intstatus & MACB_BIT(TCOMP)) {
2758 /* The TCOM bit is set even if the transmission failed */
2759 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2760 lp->stats.tx_errors++;
2763 dev_kfree_skb_irq(lp->skb);
2765 dma_unmap_single(NULL, lp->skb_physaddr,
2766 lp->skb_length, DMA_TO_DEVICE);
2767 lp->stats.tx_packets++;
2768 lp->stats.tx_bytes += lp->skb_length;
2770 netif_wake_queue(dev);
2773 /* Work-around for EMAC Errata section 41.3.1 */
2774 if (intstatus & MACB_BIT(RXUBR)) {
2775 ctl = macb_readl(lp, NCR);
2776 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2778 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2781 if (intstatus & MACB_BIT(ISR_ROVR))
2782 netdev_err(dev, "ROVR error\n");
2787 #ifdef CONFIG_NET_POLL_CONTROLLER
2788 static void at91ether_poll_controller(struct net_device *dev)
2790 unsigned long flags;
2792 local_irq_save(flags);
2793 at91ether_interrupt(dev->irq, dev);
2794 local_irq_restore(flags);
2798 static const struct net_device_ops at91ether_netdev_ops = {
2799 .ndo_open = at91ether_open,
2800 .ndo_stop = at91ether_close,
2801 .ndo_start_xmit = at91ether_start_xmit,
2802 .ndo_get_stats = macb_get_stats,
2803 .ndo_set_rx_mode = macb_set_rx_mode,
2804 .ndo_set_mac_address = eth_mac_addr,
2805 .ndo_do_ioctl = macb_ioctl,
2806 .ndo_validate_addr = eth_validate_addr,
2807 .ndo_change_mtu = eth_change_mtu,
2808 #ifdef CONFIG_NET_POLL_CONTROLLER
2809 .ndo_poll_controller = at91ether_poll_controller,
2813 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2814 struct clk **hclk, struct clk **tx_clk,
2815 struct clk **rx_clk)
2823 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2825 return PTR_ERR(*pclk);
2827 err = clk_prepare_enable(*pclk);
2829 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
2836 static int at91ether_init(struct platform_device *pdev)
2838 struct net_device *dev = platform_get_drvdata(pdev);
2839 struct macb *bp = netdev_priv(dev);
2843 dev->netdev_ops = &at91ether_netdev_ops;
2844 dev->ethtool_ops = &macb_ethtool_ops;
2846 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2851 macb_writel(bp, NCR, 0);
2853 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2854 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2855 reg |= MACB_BIT(RM9200_RMII);
2857 macb_writel(bp, NCFGR, reg);
2862 static const struct macb_config at91sam9260_config = {
2863 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2864 .clk_init = macb_clk_init,
2868 static const struct macb_config sama5d3macb_config = {
2869 .caps = MACB_CAPS_SG_DISABLED
2870 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2871 .clk_init = macb_clk_init,
2875 static const struct macb_config pc302gem_config = {
2876 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2877 .dma_burst_length = 16,
2878 .clk_init = macb_clk_init,
2882 static const struct macb_config sama5d2_config = {
2883 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2884 .dma_burst_length = 16,
2885 .clk_init = macb_clk_init,
2889 static const struct macb_config sama5d3_config = {
2890 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
2891 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2892 .dma_burst_length = 16,
2893 .clk_init = macb_clk_init,
2897 static const struct macb_config sama5d4_config = {
2898 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2899 .dma_burst_length = 4,
2900 .clk_init = macb_clk_init,
2904 static const struct macb_config emac_config = {
2905 .clk_init = at91ether_clk_init,
2906 .init = at91ether_init,
2909 static const struct macb_config np4_config = {
2910 .caps = MACB_CAPS_USRIO_DISABLED,
2911 .clk_init = macb_clk_init,
2915 static const struct macb_config zynqmp_config = {
2916 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
2917 .dma_burst_length = 16,
2918 .clk_init = macb_clk_init,
2920 .jumbo_max_len = 10240,
2923 static const struct macb_config zynq_config = {
2924 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
2925 .dma_burst_length = 16,
2926 .clk_init = macb_clk_init,
2930 static const struct of_device_id macb_dt_ids[] = {
2931 { .compatible = "cdns,at32ap7000-macb" },
2932 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2933 { .compatible = "cdns,macb" },
2934 { .compatible = "cdns,np4-macb", .data = &np4_config },
2935 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2936 { .compatible = "cdns,gem", .data = &pc302gem_config },
2937 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
2938 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2939 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
2940 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2941 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2942 { .compatible = "cdns,emac", .data = &emac_config },
2943 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2944 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
2947 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2948 #endif /* CONFIG_OF */
2950 static int macb_probe(struct platform_device *pdev)
2952 int (*clk_init)(struct platform_device *, struct clk **,
2953 struct clk **, struct clk **, struct clk **)
2955 int (*init)(struct platform_device *) = macb_init;
2956 struct device_node *np = pdev->dev.of_node;
2957 struct device_node *phy_node;
2958 const struct macb_config *macb_config = NULL;
2959 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
2960 unsigned int queue_mask, num_queues;
2961 struct macb_platform_data *pdata;
2963 struct phy_device *phydev;
2964 struct net_device *dev;
2965 struct resource *regs;
2971 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2972 mem = devm_ioremap_resource(&pdev->dev, regs);
2974 return PTR_ERR(mem);
2977 const struct of_device_id *match;
2979 match = of_match_node(macb_dt_ids, np);
2980 if (match && match->data) {
2981 macb_config = match->data;
2982 clk_init = macb_config->clk_init;
2983 init = macb_config->init;
2987 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
2991 native_io = hw_is_native_io(mem);
2993 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
2994 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2997 goto err_disable_clocks;
3000 dev->base_addr = regs->start;
3002 SET_NETDEV_DEV(dev, &pdev->dev);
3004 bp = netdev_priv(dev);
3008 bp->native_io = native_io;
3010 bp->macb_reg_readl = hw_readl_native;
3011 bp->macb_reg_writel = hw_writel_native;
3013 bp->macb_reg_readl = hw_readl;
3014 bp->macb_reg_writel = hw_writel;
3016 bp->num_queues = num_queues;
3017 bp->queue_mask = queue_mask;
3019 bp->dma_burst_length = macb_config->dma_burst_length;
3022 bp->tx_clk = tx_clk;
3023 bp->rx_clk = rx_clk;
3025 bp->jumbo_max_len = macb_config->jumbo_max_len;
3028 if (of_get_property(np, "magic-packet", NULL))
3029 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3030 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3032 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3033 if (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1)) > GEM_DBW32)
3034 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
3037 spin_lock_init(&bp->lock);
3039 /* setup capabilities */
3040 macb_configure_caps(bp, macb_config);
3042 platform_set_drvdata(pdev, dev);
3044 dev->irq = platform_get_irq(pdev, 0);
3047 goto err_out_free_netdev;
3050 mac = of_get_mac_address(np);
3052 ether_addr_copy(bp->dev->dev_addr, mac);
3054 macb_get_hwaddr(bp);
3056 /* Power up the PHY if there is a GPIO reset */
3057 phy_node = of_get_next_available_child(np, NULL);
3059 int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
3061 if (gpio_is_valid(gpio)) {
3062 bp->reset_gpio = gpio_to_desc(gpio);
3063 gpiod_direction_output(bp->reset_gpio, 1);
3066 of_node_put(phy_node);
3068 err = of_get_phy_mode(np);
3070 pdata = dev_get_platdata(&pdev->dev);
3071 if (pdata && pdata->is_rmii)
3072 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3074 bp->phy_interface = PHY_INTERFACE_MODE_MII;
3076 bp->phy_interface = err;
3079 /* IP specific init */
3082 goto err_out_free_netdev;
3084 err = macb_mii_init(bp);
3086 goto err_out_free_netdev;
3088 phydev = dev->phydev;
3090 netif_carrier_off(dev);
3092 err = register_netdev(dev);
3094 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
3095 goto err_out_unregister_mdio;
3098 phy_attached_info(phydev);
3100 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3101 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
3102 dev->base_addr, dev->irq, dev->dev_addr);
3106 err_out_unregister_mdio:
3107 phy_disconnect(dev->phydev);
3108 mdiobus_unregister(bp->mii_bus);
3109 mdiobus_free(bp->mii_bus);
3111 /* Shutdown the PHY if there is a GPIO reset */
3113 gpiod_set_value(bp->reset_gpio, 0);
3115 err_out_free_netdev:
3119 clk_disable_unprepare(tx_clk);
3120 clk_disable_unprepare(hclk);
3121 clk_disable_unprepare(pclk);
3122 clk_disable_unprepare(rx_clk);
3127 static int macb_remove(struct platform_device *pdev)
3129 struct net_device *dev;
3132 dev = platform_get_drvdata(pdev);
3135 bp = netdev_priv(dev);
3137 phy_disconnect(dev->phydev);
3138 mdiobus_unregister(bp->mii_bus);
3140 mdiobus_free(bp->mii_bus);
3142 /* Shutdown the PHY if there is a GPIO reset */
3144 gpiod_set_value(bp->reset_gpio, 0);
3146 unregister_netdev(dev);
3147 clk_disable_unprepare(bp->tx_clk);
3148 clk_disable_unprepare(bp->hclk);
3149 clk_disable_unprepare(bp->pclk);
3150 clk_disable_unprepare(bp->rx_clk);
3157 static int __maybe_unused macb_suspend(struct device *dev)
3159 struct platform_device *pdev = to_platform_device(dev);
3160 struct net_device *netdev = platform_get_drvdata(pdev);
3161 struct macb *bp = netdev_priv(netdev);
3163 netif_carrier_off(netdev);
3164 netif_device_detach(netdev);
3166 if (bp->wol & MACB_WOL_ENABLED) {
3167 macb_writel(bp, IER, MACB_BIT(WOL));
3168 macb_writel(bp, WOL, MACB_BIT(MAG));
3169 enable_irq_wake(bp->queues[0].irq);
3171 clk_disable_unprepare(bp->tx_clk);
3172 clk_disable_unprepare(bp->hclk);
3173 clk_disable_unprepare(bp->pclk);
3174 clk_disable_unprepare(bp->rx_clk);
3180 static int __maybe_unused macb_resume(struct device *dev)
3182 struct platform_device *pdev = to_platform_device(dev);
3183 struct net_device *netdev = platform_get_drvdata(pdev);
3184 struct macb *bp = netdev_priv(netdev);
3186 if (bp->wol & MACB_WOL_ENABLED) {
3187 macb_writel(bp, IDR, MACB_BIT(WOL));
3188 macb_writel(bp, WOL, 0);
3189 disable_irq_wake(bp->queues[0].irq);
3191 clk_prepare_enable(bp->pclk);
3192 clk_prepare_enable(bp->hclk);
3193 clk_prepare_enable(bp->tx_clk);
3194 clk_prepare_enable(bp->rx_clk);
3197 netif_device_attach(netdev);
3202 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3204 static struct platform_driver macb_driver = {
3205 .probe = macb_probe,
3206 .remove = macb_remove,
3209 .of_match_table = of_match_ptr(macb_dt_ids),
3214 module_platform_driver(macb_driver);
3216 MODULE_LICENSE("GPL");
3217 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3218 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3219 MODULE_ALIAS("platform:macb");