2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
9 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
10 * refers to Broadcom Inc. and/or its subsidiaries.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/stringify.h>
18 #include <linux/kernel.h>
19 #include <linux/sched/signal.h>
20 #include <linux/types.h>
21 #include <linux/compiler.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/ethtool.h>
32 #include <linux/mdio.h>
33 #include <linux/mii.h>
34 #include <linux/phy.h>
35 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44 #include <linux/ssb/ssb_driver_gige.h>
45 #include <linux/hwmon.h>
46 #include <linux/hwmon-sysfs.h>
47 #include <linux/crc32poly.h>
49 #include <net/checksum.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
56 #include <uapi/linux/net_tstamp.h>
57 #include <linux/ptp_clock_kernel.h>
64 /* Functions & macros to verify TG3_FLAGS types */
66 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
68 return test_bit(flag, bits);
71 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
76 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
78 clear_bit(flag, bits);
81 #define tg3_flag(tp, flag) \
82 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
83 #define tg3_flag_set(tp, flag) \
84 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_clear(tp, flag) \
86 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
88 #define DRV_MODULE_NAME "tg3"
89 /* DO NOT UPDATE TG3_*_NUM defines */
91 #define TG3_MIN_NUM 137
93 #define RESET_KIND_SHUTDOWN 0
94 #define RESET_KIND_INIT 1
95 #define RESET_KIND_SUSPEND 2
97 #define TG3_DEF_RX_MODE 0
98 #define TG3_DEF_TX_MODE 0
99 #define TG3_DEF_MSG_ENABLE \
109 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
111 /* length of time before we decide the hardware is borked,
112 * and dev->tx_timeout() should be called to fix the problem
115 #define TG3_TX_TIMEOUT (5 * HZ)
117 /* hardware minimum and maximum for a single frame's data payload */
118 #define TG3_MIN_MTU ETH_ZLEN
119 #define TG3_MAX_MTU(tp) \
120 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
122 /* These numbers seem to be hard coded in the NIC firmware somehow.
123 * You can't change the ring sizes, but you can change where you place
124 * them in the NIC onboard memory.
126 #define TG3_RX_STD_RING_SIZE(tp) \
127 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
128 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
129 #define TG3_DEF_RX_RING_PENDING 200
130 #define TG3_RX_JMB_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
133 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
135 /* Do not place this n-ring entries value into the tp struct itself,
136 * we really want to expose these constants to GCC so that modulo et
137 * al. operations are done with shifts and masks instead of with
138 * hw multiply/modulo instructions. Another solution would be to
139 * replace things like '% foo' with '& (foo - 1)'.
142 #define TG3_TX_RING_SIZE 512
143 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
145 #define TG3_RX_STD_RING_BYTES(tp) \
146 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
147 #define TG3_RX_JMB_RING_BYTES(tp) \
148 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
149 #define TG3_RX_RCB_RING_BYTES(tp) \
150 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
151 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
153 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
155 #define TG3_DMA_BYTE_ENAB 64
157 #define TG3_RX_STD_DMA_SZ 1536
158 #define TG3_RX_JMB_DMA_SZ 9046
160 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
162 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
163 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
165 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
166 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
168 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
169 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
171 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
172 * that are at least dword aligned when used in PCIX mode. The driver
173 * works around this bug by double copying the packet. This workaround
174 * is built into the normal double copy length check for efficiency.
176 * However, the double copy is only necessary on those architectures
177 * where unaligned memory accesses are inefficient. For those architectures
178 * where unaligned memory accesses incur little penalty, we can reintegrate
179 * the 5701 in the normal rx path. Doing so saves a device structure
180 * dereference by hardcoding the double copy threshold in place.
182 #define TG3_RX_COPY_THRESHOLD 256
183 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
184 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
186 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
189 #if (NET_IP_ALIGN != 0)
190 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
192 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
195 /* minimum number of free TX descriptors required to wake up TX process */
196 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
197 #define TG3_TX_BD_DMA_MAX_2K 2048
198 #define TG3_TX_BD_DMA_MAX_4K 4096
200 #define TG3_RAW_IP_ALIGN 2
202 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
203 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
205 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
206 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
208 #define FIRMWARE_TG3 "/*(DEBLOBBED)*/"
209 #define FIRMWARE_TG357766 "/*(DEBLOBBED)*/"
210 #define FIRMWARE_TG3TSO "/*(DEBLOBBED)*/"
211 #define FIRMWARE_TG3TSO5 "/*(DEBLOBBED)*/"
213 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
214 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
215 MODULE_LICENSE("GPL");
218 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
219 module_param(tg3_debug, int, 0);
220 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
222 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
223 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
225 static const struct pci_device_id tg3_pci_tbl[] = {
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
245 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
246 TG3_DRV_DATA_FLAG_5705_10_100},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
248 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
249 TG3_DRV_DATA_FLAG_5705_10_100},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
252 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
253 TG3_DRV_DATA_FLAG_5705_10_100},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
266 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
274 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
275 PCI_VENDOR_ID_LENOVO,
276 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
277 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
280 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
299 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
300 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
301 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
303 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
304 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
308 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
314 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
315 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
316 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
318 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
333 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
334 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
335 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
336 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
337 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
338 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
339 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
340 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
344 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
346 static const struct {
347 const char string[ETH_GSTRING_LEN];
348 } ethtool_stats_keys[] = {
351 { "rx_ucast_packets" },
352 { "rx_mcast_packets" },
353 { "rx_bcast_packets" },
355 { "rx_align_errors" },
356 { "rx_xon_pause_rcvd" },
357 { "rx_xoff_pause_rcvd" },
358 { "rx_mac_ctrl_rcvd" },
359 { "rx_xoff_entered" },
360 { "rx_frame_too_long_errors" },
362 { "rx_undersize_packets" },
363 { "rx_in_length_errors" },
364 { "rx_out_length_errors" },
365 { "rx_64_or_less_octet_packets" },
366 { "rx_65_to_127_octet_packets" },
367 { "rx_128_to_255_octet_packets" },
368 { "rx_256_to_511_octet_packets" },
369 { "rx_512_to_1023_octet_packets" },
370 { "rx_1024_to_1522_octet_packets" },
371 { "rx_1523_to_2047_octet_packets" },
372 { "rx_2048_to_4095_octet_packets" },
373 { "rx_4096_to_8191_octet_packets" },
374 { "rx_8192_to_9022_octet_packets" },
381 { "tx_flow_control" },
383 { "tx_single_collisions" },
384 { "tx_mult_collisions" },
386 { "tx_excessive_collisions" },
387 { "tx_late_collisions" },
388 { "tx_collide_2times" },
389 { "tx_collide_3times" },
390 { "tx_collide_4times" },
391 { "tx_collide_5times" },
392 { "tx_collide_6times" },
393 { "tx_collide_7times" },
394 { "tx_collide_8times" },
395 { "tx_collide_9times" },
396 { "tx_collide_10times" },
397 { "tx_collide_11times" },
398 { "tx_collide_12times" },
399 { "tx_collide_13times" },
400 { "tx_collide_14times" },
401 { "tx_collide_15times" },
402 { "tx_ucast_packets" },
403 { "tx_mcast_packets" },
404 { "tx_bcast_packets" },
405 { "tx_carrier_sense_errors" },
409 { "dma_writeq_full" },
410 { "dma_write_prioq_full" },
414 { "rx_threshold_hit" },
416 { "dma_readq_full" },
417 { "dma_read_prioq_full" },
418 { "tx_comp_queue_full" },
420 { "ring_set_send_prod_index" },
421 { "ring_status_update" },
423 { "nic_avoided_irqs" },
424 { "nic_tx_threshold_hit" },
426 { "mbuf_lwm_thresh_hit" },
429 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
430 #define TG3_NVRAM_TEST 0
431 #define TG3_LINK_TEST 1
432 #define TG3_REGISTER_TEST 2
433 #define TG3_MEMORY_TEST 3
434 #define TG3_MAC_LOOPB_TEST 4
435 #define TG3_PHY_LOOPB_TEST 5
436 #define TG3_EXT_LOOPB_TEST 6
437 #define TG3_INTERRUPT_TEST 7
440 static const struct {
441 const char string[ETH_GSTRING_LEN];
442 } ethtool_test_keys[] = {
443 [TG3_NVRAM_TEST] = { "nvram test (online) " },
444 [TG3_LINK_TEST] = { "link test (online) " },
445 [TG3_REGISTER_TEST] = { "register test (offline)" },
446 [TG3_MEMORY_TEST] = { "memory test (offline)" },
447 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
448 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
449 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
450 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
453 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
456 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
458 writel(val, tp->regs + off);
461 static u32 tg3_read32(struct tg3 *tp, u32 off)
463 return readl(tp->regs + off);
466 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
468 writel(val, tp->aperegs + off);
471 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
473 return readl(tp->aperegs + off);
476 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
480 spin_lock_irqsave(&tp->indirect_lock, flags);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
482 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
483 spin_unlock_irqrestore(&tp->indirect_lock, flags);
486 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
488 writel(val, tp->regs + off);
489 readl(tp->regs + off);
492 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
497 spin_lock_irqsave(&tp->indirect_lock, flags);
498 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
499 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
500 spin_unlock_irqrestore(&tp->indirect_lock, flags);
504 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
508 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
509 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
510 TG3_64BIT_REG_LOW, val);
513 if (off == TG3_RX_STD_PROD_IDX_REG) {
514 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
515 TG3_64BIT_REG_LOW, val);
519 spin_lock_irqsave(&tp->indirect_lock, flags);
520 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
521 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
522 spin_unlock_irqrestore(&tp->indirect_lock, flags);
524 /* In indirect mode when disabling interrupts, we also need
525 * to clear the interrupt bit in the GRC local ctrl register.
527 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
529 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
530 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
534 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
539 spin_lock_irqsave(&tp->indirect_lock, flags);
540 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
541 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 /* usec_wait specifies the wait time in usec when writing to certain registers
547 * where it is unsafe to read back the register without some delay.
548 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
549 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
551 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
553 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
554 /* Non-posted methods */
555 tp->write32(tp, off, val);
558 tg3_write32(tp, off, val);
563 /* Wait again after the read for the posted method to guarantee that
564 * the wait time is met.
570 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
572 tp->write32_mbox(tp, off, val);
573 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
574 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
575 !tg3_flag(tp, ICH_WORKAROUND)))
576 tp->read32_mbox(tp, off);
579 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
581 void __iomem *mbox = tp->regs + off;
583 if (tg3_flag(tp, TXD_MBOX_HWBUG))
585 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
586 tg3_flag(tp, FLUSH_POSTED_WRITES))
590 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
592 return readl(tp->regs + off + GRCMBOX_BASE);
595 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
597 writel(val, tp->regs + off + GRCMBOX_BASE);
600 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
601 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
602 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
603 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
604 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
606 #define tw32(reg, val) tp->write32(tp, reg, val)
607 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
608 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
609 #define tr32(reg) tp->read32(tp, reg)
611 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
615 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
616 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
619 spin_lock_irqsave(&tp->indirect_lock, flags);
620 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
621 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
622 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
624 /* Always leave this as zero. */
625 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
627 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
628 tw32_f(TG3PCI_MEM_WIN_DATA, val);
630 /* Always leave this as zero. */
631 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
633 spin_unlock_irqrestore(&tp->indirect_lock, flags);
636 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
640 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
641 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
646 spin_lock_irqsave(&tp->indirect_lock, flags);
647 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
648 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
649 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
651 /* Always leave this as zero. */
652 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
654 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
655 *val = tr32(TG3PCI_MEM_WIN_DATA);
657 /* Always leave this as zero. */
658 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
660 spin_unlock_irqrestore(&tp->indirect_lock, flags);
663 static void tg3_ape_lock_init(struct tg3 *tp)
668 if (tg3_asic_rev(tp) == ASIC_REV_5761)
669 regbase = TG3_APE_LOCK_GRANT;
671 regbase = TG3_APE_PER_LOCK_GRANT;
673 /* Make sure the driver hasn't any stale locks. */
674 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
676 case TG3_APE_LOCK_PHY0:
677 case TG3_APE_LOCK_PHY1:
678 case TG3_APE_LOCK_PHY2:
679 case TG3_APE_LOCK_PHY3:
680 bit = APE_LOCK_GRANT_DRIVER;
684 bit = APE_LOCK_GRANT_DRIVER;
686 bit = 1 << tp->pci_fn;
688 tg3_ape_write32(tp, regbase + 4 * i, bit);
693 static int tg3_ape_lock(struct tg3 *tp, int locknum)
697 u32 status, req, gnt, bit;
699 if (!tg3_flag(tp, ENABLE_APE))
703 case TG3_APE_LOCK_GPIO:
704 if (tg3_asic_rev(tp) == ASIC_REV_5761)
707 case TG3_APE_LOCK_GRC:
708 case TG3_APE_LOCK_MEM:
710 bit = APE_LOCK_REQ_DRIVER;
712 bit = 1 << tp->pci_fn;
714 case TG3_APE_LOCK_PHY0:
715 case TG3_APE_LOCK_PHY1:
716 case TG3_APE_LOCK_PHY2:
717 case TG3_APE_LOCK_PHY3:
718 bit = APE_LOCK_REQ_DRIVER;
724 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
725 req = TG3_APE_LOCK_REQ;
726 gnt = TG3_APE_LOCK_GRANT;
728 req = TG3_APE_PER_LOCK_REQ;
729 gnt = TG3_APE_PER_LOCK_GRANT;
734 tg3_ape_write32(tp, req + off, bit);
736 /* Wait for up to 1 millisecond to acquire lock. */
737 for (i = 0; i < 100; i++) {
738 status = tg3_ape_read32(tp, gnt + off);
741 if (pci_channel_offline(tp->pdev))
748 /* Revoke the lock request. */
749 tg3_ape_write32(tp, gnt + off, bit);
756 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
760 if (!tg3_flag(tp, ENABLE_APE))
764 case TG3_APE_LOCK_GPIO:
765 if (tg3_asic_rev(tp) == ASIC_REV_5761)
768 case TG3_APE_LOCK_GRC:
769 case TG3_APE_LOCK_MEM:
771 bit = APE_LOCK_GRANT_DRIVER;
773 bit = 1 << tp->pci_fn;
775 case TG3_APE_LOCK_PHY0:
776 case TG3_APE_LOCK_PHY1:
777 case TG3_APE_LOCK_PHY2:
778 case TG3_APE_LOCK_PHY3:
779 bit = APE_LOCK_GRANT_DRIVER;
785 if (tg3_asic_rev(tp) == ASIC_REV_5761)
786 gnt = TG3_APE_LOCK_GRANT;
788 gnt = TG3_APE_PER_LOCK_GRANT;
790 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
793 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
798 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
801 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
802 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
805 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
808 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
811 return timeout_us ? 0 : -EBUSY;
814 #ifdef CONFIG_TIGON3_HWMON
815 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
819 for (i = 0; i < timeout_us / 10; i++) {
820 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
822 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
828 return i == timeout_us / 10;
831 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
835 u32 i, bufoff, msgoff, maxlen, apedata;
837 if (!tg3_flag(tp, APE_HAS_NCSI))
840 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
841 if (apedata != APE_SEG_SIG_MAGIC)
844 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
845 if (!(apedata & APE_FW_STATUS_READY))
848 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
850 msgoff = bufoff + 2 * sizeof(u32);
851 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
856 /* Cap xfer sizes to scratchpad limits. */
857 length = (len > maxlen) ? maxlen : len;
860 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
861 if (!(apedata & APE_FW_STATUS_READY))
864 /* Wait for up to 1 msec for APE to service previous event. */
865 err = tg3_ape_event_lock(tp, 1000);
869 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
870 APE_EVENT_STATUS_SCRTCHPD_READ |
871 APE_EVENT_STATUS_EVENT_PENDING;
872 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
874 tg3_ape_write32(tp, bufoff, base_off);
875 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
877 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
878 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
882 if (tg3_ape_wait_for_event(tp, 30000))
885 for (i = 0; length; i += 4, length -= 4) {
886 u32 val = tg3_ape_read32(tp, msgoff + i);
887 memcpy(data, &val, sizeof(u32));
896 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
901 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
902 if (apedata != APE_SEG_SIG_MAGIC)
905 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
906 if (!(apedata & APE_FW_STATUS_READY))
909 /* Wait for up to 20 millisecond for APE to service previous event. */
910 err = tg3_ape_event_lock(tp, 20000);
914 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
915 event | APE_EVENT_STATUS_EVENT_PENDING);
917 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
918 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
923 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
928 if (!tg3_flag(tp, ENABLE_APE))
932 case RESET_KIND_INIT:
933 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
934 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
935 APE_HOST_SEG_SIG_MAGIC);
936 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
937 APE_HOST_SEG_LEN_MAGIC);
938 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
939 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
940 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
941 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
942 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
943 APE_HOST_BEHAV_NO_PHYLOCK);
944 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
945 TG3_APE_HOST_DRVR_STATE_START);
947 event = APE_EVENT_STATUS_STATE_START;
949 case RESET_KIND_SHUTDOWN:
950 if (device_may_wakeup(&tp->pdev->dev) &&
951 tg3_flag(tp, WOL_ENABLE)) {
952 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
953 TG3_APE_HOST_WOL_SPEED_AUTO);
954 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
956 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
958 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
960 event = APE_EVENT_STATUS_STATE_UNLOAD;
966 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
968 tg3_ape_send_event(tp, event);
971 static void tg3_send_ape_heartbeat(struct tg3 *tp,
972 unsigned long interval)
974 /* Check if hb interval has exceeded */
975 if (!tg3_flag(tp, ENABLE_APE) ||
976 time_before(jiffies, tp->ape_hb_jiffies + interval))
979 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
980 tp->ape_hb_jiffies = jiffies;
983 static void tg3_disable_ints(struct tg3 *tp)
987 tw32(TG3PCI_MISC_HOST_CTRL,
988 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
989 for (i = 0; i < tp->irq_max; i++)
990 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
993 static void tg3_enable_ints(struct tg3 *tp)
1000 tw32(TG3PCI_MISC_HOST_CTRL,
1001 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1003 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1004 for (i = 0; i < tp->irq_cnt; i++) {
1005 struct tg3_napi *tnapi = &tp->napi[i];
1007 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1008 if (tg3_flag(tp, 1SHOT_MSI))
1009 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1011 tp->coal_now |= tnapi->coal_now;
1014 /* Force an initial interrupt */
1015 if (!tg3_flag(tp, TAGGED_STATUS) &&
1016 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1017 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1019 tw32(HOSTCC_MODE, tp->coal_now);
1021 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1024 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1026 struct tg3 *tp = tnapi->tp;
1027 struct tg3_hw_status *sblk = tnapi->hw_status;
1028 unsigned int work_exists = 0;
1030 /* check for phy events */
1031 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1032 if (sblk->status & SD_STATUS_LINK_CHG)
1036 /* check for TX work to do */
1037 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1040 /* check for RX work to do */
1041 if (tnapi->rx_rcb_prod_idx &&
1042 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1049 * similar to tg3_enable_ints, but it accurately determines whether there
1050 * is new work pending and can return without flushing the PIO write
1051 * which reenables interrupts
1053 static void tg3_int_reenable(struct tg3_napi *tnapi)
1055 struct tg3 *tp = tnapi->tp;
1057 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1059 /* When doing tagged status, this work check is unnecessary.
1060 * The last_tag we write above tells the chip which piece of
1061 * work we've completed.
1063 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1064 tw32(HOSTCC_MODE, tp->coalesce_mode |
1065 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1068 static void tg3_switch_clocks(struct tg3 *tp)
1071 u32 orig_clock_ctrl;
1073 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1076 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1078 orig_clock_ctrl = clock_ctrl;
1079 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1080 CLOCK_CTRL_CLKRUN_OENABLE |
1082 tp->pci_clock_ctrl = clock_ctrl;
1084 if (tg3_flag(tp, 5705_PLUS)) {
1085 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1086 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1087 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1089 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1090 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1092 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1094 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1095 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1098 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1101 #define PHY_BUSY_LOOPS 5000
1103 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1112 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1116 tg3_ape_lock(tp, tp->phy_ape_lock);
1120 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1121 MI_COM_PHY_ADDR_MASK);
1122 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1123 MI_COM_REG_ADDR_MASK);
1124 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1126 tw32_f(MAC_MI_COM, frame_val);
1128 loops = PHY_BUSY_LOOPS;
1129 while (loops != 0) {
1131 frame_val = tr32(MAC_MI_COM);
1133 if ((frame_val & MI_COM_BUSY) == 0) {
1135 frame_val = tr32(MAC_MI_COM);
1143 *val = frame_val & MI_COM_DATA_MASK;
1147 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1148 tw32_f(MAC_MI_MODE, tp->mi_mode);
1152 tg3_ape_unlock(tp, tp->phy_ape_lock);
1157 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1159 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1162 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1170 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1173 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1175 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1179 tg3_ape_lock(tp, tp->phy_ape_lock);
1181 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1182 MI_COM_PHY_ADDR_MASK);
1183 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1184 MI_COM_REG_ADDR_MASK);
1185 frame_val |= (val & MI_COM_DATA_MASK);
1186 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1188 tw32_f(MAC_MI_COM, frame_val);
1190 loops = PHY_BUSY_LOOPS;
1191 while (loops != 0) {
1193 frame_val = tr32(MAC_MI_COM);
1194 if ((frame_val & MI_COM_BUSY) == 0) {
1196 frame_val = tr32(MAC_MI_COM);
1206 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1207 tw32_f(MAC_MI_MODE, tp->mi_mode);
1211 tg3_ape_unlock(tp, tp->phy_ape_lock);
1216 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1218 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1221 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1225 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1229 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1233 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1234 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1238 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1244 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1248 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1256 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1257 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1261 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1267 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1271 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1273 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1278 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1282 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1284 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1289 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1293 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1294 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1295 MII_TG3_AUXCTL_SHDWSEL_MISC);
1297 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1302 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1304 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1305 set |= MII_TG3_AUXCTL_MISC_WREN;
1307 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1310 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1315 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1321 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1323 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1325 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1326 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1331 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1333 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1334 reg | val | MII_TG3_MISC_SHDW_WREN);
1337 static int tg3_bmcr_reset(struct tg3 *tp)
1342 /* OK, reset it, and poll the BMCR_RESET bit until it
1343 * clears or we time out.
1345 phy_control = BMCR_RESET;
1346 err = tg3_writephy(tp, MII_BMCR, phy_control);
1352 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1356 if ((phy_control & BMCR_RESET) == 0) {
1368 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1370 struct tg3 *tp = bp->priv;
1373 spin_lock_bh(&tp->lock);
1375 if (__tg3_readphy(tp, mii_id, reg, &val))
1378 spin_unlock_bh(&tp->lock);
1383 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1385 struct tg3 *tp = bp->priv;
1388 spin_lock_bh(&tp->lock);
1390 if (__tg3_writephy(tp, mii_id, reg, val))
1393 spin_unlock_bh(&tp->lock);
1398 static void tg3_mdio_config_5785(struct tg3 *tp)
1401 struct phy_device *phydev;
1403 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1404 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1405 case PHY_ID_BCM50610:
1406 case PHY_ID_BCM50610M:
1407 val = MAC_PHYCFG2_50610_LED_MODES;
1409 case PHY_ID_BCMAC131:
1410 val = MAC_PHYCFG2_AC131_LED_MODES;
1412 case PHY_ID_RTL8211C:
1413 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1415 case PHY_ID_RTL8201E:
1416 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1422 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1423 tw32(MAC_PHYCFG2, val);
1425 val = tr32(MAC_PHYCFG1);
1426 val &= ~(MAC_PHYCFG1_RGMII_INT |
1427 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1428 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1429 tw32(MAC_PHYCFG1, val);
1434 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1435 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1436 MAC_PHYCFG2_FMODE_MASK_MASK |
1437 MAC_PHYCFG2_GMODE_MASK_MASK |
1438 MAC_PHYCFG2_ACT_MASK_MASK |
1439 MAC_PHYCFG2_QUAL_MASK_MASK |
1440 MAC_PHYCFG2_INBAND_ENABLE;
1442 tw32(MAC_PHYCFG2, val);
1444 val = tr32(MAC_PHYCFG1);
1445 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1446 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1447 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1448 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1449 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1450 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1451 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1453 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1454 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1455 tw32(MAC_PHYCFG1, val);
1457 val = tr32(MAC_EXT_RGMII_MODE);
1458 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1459 MAC_RGMII_MODE_RX_QUALITY |
1460 MAC_RGMII_MODE_RX_ACTIVITY |
1461 MAC_RGMII_MODE_RX_ENG_DET |
1462 MAC_RGMII_MODE_TX_ENABLE |
1463 MAC_RGMII_MODE_TX_LOWPWR |
1464 MAC_RGMII_MODE_TX_RESET);
1465 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1466 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1467 val |= MAC_RGMII_MODE_RX_INT_B |
1468 MAC_RGMII_MODE_RX_QUALITY |
1469 MAC_RGMII_MODE_RX_ACTIVITY |
1470 MAC_RGMII_MODE_RX_ENG_DET;
1471 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1472 val |= MAC_RGMII_MODE_TX_ENABLE |
1473 MAC_RGMII_MODE_TX_LOWPWR |
1474 MAC_RGMII_MODE_TX_RESET;
1476 tw32(MAC_EXT_RGMII_MODE, val);
1479 static void tg3_mdio_start(struct tg3 *tp)
1481 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1482 tw32_f(MAC_MI_MODE, tp->mi_mode);
1485 if (tg3_flag(tp, MDIOBUS_INITED) &&
1486 tg3_asic_rev(tp) == ASIC_REV_5785)
1487 tg3_mdio_config_5785(tp);
1490 static int tg3_mdio_init(struct tg3 *tp)
1494 struct phy_device *phydev;
1496 if (tg3_flag(tp, 5717_PLUS)) {
1499 tp->phy_addr = tp->pci_fn + 1;
1501 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1502 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1504 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1505 TG3_CPMU_PHY_STRAP_IS_SERDES;
1508 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1511 addr = ssb_gige_get_phyaddr(tp->pdev);
1514 tp->phy_addr = addr;
1516 tp->phy_addr = TG3_PHY_MII_ADDR;
1520 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1523 tp->mdio_bus = mdiobus_alloc();
1524 if (tp->mdio_bus == NULL)
1527 tp->mdio_bus->name = "tg3 mdio bus";
1528 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1529 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1530 tp->mdio_bus->priv = tp;
1531 tp->mdio_bus->parent = &tp->pdev->dev;
1532 tp->mdio_bus->read = &tg3_mdio_read;
1533 tp->mdio_bus->write = &tg3_mdio_write;
1534 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1536 /* The bus registration will look for all the PHYs on the mdio bus.
1537 * Unfortunately, it does not ensure the PHY is powered up before
1538 * accessing the PHY ID registers. A chip reset is the
1539 * quickest way to bring the device back to an operational state..
1541 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1544 i = mdiobus_register(tp->mdio_bus);
1546 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1547 mdiobus_free(tp->mdio_bus);
1551 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1553 if (!phydev || !phydev->drv) {
1554 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1555 mdiobus_unregister(tp->mdio_bus);
1556 mdiobus_free(tp->mdio_bus);
1560 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1561 case PHY_ID_BCM57780:
1562 phydev->interface = PHY_INTERFACE_MODE_GMII;
1563 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1565 case PHY_ID_BCM50610:
1566 case PHY_ID_BCM50610M:
1567 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1568 PHY_BRCM_RX_REFCLK_UNUSED |
1569 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1570 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1571 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1572 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1573 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1574 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1575 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1576 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1578 case PHY_ID_RTL8211C:
1579 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1581 case PHY_ID_RTL8201E:
1582 case PHY_ID_BCMAC131:
1583 phydev->interface = PHY_INTERFACE_MODE_MII;
1584 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1585 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1589 tg3_flag_set(tp, MDIOBUS_INITED);
1591 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1592 tg3_mdio_config_5785(tp);
1597 static void tg3_mdio_fini(struct tg3 *tp)
1599 if (tg3_flag(tp, MDIOBUS_INITED)) {
1600 tg3_flag_clear(tp, MDIOBUS_INITED);
1601 mdiobus_unregister(tp->mdio_bus);
1602 mdiobus_free(tp->mdio_bus);
1606 /* tp->lock is held. */
1607 static inline void tg3_generate_fw_event(struct tg3 *tp)
1611 val = tr32(GRC_RX_CPU_EVENT);
1612 val |= GRC_RX_CPU_DRIVER_EVENT;
1613 tw32_f(GRC_RX_CPU_EVENT, val);
1615 tp->last_event_jiffies = jiffies;
1618 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1620 /* tp->lock is held. */
1621 static void tg3_wait_for_event_ack(struct tg3 *tp)
1624 unsigned int delay_cnt;
1627 /* If enough time has passed, no wait is necessary. */
1628 time_remain = (long)(tp->last_event_jiffies + 1 +
1629 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1631 if (time_remain < 0)
1634 /* Check if we can shorten the wait time. */
1635 delay_cnt = jiffies_to_usecs(time_remain);
1636 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1637 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1638 delay_cnt = (delay_cnt >> 3) + 1;
1640 for (i = 0; i < delay_cnt; i++) {
1641 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1643 if (pci_channel_offline(tp->pdev))
1650 /* tp->lock is held. */
1651 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1656 if (!tg3_readphy(tp, MII_BMCR, ®))
1658 if (!tg3_readphy(tp, MII_BMSR, ®))
1659 val |= (reg & 0xffff);
1663 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1665 if (!tg3_readphy(tp, MII_LPA, ®))
1666 val |= (reg & 0xffff);
1670 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1671 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1673 if (!tg3_readphy(tp, MII_STAT1000, ®))
1674 val |= (reg & 0xffff);
1678 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1685 /* tp->lock is held. */
1686 static void tg3_ump_link_report(struct tg3 *tp)
1690 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1693 tg3_phy_gather_ump_data(tp, data);
1695 tg3_wait_for_event_ack(tp);
1697 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1698 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1699 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1700 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1701 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1702 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1704 tg3_generate_fw_event(tp);
1707 /* tp->lock is held. */
1708 static void tg3_stop_fw(struct tg3 *tp)
1710 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1711 /* Wait for RX cpu to ACK the previous event. */
1712 tg3_wait_for_event_ack(tp);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1716 tg3_generate_fw_event(tp);
1718 /* Wait for RX cpu to ACK this event. */
1719 tg3_wait_for_event_ack(tp);
1723 /* tp->lock is held. */
1724 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1726 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1727 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1729 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1731 case RESET_KIND_INIT:
1732 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1736 case RESET_KIND_SHUTDOWN:
1737 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1741 case RESET_KIND_SUSPEND:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1752 /* tp->lock is held. */
1753 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1755 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1757 case RESET_KIND_INIT:
1758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 DRV_STATE_START_DONE);
1762 case RESET_KIND_SHUTDOWN:
1763 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1764 DRV_STATE_UNLOAD_DONE);
1773 /* tp->lock is held. */
1774 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1776 if (tg3_flag(tp, ENABLE_ASF)) {
1778 case RESET_KIND_INIT:
1779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1783 case RESET_KIND_SHUTDOWN:
1784 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1788 case RESET_KIND_SUSPEND:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1799 static int tg3_poll_fw(struct tg3 *tp)
1804 if (tg3_flag(tp, NO_FWARE_REPORTED))
1807 if (tg3_flag(tp, IS_SSB_CORE)) {
1808 /* We don't use firmware. */
1812 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1813 /* Wait up to 20ms for init done. */
1814 for (i = 0; i < 200; i++) {
1815 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1817 if (pci_channel_offline(tp->pdev))
1825 /* Wait for firmware initialization to complete. */
1826 for (i = 0; i < 100000; i++) {
1827 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1828 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1830 if (pci_channel_offline(tp->pdev)) {
1831 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1832 tg3_flag_set(tp, NO_FWARE_REPORTED);
1833 netdev_info(tp->dev, "No firmware running\n");
1842 /* Chip might not be fitted with firmware. Some Sun onboard
1843 * parts are configured like that. So don't signal the timeout
1844 * of the above loop as an error, but do report the lack of
1845 * running firmware once.
1847 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1848 tg3_flag_set(tp, NO_FWARE_REPORTED);
1850 netdev_info(tp->dev, "No firmware running\n");
1853 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1854 /* The 57765 A0 needs a little more
1855 * time to do some important work.
1863 static void tg3_link_report(struct tg3 *tp)
1865 if (!netif_carrier_ok(tp->dev)) {
1866 netif_info(tp, link, tp->dev, "Link is down\n");
1867 tg3_ump_link_report(tp);
1868 } else if (netif_msg_link(tp)) {
1869 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1870 (tp->link_config.active_speed == SPEED_1000 ?
1872 (tp->link_config.active_speed == SPEED_100 ?
1874 (tp->link_config.active_duplex == DUPLEX_FULL ?
1877 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1878 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1880 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1883 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1884 netdev_info(tp->dev, "EEE is %s\n",
1885 tp->setlpicnt ? "enabled" : "disabled");
1887 tg3_ump_link_report(tp);
1890 tp->link_up = netif_carrier_ok(tp->dev);
1893 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1897 if (adv & ADVERTISE_PAUSE_CAP) {
1898 flowctrl |= FLOW_CTRL_RX;
1899 if (!(adv & ADVERTISE_PAUSE_ASYM))
1900 flowctrl |= FLOW_CTRL_TX;
1901 } else if (adv & ADVERTISE_PAUSE_ASYM)
1902 flowctrl |= FLOW_CTRL_TX;
1907 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1911 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1912 miireg = ADVERTISE_1000XPAUSE;
1913 else if (flow_ctrl & FLOW_CTRL_TX)
1914 miireg = ADVERTISE_1000XPSE_ASYM;
1915 else if (flow_ctrl & FLOW_CTRL_RX)
1916 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1923 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1927 if (adv & ADVERTISE_1000XPAUSE) {
1928 flowctrl |= FLOW_CTRL_RX;
1929 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1930 flowctrl |= FLOW_CTRL_TX;
1931 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1932 flowctrl |= FLOW_CTRL_TX;
1937 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1941 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1942 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1943 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1944 if (lcladv & ADVERTISE_1000XPAUSE)
1946 if (rmtadv & ADVERTISE_1000XPAUSE)
1953 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1957 u32 old_rx_mode = tp->rx_mode;
1958 u32 old_tx_mode = tp->tx_mode;
1960 if (tg3_flag(tp, USE_PHYLIB))
1961 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1963 autoneg = tp->link_config.autoneg;
1965 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1966 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1967 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1969 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1971 flowctrl = tp->link_config.flowctrl;
1973 tp->link_config.active_flowctrl = flowctrl;
1975 if (flowctrl & FLOW_CTRL_RX)
1976 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1978 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1980 if (old_rx_mode != tp->rx_mode)
1981 tw32_f(MAC_RX_MODE, tp->rx_mode);
1983 if (flowctrl & FLOW_CTRL_TX)
1984 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1986 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1988 if (old_tx_mode != tp->tx_mode)
1989 tw32_f(MAC_TX_MODE, tp->tx_mode);
1992 static void tg3_adjust_link(struct net_device *dev)
1994 u8 oldflowctrl, linkmesg = 0;
1995 u32 mac_mode, lcl_adv, rmt_adv;
1996 struct tg3 *tp = netdev_priv(dev);
1997 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1999 spin_lock_bh(&tp->lock);
2001 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2002 MAC_MODE_HALF_DUPLEX);
2004 oldflowctrl = tp->link_config.active_flowctrl;
2010 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2011 mac_mode |= MAC_MODE_PORT_MODE_MII;
2012 else if (phydev->speed == SPEED_1000 ||
2013 tg3_asic_rev(tp) != ASIC_REV_5785)
2014 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2016 mac_mode |= MAC_MODE_PORT_MODE_MII;
2018 if (phydev->duplex == DUPLEX_HALF)
2019 mac_mode |= MAC_MODE_HALF_DUPLEX;
2021 lcl_adv = mii_advertise_flowctrl(
2022 tp->link_config.flowctrl);
2025 rmt_adv = LPA_PAUSE_CAP;
2026 if (phydev->asym_pause)
2027 rmt_adv |= LPA_PAUSE_ASYM;
2030 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2032 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2034 if (mac_mode != tp->mac_mode) {
2035 tp->mac_mode = mac_mode;
2036 tw32_f(MAC_MODE, tp->mac_mode);
2040 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2041 if (phydev->speed == SPEED_10)
2043 MAC_MI_STAT_10MBPS_MODE |
2044 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2046 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2049 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2050 tw32(MAC_TX_LENGTHS,
2051 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2052 (6 << TX_LENGTHS_IPG_SHIFT) |
2053 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2055 tw32(MAC_TX_LENGTHS,
2056 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2057 (6 << TX_LENGTHS_IPG_SHIFT) |
2058 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2060 if (phydev->link != tp->old_link ||
2061 phydev->speed != tp->link_config.active_speed ||
2062 phydev->duplex != tp->link_config.active_duplex ||
2063 oldflowctrl != tp->link_config.active_flowctrl)
2066 tp->old_link = phydev->link;
2067 tp->link_config.active_speed = phydev->speed;
2068 tp->link_config.active_duplex = phydev->duplex;
2070 spin_unlock_bh(&tp->lock);
2073 tg3_link_report(tp);
2076 static int tg3_phy_init(struct tg3 *tp)
2078 struct phy_device *phydev;
2080 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2083 /* Bring the PHY back to a known state. */
2086 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2088 /* Attach the MAC to the PHY. */
2089 phydev = phy_connect(tp->dev, phydev_name(phydev),
2090 tg3_adjust_link, phydev->interface);
2091 if (IS_ERR(phydev)) {
2092 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2093 return PTR_ERR(phydev);
2096 /* Mask with MAC supported features. */
2097 switch (phydev->interface) {
2098 case PHY_INTERFACE_MODE_GMII:
2099 case PHY_INTERFACE_MODE_RGMII:
2100 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2101 phy_set_max_speed(phydev, SPEED_1000);
2102 phy_support_asym_pause(phydev);
2106 case PHY_INTERFACE_MODE_MII:
2107 phy_set_max_speed(phydev, SPEED_100);
2108 phy_support_asym_pause(phydev);
2111 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2115 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2117 phy_attached_info(phydev);
2122 static void tg3_phy_start(struct tg3 *tp)
2124 struct phy_device *phydev;
2126 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2129 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2131 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2132 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2133 phydev->speed = tp->link_config.speed;
2134 phydev->duplex = tp->link_config.duplex;
2135 phydev->autoneg = tp->link_config.autoneg;
2136 ethtool_convert_legacy_u32_to_link_mode(
2137 phydev->advertising, tp->link_config.advertising);
2142 phy_start_aneg(phydev);
2145 static void tg3_phy_stop(struct tg3 *tp)
2147 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2150 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2153 static void tg3_phy_fini(struct tg3 *tp)
2155 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2156 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2157 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2161 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2169 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2170 /* Cannot do read-modify-write on 5401 */
2171 err = tg3_phy_auxctl_write(tp,
2172 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2173 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2178 err = tg3_phy_auxctl_read(tp,
2179 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2183 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2184 err = tg3_phy_auxctl_write(tp,
2185 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2191 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2195 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2198 tg3_writephy(tp, MII_TG3_FET_TEST,
2199 phytest | MII_TG3_FET_SHADOW_EN);
2200 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2202 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2204 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2205 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2207 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2211 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2215 if (!tg3_flag(tp, 5705_PLUS) ||
2216 (tg3_flag(tp, 5717_PLUS) &&
2217 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2220 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2221 tg3_phy_fet_toggle_apd(tp, enable);
2225 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2226 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2227 MII_TG3_MISC_SHDW_SCR5_SDTL |
2228 MII_TG3_MISC_SHDW_SCR5_C125OE;
2229 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2230 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2232 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2235 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2237 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2239 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2242 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2246 if (!tg3_flag(tp, 5705_PLUS) ||
2247 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2250 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2253 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2254 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2256 tg3_writephy(tp, MII_TG3_FET_TEST,
2257 ephy | MII_TG3_FET_SHADOW_EN);
2258 if (!tg3_readphy(tp, reg, &phy)) {
2260 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2262 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2263 tg3_writephy(tp, reg, phy);
2265 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2270 ret = tg3_phy_auxctl_read(tp,
2271 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2274 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2276 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2277 tg3_phy_auxctl_write(tp,
2278 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2283 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2288 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2291 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2293 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2294 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2297 static void tg3_phy_apply_otp(struct tg3 *tp)
2306 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2309 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2310 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2311 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2313 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2314 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2315 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2317 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2318 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2319 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2321 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2322 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2324 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2325 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2327 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2328 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2331 tg3_phy_toggle_auxctl_smdsp(tp, false);
2334 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2337 struct ethtool_eee *dest = &tp->eee;
2339 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2345 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2348 /* Pull eee_active */
2349 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2350 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2351 dest->eee_active = 1;
2353 dest->eee_active = 0;
2355 /* Pull lp advertised settings */
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2358 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2360 /* Pull advertised and eee_enabled settings */
2361 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2363 dest->eee_enabled = !!val;
2364 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2366 /* Pull tx_lpi_enabled */
2367 val = tr32(TG3_CPMU_EEE_MODE);
2368 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2370 /* Pull lpi timer value */
2371 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2374 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2378 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2383 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2385 tp->link_config.active_duplex == DUPLEX_FULL &&
2386 (tp->link_config.active_speed == SPEED_100 ||
2387 tp->link_config.active_speed == SPEED_1000)) {
2390 if (tp->link_config.active_speed == SPEED_1000)
2391 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2393 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2395 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2397 tg3_eee_pull_config(tp, NULL);
2398 if (tp->eee.eee_active)
2402 if (!tp->setlpicnt) {
2403 if (current_link_up &&
2404 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2405 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2406 tg3_phy_toggle_auxctl_smdsp(tp, false);
2409 val = tr32(TG3_CPMU_EEE_MODE);
2410 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2414 static void tg3_phy_eee_enable(struct tg3 *tp)
2418 if (tp->link_config.active_speed == SPEED_1000 &&
2419 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2420 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2421 tg3_flag(tp, 57765_CLASS)) &&
2422 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2423 val = MII_TG3_DSP_TAP26_ALNOKO |
2424 MII_TG3_DSP_TAP26_RMRXSTO;
2425 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2426 tg3_phy_toggle_auxctl_smdsp(tp, false);
2429 val = tr32(TG3_CPMU_EEE_MODE);
2430 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2433 static int tg3_wait_macro_done(struct tg3 *tp)
2440 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2441 if ((tmp32 & 0x1000) == 0)
2451 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2453 static const u32 test_pat[4][6] = {
2454 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2455 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2456 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2457 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2461 for (chan = 0; chan < 4; chan++) {
2464 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2465 (chan * 0x2000) | 0x0200);
2466 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2468 for (i = 0; i < 6; i++)
2469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2472 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2473 if (tg3_wait_macro_done(tp)) {
2478 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 (chan * 0x2000) | 0x0200);
2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2481 if (tg3_wait_macro_done(tp)) {
2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2487 if (tg3_wait_macro_done(tp)) {
2492 for (i = 0; i < 6; i += 2) {
2495 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2496 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2497 tg3_wait_macro_done(tp)) {
2503 if (low != test_pat[chan][i] ||
2504 high != test_pat[chan][i+1]) {
2505 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2506 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2507 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2517 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2521 for (chan = 0; chan < 4; chan++) {
2524 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2525 (chan * 0x2000) | 0x0200);
2526 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2527 for (i = 0; i < 6; i++)
2528 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2529 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2530 if (tg3_wait_macro_done(tp))
2537 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2539 u32 reg32, phy9_orig;
2540 int retries, do_phy_reset, err;
2546 err = tg3_bmcr_reset(tp);
2552 /* Disable transmitter and interrupt. */
2553 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2557 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2559 /* Set full-duplex, 1000 mbps. */
2560 tg3_writephy(tp, MII_BMCR,
2561 BMCR_FULLDPLX | BMCR_SPEED1000);
2563 /* Set to master mode. */
2564 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2567 tg3_writephy(tp, MII_CTRL1000,
2568 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2570 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2574 /* Block the PHY control access. */
2575 tg3_phydsp_write(tp, 0x8005, 0x0800);
2577 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2580 } while (--retries);
2582 err = tg3_phy_reset_chanpat(tp);
2586 tg3_phydsp_write(tp, 0x8005, 0x0000);
2588 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2589 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2591 tg3_phy_toggle_auxctl_smdsp(tp, false);
2593 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2595 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2600 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2605 static void tg3_carrier_off(struct tg3 *tp)
2607 netif_carrier_off(tp->dev);
2608 tp->link_up = false;
2611 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2613 if (tg3_flag(tp, ENABLE_ASF))
2614 netdev_warn(tp->dev,
2615 "Management side-band traffic will be interrupted during phy settings change\n");
2618 /* This will reset the tigon3 PHY if there is no valid
2619 * link unless the FORCE argument is non-zero.
2621 static int tg3_phy_reset(struct tg3 *tp)
2626 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2627 val = tr32(GRC_MISC_CFG);
2628 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2631 err = tg3_readphy(tp, MII_BMSR, &val);
2632 err |= tg3_readphy(tp, MII_BMSR, &val);
2636 if (netif_running(tp->dev) && tp->link_up) {
2637 netif_carrier_off(tp->dev);
2638 tg3_link_report(tp);
2641 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2642 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2643 tg3_asic_rev(tp) == ASIC_REV_5705) {
2644 err = tg3_phy_reset_5703_4_5(tp);
2651 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2652 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2653 cpmuctrl = tr32(TG3_CPMU_CTRL);
2654 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2656 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2659 err = tg3_bmcr_reset(tp);
2663 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2664 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2665 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2667 tw32(TG3_CPMU_CTRL, cpmuctrl);
2670 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2671 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2672 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2673 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2674 CPMU_LSPD_1000MB_MACCLK_12_5) {
2675 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2677 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2681 if (tg3_flag(tp, 5717_PLUS) &&
2682 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2685 tg3_phy_apply_otp(tp);
2687 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2688 tg3_phy_toggle_apd(tp, true);
2690 tg3_phy_toggle_apd(tp, false);
2693 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2694 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2695 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2696 tg3_phydsp_write(tp, 0x000a, 0x0323);
2697 tg3_phy_toggle_auxctl_smdsp(tp, false);
2700 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2701 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2702 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2705 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2706 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2707 tg3_phydsp_write(tp, 0x000a, 0x310b);
2708 tg3_phydsp_write(tp, 0x201f, 0x9506);
2709 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2710 tg3_phy_toggle_auxctl_smdsp(tp, false);
2712 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2713 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2714 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2715 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2716 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2717 tg3_writephy(tp, MII_TG3_TEST1,
2718 MII_TG3_TEST1_TRIM_EN | 0x4);
2720 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2722 tg3_phy_toggle_auxctl_smdsp(tp, false);
2726 /* Set Extended packet length bit (bit 14) on all chips that */
2727 /* support jumbo frames */
2728 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2729 /* Cannot do read-modify-write on 5401 */
2730 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2731 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2732 /* Set bit 14 with read-modify-write to preserve other bits */
2733 err = tg3_phy_auxctl_read(tp,
2734 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2736 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2737 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2740 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2741 * jumbo frames transmission.
2743 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2744 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2745 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2746 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2749 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2750 /* adjust output voltage */
2751 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2754 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2755 tg3_phydsp_write(tp, 0xffb, 0x4000);
2757 tg3_phy_toggle_automdix(tp, true);
2758 tg3_phy_set_wirespeed(tp);
2762 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2763 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2764 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2765 TG3_GPIO_MSG_NEED_VAUX)
2766 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2767 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2768 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2769 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2770 (TG3_GPIO_MSG_DRVR_PRES << 12))
2772 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2773 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2774 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2775 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2776 (TG3_GPIO_MSG_NEED_VAUX << 12))
2778 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2782 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2783 tg3_asic_rev(tp) == ASIC_REV_5719)
2784 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2786 status = tr32(TG3_CPMU_DRV_STATUS);
2788 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2789 status &= ~(TG3_GPIO_MSG_MASK << shift);
2790 status |= (newstat << shift);
2792 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2793 tg3_asic_rev(tp) == ASIC_REV_5719)
2794 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2796 tw32(TG3_CPMU_DRV_STATUS, status);
2798 return status >> TG3_APE_GPIO_MSG_SHIFT;
2801 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2803 if (!tg3_flag(tp, IS_NIC))
2806 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2807 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2808 tg3_asic_rev(tp) == ASIC_REV_5720) {
2809 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2812 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2814 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2815 TG3_GRC_LCLCTL_PWRSW_DELAY);
2817 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2819 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2820 TG3_GRC_LCLCTL_PWRSW_DELAY);
2826 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2830 if (!tg3_flag(tp, IS_NIC) ||
2831 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2832 tg3_asic_rev(tp) == ASIC_REV_5701)
2835 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2837 tw32_wait_f(GRC_LOCAL_CTRL,
2838 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2839 TG3_GRC_LCLCTL_PWRSW_DELAY);
2841 tw32_wait_f(GRC_LOCAL_CTRL,
2843 TG3_GRC_LCLCTL_PWRSW_DELAY);
2845 tw32_wait_f(GRC_LOCAL_CTRL,
2846 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2847 TG3_GRC_LCLCTL_PWRSW_DELAY);
2850 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2852 if (!tg3_flag(tp, IS_NIC))
2855 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2856 tg3_asic_rev(tp) == ASIC_REV_5701) {
2857 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2858 (GRC_LCLCTRL_GPIO_OE0 |
2859 GRC_LCLCTRL_GPIO_OE1 |
2860 GRC_LCLCTRL_GPIO_OE2 |
2861 GRC_LCLCTRL_GPIO_OUTPUT0 |
2862 GRC_LCLCTRL_GPIO_OUTPUT1),
2863 TG3_GRC_LCLCTL_PWRSW_DELAY);
2864 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2865 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2866 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2867 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2868 GRC_LCLCTRL_GPIO_OE1 |
2869 GRC_LCLCTRL_GPIO_OE2 |
2870 GRC_LCLCTRL_GPIO_OUTPUT0 |
2871 GRC_LCLCTRL_GPIO_OUTPUT1 |
2873 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2876 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2877 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2878 TG3_GRC_LCLCTL_PWRSW_DELAY);
2880 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2881 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2882 TG3_GRC_LCLCTL_PWRSW_DELAY);
2885 u32 grc_local_ctrl = 0;
2887 /* Workaround to prevent overdrawing Amps. */
2888 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2889 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2890 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2892 TG3_GRC_LCLCTL_PWRSW_DELAY);
2895 /* On 5753 and variants, GPIO2 cannot be used. */
2896 no_gpio2 = tp->nic_sram_data_cfg &
2897 NIC_SRAM_DATA_CFG_NO_GPIO2;
2899 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2900 GRC_LCLCTRL_GPIO_OE1 |
2901 GRC_LCLCTRL_GPIO_OE2 |
2902 GRC_LCLCTRL_GPIO_OUTPUT1 |
2903 GRC_LCLCTRL_GPIO_OUTPUT2;
2905 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2906 GRC_LCLCTRL_GPIO_OUTPUT2);
2908 tw32_wait_f(GRC_LOCAL_CTRL,
2909 tp->grc_local_ctrl | grc_local_ctrl,
2910 TG3_GRC_LCLCTL_PWRSW_DELAY);
2912 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2914 tw32_wait_f(GRC_LOCAL_CTRL,
2915 tp->grc_local_ctrl | grc_local_ctrl,
2916 TG3_GRC_LCLCTL_PWRSW_DELAY);
2919 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2920 tw32_wait_f(GRC_LOCAL_CTRL,
2921 tp->grc_local_ctrl | grc_local_ctrl,
2922 TG3_GRC_LCLCTL_PWRSW_DELAY);
2927 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2931 /* Serialize power state transitions */
2932 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2935 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2936 msg = TG3_GPIO_MSG_NEED_VAUX;
2938 msg = tg3_set_function_status(tp, msg);
2940 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2943 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2944 tg3_pwrsrc_switch_to_vaux(tp);
2946 tg3_pwrsrc_die_with_vmain(tp);
2949 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2952 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2954 bool need_vaux = false;
2956 /* The GPIOs do something completely different on 57765. */
2957 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2960 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2961 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2962 tg3_asic_rev(tp) == ASIC_REV_5720) {
2963 tg3_frob_aux_power_5717(tp, include_wol ?
2964 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2968 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2969 struct net_device *dev_peer;
2971 dev_peer = pci_get_drvdata(tp->pdev_peer);
2973 /* remove_one() may have been run on the peer. */
2975 struct tg3 *tp_peer = netdev_priv(dev_peer);
2977 if (tg3_flag(tp_peer, INIT_COMPLETE))
2980 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2981 tg3_flag(tp_peer, ENABLE_ASF))
2986 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2987 tg3_flag(tp, ENABLE_ASF))
2991 tg3_pwrsrc_switch_to_vaux(tp);
2993 tg3_pwrsrc_die_with_vmain(tp);
2996 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2998 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3000 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3001 if (speed != SPEED_10)
3003 } else if (speed == SPEED_10)
3009 static bool tg3_phy_power_bug(struct tg3 *tp)
3011 switch (tg3_asic_rev(tp)) {
3016 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3025 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3034 static bool tg3_phy_led_bug(struct tg3 *tp)
3036 switch (tg3_asic_rev(tp)) {
3039 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3048 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3052 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3055 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3056 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3057 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3058 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3061 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3062 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3063 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3068 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3070 val = tr32(GRC_MISC_CFG);
3071 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3074 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3076 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3079 tg3_writephy(tp, MII_ADVERTISE, 0);
3080 tg3_writephy(tp, MII_BMCR,
3081 BMCR_ANENABLE | BMCR_ANRESTART);
3083 tg3_writephy(tp, MII_TG3_FET_TEST,
3084 phytest | MII_TG3_FET_SHADOW_EN);
3085 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3086 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3088 MII_TG3_FET_SHDW_AUXMODE4,
3091 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3094 } else if (do_low_power) {
3095 if (!tg3_phy_led_bug(tp))
3096 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3097 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3099 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3100 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3101 MII_TG3_AUXCTL_PCTL_VREG_11V;
3102 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3105 /* The PHY should not be powered down on some chips because
3108 if (tg3_phy_power_bug(tp))
3111 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3112 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3113 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3114 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3115 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3116 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3119 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3122 /* tp->lock is held. */
3123 static int tg3_nvram_lock(struct tg3 *tp)
3125 if (tg3_flag(tp, NVRAM)) {
3128 if (tp->nvram_lock_cnt == 0) {
3129 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3130 for (i = 0; i < 8000; i++) {
3131 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3136 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3140 tp->nvram_lock_cnt++;
3145 /* tp->lock is held. */
3146 static void tg3_nvram_unlock(struct tg3 *tp)
3148 if (tg3_flag(tp, NVRAM)) {
3149 if (tp->nvram_lock_cnt > 0)
3150 tp->nvram_lock_cnt--;
3151 if (tp->nvram_lock_cnt == 0)
3152 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3156 /* tp->lock is held. */
3157 static void tg3_enable_nvram_access(struct tg3 *tp)
3159 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3160 u32 nvaccess = tr32(NVRAM_ACCESS);
3162 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3166 /* tp->lock is held. */
3167 static void tg3_disable_nvram_access(struct tg3 *tp)
3169 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3170 u32 nvaccess = tr32(NVRAM_ACCESS);
3172 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3176 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3177 u32 offset, u32 *val)
3182 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3185 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3186 EEPROM_ADDR_DEVID_MASK |
3188 tw32(GRC_EEPROM_ADDR,
3190 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3191 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3192 EEPROM_ADDR_ADDR_MASK) |
3193 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3195 for (i = 0; i < 1000; i++) {
3196 tmp = tr32(GRC_EEPROM_ADDR);
3198 if (tmp & EEPROM_ADDR_COMPLETE)
3202 if (!(tmp & EEPROM_ADDR_COMPLETE))
3205 tmp = tr32(GRC_EEPROM_DATA);
3208 * The data will always be opposite the native endian
3209 * format. Perform a blind byteswap to compensate.
3216 #define NVRAM_CMD_TIMEOUT 10000
3218 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3222 tw32(NVRAM_CMD, nvram_cmd);
3223 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3224 usleep_range(10, 40);
3225 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3231 if (i == NVRAM_CMD_TIMEOUT)
3237 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3239 if (tg3_flag(tp, NVRAM) &&
3240 tg3_flag(tp, NVRAM_BUFFERED) &&
3241 tg3_flag(tp, FLASH) &&
3242 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3243 (tp->nvram_jedecnum == JEDEC_ATMEL))
3245 addr = ((addr / tp->nvram_pagesize) <<
3246 ATMEL_AT45DB0X1B_PAGE_POS) +
3247 (addr % tp->nvram_pagesize);
3252 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3254 if (tg3_flag(tp, NVRAM) &&
3255 tg3_flag(tp, NVRAM_BUFFERED) &&
3256 tg3_flag(tp, FLASH) &&
3257 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3258 (tp->nvram_jedecnum == JEDEC_ATMEL))
3260 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3261 tp->nvram_pagesize) +
3262 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3267 /* NOTE: Data read in from NVRAM is byteswapped according to
3268 * the byteswapping settings for all other register accesses.
3269 * tg3 devices are BE devices, so on a BE machine, the data
3270 * returned will be exactly as it is seen in NVRAM. On a LE
3271 * machine, the 32-bit value will be byteswapped.
3273 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3277 if (!tg3_flag(tp, NVRAM))
3278 return tg3_nvram_read_using_eeprom(tp, offset, val);
3280 offset = tg3_nvram_phys_addr(tp, offset);
3282 if (offset > NVRAM_ADDR_MSK)
3285 ret = tg3_nvram_lock(tp);
3289 tg3_enable_nvram_access(tp);
3291 tw32(NVRAM_ADDR, offset);
3292 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3293 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3296 *val = tr32(NVRAM_RDDATA);
3298 tg3_disable_nvram_access(tp);
3300 tg3_nvram_unlock(tp);
3305 /* Ensures NVRAM data is in bytestream format. */
3306 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3309 int res = tg3_nvram_read(tp, offset, &v);
3311 *val = cpu_to_be32(v);
3315 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3316 u32 offset, u32 len, u8 *buf)
3321 for (i = 0; i < len; i += 4) {
3327 memcpy(&data, buf + i, 4);
3330 * The SEEPROM interface expects the data to always be opposite
3331 * the native endian format. We accomplish this by reversing
3332 * all the operations that would have been performed on the
3333 * data from a call to tg3_nvram_read_be32().
3335 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3337 val = tr32(GRC_EEPROM_ADDR);
3338 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3340 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3342 tw32(GRC_EEPROM_ADDR, val |
3343 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3344 (addr & EEPROM_ADDR_ADDR_MASK) |
3348 for (j = 0; j < 1000; j++) {
3349 val = tr32(GRC_EEPROM_ADDR);
3351 if (val & EEPROM_ADDR_COMPLETE)
3355 if (!(val & EEPROM_ADDR_COMPLETE)) {
3364 /* offset and length are dword aligned */
3365 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3369 u32 pagesize = tp->nvram_pagesize;
3370 u32 pagemask = pagesize - 1;
3374 tmp = kmalloc(pagesize, GFP_KERNEL);
3380 u32 phy_addr, page_off, size;
3382 phy_addr = offset & ~pagemask;
3384 for (j = 0; j < pagesize; j += 4) {
3385 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3386 (__be32 *) (tmp + j));
3393 page_off = offset & pagemask;
3400 memcpy(tmp + page_off, buf, size);
3402 offset = offset + (pagesize - page_off);
3404 tg3_enable_nvram_access(tp);
3407 * Before we can erase the flash page, we need
3408 * to issue a special "write enable" command.
3410 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3412 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3415 /* Erase the target page */
3416 tw32(NVRAM_ADDR, phy_addr);
3418 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3419 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3421 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3424 /* Issue another write enable to start the write. */
3425 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3427 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3430 for (j = 0; j < pagesize; j += 4) {
3433 data = *((__be32 *) (tmp + j));
3435 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3437 tw32(NVRAM_ADDR, phy_addr + j);
3439 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3443 nvram_cmd |= NVRAM_CMD_FIRST;
3444 else if (j == (pagesize - 4))
3445 nvram_cmd |= NVRAM_CMD_LAST;
3447 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3455 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3456 tg3_nvram_exec_cmd(tp, nvram_cmd);
3463 /* offset and length are dword aligned */
3464 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3469 for (i = 0; i < len; i += 4, offset += 4) {
3470 u32 page_off, phy_addr, nvram_cmd;
3473 memcpy(&data, buf + i, 4);
3474 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3476 page_off = offset % tp->nvram_pagesize;
3478 phy_addr = tg3_nvram_phys_addr(tp, offset);
3480 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3482 if (page_off == 0 || i == 0)
3483 nvram_cmd |= NVRAM_CMD_FIRST;
3484 if (page_off == (tp->nvram_pagesize - 4))
3485 nvram_cmd |= NVRAM_CMD_LAST;
3488 nvram_cmd |= NVRAM_CMD_LAST;
3490 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3491 !tg3_flag(tp, FLASH) ||
3492 !tg3_flag(tp, 57765_PLUS))
3493 tw32(NVRAM_ADDR, phy_addr);
3495 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3496 !tg3_flag(tp, 5755_PLUS) &&
3497 (tp->nvram_jedecnum == JEDEC_ST) &&
3498 (nvram_cmd & NVRAM_CMD_FIRST)) {
3501 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3502 ret = tg3_nvram_exec_cmd(tp, cmd);
3506 if (!tg3_flag(tp, FLASH)) {
3507 /* We always do complete word writes to eeprom. */
3508 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3511 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3518 /* offset and length are dword aligned */
3519 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3523 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3524 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3525 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3529 if (!tg3_flag(tp, NVRAM)) {
3530 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3534 ret = tg3_nvram_lock(tp);
3538 tg3_enable_nvram_access(tp);
3539 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3540 tw32(NVRAM_WRITE1, 0x406);
3542 grc_mode = tr32(GRC_MODE);
3543 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3545 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3546 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3549 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3556 tg3_disable_nvram_access(tp);
3557 tg3_nvram_unlock(tp);
3560 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3561 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3568 #define RX_CPU_SCRATCH_BASE 0x30000
3569 #define RX_CPU_SCRATCH_SIZE 0x04000
3570 #define TX_CPU_SCRATCH_BASE 0x34000
3571 #define TX_CPU_SCRATCH_SIZE 0x04000
3573 /* tp->lock is held. */
3574 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3577 const int iters = 10000;
3579 for (i = 0; i < iters; i++) {
3580 tw32(cpu_base + CPU_STATE, 0xffffffff);
3581 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3582 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3584 if (pci_channel_offline(tp->pdev))
3588 return (i == iters) ? -EBUSY : 0;
3591 /* tp->lock is held. */
3592 static int tg3_rxcpu_pause(struct tg3 *tp)
3594 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3596 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3597 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3603 /* tp->lock is held. */
3604 static int tg3_txcpu_pause(struct tg3 *tp)
3606 return tg3_pause_cpu(tp, TX_CPU_BASE);
3609 /* tp->lock is held. */
3610 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3612 tw32(cpu_base + CPU_STATE, 0xffffffff);
3613 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3616 /* tp->lock is held. */
3617 static void tg3_rxcpu_resume(struct tg3 *tp)
3619 tg3_resume_cpu(tp, RX_CPU_BASE);
3622 /* tp->lock is held. */
3623 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3627 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3629 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3630 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3632 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3635 if (cpu_base == RX_CPU_BASE) {
3636 rc = tg3_rxcpu_pause(tp);
3639 * There is only an Rx CPU for the 5750 derivative in the
3642 if (tg3_flag(tp, IS_SSB_CORE))
3645 rc = tg3_txcpu_pause(tp);
3649 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3650 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3654 /* Clear firmware's nvram arbitration. */
3655 if (tg3_flag(tp, NVRAM))
3656 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3660 static int tg3_fw_data_len(struct tg3 *tp,
3661 const struct tg3_firmware_hdr *fw_hdr)
3665 /* Non fragmented firmware have one firmware header followed by a
3666 * contiguous chunk of data to be written. The length field in that
3667 * header is not the length of data to be written but the complete
3668 * length of the bss. The data length is determined based on
3669 * tp->fw->size minus headers.
3671 * Fragmented firmware have a main header followed by multiple
3672 * fragments. Each fragment is identical to non fragmented firmware
3673 * with a firmware header followed by a contiguous chunk of data. In
3674 * the main header, the length field is unused and set to 0xffffffff.
3675 * In each fragment header the length is the entire size of that
3676 * fragment i.e. fragment data + header length. Data length is
3677 * therefore length field in the header minus TG3_FW_HDR_LEN.
3679 if (tp->fw_len == 0xffffffff)
3680 fw_len = be32_to_cpu(fw_hdr->len);
3682 fw_len = tp->fw->size;
3684 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3687 /* tp->lock is held. */
3688 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3689 u32 cpu_scratch_base, int cpu_scratch_size,
3690 const struct tg3_firmware_hdr *fw_hdr)
3693 void (*write_op)(struct tg3 *, u32, u32);
3694 int total_len = tp->fw->size;
3696 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3698 "%s: Trying to load TX cpu firmware which is 5705\n",
3703 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3704 write_op = tg3_write_mem;
3706 write_op = tg3_write_indirect_reg32;
3708 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3709 /* It is possible that bootcode is still loading at this point.
3710 * Get the nvram lock first before halting the cpu.
3712 int lock_err = tg3_nvram_lock(tp);
3713 err = tg3_halt_cpu(tp, cpu_base);
3715 tg3_nvram_unlock(tp);
3719 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3720 write_op(tp, cpu_scratch_base + i, 0);
3721 tw32(cpu_base + CPU_STATE, 0xffffffff);
3722 tw32(cpu_base + CPU_MODE,
3723 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3725 /* Subtract additional main header for fragmented firmware and
3726 * advance to the first fragment
3728 total_len -= TG3_FW_HDR_LEN;
3733 u32 *fw_data = (u32 *)(fw_hdr + 1);
3734 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3735 write_op(tp, cpu_scratch_base +
3736 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3738 be32_to_cpu(fw_data[i]));
3740 total_len -= be32_to_cpu(fw_hdr->len);
3742 /* Advance to next fragment */
3743 fw_hdr = (struct tg3_firmware_hdr *)
3744 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3745 } while (total_len > 0);
3753 /* tp->lock is held. */
3754 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3757 const int iters = 5;
3759 tw32(cpu_base + CPU_STATE, 0xffffffff);
3760 tw32_f(cpu_base + CPU_PC, pc);
3762 for (i = 0; i < iters; i++) {
3763 if (tr32(cpu_base + CPU_PC) == pc)
3765 tw32(cpu_base + CPU_STATE, 0xffffffff);
3766 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3767 tw32_f(cpu_base + CPU_PC, pc);
3771 return (i == iters) ? -EBUSY : 0;
3774 /* tp->lock is held. */
3775 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3777 const struct tg3_firmware_hdr *fw_hdr;
3780 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3782 /* Firmware blob starts with version numbers, followed by
3783 start address and length. We are setting complete length.
3784 length = end_address_of_bss - start_address_of_text.
3785 Remainder is the blob to be loaded contiguously
3786 from start address. */
3788 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3789 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3794 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3795 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3800 /* Now startup only the RX cpu. */
3801 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3802 be32_to_cpu(fw_hdr->base_addr));
3804 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3805 "should be %08x\n", __func__,
3806 tr32(RX_CPU_BASE + CPU_PC),
3807 be32_to_cpu(fw_hdr->base_addr));
3811 tg3_rxcpu_resume(tp);
3816 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3818 const int iters = 1000;
3822 /* Wait for boot code to complete initialization and enter service
3823 * loop. It is then safe to download service patches
3825 for (i = 0; i < iters; i++) {
3826 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3833 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3837 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3839 netdev_warn(tp->dev,
3840 "Other patches exist. Not downloading EEE patch\n");
3847 /* tp->lock is held. */
3848 static void tg3_load_57766_firmware(struct tg3 *tp)
3850 struct tg3_firmware_hdr *fw_hdr;
3852 if (!tg3_flag(tp, NO_NVRAM))
3855 if (tg3_validate_rxcpu_state(tp))
3861 /* This firmware blob has a different format than older firmware
3862 * releases as given below. The main difference is we have fragmented
3863 * data to be written to non-contiguous locations.
3865 * In the beginning we have a firmware header identical to other
3866 * firmware which consists of version, base addr and length. The length
3867 * here is unused and set to 0xffffffff.
3869 * This is followed by a series of firmware fragments which are
3870 * individually identical to previous firmware. i.e. they have the
3871 * firmware header and followed by data for that fragment. The version
3872 * field of the individual fragment header is unused.
3875 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3876 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3879 if (tg3_rxcpu_pause(tp))
3882 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3883 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3885 tg3_rxcpu_resume(tp);
3888 /* tp->lock is held. */
3889 static int tg3_load_tso_firmware(struct tg3 *tp)
3891 const struct tg3_firmware_hdr *fw_hdr;
3892 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3895 if (!tg3_flag(tp, FW_TSO))
3898 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3900 /* Firmware blob starts with version numbers, followed by
3901 start address and length. We are setting complete length.
3902 length = end_address_of_bss - start_address_of_text.
3903 Remainder is the blob to be loaded contiguously
3904 from start address. */
3906 cpu_scratch_size = tp->fw_len;
3908 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3909 cpu_base = RX_CPU_BASE;
3910 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3912 cpu_base = TX_CPU_BASE;
3913 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3914 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3917 err = tg3_load_firmware_cpu(tp, cpu_base,
3918 cpu_scratch_base, cpu_scratch_size,
3923 /* Now startup the cpu. */
3924 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3925 be32_to_cpu(fw_hdr->base_addr));
3928 "%s fails to set CPU PC, is %08x should be %08x\n",
3929 __func__, tr32(cpu_base + CPU_PC),
3930 be32_to_cpu(fw_hdr->base_addr));
3934 tg3_resume_cpu(tp, cpu_base);
3938 /* tp->lock is held. */
3939 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3941 u32 addr_high, addr_low;
3943 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3944 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3945 (mac_addr[4] << 8) | mac_addr[5]);
3948 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3949 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3952 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3953 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3957 /* tp->lock is held. */
3958 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3963 for (i = 0; i < 4; i++) {
3964 if (i == 1 && skip_mac_1)
3966 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3969 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3970 tg3_asic_rev(tp) == ASIC_REV_5704) {
3971 for (i = 4; i < 16; i++)
3972 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3975 addr_high = (tp->dev->dev_addr[0] +
3976 tp->dev->dev_addr[1] +
3977 tp->dev->dev_addr[2] +
3978 tp->dev->dev_addr[3] +
3979 tp->dev->dev_addr[4] +
3980 tp->dev->dev_addr[5]) &
3981 TX_BACKOFF_SEED_MASK;
3982 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3985 static void tg3_enable_register_access(struct tg3 *tp)
3988 * Make sure register accesses (indirect or otherwise) will function
3991 pci_write_config_dword(tp->pdev,
3992 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3995 static int tg3_power_up(struct tg3 *tp)
3999 tg3_enable_register_access(tp);
4001 err = pci_set_power_state(tp->pdev, PCI_D0);
4003 /* Switch out of Vaux if it is a NIC */
4004 tg3_pwrsrc_switch_to_vmain(tp);
4006 netdev_err(tp->dev, "Transition to D0 failed\n");
4012 static int tg3_setup_phy(struct tg3 *, bool);
4014 static int tg3_power_down_prepare(struct tg3 *tp)
4017 bool device_should_wake, do_low_power;
4019 tg3_enable_register_access(tp);
4021 /* Restore the CLKREQ setting. */
4022 if (tg3_flag(tp, CLKREQ_BUG))
4023 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4024 PCI_EXP_LNKCTL_CLKREQ_EN);
4026 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4027 tw32(TG3PCI_MISC_HOST_CTRL,
4028 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4030 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4031 tg3_flag(tp, WOL_ENABLE);
4033 if (tg3_flag(tp, USE_PHYLIB)) {
4034 do_low_power = false;
4035 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4036 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4037 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
4038 struct phy_device *phydev;
4041 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4043 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4045 tp->link_config.speed = phydev->speed;
4046 tp->link_config.duplex = phydev->duplex;
4047 tp->link_config.autoneg = phydev->autoneg;
4048 ethtool_convert_link_mode_to_legacy_u32(
4049 &tp->link_config.advertising,
4050 phydev->advertising);
4052 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, advertising);
4053 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
4055 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
4057 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
4060 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4061 if (tg3_flag(tp, WOL_SPEED_100MB)) {
4062 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
4064 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
4066 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4069 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4074 linkmode_copy(phydev->advertising, advertising);
4075 phy_start_aneg(phydev);
4077 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4078 if (phyid != PHY_ID_BCMAC131) {
4079 phyid &= PHY_BCM_OUI_MASK;
4080 if (phyid == PHY_BCM_OUI_1 ||
4081 phyid == PHY_BCM_OUI_2 ||
4082 phyid == PHY_BCM_OUI_3)
4083 do_low_power = true;
4087 do_low_power = true;
4089 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4090 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4092 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4093 tg3_setup_phy(tp, false);
4096 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4099 val = tr32(GRC_VCPU_EXT_CTRL);
4100 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4101 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4105 for (i = 0; i < 200; i++) {
4106 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4107 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4112 if (tg3_flag(tp, WOL_CAP))
4113 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4114 WOL_DRV_STATE_SHUTDOWN |
4118 if (device_should_wake) {
4121 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4123 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4124 tg3_phy_auxctl_write(tp,
4125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4126 MII_TG3_AUXCTL_PCTL_WOL_EN |
4127 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4128 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4132 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4133 mac_mode = MAC_MODE_PORT_MODE_GMII;
4134 else if (tp->phy_flags &
4135 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4136 if (tp->link_config.active_speed == SPEED_1000)
4137 mac_mode = MAC_MODE_PORT_MODE_GMII;
4139 mac_mode = MAC_MODE_PORT_MODE_MII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4144 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4145 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4146 SPEED_100 : SPEED_10;
4147 if (tg3_5700_link_polarity(tp, speed))
4148 mac_mode |= MAC_MODE_LINK_POLARITY;
4150 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4153 mac_mode = MAC_MODE_PORT_MODE_TBI;
4156 if (!tg3_flag(tp, 5750_PLUS))
4157 tw32(MAC_LED_CTRL, tp->led_ctrl);
4159 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4160 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4161 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4162 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4164 if (tg3_flag(tp, ENABLE_APE))
4165 mac_mode |= MAC_MODE_APE_TX_EN |
4166 MAC_MODE_APE_RX_EN |
4167 MAC_MODE_TDE_ENABLE;
4169 tw32_f(MAC_MODE, mac_mode);
4172 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4176 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4177 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4178 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4181 base_val = tp->pci_clock_ctrl;
4182 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4183 CLOCK_CTRL_TXCLK_DISABLE);
4185 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4186 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4187 } else if (tg3_flag(tp, 5780_CLASS) ||
4188 tg3_flag(tp, CPMU_PRESENT) ||
4189 tg3_asic_rev(tp) == ASIC_REV_5906) {
4191 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4192 u32 newbits1, newbits2;
4194 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4195 tg3_asic_rev(tp) == ASIC_REV_5701) {
4196 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4197 CLOCK_CTRL_TXCLK_DISABLE |
4199 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4200 } else if (tg3_flag(tp, 5705_PLUS)) {
4201 newbits1 = CLOCK_CTRL_625_CORE;
4202 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4204 newbits1 = CLOCK_CTRL_ALTCLK;
4205 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4211 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4214 if (!tg3_flag(tp, 5705_PLUS)) {
4217 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4218 tg3_asic_rev(tp) == ASIC_REV_5701) {
4219 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4220 CLOCK_CTRL_TXCLK_DISABLE |
4221 CLOCK_CTRL_44MHZ_CORE);
4223 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4226 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4227 tp->pci_clock_ctrl | newbits3, 40);
4231 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4232 tg3_power_down_phy(tp, do_low_power);
4234 tg3_frob_aux_power(tp, true);
4236 /* Workaround for unstable PLL clock */
4237 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4238 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4239 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4240 u32 val = tr32(0x7d00);
4242 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4244 if (!tg3_flag(tp, ENABLE_ASF)) {
4247 err = tg3_nvram_lock(tp);
4248 tg3_halt_cpu(tp, RX_CPU_BASE);
4250 tg3_nvram_unlock(tp);
4254 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4256 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4261 static void tg3_power_down(struct tg3 *tp)
4263 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4264 pci_set_power_state(tp->pdev, PCI_D3hot);
4267 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
4269 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4270 case MII_TG3_AUX_STAT_10HALF:
4272 *duplex = DUPLEX_HALF;
4275 case MII_TG3_AUX_STAT_10FULL:
4277 *duplex = DUPLEX_FULL;
4280 case MII_TG3_AUX_STAT_100HALF:
4282 *duplex = DUPLEX_HALF;
4285 case MII_TG3_AUX_STAT_100FULL:
4287 *duplex = DUPLEX_FULL;
4290 case MII_TG3_AUX_STAT_1000HALF:
4291 *speed = SPEED_1000;
4292 *duplex = DUPLEX_HALF;
4295 case MII_TG3_AUX_STAT_1000FULL:
4296 *speed = SPEED_1000;
4297 *duplex = DUPLEX_FULL;
4301 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4302 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4304 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4308 *speed = SPEED_UNKNOWN;
4309 *duplex = DUPLEX_UNKNOWN;
4314 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4319 new_adv = ADVERTISE_CSMA;
4320 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4321 new_adv |= mii_advertise_flowctrl(flowctrl);
4323 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4327 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4328 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4330 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4331 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4332 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4334 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4339 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4342 tw32(TG3_CPMU_EEE_MODE,
4343 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4345 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4350 /* Advertise 100-BaseTX EEE ability */
4351 if (advertise & ADVERTISED_100baseT_Full)
4352 val |= MDIO_AN_EEE_ADV_100TX;
4353 /* Advertise 1000-BaseT EEE ability */
4354 if (advertise & ADVERTISED_1000baseT_Full)
4355 val |= MDIO_AN_EEE_ADV_1000T;
4357 if (!tp->eee.eee_enabled) {
4359 tp->eee.advertised = 0;
4361 tp->eee.advertised = advertise &
4362 (ADVERTISED_100baseT_Full |
4363 ADVERTISED_1000baseT_Full);
4366 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4370 switch (tg3_asic_rev(tp)) {
4372 case ASIC_REV_57765:
4373 case ASIC_REV_57766:
4375 /* If we advertised any eee advertisements above... */
4377 val = MII_TG3_DSP_TAP26_ALNOKO |
4378 MII_TG3_DSP_TAP26_RMRXSTO |
4379 MII_TG3_DSP_TAP26_OPCSINPT;
4380 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4384 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4385 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4386 MII_TG3_DSP_CH34TP2_HIBW01);
4389 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4398 static void tg3_phy_copper_begin(struct tg3 *tp)
4400 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4401 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4404 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4405 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4406 adv = ADVERTISED_10baseT_Half |
4407 ADVERTISED_10baseT_Full;
4408 if (tg3_flag(tp, WOL_SPEED_100MB))
4409 adv |= ADVERTISED_100baseT_Half |
4410 ADVERTISED_100baseT_Full;
4411 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4412 if (!(tp->phy_flags &
4413 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4414 adv |= ADVERTISED_1000baseT_Half;
4415 adv |= ADVERTISED_1000baseT_Full;
4418 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4420 adv = tp->link_config.advertising;
4421 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4422 adv &= ~(ADVERTISED_1000baseT_Half |
4423 ADVERTISED_1000baseT_Full);
4425 fc = tp->link_config.flowctrl;
4428 tg3_phy_autoneg_cfg(tp, adv, fc);
4430 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4431 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4432 /* Normally during power down we want to autonegotiate
4433 * the lowest possible speed for WOL. However, to avoid
4434 * link flap, we leave it untouched.
4439 tg3_writephy(tp, MII_BMCR,
4440 BMCR_ANENABLE | BMCR_ANRESTART);
4443 u32 bmcr, orig_bmcr;
4445 tp->link_config.active_speed = tp->link_config.speed;
4446 tp->link_config.active_duplex = tp->link_config.duplex;
4448 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4449 /* With autoneg disabled, 5715 only links up when the
4450 * advertisement register has the configured speed
4453 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4457 switch (tp->link_config.speed) {
4463 bmcr |= BMCR_SPEED100;
4467 bmcr |= BMCR_SPEED1000;
4471 if (tp->link_config.duplex == DUPLEX_FULL)
4472 bmcr |= BMCR_FULLDPLX;
4474 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4475 (bmcr != orig_bmcr)) {
4476 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4477 for (i = 0; i < 1500; i++) {
4481 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4482 tg3_readphy(tp, MII_BMSR, &tmp))
4484 if (!(tmp & BMSR_LSTATUS)) {
4489 tg3_writephy(tp, MII_BMCR, bmcr);
4495 static int tg3_phy_pull_config(struct tg3 *tp)
4500 err = tg3_readphy(tp, MII_BMCR, &val);
4504 if (!(val & BMCR_ANENABLE)) {
4505 tp->link_config.autoneg = AUTONEG_DISABLE;
4506 tp->link_config.advertising = 0;
4507 tg3_flag_clear(tp, PAUSE_AUTONEG);
4511 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4513 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4516 tp->link_config.speed = SPEED_10;
4519 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 tp->link_config.speed = SPEED_100;
4524 case BMCR_SPEED1000:
4525 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4526 tp->link_config.speed = SPEED_1000;
4534 if (val & BMCR_FULLDPLX)
4535 tp->link_config.duplex = DUPLEX_FULL;
4537 tp->link_config.duplex = DUPLEX_HALF;
4539 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4545 tp->link_config.autoneg = AUTONEG_ENABLE;
4546 tp->link_config.advertising = ADVERTISED_Autoneg;
4547 tg3_flag_set(tp, PAUSE_AUTONEG);
4549 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4552 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4556 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4557 tp->link_config.advertising |= adv | ADVERTISED_TP;
4559 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4561 tp->link_config.advertising |= ADVERTISED_FIBRE;
4564 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4568 err = tg3_readphy(tp, MII_CTRL1000, &val);
4572 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4574 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4578 adv = tg3_decode_flowctrl_1000X(val);
4579 tp->link_config.flowctrl = adv;
4581 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4582 adv = mii_adv_to_ethtool_adv_x(val);
4585 tp->link_config.advertising |= adv;
4592 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4596 /* Turn off tap power management. */
4597 /* Set Extended packet length bit */
4598 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4600 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4601 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4602 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4603 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4604 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4611 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4613 struct ethtool_eee eee;
4615 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4618 tg3_eee_pull_config(tp, &eee);
4620 if (tp->eee.eee_enabled) {
4621 if (tp->eee.advertised != eee.advertised ||
4622 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4623 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4626 /* EEE is disabled but we're advertising */
4634 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4636 u32 advmsk, tgtadv, advertising;
4638 advertising = tp->link_config.advertising;
4639 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4641 advmsk = ADVERTISE_ALL;
4642 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4643 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4644 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4647 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4650 if ((*lcladv & advmsk) != tgtadv)
4653 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4656 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4658 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4662 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4663 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4664 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4665 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4666 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4668 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4671 if (tg3_ctrl != tgtadv)
4678 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4682 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4685 if (tg3_readphy(tp, MII_STAT1000, &val))
4688 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4691 if (tg3_readphy(tp, MII_LPA, rmtadv))
4694 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4695 tp->link_config.rmt_adv = lpeth;
4700 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4702 if (curr_link_up != tp->link_up) {
4704 netif_carrier_on(tp->dev);
4706 netif_carrier_off(tp->dev);
4707 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4708 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4711 tg3_link_report(tp);
4718 static void tg3_clear_mac_status(struct tg3 *tp)
4723 MAC_STATUS_SYNC_CHANGED |
4724 MAC_STATUS_CFG_CHANGED |
4725 MAC_STATUS_MI_COMPLETION |
4726 MAC_STATUS_LNKSTATE_CHANGED);
4730 static void tg3_setup_eee(struct tg3 *tp)
4734 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4735 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4736 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4737 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4739 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4741 tw32_f(TG3_CPMU_EEE_CTRL,
4742 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4744 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4745 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4746 TG3_CPMU_EEEMD_LPI_IN_RX |
4747 TG3_CPMU_EEEMD_EEE_ENABLE;
4749 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4750 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4752 if (tg3_flag(tp, ENABLE_APE))
4753 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4755 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4757 tw32_f(TG3_CPMU_EEE_DBTMR1,
4758 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4759 (tp->eee.tx_lpi_timer & 0xffff));
4761 tw32_f(TG3_CPMU_EEE_DBTMR2,
4762 TG3_CPMU_DBTMR2_APE_TX_2047US |
4763 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4766 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4768 bool current_link_up;
4770 u32 lcl_adv, rmt_adv;
4775 tg3_clear_mac_status(tp);
4777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4783 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4785 /* Some third-party PHYs need to be reset on link going
4788 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4789 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4790 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4792 tg3_readphy(tp, MII_BMSR, &bmsr);
4793 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4794 !(bmsr & BMSR_LSTATUS))
4800 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4801 tg3_readphy(tp, MII_BMSR, &bmsr);
4802 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4803 !tg3_flag(tp, INIT_COMPLETE))
4806 if (!(bmsr & BMSR_LSTATUS)) {
4807 err = tg3_init_5401phy_dsp(tp);
4811 tg3_readphy(tp, MII_BMSR, &bmsr);
4812 for (i = 0; i < 1000; i++) {
4814 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4815 (bmsr & BMSR_LSTATUS)) {
4821 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4822 TG3_PHY_REV_BCM5401_B0 &&
4823 !(bmsr & BMSR_LSTATUS) &&
4824 tp->link_config.active_speed == SPEED_1000) {
4825 err = tg3_phy_reset(tp);
4827 err = tg3_init_5401phy_dsp(tp);
4832 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4833 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4834 /* 5701 {A0,B0} CRC bug workaround */
4835 tg3_writephy(tp, 0x15, 0x0a75);
4836 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4837 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4841 /* Clear pending interrupts... */
4842 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4843 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4846 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4847 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4848 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4850 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4851 tg3_asic_rev(tp) == ASIC_REV_5701) {
4852 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4853 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4854 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4856 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4859 current_link_up = false;
4860 current_speed = SPEED_UNKNOWN;
4861 current_duplex = DUPLEX_UNKNOWN;
4862 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4863 tp->link_config.rmt_adv = 0;
4865 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4866 err = tg3_phy_auxctl_read(tp,
4867 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4869 if (!err && !(val & (1 << 10))) {
4870 tg3_phy_auxctl_write(tp,
4871 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4878 for (i = 0; i < 100; i++) {
4879 tg3_readphy(tp, MII_BMSR, &bmsr);
4880 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4881 (bmsr & BMSR_LSTATUS))
4886 if (bmsr & BMSR_LSTATUS) {
4889 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4890 for (i = 0; i < 2000; i++) {
4892 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4897 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4902 for (i = 0; i < 200; i++) {
4903 tg3_readphy(tp, MII_BMCR, &bmcr);
4904 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4906 if (bmcr && bmcr != 0x7fff)
4914 tp->link_config.active_speed = current_speed;
4915 tp->link_config.active_duplex = current_duplex;
4917 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4918 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4920 if ((bmcr & BMCR_ANENABLE) &&
4922 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4923 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4924 current_link_up = true;
4926 /* EEE settings changes take effect only after a phy
4927 * reset. If we have skipped a reset due to Link Flap
4928 * Avoidance being enabled, do it now.
4930 if (!eee_config_ok &&
4931 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4937 if (!(bmcr & BMCR_ANENABLE) &&
4938 tp->link_config.speed == current_speed &&
4939 tp->link_config.duplex == current_duplex) {
4940 current_link_up = true;
4944 if (current_link_up &&
4945 tp->link_config.active_duplex == DUPLEX_FULL) {
4948 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4949 reg = MII_TG3_FET_GEN_STAT;
4950 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4952 reg = MII_TG3_EXT_STAT;
4953 bit = MII_TG3_EXT_STAT_MDIX;
4956 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4957 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4959 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4964 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4965 tg3_phy_copper_begin(tp);
4967 if (tg3_flag(tp, ROBOSWITCH)) {
4968 current_link_up = true;
4969 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4970 current_speed = SPEED_1000;
4971 current_duplex = DUPLEX_FULL;
4972 tp->link_config.active_speed = current_speed;
4973 tp->link_config.active_duplex = current_duplex;
4976 tg3_readphy(tp, MII_BMSR, &bmsr);
4977 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4978 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4979 current_link_up = true;
4982 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4983 if (current_link_up) {
4984 if (tp->link_config.active_speed == SPEED_100 ||
4985 tp->link_config.active_speed == SPEED_10)
4986 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4989 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4994 /* In order for the 5750 core in BCM4785 chip to work properly
4995 * in RGMII mode, the Led Control Register must be set up.
4997 if (tg3_flag(tp, RGMII_MODE)) {
4998 u32 led_ctrl = tr32(MAC_LED_CTRL);
4999 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5001 if (tp->link_config.active_speed == SPEED_10)
5002 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5003 else if (tp->link_config.active_speed == SPEED_100)
5004 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5005 LED_CTRL_100MBPS_ON);
5006 else if (tp->link_config.active_speed == SPEED_1000)
5007 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5008 LED_CTRL_1000MBPS_ON);
5010 tw32(MAC_LED_CTRL, led_ctrl);
5014 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5015 if (tp->link_config.active_duplex == DUPLEX_HALF)
5016 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5018 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5019 if (current_link_up &&
5020 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5021 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5023 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5026 /* ??? Without this setting Netgear GA302T PHY does not
5027 * ??? send/receive packets...
5029 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5030 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5031 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5032 tw32_f(MAC_MI_MODE, tp->mi_mode);
5036 tw32_f(MAC_MODE, tp->mac_mode);
5039 tg3_phy_eee_adjust(tp, current_link_up);
5041 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5042 /* Polled via timer. */
5043 tw32_f(MAC_EVENT, 0);
5045 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5049 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5051 tp->link_config.active_speed == SPEED_1000 &&
5052 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5055 (MAC_STATUS_SYNC_CHANGED |
5056 MAC_STATUS_CFG_CHANGED));
5059 NIC_SRAM_FIRMWARE_MBOX,
5060 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5063 /* Prevent send BD corruption. */
5064 if (tg3_flag(tp, CLKREQ_BUG)) {
5065 if (tp->link_config.active_speed == SPEED_100 ||
5066 tp->link_config.active_speed == SPEED_10)
5067 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5068 PCI_EXP_LNKCTL_CLKREQ_EN);
5070 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5071 PCI_EXP_LNKCTL_CLKREQ_EN);
5074 tg3_test_and_report_link_chg(tp, current_link_up);
5079 struct tg3_fiber_aneginfo {
5081 #define ANEG_STATE_UNKNOWN 0
5082 #define ANEG_STATE_AN_ENABLE 1
5083 #define ANEG_STATE_RESTART_INIT 2
5084 #define ANEG_STATE_RESTART 3
5085 #define ANEG_STATE_DISABLE_LINK_OK 4
5086 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5087 #define ANEG_STATE_ABILITY_DETECT 6
5088 #define ANEG_STATE_ACK_DETECT_INIT 7
5089 #define ANEG_STATE_ACK_DETECT 8
5090 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5091 #define ANEG_STATE_COMPLETE_ACK 10
5092 #define ANEG_STATE_IDLE_DETECT_INIT 11
5093 #define ANEG_STATE_IDLE_DETECT 12
5094 #define ANEG_STATE_LINK_OK 13
5095 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5096 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5099 #define MR_AN_ENABLE 0x00000001
5100 #define MR_RESTART_AN 0x00000002
5101 #define MR_AN_COMPLETE 0x00000004
5102 #define MR_PAGE_RX 0x00000008
5103 #define MR_NP_LOADED 0x00000010
5104 #define MR_TOGGLE_TX 0x00000020
5105 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5106 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5107 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5108 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5109 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5110 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5111 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5112 #define MR_TOGGLE_RX 0x00002000
5113 #define MR_NP_RX 0x00004000
5115 #define MR_LINK_OK 0x80000000
5117 unsigned long link_time, cur_time;
5119 u32 ability_match_cfg;
5120 int ability_match_count;
5122 char ability_match, idle_match, ack_match;
5124 u32 txconfig, rxconfig;
5125 #define ANEG_CFG_NP 0x00000080
5126 #define ANEG_CFG_ACK 0x00000040
5127 #define ANEG_CFG_RF2 0x00000020
5128 #define ANEG_CFG_RF1 0x00000010
5129 #define ANEG_CFG_PS2 0x00000001
5130 #define ANEG_CFG_PS1 0x00008000
5131 #define ANEG_CFG_HD 0x00004000
5132 #define ANEG_CFG_FD 0x00002000
5133 #define ANEG_CFG_INVAL 0x00001f06
5138 #define ANEG_TIMER_ENAB 2
5139 #define ANEG_FAILED -1
5141 #define ANEG_STATE_SETTLE_TIME 10000
5143 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5144 struct tg3_fiber_aneginfo *ap)
5147 unsigned long delta;
5151 if (ap->state == ANEG_STATE_UNKNOWN) {
5155 ap->ability_match_cfg = 0;
5156 ap->ability_match_count = 0;
5157 ap->ability_match = 0;
5163 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5164 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5166 if (rx_cfg_reg != ap->ability_match_cfg) {
5167 ap->ability_match_cfg = rx_cfg_reg;
5168 ap->ability_match = 0;
5169 ap->ability_match_count = 0;
5171 if (++ap->ability_match_count > 1) {
5172 ap->ability_match = 1;
5173 ap->ability_match_cfg = rx_cfg_reg;
5176 if (rx_cfg_reg & ANEG_CFG_ACK)
5184 ap->ability_match_cfg = 0;
5185 ap->ability_match_count = 0;
5186 ap->ability_match = 0;
5192 ap->rxconfig = rx_cfg_reg;
5195 switch (ap->state) {
5196 case ANEG_STATE_UNKNOWN:
5197 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5198 ap->state = ANEG_STATE_AN_ENABLE;
5201 case ANEG_STATE_AN_ENABLE:
5202 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5203 if (ap->flags & MR_AN_ENABLE) {
5206 ap->ability_match_cfg = 0;
5207 ap->ability_match_count = 0;
5208 ap->ability_match = 0;
5212 ap->state = ANEG_STATE_RESTART_INIT;
5214 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5218 case ANEG_STATE_RESTART_INIT:
5219 ap->link_time = ap->cur_time;
5220 ap->flags &= ~(MR_NP_LOADED);
5222 tw32(MAC_TX_AUTO_NEG, 0);
5223 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5224 tw32_f(MAC_MODE, tp->mac_mode);
5227 ret = ANEG_TIMER_ENAB;
5228 ap->state = ANEG_STATE_RESTART;
5231 case ANEG_STATE_RESTART:
5232 delta = ap->cur_time - ap->link_time;
5233 if (delta > ANEG_STATE_SETTLE_TIME)
5234 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5236 ret = ANEG_TIMER_ENAB;
5239 case ANEG_STATE_DISABLE_LINK_OK:
5243 case ANEG_STATE_ABILITY_DETECT_INIT:
5244 ap->flags &= ~(MR_TOGGLE_TX);
5245 ap->txconfig = ANEG_CFG_FD;
5246 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5247 if (flowctrl & ADVERTISE_1000XPAUSE)
5248 ap->txconfig |= ANEG_CFG_PS1;
5249 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5250 ap->txconfig |= ANEG_CFG_PS2;
5251 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5252 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5253 tw32_f(MAC_MODE, tp->mac_mode);
5256 ap->state = ANEG_STATE_ABILITY_DETECT;
5259 case ANEG_STATE_ABILITY_DETECT:
5260 if (ap->ability_match != 0 && ap->rxconfig != 0)
5261 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5264 case ANEG_STATE_ACK_DETECT_INIT:
5265 ap->txconfig |= ANEG_CFG_ACK;
5266 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5267 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5268 tw32_f(MAC_MODE, tp->mac_mode);
5271 ap->state = ANEG_STATE_ACK_DETECT;
5274 case ANEG_STATE_ACK_DETECT:
5275 if (ap->ack_match != 0) {
5276 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5277 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5278 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5280 ap->state = ANEG_STATE_AN_ENABLE;
5282 } else if (ap->ability_match != 0 &&
5283 ap->rxconfig == 0) {
5284 ap->state = ANEG_STATE_AN_ENABLE;
5288 case ANEG_STATE_COMPLETE_ACK_INIT:
5289 if (ap->rxconfig & ANEG_CFG_INVAL) {
5293 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5294 MR_LP_ADV_HALF_DUPLEX |
5295 MR_LP_ADV_SYM_PAUSE |
5296 MR_LP_ADV_ASYM_PAUSE |
5297 MR_LP_ADV_REMOTE_FAULT1 |
5298 MR_LP_ADV_REMOTE_FAULT2 |
5299 MR_LP_ADV_NEXT_PAGE |
5302 if (ap->rxconfig & ANEG_CFG_FD)
5303 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5304 if (ap->rxconfig & ANEG_CFG_HD)
5305 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_PS1)
5307 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5308 if (ap->rxconfig & ANEG_CFG_PS2)
5309 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_RF1)
5311 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5312 if (ap->rxconfig & ANEG_CFG_RF2)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5314 if (ap->rxconfig & ANEG_CFG_NP)
5315 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5317 ap->link_time = ap->cur_time;
5319 ap->flags ^= (MR_TOGGLE_TX);
5320 if (ap->rxconfig & 0x0008)
5321 ap->flags |= MR_TOGGLE_RX;
5322 if (ap->rxconfig & ANEG_CFG_NP)
5323 ap->flags |= MR_NP_RX;
5324 ap->flags |= MR_PAGE_RX;
5326 ap->state = ANEG_STATE_COMPLETE_ACK;
5327 ret = ANEG_TIMER_ENAB;
5330 case ANEG_STATE_COMPLETE_ACK:
5331 if (ap->ability_match != 0 &&
5332 ap->rxconfig == 0) {
5333 ap->state = ANEG_STATE_AN_ENABLE;
5336 delta = ap->cur_time - ap->link_time;
5337 if (delta > ANEG_STATE_SETTLE_TIME) {
5338 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5339 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5341 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5342 !(ap->flags & MR_NP_RX)) {
5343 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5351 case ANEG_STATE_IDLE_DETECT_INIT:
5352 ap->link_time = ap->cur_time;
5353 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5354 tw32_f(MAC_MODE, tp->mac_mode);
5357 ap->state = ANEG_STATE_IDLE_DETECT;
5358 ret = ANEG_TIMER_ENAB;
5361 case ANEG_STATE_IDLE_DETECT:
5362 if (ap->ability_match != 0 &&
5363 ap->rxconfig == 0) {
5364 ap->state = ANEG_STATE_AN_ENABLE;
5367 delta = ap->cur_time - ap->link_time;
5368 if (delta > ANEG_STATE_SETTLE_TIME) {
5369 /* XXX another gem from the Broadcom driver :( */
5370 ap->state = ANEG_STATE_LINK_OK;
5374 case ANEG_STATE_LINK_OK:
5375 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5379 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5380 /* ??? unimplemented */
5383 case ANEG_STATE_NEXT_PAGE_WAIT:
5384 /* ??? unimplemented */
5395 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5398 struct tg3_fiber_aneginfo aninfo;
5399 int status = ANEG_FAILED;
5403 tw32_f(MAC_TX_AUTO_NEG, 0);
5405 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5406 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5409 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5412 memset(&aninfo, 0, sizeof(aninfo));
5413 aninfo.flags |= MR_AN_ENABLE;
5414 aninfo.state = ANEG_STATE_UNKNOWN;
5415 aninfo.cur_time = 0;
5417 while (++tick < 195000) {
5418 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5419 if (status == ANEG_DONE || status == ANEG_FAILED)
5425 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5426 tw32_f(MAC_MODE, tp->mac_mode);
5429 *txflags = aninfo.txconfig;
5430 *rxflags = aninfo.flags;
5432 if (status == ANEG_DONE &&
5433 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5434 MR_LP_ADV_FULL_DUPLEX)))
5440 static void tg3_init_bcm8002(struct tg3 *tp)
5442 u32 mac_status = tr32(MAC_STATUS);
5445 /* Reset when initting first time or we have a link. */
5446 if (tg3_flag(tp, INIT_COMPLETE) &&
5447 !(mac_status & MAC_STATUS_PCS_SYNCED))
5450 /* Set PLL lock range. */
5451 tg3_writephy(tp, 0x16, 0x8007);
5454 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5456 /* Wait for reset to complete. */
5457 /* XXX schedule_timeout() ... */
5458 for (i = 0; i < 500; i++)
5461 /* Config mode; select PMA/Ch 1 regs. */
5462 tg3_writephy(tp, 0x10, 0x8411);
5464 /* Enable auto-lock and comdet, select txclk for tx. */
5465 tg3_writephy(tp, 0x11, 0x0a10);
5467 tg3_writephy(tp, 0x18, 0x00a0);
5468 tg3_writephy(tp, 0x16, 0x41ff);
5470 /* Assert and deassert POR. */
5471 tg3_writephy(tp, 0x13, 0x0400);
5473 tg3_writephy(tp, 0x13, 0x0000);
5475 tg3_writephy(tp, 0x11, 0x0a50);
5477 tg3_writephy(tp, 0x11, 0x0a10);
5479 /* Wait for signal to stabilize */
5480 /* XXX schedule_timeout() ... */
5481 for (i = 0; i < 15000; i++)
5484 /* Deselect the channel register so we can read the PHYID
5487 tg3_writephy(tp, 0x10, 0x8011);
5490 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5493 bool current_link_up;
5494 u32 sg_dig_ctrl, sg_dig_status;
5495 u32 serdes_cfg, expected_sg_dig_ctrl;
5496 int workaround, port_a;
5499 expected_sg_dig_ctrl = 0;
5502 current_link_up = false;
5504 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5505 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5507 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5510 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5511 /* preserve bits 20-23 for voltage regulator */
5512 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5515 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5517 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5518 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5520 u32 val = serdes_cfg;
5526 tw32_f(MAC_SERDES_CFG, val);
5529 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5531 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5532 tg3_setup_flow_control(tp, 0, 0);
5533 current_link_up = true;
5538 /* Want auto-negotiation. */
5539 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5541 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5542 if (flowctrl & ADVERTISE_1000XPAUSE)
5543 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5544 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5545 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5547 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5548 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5549 tp->serdes_counter &&
5550 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5551 MAC_STATUS_RCVD_CFG)) ==
5552 MAC_STATUS_PCS_SYNCED)) {
5553 tp->serdes_counter--;
5554 current_link_up = true;
5559 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5560 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5564 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5565 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5566 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5567 MAC_STATUS_SIGNAL_DET)) {
5568 sg_dig_status = tr32(SG_DIG_STATUS);
5569 mac_status = tr32(MAC_STATUS);
5571 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5572 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5573 u32 local_adv = 0, remote_adv = 0;
5575 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5576 local_adv |= ADVERTISE_1000XPAUSE;
5577 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5578 local_adv |= ADVERTISE_1000XPSE_ASYM;
5580 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5581 remote_adv |= LPA_1000XPAUSE;
5582 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5583 remote_adv |= LPA_1000XPAUSE_ASYM;
5585 tp->link_config.rmt_adv =
5586 mii_adv_to_ethtool_adv_x(remote_adv);
5588 tg3_setup_flow_control(tp, local_adv, remote_adv);
5589 current_link_up = true;
5590 tp->serdes_counter = 0;
5591 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5592 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5593 if (tp->serdes_counter)
5594 tp->serdes_counter--;
5597 u32 val = serdes_cfg;
5604 tw32_f(MAC_SERDES_CFG, val);
5607 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5610 /* Link parallel detection - link is up */
5611 /* only if we have PCS_SYNC and not */
5612 /* receiving config code words */
5613 mac_status = tr32(MAC_STATUS);
5614 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5615 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5616 tg3_setup_flow_control(tp, 0, 0);
5617 current_link_up = true;
5619 TG3_PHYFLG_PARALLEL_DETECT;
5620 tp->serdes_counter =
5621 SERDES_PARALLEL_DET_TIMEOUT;
5623 goto restart_autoneg;
5627 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5628 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5632 return current_link_up;
5635 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5637 bool current_link_up = false;
5639 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5642 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5643 u32 txflags, rxflags;
5646 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5647 u32 local_adv = 0, remote_adv = 0;
5649 if (txflags & ANEG_CFG_PS1)
5650 local_adv |= ADVERTISE_1000XPAUSE;
5651 if (txflags & ANEG_CFG_PS2)
5652 local_adv |= ADVERTISE_1000XPSE_ASYM;
5654 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5655 remote_adv |= LPA_1000XPAUSE;
5656 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE_ASYM;
5659 tp->link_config.rmt_adv =
5660 mii_adv_to_ethtool_adv_x(remote_adv);
5662 tg3_setup_flow_control(tp, local_adv, remote_adv);
5664 current_link_up = true;
5666 for (i = 0; i < 30; i++) {
5669 (MAC_STATUS_SYNC_CHANGED |
5670 MAC_STATUS_CFG_CHANGED));
5672 if ((tr32(MAC_STATUS) &
5673 (MAC_STATUS_SYNC_CHANGED |
5674 MAC_STATUS_CFG_CHANGED)) == 0)
5678 mac_status = tr32(MAC_STATUS);
5679 if (!current_link_up &&
5680 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5681 !(mac_status & MAC_STATUS_RCVD_CFG))
5682 current_link_up = true;
5684 tg3_setup_flow_control(tp, 0, 0);
5686 /* Forcing 1000FD link up. */
5687 current_link_up = true;
5689 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5692 tw32_f(MAC_MODE, tp->mac_mode);
5697 return current_link_up;
5700 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5703 u32 orig_active_speed;
5704 u8 orig_active_duplex;
5706 bool current_link_up;
5709 orig_pause_cfg = tp->link_config.active_flowctrl;
5710 orig_active_speed = tp->link_config.active_speed;
5711 orig_active_duplex = tp->link_config.active_duplex;
5713 if (!tg3_flag(tp, HW_AUTONEG) &&
5715 tg3_flag(tp, INIT_COMPLETE)) {
5716 mac_status = tr32(MAC_STATUS);
5717 mac_status &= (MAC_STATUS_PCS_SYNCED |
5718 MAC_STATUS_SIGNAL_DET |
5719 MAC_STATUS_CFG_CHANGED |
5720 MAC_STATUS_RCVD_CFG);
5721 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5722 MAC_STATUS_SIGNAL_DET)) {
5723 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5724 MAC_STATUS_CFG_CHANGED));
5729 tw32_f(MAC_TX_AUTO_NEG, 0);
5731 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5732 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5733 tw32_f(MAC_MODE, tp->mac_mode);
5736 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5737 tg3_init_bcm8002(tp);
5739 /* Enable link change event even when serdes polling. */
5740 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5743 current_link_up = false;
5744 tp->link_config.rmt_adv = 0;
5745 mac_status = tr32(MAC_STATUS);
5747 if (tg3_flag(tp, HW_AUTONEG))
5748 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5750 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5752 tp->napi[0].hw_status->status =
5753 (SD_STATUS_UPDATED |
5754 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5756 for (i = 0; i < 100; i++) {
5757 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5758 MAC_STATUS_CFG_CHANGED));
5760 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5761 MAC_STATUS_CFG_CHANGED |
5762 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5766 mac_status = tr32(MAC_STATUS);
5767 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5768 current_link_up = false;
5769 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5770 tp->serdes_counter == 0) {
5771 tw32_f(MAC_MODE, (tp->mac_mode |
5772 MAC_MODE_SEND_CONFIGS));
5774 tw32_f(MAC_MODE, tp->mac_mode);
5778 if (current_link_up) {
5779 tp->link_config.active_speed = SPEED_1000;
5780 tp->link_config.active_duplex = DUPLEX_FULL;
5781 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5782 LED_CTRL_LNKLED_OVERRIDE |
5783 LED_CTRL_1000MBPS_ON));
5785 tp->link_config.active_speed = SPEED_UNKNOWN;
5786 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5788 LED_CTRL_LNKLED_OVERRIDE |
5789 LED_CTRL_TRAFFIC_OVERRIDE));
5792 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5793 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5794 if (orig_pause_cfg != now_pause_cfg ||
5795 orig_active_speed != tp->link_config.active_speed ||
5796 orig_active_duplex != tp->link_config.active_duplex)
5797 tg3_link_report(tp);
5803 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5807 u32 current_speed = SPEED_UNKNOWN;
5808 u8 current_duplex = DUPLEX_UNKNOWN;
5809 bool current_link_up = false;
5810 u32 local_adv, remote_adv, sgsr;
5812 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5813 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5814 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5815 (sgsr & SERDES_TG3_SGMII_MODE)) {
5820 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5822 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5823 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5825 current_link_up = true;
5826 if (sgsr & SERDES_TG3_SPEED_1000) {
5827 current_speed = SPEED_1000;
5828 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5829 } else if (sgsr & SERDES_TG3_SPEED_100) {
5830 current_speed = SPEED_100;
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5833 current_speed = SPEED_10;
5834 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5837 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5838 current_duplex = DUPLEX_FULL;
5840 current_duplex = DUPLEX_HALF;
5843 tw32_f(MAC_MODE, tp->mac_mode);
5846 tg3_clear_mac_status(tp);
5848 goto fiber_setup_done;
5851 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5852 tw32_f(MAC_MODE, tp->mac_mode);
5855 tg3_clear_mac_status(tp);
5860 tp->link_config.rmt_adv = 0;
5862 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5863 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5864 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5865 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5866 bmsr |= BMSR_LSTATUS;
5868 bmsr &= ~BMSR_LSTATUS;
5871 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5873 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5874 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5875 /* do nothing, just check for link up at the end */
5876 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5879 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5880 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5881 ADVERTISE_1000XPAUSE |
5882 ADVERTISE_1000XPSE_ASYM |
5885 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5886 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5888 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5889 tg3_writephy(tp, MII_ADVERTISE, newadv);
5890 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5891 tg3_writephy(tp, MII_BMCR, bmcr);
5893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5894 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5895 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5902 bmcr &= ~BMCR_SPEED1000;
5903 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5905 if (tp->link_config.duplex == DUPLEX_FULL)
5906 new_bmcr |= BMCR_FULLDPLX;
5908 if (new_bmcr != bmcr) {
5909 /* BMCR_SPEED1000 is a reserved bit that needs
5910 * to be set on write.
5912 new_bmcr |= BMCR_SPEED1000;
5914 /* Force a linkdown */
5918 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5919 adv &= ~(ADVERTISE_1000XFULL |
5920 ADVERTISE_1000XHALF |
5922 tg3_writephy(tp, MII_ADVERTISE, adv);
5923 tg3_writephy(tp, MII_BMCR, bmcr |
5927 tg3_carrier_off(tp);
5929 tg3_writephy(tp, MII_BMCR, new_bmcr);
5931 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5932 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5933 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5934 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5935 bmsr |= BMSR_LSTATUS;
5937 bmsr &= ~BMSR_LSTATUS;
5939 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5943 if (bmsr & BMSR_LSTATUS) {
5944 current_speed = SPEED_1000;
5945 current_link_up = true;
5946 if (bmcr & BMCR_FULLDPLX)
5947 current_duplex = DUPLEX_FULL;
5949 current_duplex = DUPLEX_HALF;
5954 if (bmcr & BMCR_ANENABLE) {
5957 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5958 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5959 common = local_adv & remote_adv;
5960 if (common & (ADVERTISE_1000XHALF |
5961 ADVERTISE_1000XFULL)) {
5962 if (common & ADVERTISE_1000XFULL)
5963 current_duplex = DUPLEX_FULL;
5965 current_duplex = DUPLEX_HALF;
5967 tp->link_config.rmt_adv =
5968 mii_adv_to_ethtool_adv_x(remote_adv);
5969 } else if (!tg3_flag(tp, 5780_CLASS)) {
5970 /* Link is up via parallel detect */
5972 current_link_up = false;
5978 if (current_link_up && current_duplex == DUPLEX_FULL)
5979 tg3_setup_flow_control(tp, local_adv, remote_adv);
5981 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5982 if (tp->link_config.active_duplex == DUPLEX_HALF)
5983 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5985 tw32_f(MAC_MODE, tp->mac_mode);
5988 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5990 tp->link_config.active_speed = current_speed;
5991 tp->link_config.active_duplex = current_duplex;
5993 tg3_test_and_report_link_chg(tp, current_link_up);
5997 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5999 if (tp->serdes_counter) {
6000 /* Give autoneg time to complete. */
6001 tp->serdes_counter--;
6006 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6009 tg3_readphy(tp, MII_BMCR, &bmcr);
6010 if (bmcr & BMCR_ANENABLE) {
6013 /* Select shadow register 0x1f */
6014 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6015 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6017 /* Select expansion interrupt status register */
6018 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6019 MII_TG3_DSP_EXP1_INT_STAT);
6020 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6021 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6024 /* We have signal detect and not receiving
6025 * config code words, link is up by parallel
6029 bmcr &= ~BMCR_ANENABLE;
6030 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6031 tg3_writephy(tp, MII_BMCR, bmcr);
6032 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6035 } else if (tp->link_up &&
6036 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6037 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6040 /* Select expansion interrupt status register */
6041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6042 MII_TG3_DSP_EXP1_INT_STAT);
6043 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6047 /* Config code words received, turn on autoneg. */
6048 tg3_readphy(tp, MII_BMCR, &bmcr);
6049 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6051 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6057 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6063 err = tg3_setup_fiber_phy(tp, force_reset);
6064 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6065 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6067 err = tg3_setup_copper_phy(tp, force_reset);
6069 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6072 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6073 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6075 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6080 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6081 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6082 tw32(GRC_MISC_CFG, val);
6085 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6086 (6 << TX_LENGTHS_IPG_SHIFT);
6087 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6088 tg3_asic_rev(tp) == ASIC_REV_5762)
6089 val |= tr32(MAC_TX_LENGTHS) &
6090 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6091 TX_LENGTHS_CNT_DWN_VAL_MSK);
6093 if (tp->link_config.active_speed == SPEED_1000 &&
6094 tp->link_config.active_duplex == DUPLEX_HALF)
6095 tw32(MAC_TX_LENGTHS, val |
6096 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6098 tw32(MAC_TX_LENGTHS, val |
6099 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6101 if (!tg3_flag(tp, 5705_PLUS)) {
6103 tw32(HOSTCC_STAT_COAL_TICKS,
6104 tp->coal.stats_block_coalesce_usecs);
6106 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6110 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6111 val = tr32(PCIE_PWR_MGMT_THRESH);
6113 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6116 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6117 tw32(PCIE_PWR_MGMT_THRESH, val);
6123 /* tp->lock must be held */
6124 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts)
6128 ptp_read_system_prets(sts);
6129 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6130 ptp_read_system_postts(sts);
6131 stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6136 /* tp->lock must be held */
6137 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6139 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6141 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6142 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6143 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6144 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6147 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6148 static inline void tg3_full_unlock(struct tg3 *tp);
6149 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6151 struct tg3 *tp = netdev_priv(dev);
6153 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6154 SOF_TIMESTAMPING_RX_SOFTWARE |
6155 SOF_TIMESTAMPING_SOFTWARE;
6157 if (tg3_flag(tp, PTP_CAPABLE)) {
6158 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6159 SOF_TIMESTAMPING_RX_HARDWARE |
6160 SOF_TIMESTAMPING_RAW_HARDWARE;
6164 info->phc_index = ptp_clock_index(tp->ptp_clock);
6166 info->phc_index = -1;
6168 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6170 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6171 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6172 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6173 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6177 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6179 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6180 bool neg_adj = false;
6188 /* Frequency adjustment is performed using hardware with a 24 bit
6189 * accumulator and a programmable correction value. On each clk, the
6190 * correction value gets added to the accumulator and when it
6191 * overflows, the time counter is incremented/decremented.
6193 * So conversion from ppb to correction value is
6194 * ppb * (1 << 24) / 1000000000
6196 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6197 TG3_EAV_REF_CLK_CORRECT_MASK;
6199 tg3_full_lock(tp, 0);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6203 TG3_EAV_REF_CLK_CORRECT_EN |
6204 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6206 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6208 tg3_full_unlock(tp);
6213 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6215 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6217 tg3_full_lock(tp, 0);
6218 tp->ptp_adjust += delta;
6219 tg3_full_unlock(tp);
6224 static int tg3_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
6225 struct ptp_system_timestamp *sts)
6228 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6230 tg3_full_lock(tp, 0);
6231 ns = tg3_refclk_read(tp, sts);
6232 ns += tp->ptp_adjust;
6233 tg3_full_unlock(tp);
6235 *ts = ns_to_timespec64(ns);
6240 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6241 const struct timespec64 *ts)
6244 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6246 ns = timespec64_to_ns(ts);
6248 tg3_full_lock(tp, 0);
6249 tg3_refclk_write(tp, ns);
6251 tg3_full_unlock(tp);
6256 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6257 struct ptp_clock_request *rq, int on)
6259 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6264 case PTP_CLK_REQ_PEROUT:
6265 /* Reject requests with unsupported flags */
6266 if (rq->perout.flags)
6269 if (rq->perout.index != 0)
6272 tg3_full_lock(tp, 0);
6273 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6274 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6279 nsec = rq->perout.start.sec * 1000000000ULL +
6280 rq->perout.start.nsec;
6282 if (rq->perout.period.sec || rq->perout.period.nsec) {
6283 netdev_warn(tp->dev,
6284 "Device supports only a one-shot timesync output, period must be 0\n");
6289 if (nsec & (1ULL << 63)) {
6290 netdev_warn(tp->dev,
6291 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6296 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6297 tw32(TG3_EAV_WATCHDOG0_MSB,
6298 TG3_EAV_WATCHDOG0_EN |
6299 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6301 tw32(TG3_EAV_REF_CLCK_CTL,
6302 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6304 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6305 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6309 tg3_full_unlock(tp);
6319 static const struct ptp_clock_info tg3_ptp_caps = {
6320 .owner = THIS_MODULE,
6321 .name = "tg3 clock",
6322 .max_adj = 250000000,
6328 .adjfreq = tg3_ptp_adjfreq,
6329 .adjtime = tg3_ptp_adjtime,
6330 .gettimex64 = tg3_ptp_gettimex,
6331 .settime64 = tg3_ptp_settime,
6332 .enable = tg3_ptp_enable,
6335 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6336 struct skb_shared_hwtstamps *timestamp)
6338 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6339 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6343 /* tp->lock must be held */
6344 static void tg3_ptp_init(struct tg3 *tp)
6346 if (!tg3_flag(tp, PTP_CAPABLE))
6349 /* Initialize the hardware clock to the system time. */
6350 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6352 tp->ptp_info = tg3_ptp_caps;
6355 /* tp->lock must be held */
6356 static void tg3_ptp_resume(struct tg3 *tp)
6358 if (!tg3_flag(tp, PTP_CAPABLE))
6361 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6365 static void tg3_ptp_fini(struct tg3 *tp)
6367 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6370 ptp_clock_unregister(tp->ptp_clock);
6371 tp->ptp_clock = NULL;
6375 static inline int tg3_irq_sync(struct tg3 *tp)
6377 return tp->irq_sync;
6380 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6384 dst = (u32 *)((u8 *)dst + off);
6385 for (i = 0; i < len; i += sizeof(u32))
6386 *dst++ = tr32(off + i);
6389 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6391 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6392 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6393 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6394 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6395 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6396 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6397 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6398 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6399 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6400 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6402 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6403 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6404 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6405 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6406 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6407 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6408 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6409 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6411 if (tg3_flag(tp, SUPPORT_MSIX))
6412 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6414 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6415 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6416 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6417 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6418 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6420 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6421 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6423 if (!tg3_flag(tp, 5705_PLUS)) {
6424 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6425 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6426 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6429 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6430 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6431 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6432 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6433 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6435 if (tg3_flag(tp, NVRAM))
6436 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6439 static void tg3_dump_state(struct tg3 *tp)
6444 /* If it is a PCI error, all registers will be 0xffff,
6445 * we don't dump them out, just report the error and return
6447 if (tp->pdev->error_state != pci_channel_io_normal) {
6448 netdev_err(tp->dev, "PCI channel ERROR!\n");
6452 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6456 if (tg3_flag(tp, PCI_EXPRESS)) {
6457 /* Read up to but not including private PCI registers */
6458 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6459 regs[i / sizeof(u32)] = tr32(i);
6461 tg3_dump_legacy_regs(tp, regs);
6463 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6464 if (!regs[i + 0] && !regs[i + 1] &&
6465 !regs[i + 2] && !regs[i + 3])
6468 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6470 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6475 for (i = 0; i < tp->irq_cnt; i++) {
6476 struct tg3_napi *tnapi = &tp->napi[i];
6478 /* SW status block */
6480 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6482 tnapi->hw_status->status,
6483 tnapi->hw_status->status_tag,
6484 tnapi->hw_status->rx_jumbo_consumer,
6485 tnapi->hw_status->rx_consumer,
6486 tnapi->hw_status->rx_mini_consumer,
6487 tnapi->hw_status->idx[0].rx_producer,
6488 tnapi->hw_status->idx[0].tx_consumer);
6491 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6493 tnapi->last_tag, tnapi->last_irq_tag,
6494 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6496 tnapi->prodring.rx_std_prod_idx,
6497 tnapi->prodring.rx_std_cons_idx,
6498 tnapi->prodring.rx_jmb_prod_idx,
6499 tnapi->prodring.rx_jmb_cons_idx);
6503 /* This is called whenever we suspect that the system chipset is re-
6504 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6505 * is bogus tx completions. We try to recover by setting the
6506 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6509 static void tg3_tx_recover(struct tg3 *tp)
6511 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6512 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6514 netdev_warn(tp->dev,
6515 "The system may be re-ordering memory-mapped I/O "
6516 "cycles to the network device, attempting to recover. "
6517 "Please report the problem to the driver maintainer "
6518 "and include system chipset information.\n");
6520 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6523 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6525 /* Tell compiler to fetch tx indices from memory. */
6527 return tnapi->tx_pending -
6528 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6531 /* Tigon3 never reports partial packet sends. So we do not
6532 * need special logic to handle SKBs that have not had all
6533 * of their frags sent yet, like SunGEM does.
6535 static void tg3_tx(struct tg3_napi *tnapi)
6537 struct tg3 *tp = tnapi->tp;
6538 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6539 u32 sw_idx = tnapi->tx_cons;
6540 struct netdev_queue *txq;
6541 int index = tnapi - tp->napi;
6542 unsigned int pkts_compl = 0, bytes_compl = 0;
6544 if (tg3_flag(tp, ENABLE_TSS))
6547 txq = netdev_get_tx_queue(tp->dev, index);
6549 while (sw_idx != hw_idx) {
6550 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6551 struct sk_buff *skb = ri->skb;
6554 if (unlikely(skb == NULL)) {
6559 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6560 struct skb_shared_hwtstamps timestamp;
6561 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6562 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6564 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6566 skb_tstamp_tx(skb, ×tamp);
6569 pci_unmap_single(tp->pdev,
6570 dma_unmap_addr(ri, mapping),
6576 while (ri->fragmented) {
6577 ri->fragmented = false;
6578 sw_idx = NEXT_TX(sw_idx);
6579 ri = &tnapi->tx_buffers[sw_idx];
6582 sw_idx = NEXT_TX(sw_idx);
6584 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6585 ri = &tnapi->tx_buffers[sw_idx];
6586 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6589 pci_unmap_page(tp->pdev,
6590 dma_unmap_addr(ri, mapping),
6591 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6594 while (ri->fragmented) {
6595 ri->fragmented = false;
6596 sw_idx = NEXT_TX(sw_idx);
6597 ri = &tnapi->tx_buffers[sw_idx];
6600 sw_idx = NEXT_TX(sw_idx);
6604 bytes_compl += skb->len;
6606 dev_consume_skb_any(skb);
6608 if (unlikely(tx_bug)) {
6614 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6616 tnapi->tx_cons = sw_idx;
6618 /* Need to make the tx_cons update visible to tg3_start_xmit()
6619 * before checking for netif_queue_stopped(). Without the
6620 * memory barrier, there is a small possibility that tg3_start_xmit()
6621 * will miss it and cause the queue to be stopped forever.
6625 if (unlikely(netif_tx_queue_stopped(txq) &&
6626 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6627 __netif_tx_lock(txq, smp_processor_id());
6628 if (netif_tx_queue_stopped(txq) &&
6629 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6630 netif_tx_wake_queue(txq);
6631 __netif_tx_unlock(txq);
6635 static void tg3_frag_free(bool is_frag, void *data)
6638 skb_free_frag(data);
6643 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6645 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6646 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6651 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6652 map_sz, PCI_DMA_FROMDEVICE);
6653 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6658 /* Returns size of skb allocated or < 0 on error.
6660 * We only need to fill in the address because the other members
6661 * of the RX descriptor are invariant, see tg3_init_rings.
6663 * Note the purposeful assymetry of cpu vs. chip accesses. For
6664 * posting buffers we only dirty the first cache line of the RX
6665 * descriptor (containing the address). Whereas for the RX status
6666 * buffers the cpu only reads the last cacheline of the RX descriptor
6667 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6669 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6670 u32 opaque_key, u32 dest_idx_unmasked,
6671 unsigned int *frag_size)
6673 struct tg3_rx_buffer_desc *desc;
6674 struct ring_info *map;
6677 int skb_size, data_size, dest_idx;
6679 switch (opaque_key) {
6680 case RXD_OPAQUE_RING_STD:
6681 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6682 desc = &tpr->rx_std[dest_idx];
6683 map = &tpr->rx_std_buffers[dest_idx];
6684 data_size = tp->rx_pkt_map_sz;
6687 case RXD_OPAQUE_RING_JUMBO:
6688 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6689 desc = &tpr->rx_jmb[dest_idx].std;
6690 map = &tpr->rx_jmb_buffers[dest_idx];
6691 data_size = TG3_RX_JMB_MAP_SZ;
6698 /* Do not overwrite any of the map or rp information
6699 * until we are sure we can commit to a new buffer.
6701 * Callers depend upon this behavior and assume that
6702 * we leave everything unchanged if we fail.
6704 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6705 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6706 if (skb_size <= PAGE_SIZE) {
6707 data = napi_alloc_frag(skb_size);
6708 *frag_size = skb_size;
6710 data = kmalloc(skb_size, GFP_ATOMIC);
6716 mapping = pci_map_single(tp->pdev,
6717 data + TG3_RX_OFFSET(tp),
6719 PCI_DMA_FROMDEVICE);
6720 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6721 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6726 dma_unmap_addr_set(map, mapping, mapping);
6728 desc->addr_hi = ((u64)mapping >> 32);
6729 desc->addr_lo = ((u64)mapping & 0xffffffff);
6734 /* We only need to move over in the address because the other
6735 * members of the RX descriptor are invariant. See notes above
6736 * tg3_alloc_rx_data for full details.
6738 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6739 struct tg3_rx_prodring_set *dpr,
6740 u32 opaque_key, int src_idx,
6741 u32 dest_idx_unmasked)
6743 struct tg3 *tp = tnapi->tp;
6744 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6745 struct ring_info *src_map, *dest_map;
6746 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6749 switch (opaque_key) {
6750 case RXD_OPAQUE_RING_STD:
6751 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6752 dest_desc = &dpr->rx_std[dest_idx];
6753 dest_map = &dpr->rx_std_buffers[dest_idx];
6754 src_desc = &spr->rx_std[src_idx];
6755 src_map = &spr->rx_std_buffers[src_idx];
6758 case RXD_OPAQUE_RING_JUMBO:
6759 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6760 dest_desc = &dpr->rx_jmb[dest_idx].std;
6761 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6762 src_desc = &spr->rx_jmb[src_idx].std;
6763 src_map = &spr->rx_jmb_buffers[src_idx];
6770 dest_map->data = src_map->data;
6771 dma_unmap_addr_set(dest_map, mapping,
6772 dma_unmap_addr(src_map, mapping));
6773 dest_desc->addr_hi = src_desc->addr_hi;
6774 dest_desc->addr_lo = src_desc->addr_lo;
6776 /* Ensure that the update to the skb happens after the physical
6777 * addresses have been transferred to the new BD location.
6781 src_map->data = NULL;
6784 /* The RX ring scheme is composed of multiple rings which post fresh
6785 * buffers to the chip, and one special ring the chip uses to report
6786 * status back to the host.
6788 * The special ring reports the status of received packets to the
6789 * host. The chip does not write into the original descriptor the
6790 * RX buffer was obtained from. The chip simply takes the original
6791 * descriptor as provided by the host, updates the status and length
6792 * field, then writes this into the next status ring entry.
6794 * Each ring the host uses to post buffers to the chip is described
6795 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6796 * it is first placed into the on-chip ram. When the packet's length
6797 * is known, it walks down the TG3_BDINFO entries to select the ring.
6798 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6799 * which is within the range of the new packet's length is chosen.
6801 * The "separate ring for rx status" scheme may sound queer, but it makes
6802 * sense from a cache coherency perspective. If only the host writes
6803 * to the buffer post rings, and only the chip writes to the rx status
6804 * rings, then cache lines never move beyond shared-modified state.
6805 * If both the host and chip were to write into the same ring, cache line
6806 * eviction could occur since both entities want it in an exclusive state.
6808 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6810 struct tg3 *tp = tnapi->tp;
6811 u32 work_mask, rx_std_posted = 0;
6812 u32 std_prod_idx, jmb_prod_idx;
6813 u32 sw_idx = tnapi->rx_rcb_ptr;
6816 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6818 hw_idx = *(tnapi->rx_rcb_prod_idx);
6820 * We need to order the read of hw_idx and the read of
6821 * the opaque cookie.
6826 std_prod_idx = tpr->rx_std_prod_idx;
6827 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6828 while (sw_idx != hw_idx && budget > 0) {
6829 struct ring_info *ri;
6830 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6832 struct sk_buff *skb;
6833 dma_addr_t dma_addr;
6834 u32 opaque_key, desc_idx, *post_ptr;
6838 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6839 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6840 if (opaque_key == RXD_OPAQUE_RING_STD) {
6841 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6842 dma_addr = dma_unmap_addr(ri, mapping);
6844 post_ptr = &std_prod_idx;
6846 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6847 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6848 dma_addr = dma_unmap_addr(ri, mapping);
6850 post_ptr = &jmb_prod_idx;
6852 goto next_pkt_nopost;
6854 work_mask |= opaque_key;
6856 if (desc->err_vlan & RXD_ERR_MASK) {
6858 tg3_recycle_rx(tnapi, tpr, opaque_key,
6859 desc_idx, *post_ptr);
6861 /* Other statistics kept track of by card. */
6862 tnapi->rx_dropped++;
6866 prefetch(data + TG3_RX_OFFSET(tp));
6867 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6870 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6871 RXD_FLAG_PTPSTAT_PTPV1 ||
6872 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6873 RXD_FLAG_PTPSTAT_PTPV2) {
6874 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6875 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6878 if (len > TG3_RX_COPY_THRESH(tp)) {
6880 unsigned int frag_size;
6882 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6883 *post_ptr, &frag_size);
6887 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6888 PCI_DMA_FROMDEVICE);
6890 /* Ensure that the update to the data happens
6891 * after the usage of the old DMA mapping.
6897 skb = build_skb(data, frag_size);
6899 tg3_frag_free(frag_size != 0, data);
6900 goto drop_it_no_recycle;
6902 skb_reserve(skb, TG3_RX_OFFSET(tp));
6904 tg3_recycle_rx(tnapi, tpr, opaque_key,
6905 desc_idx, *post_ptr);
6907 skb = netdev_alloc_skb(tp->dev,
6908 len + TG3_RAW_IP_ALIGN);
6910 goto drop_it_no_recycle;
6912 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6913 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6915 data + TG3_RX_OFFSET(tp),
6917 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6922 tg3_hwclock_to_timestamp(tp, tstamp,
6923 skb_hwtstamps(skb));
6925 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6926 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6927 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6928 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6929 skb->ip_summed = CHECKSUM_UNNECESSARY;
6931 skb_checksum_none_assert(skb);
6933 skb->protocol = eth_type_trans(skb, tp->dev);
6935 if (len > (tp->dev->mtu + ETH_HLEN) &&
6936 skb->protocol != htons(ETH_P_8021Q) &&
6937 skb->protocol != htons(ETH_P_8021AD)) {
6938 dev_kfree_skb_any(skb);
6939 goto drop_it_no_recycle;
6942 if (desc->type_flags & RXD_FLAG_VLAN &&
6943 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6944 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6945 desc->err_vlan & RXD_VLAN_MASK);
6947 napi_gro_receive(&tnapi->napi, skb);
6955 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6956 tpr->rx_std_prod_idx = std_prod_idx &
6957 tp->rx_std_ring_mask;
6958 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6959 tpr->rx_std_prod_idx);
6960 work_mask &= ~RXD_OPAQUE_RING_STD;
6965 sw_idx &= tp->rx_ret_ring_mask;
6967 /* Refresh hw_idx to see if there is new work */
6968 if (sw_idx == hw_idx) {
6969 hw_idx = *(tnapi->rx_rcb_prod_idx);
6974 /* ACK the status ring. */
6975 tnapi->rx_rcb_ptr = sw_idx;
6976 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6978 /* Refill RX ring(s). */
6979 if (!tg3_flag(tp, ENABLE_RSS)) {
6980 /* Sync BD data before updating mailbox */
6983 if (work_mask & RXD_OPAQUE_RING_STD) {
6984 tpr->rx_std_prod_idx = std_prod_idx &
6985 tp->rx_std_ring_mask;
6986 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6987 tpr->rx_std_prod_idx);
6989 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6990 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6991 tp->rx_jmb_ring_mask;
6992 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6993 tpr->rx_jmb_prod_idx);
6995 } else if (work_mask) {
6996 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6997 * updated before the producer indices can be updated.
7001 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
7002 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
7004 if (tnapi != &tp->napi[1]) {
7005 tp->rx_refill = true;
7006 napi_schedule(&tp->napi[1].napi);
7013 static void tg3_poll_link(struct tg3 *tp)
7015 /* handle link change and other phy events */
7016 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7017 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7019 if (sblk->status & SD_STATUS_LINK_CHG) {
7020 sblk->status = SD_STATUS_UPDATED |
7021 (sblk->status & ~SD_STATUS_LINK_CHG);
7022 spin_lock(&tp->lock);
7023 if (tg3_flag(tp, USE_PHYLIB)) {
7025 (MAC_STATUS_SYNC_CHANGED |
7026 MAC_STATUS_CFG_CHANGED |
7027 MAC_STATUS_MI_COMPLETION |
7028 MAC_STATUS_LNKSTATE_CHANGED));
7031 tg3_setup_phy(tp, false);
7032 spin_unlock(&tp->lock);
7037 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7038 struct tg3_rx_prodring_set *dpr,
7039 struct tg3_rx_prodring_set *spr)
7041 u32 si, di, cpycnt, src_prod_idx;
7045 src_prod_idx = spr->rx_std_prod_idx;
7047 /* Make sure updates to the rx_std_buffers[] entries and the
7048 * standard producer index are seen in the correct order.
7052 if (spr->rx_std_cons_idx == src_prod_idx)
7055 if (spr->rx_std_cons_idx < src_prod_idx)
7056 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7058 cpycnt = tp->rx_std_ring_mask + 1 -
7059 spr->rx_std_cons_idx;
7061 cpycnt = min(cpycnt,
7062 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7064 si = spr->rx_std_cons_idx;
7065 di = dpr->rx_std_prod_idx;
7067 for (i = di; i < di + cpycnt; i++) {
7068 if (dpr->rx_std_buffers[i].data) {
7078 /* Ensure that updates to the rx_std_buffers ring and the
7079 * shadowed hardware producer ring from tg3_recycle_skb() are
7080 * ordered correctly WRT the skb check above.
7084 memcpy(&dpr->rx_std_buffers[di],
7085 &spr->rx_std_buffers[si],
7086 cpycnt * sizeof(struct ring_info));
7088 for (i = 0; i < cpycnt; i++, di++, si++) {
7089 struct tg3_rx_buffer_desc *sbd, *dbd;
7090 sbd = &spr->rx_std[si];
7091 dbd = &dpr->rx_std[di];
7092 dbd->addr_hi = sbd->addr_hi;
7093 dbd->addr_lo = sbd->addr_lo;
7096 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7097 tp->rx_std_ring_mask;
7098 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7099 tp->rx_std_ring_mask;
7103 src_prod_idx = spr->rx_jmb_prod_idx;
7105 /* Make sure updates to the rx_jmb_buffers[] entries and
7106 * the jumbo producer index are seen in the correct order.
7110 if (spr->rx_jmb_cons_idx == src_prod_idx)
7113 if (spr->rx_jmb_cons_idx < src_prod_idx)
7114 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7116 cpycnt = tp->rx_jmb_ring_mask + 1 -
7117 spr->rx_jmb_cons_idx;
7119 cpycnt = min(cpycnt,
7120 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7122 si = spr->rx_jmb_cons_idx;
7123 di = dpr->rx_jmb_prod_idx;
7125 for (i = di; i < di + cpycnt; i++) {
7126 if (dpr->rx_jmb_buffers[i].data) {
7136 /* Ensure that updates to the rx_jmb_buffers ring and the
7137 * shadowed hardware producer ring from tg3_recycle_skb() are
7138 * ordered correctly WRT the skb check above.
7142 memcpy(&dpr->rx_jmb_buffers[di],
7143 &spr->rx_jmb_buffers[si],
7144 cpycnt * sizeof(struct ring_info));
7146 for (i = 0; i < cpycnt; i++, di++, si++) {
7147 struct tg3_rx_buffer_desc *sbd, *dbd;
7148 sbd = &spr->rx_jmb[si].std;
7149 dbd = &dpr->rx_jmb[di].std;
7150 dbd->addr_hi = sbd->addr_hi;
7151 dbd->addr_lo = sbd->addr_lo;
7154 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7155 tp->rx_jmb_ring_mask;
7156 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7157 tp->rx_jmb_ring_mask;
7163 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7165 struct tg3 *tp = tnapi->tp;
7167 /* run TX completion thread */
7168 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7170 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7174 if (!tnapi->rx_rcb_prod_idx)
7177 /* run RX thread, within the bounds set by NAPI.
7178 * All RX "locking" is done by ensuring outside
7179 * code synchronizes with tg3->napi.poll()
7181 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7182 work_done += tg3_rx(tnapi, budget - work_done);
7184 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7185 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7187 u32 std_prod_idx = dpr->rx_std_prod_idx;
7188 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7190 tp->rx_refill = false;
7191 for (i = 1; i <= tp->rxq_cnt; i++)
7192 err |= tg3_rx_prodring_xfer(tp, dpr,
7193 &tp->napi[i].prodring);
7197 if (std_prod_idx != dpr->rx_std_prod_idx)
7198 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7199 dpr->rx_std_prod_idx);
7201 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7202 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7203 dpr->rx_jmb_prod_idx);
7206 tw32_f(HOSTCC_MODE, tp->coal_now);
7212 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7214 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7215 schedule_work(&tp->reset_task);
7218 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7220 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7221 cancel_work_sync(&tp->reset_task);
7222 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7225 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7227 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7228 struct tg3 *tp = tnapi->tp;
7230 struct tg3_hw_status *sblk = tnapi->hw_status;
7233 work_done = tg3_poll_work(tnapi, work_done, budget);
7235 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7238 if (unlikely(work_done >= budget))
7241 /* tp->last_tag is used in tg3_int_reenable() below
7242 * to tell the hw how much work has been processed,
7243 * so we must read it before checking for more work.
7245 tnapi->last_tag = sblk->status_tag;
7246 tnapi->last_irq_tag = tnapi->last_tag;
7249 /* check for RX/TX work to do */
7250 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7251 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7253 /* This test here is not race free, but will reduce
7254 * the number of interrupts by looping again.
7256 if (tnapi == &tp->napi[1] && tp->rx_refill)
7259 napi_complete_done(napi, work_done);
7260 /* Reenable interrupts. */
7261 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7263 /* This test here is synchronized by napi_schedule()
7264 * and napi_complete() to close the race condition.
7266 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7267 tw32(HOSTCC_MODE, tp->coalesce_mode |
7268 HOSTCC_MODE_ENABLE |
7275 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7279 /* work_done is guaranteed to be less than budget. */
7280 napi_complete(napi);
7281 tg3_reset_task_schedule(tp);
7285 static void tg3_process_error(struct tg3 *tp)
7288 bool real_error = false;
7290 if (tg3_flag(tp, ERROR_PROCESSED))
7293 /* Check Flow Attention register */
7294 val = tr32(HOSTCC_FLOW_ATTN);
7295 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7296 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7300 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7301 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7305 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7306 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7315 tg3_flag_set(tp, ERROR_PROCESSED);
7316 tg3_reset_task_schedule(tp);
7319 static int tg3_poll(struct napi_struct *napi, int budget)
7321 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7322 struct tg3 *tp = tnapi->tp;
7324 struct tg3_hw_status *sblk = tnapi->hw_status;
7327 if (sblk->status & SD_STATUS_ERROR)
7328 tg3_process_error(tp);
7332 work_done = tg3_poll_work(tnapi, work_done, budget);
7334 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7337 if (unlikely(work_done >= budget))
7340 if (tg3_flag(tp, TAGGED_STATUS)) {
7341 /* tp->last_tag is used in tg3_int_reenable() below
7342 * to tell the hw how much work has been processed,
7343 * so we must read it before checking for more work.
7345 tnapi->last_tag = sblk->status_tag;
7346 tnapi->last_irq_tag = tnapi->last_tag;
7349 sblk->status &= ~SD_STATUS_UPDATED;
7351 if (likely(!tg3_has_work(tnapi))) {
7352 napi_complete_done(napi, work_done);
7353 tg3_int_reenable(tnapi);
7358 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7362 /* work_done is guaranteed to be less than budget. */
7363 napi_complete(napi);
7364 tg3_reset_task_schedule(tp);
7368 static void tg3_napi_disable(struct tg3 *tp)
7372 for (i = tp->irq_cnt - 1; i >= 0; i--)
7373 napi_disable(&tp->napi[i].napi);
7376 static void tg3_napi_enable(struct tg3 *tp)
7380 for (i = 0; i < tp->irq_cnt; i++)
7381 napi_enable(&tp->napi[i].napi);
7384 static void tg3_napi_init(struct tg3 *tp)
7388 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7389 for (i = 1; i < tp->irq_cnt; i++)
7390 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7393 static void tg3_napi_fini(struct tg3 *tp)
7397 for (i = 0; i < tp->irq_cnt; i++)
7398 netif_napi_del(&tp->napi[i].napi);
7401 static inline void tg3_netif_stop(struct tg3 *tp)
7403 netif_trans_update(tp->dev); /* prevent tx timeout */
7404 tg3_napi_disable(tp);
7405 netif_carrier_off(tp->dev);
7406 netif_tx_disable(tp->dev);
7409 /* tp->lock must be held */
7410 static inline void tg3_netif_start(struct tg3 *tp)
7414 /* NOTE: unconditional netif_tx_wake_all_queues is only
7415 * appropriate so long as all callers are assured to
7416 * have free tx slots (such as after tg3_init_hw)
7418 netif_tx_wake_all_queues(tp->dev);
7421 netif_carrier_on(tp->dev);
7423 tg3_napi_enable(tp);
7424 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7425 tg3_enable_ints(tp);
7428 static void tg3_irq_quiesce(struct tg3 *tp)
7429 __releases(tp->lock)
7430 __acquires(tp->lock)
7434 BUG_ON(tp->irq_sync);
7439 spin_unlock_bh(&tp->lock);
7441 for (i = 0; i < tp->irq_cnt; i++)
7442 synchronize_irq(tp->napi[i].irq_vec);
7444 spin_lock_bh(&tp->lock);
7447 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7448 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7449 * with as well. Most of the time, this is not necessary except when
7450 * shutting down the device.
7452 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7454 spin_lock_bh(&tp->lock);
7456 tg3_irq_quiesce(tp);
7459 static inline void tg3_full_unlock(struct tg3 *tp)
7461 spin_unlock_bh(&tp->lock);
7464 /* One-shot MSI handler - Chip automatically disables interrupt
7465 * after sending MSI so driver doesn't have to do it.
7467 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7469 struct tg3_napi *tnapi = dev_id;
7470 struct tg3 *tp = tnapi->tp;
7472 prefetch(tnapi->hw_status);
7474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7476 if (likely(!tg3_irq_sync(tp)))
7477 napi_schedule(&tnapi->napi);
7482 /* MSI ISR - No need to check for interrupt sharing and no need to
7483 * flush status block and interrupt mailbox. PCI ordering rules
7484 * guarantee that MSI will arrive after the status block.
7486 static irqreturn_t tg3_msi(int irq, void *dev_id)
7488 struct tg3_napi *tnapi = dev_id;
7489 struct tg3 *tp = tnapi->tp;
7491 prefetch(tnapi->hw_status);
7493 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7495 * Writing any value to intr-mbox-0 clears PCI INTA# and
7496 * chip-internal interrupt pending events.
7497 * Writing non-zero to intr-mbox-0 additional tells the
7498 * NIC to stop sending us irqs, engaging "in-intr-handler"
7501 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7502 if (likely(!tg3_irq_sync(tp)))
7503 napi_schedule(&tnapi->napi);
7505 return IRQ_RETVAL(1);
7508 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7510 struct tg3_napi *tnapi = dev_id;
7511 struct tg3 *tp = tnapi->tp;
7512 struct tg3_hw_status *sblk = tnapi->hw_status;
7513 unsigned int handled = 1;
7515 /* In INTx mode, it is possible for the interrupt to arrive at
7516 * the CPU before the status block posted prior to the interrupt.
7517 * Reading the PCI State register will confirm whether the
7518 * interrupt is ours and will flush the status block.
7520 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7521 if (tg3_flag(tp, CHIP_RESETTING) ||
7522 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7529 * Writing any value to intr-mbox-0 clears PCI INTA# and
7530 * chip-internal interrupt pending events.
7531 * Writing non-zero to intr-mbox-0 additional tells the
7532 * NIC to stop sending us irqs, engaging "in-intr-handler"
7535 * Flush the mailbox to de-assert the IRQ immediately to prevent
7536 * spurious interrupts. The flush impacts performance but
7537 * excessive spurious interrupts can be worse in some cases.
7539 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7540 if (tg3_irq_sync(tp))
7542 sblk->status &= ~SD_STATUS_UPDATED;
7543 if (likely(tg3_has_work(tnapi))) {
7544 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7545 napi_schedule(&tnapi->napi);
7547 /* No work, shared interrupt perhaps? re-enable
7548 * interrupts, and flush that PCI write
7550 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7554 return IRQ_RETVAL(handled);
7557 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7559 struct tg3_napi *tnapi = dev_id;
7560 struct tg3 *tp = tnapi->tp;
7561 struct tg3_hw_status *sblk = tnapi->hw_status;
7562 unsigned int handled = 1;
7564 /* In INTx mode, it is possible for the interrupt to arrive at
7565 * the CPU before the status block posted prior to the interrupt.
7566 * Reading the PCI State register will confirm whether the
7567 * interrupt is ours and will flush the status block.
7569 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7570 if (tg3_flag(tp, CHIP_RESETTING) ||
7571 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7578 * writing any value to intr-mbox-0 clears PCI INTA# and
7579 * chip-internal interrupt pending events.
7580 * writing non-zero to intr-mbox-0 additional tells the
7581 * NIC to stop sending us irqs, engaging "in-intr-handler"
7584 * Flush the mailbox to de-assert the IRQ immediately to prevent
7585 * spurious interrupts. The flush impacts performance but
7586 * excessive spurious interrupts can be worse in some cases.
7588 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7591 * In a shared interrupt configuration, sometimes other devices'
7592 * interrupts will scream. We record the current status tag here
7593 * so that the above check can report that the screaming interrupts
7594 * are unhandled. Eventually they will be silenced.
7596 tnapi->last_irq_tag = sblk->status_tag;
7598 if (tg3_irq_sync(tp))
7601 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7603 napi_schedule(&tnapi->napi);
7606 return IRQ_RETVAL(handled);
7609 /* ISR for interrupt test */
7610 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7612 struct tg3_napi *tnapi = dev_id;
7613 struct tg3 *tp = tnapi->tp;
7614 struct tg3_hw_status *sblk = tnapi->hw_status;
7616 if ((sblk->status & SD_STATUS_UPDATED) ||
7617 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7618 tg3_disable_ints(tp);
7619 return IRQ_RETVAL(1);
7621 return IRQ_RETVAL(0);
7624 #ifdef CONFIG_NET_POLL_CONTROLLER
7625 static void tg3_poll_controller(struct net_device *dev)
7628 struct tg3 *tp = netdev_priv(dev);
7630 if (tg3_irq_sync(tp))
7633 for (i = 0; i < tp->irq_cnt; i++)
7634 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7638 static void tg3_tx_timeout(struct net_device *dev, unsigned int txqueue)
7640 struct tg3 *tp = netdev_priv(dev);
7642 if (netif_msg_tx_err(tp)) {
7643 netdev_err(dev, "transmit timed out, resetting\n");
7647 tg3_reset_task_schedule(tp);
7650 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7651 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7653 u32 base = (u32) mapping & 0xffffffff;
7655 return base + len + 8 < base;
7658 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7659 * of any 4GB boundaries: 4G, 8G, etc
7661 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7664 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7665 u32 base = (u32) mapping & 0xffffffff;
7667 return ((base + len + (mss & 0x3fff)) < base);
7672 /* Test for DMA addresses > 40-bit */
7673 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7676 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7677 if (tg3_flag(tp, 40BIT_DMA_BUG))
7678 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7685 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7686 dma_addr_t mapping, u32 len, u32 flags,
7689 txbd->addr_hi = ((u64) mapping >> 32);
7690 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7691 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7692 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7695 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7696 dma_addr_t map, u32 len, u32 flags,
7699 struct tg3 *tp = tnapi->tp;
7702 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7705 if (tg3_4g_overflow_test(map, len))
7708 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7711 if (tg3_40bit_overflow_test(tp, map, len))
7714 if (tp->dma_limit) {
7715 u32 prvidx = *entry;
7716 u32 tmp_flag = flags & ~TXD_FLAG_END;
7717 while (len > tp->dma_limit && *budget) {
7718 u32 frag_len = tp->dma_limit;
7719 len -= tp->dma_limit;
7721 /* Avoid the 8byte DMA problem */
7723 len += tp->dma_limit / 2;
7724 frag_len = tp->dma_limit / 2;
7727 tnapi->tx_buffers[*entry].fragmented = true;
7729 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7730 frag_len, tmp_flag, mss, vlan);
7733 *entry = NEXT_TX(*entry);
7740 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7741 len, flags, mss, vlan);
7743 *entry = NEXT_TX(*entry);
7746 tnapi->tx_buffers[prvidx].fragmented = false;
7750 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7751 len, flags, mss, vlan);
7752 *entry = NEXT_TX(*entry);
7758 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7761 struct sk_buff *skb;
7762 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7767 pci_unmap_single(tnapi->tp->pdev,
7768 dma_unmap_addr(txb, mapping),
7772 while (txb->fragmented) {
7773 txb->fragmented = false;
7774 entry = NEXT_TX(entry);
7775 txb = &tnapi->tx_buffers[entry];
7778 for (i = 0; i <= last; i++) {
7779 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7781 entry = NEXT_TX(entry);
7782 txb = &tnapi->tx_buffers[entry];
7784 pci_unmap_page(tnapi->tp->pdev,
7785 dma_unmap_addr(txb, mapping),
7786 skb_frag_size(frag), PCI_DMA_TODEVICE);
7788 while (txb->fragmented) {
7789 txb->fragmented = false;
7790 entry = NEXT_TX(entry);
7791 txb = &tnapi->tx_buffers[entry];
7796 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7797 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7798 struct sk_buff **pskb,
7799 u32 *entry, u32 *budget,
7800 u32 base_flags, u32 mss, u32 vlan)
7802 struct tg3 *tp = tnapi->tp;
7803 struct sk_buff *new_skb, *skb = *pskb;
7804 dma_addr_t new_addr = 0;
7807 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7808 new_skb = skb_copy(skb, GFP_ATOMIC);
7810 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7812 new_skb = skb_copy_expand(skb,
7813 skb_headroom(skb) + more_headroom,
7814 skb_tailroom(skb), GFP_ATOMIC);
7820 /* New SKB is guaranteed to be linear. */
7821 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7823 /* Make sure the mapping succeeded */
7824 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7825 dev_kfree_skb_any(new_skb);
7828 u32 save_entry = *entry;
7830 base_flags |= TXD_FLAG_END;
7832 tnapi->tx_buffers[*entry].skb = new_skb;
7833 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7836 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7837 new_skb->len, base_flags,
7839 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7840 dev_kfree_skb_any(new_skb);
7846 dev_consume_skb_any(skb);
7851 static bool tg3_tso_bug_gso_check(struct tg3_napi *tnapi, struct sk_buff *skb)
7853 /* Check if we will never have enough descriptors,
7854 * as gso_segs can be more than current ring size
7856 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3;
7859 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7861 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7862 * indicated in tg3_tx_frag_set()
7864 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7865 struct netdev_queue *txq, struct sk_buff *skb)
7867 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7868 struct sk_buff *segs, *seg, *next;
7870 /* Estimate the number of fragments in the worst case */
7871 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7872 netif_tx_stop_queue(txq);
7874 /* netif_tx_stop_queue() must be done before checking
7875 * checking tx index in tg3_tx_avail() below, because in
7876 * tg3_tx(), we update tx index before checking for
7877 * netif_tx_queue_stopped().
7880 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7881 return NETDEV_TX_BUSY;
7883 netif_tx_wake_queue(txq);
7886 segs = skb_gso_segment(skb, tp->dev->features &
7887 ~(NETIF_F_TSO | NETIF_F_TSO6));
7888 if (IS_ERR(segs) || !segs) {
7889 tnapi->tx_dropped++;
7890 goto tg3_tso_bug_end;
7893 skb_list_walk_safe(segs, seg, next) {
7894 skb_mark_not_on_list(seg);
7895 tg3_start_xmit(seg, tp->dev);
7899 dev_consume_skb_any(skb);
7901 return NETDEV_TX_OK;
7904 /* hard_start_xmit for all devices */
7905 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7907 struct tg3 *tp = netdev_priv(dev);
7908 u32 len, entry, base_flags, mss, vlan = 0;
7910 int i = -1, would_hit_hwbug;
7912 struct tg3_napi *tnapi;
7913 struct netdev_queue *txq;
7915 struct iphdr *iph = NULL;
7916 struct tcphdr *tcph = NULL;
7917 __sum16 tcp_csum = 0, ip_csum = 0;
7918 __be16 ip_tot_len = 0;
7920 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7921 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7922 if (tg3_flag(tp, ENABLE_TSS))
7925 budget = tg3_tx_avail(tnapi);
7927 /* We are running in BH disabled context with netif_tx_lock
7928 * and TX reclaim runs via tp->napi.poll inside of a software
7929 * interrupt. Furthermore, IRQ processing runs lockless so we have
7930 * no IRQ context deadlocks to worry about either. Rejoice!
7932 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7933 if (!netif_tx_queue_stopped(txq)) {
7934 netif_tx_stop_queue(txq);
7936 /* This is a hard error, log it. */
7938 "BUG! Tx Ring full when queue awake!\n");
7940 return NETDEV_TX_BUSY;
7943 entry = tnapi->tx_prod;
7946 mss = skb_shinfo(skb)->gso_size;
7948 u32 tcp_opt_len, hdr_len;
7950 if (skb_cow_head(skb, 0))
7954 tcp_opt_len = tcp_optlen(skb);
7956 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7958 /* HW/FW can not correctly segment packets that have been
7959 * vlan encapsulated.
7961 if (skb->protocol == htons(ETH_P_8021Q) ||
7962 skb->protocol == htons(ETH_P_8021AD)) {
7963 if (tg3_tso_bug_gso_check(tnapi, skb))
7964 return tg3_tso_bug(tp, tnapi, txq, skb);
7968 if (!skb_is_gso_v6(skb)) {
7969 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7970 tg3_flag(tp, TSO_BUG)) {
7971 if (tg3_tso_bug_gso_check(tnapi, skb))
7972 return tg3_tso_bug(tp, tnapi, txq, skb);
7975 ip_csum = iph->check;
7976 ip_tot_len = iph->tot_len;
7978 iph->tot_len = htons(mss + hdr_len);
7981 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7982 TXD_FLAG_CPU_POST_DMA);
7984 tcph = tcp_hdr(skb);
7985 tcp_csum = tcph->check;
7987 if (tg3_flag(tp, HW_TSO_1) ||
7988 tg3_flag(tp, HW_TSO_2) ||
7989 tg3_flag(tp, HW_TSO_3)) {
7991 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7993 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7997 if (tg3_flag(tp, HW_TSO_3)) {
7998 mss |= (hdr_len & 0xc) << 12;
8000 base_flags |= 0x00000010;
8001 base_flags |= (hdr_len & 0x3e0) << 5;
8002 } else if (tg3_flag(tp, HW_TSO_2))
8003 mss |= hdr_len << 9;
8004 else if (tg3_flag(tp, HW_TSO_1) ||
8005 tg3_asic_rev(tp) == ASIC_REV_5705) {
8006 if (tcp_opt_len || iph->ihl > 5) {
8009 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
8010 mss |= (tsflags << 11);
8013 if (tcp_opt_len || iph->ihl > 5) {
8016 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
8017 base_flags |= tsflags << 12;
8020 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
8021 /* HW/FW can not correctly checksum packets that have been
8022 * vlan encapsulated.
8024 if (skb->protocol == htons(ETH_P_8021Q) ||
8025 skb->protocol == htons(ETH_P_8021AD)) {
8026 if (skb_checksum_help(skb))
8029 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8033 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8034 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8035 base_flags |= TXD_FLAG_JMB_PKT;
8037 if (skb_vlan_tag_present(skb)) {
8038 base_flags |= TXD_FLAG_VLAN;
8039 vlan = skb_vlan_tag_get(skb);
8042 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8043 tg3_flag(tp, TX_TSTAMP_EN)) {
8044 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8045 base_flags |= TXD_FLAG_HWTSTAMP;
8048 len = skb_headlen(skb);
8050 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8051 if (pci_dma_mapping_error(tp->pdev, mapping))
8055 tnapi->tx_buffers[entry].skb = skb;
8056 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8058 would_hit_hwbug = 0;
8060 if (tg3_flag(tp, 5701_DMA_BUG))
8061 would_hit_hwbug = 1;
8063 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8064 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8066 would_hit_hwbug = 1;
8067 } else if (skb_shinfo(skb)->nr_frags > 0) {
8070 if (!tg3_flag(tp, HW_TSO_1) &&
8071 !tg3_flag(tp, HW_TSO_2) &&
8072 !tg3_flag(tp, HW_TSO_3))
8075 /* Now loop through additional data
8076 * fragments, and queue them.
8078 last = skb_shinfo(skb)->nr_frags - 1;
8079 for (i = 0; i <= last; i++) {
8080 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8082 len = skb_frag_size(frag);
8083 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8084 len, DMA_TO_DEVICE);
8086 tnapi->tx_buffers[entry].skb = NULL;
8087 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8089 if (dma_mapping_error(&tp->pdev->dev, mapping))
8093 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8095 ((i == last) ? TXD_FLAG_END : 0),
8097 would_hit_hwbug = 1;
8103 if (would_hit_hwbug) {
8104 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8106 if (mss && tg3_tso_bug_gso_check(tnapi, skb)) {
8107 /* If it's a TSO packet, do GSO instead of
8108 * allocating and copying to a large linear SKB
8111 iph->check = ip_csum;
8112 iph->tot_len = ip_tot_len;
8114 tcph->check = tcp_csum;
8115 return tg3_tso_bug(tp, tnapi, txq, skb);
8118 /* If the workaround fails due to memory/mapping
8119 * failure, silently drop this packet.
8121 entry = tnapi->tx_prod;
8122 budget = tg3_tx_avail(tnapi);
8123 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8124 base_flags, mss, vlan))
8128 skb_tx_timestamp(skb);
8129 netdev_tx_sent_queue(txq, skb->len);
8131 /* Sync BD data before updating mailbox */
8134 tnapi->tx_prod = entry;
8135 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8136 netif_tx_stop_queue(txq);
8138 /* netif_tx_stop_queue() must be done before checking
8139 * checking tx index in tg3_tx_avail() below, because in
8140 * tg3_tx(), we update tx index before checking for
8141 * netif_tx_queue_stopped().
8144 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8145 netif_tx_wake_queue(txq);
8148 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) {
8149 /* Packets are ready, update Tx producer idx on card. */
8150 tw32_tx_mbox(tnapi->prodmbox, entry);
8153 return NETDEV_TX_OK;
8156 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8157 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8159 dev_kfree_skb_any(skb);
8161 tnapi->tx_dropped++;
8162 return NETDEV_TX_OK;
8165 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8168 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8169 MAC_MODE_PORT_MODE_MASK);
8171 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8173 if (!tg3_flag(tp, 5705_PLUS))
8174 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8176 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8177 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8179 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8181 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8183 if (tg3_flag(tp, 5705_PLUS) ||
8184 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8185 tg3_asic_rev(tp) == ASIC_REV_5700)
8186 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8189 tw32(MAC_MODE, tp->mac_mode);
8193 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8195 u32 val, bmcr, mac_mode, ptest = 0;
8197 tg3_phy_toggle_apd(tp, false);
8198 tg3_phy_toggle_automdix(tp, false);
8200 if (extlpbk && tg3_phy_set_extloopbk(tp))
8203 bmcr = BMCR_FULLDPLX;
8208 bmcr |= BMCR_SPEED100;
8212 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8214 bmcr |= BMCR_SPEED100;
8217 bmcr |= BMCR_SPEED1000;
8222 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8223 tg3_readphy(tp, MII_CTRL1000, &val);
8224 val |= CTL1000_AS_MASTER |
8225 CTL1000_ENABLE_MASTER;
8226 tg3_writephy(tp, MII_CTRL1000, val);
8228 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8229 MII_TG3_FET_PTEST_TRIM_2;
8230 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8233 bmcr |= BMCR_LOOPBACK;
8235 tg3_writephy(tp, MII_BMCR, bmcr);
8237 /* The write needs to be flushed for the FETs */
8238 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8239 tg3_readphy(tp, MII_BMCR, &bmcr);
8243 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8244 tg3_asic_rev(tp) == ASIC_REV_5785) {
8245 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8246 MII_TG3_FET_PTEST_FRC_TX_LINK |
8247 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8249 /* The write needs to be flushed for the AC131 */
8250 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8253 /* Reset to prevent losing 1st rx packet intermittently */
8254 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8255 tg3_flag(tp, 5780_CLASS)) {
8256 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8258 tw32_f(MAC_RX_MODE, tp->rx_mode);
8261 mac_mode = tp->mac_mode &
8262 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8263 if (speed == SPEED_1000)
8264 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8266 mac_mode |= MAC_MODE_PORT_MODE_MII;
8268 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8269 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8271 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8272 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8273 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8274 mac_mode |= MAC_MODE_LINK_POLARITY;
8276 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8277 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8280 tw32(MAC_MODE, mac_mode);
8286 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8288 struct tg3 *tp = netdev_priv(dev);
8290 if (features & NETIF_F_LOOPBACK) {
8291 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8294 spin_lock_bh(&tp->lock);
8295 tg3_mac_loopback(tp, true);
8296 netif_carrier_on(tp->dev);
8297 spin_unlock_bh(&tp->lock);
8298 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8300 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8303 spin_lock_bh(&tp->lock);
8304 tg3_mac_loopback(tp, false);
8305 /* Force link status check */
8306 tg3_setup_phy(tp, true);
8307 spin_unlock_bh(&tp->lock);
8308 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8312 static netdev_features_t tg3_fix_features(struct net_device *dev,
8313 netdev_features_t features)
8315 struct tg3 *tp = netdev_priv(dev);
8317 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8318 features &= ~NETIF_F_ALL_TSO;
8323 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8325 netdev_features_t changed = dev->features ^ features;
8327 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8328 tg3_set_loopback(dev, features);
8333 static void tg3_rx_prodring_free(struct tg3 *tp,
8334 struct tg3_rx_prodring_set *tpr)
8338 if (tpr != &tp->napi[0].prodring) {
8339 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8340 i = (i + 1) & tp->rx_std_ring_mask)
8341 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8344 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8345 for (i = tpr->rx_jmb_cons_idx;
8346 i != tpr->rx_jmb_prod_idx;
8347 i = (i + 1) & tp->rx_jmb_ring_mask) {
8348 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8356 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8357 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8360 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8361 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8362 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8367 /* Initialize rx rings for packet processing.
8369 * The chip has been shut down and the driver detached from
8370 * the networking, so no interrupts or new tx packets will
8371 * end up in the driver. tp->{tx,}lock are held and thus
8374 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8375 struct tg3_rx_prodring_set *tpr)
8377 u32 i, rx_pkt_dma_sz;
8379 tpr->rx_std_cons_idx = 0;
8380 tpr->rx_std_prod_idx = 0;
8381 tpr->rx_jmb_cons_idx = 0;
8382 tpr->rx_jmb_prod_idx = 0;
8384 if (tpr != &tp->napi[0].prodring) {
8385 memset(&tpr->rx_std_buffers[0], 0,
8386 TG3_RX_STD_BUFF_RING_SIZE(tp));
8387 if (tpr->rx_jmb_buffers)
8388 memset(&tpr->rx_jmb_buffers[0], 0,
8389 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8393 /* Zero out all descriptors. */
8394 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8396 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8397 if (tg3_flag(tp, 5780_CLASS) &&
8398 tp->dev->mtu > ETH_DATA_LEN)
8399 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8400 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8402 /* Initialize invariants of the rings, we only set this
8403 * stuff once. This works because the card does not
8404 * write into the rx buffer posting rings.
8406 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8407 struct tg3_rx_buffer_desc *rxd;
8409 rxd = &tpr->rx_std[i];
8410 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8411 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8412 rxd->opaque = (RXD_OPAQUE_RING_STD |
8413 (i << RXD_OPAQUE_INDEX_SHIFT));
8416 /* Now allocate fresh SKBs for each rx ring. */
8417 for (i = 0; i < tp->rx_pending; i++) {
8418 unsigned int frag_size;
8420 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8422 netdev_warn(tp->dev,
8423 "Using a smaller RX standard ring. Only "
8424 "%d out of %d buffers were allocated "
8425 "successfully\n", i, tp->rx_pending);
8433 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8436 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8438 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8441 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8442 struct tg3_rx_buffer_desc *rxd;
8444 rxd = &tpr->rx_jmb[i].std;
8445 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8446 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8448 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8449 (i << RXD_OPAQUE_INDEX_SHIFT));
8452 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8453 unsigned int frag_size;
8455 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8457 netdev_warn(tp->dev,
8458 "Using a smaller RX jumbo ring. Only %d "
8459 "out of %d buffers were allocated "
8460 "successfully\n", i, tp->rx_jumbo_pending);
8463 tp->rx_jumbo_pending = i;
8472 tg3_rx_prodring_free(tp, tpr);
8476 static void tg3_rx_prodring_fini(struct tg3 *tp,
8477 struct tg3_rx_prodring_set *tpr)
8479 kfree(tpr->rx_std_buffers);
8480 tpr->rx_std_buffers = NULL;
8481 kfree(tpr->rx_jmb_buffers);
8482 tpr->rx_jmb_buffers = NULL;
8484 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8485 tpr->rx_std, tpr->rx_std_mapping);
8489 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8490 tpr->rx_jmb, tpr->rx_jmb_mapping);
8495 static int tg3_rx_prodring_init(struct tg3 *tp,
8496 struct tg3_rx_prodring_set *tpr)
8498 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8500 if (!tpr->rx_std_buffers)
8503 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8504 TG3_RX_STD_RING_BYTES(tp),
8505 &tpr->rx_std_mapping,
8510 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8511 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8513 if (!tpr->rx_jmb_buffers)
8516 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8517 TG3_RX_JMB_RING_BYTES(tp),
8518 &tpr->rx_jmb_mapping,
8527 tg3_rx_prodring_fini(tp, tpr);
8531 /* Free up pending packets in all rx/tx rings.
8533 * The chip has been shut down and the driver detached from
8534 * the networking, so no interrupts or new tx packets will
8535 * end up in the driver. tp->{tx,}lock is not held and we are not
8536 * in an interrupt context and thus may sleep.
8538 static void tg3_free_rings(struct tg3 *tp)
8542 for (j = 0; j < tp->irq_cnt; j++) {
8543 struct tg3_napi *tnapi = &tp->napi[j];
8545 tg3_rx_prodring_free(tp, &tnapi->prodring);
8547 if (!tnapi->tx_buffers)
8550 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8551 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8556 tg3_tx_skb_unmap(tnapi, i,
8557 skb_shinfo(skb)->nr_frags - 1);
8559 dev_consume_skb_any(skb);
8561 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8565 /* Initialize tx/rx rings for packet processing.
8567 * The chip has been shut down and the driver detached from
8568 * the networking, so no interrupts or new tx packets will
8569 * end up in the driver. tp->{tx,}lock are held and thus
8572 static int tg3_init_rings(struct tg3 *tp)
8576 /* Free up all the SKBs. */
8579 for (i = 0; i < tp->irq_cnt; i++) {
8580 struct tg3_napi *tnapi = &tp->napi[i];
8582 tnapi->last_tag = 0;
8583 tnapi->last_irq_tag = 0;
8584 tnapi->hw_status->status = 0;
8585 tnapi->hw_status->status_tag = 0;
8586 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8591 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8593 tnapi->rx_rcb_ptr = 0;
8595 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8597 if (tnapi->prodring.rx_std &&
8598 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8607 static void tg3_mem_tx_release(struct tg3 *tp)
8611 for (i = 0; i < tp->irq_max; i++) {
8612 struct tg3_napi *tnapi = &tp->napi[i];
8614 if (tnapi->tx_ring) {
8615 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8616 tnapi->tx_ring, tnapi->tx_desc_mapping);
8617 tnapi->tx_ring = NULL;
8620 kfree(tnapi->tx_buffers);
8621 tnapi->tx_buffers = NULL;
8625 static int tg3_mem_tx_acquire(struct tg3 *tp)
8628 struct tg3_napi *tnapi = &tp->napi[0];
8630 /* If multivector TSS is enabled, vector 0 does not handle
8631 * tx interrupts. Don't allocate any resources for it.
8633 if (tg3_flag(tp, ENABLE_TSS))
8636 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8637 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE,
8638 sizeof(struct tg3_tx_ring_info),
8640 if (!tnapi->tx_buffers)
8643 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8645 &tnapi->tx_desc_mapping,
8647 if (!tnapi->tx_ring)
8654 tg3_mem_tx_release(tp);
8658 static void tg3_mem_rx_release(struct tg3 *tp)
8662 for (i = 0; i < tp->irq_max; i++) {
8663 struct tg3_napi *tnapi = &tp->napi[i];
8665 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8670 dma_free_coherent(&tp->pdev->dev,
8671 TG3_RX_RCB_RING_BYTES(tp),
8673 tnapi->rx_rcb_mapping);
8674 tnapi->rx_rcb = NULL;
8678 static int tg3_mem_rx_acquire(struct tg3 *tp)
8680 unsigned int i, limit;
8682 limit = tp->rxq_cnt;
8684 /* If RSS is enabled, we need a (dummy) producer ring
8685 * set on vector zero. This is the true hw prodring.
8687 if (tg3_flag(tp, ENABLE_RSS))
8690 for (i = 0; i < limit; i++) {
8691 struct tg3_napi *tnapi = &tp->napi[i];
8693 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8696 /* If multivector RSS is enabled, vector 0
8697 * does not handle rx or tx interrupts.
8698 * Don't allocate any resources for it.
8700 if (!i && tg3_flag(tp, ENABLE_RSS))
8703 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
8704 TG3_RX_RCB_RING_BYTES(tp),
8705 &tnapi->rx_rcb_mapping,
8714 tg3_mem_rx_release(tp);
8719 * Must not be invoked with interrupt sources disabled and
8720 * the hardware shutdown down.
8722 static void tg3_free_consistent(struct tg3 *tp)
8726 for (i = 0; i < tp->irq_cnt; i++) {
8727 struct tg3_napi *tnapi = &tp->napi[i];
8729 if (tnapi->hw_status) {
8730 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8732 tnapi->status_mapping);
8733 tnapi->hw_status = NULL;
8737 tg3_mem_rx_release(tp);
8738 tg3_mem_tx_release(tp);
8740 /* tp->hw_stats can be referenced safely:
8741 * 1. under rtnl_lock
8742 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
8745 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8746 tp->hw_stats, tp->stats_mapping);
8747 tp->hw_stats = NULL;
8752 * Must not be invoked with interrupt sources disabled and
8753 * the hardware shutdown down. Can sleep.
8755 static int tg3_alloc_consistent(struct tg3 *tp)
8759 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8760 sizeof(struct tg3_hw_stats),
8761 &tp->stats_mapping, GFP_KERNEL);
8765 for (i = 0; i < tp->irq_cnt; i++) {
8766 struct tg3_napi *tnapi = &tp->napi[i];
8767 struct tg3_hw_status *sblk;
8769 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8771 &tnapi->status_mapping,
8773 if (!tnapi->hw_status)
8776 sblk = tnapi->hw_status;
8778 if (tg3_flag(tp, ENABLE_RSS)) {
8779 u16 *prodptr = NULL;
8782 * When RSS is enabled, the status block format changes
8783 * slightly. The "rx_jumbo_consumer", "reserved",
8784 * and "rx_mini_consumer" members get mapped to the
8785 * other three rx return ring producer indexes.
8789 prodptr = &sblk->idx[0].rx_producer;
8792 prodptr = &sblk->rx_jumbo_consumer;
8795 prodptr = &sblk->reserved;
8798 prodptr = &sblk->rx_mini_consumer;
8801 tnapi->rx_rcb_prod_idx = prodptr;
8803 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8807 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8813 tg3_free_consistent(tp);
8817 #define MAX_WAIT_CNT 1000
8819 /* To stop a block, clear the enable bit and poll till it
8820 * clears. tp->lock is held.
8822 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8827 if (tg3_flag(tp, 5705_PLUS)) {
8834 /* We can't enable/disable these bits of the
8835 * 5705/5750, just say success.
8848 for (i = 0; i < MAX_WAIT_CNT; i++) {
8849 if (pci_channel_offline(tp->pdev)) {
8850 dev_err(&tp->pdev->dev,
8851 "tg3_stop_block device offline, "
8852 "ofs=%lx enable_bit=%x\n",
8859 if ((val & enable_bit) == 0)
8863 if (i == MAX_WAIT_CNT && !silent) {
8864 dev_err(&tp->pdev->dev,
8865 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8873 /* tp->lock is held. */
8874 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8878 tg3_disable_ints(tp);
8880 if (pci_channel_offline(tp->pdev)) {
8881 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8882 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8887 tp->rx_mode &= ~RX_MODE_ENABLE;
8888 tw32_f(MAC_RX_MODE, tp->rx_mode);
8891 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8892 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8893 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8894 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8895 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8896 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8898 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8899 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8900 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8901 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8902 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8903 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8904 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8906 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8907 tw32_f(MAC_MODE, tp->mac_mode);
8910 tp->tx_mode &= ~TX_MODE_ENABLE;
8911 tw32_f(MAC_TX_MODE, tp->tx_mode);
8913 for (i = 0; i < MAX_WAIT_CNT; i++) {
8915 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8918 if (i >= MAX_WAIT_CNT) {
8919 dev_err(&tp->pdev->dev,
8920 "%s timed out, TX_MODE_ENABLE will not clear "
8921 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8925 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8926 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8927 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8929 tw32(FTQ_RESET, 0xffffffff);
8930 tw32(FTQ_RESET, 0x00000000);
8932 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8933 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8936 for (i = 0; i < tp->irq_cnt; i++) {
8937 struct tg3_napi *tnapi = &tp->napi[i];
8938 if (tnapi->hw_status)
8939 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8945 /* Save PCI command register before chip reset */
8946 static void tg3_save_pci_state(struct tg3 *tp)
8948 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8951 /* Restore PCI state after chip reset */
8952 static void tg3_restore_pci_state(struct tg3 *tp)
8956 /* Re-enable indirect register accesses. */
8957 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8958 tp->misc_host_ctrl);
8960 /* Set MAX PCI retry to zero. */
8961 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8962 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8963 tg3_flag(tp, PCIX_MODE))
8964 val |= PCISTATE_RETRY_SAME_DMA;
8965 /* Allow reads and writes to the APE register and memory space. */
8966 if (tg3_flag(tp, ENABLE_APE))
8967 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8968 PCISTATE_ALLOW_APE_SHMEM_WR |
8969 PCISTATE_ALLOW_APE_PSPACE_WR;
8970 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8972 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8974 if (!tg3_flag(tp, PCI_EXPRESS)) {
8975 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8976 tp->pci_cacheline_sz);
8977 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8981 /* Make sure PCI-X relaxed ordering bit is clear. */
8982 if (tg3_flag(tp, PCIX_MODE)) {
8985 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8987 pcix_cmd &= ~PCI_X_CMD_ERO;
8988 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8992 if (tg3_flag(tp, 5780_CLASS)) {
8994 /* Chip reset on 5780 will reset MSI enable bit,
8995 * so need to restore it.
8997 if (tg3_flag(tp, USING_MSI)) {
9000 pci_read_config_word(tp->pdev,
9001 tp->msi_cap + PCI_MSI_FLAGS,
9003 pci_write_config_word(tp->pdev,
9004 tp->msi_cap + PCI_MSI_FLAGS,
9005 ctrl | PCI_MSI_FLAGS_ENABLE);
9006 val = tr32(MSGINT_MODE);
9007 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9012 static void tg3_override_clk(struct tg3 *tp)
9016 switch (tg3_asic_rev(tp)) {
9018 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9019 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9020 TG3_CPMU_MAC_ORIDE_ENABLE);
9025 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9033 static void tg3_restore_clk(struct tg3 *tp)
9037 switch (tg3_asic_rev(tp)) {
9039 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9040 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9041 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9046 val = tr32(TG3_CPMU_CLCK_ORIDE);
9047 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9055 /* tp->lock is held. */
9056 static int tg3_chip_reset(struct tg3 *tp)
9057 __releases(tp->lock)
9058 __acquires(tp->lock)
9061 void (*write_op)(struct tg3 *, u32, u32);
9064 if (!pci_device_is_present(tp->pdev))
9069 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9071 /* No matching tg3_nvram_unlock() after this because
9072 * chip reset below will undo the nvram lock.
9074 tp->nvram_lock_cnt = 0;
9076 /* GRC_MISC_CFG core clock reset will clear the memory
9077 * enable bit in PCI register 4 and the MSI enable bit
9078 * on some chips, so we save relevant registers here.
9080 tg3_save_pci_state(tp);
9082 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9083 tg3_flag(tp, 5755_PLUS))
9084 tw32(GRC_FASTBOOT_PC, 0);
9087 * We must avoid the readl() that normally takes place.
9088 * It locks machines, causes machine checks, and other
9089 * fun things. So, temporarily disable the 5701
9090 * hardware workaround, while we do the reset.
9092 write_op = tp->write32;
9093 if (write_op == tg3_write_flush_reg32)
9094 tp->write32 = tg3_write32;
9096 /* Prevent the irq handler from reading or writing PCI registers
9097 * during chip reset when the memory enable bit in the PCI command
9098 * register may be cleared. The chip does not generate interrupt
9099 * at this time, but the irq handler may still be called due to irq
9100 * sharing or irqpoll.
9102 tg3_flag_set(tp, CHIP_RESETTING);
9103 for (i = 0; i < tp->irq_cnt; i++) {
9104 struct tg3_napi *tnapi = &tp->napi[i];
9105 if (tnapi->hw_status) {
9106 tnapi->hw_status->status = 0;
9107 tnapi->hw_status->status_tag = 0;
9109 tnapi->last_tag = 0;
9110 tnapi->last_irq_tag = 0;
9114 tg3_full_unlock(tp);
9116 for (i = 0; i < tp->irq_cnt; i++)
9117 synchronize_irq(tp->napi[i].irq_vec);
9119 tg3_full_lock(tp, 0);
9121 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9122 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9123 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9127 val = GRC_MISC_CFG_CORECLK_RESET;
9129 if (tg3_flag(tp, PCI_EXPRESS)) {
9130 /* Force PCIe 1.0a mode */
9131 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9132 !tg3_flag(tp, 57765_PLUS) &&
9133 tr32(TG3_PCIE_PHY_TSTCTL) ==
9134 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9135 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9137 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9138 tw32(GRC_MISC_CFG, (1 << 29));
9143 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9144 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9145 tw32(GRC_VCPU_EXT_CTRL,
9146 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9149 /* Set the clock to the highest frequency to avoid timeouts. With link
9150 * aware mode, the clock speed could be slow and bootcode does not
9151 * complete within the expected time. Override the clock to allow the
9152 * bootcode to finish sooner and then restore it.
9154 tg3_override_clk(tp);
9156 /* Manage gphy power for all CPMU absent PCIe devices. */
9157 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9158 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9160 tw32(GRC_MISC_CFG, val);
9162 /* restore 5701 hardware bug workaround write method */
9163 tp->write32 = write_op;
9165 /* Unfortunately, we have to delay before the PCI read back.
9166 * Some 575X chips even will not respond to a PCI cfg access
9167 * when the reset command is given to the chip.
9169 * How do these hardware designers expect things to work
9170 * properly if the PCI write is posted for a long period
9171 * of time? It is always necessary to have some method by
9172 * which a register read back can occur to push the write
9173 * out which does the reset.
9175 * For most tg3 variants the trick below was working.
9180 /* Flush PCI posted writes. The normal MMIO registers
9181 * are inaccessible at this time so this is the only
9182 * way to make this reliably (actually, this is no longer
9183 * the case, see above). I tried to use indirect
9184 * register read/write but this upset some 5701 variants.
9186 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9190 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9193 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9197 /* Wait for link training to complete. */
9198 for (j = 0; j < 5000; j++)
9201 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9202 pci_write_config_dword(tp->pdev, 0xc4,
9203 cfg_val | (1 << 15));
9206 /* Clear the "no snoop" and "relaxed ordering" bits. */
9207 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9209 * Older PCIe devices only support the 128 byte
9210 * MPS setting. Enforce the restriction.
9212 if (!tg3_flag(tp, CPMU_PRESENT))
9213 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9214 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9216 /* Clear error status */
9217 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9218 PCI_EXP_DEVSTA_CED |
9219 PCI_EXP_DEVSTA_NFED |
9220 PCI_EXP_DEVSTA_FED |
9221 PCI_EXP_DEVSTA_URD);
9224 tg3_restore_pci_state(tp);
9226 tg3_flag_clear(tp, CHIP_RESETTING);
9227 tg3_flag_clear(tp, ERROR_PROCESSED);
9230 if (tg3_flag(tp, 5780_CLASS))
9231 val = tr32(MEMARB_MODE);
9232 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9234 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9236 tw32(0x5000, 0x400);
9239 if (tg3_flag(tp, IS_SSB_CORE)) {
9241 * BCM4785: In order to avoid repercussions from using
9242 * potentially defective internal ROM, stop the Rx RISC CPU,
9243 * which is not required.
9246 tg3_halt_cpu(tp, RX_CPU_BASE);
9249 err = tg3_poll_fw(tp);
9253 tw32(GRC_MODE, tp->grc_mode);
9255 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9258 tw32(0xc4, val | (1 << 15));
9261 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9262 tg3_asic_rev(tp) == ASIC_REV_5705) {
9263 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9264 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9265 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9266 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9269 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9270 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9272 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9273 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9278 tw32_f(MAC_MODE, val);
9281 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9285 if (tg3_flag(tp, PCI_EXPRESS) &&
9286 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9287 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9288 !tg3_flag(tp, 57765_PLUS)) {
9291 tw32(0x7c00, val | (1 << 25));
9294 tg3_restore_clk(tp);
9296 /* Increase the core clock speed to fix tx timeout issue for 5762
9297 * with 100Mbps link speed.
9299 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
9300 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9301 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9302 TG3_CPMU_MAC_ORIDE_ENABLE);
9305 /* Reprobe ASF enable state. */
9306 tg3_flag_clear(tp, ENABLE_ASF);
9307 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9308 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9310 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9311 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9312 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9315 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9316 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9317 tg3_flag_set(tp, ENABLE_ASF);
9318 tp->last_event_jiffies = jiffies;
9319 if (tg3_flag(tp, 5750_PLUS))
9320 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9322 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9323 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9324 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9325 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9326 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9333 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9334 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9335 static void __tg3_set_rx_mode(struct net_device *);
9337 /* tp->lock is held. */
9338 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9344 tg3_write_sig_pre_reset(tp, kind);
9346 tg3_abort_hw(tp, silent);
9347 err = tg3_chip_reset(tp);
9349 __tg3_set_mac_addr(tp, false);
9351 tg3_write_sig_legacy(tp, kind);
9352 tg3_write_sig_post_reset(tp, kind);
9355 /* Save the stats across chip resets... */
9356 tg3_get_nstats(tp, &tp->net_stats_prev);
9357 tg3_get_estats(tp, &tp->estats_prev);
9359 /* And make sure the next sample is new data */
9360 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9362 for (i = 0; i < TG3_IRQ_MAX_VECS; ++i) {
9363 struct tg3_napi *tnapi = &tp->napi[i];
9365 tnapi->rx_dropped = 0;
9366 tnapi->tx_dropped = 0;
9373 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9375 struct tg3 *tp = netdev_priv(dev);
9376 struct sockaddr *addr = p;
9378 bool skip_mac_1 = false;
9380 if (!is_valid_ether_addr(addr->sa_data))
9381 return -EADDRNOTAVAIL;
9383 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9385 if (!netif_running(dev))
9388 if (tg3_flag(tp, ENABLE_ASF)) {
9389 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9391 addr0_high = tr32(MAC_ADDR_0_HIGH);
9392 addr0_low = tr32(MAC_ADDR_0_LOW);
9393 addr1_high = tr32(MAC_ADDR_1_HIGH);
9394 addr1_low = tr32(MAC_ADDR_1_LOW);
9396 /* Skip MAC addr 1 if ASF is using it. */
9397 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9398 !(addr1_high == 0 && addr1_low == 0))
9401 spin_lock_bh(&tp->lock);
9402 __tg3_set_mac_addr(tp, skip_mac_1);
9403 __tg3_set_rx_mode(dev);
9404 spin_unlock_bh(&tp->lock);
9409 /* tp->lock is held. */
9410 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9411 dma_addr_t mapping, u32 maxlen_flags,
9415 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9416 ((u64) mapping >> 32));
9418 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9419 ((u64) mapping & 0xffffffff));
9421 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9424 if (!tg3_flag(tp, 5705_PLUS))
9426 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9431 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9435 if (!tg3_flag(tp, ENABLE_TSS)) {
9436 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9437 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9438 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9440 tw32(HOSTCC_TXCOL_TICKS, 0);
9441 tw32(HOSTCC_TXMAX_FRAMES, 0);
9442 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9444 for (; i < tp->txq_cnt; i++) {
9447 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9448 tw32(reg, ec->tx_coalesce_usecs);
9449 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9450 tw32(reg, ec->tx_max_coalesced_frames);
9451 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9452 tw32(reg, ec->tx_max_coalesced_frames_irq);
9456 for (; i < tp->irq_max - 1; i++) {
9457 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9458 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9459 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9463 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9466 u32 limit = tp->rxq_cnt;
9468 if (!tg3_flag(tp, ENABLE_RSS)) {
9469 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9470 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9471 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9474 tw32(HOSTCC_RXCOL_TICKS, 0);
9475 tw32(HOSTCC_RXMAX_FRAMES, 0);
9476 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9479 for (; i < limit; i++) {
9482 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9483 tw32(reg, ec->rx_coalesce_usecs);
9484 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9485 tw32(reg, ec->rx_max_coalesced_frames);
9486 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9487 tw32(reg, ec->rx_max_coalesced_frames_irq);
9490 for (; i < tp->irq_max - 1; i++) {
9491 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9492 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9493 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9497 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9499 tg3_coal_tx_init(tp, ec);
9500 tg3_coal_rx_init(tp, ec);
9502 if (!tg3_flag(tp, 5705_PLUS)) {
9503 u32 val = ec->stats_block_coalesce_usecs;
9505 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9506 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9511 tw32(HOSTCC_STAT_COAL_TICKS, val);
9515 /* tp->lock is held. */
9516 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9520 /* Disable all transmit rings but the first. */
9521 if (!tg3_flag(tp, 5705_PLUS))
9522 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9523 else if (tg3_flag(tp, 5717_PLUS))
9524 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9525 else if (tg3_flag(tp, 57765_CLASS) ||
9526 tg3_asic_rev(tp) == ASIC_REV_5762)
9527 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9529 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9531 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9532 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9533 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9534 BDINFO_FLAGS_DISABLED);
9537 /* tp->lock is held. */
9538 static void tg3_tx_rcbs_init(struct tg3 *tp)
9541 u32 txrcb = NIC_SRAM_SEND_RCB;
9543 if (tg3_flag(tp, ENABLE_TSS))
9546 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9547 struct tg3_napi *tnapi = &tp->napi[i];
9549 if (!tnapi->tx_ring)
9552 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9553 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9554 NIC_SRAM_TX_BUFFER_DESC);
9558 /* tp->lock is held. */
9559 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9563 /* Disable all receive return rings but the first. */
9564 if (tg3_flag(tp, 5717_PLUS))
9565 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9566 else if (!tg3_flag(tp, 5705_PLUS))
9567 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9568 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9569 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9570 tg3_flag(tp, 57765_CLASS))
9571 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9573 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9575 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9576 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9577 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9578 BDINFO_FLAGS_DISABLED);
9581 /* tp->lock is held. */
9582 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9585 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9587 if (tg3_flag(tp, ENABLE_RSS))
9590 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9591 struct tg3_napi *tnapi = &tp->napi[i];
9596 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9597 (tp->rx_ret_ring_mask + 1) <<
9598 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9602 /* tp->lock is held. */
9603 static void tg3_rings_reset(struct tg3 *tp)
9607 struct tg3_napi *tnapi = &tp->napi[0];
9609 tg3_tx_rcbs_disable(tp);
9611 tg3_rx_ret_rcbs_disable(tp);
9613 /* Disable interrupts */
9614 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9615 tp->napi[0].chk_msi_cnt = 0;
9616 tp->napi[0].last_rx_cons = 0;
9617 tp->napi[0].last_tx_cons = 0;
9619 /* Zero mailbox registers. */
9620 if (tg3_flag(tp, SUPPORT_MSIX)) {
9621 for (i = 1; i < tp->irq_max; i++) {
9622 tp->napi[i].tx_prod = 0;
9623 tp->napi[i].tx_cons = 0;
9624 if (tg3_flag(tp, ENABLE_TSS))
9625 tw32_mailbox(tp->napi[i].prodmbox, 0);
9626 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9627 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9628 tp->napi[i].chk_msi_cnt = 0;
9629 tp->napi[i].last_rx_cons = 0;
9630 tp->napi[i].last_tx_cons = 0;
9632 if (!tg3_flag(tp, ENABLE_TSS))
9633 tw32_mailbox(tp->napi[0].prodmbox, 0);
9635 tp->napi[0].tx_prod = 0;
9636 tp->napi[0].tx_cons = 0;
9637 tw32_mailbox(tp->napi[0].prodmbox, 0);
9638 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9641 /* Make sure the NIC-based send BD rings are disabled. */
9642 if (!tg3_flag(tp, 5705_PLUS)) {
9643 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9644 for (i = 0; i < 16; i++)
9645 tw32_tx_mbox(mbox + i * 8, 0);
9648 /* Clear status block in ram. */
9649 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9651 /* Set status block DMA address */
9652 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9653 ((u64) tnapi->status_mapping >> 32));
9654 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9655 ((u64) tnapi->status_mapping & 0xffffffff));
9657 stblk = HOSTCC_STATBLCK_RING1;
9659 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9660 u64 mapping = (u64)tnapi->status_mapping;
9661 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9662 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9665 /* Clear status block in ram. */
9666 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9669 tg3_tx_rcbs_init(tp);
9670 tg3_rx_ret_rcbs_init(tp);
9673 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9675 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9677 if (!tg3_flag(tp, 5750_PLUS) ||
9678 tg3_flag(tp, 5780_CLASS) ||
9679 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9680 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9681 tg3_flag(tp, 57765_PLUS))
9682 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9683 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9684 tg3_asic_rev(tp) == ASIC_REV_5787)
9685 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9687 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9689 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9690 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9692 val = min(nic_rep_thresh, host_rep_thresh);
9693 tw32(RCVBDI_STD_THRESH, val);
9695 if (tg3_flag(tp, 57765_PLUS))
9696 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9698 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9701 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9703 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9705 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9706 tw32(RCVBDI_JUMBO_THRESH, val);
9708 if (tg3_flag(tp, 57765_PLUS))
9709 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9712 static inline u32 calc_crc(unsigned char *buf, int len)
9720 for (j = 0; j < len; j++) {
9723 for (k = 0; k < 8; k++) {
9729 reg ^= CRC32_POLY_LE;
9736 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9738 /* accept or reject all multicast frames */
9739 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9740 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9741 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9742 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9745 static void __tg3_set_rx_mode(struct net_device *dev)
9747 struct tg3 *tp = netdev_priv(dev);
9750 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9751 RX_MODE_KEEP_VLAN_TAG);
9753 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9754 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9757 if (!tg3_flag(tp, ENABLE_ASF))
9758 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9761 if (dev->flags & IFF_PROMISC) {
9762 /* Promiscuous mode. */
9763 rx_mode |= RX_MODE_PROMISC;
9764 } else if (dev->flags & IFF_ALLMULTI) {
9765 /* Accept all multicast. */
9766 tg3_set_multi(tp, 1);
9767 } else if (netdev_mc_empty(dev)) {
9768 /* Reject all multicast. */
9769 tg3_set_multi(tp, 0);
9771 /* Accept one or more multicast(s). */
9772 struct netdev_hw_addr *ha;
9773 u32 mc_filter[4] = { 0, };
9778 netdev_for_each_mc_addr(ha, dev) {
9779 crc = calc_crc(ha->addr, ETH_ALEN);
9781 regidx = (bit & 0x60) >> 5;
9783 mc_filter[regidx] |= (1 << bit);
9786 tw32(MAC_HASH_REG_0, mc_filter[0]);
9787 tw32(MAC_HASH_REG_1, mc_filter[1]);
9788 tw32(MAC_HASH_REG_2, mc_filter[2]);
9789 tw32(MAC_HASH_REG_3, mc_filter[3]);
9792 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9793 rx_mode |= RX_MODE_PROMISC;
9794 } else if (!(dev->flags & IFF_PROMISC)) {
9795 /* Add all entries into to the mac addr filter list */
9797 struct netdev_hw_addr *ha;
9799 netdev_for_each_uc_addr(ha, dev) {
9800 __tg3_set_one_mac_addr(tp, ha->addr,
9801 i + TG3_UCAST_ADDR_IDX(tp));
9806 if (rx_mode != tp->rx_mode) {
9807 tp->rx_mode = rx_mode;
9808 tw32_f(MAC_RX_MODE, rx_mode);
9813 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9817 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9818 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9821 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9825 if (!tg3_flag(tp, SUPPORT_MSIX))
9828 if (tp->rxq_cnt == 1) {
9829 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9833 /* Validate table against current IRQ count */
9834 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9835 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9839 if (i != TG3_RSS_INDIR_TBL_SIZE)
9840 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9843 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9846 u32 reg = MAC_RSS_INDIR_TBL_0;
9848 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9849 u32 val = tp->rss_ind_tbl[i];
9851 for (; i % 8; i++) {
9853 val |= tp->rss_ind_tbl[i];
9860 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9862 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9863 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9865 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9868 /* tp->lock is held. */
9869 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9871 u32 val, rdmac_mode;
9873 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9875 tg3_disable_ints(tp);
9879 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9881 if (tg3_flag(tp, INIT_COMPLETE))
9882 tg3_abort_hw(tp, 1);
9884 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9885 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9886 tg3_phy_pull_config(tp);
9887 tg3_eee_pull_config(tp, NULL);
9888 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9891 /* Enable MAC control of LPI */
9892 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9898 err = tg3_chip_reset(tp);
9902 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9904 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9905 val = tr32(TG3_CPMU_CTRL);
9906 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9907 tw32(TG3_CPMU_CTRL, val);
9909 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9910 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9911 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9912 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9914 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9915 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9916 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9917 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9919 val = tr32(TG3_CPMU_HST_ACC);
9920 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9921 val |= CPMU_HST_ACC_MACCLK_6_25;
9922 tw32(TG3_CPMU_HST_ACC, val);
9925 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9926 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9927 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9928 PCIE_PWR_MGMT_L1_THRESH_4MS;
9929 tw32(PCIE_PWR_MGMT_THRESH, val);
9931 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9932 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9934 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9936 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9937 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9940 if (tg3_flag(tp, L1PLLPD_EN)) {
9941 u32 grc_mode = tr32(GRC_MODE);
9943 /* Access the lower 1K of PL PCIE block registers. */
9944 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9945 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9947 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9948 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9949 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9951 tw32(GRC_MODE, grc_mode);
9954 if (tg3_flag(tp, 57765_CLASS)) {
9955 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9956 u32 grc_mode = tr32(GRC_MODE);
9958 /* Access the lower 1K of PL PCIE block registers. */
9959 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9960 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9962 val = tr32(TG3_PCIE_TLDLPL_PORT +
9963 TG3_PCIE_PL_LO_PHYCTL5);
9964 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9965 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9967 tw32(GRC_MODE, grc_mode);
9970 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9973 /* Fix transmit hangs */
9974 val = tr32(TG3_CPMU_PADRNG_CTL);
9975 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9976 tw32(TG3_CPMU_PADRNG_CTL, val);
9978 grc_mode = tr32(GRC_MODE);
9980 /* Access the lower 1K of DL PCIE block registers. */
9981 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9982 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9984 val = tr32(TG3_PCIE_TLDLPL_PORT +
9985 TG3_PCIE_DL_LO_FTSMAX);
9986 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9987 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9988 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9990 tw32(GRC_MODE, grc_mode);
9993 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9994 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9995 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9996 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9999 /* This works around an issue with Athlon chipsets on
10000 * B3 tigon3 silicon. This bit has no effect on any
10001 * other revision. But do not set this on PCI Express
10002 * chips and don't even touch the clocks if the CPMU is present.
10004 if (!tg3_flag(tp, CPMU_PRESENT)) {
10005 if (!tg3_flag(tp, PCI_EXPRESS))
10006 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
10007 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10010 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
10011 tg3_flag(tp, PCIX_MODE)) {
10012 val = tr32(TG3PCI_PCISTATE);
10013 val |= PCISTATE_RETRY_SAME_DMA;
10014 tw32(TG3PCI_PCISTATE, val);
10017 if (tg3_flag(tp, ENABLE_APE)) {
10018 /* Allow reads and writes to the
10019 * APE register and memory space.
10021 val = tr32(TG3PCI_PCISTATE);
10022 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
10023 PCISTATE_ALLOW_APE_SHMEM_WR |
10024 PCISTATE_ALLOW_APE_PSPACE_WR;
10025 tw32(TG3PCI_PCISTATE, val);
10028 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
10029 /* Enable some hw fixes. */
10030 val = tr32(TG3PCI_MSI_DATA);
10031 val |= (1 << 26) | (1 << 28) | (1 << 29);
10032 tw32(TG3PCI_MSI_DATA, val);
10035 /* Descriptor ring init may make accesses to the
10036 * NIC SRAM area to setup the TX descriptors, so we
10037 * can only do this after the hardware has been
10038 * successfully reset.
10040 err = tg3_init_rings(tp);
10044 if (tg3_flag(tp, 57765_PLUS)) {
10045 val = tr32(TG3PCI_DMA_RW_CTRL) &
10046 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
10047 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10048 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10049 if (!tg3_flag(tp, 57765_CLASS) &&
10050 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10051 tg3_asic_rev(tp) != ASIC_REV_5762)
10052 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10053 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10054 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10055 tg3_asic_rev(tp) != ASIC_REV_5761) {
10056 /* This value is determined during the probe time DMA
10057 * engine test, tg3_test_dma.
10059 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10062 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10063 GRC_MODE_4X_NIC_SEND_RINGS |
10064 GRC_MODE_NO_TX_PHDR_CSUM |
10065 GRC_MODE_NO_RX_PHDR_CSUM);
10066 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10068 /* Pseudo-header checksum is done by hardware logic and not
10069 * the offload processers, so make the chip do the pseudo-
10070 * header checksums on receive. For transmit it is more
10071 * convenient to do the pseudo-header checksum in software
10072 * as Linux does that on transmit for us in all cases.
10074 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10076 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10078 tw32(TG3_RX_PTP_CTL,
10079 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10081 if (tg3_flag(tp, PTP_CAPABLE))
10082 val |= GRC_MODE_TIME_SYNC_ENABLE;
10084 tw32(GRC_MODE, tp->grc_mode | val);
10086 /* On one of the AMD platform, MRRS is restricted to 4000 because of
10087 * south bridge limitation. As a workaround, Driver is setting MRRS
10088 * to 2048 instead of default 4096.
10090 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10091 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
10092 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
10093 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10096 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10097 val = tr32(GRC_MISC_CFG);
10099 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10100 tw32(GRC_MISC_CFG, val);
10102 /* Initialize MBUF/DESC pool. */
10103 if (tg3_flag(tp, 5750_PLUS)) {
10105 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10106 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10107 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10108 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10110 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10111 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10112 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10113 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10116 fw_len = tp->fw_len;
10117 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10118 tw32(BUFMGR_MB_POOL_ADDR,
10119 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10120 tw32(BUFMGR_MB_POOL_SIZE,
10121 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10124 if (tp->dev->mtu <= ETH_DATA_LEN) {
10125 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10126 tp->bufmgr_config.mbuf_read_dma_low_water);
10127 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10128 tp->bufmgr_config.mbuf_mac_rx_low_water);
10129 tw32(BUFMGR_MB_HIGH_WATER,
10130 tp->bufmgr_config.mbuf_high_water);
10132 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10133 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10134 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10135 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10136 tw32(BUFMGR_MB_HIGH_WATER,
10137 tp->bufmgr_config.mbuf_high_water_jumbo);
10139 tw32(BUFMGR_DMA_LOW_WATER,
10140 tp->bufmgr_config.dma_low_water);
10141 tw32(BUFMGR_DMA_HIGH_WATER,
10142 tp->bufmgr_config.dma_high_water);
10144 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10145 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10146 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10147 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10148 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10149 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10150 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10151 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10152 tw32(BUFMGR_MODE, val);
10153 for (i = 0; i < 2000; i++) {
10154 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10159 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10163 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10164 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10166 tg3_setup_rxbd_thresholds(tp);
10168 /* Initialize TG3_BDINFO's at:
10169 * RCVDBDI_STD_BD: standard eth size rx ring
10170 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10171 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10174 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10175 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10176 * ring attribute flags
10177 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10179 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10180 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10182 * The size of each ring is fixed in the firmware, but the location is
10185 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10186 ((u64) tpr->rx_std_mapping >> 32));
10187 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10188 ((u64) tpr->rx_std_mapping & 0xffffffff));
10189 if (!tg3_flag(tp, 5717_PLUS))
10190 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10191 NIC_SRAM_RX_BUFFER_DESC);
10193 /* Disable the mini ring */
10194 if (!tg3_flag(tp, 5705_PLUS))
10195 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10196 BDINFO_FLAGS_DISABLED);
10198 /* Program the jumbo buffer descriptor ring control
10199 * blocks on those devices that have them.
10201 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10202 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10204 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10205 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10206 ((u64) tpr->rx_jmb_mapping >> 32));
10207 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10208 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10209 val = TG3_RX_JMB_RING_SIZE(tp) <<
10210 BDINFO_FLAGS_MAXLEN_SHIFT;
10211 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10212 val | BDINFO_FLAGS_USE_EXT_RECV);
10213 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10214 tg3_flag(tp, 57765_CLASS) ||
10215 tg3_asic_rev(tp) == ASIC_REV_5762)
10216 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10217 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10219 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10220 BDINFO_FLAGS_DISABLED);
10223 if (tg3_flag(tp, 57765_PLUS)) {
10224 val = TG3_RX_STD_RING_SIZE(tp);
10225 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10226 val |= (TG3_RX_STD_DMA_SZ << 2);
10228 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10230 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10232 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10234 tpr->rx_std_prod_idx = tp->rx_pending;
10235 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10237 tpr->rx_jmb_prod_idx =
10238 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10239 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10241 tg3_rings_reset(tp);
10243 /* Initialize MAC address and backoff seed. */
10244 __tg3_set_mac_addr(tp, false);
10246 /* MTU + ethernet header + FCS + optional VLAN tag */
10247 tw32(MAC_RX_MTU_SIZE,
10248 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10250 /* The slot time is changed by tg3_setup_phy if we
10251 * run at gigabit with half duplex.
10253 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10254 (6 << TX_LENGTHS_IPG_SHIFT) |
10255 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10257 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10258 tg3_asic_rev(tp) == ASIC_REV_5762)
10259 val |= tr32(MAC_TX_LENGTHS) &
10260 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10261 TX_LENGTHS_CNT_DWN_VAL_MSK);
10263 tw32(MAC_TX_LENGTHS, val);
10265 /* Receive rules. */
10266 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10267 tw32(RCVLPC_CONFIG, 0x0181);
10269 /* Calculate RDMAC_MODE setting early, we need it to determine
10270 * the RCVLPC_STATE_ENABLE mask.
10272 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10273 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10274 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10275 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10276 RDMAC_MODE_LNGREAD_ENAB);
10278 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10279 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10281 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10282 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10283 tg3_asic_rev(tp) == ASIC_REV_57780)
10284 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10285 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10286 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10288 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10289 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10290 if (tg3_flag(tp, TSO_CAPABLE) &&
10291 tg3_asic_rev(tp) == ASIC_REV_5705) {
10292 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10293 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10294 !tg3_flag(tp, IS_5788)) {
10295 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10299 if (tg3_flag(tp, PCI_EXPRESS))
10300 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10302 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10304 if (tp->dev->mtu <= ETH_DATA_LEN) {
10305 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10306 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10310 if (tg3_flag(tp, HW_TSO_1) ||
10311 tg3_flag(tp, HW_TSO_2) ||
10312 tg3_flag(tp, HW_TSO_3))
10313 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10315 if (tg3_flag(tp, 57765_PLUS) ||
10316 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10317 tg3_asic_rev(tp) == ASIC_REV_57780)
10318 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10320 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10321 tg3_asic_rev(tp) == ASIC_REV_5762)
10322 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10324 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10325 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10326 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10327 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10328 tg3_flag(tp, 57765_PLUS)) {
10331 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10332 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10334 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10336 val = tr32(tgtreg);
10337 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10338 tg3_asic_rev(tp) == ASIC_REV_5762) {
10339 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10340 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10341 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10342 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10343 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10344 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10346 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10349 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10350 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10351 tg3_asic_rev(tp) == ASIC_REV_5762) {
10354 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10355 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10357 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10359 val = tr32(tgtreg);
10361 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10362 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10365 /* Receive/send statistics. */
10366 if (tg3_flag(tp, 5750_PLUS)) {
10367 val = tr32(RCVLPC_STATS_ENABLE);
10368 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10369 tw32(RCVLPC_STATS_ENABLE, val);
10370 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10371 tg3_flag(tp, TSO_CAPABLE)) {
10372 val = tr32(RCVLPC_STATS_ENABLE);
10373 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10374 tw32(RCVLPC_STATS_ENABLE, val);
10376 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10378 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10379 tw32(SNDDATAI_STATSENAB, 0xffffff);
10380 tw32(SNDDATAI_STATSCTRL,
10381 (SNDDATAI_SCTRL_ENABLE |
10382 SNDDATAI_SCTRL_FASTUPD));
10384 /* Setup host coalescing engine. */
10385 tw32(HOSTCC_MODE, 0);
10386 for (i = 0; i < 2000; i++) {
10387 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10392 __tg3_set_coalesce(tp, &tp->coal);
10394 if (!tg3_flag(tp, 5705_PLUS)) {
10395 /* Status/statistics block address. See tg3_timer,
10396 * the tg3_periodic_fetch_stats call there, and
10397 * tg3_get_stats to see how this works for 5705/5750 chips.
10399 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10400 ((u64) tp->stats_mapping >> 32));
10401 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10402 ((u64) tp->stats_mapping & 0xffffffff));
10403 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10405 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10407 /* Clear statistics and status block memory areas */
10408 for (i = NIC_SRAM_STATS_BLK;
10409 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10410 i += sizeof(u32)) {
10411 tg3_write_mem(tp, i, 0);
10416 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10418 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10419 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10420 if (!tg3_flag(tp, 5705_PLUS))
10421 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10423 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10424 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10425 /* reset to prevent losing 1st rx packet intermittently */
10426 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10430 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10431 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10432 MAC_MODE_FHDE_ENABLE;
10433 if (tg3_flag(tp, ENABLE_APE))
10434 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10435 if (!tg3_flag(tp, 5705_PLUS) &&
10436 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10437 tg3_asic_rev(tp) != ASIC_REV_5700)
10438 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10439 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10442 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10443 * If TG3_FLAG_IS_NIC is zero, we should read the
10444 * register to preserve the GPIO settings for LOMs. The GPIOs,
10445 * whether used as inputs or outputs, are set by boot code after
10448 if (!tg3_flag(tp, IS_NIC)) {
10451 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10452 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10453 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10455 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10456 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10457 GRC_LCLCTRL_GPIO_OUTPUT3;
10459 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10460 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10462 tp->grc_local_ctrl &= ~gpio_mask;
10463 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10465 /* GPIO1 must be driven high for eeprom write protect */
10466 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10467 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10468 GRC_LCLCTRL_GPIO_OUTPUT1);
10470 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10473 if (tg3_flag(tp, USING_MSIX)) {
10474 val = tr32(MSGINT_MODE);
10475 val |= MSGINT_MODE_ENABLE;
10476 if (tp->irq_cnt > 1)
10477 val |= MSGINT_MODE_MULTIVEC_EN;
10478 if (!tg3_flag(tp, 1SHOT_MSI))
10479 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10480 tw32(MSGINT_MODE, val);
10483 if (!tg3_flag(tp, 5705_PLUS)) {
10484 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10488 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10489 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10490 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10491 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10492 WDMAC_MODE_LNGREAD_ENAB);
10494 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10495 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10496 if (tg3_flag(tp, TSO_CAPABLE) &&
10497 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10498 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10500 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10501 !tg3_flag(tp, IS_5788)) {
10502 val |= WDMAC_MODE_RX_ACCEL;
10506 /* Enable host coalescing bug fix */
10507 if (tg3_flag(tp, 5755_PLUS))
10508 val |= WDMAC_MODE_STATUS_TAG_FIX;
10510 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10511 val |= WDMAC_MODE_BURST_ALL_DATA;
10513 tw32_f(WDMAC_MODE, val);
10516 if (tg3_flag(tp, PCIX_MODE)) {
10519 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10521 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10522 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10523 pcix_cmd |= PCI_X_CMD_READ_2K;
10524 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10525 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10526 pcix_cmd |= PCI_X_CMD_READ_2K;
10528 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10532 tw32_f(RDMAC_MODE, rdmac_mode);
10535 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10536 tg3_asic_rev(tp) == ASIC_REV_5720) {
10537 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10538 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10541 if (i < TG3_NUM_RDMA_CHANNELS) {
10542 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10543 val |= tg3_lso_rd_dma_workaround_bit(tp);
10544 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10545 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10549 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10550 if (!tg3_flag(tp, 5705_PLUS))
10551 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10553 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10554 tw32(SNDDATAC_MODE,
10555 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10557 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10559 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10560 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10561 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10562 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10563 val |= RCVDBDI_MODE_LRG_RING_SZ;
10564 tw32(RCVDBDI_MODE, val);
10565 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10566 if (tg3_flag(tp, HW_TSO_1) ||
10567 tg3_flag(tp, HW_TSO_2) ||
10568 tg3_flag(tp, HW_TSO_3))
10569 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10570 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10571 if (tg3_flag(tp, ENABLE_TSS))
10572 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10573 tw32(SNDBDI_MODE, val);
10574 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10576 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10577 err = tg3_load_5701_a0_firmware_fix(tp);
10582 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10583 /* Ignore any errors for the firmware download. If download
10584 * fails, the device will operate with EEE disabled
10586 tg3_load_57766_firmware(tp);
10589 if (tg3_flag(tp, TSO_CAPABLE)) {
10590 err = tg3_load_tso_firmware(tp);
10595 tp->tx_mode = TX_MODE_ENABLE;
10597 if (tg3_flag(tp, 5755_PLUS) ||
10598 tg3_asic_rev(tp) == ASIC_REV_5906)
10599 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10601 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10602 tg3_asic_rev(tp) == ASIC_REV_5762) {
10603 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10604 tp->tx_mode &= ~val;
10605 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10608 tw32_f(MAC_TX_MODE, tp->tx_mode);
10611 if (tg3_flag(tp, ENABLE_RSS)) {
10614 tg3_rss_write_indir_tbl(tp);
10616 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10618 for (i = 0; i < 10 ; i++)
10619 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10622 tp->rx_mode = RX_MODE_ENABLE;
10623 if (tg3_flag(tp, 5755_PLUS))
10624 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10626 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10627 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10629 if (tg3_flag(tp, ENABLE_RSS))
10630 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10631 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10632 RX_MODE_RSS_IPV6_HASH_EN |
10633 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10634 RX_MODE_RSS_IPV4_HASH_EN |
10635 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10637 tw32_f(MAC_RX_MODE, tp->rx_mode);
10640 tw32(MAC_LED_CTRL, tp->led_ctrl);
10642 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10643 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10644 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10647 tw32_f(MAC_RX_MODE, tp->rx_mode);
10650 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10651 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10652 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10653 /* Set drive transmission level to 1.2V */
10654 /* only if the signal pre-emphasis bit is not set */
10655 val = tr32(MAC_SERDES_CFG);
10658 tw32(MAC_SERDES_CFG, val);
10660 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10661 tw32(MAC_SERDES_CFG, 0x616000);
10664 /* Prevent chip from dropping frames when flow control
10667 if (tg3_flag(tp, 57765_CLASS))
10671 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10673 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10674 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10675 /* Use hardware link auto-negotiation */
10676 tg3_flag_set(tp, HW_AUTONEG);
10679 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10680 tg3_asic_rev(tp) == ASIC_REV_5714) {
10683 tmp = tr32(SERDES_RX_CTRL);
10684 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10685 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10686 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10687 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10690 if (!tg3_flag(tp, USE_PHYLIB)) {
10691 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10692 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10694 err = tg3_setup_phy(tp, false);
10698 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10699 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10702 /* Clear CRC stats. */
10703 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10704 tg3_writephy(tp, MII_TG3_TEST1,
10705 tmp | MII_TG3_TEST1_CRC_EN);
10706 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10711 __tg3_set_rx_mode(tp->dev);
10713 /* Initialize receive rules. */
10714 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10715 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10716 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10717 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10719 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10723 if (tg3_flag(tp, ENABLE_ASF))
10727 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10730 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10733 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10736 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10739 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10742 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10745 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10748 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10751 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10754 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10757 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10760 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10763 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10765 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10773 if (tg3_flag(tp, ENABLE_APE))
10774 /* Write our heartbeat update interval to APE. */
10775 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10776 APE_HOST_HEARTBEAT_INT_5SEC);
10778 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10783 /* Called at device open time to get the chip ready for
10784 * packet processing. Invoked with tp->lock held.
10786 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10788 /* Chip may have been just powered on. If so, the boot code may still
10789 * be running initialization. Wait for it to finish to avoid races in
10790 * accessing the hardware.
10792 tg3_enable_register_access(tp);
10795 tg3_switch_clocks(tp);
10797 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10799 return tg3_reset_hw(tp, reset_phy);
10802 #ifdef CONFIG_TIGON3_HWMON
10803 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10805 u32 off, len = TG3_OCIR_LEN;
10808 for (i = 0, off = 0; i < TG3_SD_NUM_RECS; i++, ocir++, off += len) {
10809 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10811 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10812 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10813 memset(ocir, 0, len);
10817 /* sysfs attributes for hwmon */
10818 static ssize_t tg3_show_temp(struct device *dev,
10819 struct device_attribute *devattr, char *buf)
10821 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10822 struct tg3 *tp = dev_get_drvdata(dev);
10825 spin_lock_bh(&tp->lock);
10826 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10827 sizeof(temperature));
10828 spin_unlock_bh(&tp->lock);
10829 return sprintf(buf, "%u\n", temperature * 1000);
10833 static SENSOR_DEVICE_ATTR(temp1_input, 0444, tg3_show_temp, NULL,
10834 TG3_TEMP_SENSOR_OFFSET);
10835 static SENSOR_DEVICE_ATTR(temp1_crit, 0444, tg3_show_temp, NULL,
10836 TG3_TEMP_CAUTION_OFFSET);
10837 static SENSOR_DEVICE_ATTR(temp1_max, 0444, tg3_show_temp, NULL,
10838 TG3_TEMP_MAX_OFFSET);
10840 static struct attribute *tg3_attrs[] = {
10841 &sensor_dev_attr_temp1_input.dev_attr.attr,
10842 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10843 &sensor_dev_attr_temp1_max.dev_attr.attr,
10846 ATTRIBUTE_GROUPS(tg3);
10848 static void tg3_hwmon_close(struct tg3 *tp)
10850 if (tp->hwmon_dev) {
10851 hwmon_device_unregister(tp->hwmon_dev);
10852 tp->hwmon_dev = NULL;
10856 static void tg3_hwmon_open(struct tg3 *tp)
10860 struct pci_dev *pdev = tp->pdev;
10861 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10863 tg3_sd_scan_scratchpad(tp, ocirs);
10865 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10866 if (!ocirs[i].src_data_length)
10869 size += ocirs[i].src_hdr_length;
10870 size += ocirs[i].src_data_length;
10876 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10878 if (IS_ERR(tp->hwmon_dev)) {
10879 tp->hwmon_dev = NULL;
10880 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10884 static inline void tg3_hwmon_close(struct tg3 *tp) { }
10885 static inline void tg3_hwmon_open(struct tg3 *tp) { }
10886 #endif /* CONFIG_TIGON3_HWMON */
10889 #define TG3_STAT_ADD32(PSTAT, REG) \
10890 do { u32 __val = tr32(REG); \
10891 (PSTAT)->low += __val; \
10892 if ((PSTAT)->low < __val) \
10893 (PSTAT)->high += 1; \
10896 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10898 struct tg3_hw_stats *sp = tp->hw_stats;
10903 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10904 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10905 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10906 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10907 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10908 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10909 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10910 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10911 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10912 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10913 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10914 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10915 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10916 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10917 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10918 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10921 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10922 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10923 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10924 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10927 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10928 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10929 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10930 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10931 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10932 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10933 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10934 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10935 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10936 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10937 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10938 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10939 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10940 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10942 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10943 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10944 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10945 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10946 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10947 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10949 u32 val = tr32(HOSTCC_FLOW_ATTN);
10950 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10952 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10953 sp->rx_discards.low += val;
10954 if (sp->rx_discards.low < val)
10955 sp->rx_discards.high += 1;
10957 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10959 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10962 static void tg3_chk_missed_msi(struct tg3 *tp)
10966 for (i = 0; i < tp->irq_cnt; i++) {
10967 struct tg3_napi *tnapi = &tp->napi[i];
10969 if (tg3_has_work(tnapi)) {
10970 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10971 tnapi->last_tx_cons == tnapi->tx_cons) {
10972 if (tnapi->chk_msi_cnt < 1) {
10973 tnapi->chk_msi_cnt++;
10979 tnapi->chk_msi_cnt = 0;
10980 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10981 tnapi->last_tx_cons = tnapi->tx_cons;
10985 static void tg3_timer(struct timer_list *t)
10987 struct tg3 *tp = from_timer(tp, t, timer);
10989 spin_lock(&tp->lock);
10991 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10992 spin_unlock(&tp->lock);
10993 goto restart_timer;
10996 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10997 tg3_flag(tp, 57765_CLASS))
10998 tg3_chk_missed_msi(tp);
11000 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
11001 /* BCM4785: Flush posted writes from GbE to host memory. */
11005 if (!tg3_flag(tp, TAGGED_STATUS)) {
11006 /* All of this garbage is because when using non-tagged
11007 * IRQ status the mailbox/status_block protocol the chip
11008 * uses with the cpu is race prone.
11010 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
11011 tw32(GRC_LOCAL_CTRL,
11012 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
11014 tw32(HOSTCC_MODE, tp->coalesce_mode |
11015 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
11018 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11019 spin_unlock(&tp->lock);
11020 tg3_reset_task_schedule(tp);
11021 goto restart_timer;
11025 /* This part only runs once per second. */
11026 if (!--tp->timer_counter) {
11027 if (tg3_flag(tp, 5705_PLUS))
11028 tg3_periodic_fetch_stats(tp);
11030 if (tp->setlpicnt && !--tp->setlpicnt)
11031 tg3_phy_eee_enable(tp);
11033 if (tg3_flag(tp, USE_LINKCHG_REG)) {
11037 mac_stat = tr32(MAC_STATUS);
11040 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
11041 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
11043 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
11047 tg3_setup_phy(tp, false);
11048 } else if (tg3_flag(tp, POLL_SERDES)) {
11049 u32 mac_stat = tr32(MAC_STATUS);
11050 int need_setup = 0;
11053 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
11056 if (!tp->link_up &&
11057 (mac_stat & (MAC_STATUS_PCS_SYNCED |
11058 MAC_STATUS_SIGNAL_DET))) {
11062 if (!tp->serdes_counter) {
11065 ~MAC_MODE_PORT_MODE_MASK));
11067 tw32_f(MAC_MODE, tp->mac_mode);
11070 tg3_setup_phy(tp, false);
11072 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11073 tg3_flag(tp, 5780_CLASS)) {
11074 tg3_serdes_parallel_detect(tp);
11075 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11076 u32 cpmu = tr32(TG3_CPMU_STATUS);
11077 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
11078 TG3_CPMU_STATUS_LINK_MASK);
11080 if (link_up != tp->link_up)
11081 tg3_setup_phy(tp, false);
11084 tp->timer_counter = tp->timer_multiplier;
11087 /* Heartbeat is only sent once every 2 seconds.
11089 * The heartbeat is to tell the ASF firmware that the host
11090 * driver is still alive. In the event that the OS crashes,
11091 * ASF needs to reset the hardware to free up the FIFO space
11092 * that may be filled with rx packets destined for the host.
11093 * If the FIFO is full, ASF will no longer function properly.
11095 * Unintended resets have been reported on real time kernels
11096 * where the timer doesn't run on time. Netpoll will also have
11099 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11100 * to check the ring condition when the heartbeat is expiring
11101 * before doing the reset. This will prevent most unintended
11104 if (!--tp->asf_counter) {
11105 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11106 tg3_wait_for_event_ack(tp);
11108 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11109 FWCMD_NICDRV_ALIVE3);
11110 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11111 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11112 TG3_FW_UPDATE_TIMEOUT_SEC);
11114 tg3_generate_fw_event(tp);
11116 tp->asf_counter = tp->asf_multiplier;
11119 /* Update the APE heartbeat every 5 seconds.*/
11120 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
11122 spin_unlock(&tp->lock);
11125 tp->timer.expires = jiffies + tp->timer_offset;
11126 add_timer(&tp->timer);
11129 static void tg3_timer_init(struct tg3 *tp)
11131 if (tg3_flag(tp, TAGGED_STATUS) &&
11132 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11133 !tg3_flag(tp, 57765_CLASS))
11134 tp->timer_offset = HZ;
11136 tp->timer_offset = HZ / 10;
11138 BUG_ON(tp->timer_offset > HZ);
11140 tp->timer_multiplier = (HZ / tp->timer_offset);
11141 tp->asf_multiplier = (HZ / tp->timer_offset) *
11142 TG3_FW_UPDATE_FREQ_SEC;
11144 timer_setup(&tp->timer, tg3_timer, 0);
11147 static void tg3_timer_start(struct tg3 *tp)
11149 tp->asf_counter = tp->asf_multiplier;
11150 tp->timer_counter = tp->timer_multiplier;
11152 tp->timer.expires = jiffies + tp->timer_offset;
11153 add_timer(&tp->timer);
11156 static void tg3_timer_stop(struct tg3 *tp)
11158 del_timer_sync(&tp->timer);
11161 /* Restart hardware after configuration changes, self-test, etc.
11162 * Invoked with tp->lock held.
11164 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11165 __releases(tp->lock)
11166 __acquires(tp->lock)
11170 err = tg3_init_hw(tp, reset_phy);
11172 netdev_err(tp->dev,
11173 "Failed to re-initialize device, aborting\n");
11174 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11175 tg3_full_unlock(tp);
11176 tg3_timer_stop(tp);
11178 tg3_napi_enable(tp);
11179 dev_close(tp->dev);
11180 tg3_full_lock(tp, 0);
11185 static void tg3_reset_task(struct work_struct *work)
11187 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11191 tg3_full_lock(tp, 0);
11193 if (tp->pcierr_recovery || !netif_running(tp->dev) ||
11194 tp->pdev->error_state != pci_channel_io_normal) {
11195 tg3_flag_clear(tp, RESET_TASK_PENDING);
11196 tg3_full_unlock(tp);
11201 tg3_full_unlock(tp);
11205 tg3_netif_stop(tp);
11207 tg3_full_lock(tp, 1);
11209 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11210 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11211 tp->write32_rx_mbox = tg3_write_flush_reg32;
11212 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11213 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11216 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11217 err = tg3_init_hw(tp, true);
11219 tg3_full_unlock(tp);
11221 tg3_napi_enable(tp);
11222 /* Clear this flag so that tg3_reset_task_cancel() will not
11223 * call cancel_work_sync() and wait forever.
11225 tg3_flag_clear(tp, RESET_TASK_PENDING);
11226 dev_close(tp->dev);
11230 tg3_netif_start(tp);
11232 tg3_full_unlock(tp);
11237 tg3_flag_clear(tp, RESET_TASK_PENDING);
11242 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11245 unsigned long flags;
11247 struct tg3_napi *tnapi = &tp->napi[irq_num];
11249 if (tp->irq_cnt == 1)
11250 name = tp->dev->name;
11252 name = &tnapi->irq_lbl[0];
11253 if (tnapi->tx_buffers && tnapi->rx_rcb)
11254 snprintf(name, IFNAMSIZ,
11255 "%s-txrx-%d", tp->dev->name, irq_num);
11256 else if (tnapi->tx_buffers)
11257 snprintf(name, IFNAMSIZ,
11258 "%s-tx-%d", tp->dev->name, irq_num);
11259 else if (tnapi->rx_rcb)
11260 snprintf(name, IFNAMSIZ,
11261 "%s-rx-%d", tp->dev->name, irq_num);
11263 snprintf(name, IFNAMSIZ,
11264 "%s-%d", tp->dev->name, irq_num);
11265 name[IFNAMSIZ-1] = 0;
11268 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11270 if (tg3_flag(tp, 1SHOT_MSI))
11271 fn = tg3_msi_1shot;
11274 fn = tg3_interrupt;
11275 if (tg3_flag(tp, TAGGED_STATUS))
11276 fn = tg3_interrupt_tagged;
11277 flags = IRQF_SHARED;
11280 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11283 static int tg3_test_interrupt(struct tg3 *tp)
11285 struct tg3_napi *tnapi = &tp->napi[0];
11286 struct net_device *dev = tp->dev;
11287 int err, i, intr_ok = 0;
11290 if (!netif_running(dev))
11293 tg3_disable_ints(tp);
11295 free_irq(tnapi->irq_vec, tnapi);
11298 * Turn off MSI one shot mode. Otherwise this test has no
11299 * observable way to know whether the interrupt was delivered.
11301 if (tg3_flag(tp, 57765_PLUS)) {
11302 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11303 tw32(MSGINT_MODE, val);
11306 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11307 IRQF_SHARED, dev->name, tnapi);
11311 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11312 tg3_enable_ints(tp);
11314 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11317 for (i = 0; i < 5; i++) {
11318 u32 int_mbox, misc_host_ctrl;
11320 int_mbox = tr32_mailbox(tnapi->int_mbox);
11321 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11323 if ((int_mbox != 0) ||
11324 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11329 if (tg3_flag(tp, 57765_PLUS) &&
11330 tnapi->hw_status->status_tag != tnapi->last_tag)
11331 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11336 tg3_disable_ints(tp);
11338 free_irq(tnapi->irq_vec, tnapi);
11340 err = tg3_request_irq(tp, 0);
11346 /* Reenable MSI one shot mode. */
11347 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11348 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11349 tw32(MSGINT_MODE, val);
11357 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11358 * successfully restored
11360 static int tg3_test_msi(struct tg3 *tp)
11365 if (!tg3_flag(tp, USING_MSI))
11368 /* Turn off SERR reporting in case MSI terminates with Master
11371 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11372 pci_write_config_word(tp->pdev, PCI_COMMAND,
11373 pci_cmd & ~PCI_COMMAND_SERR);
11375 err = tg3_test_interrupt(tp);
11377 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11382 /* other failures */
11386 /* MSI test failed, go back to INTx mode */
11387 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11388 "to INTx mode. Please report this failure to the PCI "
11389 "maintainer and include system chipset information\n");
11391 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11393 pci_disable_msi(tp->pdev);
11395 tg3_flag_clear(tp, USING_MSI);
11396 tp->napi[0].irq_vec = tp->pdev->irq;
11398 err = tg3_request_irq(tp, 0);
11402 /* Need to reset the chip because the MSI cycle may have terminated
11403 * with Master Abort.
11405 tg3_full_lock(tp, 1);
11407 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11408 err = tg3_init_hw(tp, true);
11410 tg3_full_unlock(tp);
11413 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11418 static int tg3_request_firmware(struct tg3 *tp)
11420 const struct tg3_firmware_hdr *fw_hdr;
11422 if (reject_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11423 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11428 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11430 /* Firmware blob starts with version numbers, followed by
11431 * start address and _full_ length including BSS sections
11432 * (which must be longer than the actual data, of course
11435 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11436 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11437 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11438 tp->fw_len, tp->fw_needed);
11439 release_firmware(tp->fw);
11444 /* We no longer need firmware; we have it. */
11445 tp->fw_needed = NULL;
11449 static u32 tg3_irq_count(struct tg3 *tp)
11451 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11454 /* We want as many rx rings enabled as there are cpus.
11455 * In multiqueue MSI-X mode, the first MSI-X vector
11456 * only deals with link interrupts, etc, so we add
11457 * one to the number of vectors we are requesting.
11459 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11465 static bool tg3_enable_msix(struct tg3 *tp)
11468 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11470 tp->txq_cnt = tp->txq_req;
11471 tp->rxq_cnt = tp->rxq_req;
11473 tp->rxq_cnt = netif_get_num_default_rss_queues();
11474 if (tp->rxq_cnt > tp->rxq_max)
11475 tp->rxq_cnt = tp->rxq_max;
11477 /* Disable multiple TX rings by default. Simple round-robin hardware
11478 * scheduling of the TX rings can cause starvation of rings with
11479 * small packets when other rings have TSO or jumbo packets.
11484 tp->irq_cnt = tg3_irq_count(tp);
11486 for (i = 0; i < tp->irq_max; i++) {
11487 msix_ent[i].entry = i;
11488 msix_ent[i].vector = 0;
11491 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11494 } else if (rc < tp->irq_cnt) {
11495 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11498 tp->rxq_cnt = max(rc - 1, 1);
11500 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11503 for (i = 0; i < tp->irq_max; i++)
11504 tp->napi[i].irq_vec = msix_ent[i].vector;
11506 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11507 pci_disable_msix(tp->pdev);
11511 if (tp->irq_cnt == 1)
11514 tg3_flag_set(tp, ENABLE_RSS);
11516 if (tp->txq_cnt > 1)
11517 tg3_flag_set(tp, ENABLE_TSS);
11519 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11524 static void tg3_ints_init(struct tg3 *tp)
11526 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11527 !tg3_flag(tp, TAGGED_STATUS)) {
11528 /* All MSI supporting chips should support tagged
11529 * status. Assert that this is the case.
11531 netdev_warn(tp->dev,
11532 "MSI without TAGGED_STATUS? Not using MSI\n");
11536 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11537 tg3_flag_set(tp, USING_MSIX);
11538 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11539 tg3_flag_set(tp, USING_MSI);
11541 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11542 u32 msi_mode = tr32(MSGINT_MODE);
11543 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11544 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11545 if (!tg3_flag(tp, 1SHOT_MSI))
11546 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11547 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11550 if (!tg3_flag(tp, USING_MSIX)) {
11552 tp->napi[0].irq_vec = tp->pdev->irq;
11555 if (tp->irq_cnt == 1) {
11558 netif_set_real_num_tx_queues(tp->dev, 1);
11559 netif_set_real_num_rx_queues(tp->dev, 1);
11563 static void tg3_ints_fini(struct tg3 *tp)
11565 if (tg3_flag(tp, USING_MSIX))
11566 pci_disable_msix(tp->pdev);
11567 else if (tg3_flag(tp, USING_MSI))
11568 pci_disable_msi(tp->pdev);
11569 tg3_flag_clear(tp, USING_MSI);
11570 tg3_flag_clear(tp, USING_MSIX);
11571 tg3_flag_clear(tp, ENABLE_RSS);
11572 tg3_flag_clear(tp, ENABLE_TSS);
11575 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11578 struct net_device *dev = tp->dev;
11582 * Setup interrupts first so we know how
11583 * many NAPI resources to allocate
11587 tg3_rss_check_indir_tbl(tp);
11589 /* The placement of this call is tied
11590 * to the setup and use of Host TX descriptors.
11592 err = tg3_alloc_consistent(tp);
11594 goto out_ints_fini;
11598 tg3_napi_enable(tp);
11600 for (i = 0; i < tp->irq_cnt; i++) {
11601 err = tg3_request_irq(tp, i);
11603 for (i--; i >= 0; i--) {
11604 struct tg3_napi *tnapi = &tp->napi[i];
11606 free_irq(tnapi->irq_vec, tnapi);
11608 goto out_napi_fini;
11612 tg3_full_lock(tp, 0);
11615 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11617 err = tg3_init_hw(tp, reset_phy);
11619 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11620 tg3_free_rings(tp);
11623 tg3_full_unlock(tp);
11628 if (test_irq && tg3_flag(tp, USING_MSI)) {
11629 err = tg3_test_msi(tp);
11632 tg3_full_lock(tp, 0);
11633 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11634 tg3_free_rings(tp);
11635 tg3_full_unlock(tp);
11637 goto out_napi_fini;
11640 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11641 u32 val = tr32(PCIE_TRANSACTION_CFG);
11643 tw32(PCIE_TRANSACTION_CFG,
11644 val | PCIE_TRANS_CFG_1SHOT_MSI);
11650 tg3_hwmon_open(tp);
11652 tg3_full_lock(tp, 0);
11654 tg3_timer_start(tp);
11655 tg3_flag_set(tp, INIT_COMPLETE);
11656 tg3_enable_ints(tp);
11658 tg3_ptp_resume(tp);
11660 tg3_full_unlock(tp);
11662 netif_tx_start_all_queues(dev);
11665 * Reset loopback feature if it was turned on while the device was down
11666 * make sure that it's installed properly now.
11668 if (dev->features & NETIF_F_LOOPBACK)
11669 tg3_set_loopback(dev, dev->features);
11674 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11675 struct tg3_napi *tnapi = &tp->napi[i];
11676 free_irq(tnapi->irq_vec, tnapi);
11680 tg3_napi_disable(tp);
11682 tg3_free_consistent(tp);
11690 static void tg3_stop(struct tg3 *tp)
11694 tg3_reset_task_cancel(tp);
11695 tg3_netif_stop(tp);
11697 tg3_timer_stop(tp);
11699 tg3_hwmon_close(tp);
11703 tg3_full_lock(tp, 1);
11705 tg3_disable_ints(tp);
11707 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11708 tg3_free_rings(tp);
11709 tg3_flag_clear(tp, INIT_COMPLETE);
11711 tg3_full_unlock(tp);
11713 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11714 struct tg3_napi *tnapi = &tp->napi[i];
11715 free_irq(tnapi->irq_vec, tnapi);
11722 tg3_free_consistent(tp);
11725 static int tg3_open(struct net_device *dev)
11727 struct tg3 *tp = netdev_priv(dev);
11730 if (tp->pcierr_recovery) {
11731 netdev_err(dev, "Failed to open device. PCI error recovery "
11736 if (tp->fw_needed) {
11737 err = tg3_request_firmware(tp);
11738 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11740 netdev_warn(tp->dev, "EEE capability disabled\n");
11741 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11742 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11743 netdev_warn(tp->dev, "EEE capability restored\n");
11744 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11746 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11750 netdev_warn(tp->dev, "TSO capability disabled\n");
11751 tg3_flag_clear(tp, TSO_CAPABLE);
11752 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11753 netdev_notice(tp->dev, "TSO capability restored\n");
11754 tg3_flag_set(tp, TSO_CAPABLE);
11758 tg3_carrier_off(tp);
11760 err = tg3_power_up(tp);
11764 tg3_full_lock(tp, 0);
11766 tg3_disable_ints(tp);
11767 tg3_flag_clear(tp, INIT_COMPLETE);
11769 tg3_full_unlock(tp);
11771 err = tg3_start(tp,
11772 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11775 tg3_frob_aux_power(tp, false);
11776 pci_set_power_state(tp->pdev, PCI_D3hot);
11782 static int tg3_close(struct net_device *dev)
11784 struct tg3 *tp = netdev_priv(dev);
11786 if (tp->pcierr_recovery) {
11787 netdev_err(dev, "Failed to close device. PCI error recovery "
11794 if (pci_device_is_present(tp->pdev)) {
11795 tg3_power_down_prepare(tp);
11797 tg3_carrier_off(tp);
11802 static inline u64 get_stat64(tg3_stat64_t *val)
11804 return ((u64)val->high << 32) | ((u64)val->low);
11807 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11809 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11811 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11812 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11813 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11816 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11817 tg3_writephy(tp, MII_TG3_TEST1,
11818 val | MII_TG3_TEST1_CRC_EN);
11819 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11823 tp->phy_crc_errors += val;
11825 return tp->phy_crc_errors;
11828 return get_stat64(&hw_stats->rx_fcs_errors);
11831 #define ESTAT_ADD(member) \
11832 estats->member = old_estats->member + \
11833 get_stat64(&hw_stats->member)
11835 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11837 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11838 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11840 ESTAT_ADD(rx_octets);
11841 ESTAT_ADD(rx_fragments);
11842 ESTAT_ADD(rx_ucast_packets);
11843 ESTAT_ADD(rx_mcast_packets);
11844 ESTAT_ADD(rx_bcast_packets);
11845 ESTAT_ADD(rx_fcs_errors);
11846 ESTAT_ADD(rx_align_errors);
11847 ESTAT_ADD(rx_xon_pause_rcvd);
11848 ESTAT_ADD(rx_xoff_pause_rcvd);
11849 ESTAT_ADD(rx_mac_ctrl_rcvd);
11850 ESTAT_ADD(rx_xoff_entered);
11851 ESTAT_ADD(rx_frame_too_long_errors);
11852 ESTAT_ADD(rx_jabbers);
11853 ESTAT_ADD(rx_undersize_packets);
11854 ESTAT_ADD(rx_in_length_errors);
11855 ESTAT_ADD(rx_out_length_errors);
11856 ESTAT_ADD(rx_64_or_less_octet_packets);
11857 ESTAT_ADD(rx_65_to_127_octet_packets);
11858 ESTAT_ADD(rx_128_to_255_octet_packets);
11859 ESTAT_ADD(rx_256_to_511_octet_packets);
11860 ESTAT_ADD(rx_512_to_1023_octet_packets);
11861 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11862 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11863 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11864 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11865 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11867 ESTAT_ADD(tx_octets);
11868 ESTAT_ADD(tx_collisions);
11869 ESTAT_ADD(tx_xon_sent);
11870 ESTAT_ADD(tx_xoff_sent);
11871 ESTAT_ADD(tx_flow_control);
11872 ESTAT_ADD(tx_mac_errors);
11873 ESTAT_ADD(tx_single_collisions);
11874 ESTAT_ADD(tx_mult_collisions);
11875 ESTAT_ADD(tx_deferred);
11876 ESTAT_ADD(tx_excessive_collisions);
11877 ESTAT_ADD(tx_late_collisions);
11878 ESTAT_ADD(tx_collide_2times);
11879 ESTAT_ADD(tx_collide_3times);
11880 ESTAT_ADD(tx_collide_4times);
11881 ESTAT_ADD(tx_collide_5times);
11882 ESTAT_ADD(tx_collide_6times);
11883 ESTAT_ADD(tx_collide_7times);
11884 ESTAT_ADD(tx_collide_8times);
11885 ESTAT_ADD(tx_collide_9times);
11886 ESTAT_ADD(tx_collide_10times);
11887 ESTAT_ADD(tx_collide_11times);
11888 ESTAT_ADD(tx_collide_12times);
11889 ESTAT_ADD(tx_collide_13times);
11890 ESTAT_ADD(tx_collide_14times);
11891 ESTAT_ADD(tx_collide_15times);
11892 ESTAT_ADD(tx_ucast_packets);
11893 ESTAT_ADD(tx_mcast_packets);
11894 ESTAT_ADD(tx_bcast_packets);
11895 ESTAT_ADD(tx_carrier_sense_errors);
11896 ESTAT_ADD(tx_discards);
11897 ESTAT_ADD(tx_errors);
11899 ESTAT_ADD(dma_writeq_full);
11900 ESTAT_ADD(dma_write_prioq_full);
11901 ESTAT_ADD(rxbds_empty);
11902 ESTAT_ADD(rx_discards);
11903 ESTAT_ADD(rx_errors);
11904 ESTAT_ADD(rx_threshold_hit);
11906 ESTAT_ADD(dma_readq_full);
11907 ESTAT_ADD(dma_read_prioq_full);
11908 ESTAT_ADD(tx_comp_queue_full);
11910 ESTAT_ADD(ring_set_send_prod_index);
11911 ESTAT_ADD(ring_status_update);
11912 ESTAT_ADD(nic_irqs);
11913 ESTAT_ADD(nic_avoided_irqs);
11914 ESTAT_ADD(nic_tx_threshold_hit);
11916 ESTAT_ADD(mbuf_lwm_thresh_hit);
11919 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11921 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11922 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11923 unsigned long rx_dropped;
11924 unsigned long tx_dropped;
11927 stats->rx_packets = old_stats->rx_packets +
11928 get_stat64(&hw_stats->rx_ucast_packets) +
11929 get_stat64(&hw_stats->rx_mcast_packets) +
11930 get_stat64(&hw_stats->rx_bcast_packets);
11932 stats->tx_packets = old_stats->tx_packets +
11933 get_stat64(&hw_stats->tx_ucast_packets) +
11934 get_stat64(&hw_stats->tx_mcast_packets) +
11935 get_stat64(&hw_stats->tx_bcast_packets);
11937 stats->rx_bytes = old_stats->rx_bytes +
11938 get_stat64(&hw_stats->rx_octets);
11939 stats->tx_bytes = old_stats->tx_bytes +
11940 get_stat64(&hw_stats->tx_octets);
11942 stats->rx_errors = old_stats->rx_errors +
11943 get_stat64(&hw_stats->rx_errors);
11944 stats->tx_errors = old_stats->tx_errors +
11945 get_stat64(&hw_stats->tx_errors) +
11946 get_stat64(&hw_stats->tx_mac_errors) +
11947 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11948 get_stat64(&hw_stats->tx_discards);
11950 stats->multicast = old_stats->multicast +
11951 get_stat64(&hw_stats->rx_mcast_packets);
11952 stats->collisions = old_stats->collisions +
11953 get_stat64(&hw_stats->tx_collisions);
11955 stats->rx_length_errors = old_stats->rx_length_errors +
11956 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11957 get_stat64(&hw_stats->rx_undersize_packets);
11959 stats->rx_frame_errors = old_stats->rx_frame_errors +
11960 get_stat64(&hw_stats->rx_align_errors);
11961 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11962 get_stat64(&hw_stats->tx_discards);
11963 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11964 get_stat64(&hw_stats->tx_carrier_sense_errors);
11966 stats->rx_crc_errors = old_stats->rx_crc_errors +
11967 tg3_calc_crc_errors(tp);
11969 stats->rx_missed_errors = old_stats->rx_missed_errors +
11970 get_stat64(&hw_stats->rx_discards);
11972 /* Aggregate per-queue counters. The per-queue counters are updated
11973 * by a single writer, race-free. The result computed by this loop
11974 * might not be 100% accurate (counters can be updated in the middle of
11975 * the loop) but the next tg3_get_nstats() will recompute the current
11976 * value so it is acceptable.
11978 * Note that these counters wrap around at 4G on 32bit machines.
11980 rx_dropped = (unsigned long)(old_stats->rx_dropped);
11981 tx_dropped = (unsigned long)(old_stats->tx_dropped);
11983 for (i = 0; i < tp->irq_cnt; i++) {
11984 struct tg3_napi *tnapi = &tp->napi[i];
11986 rx_dropped += tnapi->rx_dropped;
11987 tx_dropped += tnapi->tx_dropped;
11990 stats->rx_dropped = rx_dropped;
11991 stats->tx_dropped = tx_dropped;
11994 static int tg3_get_regs_len(struct net_device *dev)
11996 return TG3_REG_BLK_SIZE;
11999 static void tg3_get_regs(struct net_device *dev,
12000 struct ethtool_regs *regs, void *_p)
12002 struct tg3 *tp = netdev_priv(dev);
12006 memset(_p, 0, TG3_REG_BLK_SIZE);
12008 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12011 tg3_full_lock(tp, 0);
12013 tg3_dump_legacy_regs(tp, (u32 *)_p);
12015 tg3_full_unlock(tp);
12018 static int tg3_get_eeprom_len(struct net_device *dev)
12020 struct tg3 *tp = netdev_priv(dev);
12022 return tp->nvram_size;
12025 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12027 struct tg3 *tp = netdev_priv(dev);
12028 int ret, cpmu_restore = 0;
12030 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
12033 if (tg3_flag(tp, NO_NVRAM))
12036 offset = eeprom->offset;
12040 eeprom->magic = TG3_EEPROM_MAGIC;
12042 /* Override clock, link aware and link idle modes */
12043 if (tg3_flag(tp, CPMU_PRESENT)) {
12044 cpmu_val = tr32(TG3_CPMU_CTRL);
12045 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
12046 CPMU_CTRL_LINK_IDLE_MODE)) {
12047 tw32(TG3_CPMU_CTRL, cpmu_val &
12048 ~(CPMU_CTRL_LINK_AWARE_MODE |
12049 CPMU_CTRL_LINK_IDLE_MODE));
12053 tg3_override_clk(tp);
12056 /* adjustments to start on required 4 byte boundary */
12057 b_offset = offset & 3;
12058 b_count = 4 - b_offset;
12059 if (b_count > len) {
12060 /* i.e. offset=1 len=2 */
12063 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12066 memcpy(data, ((char *)&val) + b_offset, b_count);
12069 eeprom->len += b_count;
12072 /* read bytes up to the last 4 byte boundary */
12073 pd = &data[eeprom->len];
12074 for (i = 0; i < (len - (len & 3)); i += 4) {
12075 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12082 memcpy(pd + i, &val, 4);
12083 if (need_resched()) {
12084 if (signal_pending(current)) {
12095 /* read last bytes not ending on 4 byte boundary */
12096 pd = &data[eeprom->len];
12098 b_offset = offset + len - b_count;
12099 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12102 memcpy(pd, &val, b_count);
12103 eeprom->len += b_count;
12108 /* Restore clock, link aware and link idle modes */
12109 tg3_restore_clk(tp);
12111 tw32(TG3_CPMU_CTRL, cpmu_val);
12116 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12118 struct tg3 *tp = netdev_priv(dev);
12120 u32 offset, len, b_offset, odd_len;
12122 __be32 start = 0, end;
12124 if (tg3_flag(tp, NO_NVRAM) ||
12125 eeprom->magic != TG3_EEPROM_MAGIC)
12128 offset = eeprom->offset;
12131 if ((b_offset = (offset & 3))) {
12132 /* adjustments to start on required 4 byte boundary */
12133 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12144 /* adjustments to end on required 4 byte boundary */
12146 len = (len + 3) & ~3;
12147 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12153 if (b_offset || odd_len) {
12154 buf = kmalloc(len, GFP_KERNEL);
12158 memcpy(buf, &start, 4);
12160 memcpy(buf+len-4, &end, 4);
12161 memcpy(buf + b_offset, data, eeprom->len);
12164 ret = tg3_nvram_write_block(tp, offset, len, buf);
12172 static int tg3_get_link_ksettings(struct net_device *dev,
12173 struct ethtool_link_ksettings *cmd)
12175 struct tg3 *tp = netdev_priv(dev);
12176 u32 supported, advertising;
12178 if (tg3_flag(tp, USE_PHYLIB)) {
12179 struct phy_device *phydev;
12180 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12182 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12183 phy_ethtool_ksettings_get(phydev, cmd);
12188 supported = (SUPPORTED_Autoneg);
12190 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12191 supported |= (SUPPORTED_1000baseT_Half |
12192 SUPPORTED_1000baseT_Full);
12194 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12195 supported |= (SUPPORTED_100baseT_Half |
12196 SUPPORTED_100baseT_Full |
12197 SUPPORTED_10baseT_Half |
12198 SUPPORTED_10baseT_Full |
12200 cmd->base.port = PORT_TP;
12202 supported |= SUPPORTED_FIBRE;
12203 cmd->base.port = PORT_FIBRE;
12205 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
12208 advertising = tp->link_config.advertising;
12209 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12210 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12211 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12212 advertising |= ADVERTISED_Pause;
12214 advertising |= ADVERTISED_Pause |
12215 ADVERTISED_Asym_Pause;
12217 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12218 advertising |= ADVERTISED_Asym_Pause;
12221 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
12224 if (netif_running(dev) && tp->link_up) {
12225 cmd->base.speed = tp->link_config.active_speed;
12226 cmd->base.duplex = tp->link_config.active_duplex;
12227 ethtool_convert_legacy_u32_to_link_mode(
12228 cmd->link_modes.lp_advertising,
12229 tp->link_config.rmt_adv);
12231 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12232 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12233 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
12235 cmd->base.eth_tp_mdix = ETH_TP_MDI;
12238 cmd->base.speed = SPEED_UNKNOWN;
12239 cmd->base.duplex = DUPLEX_UNKNOWN;
12240 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
12242 cmd->base.phy_address = tp->phy_addr;
12243 cmd->base.autoneg = tp->link_config.autoneg;
12247 static int tg3_set_link_ksettings(struct net_device *dev,
12248 const struct ethtool_link_ksettings *cmd)
12250 struct tg3 *tp = netdev_priv(dev);
12251 u32 speed = cmd->base.speed;
12254 if (tg3_flag(tp, USE_PHYLIB)) {
12255 struct phy_device *phydev;
12256 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12258 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12259 return phy_ethtool_ksettings_set(phydev, cmd);
12262 if (cmd->base.autoneg != AUTONEG_ENABLE &&
12263 cmd->base.autoneg != AUTONEG_DISABLE)
12266 if (cmd->base.autoneg == AUTONEG_DISABLE &&
12267 cmd->base.duplex != DUPLEX_FULL &&
12268 cmd->base.duplex != DUPLEX_HALF)
12271 ethtool_convert_link_mode_to_legacy_u32(&advertising,
12272 cmd->link_modes.advertising);
12274 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12275 u32 mask = ADVERTISED_Autoneg |
12277 ADVERTISED_Asym_Pause;
12279 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12280 mask |= ADVERTISED_1000baseT_Half |
12281 ADVERTISED_1000baseT_Full;
12283 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12284 mask |= ADVERTISED_100baseT_Half |
12285 ADVERTISED_100baseT_Full |
12286 ADVERTISED_10baseT_Half |
12287 ADVERTISED_10baseT_Full |
12290 mask |= ADVERTISED_FIBRE;
12292 if (advertising & ~mask)
12295 mask &= (ADVERTISED_1000baseT_Half |
12296 ADVERTISED_1000baseT_Full |
12297 ADVERTISED_100baseT_Half |
12298 ADVERTISED_100baseT_Full |
12299 ADVERTISED_10baseT_Half |
12300 ADVERTISED_10baseT_Full);
12302 advertising &= mask;
12304 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12305 if (speed != SPEED_1000)
12308 if (cmd->base.duplex != DUPLEX_FULL)
12311 if (speed != SPEED_100 &&
12317 tg3_full_lock(tp, 0);
12319 tp->link_config.autoneg = cmd->base.autoneg;
12320 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12321 tp->link_config.advertising = (advertising |
12322 ADVERTISED_Autoneg);
12323 tp->link_config.speed = SPEED_UNKNOWN;
12324 tp->link_config.duplex = DUPLEX_UNKNOWN;
12326 tp->link_config.advertising = 0;
12327 tp->link_config.speed = speed;
12328 tp->link_config.duplex = cmd->base.duplex;
12331 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12333 tg3_warn_mgmt_link_flap(tp);
12335 if (netif_running(dev))
12336 tg3_setup_phy(tp, true);
12338 tg3_full_unlock(tp);
12343 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12345 struct tg3 *tp = netdev_priv(dev);
12347 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12348 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12349 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12352 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12354 struct tg3 *tp = netdev_priv(dev);
12356 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12357 wol->supported = WAKE_MAGIC;
12359 wol->supported = 0;
12361 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12362 wol->wolopts = WAKE_MAGIC;
12363 memset(&wol->sopass, 0, sizeof(wol->sopass));
12366 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12368 struct tg3 *tp = netdev_priv(dev);
12369 struct device *dp = &tp->pdev->dev;
12371 if (wol->wolopts & ~WAKE_MAGIC)
12373 if ((wol->wolopts & WAKE_MAGIC) &&
12374 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12377 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12379 if (device_may_wakeup(dp))
12380 tg3_flag_set(tp, WOL_ENABLE);
12382 tg3_flag_clear(tp, WOL_ENABLE);
12387 static u32 tg3_get_msglevel(struct net_device *dev)
12389 struct tg3 *tp = netdev_priv(dev);
12390 return tp->msg_enable;
12393 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12395 struct tg3 *tp = netdev_priv(dev);
12396 tp->msg_enable = value;
12399 static int tg3_nway_reset(struct net_device *dev)
12401 struct tg3 *tp = netdev_priv(dev);
12404 if (!netif_running(dev))
12407 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12410 tg3_warn_mgmt_link_flap(tp);
12412 if (tg3_flag(tp, USE_PHYLIB)) {
12413 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12415 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
12419 spin_lock_bh(&tp->lock);
12421 tg3_readphy(tp, MII_BMCR, &bmcr);
12422 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12423 ((bmcr & BMCR_ANENABLE) ||
12424 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12425 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12429 spin_unlock_bh(&tp->lock);
12435 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12437 struct tg3 *tp = netdev_priv(dev);
12439 ering->rx_max_pending = tp->rx_std_ring_mask;
12440 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12441 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12443 ering->rx_jumbo_max_pending = 0;
12445 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12447 ering->rx_pending = tp->rx_pending;
12448 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12449 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12451 ering->rx_jumbo_pending = 0;
12453 ering->tx_pending = tp->napi[0].tx_pending;
12456 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12458 struct tg3 *tp = netdev_priv(dev);
12459 int i, irq_sync = 0, err = 0;
12460 bool reset_phy = false;
12462 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12463 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12464 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12465 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12466 (tg3_flag(tp, TSO_BUG) &&
12467 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12470 if (netif_running(dev)) {
12472 tg3_netif_stop(tp);
12476 tg3_full_lock(tp, irq_sync);
12478 tp->rx_pending = ering->rx_pending;
12480 if (tg3_flag(tp, MAX_RXPEND_64) &&
12481 tp->rx_pending > 63)
12482 tp->rx_pending = 63;
12484 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12485 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12487 for (i = 0; i < tp->irq_max; i++)
12488 tp->napi[i].tx_pending = ering->tx_pending;
12490 if (netif_running(dev)) {
12491 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12492 /* Reset PHY to avoid PHY lock up */
12493 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12494 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12495 tg3_asic_rev(tp) == ASIC_REV_5720)
12498 err = tg3_restart_hw(tp, reset_phy);
12500 tg3_netif_start(tp);
12503 tg3_full_unlock(tp);
12505 if (irq_sync && !err)
12511 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12513 struct tg3 *tp = netdev_priv(dev);
12515 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12517 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12518 epause->rx_pause = 1;
12520 epause->rx_pause = 0;
12522 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12523 epause->tx_pause = 1;
12525 epause->tx_pause = 0;
12528 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12530 struct tg3 *tp = netdev_priv(dev);
12532 bool reset_phy = false;
12534 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12535 tg3_warn_mgmt_link_flap(tp);
12537 if (tg3_flag(tp, USE_PHYLIB)) {
12538 struct phy_device *phydev;
12540 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12542 if (!phy_validate_pause(phydev, epause))
12545 tp->link_config.flowctrl = 0;
12546 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
12547 if (epause->rx_pause) {
12548 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12550 if (epause->tx_pause) {
12551 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12553 } else if (epause->tx_pause) {
12554 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12557 if (epause->autoneg)
12558 tg3_flag_set(tp, PAUSE_AUTONEG);
12560 tg3_flag_clear(tp, PAUSE_AUTONEG);
12562 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12563 if (phydev->autoneg) {
12564 /* phy_set_asym_pause() will
12565 * renegotiate the link to inform our
12566 * link partner of our flow control
12567 * settings, even if the flow control
12568 * is forced. Let tg3_adjust_link()
12569 * do the final flow control setup.
12574 if (!epause->autoneg)
12575 tg3_setup_flow_control(tp, 0, 0);
12580 if (netif_running(dev)) {
12581 tg3_netif_stop(tp);
12585 tg3_full_lock(tp, irq_sync);
12587 if (epause->autoneg)
12588 tg3_flag_set(tp, PAUSE_AUTONEG);
12590 tg3_flag_clear(tp, PAUSE_AUTONEG);
12591 if (epause->rx_pause)
12592 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12594 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12595 if (epause->tx_pause)
12596 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12598 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12600 if (netif_running(dev)) {
12601 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12602 /* Reset PHY to avoid PHY lock up */
12603 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12604 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12605 tg3_asic_rev(tp) == ASIC_REV_5720)
12608 err = tg3_restart_hw(tp, reset_phy);
12610 tg3_netif_start(tp);
12613 tg3_full_unlock(tp);
12616 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12621 static int tg3_get_sset_count(struct net_device *dev, int sset)
12625 return TG3_NUM_TEST;
12627 return TG3_NUM_STATS;
12629 return -EOPNOTSUPP;
12633 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12634 u32 *rules __always_unused)
12636 struct tg3 *tp = netdev_priv(dev);
12638 if (!tg3_flag(tp, SUPPORT_MSIX))
12639 return -EOPNOTSUPP;
12641 switch (info->cmd) {
12642 case ETHTOOL_GRXRINGS:
12643 if (netif_running(tp->dev))
12644 info->data = tp->rxq_cnt;
12646 info->data = num_online_cpus();
12647 if (info->data > TG3_RSS_MAX_NUM_QS)
12648 info->data = TG3_RSS_MAX_NUM_QS;
12654 return -EOPNOTSUPP;
12658 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12661 struct tg3 *tp = netdev_priv(dev);
12663 if (tg3_flag(tp, SUPPORT_MSIX))
12664 size = TG3_RSS_INDIR_TBL_SIZE;
12669 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
12671 struct tg3 *tp = netdev_priv(dev);
12675 *hfunc = ETH_RSS_HASH_TOP;
12679 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12680 indir[i] = tp->rss_ind_tbl[i];
12685 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12688 struct tg3 *tp = netdev_priv(dev);
12691 /* We require at least one supported parameter to be changed and no
12692 * change in any of the unsupported parameters
12695 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12696 return -EOPNOTSUPP;
12701 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12702 tp->rss_ind_tbl[i] = indir[i];
12704 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12707 /* It is legal to write the indirection
12708 * table while the device is running.
12710 tg3_full_lock(tp, 0);
12711 tg3_rss_write_indir_tbl(tp);
12712 tg3_full_unlock(tp);
12717 static void tg3_get_channels(struct net_device *dev,
12718 struct ethtool_channels *channel)
12720 struct tg3 *tp = netdev_priv(dev);
12721 u32 deflt_qs = netif_get_num_default_rss_queues();
12723 channel->max_rx = tp->rxq_max;
12724 channel->max_tx = tp->txq_max;
12726 if (netif_running(dev)) {
12727 channel->rx_count = tp->rxq_cnt;
12728 channel->tx_count = tp->txq_cnt;
12731 channel->rx_count = tp->rxq_req;
12733 channel->rx_count = min(deflt_qs, tp->rxq_max);
12736 channel->tx_count = tp->txq_req;
12738 channel->tx_count = min(deflt_qs, tp->txq_max);
12742 static int tg3_set_channels(struct net_device *dev,
12743 struct ethtool_channels *channel)
12745 struct tg3 *tp = netdev_priv(dev);
12747 if (!tg3_flag(tp, SUPPORT_MSIX))
12748 return -EOPNOTSUPP;
12750 if (channel->rx_count > tp->rxq_max ||
12751 channel->tx_count > tp->txq_max)
12754 tp->rxq_req = channel->rx_count;
12755 tp->txq_req = channel->tx_count;
12757 if (!netif_running(dev))
12762 tg3_carrier_off(tp);
12764 tg3_start(tp, true, false, false);
12769 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12771 switch (stringset) {
12773 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12776 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12779 WARN_ON(1); /* we need a WARN() */
12784 static int tg3_set_phys_id(struct net_device *dev,
12785 enum ethtool_phys_id_state state)
12787 struct tg3 *tp = netdev_priv(dev);
12790 case ETHTOOL_ID_ACTIVE:
12791 return 1; /* cycle on/off once per second */
12793 case ETHTOOL_ID_ON:
12794 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12795 LED_CTRL_1000MBPS_ON |
12796 LED_CTRL_100MBPS_ON |
12797 LED_CTRL_10MBPS_ON |
12798 LED_CTRL_TRAFFIC_OVERRIDE |
12799 LED_CTRL_TRAFFIC_BLINK |
12800 LED_CTRL_TRAFFIC_LED);
12803 case ETHTOOL_ID_OFF:
12804 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12805 LED_CTRL_TRAFFIC_OVERRIDE);
12808 case ETHTOOL_ID_INACTIVE:
12809 tw32(MAC_LED_CTRL, tp->led_ctrl);
12816 static void tg3_get_ethtool_stats(struct net_device *dev,
12817 struct ethtool_stats *estats, u64 *tmp_stats)
12819 struct tg3 *tp = netdev_priv(dev);
12822 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12824 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12827 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12831 u32 offset = 0, len = 0;
12834 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12837 if (magic == TG3_EEPROM_MAGIC) {
12838 for (offset = TG3_NVM_DIR_START;
12839 offset < TG3_NVM_DIR_END;
12840 offset += TG3_NVM_DIRENT_SIZE) {
12841 if (tg3_nvram_read(tp, offset, &val))
12844 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12845 TG3_NVM_DIRTYPE_EXTVPD)
12849 if (offset != TG3_NVM_DIR_END) {
12850 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12851 if (tg3_nvram_read(tp, offset + 4, &offset))
12854 offset = tg3_nvram_logical_addr(tp, offset);
12858 if (!offset || !len) {
12859 offset = TG3_NVM_VPD_OFF;
12860 len = TG3_NVM_VPD_LEN;
12863 buf = kmalloc(len, GFP_KERNEL);
12867 if (magic == TG3_EEPROM_MAGIC) {
12868 for (i = 0; i < len; i += 4) {
12869 /* The data is in little-endian format in NVRAM.
12870 * Use the big-endian read routines to preserve
12871 * the byte order as it exists in NVRAM.
12873 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12879 unsigned int pos = 0;
12881 ptr = (u8 *)&buf[0];
12882 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12883 cnt = pci_read_vpd(tp->pdev, pos,
12885 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12903 #define NVRAM_TEST_SIZE 0x100
12904 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12905 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12906 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12907 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12908 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12909 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12910 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12911 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12913 static int tg3_test_nvram(struct tg3 *tp)
12915 u32 csum, magic, len;
12917 int i, j, k, err = 0, size;
12919 if (tg3_flag(tp, NO_NVRAM))
12922 if (tg3_nvram_read(tp, 0, &magic) != 0)
12925 if (magic == TG3_EEPROM_MAGIC)
12926 size = NVRAM_TEST_SIZE;
12927 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12928 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12929 TG3_EEPROM_SB_FORMAT_1) {
12930 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12931 case TG3_EEPROM_SB_REVISION_0:
12932 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12934 case TG3_EEPROM_SB_REVISION_2:
12935 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12937 case TG3_EEPROM_SB_REVISION_3:
12938 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12940 case TG3_EEPROM_SB_REVISION_4:
12941 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12943 case TG3_EEPROM_SB_REVISION_5:
12944 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12946 case TG3_EEPROM_SB_REVISION_6:
12947 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12954 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12955 size = NVRAM_SELFBOOT_HW_SIZE;
12959 buf = kmalloc(size, GFP_KERNEL);
12964 for (i = 0, j = 0; i < size; i += 4, j++) {
12965 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12972 /* Selfboot format */
12973 magic = be32_to_cpu(buf[0]);
12974 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12975 TG3_EEPROM_MAGIC_FW) {
12976 u8 *buf8 = (u8 *) buf, csum8 = 0;
12978 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12979 TG3_EEPROM_SB_REVISION_2) {
12980 /* For rev 2, the csum doesn't include the MBA. */
12981 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12983 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12986 for (i = 0; i < size; i++)
12999 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
13000 TG3_EEPROM_MAGIC_HW) {
13001 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
13002 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
13003 u8 *buf8 = (u8 *) buf;
13005 /* Separate the parity bits and the data bytes. */
13006 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
13007 if ((i == 0) || (i == 8)) {
13011 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
13012 parity[k++] = buf8[i] & msk;
13014 } else if (i == 16) {
13018 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
13019 parity[k++] = buf8[i] & msk;
13022 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
13023 parity[k++] = buf8[i] & msk;
13026 data[j++] = buf8[i];
13030 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
13031 u8 hw8 = hweight8(data[i]);
13033 if ((hw8 & 0x1) && parity[i])
13035 else if (!(hw8 & 0x1) && !parity[i])
13044 /* Bootstrap checksum at offset 0x10 */
13045 csum = calc_crc((unsigned char *) buf, 0x10);
13046 if (csum != le32_to_cpu(buf[0x10/4]))
13049 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
13050 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
13051 if (csum != le32_to_cpu(buf[0xfc/4]))
13056 buf = tg3_vpd_readblock(tp, &len);
13060 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
13062 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
13066 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
13069 i += PCI_VPD_LRDT_TAG_SIZE;
13070 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
13071 PCI_VPD_RO_KEYWORD_CHKSUM);
13075 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13077 for (i = 0; i <= j; i++)
13078 csum8 += ((u8 *)buf)[i];
13092 #define TG3_SERDES_TIMEOUT_SEC 2
13093 #define TG3_COPPER_TIMEOUT_SEC 6
13095 static int tg3_test_link(struct tg3 *tp)
13099 if (!netif_running(tp->dev))
13102 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13103 max = TG3_SERDES_TIMEOUT_SEC;
13105 max = TG3_COPPER_TIMEOUT_SEC;
13107 for (i = 0; i < max; i++) {
13111 if (msleep_interruptible(1000))
13118 /* Only test the commonly used registers */
13119 static int tg3_test_registers(struct tg3 *tp)
13121 int i, is_5705, is_5750;
13122 u32 offset, read_mask, write_mask, val, save_val, read_val;
13126 #define TG3_FL_5705 0x1
13127 #define TG3_FL_NOT_5705 0x2
13128 #define TG3_FL_NOT_5788 0x4
13129 #define TG3_FL_NOT_5750 0x8
13133 /* MAC Control Registers */
13134 { MAC_MODE, TG3_FL_NOT_5705,
13135 0x00000000, 0x00ef6f8c },
13136 { MAC_MODE, TG3_FL_5705,
13137 0x00000000, 0x01ef6b8c },
13138 { MAC_STATUS, TG3_FL_NOT_5705,
13139 0x03800107, 0x00000000 },
13140 { MAC_STATUS, TG3_FL_5705,
13141 0x03800100, 0x00000000 },
13142 { MAC_ADDR_0_HIGH, 0x0000,
13143 0x00000000, 0x0000ffff },
13144 { MAC_ADDR_0_LOW, 0x0000,
13145 0x00000000, 0xffffffff },
13146 { MAC_RX_MTU_SIZE, 0x0000,
13147 0x00000000, 0x0000ffff },
13148 { MAC_TX_MODE, 0x0000,
13149 0x00000000, 0x00000070 },
13150 { MAC_TX_LENGTHS, 0x0000,
13151 0x00000000, 0x00003fff },
13152 { MAC_RX_MODE, TG3_FL_NOT_5705,
13153 0x00000000, 0x000007fc },
13154 { MAC_RX_MODE, TG3_FL_5705,
13155 0x00000000, 0x000007dc },
13156 { MAC_HASH_REG_0, 0x0000,
13157 0x00000000, 0xffffffff },
13158 { MAC_HASH_REG_1, 0x0000,
13159 0x00000000, 0xffffffff },
13160 { MAC_HASH_REG_2, 0x0000,
13161 0x00000000, 0xffffffff },
13162 { MAC_HASH_REG_3, 0x0000,
13163 0x00000000, 0xffffffff },
13165 /* Receive Data and Receive BD Initiator Control Registers. */
13166 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13167 0x00000000, 0xffffffff },
13168 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13169 0x00000000, 0xffffffff },
13170 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13171 0x00000000, 0x00000003 },
13172 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13173 0x00000000, 0xffffffff },
13174 { RCVDBDI_STD_BD+0, 0x0000,
13175 0x00000000, 0xffffffff },
13176 { RCVDBDI_STD_BD+4, 0x0000,
13177 0x00000000, 0xffffffff },
13178 { RCVDBDI_STD_BD+8, 0x0000,
13179 0x00000000, 0xffff0002 },
13180 { RCVDBDI_STD_BD+0xc, 0x0000,
13181 0x00000000, 0xffffffff },
13183 /* Receive BD Initiator Control Registers. */
13184 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13185 0x00000000, 0xffffffff },
13186 { RCVBDI_STD_THRESH, TG3_FL_5705,
13187 0x00000000, 0x000003ff },
13188 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13189 0x00000000, 0xffffffff },
13191 /* Host Coalescing Control Registers. */
13192 { HOSTCC_MODE, TG3_FL_NOT_5705,
13193 0x00000000, 0x00000004 },
13194 { HOSTCC_MODE, TG3_FL_5705,
13195 0x00000000, 0x000000f6 },
13196 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13197 0x00000000, 0xffffffff },
13198 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13199 0x00000000, 0x000003ff },
13200 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13201 0x00000000, 0xffffffff },
13202 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13203 0x00000000, 0x000003ff },
13204 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13205 0x00000000, 0xffffffff },
13206 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13207 0x00000000, 0x000000ff },
13208 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13209 0x00000000, 0xffffffff },
13210 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13211 0x00000000, 0x000000ff },
13212 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13213 0x00000000, 0xffffffff },
13214 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13215 0x00000000, 0xffffffff },
13216 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13217 0x00000000, 0xffffffff },
13218 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13219 0x00000000, 0x000000ff },
13220 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13221 0x00000000, 0xffffffff },
13222 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13223 0x00000000, 0x000000ff },
13224 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13225 0x00000000, 0xffffffff },
13226 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13227 0x00000000, 0xffffffff },
13228 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13229 0x00000000, 0xffffffff },
13230 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13231 0x00000000, 0xffffffff },
13232 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13233 0x00000000, 0xffffffff },
13234 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13235 0xffffffff, 0x00000000 },
13236 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13237 0xffffffff, 0x00000000 },
13239 /* Buffer Manager Control Registers. */
13240 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13241 0x00000000, 0x007fff80 },
13242 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13243 0x00000000, 0x007fffff },
13244 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13245 0x00000000, 0x0000003f },
13246 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13247 0x00000000, 0x000001ff },
13248 { BUFMGR_MB_HIGH_WATER, 0x0000,
13249 0x00000000, 0x000001ff },
13250 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13251 0xffffffff, 0x00000000 },
13252 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13253 0xffffffff, 0x00000000 },
13255 /* Mailbox Registers */
13256 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13257 0x00000000, 0x000001ff },
13258 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13259 0x00000000, 0x000001ff },
13260 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13261 0x00000000, 0x000007ff },
13262 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13263 0x00000000, 0x000001ff },
13265 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13268 is_5705 = is_5750 = 0;
13269 if (tg3_flag(tp, 5705_PLUS)) {
13271 if (tg3_flag(tp, 5750_PLUS))
13275 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13276 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13279 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13282 if (tg3_flag(tp, IS_5788) &&
13283 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13286 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13289 offset = (u32) reg_tbl[i].offset;
13290 read_mask = reg_tbl[i].read_mask;
13291 write_mask = reg_tbl[i].write_mask;
13293 /* Save the original register content */
13294 save_val = tr32(offset);
13296 /* Determine the read-only value. */
13297 read_val = save_val & read_mask;
13299 /* Write zero to the register, then make sure the read-only bits
13300 * are not changed and the read/write bits are all zeros.
13304 val = tr32(offset);
13306 /* Test the read-only and read/write bits. */
13307 if (((val & read_mask) != read_val) || (val & write_mask))
13310 /* Write ones to all the bits defined by RdMask and WrMask, then
13311 * make sure the read-only bits are not changed and the
13312 * read/write bits are all ones.
13314 tw32(offset, read_mask | write_mask);
13316 val = tr32(offset);
13318 /* Test the read-only bits. */
13319 if ((val & read_mask) != read_val)
13322 /* Test the read/write bits. */
13323 if ((val & write_mask) != write_mask)
13326 tw32(offset, save_val);
13332 if (netif_msg_hw(tp))
13333 netdev_err(tp->dev,
13334 "Register test failed at offset %x\n", offset);
13335 tw32(offset, save_val);
13339 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13341 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13345 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13346 for (j = 0; j < len; j += 4) {
13349 tg3_write_mem(tp, offset + j, test_pattern[i]);
13350 tg3_read_mem(tp, offset + j, &val);
13351 if (val != test_pattern[i])
13358 static int tg3_test_memory(struct tg3 *tp)
13360 static struct mem_entry {
13363 } mem_tbl_570x[] = {
13364 { 0x00000000, 0x00b50},
13365 { 0x00002000, 0x1c000},
13366 { 0xffffffff, 0x00000}
13367 }, mem_tbl_5705[] = {
13368 { 0x00000100, 0x0000c},
13369 { 0x00000200, 0x00008},
13370 { 0x00004000, 0x00800},
13371 { 0x00006000, 0x01000},
13372 { 0x00008000, 0x02000},
13373 { 0x00010000, 0x0e000},
13374 { 0xffffffff, 0x00000}
13375 }, mem_tbl_5755[] = {
13376 { 0x00000200, 0x00008},
13377 { 0x00004000, 0x00800},
13378 { 0x00006000, 0x00800},
13379 { 0x00008000, 0x02000},
13380 { 0x00010000, 0x0c000},
13381 { 0xffffffff, 0x00000}
13382 }, mem_tbl_5906[] = {
13383 { 0x00000200, 0x00008},
13384 { 0x00004000, 0x00400},
13385 { 0x00006000, 0x00400},
13386 { 0x00008000, 0x01000},
13387 { 0x00010000, 0x01000},
13388 { 0xffffffff, 0x00000}
13389 }, mem_tbl_5717[] = {
13390 { 0x00000200, 0x00008},
13391 { 0x00010000, 0x0a000},
13392 { 0x00020000, 0x13c00},
13393 { 0xffffffff, 0x00000}
13394 }, mem_tbl_57765[] = {
13395 { 0x00000200, 0x00008},
13396 { 0x00004000, 0x00800},
13397 { 0x00006000, 0x09800},
13398 { 0x00010000, 0x0a000},
13399 { 0xffffffff, 0x00000}
13401 struct mem_entry *mem_tbl;
13405 if (tg3_flag(tp, 5717_PLUS))
13406 mem_tbl = mem_tbl_5717;
13407 else if (tg3_flag(tp, 57765_CLASS) ||
13408 tg3_asic_rev(tp) == ASIC_REV_5762)
13409 mem_tbl = mem_tbl_57765;
13410 else if (tg3_flag(tp, 5755_PLUS))
13411 mem_tbl = mem_tbl_5755;
13412 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13413 mem_tbl = mem_tbl_5906;
13414 else if (tg3_flag(tp, 5705_PLUS))
13415 mem_tbl = mem_tbl_5705;
13417 mem_tbl = mem_tbl_570x;
13419 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13420 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13428 #define TG3_TSO_MSS 500
13430 #define TG3_TSO_IP_HDR_LEN 20
13431 #define TG3_TSO_TCP_HDR_LEN 20
13432 #define TG3_TSO_TCP_OPT_LEN 12
13434 static const u8 tg3_tso_header[] = {
13436 0x45, 0x00, 0x00, 0x00,
13437 0x00, 0x00, 0x40, 0x00,
13438 0x40, 0x06, 0x00, 0x00,
13439 0x0a, 0x00, 0x00, 0x01,
13440 0x0a, 0x00, 0x00, 0x02,
13441 0x0d, 0x00, 0xe0, 0x00,
13442 0x00, 0x00, 0x01, 0x00,
13443 0x00, 0x00, 0x02, 0x00,
13444 0x80, 0x10, 0x10, 0x00,
13445 0x14, 0x09, 0x00, 0x00,
13446 0x01, 0x01, 0x08, 0x0a,
13447 0x11, 0x11, 0x11, 0x11,
13448 0x11, 0x11, 0x11, 0x11,
13451 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13453 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13454 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13456 struct sk_buff *skb;
13457 u8 *tx_data, *rx_data;
13459 int num_pkts, tx_len, rx_len, i, err;
13460 struct tg3_rx_buffer_desc *desc;
13461 struct tg3_napi *tnapi, *rnapi;
13462 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13464 tnapi = &tp->napi[0];
13465 rnapi = &tp->napi[0];
13466 if (tp->irq_cnt > 1) {
13467 if (tg3_flag(tp, ENABLE_RSS))
13468 rnapi = &tp->napi[1];
13469 if (tg3_flag(tp, ENABLE_TSS))
13470 tnapi = &tp->napi[1];
13472 coal_now = tnapi->coal_now | rnapi->coal_now;
13477 skb = netdev_alloc_skb(tp->dev, tx_len);
13481 tx_data = skb_put(skb, tx_len);
13482 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13483 memset(tx_data + ETH_ALEN, 0x0, 8);
13485 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13487 if (tso_loopback) {
13488 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13490 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13491 TG3_TSO_TCP_OPT_LEN;
13493 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13494 sizeof(tg3_tso_header));
13497 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13498 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13500 /* Set the total length field in the IP header */
13501 iph->tot_len = htons((u16)(mss + hdr_len));
13503 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13504 TXD_FLAG_CPU_POST_DMA);
13506 if (tg3_flag(tp, HW_TSO_1) ||
13507 tg3_flag(tp, HW_TSO_2) ||
13508 tg3_flag(tp, HW_TSO_3)) {
13510 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13511 th = (struct tcphdr *)&tx_data[val];
13514 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13516 if (tg3_flag(tp, HW_TSO_3)) {
13517 mss |= (hdr_len & 0xc) << 12;
13518 if (hdr_len & 0x10)
13519 base_flags |= 0x00000010;
13520 base_flags |= (hdr_len & 0x3e0) << 5;
13521 } else if (tg3_flag(tp, HW_TSO_2))
13522 mss |= hdr_len << 9;
13523 else if (tg3_flag(tp, HW_TSO_1) ||
13524 tg3_asic_rev(tp) == ASIC_REV_5705) {
13525 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13527 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13530 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13533 data_off = ETH_HLEN;
13535 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13536 tx_len > VLAN_ETH_FRAME_LEN)
13537 base_flags |= TXD_FLAG_JMB_PKT;
13540 for (i = data_off; i < tx_len; i++)
13541 tx_data[i] = (u8) (i & 0xff);
13543 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13544 if (pci_dma_mapping_error(tp->pdev, map)) {
13545 dev_kfree_skb(skb);
13549 val = tnapi->tx_prod;
13550 tnapi->tx_buffers[val].skb = skb;
13551 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13553 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13558 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13560 budget = tg3_tx_avail(tnapi);
13561 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13562 base_flags | TXD_FLAG_END, mss, 0)) {
13563 tnapi->tx_buffers[val].skb = NULL;
13564 dev_kfree_skb(skb);
13570 /* Sync BD data before updating mailbox */
13573 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13574 tr32_mailbox(tnapi->prodmbox);
13578 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13579 for (i = 0; i < 35; i++) {
13580 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13585 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13586 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13587 if ((tx_idx == tnapi->tx_prod) &&
13588 (rx_idx == (rx_start_idx + num_pkts)))
13592 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13593 dev_kfree_skb(skb);
13595 if (tx_idx != tnapi->tx_prod)
13598 if (rx_idx != rx_start_idx + num_pkts)
13602 while (rx_idx != rx_start_idx) {
13603 desc = &rnapi->rx_rcb[rx_start_idx++];
13604 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13605 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13607 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13608 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13611 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13614 if (!tso_loopback) {
13615 if (rx_len != tx_len)
13618 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13619 if (opaque_key != RXD_OPAQUE_RING_STD)
13622 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13625 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13626 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13627 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13631 if (opaque_key == RXD_OPAQUE_RING_STD) {
13632 rx_data = tpr->rx_std_buffers[desc_idx].data;
13633 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13635 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13636 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13637 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13642 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13643 PCI_DMA_FROMDEVICE);
13645 rx_data += TG3_RX_OFFSET(tp);
13646 for (i = data_off; i < rx_len; i++, val++) {
13647 if (*(rx_data + i) != (u8) (val & 0xff))
13654 /* tg3_free_rings will unmap and free the rx_data */
13659 #define TG3_STD_LOOPBACK_FAILED 1
13660 #define TG3_JMB_LOOPBACK_FAILED 2
13661 #define TG3_TSO_LOOPBACK_FAILED 4
13662 #define TG3_LOOPBACK_FAILED \
13663 (TG3_STD_LOOPBACK_FAILED | \
13664 TG3_JMB_LOOPBACK_FAILED | \
13665 TG3_TSO_LOOPBACK_FAILED)
13667 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13671 u32 jmb_pkt_sz = 9000;
13674 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13676 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13677 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13679 if (!netif_running(tp->dev)) {
13680 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13681 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13683 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13687 err = tg3_reset_hw(tp, true);
13689 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13690 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13692 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13696 if (tg3_flag(tp, ENABLE_RSS)) {
13699 /* Reroute all rx packets to the 1st queue */
13700 for (i = MAC_RSS_INDIR_TBL_0;
13701 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13705 /* HW errata - mac loopback fails in some cases on 5780.
13706 * Normal traffic and PHY loopback are not affected by
13707 * errata. Also, the MAC loopback test is deprecated for
13708 * all newer ASIC revisions.
13710 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13711 !tg3_flag(tp, CPMU_PRESENT)) {
13712 tg3_mac_loopback(tp, true);
13714 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13715 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13717 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13718 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13719 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13721 tg3_mac_loopback(tp, false);
13724 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13725 !tg3_flag(tp, USE_PHYLIB)) {
13728 tg3_phy_lpbk_set(tp, 0, false);
13730 /* Wait for link */
13731 for (i = 0; i < 100; i++) {
13732 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13737 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13738 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13739 if (tg3_flag(tp, TSO_CAPABLE) &&
13740 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13741 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13742 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13743 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13744 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13747 tg3_phy_lpbk_set(tp, 0, true);
13749 /* All link indications report up, but the hardware
13750 * isn't really ready for about 20 msec. Double it
13755 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13756 data[TG3_EXT_LOOPB_TEST] |=
13757 TG3_STD_LOOPBACK_FAILED;
13758 if (tg3_flag(tp, TSO_CAPABLE) &&
13759 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13760 data[TG3_EXT_LOOPB_TEST] |=
13761 TG3_TSO_LOOPBACK_FAILED;
13762 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13763 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13764 data[TG3_EXT_LOOPB_TEST] |=
13765 TG3_JMB_LOOPBACK_FAILED;
13768 /* Re-enable gphy autopowerdown. */
13769 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13770 tg3_phy_toggle_apd(tp, true);
13773 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13774 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13777 tp->phy_flags |= eee_cap;
13782 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13785 struct tg3 *tp = netdev_priv(dev);
13786 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13788 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13789 if (tg3_power_up(tp)) {
13790 etest->flags |= ETH_TEST_FL_FAILED;
13791 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13794 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13797 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13799 if (tg3_test_nvram(tp) != 0) {
13800 etest->flags |= ETH_TEST_FL_FAILED;
13801 data[TG3_NVRAM_TEST] = 1;
13803 if (!doextlpbk && tg3_test_link(tp)) {
13804 etest->flags |= ETH_TEST_FL_FAILED;
13805 data[TG3_LINK_TEST] = 1;
13807 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13808 int err, err2 = 0, irq_sync = 0;
13810 if (netif_running(dev)) {
13812 tg3_netif_stop(tp);
13816 tg3_full_lock(tp, irq_sync);
13817 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13818 err = tg3_nvram_lock(tp);
13819 tg3_halt_cpu(tp, RX_CPU_BASE);
13820 if (!tg3_flag(tp, 5705_PLUS))
13821 tg3_halt_cpu(tp, TX_CPU_BASE);
13823 tg3_nvram_unlock(tp);
13825 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13828 if (tg3_test_registers(tp) != 0) {
13829 etest->flags |= ETH_TEST_FL_FAILED;
13830 data[TG3_REGISTER_TEST] = 1;
13833 if (tg3_test_memory(tp) != 0) {
13834 etest->flags |= ETH_TEST_FL_FAILED;
13835 data[TG3_MEMORY_TEST] = 1;
13839 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13841 if (tg3_test_loopback(tp, data, doextlpbk))
13842 etest->flags |= ETH_TEST_FL_FAILED;
13844 tg3_full_unlock(tp);
13846 if (tg3_test_interrupt(tp) != 0) {
13847 etest->flags |= ETH_TEST_FL_FAILED;
13848 data[TG3_INTERRUPT_TEST] = 1;
13851 tg3_full_lock(tp, 0);
13853 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13854 if (netif_running(dev)) {
13855 tg3_flag_set(tp, INIT_COMPLETE);
13856 err2 = tg3_restart_hw(tp, true);
13858 tg3_netif_start(tp);
13861 tg3_full_unlock(tp);
13863 if (irq_sync && !err2)
13866 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13867 tg3_power_down_prepare(tp);
13871 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13873 struct tg3 *tp = netdev_priv(dev);
13874 struct hwtstamp_config stmpconf;
13876 if (!tg3_flag(tp, PTP_CAPABLE))
13877 return -EOPNOTSUPP;
13879 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13882 if (stmpconf.flags)
13885 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13886 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13889 switch (stmpconf.rx_filter) {
13890 case HWTSTAMP_FILTER_NONE:
13893 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13894 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13895 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13897 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13898 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13899 TG3_RX_PTP_CTL_SYNC_EVNT;
13901 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13902 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13903 TG3_RX_PTP_CTL_DELAY_REQ;
13905 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13906 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13907 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13909 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13910 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13911 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13913 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13914 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13915 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13917 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13918 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13919 TG3_RX_PTP_CTL_SYNC_EVNT;
13921 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13922 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13923 TG3_RX_PTP_CTL_SYNC_EVNT;
13925 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13926 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13927 TG3_RX_PTP_CTL_SYNC_EVNT;
13929 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13930 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13931 TG3_RX_PTP_CTL_DELAY_REQ;
13933 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13934 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13935 TG3_RX_PTP_CTL_DELAY_REQ;
13937 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13938 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13939 TG3_RX_PTP_CTL_DELAY_REQ;
13945 if (netif_running(dev) && tp->rxptpctl)
13946 tw32(TG3_RX_PTP_CTL,
13947 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13949 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13950 tg3_flag_set(tp, TX_TSTAMP_EN);
13952 tg3_flag_clear(tp, TX_TSTAMP_EN);
13954 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13958 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13960 struct tg3 *tp = netdev_priv(dev);
13961 struct hwtstamp_config stmpconf;
13963 if (!tg3_flag(tp, PTP_CAPABLE))
13964 return -EOPNOTSUPP;
13966 stmpconf.flags = 0;
13967 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13968 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13970 switch (tp->rxptpctl) {
13972 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13974 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13975 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13977 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13978 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13980 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13981 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13983 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13984 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13986 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13987 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13989 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13990 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13992 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13993 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13995 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13996 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13998 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13999 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
14001 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
14002 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
14004 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
14005 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
14007 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
14008 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
14015 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
14019 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
14021 struct mii_ioctl_data *data = if_mii(ifr);
14022 struct tg3 *tp = netdev_priv(dev);
14025 if (tg3_flag(tp, USE_PHYLIB)) {
14026 struct phy_device *phydev;
14027 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
14029 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
14030 return phy_mii_ioctl(phydev, ifr, cmd);
14035 data->phy_id = tp->phy_addr;
14038 case SIOCGMIIREG: {
14041 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14042 break; /* We have no PHY */
14044 if (!netif_running(dev))
14047 spin_lock_bh(&tp->lock);
14048 err = __tg3_readphy(tp, data->phy_id & 0x1f,
14049 data->reg_num & 0x1f, &mii_regval);
14050 spin_unlock_bh(&tp->lock);
14052 data->val_out = mii_regval;
14058 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14059 break; /* We have no PHY */
14061 if (!netif_running(dev))
14064 spin_lock_bh(&tp->lock);
14065 err = __tg3_writephy(tp, data->phy_id & 0x1f,
14066 data->reg_num & 0x1f, data->val_in);
14067 spin_unlock_bh(&tp->lock);
14071 case SIOCSHWTSTAMP:
14072 return tg3_hwtstamp_set(dev, ifr);
14074 case SIOCGHWTSTAMP:
14075 return tg3_hwtstamp_get(dev, ifr);
14081 return -EOPNOTSUPP;
14084 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
14086 struct tg3 *tp = netdev_priv(dev);
14088 memcpy(ec, &tp->coal, sizeof(*ec));
14092 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
14094 struct tg3 *tp = netdev_priv(dev);
14095 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
14096 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
14098 if (!tg3_flag(tp, 5705_PLUS)) {
14099 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14100 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14101 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14102 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14105 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14106 (!ec->rx_coalesce_usecs) ||
14107 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14108 (!ec->tx_coalesce_usecs) ||
14109 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14110 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14111 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14112 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14113 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14114 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14115 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14116 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14119 /* Only copy relevant parameters, ignore all others. */
14120 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14121 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14122 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14123 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14124 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14125 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14126 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14127 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14128 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14130 if (netif_running(dev)) {
14131 tg3_full_lock(tp, 0);
14132 __tg3_set_coalesce(tp, &tp->coal);
14133 tg3_full_unlock(tp);
14138 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14140 struct tg3 *tp = netdev_priv(dev);
14142 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14143 netdev_warn(tp->dev, "Board does not support EEE!\n");
14144 return -EOPNOTSUPP;
14147 if (edata->advertised != tp->eee.advertised) {
14148 netdev_warn(tp->dev,
14149 "Direct manipulation of EEE advertisement is not supported\n");
14153 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14154 netdev_warn(tp->dev,
14155 "Maximal Tx Lpi timer supported is %#x(u)\n",
14156 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14162 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14163 tg3_warn_mgmt_link_flap(tp);
14165 if (netif_running(tp->dev)) {
14166 tg3_full_lock(tp, 0);
14169 tg3_full_unlock(tp);
14175 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14177 struct tg3 *tp = netdev_priv(dev);
14179 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14180 netdev_warn(tp->dev,
14181 "Board does not support EEE!\n");
14182 return -EOPNOTSUPP;
14189 static const struct ethtool_ops tg3_ethtool_ops = {
14190 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
14191 ETHTOOL_COALESCE_MAX_FRAMES |
14192 ETHTOOL_COALESCE_USECS_IRQ |
14193 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
14194 ETHTOOL_COALESCE_STATS_BLOCK_USECS,
14195 .get_drvinfo = tg3_get_drvinfo,
14196 .get_regs_len = tg3_get_regs_len,
14197 .get_regs = tg3_get_regs,
14198 .get_wol = tg3_get_wol,
14199 .set_wol = tg3_set_wol,
14200 .get_msglevel = tg3_get_msglevel,
14201 .set_msglevel = tg3_set_msglevel,
14202 .nway_reset = tg3_nway_reset,
14203 .get_link = ethtool_op_get_link,
14204 .get_eeprom_len = tg3_get_eeprom_len,
14205 .get_eeprom = tg3_get_eeprom,
14206 .set_eeprom = tg3_set_eeprom,
14207 .get_ringparam = tg3_get_ringparam,
14208 .set_ringparam = tg3_set_ringparam,
14209 .get_pauseparam = tg3_get_pauseparam,
14210 .set_pauseparam = tg3_set_pauseparam,
14211 .self_test = tg3_self_test,
14212 .get_strings = tg3_get_strings,
14213 .set_phys_id = tg3_set_phys_id,
14214 .get_ethtool_stats = tg3_get_ethtool_stats,
14215 .get_coalesce = tg3_get_coalesce,
14216 .set_coalesce = tg3_set_coalesce,
14217 .get_sset_count = tg3_get_sset_count,
14218 .get_rxnfc = tg3_get_rxnfc,
14219 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14220 .get_rxfh = tg3_get_rxfh,
14221 .set_rxfh = tg3_set_rxfh,
14222 .get_channels = tg3_get_channels,
14223 .set_channels = tg3_set_channels,
14224 .get_ts_info = tg3_get_ts_info,
14225 .get_eee = tg3_get_eee,
14226 .set_eee = tg3_set_eee,
14227 .get_link_ksettings = tg3_get_link_ksettings,
14228 .set_link_ksettings = tg3_set_link_ksettings,
14231 static void tg3_get_stats64(struct net_device *dev,
14232 struct rtnl_link_stats64 *stats)
14234 struct tg3 *tp = netdev_priv(dev);
14236 spin_lock_bh(&tp->lock);
14237 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {
14238 *stats = tp->net_stats_prev;
14239 spin_unlock_bh(&tp->lock);
14243 tg3_get_nstats(tp, stats);
14244 spin_unlock_bh(&tp->lock);
14247 static void tg3_set_rx_mode(struct net_device *dev)
14249 struct tg3 *tp = netdev_priv(dev);
14251 if (!netif_running(dev))
14254 tg3_full_lock(tp, 0);
14255 __tg3_set_rx_mode(dev);
14256 tg3_full_unlock(tp);
14259 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14262 dev->mtu = new_mtu;
14264 if (new_mtu > ETH_DATA_LEN) {
14265 if (tg3_flag(tp, 5780_CLASS)) {
14266 netdev_update_features(dev);
14267 tg3_flag_clear(tp, TSO_CAPABLE);
14269 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14272 if (tg3_flag(tp, 5780_CLASS)) {
14273 tg3_flag_set(tp, TSO_CAPABLE);
14274 netdev_update_features(dev);
14276 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14280 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14282 struct tg3 *tp = netdev_priv(dev);
14284 bool reset_phy = false;
14286 if (!netif_running(dev)) {
14287 /* We'll just catch it later when the
14290 tg3_set_mtu(dev, tp, new_mtu);
14296 tg3_netif_stop(tp);
14298 tg3_set_mtu(dev, tp, new_mtu);
14300 tg3_full_lock(tp, 1);
14302 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14304 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14305 * breaks all requests to 256 bytes.
14307 if (tg3_asic_rev(tp) == ASIC_REV_57766 ||
14308 tg3_asic_rev(tp) == ASIC_REV_5717 ||
14309 tg3_asic_rev(tp) == ASIC_REV_5719 ||
14310 tg3_asic_rev(tp) == ASIC_REV_5720)
14313 err = tg3_restart_hw(tp, reset_phy);
14316 tg3_netif_start(tp);
14318 tg3_full_unlock(tp);
14326 static const struct net_device_ops tg3_netdev_ops = {
14327 .ndo_open = tg3_open,
14328 .ndo_stop = tg3_close,
14329 .ndo_start_xmit = tg3_start_xmit,
14330 .ndo_get_stats64 = tg3_get_stats64,
14331 .ndo_validate_addr = eth_validate_addr,
14332 .ndo_set_rx_mode = tg3_set_rx_mode,
14333 .ndo_set_mac_address = tg3_set_mac_addr,
14334 .ndo_do_ioctl = tg3_ioctl,
14335 .ndo_tx_timeout = tg3_tx_timeout,
14336 .ndo_change_mtu = tg3_change_mtu,
14337 .ndo_fix_features = tg3_fix_features,
14338 .ndo_set_features = tg3_set_features,
14339 #ifdef CONFIG_NET_POLL_CONTROLLER
14340 .ndo_poll_controller = tg3_poll_controller,
14344 static void tg3_get_eeprom_size(struct tg3 *tp)
14346 u32 cursize, val, magic;
14348 tp->nvram_size = EEPROM_CHIP_SIZE;
14350 if (tg3_nvram_read(tp, 0, &magic) != 0)
14353 if ((magic != TG3_EEPROM_MAGIC) &&
14354 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14355 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14359 * Size the chip by reading offsets at increasing powers of two.
14360 * When we encounter our validation signature, we know the addressing
14361 * has wrapped around, and thus have our chip size.
14365 while (cursize < tp->nvram_size) {
14366 if (tg3_nvram_read(tp, cursize, &val) != 0)
14375 tp->nvram_size = cursize;
14378 static void tg3_get_nvram_size(struct tg3 *tp)
14382 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14385 /* Selfboot format */
14386 if (val != TG3_EEPROM_MAGIC) {
14387 tg3_get_eeprom_size(tp);
14391 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14393 /* This is confusing. We want to operate on the
14394 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14395 * call will read from NVRAM and byteswap the data
14396 * according to the byteswapping settings for all
14397 * other register accesses. This ensures the data we
14398 * want will always reside in the lower 16-bits.
14399 * However, the data in NVRAM is in LE format, which
14400 * means the data from the NVRAM read will always be
14401 * opposite the endianness of the CPU. The 16-bit
14402 * byteswap then brings the data to CPU endianness.
14404 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14408 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14411 static void tg3_get_nvram_info(struct tg3 *tp)
14415 nvcfg1 = tr32(NVRAM_CFG1);
14416 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14417 tg3_flag_set(tp, FLASH);
14419 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14420 tw32(NVRAM_CFG1, nvcfg1);
14423 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14424 tg3_flag(tp, 5780_CLASS)) {
14425 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14426 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14427 tp->nvram_jedecnum = JEDEC_ATMEL;
14428 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14429 tg3_flag_set(tp, NVRAM_BUFFERED);
14431 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14432 tp->nvram_jedecnum = JEDEC_ATMEL;
14433 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14435 case FLASH_VENDOR_ATMEL_EEPROM:
14436 tp->nvram_jedecnum = JEDEC_ATMEL;
14437 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14438 tg3_flag_set(tp, NVRAM_BUFFERED);
14440 case FLASH_VENDOR_ST:
14441 tp->nvram_jedecnum = JEDEC_ST;
14442 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14443 tg3_flag_set(tp, NVRAM_BUFFERED);
14445 case FLASH_VENDOR_SAIFUN:
14446 tp->nvram_jedecnum = JEDEC_SAIFUN;
14447 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14449 case FLASH_VENDOR_SST_SMALL:
14450 case FLASH_VENDOR_SST_LARGE:
14451 tp->nvram_jedecnum = JEDEC_SST;
14452 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14456 tp->nvram_jedecnum = JEDEC_ATMEL;
14457 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14458 tg3_flag_set(tp, NVRAM_BUFFERED);
14462 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14464 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14465 case FLASH_5752PAGE_SIZE_256:
14466 tp->nvram_pagesize = 256;
14468 case FLASH_5752PAGE_SIZE_512:
14469 tp->nvram_pagesize = 512;
14471 case FLASH_5752PAGE_SIZE_1K:
14472 tp->nvram_pagesize = 1024;
14474 case FLASH_5752PAGE_SIZE_2K:
14475 tp->nvram_pagesize = 2048;
14477 case FLASH_5752PAGE_SIZE_4K:
14478 tp->nvram_pagesize = 4096;
14480 case FLASH_5752PAGE_SIZE_264:
14481 tp->nvram_pagesize = 264;
14483 case FLASH_5752PAGE_SIZE_528:
14484 tp->nvram_pagesize = 528;
14489 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14493 nvcfg1 = tr32(NVRAM_CFG1);
14495 /* NVRAM protection for TPM */
14496 if (nvcfg1 & (1 << 27))
14497 tg3_flag_set(tp, PROTECTED_NVRAM);
14499 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14500 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14501 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14502 tp->nvram_jedecnum = JEDEC_ATMEL;
14503 tg3_flag_set(tp, NVRAM_BUFFERED);
14505 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14506 tp->nvram_jedecnum = JEDEC_ATMEL;
14507 tg3_flag_set(tp, NVRAM_BUFFERED);
14508 tg3_flag_set(tp, FLASH);
14510 case FLASH_5752VENDOR_ST_M45PE10:
14511 case FLASH_5752VENDOR_ST_M45PE20:
14512 case FLASH_5752VENDOR_ST_M45PE40:
14513 tp->nvram_jedecnum = JEDEC_ST;
14514 tg3_flag_set(tp, NVRAM_BUFFERED);
14515 tg3_flag_set(tp, FLASH);
14519 if (tg3_flag(tp, FLASH)) {
14520 tg3_nvram_get_pagesize(tp, nvcfg1);
14522 /* For eeprom, set pagesize to maximum eeprom size */
14523 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14525 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14526 tw32(NVRAM_CFG1, nvcfg1);
14530 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14532 u32 nvcfg1, protect = 0;
14534 nvcfg1 = tr32(NVRAM_CFG1);
14536 /* NVRAM protection for TPM */
14537 if (nvcfg1 & (1 << 27)) {
14538 tg3_flag_set(tp, PROTECTED_NVRAM);
14542 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14544 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14545 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14546 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14547 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14548 tp->nvram_jedecnum = JEDEC_ATMEL;
14549 tg3_flag_set(tp, NVRAM_BUFFERED);
14550 tg3_flag_set(tp, FLASH);
14551 tp->nvram_pagesize = 264;
14552 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14553 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14554 tp->nvram_size = (protect ? 0x3e200 :
14555 TG3_NVRAM_SIZE_512KB);
14556 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14557 tp->nvram_size = (protect ? 0x1f200 :
14558 TG3_NVRAM_SIZE_256KB);
14560 tp->nvram_size = (protect ? 0x1f200 :
14561 TG3_NVRAM_SIZE_128KB);
14563 case FLASH_5752VENDOR_ST_M45PE10:
14564 case FLASH_5752VENDOR_ST_M45PE20:
14565 case FLASH_5752VENDOR_ST_M45PE40:
14566 tp->nvram_jedecnum = JEDEC_ST;
14567 tg3_flag_set(tp, NVRAM_BUFFERED);
14568 tg3_flag_set(tp, FLASH);
14569 tp->nvram_pagesize = 256;
14570 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14571 tp->nvram_size = (protect ?
14572 TG3_NVRAM_SIZE_64KB :
14573 TG3_NVRAM_SIZE_128KB);
14574 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14575 tp->nvram_size = (protect ?
14576 TG3_NVRAM_SIZE_64KB :
14577 TG3_NVRAM_SIZE_256KB);
14579 tp->nvram_size = (protect ?
14580 TG3_NVRAM_SIZE_128KB :
14581 TG3_NVRAM_SIZE_512KB);
14586 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14590 nvcfg1 = tr32(NVRAM_CFG1);
14592 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14593 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14594 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14595 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14596 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14597 tp->nvram_jedecnum = JEDEC_ATMEL;
14598 tg3_flag_set(tp, NVRAM_BUFFERED);
14599 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14601 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14602 tw32(NVRAM_CFG1, nvcfg1);
14604 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14605 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14606 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14607 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14608 tp->nvram_jedecnum = JEDEC_ATMEL;
14609 tg3_flag_set(tp, NVRAM_BUFFERED);
14610 tg3_flag_set(tp, FLASH);
14611 tp->nvram_pagesize = 264;
14613 case FLASH_5752VENDOR_ST_M45PE10:
14614 case FLASH_5752VENDOR_ST_M45PE20:
14615 case FLASH_5752VENDOR_ST_M45PE40:
14616 tp->nvram_jedecnum = JEDEC_ST;
14617 tg3_flag_set(tp, NVRAM_BUFFERED);
14618 tg3_flag_set(tp, FLASH);
14619 tp->nvram_pagesize = 256;
14624 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14626 u32 nvcfg1, protect = 0;
14628 nvcfg1 = tr32(NVRAM_CFG1);
14630 /* NVRAM protection for TPM */
14631 if (nvcfg1 & (1 << 27)) {
14632 tg3_flag_set(tp, PROTECTED_NVRAM);
14636 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14638 case FLASH_5761VENDOR_ATMEL_ADB021D:
14639 case FLASH_5761VENDOR_ATMEL_ADB041D:
14640 case FLASH_5761VENDOR_ATMEL_ADB081D:
14641 case FLASH_5761VENDOR_ATMEL_ADB161D:
14642 case FLASH_5761VENDOR_ATMEL_MDB021D:
14643 case FLASH_5761VENDOR_ATMEL_MDB041D:
14644 case FLASH_5761VENDOR_ATMEL_MDB081D:
14645 case FLASH_5761VENDOR_ATMEL_MDB161D:
14646 tp->nvram_jedecnum = JEDEC_ATMEL;
14647 tg3_flag_set(tp, NVRAM_BUFFERED);
14648 tg3_flag_set(tp, FLASH);
14649 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14650 tp->nvram_pagesize = 256;
14652 case FLASH_5761VENDOR_ST_A_M45PE20:
14653 case FLASH_5761VENDOR_ST_A_M45PE40:
14654 case FLASH_5761VENDOR_ST_A_M45PE80:
14655 case FLASH_5761VENDOR_ST_A_M45PE16:
14656 case FLASH_5761VENDOR_ST_M_M45PE20:
14657 case FLASH_5761VENDOR_ST_M_M45PE40:
14658 case FLASH_5761VENDOR_ST_M_M45PE80:
14659 case FLASH_5761VENDOR_ST_M_M45PE16:
14660 tp->nvram_jedecnum = JEDEC_ST;
14661 tg3_flag_set(tp, NVRAM_BUFFERED);
14662 tg3_flag_set(tp, FLASH);
14663 tp->nvram_pagesize = 256;
14668 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14671 case FLASH_5761VENDOR_ATMEL_ADB161D:
14672 case FLASH_5761VENDOR_ATMEL_MDB161D:
14673 case FLASH_5761VENDOR_ST_A_M45PE16:
14674 case FLASH_5761VENDOR_ST_M_M45PE16:
14675 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14677 case FLASH_5761VENDOR_ATMEL_ADB081D:
14678 case FLASH_5761VENDOR_ATMEL_MDB081D:
14679 case FLASH_5761VENDOR_ST_A_M45PE80:
14680 case FLASH_5761VENDOR_ST_M_M45PE80:
14681 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14683 case FLASH_5761VENDOR_ATMEL_ADB041D:
14684 case FLASH_5761VENDOR_ATMEL_MDB041D:
14685 case FLASH_5761VENDOR_ST_A_M45PE40:
14686 case FLASH_5761VENDOR_ST_M_M45PE40:
14687 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14689 case FLASH_5761VENDOR_ATMEL_ADB021D:
14690 case FLASH_5761VENDOR_ATMEL_MDB021D:
14691 case FLASH_5761VENDOR_ST_A_M45PE20:
14692 case FLASH_5761VENDOR_ST_M_M45PE20:
14693 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14699 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14701 tp->nvram_jedecnum = JEDEC_ATMEL;
14702 tg3_flag_set(tp, NVRAM_BUFFERED);
14703 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14706 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14710 nvcfg1 = tr32(NVRAM_CFG1);
14712 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14713 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14714 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14715 tp->nvram_jedecnum = JEDEC_ATMEL;
14716 tg3_flag_set(tp, NVRAM_BUFFERED);
14717 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14719 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14720 tw32(NVRAM_CFG1, nvcfg1);
14722 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14723 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14724 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14725 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14726 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14727 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14728 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14729 tp->nvram_jedecnum = JEDEC_ATMEL;
14730 tg3_flag_set(tp, NVRAM_BUFFERED);
14731 tg3_flag_set(tp, FLASH);
14733 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14734 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14735 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14736 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14737 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14739 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14740 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14741 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14743 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14744 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14745 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14749 case FLASH_5752VENDOR_ST_M45PE10:
14750 case FLASH_5752VENDOR_ST_M45PE20:
14751 case FLASH_5752VENDOR_ST_M45PE40:
14752 tp->nvram_jedecnum = JEDEC_ST;
14753 tg3_flag_set(tp, NVRAM_BUFFERED);
14754 tg3_flag_set(tp, FLASH);
14756 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14757 case FLASH_5752VENDOR_ST_M45PE10:
14758 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14760 case FLASH_5752VENDOR_ST_M45PE20:
14761 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14763 case FLASH_5752VENDOR_ST_M45PE40:
14764 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14769 tg3_flag_set(tp, NO_NVRAM);
14773 tg3_nvram_get_pagesize(tp, nvcfg1);
14774 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14775 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14779 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14783 nvcfg1 = tr32(NVRAM_CFG1);
14785 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14786 case FLASH_5717VENDOR_ATMEL_EEPROM:
14787 case FLASH_5717VENDOR_MICRO_EEPROM:
14788 tp->nvram_jedecnum = JEDEC_ATMEL;
14789 tg3_flag_set(tp, NVRAM_BUFFERED);
14790 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14792 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14793 tw32(NVRAM_CFG1, nvcfg1);
14795 case FLASH_5717VENDOR_ATMEL_MDB011D:
14796 case FLASH_5717VENDOR_ATMEL_ADB011B:
14797 case FLASH_5717VENDOR_ATMEL_ADB011D:
14798 case FLASH_5717VENDOR_ATMEL_MDB021D:
14799 case FLASH_5717VENDOR_ATMEL_ADB021B:
14800 case FLASH_5717VENDOR_ATMEL_ADB021D:
14801 case FLASH_5717VENDOR_ATMEL_45USPT:
14802 tp->nvram_jedecnum = JEDEC_ATMEL;
14803 tg3_flag_set(tp, NVRAM_BUFFERED);
14804 tg3_flag_set(tp, FLASH);
14806 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14807 case FLASH_5717VENDOR_ATMEL_MDB021D:
14808 /* Detect size with tg3_nvram_get_size() */
14810 case FLASH_5717VENDOR_ATMEL_ADB021B:
14811 case FLASH_5717VENDOR_ATMEL_ADB021D:
14812 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14815 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14819 case FLASH_5717VENDOR_ST_M_M25PE10:
14820 case FLASH_5717VENDOR_ST_A_M25PE10:
14821 case FLASH_5717VENDOR_ST_M_M45PE10:
14822 case FLASH_5717VENDOR_ST_A_M45PE10:
14823 case FLASH_5717VENDOR_ST_M_M25PE20:
14824 case FLASH_5717VENDOR_ST_A_M25PE20:
14825 case FLASH_5717VENDOR_ST_M_M45PE20:
14826 case FLASH_5717VENDOR_ST_A_M45PE20:
14827 case FLASH_5717VENDOR_ST_25USPT:
14828 case FLASH_5717VENDOR_ST_45USPT:
14829 tp->nvram_jedecnum = JEDEC_ST;
14830 tg3_flag_set(tp, NVRAM_BUFFERED);
14831 tg3_flag_set(tp, FLASH);
14833 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14834 case FLASH_5717VENDOR_ST_M_M25PE20:
14835 case FLASH_5717VENDOR_ST_M_M45PE20:
14836 /* Detect size with tg3_nvram_get_size() */
14838 case FLASH_5717VENDOR_ST_A_M25PE20:
14839 case FLASH_5717VENDOR_ST_A_M45PE20:
14840 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14843 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14848 tg3_flag_set(tp, NO_NVRAM);
14852 tg3_nvram_get_pagesize(tp, nvcfg1);
14853 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14854 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14857 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14859 u32 nvcfg1, nvmpinstrp, nv_status;
14861 nvcfg1 = tr32(NVRAM_CFG1);
14862 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14864 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14865 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14866 tg3_flag_set(tp, NO_NVRAM);
14870 switch (nvmpinstrp) {
14871 case FLASH_5762_MX25L_100:
14872 case FLASH_5762_MX25L_200:
14873 case FLASH_5762_MX25L_400:
14874 case FLASH_5762_MX25L_800:
14875 case FLASH_5762_MX25L_160_320:
14876 tp->nvram_pagesize = 4096;
14877 tp->nvram_jedecnum = JEDEC_MACRONIX;
14878 tg3_flag_set(tp, NVRAM_BUFFERED);
14879 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14880 tg3_flag_set(tp, FLASH);
14881 nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
14883 (1 << (nv_status >> AUTOSENSE_DEVID &
14884 AUTOSENSE_DEVID_MASK)
14885 << AUTOSENSE_SIZE_IN_MB);
14888 case FLASH_5762_EEPROM_HD:
14889 nvmpinstrp = FLASH_5720_EEPROM_HD;
14891 case FLASH_5762_EEPROM_LD:
14892 nvmpinstrp = FLASH_5720_EEPROM_LD;
14894 case FLASH_5720VENDOR_M_ST_M45PE20:
14895 /* This pinstrap supports multiple sizes, so force it
14896 * to read the actual size from location 0xf0.
14898 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14903 switch (nvmpinstrp) {
14904 case FLASH_5720_EEPROM_HD:
14905 case FLASH_5720_EEPROM_LD:
14906 tp->nvram_jedecnum = JEDEC_ATMEL;
14907 tg3_flag_set(tp, NVRAM_BUFFERED);
14909 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14910 tw32(NVRAM_CFG1, nvcfg1);
14911 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14912 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14914 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14916 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14917 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14918 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14919 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14920 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14921 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14922 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14923 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14924 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14925 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14926 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14927 case FLASH_5720VENDOR_ATMEL_45USPT:
14928 tp->nvram_jedecnum = JEDEC_ATMEL;
14929 tg3_flag_set(tp, NVRAM_BUFFERED);
14930 tg3_flag_set(tp, FLASH);
14932 switch (nvmpinstrp) {
14933 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14934 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14935 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14936 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14938 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14939 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14940 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14941 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14943 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14944 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14945 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14948 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14949 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14953 case FLASH_5720VENDOR_M_ST_M25PE10:
14954 case FLASH_5720VENDOR_M_ST_M45PE10:
14955 case FLASH_5720VENDOR_A_ST_M25PE10:
14956 case FLASH_5720VENDOR_A_ST_M45PE10:
14957 case FLASH_5720VENDOR_M_ST_M25PE20:
14958 case FLASH_5720VENDOR_M_ST_M45PE20:
14959 case FLASH_5720VENDOR_A_ST_M25PE20:
14960 case FLASH_5720VENDOR_A_ST_M45PE20:
14961 case FLASH_5720VENDOR_M_ST_M25PE40:
14962 case FLASH_5720VENDOR_M_ST_M45PE40:
14963 case FLASH_5720VENDOR_A_ST_M25PE40:
14964 case FLASH_5720VENDOR_A_ST_M45PE40:
14965 case FLASH_5720VENDOR_M_ST_M25PE80:
14966 case FLASH_5720VENDOR_M_ST_M45PE80:
14967 case FLASH_5720VENDOR_A_ST_M25PE80:
14968 case FLASH_5720VENDOR_A_ST_M45PE80:
14969 case FLASH_5720VENDOR_ST_25USPT:
14970 case FLASH_5720VENDOR_ST_45USPT:
14971 tp->nvram_jedecnum = JEDEC_ST;
14972 tg3_flag_set(tp, NVRAM_BUFFERED);
14973 tg3_flag_set(tp, FLASH);
14975 switch (nvmpinstrp) {
14976 case FLASH_5720VENDOR_M_ST_M25PE20:
14977 case FLASH_5720VENDOR_M_ST_M45PE20:
14978 case FLASH_5720VENDOR_A_ST_M25PE20:
14979 case FLASH_5720VENDOR_A_ST_M45PE20:
14980 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14982 case FLASH_5720VENDOR_M_ST_M25PE40:
14983 case FLASH_5720VENDOR_M_ST_M45PE40:
14984 case FLASH_5720VENDOR_A_ST_M25PE40:
14985 case FLASH_5720VENDOR_A_ST_M45PE40:
14986 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14988 case FLASH_5720VENDOR_M_ST_M25PE80:
14989 case FLASH_5720VENDOR_M_ST_M45PE80:
14990 case FLASH_5720VENDOR_A_ST_M25PE80:
14991 case FLASH_5720VENDOR_A_ST_M45PE80:
14992 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14995 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14996 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
15001 tg3_flag_set(tp, NO_NVRAM);
15005 tg3_nvram_get_pagesize(tp, nvcfg1);
15006 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
15007 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
15009 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
15012 if (tg3_nvram_read(tp, 0, &val))
15015 if (val != TG3_EEPROM_MAGIC &&
15016 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
15017 tg3_flag_set(tp, NO_NVRAM);
15021 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
15022 static void tg3_nvram_init(struct tg3 *tp)
15024 if (tg3_flag(tp, IS_SSB_CORE)) {
15025 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
15026 tg3_flag_clear(tp, NVRAM);
15027 tg3_flag_clear(tp, NVRAM_BUFFERED);
15028 tg3_flag_set(tp, NO_NVRAM);
15032 tw32_f(GRC_EEPROM_ADDR,
15033 (EEPROM_ADDR_FSM_RESET |
15034 (EEPROM_DEFAULT_CLOCK_PERIOD <<
15035 EEPROM_ADDR_CLKPERD_SHIFT)));
15039 /* Enable seeprom accesses. */
15040 tw32_f(GRC_LOCAL_CTRL,
15041 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
15044 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15045 tg3_asic_rev(tp) != ASIC_REV_5701) {
15046 tg3_flag_set(tp, NVRAM);
15048 if (tg3_nvram_lock(tp)) {
15049 netdev_warn(tp->dev,
15050 "Cannot get nvram lock, %s failed\n",
15054 tg3_enable_nvram_access(tp);
15056 tp->nvram_size = 0;
15058 if (tg3_asic_rev(tp) == ASIC_REV_5752)
15059 tg3_get_5752_nvram_info(tp);
15060 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
15061 tg3_get_5755_nvram_info(tp);
15062 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
15063 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15064 tg3_asic_rev(tp) == ASIC_REV_5785)
15065 tg3_get_5787_nvram_info(tp);
15066 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
15067 tg3_get_5761_nvram_info(tp);
15068 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
15069 tg3_get_5906_nvram_info(tp);
15070 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
15071 tg3_flag(tp, 57765_CLASS))
15072 tg3_get_57780_nvram_info(tp);
15073 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15074 tg3_asic_rev(tp) == ASIC_REV_5719)
15075 tg3_get_5717_nvram_info(tp);
15076 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
15077 tg3_asic_rev(tp) == ASIC_REV_5762)
15078 tg3_get_5720_nvram_info(tp);
15080 tg3_get_nvram_info(tp);
15082 if (tp->nvram_size == 0)
15083 tg3_get_nvram_size(tp);
15085 tg3_disable_nvram_access(tp);
15086 tg3_nvram_unlock(tp);
15089 tg3_flag_clear(tp, NVRAM);
15090 tg3_flag_clear(tp, NVRAM_BUFFERED);
15092 tg3_get_eeprom_size(tp);
15096 struct subsys_tbl_ent {
15097 u16 subsys_vendor, subsys_devid;
15101 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
15102 /* Broadcom boards. */
15103 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15104 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
15105 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15106 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
15107 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15108 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
15109 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15110 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15111 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15112 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
15113 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15114 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
15115 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15116 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15117 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15118 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
15119 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15120 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
15121 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15122 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
15123 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15124 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15127 { TG3PCI_SUBVENDOR_ID_3COM,
15128 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15129 { TG3PCI_SUBVENDOR_ID_3COM,
15130 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15131 { TG3PCI_SUBVENDOR_ID_3COM,
15132 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15133 { TG3PCI_SUBVENDOR_ID_3COM,
15134 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15135 { TG3PCI_SUBVENDOR_ID_3COM,
15136 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15139 { TG3PCI_SUBVENDOR_ID_DELL,
15140 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15141 { TG3PCI_SUBVENDOR_ID_DELL,
15142 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15143 { TG3PCI_SUBVENDOR_ID_DELL,
15144 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15145 { TG3PCI_SUBVENDOR_ID_DELL,
15146 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15148 /* Compaq boards. */
15149 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15150 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15151 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15152 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15153 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15154 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15155 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15156 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15157 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15158 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15161 { TG3PCI_SUBVENDOR_ID_IBM,
15162 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15165 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15169 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15170 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15171 tp->pdev->subsystem_vendor) &&
15172 (subsys_id_to_phy_id[i].subsys_devid ==
15173 tp->pdev->subsystem_device))
15174 return &subsys_id_to_phy_id[i];
15179 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15183 tp->phy_id = TG3_PHY_ID_INVALID;
15184 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15186 /* Assume an onboard device and WOL capable by default. */
15187 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15188 tg3_flag_set(tp, WOL_CAP);
15190 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15191 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15192 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15193 tg3_flag_set(tp, IS_NIC);
15195 val = tr32(VCPU_CFGSHDW);
15196 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15197 tg3_flag_set(tp, ASPM_WORKAROUND);
15198 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15199 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15200 tg3_flag_set(tp, WOL_ENABLE);
15201 device_set_wakeup_enable(&tp->pdev->dev, true);
15206 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15207 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15208 u32 nic_cfg, led_cfg;
15209 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15210 u32 nic_phy_id, ver, eeprom_phy_id;
15211 int eeprom_phy_serdes = 0;
15213 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15214 tp->nic_sram_data_cfg = nic_cfg;
15216 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15217 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15218 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15219 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15220 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15221 (ver > 0) && (ver < 0x100))
15222 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15224 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15225 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15227 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15228 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15229 tg3_asic_rev(tp) == ASIC_REV_5720)
15230 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15232 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15233 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15234 eeprom_phy_serdes = 1;
15236 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15237 if (nic_phy_id != 0) {
15238 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15239 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15241 eeprom_phy_id = (id1 >> 16) << 10;
15242 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15243 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15247 tp->phy_id = eeprom_phy_id;
15248 if (eeprom_phy_serdes) {
15249 if (!tg3_flag(tp, 5705_PLUS))
15250 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15252 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15255 if (tg3_flag(tp, 5750_PLUS))
15256 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15257 SHASTA_EXT_LED_MODE_MASK);
15259 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15263 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15264 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15267 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15268 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15271 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15272 tp->led_ctrl = LED_CTRL_MODE_MAC;
15274 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15275 * read on some older 5700/5701 bootcode.
15277 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15278 tg3_asic_rev(tp) == ASIC_REV_5701)
15279 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15283 case SHASTA_EXT_LED_SHARED:
15284 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15285 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15286 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15287 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15288 LED_CTRL_MODE_PHY_2);
15290 if (tg3_flag(tp, 5717_PLUS) ||
15291 tg3_asic_rev(tp) == ASIC_REV_5762)
15292 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15293 LED_CTRL_BLINK_RATE_MASK;
15297 case SHASTA_EXT_LED_MAC:
15298 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15301 case SHASTA_EXT_LED_COMBO:
15302 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15303 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15304 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15305 LED_CTRL_MODE_PHY_2);
15310 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15311 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15312 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15313 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15315 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15316 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15318 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15319 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15320 if ((tp->pdev->subsystem_vendor ==
15321 PCI_VENDOR_ID_ARIMA) &&
15322 (tp->pdev->subsystem_device == 0x205a ||
15323 tp->pdev->subsystem_device == 0x2063))
15324 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15326 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15327 tg3_flag_set(tp, IS_NIC);
15330 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15331 tg3_flag_set(tp, ENABLE_ASF);
15332 if (tg3_flag(tp, 5750_PLUS))
15333 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15336 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15337 tg3_flag(tp, 5750_PLUS))
15338 tg3_flag_set(tp, ENABLE_APE);
15340 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15341 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15342 tg3_flag_clear(tp, WOL_CAP);
15344 if (tg3_flag(tp, WOL_CAP) &&
15345 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15346 tg3_flag_set(tp, WOL_ENABLE);
15347 device_set_wakeup_enable(&tp->pdev->dev, true);
15350 if (cfg2 & (1 << 17))
15351 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15353 /* serdes signal pre-emphasis in register 0x590 set by */
15354 /* bootcode if bit 18 is set */
15355 if (cfg2 & (1 << 18))
15356 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15358 if ((tg3_flag(tp, 57765_PLUS) ||
15359 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15360 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15361 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15362 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15364 if (tg3_flag(tp, PCI_EXPRESS)) {
15367 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15368 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15369 !tg3_flag(tp, 57765_PLUS) &&
15370 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15371 tg3_flag_set(tp, ASPM_WORKAROUND);
15372 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15373 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15374 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15375 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15378 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15379 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15380 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15381 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15382 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15383 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15385 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15386 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15389 if (tg3_flag(tp, WOL_CAP))
15390 device_set_wakeup_enable(&tp->pdev->dev,
15391 tg3_flag(tp, WOL_ENABLE));
15393 device_set_wakeup_capable(&tp->pdev->dev, false);
15396 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15399 u32 val2, off = offset * 8;
15401 err = tg3_nvram_lock(tp);
15405 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15406 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15407 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15408 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15411 for (i = 0; i < 100; i++) {
15412 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15413 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15414 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15420 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15422 tg3_nvram_unlock(tp);
15423 if (val2 & APE_OTP_STATUS_CMD_DONE)
15429 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15434 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15435 tw32(OTP_CTRL, cmd);
15437 /* Wait for up to 1 ms for command to execute. */
15438 for (i = 0; i < 100; i++) {
15439 val = tr32(OTP_STATUS);
15440 if (val & OTP_STATUS_CMD_DONE)
15445 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15448 /* Read the gphy configuration from the OTP region of the chip. The gphy
15449 * configuration is a 32-bit value that straddles the alignment boundary.
15450 * We do two 32-bit reads and then shift and merge the results.
15452 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15454 u32 bhalf_otp, thalf_otp;
15456 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15458 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15461 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15463 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15466 thalf_otp = tr32(OTP_READ_DATA);
15468 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15470 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15473 bhalf_otp = tr32(OTP_READ_DATA);
15475 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15478 static void tg3_phy_init_link_config(struct tg3 *tp)
15480 u32 adv = ADVERTISED_Autoneg;
15482 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15483 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15484 adv |= ADVERTISED_1000baseT_Half;
15485 adv |= ADVERTISED_1000baseT_Full;
15488 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15489 adv |= ADVERTISED_100baseT_Half |
15490 ADVERTISED_100baseT_Full |
15491 ADVERTISED_10baseT_Half |
15492 ADVERTISED_10baseT_Full |
15495 adv |= ADVERTISED_FIBRE;
15497 tp->link_config.advertising = adv;
15498 tp->link_config.speed = SPEED_UNKNOWN;
15499 tp->link_config.duplex = DUPLEX_UNKNOWN;
15500 tp->link_config.autoneg = AUTONEG_ENABLE;
15501 tp->link_config.active_speed = SPEED_UNKNOWN;
15502 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15507 static int tg3_phy_probe(struct tg3 *tp)
15509 u32 hw_phy_id_1, hw_phy_id_2;
15510 u32 hw_phy_id, hw_phy_id_masked;
15513 /* flow control autonegotiation is default behavior */
15514 tg3_flag_set(tp, PAUSE_AUTONEG);
15515 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15517 if (tg3_flag(tp, ENABLE_APE)) {
15518 switch (tp->pci_fn) {
15520 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15523 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15526 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15529 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15534 if (!tg3_flag(tp, ENABLE_ASF) &&
15535 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15536 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15537 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15538 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15540 if (tg3_flag(tp, USE_PHYLIB))
15541 return tg3_phy_init(tp);
15543 /* Reading the PHY ID register can conflict with ASF
15544 * firmware access to the PHY hardware.
15547 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15548 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15550 /* Now read the physical PHY_ID from the chip and verify
15551 * that it is sane. If it doesn't look good, we fall back
15552 * to either the hard-coded table based PHY_ID and failing
15553 * that the value found in the eeprom area.
15555 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15556 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15558 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15559 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15560 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15562 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15565 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15566 tp->phy_id = hw_phy_id;
15567 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15568 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15570 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15572 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15573 /* Do nothing, phy ID already set up in
15574 * tg3_get_eeprom_hw_cfg().
15577 struct subsys_tbl_ent *p;
15579 /* No eeprom signature? Try the hardcoded
15580 * subsys device table.
15582 p = tg3_lookup_by_subsys(tp);
15584 tp->phy_id = p->phy_id;
15585 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15586 /* For now we saw the IDs 0xbc050cd0,
15587 * 0xbc050f80 and 0xbc050c30 on devices
15588 * connected to an BCM4785 and there are
15589 * probably more. Just assume that the phy is
15590 * supported when it is connected to a SSB core
15597 tp->phy_id == TG3_PHY_ID_BCM8002)
15598 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15602 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15603 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15604 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15605 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15606 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15607 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15608 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15609 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15610 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15611 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15613 tp->eee.supported = SUPPORTED_100baseT_Full |
15614 SUPPORTED_1000baseT_Full;
15615 tp->eee.advertised = ADVERTISED_100baseT_Full |
15616 ADVERTISED_1000baseT_Full;
15617 tp->eee.eee_enabled = 1;
15618 tp->eee.tx_lpi_enabled = 1;
15619 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15622 tg3_phy_init_link_config(tp);
15624 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15625 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15626 !tg3_flag(tp, ENABLE_APE) &&
15627 !tg3_flag(tp, ENABLE_ASF)) {
15630 tg3_readphy(tp, MII_BMSR, &bmsr);
15631 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15632 (bmsr & BMSR_LSTATUS))
15633 goto skip_phy_reset;
15635 err = tg3_phy_reset(tp);
15639 tg3_phy_set_wirespeed(tp);
15641 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15642 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15643 tp->link_config.flowctrl);
15645 tg3_writephy(tp, MII_BMCR,
15646 BMCR_ANENABLE | BMCR_ANRESTART);
15651 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15652 err = tg3_init_5401phy_dsp(tp);
15656 err = tg3_init_5401phy_dsp(tp);
15662 static void tg3_read_vpd(struct tg3 *tp)
15665 unsigned int block_end, rosize, len;
15669 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15673 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15675 goto out_not_found;
15677 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15678 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15679 i += PCI_VPD_LRDT_TAG_SIZE;
15681 if (block_end > vpdlen)
15682 goto out_not_found;
15684 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15685 PCI_VPD_RO_KEYWORD_MFR_ID);
15687 len = pci_vpd_info_field_size(&vpd_data[j]);
15689 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15690 if (j + len > block_end || len != 4 ||
15691 memcmp(&vpd_data[j], "1028", 4))
15694 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15695 PCI_VPD_RO_KEYWORD_VENDOR0);
15699 len = pci_vpd_info_field_size(&vpd_data[j]);
15701 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15702 if (j + len > block_end)
15705 if (len >= sizeof(tp->fw_ver))
15706 len = sizeof(tp->fw_ver) - 1;
15707 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15708 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15713 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15714 PCI_VPD_RO_KEYWORD_PARTNO);
15716 goto out_not_found;
15718 len = pci_vpd_info_field_size(&vpd_data[i]);
15720 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15721 if (len > TG3_BPN_SIZE ||
15722 (len + i) > vpdlen)
15723 goto out_not_found;
15725 memcpy(tp->board_part_number, &vpd_data[i], len);
15729 if (tp->board_part_number[0])
15733 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15734 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15735 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15736 strcpy(tp->board_part_number, "BCM5717");
15737 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15738 strcpy(tp->board_part_number, "BCM5718");
15741 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15742 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15743 strcpy(tp->board_part_number, "BCM57780");
15744 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15745 strcpy(tp->board_part_number, "BCM57760");
15746 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15747 strcpy(tp->board_part_number, "BCM57790");
15748 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15749 strcpy(tp->board_part_number, "BCM57788");
15752 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15753 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15754 strcpy(tp->board_part_number, "BCM57761");
15755 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15756 strcpy(tp->board_part_number, "BCM57765");
15757 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15758 strcpy(tp->board_part_number, "BCM57781");
15759 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15760 strcpy(tp->board_part_number, "BCM57785");
15761 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15762 strcpy(tp->board_part_number, "BCM57791");
15763 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15764 strcpy(tp->board_part_number, "BCM57795");
15767 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15768 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15769 strcpy(tp->board_part_number, "BCM57762");
15770 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15771 strcpy(tp->board_part_number, "BCM57766");
15772 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15773 strcpy(tp->board_part_number, "BCM57782");
15774 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15775 strcpy(tp->board_part_number, "BCM57786");
15778 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15779 strcpy(tp->board_part_number, "BCM95906");
15782 strcpy(tp->board_part_number, "none");
15786 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15790 if (tg3_nvram_read(tp, offset, &val) ||
15791 (val & 0xfc000000) != 0x0c000000 ||
15792 tg3_nvram_read(tp, offset + 4, &val) ||
15799 static void tg3_read_bc_ver(struct tg3 *tp)
15801 u32 val, offset, start, ver_offset;
15803 bool newver = false;
15805 if (tg3_nvram_read(tp, 0xc, &offset) ||
15806 tg3_nvram_read(tp, 0x4, &start))
15809 offset = tg3_nvram_logical_addr(tp, offset);
15811 if (tg3_nvram_read(tp, offset, &val))
15814 if ((val & 0xfc000000) == 0x0c000000) {
15815 if (tg3_nvram_read(tp, offset + 4, &val))
15822 dst_off = strlen(tp->fw_ver);
15825 if (TG3_VER_SIZE - dst_off < 16 ||
15826 tg3_nvram_read(tp, offset + 8, &ver_offset))
15829 offset = offset + ver_offset - start;
15830 for (i = 0; i < 16; i += 4) {
15832 if (tg3_nvram_read_be32(tp, offset + i, &v))
15835 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15840 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15843 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15844 TG3_NVM_BCVER_MAJSFT;
15845 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15846 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15847 "v%d.%02d", major, minor);
15851 static void tg3_read_hwsb_ver(struct tg3 *tp)
15853 u32 val, major, minor;
15855 /* Use native endian representation */
15856 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15859 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15860 TG3_NVM_HWSB_CFG1_MAJSFT;
15861 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15862 TG3_NVM_HWSB_CFG1_MINSFT;
15864 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15867 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15869 u32 offset, major, minor, build;
15871 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15873 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15876 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15877 case TG3_EEPROM_SB_REVISION_0:
15878 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15880 case TG3_EEPROM_SB_REVISION_2:
15881 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15883 case TG3_EEPROM_SB_REVISION_3:
15884 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15886 case TG3_EEPROM_SB_REVISION_4:
15887 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15889 case TG3_EEPROM_SB_REVISION_5:
15890 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15892 case TG3_EEPROM_SB_REVISION_6:
15893 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15899 if (tg3_nvram_read(tp, offset, &val))
15902 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15903 TG3_EEPROM_SB_EDH_BLD_SHFT;
15904 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15905 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15906 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15908 if (minor > 99 || build > 26)
15911 offset = strlen(tp->fw_ver);
15912 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15913 " v%d.%02d", major, minor);
15916 offset = strlen(tp->fw_ver);
15917 if (offset < TG3_VER_SIZE - 1)
15918 tp->fw_ver[offset] = 'a' + build - 1;
15922 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15924 u32 val, offset, start;
15927 for (offset = TG3_NVM_DIR_START;
15928 offset < TG3_NVM_DIR_END;
15929 offset += TG3_NVM_DIRENT_SIZE) {
15930 if (tg3_nvram_read(tp, offset, &val))
15933 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15937 if (offset == TG3_NVM_DIR_END)
15940 if (!tg3_flag(tp, 5705_PLUS))
15941 start = 0x08000000;
15942 else if (tg3_nvram_read(tp, offset - 4, &start))
15945 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15946 !tg3_fw_img_is_valid(tp, offset) ||
15947 tg3_nvram_read(tp, offset + 8, &val))
15950 offset += val - start;
15952 vlen = strlen(tp->fw_ver);
15954 tp->fw_ver[vlen++] = ',';
15955 tp->fw_ver[vlen++] = ' ';
15957 for (i = 0; i < 4; i++) {
15959 if (tg3_nvram_read_be32(tp, offset, &v))
15962 offset += sizeof(v);
15964 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15965 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15969 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15974 static void tg3_probe_ncsi(struct tg3 *tp)
15978 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15979 if (apedata != APE_SEG_SIG_MAGIC)
15982 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15983 if (!(apedata & APE_FW_STATUS_READY))
15986 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15987 tg3_flag_set(tp, APE_HAS_NCSI);
15990 static void tg3_read_dash_ver(struct tg3 *tp)
15996 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15998 if (tg3_flag(tp, APE_HAS_NCSI))
16000 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
16005 vlen = strlen(tp->fw_ver);
16007 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
16009 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
16010 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
16011 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
16012 (apedata & APE_FW_VERSION_BLDMSK));
16015 static void tg3_read_otp_ver(struct tg3 *tp)
16019 if (tg3_asic_rev(tp) != ASIC_REV_5762)
16022 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
16023 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
16024 TG3_OTP_MAGIC0_VALID(val)) {
16025 u64 val64 = (u64) val << 32 | val2;
16029 for (i = 0; i < 7; i++) {
16030 if ((val64 & 0xff) == 0)
16032 ver = val64 & 0xff;
16035 vlen = strlen(tp->fw_ver);
16036 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
16040 static void tg3_read_fw_ver(struct tg3 *tp)
16043 bool vpd_vers = false;
16045 if (tp->fw_ver[0] != 0)
16048 if (tg3_flag(tp, NO_NVRAM)) {
16049 strcat(tp->fw_ver, "sb");
16050 tg3_read_otp_ver(tp);
16054 if (tg3_nvram_read(tp, 0, &val))
16057 if (val == TG3_EEPROM_MAGIC)
16058 tg3_read_bc_ver(tp);
16059 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
16060 tg3_read_sb_ver(tp, val);
16061 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
16062 tg3_read_hwsb_ver(tp);
16064 if (tg3_flag(tp, ENABLE_ASF)) {
16065 if (tg3_flag(tp, ENABLE_APE)) {
16066 tg3_probe_ncsi(tp);
16068 tg3_read_dash_ver(tp);
16069 } else if (!vpd_vers) {
16070 tg3_read_mgmtfw_ver(tp);
16074 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
16077 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
16079 if (tg3_flag(tp, LRG_PROD_RING_CAP))
16080 return TG3_RX_RET_MAX_SIZE_5717;
16081 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
16082 return TG3_RX_RET_MAX_SIZE_5700;
16084 return TG3_RX_RET_MAX_SIZE_5705;
16087 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
16088 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
16089 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
16090 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
16094 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16096 struct pci_dev *peer;
16097 unsigned int func, devnr = tp->pdev->devfn & ~7;
16099 for (func = 0; func < 8; func++) {
16100 peer = pci_get_slot(tp->pdev->bus, devnr | func);
16101 if (peer && peer != tp->pdev)
16105 /* 5704 can be configured in single-port mode, set peer to
16106 * tp->pdev in that case.
16114 * We don't need to keep the refcount elevated; there's no way
16115 * to remove one half of this device without removing the other
16122 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16124 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16125 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16128 /* All devices that use the alternate
16129 * ASIC REV location have a CPMU.
16131 tg3_flag_set(tp, CPMU_PRESENT);
16133 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16134 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16135 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16136 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16137 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16138 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16139 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16140 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16141 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16142 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16143 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16144 reg = TG3PCI_GEN2_PRODID_ASICREV;
16145 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16146 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16147 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16148 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16149 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16150 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16151 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16152 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16153 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16154 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16155 reg = TG3PCI_GEN15_PRODID_ASICREV;
16157 reg = TG3PCI_PRODID_ASICREV;
16159 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16162 /* Wrong chip ID in 5752 A0. This code can be removed later
16163 * as A0 is not in production.
16165 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16166 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16168 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16169 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16171 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16172 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16173 tg3_asic_rev(tp) == ASIC_REV_5720)
16174 tg3_flag_set(tp, 5717_PLUS);
16176 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16177 tg3_asic_rev(tp) == ASIC_REV_57766)
16178 tg3_flag_set(tp, 57765_CLASS);
16180 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16181 tg3_asic_rev(tp) == ASIC_REV_5762)
16182 tg3_flag_set(tp, 57765_PLUS);
16184 /* Intentionally exclude ASIC_REV_5906 */
16185 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16186 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16187 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16188 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16189 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16190 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16191 tg3_flag(tp, 57765_PLUS))
16192 tg3_flag_set(tp, 5755_PLUS);
16194 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16195 tg3_asic_rev(tp) == ASIC_REV_5714)
16196 tg3_flag_set(tp, 5780_CLASS);
16198 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16199 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16200 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16201 tg3_flag(tp, 5755_PLUS) ||
16202 tg3_flag(tp, 5780_CLASS))
16203 tg3_flag_set(tp, 5750_PLUS);
16205 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16206 tg3_flag(tp, 5750_PLUS))
16207 tg3_flag_set(tp, 5705_PLUS);
16210 static bool tg3_10_100_only_device(struct tg3 *tp,
16211 const struct pci_device_id *ent)
16213 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16215 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16216 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16217 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16220 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16221 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16222 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16232 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16235 u32 pci_state_reg, grc_misc_cfg;
16240 /* Force memory write invalidate off. If we leave it on,
16241 * then on 5700_BX chips we have to enable a workaround.
16242 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16243 * to match the cacheline size. The Broadcom driver have this
16244 * workaround but turns MWI off all the times so never uses
16245 * it. This seems to suggest that the workaround is insufficient.
16247 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16248 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16249 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16251 /* Important! -- Make sure register accesses are byteswapped
16252 * correctly. Also, for those chips that require it, make
16253 * sure that indirect register accesses are enabled before
16254 * the first operation.
16256 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16258 tp->misc_host_ctrl |= (misc_ctrl_reg &
16259 MISC_HOST_CTRL_CHIPREV);
16260 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16261 tp->misc_host_ctrl);
16263 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16265 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16266 * we need to disable memory and use config. cycles
16267 * only to access all registers. The 5702/03 chips
16268 * can mistakenly decode the special cycles from the
16269 * ICH chipsets as memory write cycles, causing corruption
16270 * of register and memory space. Only certain ICH bridges
16271 * will drive special cycles with non-zero data during the
16272 * address phase which can fall within the 5703's address
16273 * range. This is not an ICH bug as the PCI spec allows
16274 * non-zero address during special cycles. However, only
16275 * these ICH bridges are known to drive non-zero addresses
16276 * during special cycles.
16278 * Since special cycles do not cross PCI bridges, we only
16279 * enable this workaround if the 5703 is on the secondary
16280 * bus of these ICH bridges.
16282 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16283 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16284 static struct tg3_dev_id {
16288 } ich_chipsets[] = {
16289 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16291 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16293 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16295 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16299 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16300 struct pci_dev *bridge = NULL;
16302 while (pci_id->vendor != 0) {
16303 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16309 if (pci_id->rev != PCI_ANY_ID) {
16310 if (bridge->revision > pci_id->rev)
16313 if (bridge->subordinate &&
16314 (bridge->subordinate->number ==
16315 tp->pdev->bus->number)) {
16316 tg3_flag_set(tp, ICH_WORKAROUND);
16317 pci_dev_put(bridge);
16323 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16324 static struct tg3_dev_id {
16327 } bridge_chipsets[] = {
16328 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16329 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16332 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16333 struct pci_dev *bridge = NULL;
16335 while (pci_id->vendor != 0) {
16336 bridge = pci_get_device(pci_id->vendor,
16343 if (bridge->subordinate &&
16344 (bridge->subordinate->number <=
16345 tp->pdev->bus->number) &&
16346 (bridge->subordinate->busn_res.end >=
16347 tp->pdev->bus->number)) {
16348 tg3_flag_set(tp, 5701_DMA_BUG);
16349 pci_dev_put(bridge);
16355 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16356 * DMA addresses > 40-bit. This bridge may have other additional
16357 * 57xx devices behind it in some 4-port NIC designs for example.
16358 * Any tg3 device found behind the bridge will also need the 40-bit
16361 if (tg3_flag(tp, 5780_CLASS)) {
16362 tg3_flag_set(tp, 40BIT_DMA_BUG);
16363 tp->msi_cap = tp->pdev->msi_cap;
16365 struct pci_dev *bridge = NULL;
16368 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16369 PCI_DEVICE_ID_SERVERWORKS_EPB,
16371 if (bridge && bridge->subordinate &&
16372 (bridge->subordinate->number <=
16373 tp->pdev->bus->number) &&
16374 (bridge->subordinate->busn_res.end >=
16375 tp->pdev->bus->number)) {
16376 tg3_flag_set(tp, 40BIT_DMA_BUG);
16377 pci_dev_put(bridge);
16383 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16384 tg3_asic_rev(tp) == ASIC_REV_5714)
16385 tp->pdev_peer = tg3_find_peer(tp);
16387 /* Determine TSO capabilities */
16388 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16389 ; /* Do nothing. HW bug. */
16390 else if (tg3_flag(tp, 57765_PLUS))
16391 tg3_flag_set(tp, HW_TSO_3);
16392 else if (tg3_flag(tp, 5755_PLUS) ||
16393 tg3_asic_rev(tp) == ASIC_REV_5906)
16394 tg3_flag_set(tp, HW_TSO_2);
16395 else if (tg3_flag(tp, 5750_PLUS)) {
16396 tg3_flag_set(tp, HW_TSO_1);
16397 tg3_flag_set(tp, TSO_BUG);
16398 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16399 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16400 tg3_flag_clear(tp, TSO_BUG);
16401 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16402 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16403 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16404 tg3_flag_set(tp, FW_TSO);
16405 tg3_flag_set(tp, TSO_BUG);
16406 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16407 tp->fw_needed = FIRMWARE_TG3TSO5;
16409 tp->fw_needed = FIRMWARE_TG3TSO;
16412 /* Selectively allow TSO based on operating conditions */
16413 if (tg3_flag(tp, HW_TSO_1) ||
16414 tg3_flag(tp, HW_TSO_2) ||
16415 tg3_flag(tp, HW_TSO_3) ||
16416 tg3_flag(tp, FW_TSO)) {
16417 /* For firmware TSO, assume ASF is disabled.
16418 * We'll disable TSO later if we discover ASF
16419 * is enabled in tg3_get_eeprom_hw_cfg().
16421 tg3_flag_set(tp, TSO_CAPABLE);
16423 tg3_flag_clear(tp, TSO_CAPABLE);
16424 tg3_flag_clear(tp, TSO_BUG);
16425 tp->fw_needed = NULL;
16428 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16429 tp->fw_needed = FIRMWARE_TG3;
16431 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16432 tp->fw_needed = FIRMWARE_TG357766;
16436 if (tg3_flag(tp, 5750_PLUS)) {
16437 tg3_flag_set(tp, SUPPORT_MSI);
16438 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16439 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16440 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16441 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16442 tp->pdev_peer == tp->pdev))
16443 tg3_flag_clear(tp, SUPPORT_MSI);
16445 if (tg3_flag(tp, 5755_PLUS) ||
16446 tg3_asic_rev(tp) == ASIC_REV_5906) {
16447 tg3_flag_set(tp, 1SHOT_MSI);
16450 if (tg3_flag(tp, 57765_PLUS)) {
16451 tg3_flag_set(tp, SUPPORT_MSIX);
16452 tp->irq_max = TG3_IRQ_MAX_VECS;
16458 if (tp->irq_max > 1) {
16459 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16460 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16462 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16463 tg3_asic_rev(tp) == ASIC_REV_5720)
16464 tp->txq_max = tp->irq_max - 1;
16467 if (tg3_flag(tp, 5755_PLUS) ||
16468 tg3_asic_rev(tp) == ASIC_REV_5906)
16469 tg3_flag_set(tp, SHORT_DMA_BUG);
16471 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16472 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16474 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16475 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16476 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16477 tg3_asic_rev(tp) == ASIC_REV_5762)
16478 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16480 if (tg3_flag(tp, 57765_PLUS) &&
16481 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16482 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16484 if (!tg3_flag(tp, 5705_PLUS) ||
16485 tg3_flag(tp, 5780_CLASS) ||
16486 tg3_flag(tp, USE_JUMBO_BDFLAG))
16487 tg3_flag_set(tp, JUMBO_CAPABLE);
16489 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16492 if (pci_is_pcie(tp->pdev)) {
16495 tg3_flag_set(tp, PCI_EXPRESS);
16497 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16498 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16499 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16500 tg3_flag_clear(tp, HW_TSO_2);
16501 tg3_flag_clear(tp, TSO_CAPABLE);
16503 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16504 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16505 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16506 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16507 tg3_flag_set(tp, CLKREQ_BUG);
16508 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16509 tg3_flag_set(tp, L1PLLPD_EN);
16511 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16512 /* BCM5785 devices are effectively PCIe devices, and should
16513 * follow PCIe codepaths, but do not have a PCIe capabilities
16516 tg3_flag_set(tp, PCI_EXPRESS);
16517 } else if (!tg3_flag(tp, 5705_PLUS) ||
16518 tg3_flag(tp, 5780_CLASS)) {
16519 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16520 if (!tp->pcix_cap) {
16521 dev_err(&tp->pdev->dev,
16522 "Cannot find PCI-X capability, aborting\n");
16526 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16527 tg3_flag_set(tp, PCIX_MODE);
16530 /* If we have an AMD 762 or VIA K8T800 chipset, write
16531 * reordering to the mailbox registers done by the host
16532 * controller can cause major troubles. We read back from
16533 * every mailbox register write to force the writes to be
16534 * posted to the chip in order.
16536 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16537 !tg3_flag(tp, PCI_EXPRESS))
16538 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16540 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16541 &tp->pci_cacheline_sz);
16542 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16543 &tp->pci_lat_timer);
16544 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16545 tp->pci_lat_timer < 64) {
16546 tp->pci_lat_timer = 64;
16547 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16548 tp->pci_lat_timer);
16551 /* Important! -- It is critical that the PCI-X hw workaround
16552 * situation is decided before the first MMIO register access.
16554 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16555 /* 5700 BX chips need to have their TX producer index
16556 * mailboxes written twice to workaround a bug.
16558 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16560 /* If we are in PCI-X mode, enable register write workaround.
16562 * The workaround is to use indirect register accesses
16563 * for all chip writes not to mailbox registers.
16565 if (tg3_flag(tp, PCIX_MODE)) {
16568 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16570 /* The chip can have it's power management PCI config
16571 * space registers clobbered due to this bug.
16572 * So explicitly force the chip into D0 here.
16574 pci_read_config_dword(tp->pdev,
16575 tp->pdev->pm_cap + PCI_PM_CTRL,
16577 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16578 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16579 pci_write_config_dword(tp->pdev,
16580 tp->pdev->pm_cap + PCI_PM_CTRL,
16583 /* Also, force SERR#/PERR# in PCI command. */
16584 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16585 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16586 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16590 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16591 tg3_flag_set(tp, PCI_HIGH_SPEED);
16592 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16593 tg3_flag_set(tp, PCI_32BIT);
16595 /* Chip-specific fixup from Broadcom driver */
16596 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16597 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16598 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16599 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16602 /* Default fast path register access methods */
16603 tp->read32 = tg3_read32;
16604 tp->write32 = tg3_write32;
16605 tp->read32_mbox = tg3_read32;
16606 tp->write32_mbox = tg3_write32;
16607 tp->write32_tx_mbox = tg3_write32;
16608 tp->write32_rx_mbox = tg3_write32;
16610 /* Various workaround register access methods */
16611 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16612 tp->write32 = tg3_write_indirect_reg32;
16613 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16614 (tg3_flag(tp, PCI_EXPRESS) &&
16615 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16617 * Back to back register writes can cause problems on these
16618 * chips, the workaround is to read back all reg writes
16619 * except those to mailbox regs.
16621 * See tg3_write_indirect_reg32().
16623 tp->write32 = tg3_write_flush_reg32;
16626 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16627 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16628 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16629 tp->write32_rx_mbox = tg3_write_flush_reg32;
16632 if (tg3_flag(tp, ICH_WORKAROUND)) {
16633 tp->read32 = tg3_read_indirect_reg32;
16634 tp->write32 = tg3_write_indirect_reg32;
16635 tp->read32_mbox = tg3_read_indirect_mbox;
16636 tp->write32_mbox = tg3_write_indirect_mbox;
16637 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16638 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16643 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16644 pci_cmd &= ~PCI_COMMAND_MEMORY;
16645 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16647 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16648 tp->read32_mbox = tg3_read32_mbox_5906;
16649 tp->write32_mbox = tg3_write32_mbox_5906;
16650 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16651 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16654 if (tp->write32 == tg3_write_indirect_reg32 ||
16655 (tg3_flag(tp, PCIX_MODE) &&
16656 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16657 tg3_asic_rev(tp) == ASIC_REV_5701)))
16658 tg3_flag_set(tp, SRAM_USE_CONFIG);
16660 /* The memory arbiter has to be enabled in order for SRAM accesses
16661 * to succeed. Normally on powerup the tg3 chip firmware will make
16662 * sure it is enabled, but other entities such as system netboot
16663 * code might disable it.
16665 val = tr32(MEMARB_MODE);
16666 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16668 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16669 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16670 tg3_flag(tp, 5780_CLASS)) {
16671 if (tg3_flag(tp, PCIX_MODE)) {
16672 pci_read_config_dword(tp->pdev,
16673 tp->pcix_cap + PCI_X_STATUS,
16675 tp->pci_fn = val & 0x7;
16677 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16678 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16679 tg3_asic_rev(tp) == ASIC_REV_5720) {
16680 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16681 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16682 val = tr32(TG3_CPMU_STATUS);
16684 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16685 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16687 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16688 TG3_CPMU_STATUS_FSHFT_5719;
16691 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16692 tp->write32_tx_mbox = tg3_write_flush_reg32;
16693 tp->write32_rx_mbox = tg3_write_flush_reg32;
16696 /* Get eeprom hw config before calling tg3_set_power_state().
16697 * In particular, the TG3_FLAG_IS_NIC flag must be
16698 * determined before calling tg3_set_power_state() so that
16699 * we know whether or not to switch out of Vaux power.
16700 * When the flag is set, it means that GPIO1 is used for eeprom
16701 * write protect and also implies that it is a LOM where GPIOs
16702 * are not used to switch power.
16704 tg3_get_eeprom_hw_cfg(tp);
16706 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16707 tg3_flag_clear(tp, TSO_CAPABLE);
16708 tg3_flag_clear(tp, TSO_BUG);
16709 tp->fw_needed = NULL;
16712 if (tg3_flag(tp, ENABLE_APE)) {
16713 /* Allow reads and writes to the
16714 * APE register and memory space.
16716 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16717 PCISTATE_ALLOW_APE_SHMEM_WR |
16718 PCISTATE_ALLOW_APE_PSPACE_WR;
16719 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16722 tg3_ape_lock_init(tp);
16723 tp->ape_hb_interval =
16724 msecs_to_jiffies(APE_HOST_HEARTBEAT_INT_5SEC);
16727 /* Set up tp->grc_local_ctrl before calling
16728 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16729 * will bring 5700's external PHY out of reset.
16730 * It is also used as eeprom write protect on LOMs.
16732 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16733 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16734 tg3_flag(tp, EEPROM_WRITE_PROT))
16735 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16736 GRC_LCLCTRL_GPIO_OUTPUT1);
16737 /* Unused GPIO3 must be driven as output on 5752 because there
16738 * are no pull-up resistors on unused GPIO pins.
16740 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16741 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16743 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16744 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16745 tg3_flag(tp, 57765_CLASS))
16746 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16748 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16749 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16750 /* Turn off the debug UART. */
16751 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16752 if (tg3_flag(tp, IS_NIC))
16753 /* Keep VMain power. */
16754 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16755 GRC_LCLCTRL_GPIO_OUTPUT0;
16758 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16759 tp->grc_local_ctrl |=
16760 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16762 /* Switch out of Vaux if it is a NIC */
16763 tg3_pwrsrc_switch_to_vmain(tp);
16765 /* Derive initial jumbo mode from MTU assigned in
16766 * ether_setup() via the alloc_etherdev() call
16768 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16769 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16771 /* Determine WakeOnLan speed to use. */
16772 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16773 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16774 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16775 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16776 tg3_flag_clear(tp, WOL_SPEED_100MB);
16778 tg3_flag_set(tp, WOL_SPEED_100MB);
16781 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16782 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16784 /* A few boards don't want Ethernet@WireSpeed phy feature */
16785 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16786 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16787 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16788 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16789 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16790 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16791 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16793 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16794 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16795 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16796 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16797 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16799 if (tg3_flag(tp, 5705_PLUS) &&
16800 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16801 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16802 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16803 !tg3_flag(tp, 57765_PLUS)) {
16804 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16805 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16806 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16807 tg3_asic_rev(tp) == ASIC_REV_5761) {
16808 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16809 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16810 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16811 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16812 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16814 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16817 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16818 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16819 tp->phy_otp = tg3_read_otp_phycfg(tp);
16820 if (tp->phy_otp == 0)
16821 tp->phy_otp = TG3_OTP_DEFAULT;
16824 if (tg3_flag(tp, CPMU_PRESENT))
16825 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16827 tp->mi_mode = MAC_MI_MODE_BASE;
16829 tp->coalesce_mode = 0;
16830 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16831 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16832 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16834 /* Set these bits to enable statistics workaround. */
16835 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16836 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16837 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16838 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16839 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16840 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16843 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16844 tg3_asic_rev(tp) == ASIC_REV_57780)
16845 tg3_flag_set(tp, USE_PHYLIB);
16847 err = tg3_mdio_init(tp);
16851 /* Initialize data/descriptor byte/word swapping. */
16852 val = tr32(GRC_MODE);
16853 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16854 tg3_asic_rev(tp) == ASIC_REV_5762)
16855 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16856 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16857 GRC_MODE_B2HRX_ENABLE |
16858 GRC_MODE_HTX2B_ENABLE |
16859 GRC_MODE_HOST_STACKUP);
16861 val &= GRC_MODE_HOST_STACKUP;
16863 tw32(GRC_MODE, val | tp->grc_mode);
16865 tg3_switch_clocks(tp);
16867 /* Clear this out for sanity. */
16868 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16870 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16871 tw32(TG3PCI_REG_BASE_ADDR, 0);
16873 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16875 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16876 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16877 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16878 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16879 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16880 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16881 void __iomem *sram_base;
16883 /* Write some dummy words into the SRAM status block
16884 * area, see if it reads back correctly. If the return
16885 * value is bad, force enable the PCIX workaround.
16887 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16889 writel(0x00000000, sram_base);
16890 writel(0x00000000, sram_base + 4);
16891 writel(0xffffffff, sram_base + 4);
16892 if (readl(sram_base) != 0x00000000)
16893 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16898 tg3_nvram_init(tp);
16900 /* If the device has an NVRAM, no need to load patch firmware */
16901 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16902 !tg3_flag(tp, NO_NVRAM))
16903 tp->fw_needed = NULL;
16905 grc_misc_cfg = tr32(GRC_MISC_CFG);
16906 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16908 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16909 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16910 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16911 tg3_flag_set(tp, IS_5788);
16913 if (!tg3_flag(tp, IS_5788) &&
16914 tg3_asic_rev(tp) != ASIC_REV_5700)
16915 tg3_flag_set(tp, TAGGED_STATUS);
16916 if (tg3_flag(tp, TAGGED_STATUS)) {
16917 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16918 HOSTCC_MODE_CLRTICK_TXBD);
16920 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16921 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16922 tp->misc_host_ctrl);
16925 /* Preserve the APE MAC_MODE bits */
16926 if (tg3_flag(tp, ENABLE_APE))
16927 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16931 if (tg3_10_100_only_device(tp, ent))
16932 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16934 err = tg3_phy_probe(tp);
16936 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16937 /* ... but do not return immediately ... */
16942 tg3_read_fw_ver(tp);
16944 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16945 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16947 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16948 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16950 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16953 /* 5700 {AX,BX} chips have a broken status block link
16954 * change bit implementation, so we must use the
16955 * status register in those cases.
16957 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16958 tg3_flag_set(tp, USE_LINKCHG_REG);
16960 tg3_flag_clear(tp, USE_LINKCHG_REG);
16962 /* The led_ctrl is set during tg3_phy_probe, here we might
16963 * have to force the link status polling mechanism based
16964 * upon subsystem IDs.
16966 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16967 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16968 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16969 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16970 tg3_flag_set(tp, USE_LINKCHG_REG);
16973 /* For all SERDES we poll the MAC status register. */
16974 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16975 tg3_flag_set(tp, POLL_SERDES);
16977 tg3_flag_clear(tp, POLL_SERDES);
16979 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16980 tg3_flag_set(tp, POLL_CPMU_LINK);
16982 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16983 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16984 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16985 tg3_flag(tp, PCIX_MODE)) {
16986 tp->rx_offset = NET_SKB_PAD;
16987 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16988 tp->rx_copy_thresh = ~(u16)0;
16992 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16993 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16994 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16996 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16998 /* Increment the rx prod index on the rx std ring by at most
16999 * 8 for these chips to workaround hw errata.
17001 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
17002 tg3_asic_rev(tp) == ASIC_REV_5752 ||
17003 tg3_asic_rev(tp) == ASIC_REV_5755)
17004 tp->rx_std_max_post = 8;
17006 if (tg3_flag(tp, ASPM_WORKAROUND))
17007 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
17008 PCIE_PWR_MGMT_L1_THRESH_MSK;
17013 static int tg3_get_device_address(struct tg3 *tp)
17015 struct net_device *dev = tp->dev;
17016 u32 hi, lo, mac_offset;
17020 if (!eth_platform_get_mac_address(&tp->pdev->dev, dev->dev_addr))
17023 if (tg3_flag(tp, IS_SSB_CORE)) {
17024 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
17025 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
17030 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
17031 tg3_flag(tp, 5780_CLASS)) {
17032 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
17034 if (tg3_nvram_lock(tp))
17035 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
17037 tg3_nvram_unlock(tp);
17038 } else if (tg3_flag(tp, 5717_PLUS)) {
17039 if (tp->pci_fn & 1)
17041 if (tp->pci_fn > 1)
17042 mac_offset += 0x18c;
17043 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
17046 /* First try to get it from MAC address mailbox. */
17047 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
17048 if ((hi >> 16) == 0x484b) {
17049 dev->dev_addr[0] = (hi >> 8) & 0xff;
17050 dev->dev_addr[1] = (hi >> 0) & 0xff;
17052 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
17053 dev->dev_addr[2] = (lo >> 24) & 0xff;
17054 dev->dev_addr[3] = (lo >> 16) & 0xff;
17055 dev->dev_addr[4] = (lo >> 8) & 0xff;
17056 dev->dev_addr[5] = (lo >> 0) & 0xff;
17058 /* Some old bootcode may report a 0 MAC address in SRAM */
17059 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
17062 /* Next, try NVRAM. */
17063 if (!tg3_flag(tp, NO_NVRAM) &&
17064 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
17065 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
17066 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
17067 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
17069 /* Finally just fetch it out of the MAC control regs. */
17071 hi = tr32(MAC_ADDR_0_HIGH);
17072 lo = tr32(MAC_ADDR_0_LOW);
17074 dev->dev_addr[5] = lo & 0xff;
17075 dev->dev_addr[4] = (lo >> 8) & 0xff;
17076 dev->dev_addr[3] = (lo >> 16) & 0xff;
17077 dev->dev_addr[2] = (lo >> 24) & 0xff;
17078 dev->dev_addr[1] = hi & 0xff;
17079 dev->dev_addr[0] = (hi >> 8) & 0xff;
17083 if (!is_valid_ether_addr(&dev->dev_addr[0]))
17088 #define BOUNDARY_SINGLE_CACHELINE 1
17089 #define BOUNDARY_MULTI_CACHELINE 2
17091 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17093 int cacheline_size;
17097 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17099 cacheline_size = 1024;
17101 cacheline_size = (int) byte * 4;
17103 /* On 5703 and later chips, the boundary bits have no
17106 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17107 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17108 !tg3_flag(tp, PCI_EXPRESS))
17111 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17112 goal = BOUNDARY_MULTI_CACHELINE;
17114 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17115 goal = BOUNDARY_SINGLE_CACHELINE;
17121 if (tg3_flag(tp, 57765_PLUS)) {
17122 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17129 /* PCI controllers on most RISC systems tend to disconnect
17130 * when a device tries to burst across a cache-line boundary.
17131 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17133 * Unfortunately, for PCI-E there are only limited
17134 * write-side controls for this, and thus for reads
17135 * we will still get the disconnects. We'll also waste
17136 * these PCI cycles for both read and write for chips
17137 * other than 5700 and 5701 which do not implement the
17140 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17141 switch (cacheline_size) {
17146 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17147 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17148 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17150 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17151 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17156 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17157 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17161 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17162 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17165 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17166 switch (cacheline_size) {
17170 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17171 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17172 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17178 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17179 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17183 switch (cacheline_size) {
17185 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17186 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17187 DMA_RWCTRL_WRITE_BNDRY_16);
17192 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17193 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17194 DMA_RWCTRL_WRITE_BNDRY_32);
17199 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17200 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17201 DMA_RWCTRL_WRITE_BNDRY_64);
17206 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17207 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17208 DMA_RWCTRL_WRITE_BNDRY_128);
17213 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17214 DMA_RWCTRL_WRITE_BNDRY_256);
17217 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17218 DMA_RWCTRL_WRITE_BNDRY_512);
17222 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17223 DMA_RWCTRL_WRITE_BNDRY_1024);
17232 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17233 int size, bool to_device)
17235 struct tg3_internal_buffer_desc test_desc;
17236 u32 sram_dma_descs;
17239 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17241 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17242 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17243 tw32(RDMAC_STATUS, 0);
17244 tw32(WDMAC_STATUS, 0);
17246 tw32(BUFMGR_MODE, 0);
17247 tw32(FTQ_RESET, 0);
17249 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17250 test_desc.addr_lo = buf_dma & 0xffffffff;
17251 test_desc.nic_mbuf = 0x00002100;
17252 test_desc.len = size;
17255 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17256 * the *second* time the tg3 driver was getting loaded after an
17259 * Broadcom tells me:
17260 * ...the DMA engine is connected to the GRC block and a DMA
17261 * reset may affect the GRC block in some unpredictable way...
17262 * The behavior of resets to individual blocks has not been tested.
17264 * Broadcom noted the GRC reset will also reset all sub-components.
17267 test_desc.cqid_sqid = (13 << 8) | 2;
17269 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17272 test_desc.cqid_sqid = (16 << 8) | 7;
17274 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17277 test_desc.flags = 0x00000005;
17279 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17282 val = *(((u32 *)&test_desc) + i);
17283 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17284 sram_dma_descs + (i * sizeof(u32)));
17285 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17287 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17290 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17292 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17295 for (i = 0; i < 40; i++) {
17299 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17301 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17302 if ((val & 0xffff) == sram_dma_descs) {
17313 #define TEST_BUFFER_SIZE 0x2000
17315 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17316 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17320 static int tg3_test_dma(struct tg3 *tp)
17322 dma_addr_t buf_dma;
17323 u32 *buf, saved_dma_rwctrl;
17326 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17327 &buf_dma, GFP_KERNEL);
17333 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17334 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17336 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17338 if (tg3_flag(tp, 57765_PLUS))
17341 if (tg3_flag(tp, PCI_EXPRESS)) {
17342 /* DMA read watermark not used on PCIE */
17343 tp->dma_rwctrl |= 0x00180000;
17344 } else if (!tg3_flag(tp, PCIX_MODE)) {
17345 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17346 tg3_asic_rev(tp) == ASIC_REV_5750)
17347 tp->dma_rwctrl |= 0x003f0000;
17349 tp->dma_rwctrl |= 0x003f000f;
17351 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17352 tg3_asic_rev(tp) == ASIC_REV_5704) {
17353 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17354 u32 read_water = 0x7;
17356 /* If the 5704 is behind the EPB bridge, we can
17357 * do the less restrictive ONE_DMA workaround for
17358 * better performance.
17360 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17361 tg3_asic_rev(tp) == ASIC_REV_5704)
17362 tp->dma_rwctrl |= 0x8000;
17363 else if (ccval == 0x6 || ccval == 0x7)
17364 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17366 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17368 /* Set bit 23 to enable PCIX hw bug fix */
17370 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17371 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17373 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17374 /* 5780 always in PCIX mode */
17375 tp->dma_rwctrl |= 0x00144000;
17376 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17377 /* 5714 always in PCIX mode */
17378 tp->dma_rwctrl |= 0x00148000;
17380 tp->dma_rwctrl |= 0x001b000f;
17383 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17384 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17386 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17387 tg3_asic_rev(tp) == ASIC_REV_5704)
17388 tp->dma_rwctrl &= 0xfffffff0;
17390 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17391 tg3_asic_rev(tp) == ASIC_REV_5701) {
17392 /* Remove this if it causes problems for some boards. */
17393 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17395 /* On 5700/5701 chips, we need to set this bit.
17396 * Otherwise the chip will issue cacheline transactions
17397 * to streamable DMA memory with not all the byte
17398 * enables turned on. This is an error on several
17399 * RISC PCI controllers, in particular sparc64.
17401 * On 5703/5704 chips, this bit has been reassigned
17402 * a different meaning. In particular, it is used
17403 * on those chips to enable a PCI-X workaround.
17405 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17408 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17411 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17412 tg3_asic_rev(tp) != ASIC_REV_5701)
17415 /* It is best to perform DMA test with maximum write burst size
17416 * to expose the 5700/5701 write DMA bug.
17418 saved_dma_rwctrl = tp->dma_rwctrl;
17419 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17420 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17425 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17428 /* Send the buffer to the chip. */
17429 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17431 dev_err(&tp->pdev->dev,
17432 "%s: Buffer write failed. err = %d\n",
17437 /* Now read it back. */
17438 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17440 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17441 "err = %d\n", __func__, ret);
17446 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17450 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17451 DMA_RWCTRL_WRITE_BNDRY_16) {
17452 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17453 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17454 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17457 dev_err(&tp->pdev->dev,
17458 "%s: Buffer corrupted on read back! "
17459 "(%d != %d)\n", __func__, p[i], i);
17465 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17471 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17472 DMA_RWCTRL_WRITE_BNDRY_16) {
17473 /* DMA test passed without adjusting DMA boundary,
17474 * now look for chipsets that are known to expose the
17475 * DMA bug without failing the test.
17477 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17478 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17479 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17481 /* Safe to use the calculated DMA boundary. */
17482 tp->dma_rwctrl = saved_dma_rwctrl;
17485 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17489 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17494 static void tg3_init_bufmgr_config(struct tg3 *tp)
17496 if (tg3_flag(tp, 57765_PLUS)) {
17497 tp->bufmgr_config.mbuf_read_dma_low_water =
17498 DEFAULT_MB_RDMA_LOW_WATER_5705;
17499 tp->bufmgr_config.mbuf_mac_rx_low_water =
17500 DEFAULT_MB_MACRX_LOW_WATER_57765;
17501 tp->bufmgr_config.mbuf_high_water =
17502 DEFAULT_MB_HIGH_WATER_57765;
17504 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17505 DEFAULT_MB_RDMA_LOW_WATER_5705;
17506 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17507 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17508 tp->bufmgr_config.mbuf_high_water_jumbo =
17509 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17510 } else if (tg3_flag(tp, 5705_PLUS)) {
17511 tp->bufmgr_config.mbuf_read_dma_low_water =
17512 DEFAULT_MB_RDMA_LOW_WATER_5705;
17513 tp->bufmgr_config.mbuf_mac_rx_low_water =
17514 DEFAULT_MB_MACRX_LOW_WATER_5705;
17515 tp->bufmgr_config.mbuf_high_water =
17516 DEFAULT_MB_HIGH_WATER_5705;
17517 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17518 tp->bufmgr_config.mbuf_mac_rx_low_water =
17519 DEFAULT_MB_MACRX_LOW_WATER_5906;
17520 tp->bufmgr_config.mbuf_high_water =
17521 DEFAULT_MB_HIGH_WATER_5906;
17524 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17525 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17526 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17527 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17528 tp->bufmgr_config.mbuf_high_water_jumbo =
17529 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17531 tp->bufmgr_config.mbuf_read_dma_low_water =
17532 DEFAULT_MB_RDMA_LOW_WATER;
17533 tp->bufmgr_config.mbuf_mac_rx_low_water =
17534 DEFAULT_MB_MACRX_LOW_WATER;
17535 tp->bufmgr_config.mbuf_high_water =
17536 DEFAULT_MB_HIGH_WATER;
17538 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17539 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17540 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17541 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17542 tp->bufmgr_config.mbuf_high_water_jumbo =
17543 DEFAULT_MB_HIGH_WATER_JUMBO;
17546 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17547 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17550 static char *tg3_phy_string(struct tg3 *tp)
17552 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17553 case TG3_PHY_ID_BCM5400: return "5400";
17554 case TG3_PHY_ID_BCM5401: return "5401";
17555 case TG3_PHY_ID_BCM5411: return "5411";
17556 case TG3_PHY_ID_BCM5701: return "5701";
17557 case TG3_PHY_ID_BCM5703: return "5703";
17558 case TG3_PHY_ID_BCM5704: return "5704";
17559 case TG3_PHY_ID_BCM5705: return "5705";
17560 case TG3_PHY_ID_BCM5750: return "5750";
17561 case TG3_PHY_ID_BCM5752: return "5752";
17562 case TG3_PHY_ID_BCM5714: return "5714";
17563 case TG3_PHY_ID_BCM5780: return "5780";
17564 case TG3_PHY_ID_BCM5755: return "5755";
17565 case TG3_PHY_ID_BCM5787: return "5787";
17566 case TG3_PHY_ID_BCM5784: return "5784";
17567 case TG3_PHY_ID_BCM5756: return "5722/5756";
17568 case TG3_PHY_ID_BCM5906: return "5906";
17569 case TG3_PHY_ID_BCM5761: return "5761";
17570 case TG3_PHY_ID_BCM5718C: return "5718C";
17571 case TG3_PHY_ID_BCM5718S: return "5718S";
17572 case TG3_PHY_ID_BCM57765: return "57765";
17573 case TG3_PHY_ID_BCM5719C: return "5719C";
17574 case TG3_PHY_ID_BCM5720C: return "5720C";
17575 case TG3_PHY_ID_BCM5762: return "5762C";
17576 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17577 case 0: return "serdes";
17578 default: return "unknown";
17582 static char *tg3_bus_string(struct tg3 *tp, char *str)
17584 if (tg3_flag(tp, PCI_EXPRESS)) {
17585 strcpy(str, "PCI Express");
17587 } else if (tg3_flag(tp, PCIX_MODE)) {
17588 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17590 strcpy(str, "PCIX:");
17592 if ((clock_ctrl == 7) ||
17593 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17594 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17595 strcat(str, "133MHz");
17596 else if (clock_ctrl == 0)
17597 strcat(str, "33MHz");
17598 else if (clock_ctrl == 2)
17599 strcat(str, "50MHz");
17600 else if (clock_ctrl == 4)
17601 strcat(str, "66MHz");
17602 else if (clock_ctrl == 6)
17603 strcat(str, "100MHz");
17605 strcpy(str, "PCI:");
17606 if (tg3_flag(tp, PCI_HIGH_SPEED))
17607 strcat(str, "66MHz");
17609 strcat(str, "33MHz");
17611 if (tg3_flag(tp, PCI_32BIT))
17612 strcat(str, ":32-bit");
17614 strcat(str, ":64-bit");
17618 static void tg3_init_coal(struct tg3 *tp)
17620 struct ethtool_coalesce *ec = &tp->coal;
17622 memset(ec, 0, sizeof(*ec));
17623 ec->cmd = ETHTOOL_GCOALESCE;
17624 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17625 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17626 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17627 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17628 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17629 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17630 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17631 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17632 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17634 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17635 HOSTCC_MODE_CLRTICK_TXBD)) {
17636 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17637 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17638 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17639 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17642 if (tg3_flag(tp, 5705_PLUS)) {
17643 ec->rx_coalesce_usecs_irq = 0;
17644 ec->tx_coalesce_usecs_irq = 0;
17645 ec->stats_block_coalesce_usecs = 0;
17649 static int tg3_init_one(struct pci_dev *pdev,
17650 const struct pci_device_id *ent)
17652 struct net_device *dev;
17655 u32 sndmbx, rcvmbx, intmbx;
17657 u64 dma_mask, persist_dma_mask;
17658 netdev_features_t features = 0;
17660 err = pci_enable_device(pdev);
17662 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17666 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17668 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17669 goto err_out_disable_pdev;
17672 pci_set_master(pdev);
17674 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17677 goto err_out_free_res;
17680 SET_NETDEV_DEV(dev, &pdev->dev);
17682 tp = netdev_priv(dev);
17685 tp->rx_mode = TG3_DEF_RX_MODE;
17686 tp->tx_mode = TG3_DEF_TX_MODE;
17688 tp->pcierr_recovery = false;
17691 tp->msg_enable = tg3_debug;
17693 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17695 if (pdev_is_ssb_gige_core(pdev)) {
17696 tg3_flag_set(tp, IS_SSB_CORE);
17697 if (ssb_gige_must_flush_posted_writes(pdev))
17698 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17699 if (ssb_gige_one_dma_at_once(pdev))
17700 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17701 if (ssb_gige_have_roboswitch(pdev)) {
17702 tg3_flag_set(tp, USE_PHYLIB);
17703 tg3_flag_set(tp, ROBOSWITCH);
17705 if (ssb_gige_is_rgmii(pdev))
17706 tg3_flag_set(tp, RGMII_MODE);
17709 /* The word/byte swap controls here control register access byte
17710 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17713 tp->misc_host_ctrl =
17714 MISC_HOST_CTRL_MASK_PCI_INT |
17715 MISC_HOST_CTRL_WORD_SWAP |
17716 MISC_HOST_CTRL_INDIR_ACCESS |
17717 MISC_HOST_CTRL_PCISTATE_RW;
17719 /* The NONFRM (non-frame) byte/word swap controls take effect
17720 * on descriptor entries, anything which isn't packet data.
17722 * The StrongARM chips on the board (one for tx, one for rx)
17723 * are running in big-endian mode.
17725 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17726 GRC_MODE_WSWAP_NONFRM_DATA);
17727 #ifdef __BIG_ENDIAN
17728 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17730 spin_lock_init(&tp->lock);
17731 spin_lock_init(&tp->indirect_lock);
17732 INIT_WORK(&tp->reset_task, tg3_reset_task);
17734 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17736 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17738 goto err_out_free_dev;
17741 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17742 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17743 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17744 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17745 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17746 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17747 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17748 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17749 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17750 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17751 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17752 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17753 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17754 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17755 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17756 tg3_flag_set(tp, ENABLE_APE);
17757 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17758 if (!tp->aperegs) {
17759 dev_err(&pdev->dev,
17760 "Cannot map APE registers, aborting\n");
17762 goto err_out_iounmap;
17766 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17767 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17769 dev->ethtool_ops = &tg3_ethtool_ops;
17770 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17771 dev->netdev_ops = &tg3_netdev_ops;
17772 dev->irq = pdev->irq;
17774 err = tg3_get_invariants(tp, ent);
17776 dev_err(&pdev->dev,
17777 "Problem fetching invariants of chip, aborting\n");
17778 goto err_out_apeunmap;
17781 /* The EPB bridge inside 5714, 5715, and 5780 and any
17782 * device behind the EPB cannot support DMA addresses > 40-bit.
17783 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17784 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17785 * do DMA address check in tg3_start_xmit().
17787 if (tg3_flag(tp, IS_5788))
17788 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17789 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17790 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17791 #ifdef CONFIG_HIGHMEM
17792 dma_mask = DMA_BIT_MASK(64);
17795 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17797 /* Configure DMA attributes. */
17798 if (dma_mask > DMA_BIT_MASK(32)) {
17799 err = pci_set_dma_mask(pdev, dma_mask);
17801 features |= NETIF_F_HIGHDMA;
17802 err = pci_set_consistent_dma_mask(pdev,
17805 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17806 "DMA for consistent allocations\n");
17807 goto err_out_apeunmap;
17811 if (err || dma_mask == DMA_BIT_MASK(32)) {
17812 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17814 dev_err(&pdev->dev,
17815 "No usable DMA configuration, aborting\n");
17816 goto err_out_apeunmap;
17820 tg3_init_bufmgr_config(tp);
17822 /* 5700 B0 chips do not support checksumming correctly due
17823 * to hardware bugs.
17825 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17826 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17828 if (tg3_flag(tp, 5755_PLUS))
17829 features |= NETIF_F_IPV6_CSUM;
17832 /* TSO is on by default on chips that support hardware TSO.
17833 * Firmware TSO on older chips gives lower performance, so it
17834 * is off by default, but can be enabled using ethtool.
17836 if ((tg3_flag(tp, HW_TSO_1) ||
17837 tg3_flag(tp, HW_TSO_2) ||
17838 tg3_flag(tp, HW_TSO_3)) &&
17839 (features & NETIF_F_IP_CSUM))
17840 features |= NETIF_F_TSO;
17841 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17842 if (features & NETIF_F_IPV6_CSUM)
17843 features |= NETIF_F_TSO6;
17844 if (tg3_flag(tp, HW_TSO_3) ||
17845 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17846 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17847 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17848 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17849 tg3_asic_rev(tp) == ASIC_REV_57780)
17850 features |= NETIF_F_TSO_ECN;
17853 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17854 NETIF_F_HW_VLAN_CTAG_RX;
17855 dev->vlan_features |= features;
17858 * Add loopback capability only for a subset of devices that support
17859 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17860 * loopback for the remaining devices.
17862 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17863 !tg3_flag(tp, CPMU_PRESENT))
17864 /* Add the loopback capability */
17865 features |= NETIF_F_LOOPBACK;
17867 dev->hw_features |= features;
17868 dev->priv_flags |= IFF_UNICAST_FLT;
17870 /* MTU range: 60 - 9000 or 1500, depending on hardware */
17871 dev->min_mtu = TG3_MIN_MTU;
17872 dev->max_mtu = TG3_MAX_MTU(tp);
17874 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17875 !tg3_flag(tp, TSO_CAPABLE) &&
17876 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17877 tg3_flag_set(tp, MAX_RXPEND_64);
17878 tp->rx_pending = 63;
17881 err = tg3_get_device_address(tp);
17883 dev_err(&pdev->dev,
17884 "Could not obtain valid ethernet address, aborting\n");
17885 goto err_out_apeunmap;
17888 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17889 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17890 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17891 for (i = 0; i < tp->irq_max; i++) {
17892 struct tg3_napi *tnapi = &tp->napi[i];
17895 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17897 tnapi->int_mbox = intmbx;
17903 tnapi->consmbox = rcvmbx;
17904 tnapi->prodmbox = sndmbx;
17907 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17909 tnapi->coal_now = HOSTCC_MODE_NOW;
17911 if (!tg3_flag(tp, SUPPORT_MSIX))
17915 * If we support MSIX, we'll be using RSS. If we're using
17916 * RSS, the first vector only handles link interrupts and the
17917 * remaining vectors handle rx and tx interrupts. Reuse the
17918 * mailbox values for the next iteration. The values we setup
17919 * above are still useful for the single vectored mode.
17933 * Reset chip in case UNDI or EFI driver did not shutdown
17934 * DMA self test will enable WDMAC and we'll see (spurious)
17935 * pending DMA on the PCI bus at that point.
17937 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17938 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17939 tg3_full_lock(tp, 0);
17940 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17941 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17942 tg3_full_unlock(tp);
17945 err = tg3_test_dma(tp);
17947 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17948 goto err_out_apeunmap;
17953 pci_set_drvdata(pdev, dev);
17955 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17956 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17957 tg3_asic_rev(tp) == ASIC_REV_5762)
17958 tg3_flag_set(tp, PTP_CAPABLE);
17960 tg3_timer_init(tp);
17962 tg3_carrier_off(tp);
17964 err = register_netdev(dev);
17966 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17967 goto err_out_apeunmap;
17970 if (tg3_flag(tp, PTP_CAPABLE)) {
17972 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17974 if (IS_ERR(tp->ptp_clock))
17975 tp->ptp_clock = NULL;
17978 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17979 tp->board_part_number,
17980 tg3_chip_rev_id(tp),
17981 tg3_bus_string(tp, str),
17984 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {
17987 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17988 ethtype = "10/100Base-TX";
17989 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17990 ethtype = "1000Base-SX";
17992 ethtype = "10/100/1000Base-T";
17994 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17995 "(WireSpeed[%d], EEE[%d])\n",
17996 tg3_phy_string(tp), ethtype,
17997 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17998 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
18001 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
18002 (dev->features & NETIF_F_RXCSUM) != 0,
18003 tg3_flag(tp, USE_LINKCHG_REG) != 0,
18004 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
18005 tg3_flag(tp, ENABLE_ASF) != 0,
18006 tg3_flag(tp, TSO_CAPABLE) != 0);
18007 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
18009 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
18010 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
18012 pci_save_state(pdev);
18018 iounmap(tp->aperegs);
18019 tp->aperegs = NULL;
18032 pci_release_regions(pdev);
18034 err_out_disable_pdev:
18035 if (pci_is_enabled(pdev))
18036 pci_disable_device(pdev);
18040 static void tg3_remove_one(struct pci_dev *pdev)
18042 struct net_device *dev = pci_get_drvdata(pdev);
18045 struct tg3 *tp = netdev_priv(dev);
18049 release_firmware(tp->fw);
18051 tg3_reset_task_cancel(tp);
18053 if (tg3_flag(tp, USE_PHYLIB)) {
18058 unregister_netdev(dev);
18060 iounmap(tp->aperegs);
18061 tp->aperegs = NULL;
18068 pci_release_regions(pdev);
18069 pci_disable_device(pdev);
18073 #ifdef CONFIG_PM_SLEEP
18074 static int tg3_suspend(struct device *device)
18076 struct net_device *dev = dev_get_drvdata(device);
18077 struct tg3 *tp = netdev_priv(dev);
18082 if (!netif_running(dev))
18085 tg3_reset_task_cancel(tp);
18087 tg3_netif_stop(tp);
18089 tg3_timer_stop(tp);
18091 tg3_full_lock(tp, 1);
18092 tg3_disable_ints(tp);
18093 tg3_full_unlock(tp);
18095 netif_device_detach(dev);
18097 tg3_full_lock(tp, 0);
18098 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18099 tg3_flag_clear(tp, INIT_COMPLETE);
18100 tg3_full_unlock(tp);
18102 err = tg3_power_down_prepare(tp);
18106 tg3_full_lock(tp, 0);
18108 tg3_flag_set(tp, INIT_COMPLETE);
18109 err2 = tg3_restart_hw(tp, true);
18113 tg3_timer_start(tp);
18115 netif_device_attach(dev);
18116 tg3_netif_start(tp);
18119 tg3_full_unlock(tp);
18130 static int tg3_resume(struct device *device)
18132 struct net_device *dev = dev_get_drvdata(device);
18133 struct tg3 *tp = netdev_priv(dev);
18138 if (!netif_running(dev))
18141 netif_device_attach(dev);
18143 tg3_full_lock(tp, 0);
18145 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18147 tg3_flag_set(tp, INIT_COMPLETE);
18148 err = tg3_restart_hw(tp,
18149 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18153 tg3_timer_start(tp);
18155 tg3_netif_start(tp);
18158 tg3_full_unlock(tp);
18167 #endif /* CONFIG_PM_SLEEP */
18169 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18171 static void tg3_shutdown(struct pci_dev *pdev)
18173 struct net_device *dev = pci_get_drvdata(pdev);
18174 struct tg3 *tp = netdev_priv(dev);
18176 tg3_reset_task_cancel(tp);
18180 netif_device_detach(dev);
18182 if (netif_running(dev))
18185 if (system_state == SYSTEM_POWER_OFF)
18186 tg3_power_down(tp);
18190 pci_disable_device(pdev);
18194 * tg3_io_error_detected - called when PCI error is detected
18195 * @pdev: Pointer to PCI device
18196 * @state: The current pci connection state
18198 * This function is called after a PCI bus error affecting
18199 * this device has been detected.
18201 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18202 pci_channel_state_t state)
18204 struct net_device *netdev = pci_get_drvdata(pdev);
18205 struct tg3 *tp = netdev_priv(netdev);
18206 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18208 netdev_info(netdev, "PCI I/O error detected\n");
18210 /* Want to make sure that the reset task doesn't run */
18211 tg3_reset_task_cancel(tp);
18215 /* Could be second call or maybe we don't have netdev yet */
18216 if (!netdev || tp->pcierr_recovery || !netif_running(netdev))
18219 /* We needn't recover from permanent error */
18220 if (state == pci_channel_io_frozen)
18221 tp->pcierr_recovery = true;
18225 tg3_netif_stop(tp);
18227 tg3_timer_stop(tp);
18229 netif_device_detach(netdev);
18231 /* Clean up software state, even if MMIO is blocked */
18232 tg3_full_lock(tp, 0);
18233 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18234 tg3_full_unlock(tp);
18237 if (state == pci_channel_io_perm_failure) {
18239 tg3_napi_enable(tp);
18242 err = PCI_ERS_RESULT_DISCONNECT;
18244 pci_disable_device(pdev);
18253 * tg3_io_slot_reset - called after the pci bus has been reset.
18254 * @pdev: Pointer to PCI device
18256 * Restart the card from scratch, as if from a cold-boot.
18257 * At this point, the card has exprienced a hard reset,
18258 * followed by fixups by BIOS, and has its config space
18259 * set up identically to what it was at cold boot.
18261 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18263 struct net_device *netdev = pci_get_drvdata(pdev);
18264 struct tg3 *tp = netdev_priv(netdev);
18265 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18270 if (pci_enable_device(pdev)) {
18271 dev_err(&pdev->dev,
18272 "Cannot re-enable PCI device after reset.\n");
18276 pci_set_master(pdev);
18277 pci_restore_state(pdev);
18278 pci_save_state(pdev);
18280 if (!netdev || !netif_running(netdev)) {
18281 rc = PCI_ERS_RESULT_RECOVERED;
18285 err = tg3_power_up(tp);
18289 rc = PCI_ERS_RESULT_RECOVERED;
18292 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18293 tg3_napi_enable(tp);
18302 * tg3_io_resume - called when traffic can start flowing again.
18303 * @pdev: Pointer to PCI device
18305 * This callback is called when the error recovery driver tells
18306 * us that its OK to resume normal operation.
18308 static void tg3_io_resume(struct pci_dev *pdev)
18310 struct net_device *netdev = pci_get_drvdata(pdev);
18311 struct tg3 *tp = netdev_priv(netdev);
18316 if (!netdev || !netif_running(netdev))
18319 tg3_full_lock(tp, 0);
18320 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18321 tg3_flag_set(tp, INIT_COMPLETE);
18322 err = tg3_restart_hw(tp, true);
18324 tg3_full_unlock(tp);
18325 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18329 netif_device_attach(netdev);
18331 tg3_timer_start(tp);
18333 tg3_netif_start(tp);
18335 tg3_full_unlock(tp);
18340 tp->pcierr_recovery = false;
18344 static const struct pci_error_handlers tg3_err_handler = {
18345 .error_detected = tg3_io_error_detected,
18346 .slot_reset = tg3_io_slot_reset,
18347 .resume = tg3_io_resume
18350 static struct pci_driver tg3_driver = {
18351 .name = DRV_MODULE_NAME,
18352 .id_table = tg3_pci_tbl,
18353 .probe = tg3_init_one,
18354 .remove = tg3_remove_one,
18355 .err_handler = &tg3_err_handler,
18356 .driver.pm = &tg3_pm_ops,
18357 .shutdown = tg3_shutdown,
18360 module_pci_driver(tg3_driver);