1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET MDIO routines
5 * Copyright (c) 2014-2017 Broadcom
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
29 /* setup netdev link state when PHY link status change and
30 * update UMAC and RGMII block when link up
32 void bcmgenet_mii_setup(struct net_device *dev)
34 struct bcmgenet_priv *priv = netdev_priv(dev);
35 struct phy_device *phydev = dev->phydev;
36 u32 reg, cmd_bits = 0;
37 bool status_changed = false;
39 if (priv->old_link != phydev->link) {
40 status_changed = true;
41 priv->old_link = phydev->link;
45 /* check speed/duplex/pause changes */
46 if (priv->old_speed != phydev->speed) {
47 status_changed = true;
48 priv->old_speed = phydev->speed;
51 if (priv->old_duplex != phydev->duplex) {
52 status_changed = true;
53 priv->old_duplex = phydev->duplex;
56 if (priv->old_pause != phydev->pause) {
57 status_changed = true;
58 priv->old_pause = phydev->pause;
61 /* done if nothing has changed */
66 if (phydev->speed == SPEED_1000)
67 cmd_bits = UMAC_SPEED_1000;
68 else if (phydev->speed == SPEED_100)
69 cmd_bits = UMAC_SPEED_100;
71 cmd_bits = UMAC_SPEED_10;
72 cmd_bits <<= CMD_SPEED_SHIFT;
75 if (phydev->duplex != DUPLEX_FULL)
76 cmd_bits |= CMD_HD_EN;
78 /* pause capability */
80 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
83 * Program UMAC and RGMII block based on established
84 * link speed, duplex, and pause. The speed set in
85 * umac->cmd tell RGMII block which clock to use for
86 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
87 * Receive clock is provided by the PHY.
89 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
92 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
94 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
95 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
97 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
99 if (reg & CMD_SW_RESET) {
100 reg &= ~CMD_SW_RESET;
101 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
103 reg |= CMD_TX_EN | CMD_RX_EN;
105 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
107 priv->eee.eee_active = phy_init_eee(phydev, 0) >= 0;
108 bcmgenet_eee_enable_set(dev,
109 priv->eee.eee_enabled && priv->eee.eee_active,
110 priv->eee.tx_lpi_enabled);
112 /* done if nothing has changed */
116 /* needed for MoCA fixed PHY to reflect correct link status */
117 netif_carrier_off(dev);
120 phy_print_status(phydev);
124 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
125 struct fixed_phy_status *status)
127 struct bcmgenet_priv *priv;
130 if (dev && dev->phydev && status) {
131 priv = netdev_priv(dev);
132 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
133 status->link = !!(reg & MODE_LINK_STATUS);
139 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
141 struct bcmgenet_priv *priv = netdev_priv(dev);
144 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
145 if (GENET_IS_V4(priv)) {
146 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
148 reg &= ~EXT_CK25_DIS;
149 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
152 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
153 reg |= EXT_GPHY_RESET;
154 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
157 reg &= ~EXT_GPHY_RESET;
159 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
161 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
165 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
172 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
174 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
175 fixed_phy_set_link_update(priv->dev->phydev,
176 bcmgenet_fixed_phy_link_update);
179 int bcmgenet_mii_config(struct net_device *dev, bool init)
181 struct bcmgenet_priv *priv = netdev_priv(dev);
182 struct phy_device *phydev = dev->phydev;
183 struct device *kdev = &priv->pdev->dev;
184 const char *phy_name = NULL;
189 switch (priv->phy_interface) {
190 case PHY_INTERFACE_MODE_INTERNAL:
191 phy_name = "internal PHY";
193 case PHY_INTERFACE_MODE_MOCA:
194 /* Irrespective of the actually configured PHY speed (100 or
195 * 1000) GENETv4 only has an internal GPHY so we will just end
196 * up masking the Gigabit features from what we support, not
197 * switching to the EPHY
199 if (GENET_IS_V4(priv))
200 port_ctrl = PORT_MODE_INT_GPHY;
202 port_ctrl = PORT_MODE_INT_EPHY;
206 if (!GENET_IS_V5(priv))
207 port_ctrl |= LED_ACT_SOURCE_MAC;
208 bcmgenet_moca_phy_setup(priv);
212 case PHY_INTERFACE_MODE_MII:
213 phy_name = "external MII";
214 phy_set_max_speed(phydev, SPEED_100);
215 port_ctrl = PORT_MODE_EXT_EPHY;
218 case PHY_INTERFACE_MODE_REVMII:
219 phy_name = "external RvMII";
220 /* of_mdiobus_register took care of reading the 'max-speed'
221 * PHY property for us, effectively limiting the PHY supported
222 * capabilities, use that knowledge to also configure the
223 * Reverse MII interface correctly.
225 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
226 dev->phydev->supported))
227 port_ctrl = PORT_MODE_EXT_RVMII_50;
229 port_ctrl = PORT_MODE_EXT_RVMII_25;
232 case PHY_INTERFACE_MODE_RGMII:
233 /* RGMII_NO_ID: TXC transitions at the same time as TXD
234 * (requires PCB or receiver-side delay)
236 * ID is implicitly disabled for 100Mbps (RG)MII operation.
238 phy_name = "external RGMII (no delay)";
239 id_mode_dis = BIT(16);
240 port_ctrl = PORT_MODE_EXT_GPHY;
243 case PHY_INTERFACE_MODE_RGMII_TXID:
244 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */
245 phy_name = "external RGMII (TX delay)";
246 port_ctrl = PORT_MODE_EXT_GPHY;
249 case PHY_INTERFACE_MODE_RGMII_RXID:
250 phy_name = "external RGMII (RX delay)";
251 port_ctrl = PORT_MODE_EXT_GPHY;
254 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
258 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
260 priv->ext_phy = !priv->internal_phy &&
261 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
263 /* This is an external PHY (xMII), so we need to enable the RGMII
264 * block for the interface to work
267 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
270 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
271 reg |= RGMII_MODE_EN_V123;
273 reg |= RGMII_MODE_EN;
274 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
278 dev_info(kdev, "configuring instance for %s\n", phy_name);
283 int bcmgenet_mii_probe(struct net_device *dev)
285 struct bcmgenet_priv *priv = netdev_priv(dev);
286 struct device *kdev = &priv->pdev->dev;
287 struct device_node *dn = kdev->of_node;
288 struct phy_device *phydev;
292 /* Communicate the integrated PHY revision */
293 if (priv->internal_phy)
294 phy_flags = priv->gphy_rev;
296 /* Initialize link state variables that bcmgenet_mii_setup() uses */
298 priv->old_speed = -1;
299 priv->old_duplex = -1;
300 priv->old_pause = -1;
303 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
304 phy_flags, priv->phy_interface);
306 pr_err("could not attach to PHY\n");
310 if (has_acpi_companion(kdev)) {
311 char mdio_bus_id[MII_BUS_ID_SIZE];
312 struct mii_bus *unimacbus;
314 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
315 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
317 unimacbus = mdio_find_bus(mdio_bus_id);
319 pr_err("Unable to find mii\n");
322 phydev = phy_find_first(unimacbus);
323 put_device(&unimacbus->dev);
325 pr_err("Unable to find PHY\n");
329 phydev = dev->phydev;
331 phydev->dev_flags = phy_flags;
333 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
334 priv->phy_interface);
336 pr_err("could not attach to PHY\n");
341 /* Configure port multiplexer based on what the probed PHY device since
342 * reading the 'max-speed' property determines the maximum supported
343 * PHY speed which is needed for bcmgenet_mii_config() to configure
344 * things appropriately.
346 ret = bcmgenet_mii_config(dev, true);
348 phy_disconnect(dev->phydev);
352 linkmode_copy(phydev->advertising, phydev->supported);
354 /* The internal PHY has its link interrupts routed to the
355 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
356 * that prevents the signaling of link UP interrupts when
357 * the link operates at 10Mbps, so fallback to polling for
358 * those versions of GENET.
360 if (priv->internal_phy && !GENET_IS_V5(priv))
361 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
366 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
368 struct device_node *dn = priv->pdev->dev.of_node;
369 struct device *kdev = &priv->pdev->dev;
372 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
376 priv->mdio_dn = of_get_compatible_child(dn, compat);
378 if (!priv->mdio_dn) {
379 dev_err(kdev, "unable to find MDIO bus node\n");
383 return priv->mdio_dn;
386 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
387 struct unimac_mdio_pdata *ppd)
389 struct device *kdev = &priv->pdev->dev;
390 struct bcmgenet_platform_data *pd = kdev->platform_data;
392 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
394 * Internal or external PHY with MDIO access
396 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
397 ppd->phy_mask = 1 << pd->phy_address;
403 static int bcmgenet_mii_wait(void *wait_func_data)
405 struct bcmgenet_priv *priv = wait_func_data;
407 wait_event_timeout(priv->wq,
408 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
414 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
416 struct platform_device *pdev = priv->pdev;
417 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
418 struct device_node *dn = pdev->dev.of_node;
419 struct unimac_mdio_pdata ppd;
420 struct platform_device *ppdev;
421 struct resource *pres, res;
424 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 dev_err(&pdev->dev, "Invalid resource\n");
429 memset(&res, 0, sizeof(res));
430 memset(&ppd, 0, sizeof(ppd));
432 ppd.wait_func = bcmgenet_mii_wait;
433 ppd.wait_func_data = priv;
434 ppd.bus_name = "bcmgenet MII bus";
436 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
437 * and is 2 * 32-bits word long, 8 bytes total.
439 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
440 res.end = res.start + 8;
441 res.flags = IORESOURCE_MEM;
444 id = of_alias_get_id(dn, "eth");
448 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
452 /* Retain this platform_device pointer for later cleanup */
453 priv->mii_pdev = ppdev;
454 ppdev->dev.parent = &pdev->dev;
456 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
458 bcmgenet_mii_pdata_init(priv, &ppd);
462 ret = platform_device_add_resources(ppdev, &res, 1);
466 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
470 ret = platform_device_add(ppdev);
476 platform_device_put(ppdev);
480 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
482 struct device *kdev = &priv->pdev->dev;
483 int phy_mode = device_get_phy_mode(kdev);
486 dev_err(kdev, "invalid PHY mode property\n");
490 priv->phy_interface = phy_mode;
492 /* We need to specifically look up whether this PHY interface is
493 * internal or not *before* we even try to probe the PHY driver
494 * over MDIO as we may have shut down the internal PHY for power
497 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
498 priv->internal_phy = true;
503 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
505 struct device_node *dn = priv->pdev->dev.of_node;
506 struct phy_device *phydev;
509 /* Fetch the PHY phandle */
510 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
512 /* In the case of a fixed PHY, the DT node associated
513 * to the PHY is the Ethernet MAC DT node.
515 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
516 ret = of_phy_register_fixed_link(dn);
520 priv->phy_dn = of_node_get(dn);
523 /* Get the link mode */
524 ret = bcmgenet_phy_interface_init(priv);
528 /* Make sure we initialize MoCA PHYs with a link down */
529 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
530 phydev = of_phy_find_device(dn);
533 put_device(&phydev->mdio.dev);
540 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
542 struct device *kdev = &priv->pdev->dev;
543 struct bcmgenet_platform_data *pd = kdev->platform_data;
544 char phy_name[MII_BUS_ID_SIZE + 3];
545 char mdio_bus_id[MII_BUS_ID_SIZE];
546 struct phy_device *phydev;
548 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
549 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
551 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
552 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
553 mdio_bus_id, pd->phy_address);
556 * Internal or external PHY with MDIO access
558 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
560 dev_err(kdev, "failed to register PHY device\n");
565 * MoCA port or no MDIO access.
566 * Use fixed PHY to represent the link layer.
568 struct fixed_phy_status fphy_status = {
570 .speed = pd->phy_speed,
571 .duplex = pd->phy_duplex,
576 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
577 if (IS_ERR(phydev)) {
578 dev_err(kdev, "failed to register fixed PHY device\n");
582 /* Make sure we initialize MoCA PHYs with a link down */
587 priv->phy_interface = pd->phy_interface;
592 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
594 struct device *kdev = &priv->pdev->dev;
595 struct device_node *dn = kdev->of_node;
598 return bcmgenet_mii_of_init(priv);
599 else if (has_acpi_companion(kdev))
600 return bcmgenet_phy_interface_init(priv);
602 return bcmgenet_mii_pd_init(priv);
605 int bcmgenet_mii_init(struct net_device *dev)
607 struct bcmgenet_priv *priv = netdev_priv(dev);
610 ret = bcmgenet_mii_register(priv);
614 ret = bcmgenet_mii_bus_init(priv);
621 bcmgenet_mii_exit(dev);
625 void bcmgenet_mii_exit(struct net_device *dev)
627 struct bcmgenet_priv *priv = netdev_priv(dev);
628 struct device_node *dn = priv->pdev->dev.of_node;
630 if (of_phy_is_fixed_link(dn))
631 of_phy_deregister_fixed_link(dn);
632 of_node_put(priv->phy_dn);
633 clk_prepare_enable(priv->clk);
634 platform_device_unregister(priv->mii_pdev);
635 clk_disable_unprepare(priv->clk);