drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27 #include <linux/platform_data/mdio-bcm-unimac.h>
  28
  29 #include "bcmgenet.h"
  30
  31 /* setup netdev link state when PHY link status change and
  32  * update UMAC and RGMII block when link up
  33  */
  34 void bcmgenet_mii_setup(struct net_device *dev)
  35 {
  36         struct bcmgenet_priv *priv = netdev_priv(dev);
  37         struct phy_device *phydev = dev->phydev;
  38         u32 reg, cmd_bits = 0;
  39         bool status_changed = false;
  40
  41         if (priv->old_link != phydev->link) {
  42                 status_changed = true;
  43                 priv->old_link = phydev->link;
  44         }
  45
  46         if (phydev->link) {
  47                 /* check speed/duplex/pause changes */
  48                 if (priv->old_speed != phydev->speed) {
  49                         status_changed = true;
  50                         priv->old_speed = phydev->speed;
  51                 }
  52
  53                 if (priv->old_duplex != phydev->duplex) {
  54                         status_changed = true;
  55                         priv->old_duplex = phydev->duplex;
  56                 }
  57
  58                 if (priv->old_pause != phydev->pause) {
  59                         status_changed = true;
  60                         priv->old_pause = phydev->pause;
  61                 }
  62
  63                 /* done if nothing has changed */
  64                 if (!status_changed)
  65                         return;
  66
  67                 /* speed */
  68                 if (phydev->speed == SPEED_1000)
  69                         cmd_bits = UMAC_SPEED_1000;
  70                 else if (phydev->speed == SPEED_100)
  71                         cmd_bits = UMAC_SPEED_100;
  72                 else
  73                         cmd_bits = UMAC_SPEED_10;
  74                 cmd_bits <<= CMD_SPEED_SHIFT;
  75
  76                 /* duplex */
  77                 if (phydev->duplex != DUPLEX_FULL)
  78                         cmd_bits |= CMD_HD_EN;
  79
  80                 /* pause capability */
  81                 if (!phydev->pause)
  82                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  83
  84                 /*
  85                  * Program UMAC and RGMII block based on established
  86                  * link speed, duplex, and pause. The speed set in
  87                  * umac->cmd tell RGMII block which clock to use for
  88                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
  89                  * Receive clock is provided by the PHY.
  90                  */
  91                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
  92                 reg &= ~OOB_DISABLE;
  93                 reg |= RGMII_LINK;
  94                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
  95
  96                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
  97                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  98                                CMD_HD_EN |
  99                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 100                 reg |= cmd_bits;
 101                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 102         } else {
 103                 /* done if nothing has changed */
 104                 if (!status_changed)
 105                         return;
 106
 107                 /* needed for MoCA fixed PHY to reflect correct link status */
 108                 netif_carrier_off(dev);
 109         }
 110
 111         phy_print_status(phydev);
 112 }
 113
 114
 115 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 116                                           struct fixed_phy_status *status)
 117 {
 118         struct bcmgenet_priv *priv;
 119         u32 reg;
 120
 121         if (dev && dev->phydev && status) {
 122                 priv = netdev_priv(dev);
 123                 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
 124                 status->link = !!(reg & MODE_LINK_STATUS);
 125         }
 126
 127         return 0;
 128 }
 129
 130 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 131 {
 132         struct bcmgenet_priv *priv = netdev_priv(dev);
 133         u32 reg = 0;
 134
 135         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 136         if (GENET_IS_V4(priv)) {
 137                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 138                 if (enable) {
 139                         reg &= ~EXT_CK25_DIS;
 140                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 141                         mdelay(1);
 142
 143                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 144                         reg |= EXT_GPHY_RESET;
 145                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 146                         mdelay(1);
 147
 148                         reg &= ~EXT_GPHY_RESET;
 149                 } else {
 150                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 151                                EXT_GPHY_RESET;
 152                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 153                         mdelay(1);
 154                         reg |= EXT_CK25_DIS;
 155                 }
 156                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 157                 udelay(60);
 158         } else {
 159                 mdelay(1);
 160         }
 161 }
 162
 163 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 164 {
 165         u32 reg;
 166
 167         if (!GENET_IS_V5(priv)) {
 168                 /* Speed settings are set in bcmgenet_mii_setup() */
 169                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 170                 reg |= LED_ACT_SOURCE_MAC;
 171                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 172         }
 173
 174         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 175                 fixed_phy_set_link_update(priv->dev->phydev,
 176                                           bcmgenet_fixed_phy_link_update);
 177 }
 178
 179 int bcmgenet_mii_config(struct net_device *dev, bool init)
 180 {
 181         struct bcmgenet_priv *priv = netdev_priv(dev);
 182         struct phy_device *phydev = dev->phydev;
 183         struct device *kdev = &priv->pdev->dev;
 184         const char *phy_name = NULL;
 185         u32 id_mode_dis = 0;
 186         u32 port_ctrl;
 187         int bmcr = -1;
 188         int ret;
 189         u32 reg;
 190
 191         /* MAC clocking workaround during reset of umac state machines */
 192         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 193         if (reg & CMD_SW_RESET) {
 194                 /* An MII PHY must be isolated to prevent TXC contention */
 195                 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
 196                         ret = phy_read(phydev, MII_BMCR);
 197                         if (ret >= 0) {
 198                                 bmcr = ret;
 199                                 ret = phy_write(phydev, MII_BMCR,
 200                                                 bmcr | BMCR_ISOLATE);
 201                         }
 202                         if (ret) {
 203                                 netdev_err(dev, "failed to isolate PHY\n");
 204                                 return ret;
 205                         }
 206                 }
 207                 /* Switch MAC clocking to RGMII generated clock */
 208                 bcmgenet_sys_writel(priv, PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 209                 /* Ensure 5 clks with Rx disabled
 210                  * followed by 5 clks with Reset asserted
 211                  */
 212                 udelay(4);
 213                 reg &= ~(CMD_SW_RESET | CMD_LCL_LOOP_EN);
 214                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 215                 /* Ensure 5 more clocks before Rx is enabled */
 216                 udelay(2);
 217         }
 218
 219         priv->ext_phy = !priv->internal_phy &&
 220                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 221
 222         switch (priv->phy_interface) {
 223         case PHY_INTERFACE_MODE_INTERNAL:
 224         case PHY_INTERFACE_MODE_MOCA:
 225                 /* Irrespective of the actually configured PHY speed (100 or
 226                  * 1000) GENETv4 only has an internal GPHY so we will just end
 227                  * up masking the Gigabit features from what we support, not
 228                  * switching to the EPHY
 229                  */
 230                 if (GENET_IS_V4(priv))
 231                         port_ctrl = PORT_MODE_INT_GPHY;
 232                 else
 233                         port_ctrl = PORT_MODE_INT_EPHY;
 234
 235                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 236
 237                 if (priv->internal_phy) {
 238                         phy_name = "internal PHY";
 239                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 240                         phy_name = "MoCA";
 241                         bcmgenet_moca_phy_setup(priv);
 242                 }
 243                 break;
 244
 245         case PHY_INTERFACE_MODE_MII:
 246                 phy_name = "external MII";
 247                 phydev->supported &= PHY_BASIC_FEATURES;
 248                 bcmgenet_sys_writel(priv,
 249                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 250                 /* Restore the MII PHY after isolation */
 251                 if (bmcr >= 0)
 252                         phy_write(phydev, MII_BMCR, bmcr);
 253                 break;
 254
 255         case PHY_INTERFACE_MODE_REVMII:
 256                 phy_name = "external RvMII";
 257                 /* of_mdiobus_register took care of reading the 'max-speed'
 258                  * PHY property for us, effectively limiting the PHY supported
 259                  * capabilities, use that knowledge to also configure the
 260                  * Reverse MII interface correctly.
 261                  */
 262                 if (dev->phydev->supported & PHY_1000BT_FEATURES)
 263                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 264                 else
 265                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 266                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 267                 break;
 268
 269         case PHY_INTERFACE_MODE_RGMII:
 270                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 271                  *              (requires PCB or receiver-side delay)
 272                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 273                  *
 274                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 275                  */
 276                 id_mode_dis = BIT(16);
 277                 /* fall through */
 278         case PHY_INTERFACE_MODE_RGMII_TXID:
 279                 if (id_mode_dis)
 280                         phy_name = "external RGMII (no delay)";
 281                 else
 282                         phy_name = "external RGMII (TX delay)";
 283                 bcmgenet_sys_writel(priv,
 284                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 285                 break;
 286         default:
 287                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 288                 return -EINVAL;
 289         }
 290
 291         /* This is an external PHY (xMII), so we need to enable the RGMII
 292          * block for the interface to work
 293          */
 294         if (priv->ext_phy) {
 295                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 296                 reg |= id_mode_dis;
 297                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
 298                         reg |= RGMII_MODE_EN_V123;
 299                 else
 300                         reg |= RGMII_MODE_EN;
 301                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 302         }
 303
 304         if (init)
 305                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 306
 307         return 0;
 308 }
 309
 310 int bcmgenet_mii_probe(struct net_device *dev)
 311 {
 312         struct bcmgenet_priv *priv = netdev_priv(dev);
 313         struct device_node *dn = priv->pdev->dev.of_node;
 314         struct phy_device *phydev;
 315         u32 phy_flags = 0;
 316         int ret;
 317
 318         /* Communicate the integrated PHY revision */
 319         if (priv->internal_phy)
 320                 phy_flags = priv->gphy_rev;
 321
 322         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 323         priv->old_link = -1;
 324         priv->old_speed = -1;
 325         priv->old_duplex = -1;
 326         priv->old_pause = -1;
 327
 328         if (dn) {
 329                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 330                                         phy_flags, priv->phy_interface);
 331                 if (!phydev) {
 332                         pr_err("could not attach to PHY\n");
 333                         return -ENODEV;
 334                 }
 335         } else {
 336                 phydev = dev->phydev;
 337                 phydev->dev_flags = phy_flags;
 338
 339                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 340                                          priv->phy_interface);
 341                 if (ret) {
 342                         pr_err("could not attach to PHY\n");
 343                         return -ENODEV;
 344                 }
 345         }
 346
 347         /* Configure port multiplexer based on what the probed PHY device since
 348          * reading the 'max-speed' property determines the maximum supported
 349          * PHY speed which is needed for bcmgenet_mii_config() to configure
 350          * things appropriately.
 351          */
 352         ret = bcmgenet_mii_config(dev, true);
 353         if (ret) {
 354                 phy_disconnect(dev->phydev);
 355                 return ret;
 356         }
 357
 358         phydev->advertising = phydev->supported;
 359
 360         /* The internal PHY has its link interrupts routed to the
 361          * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
 362          * that prevents the signaling of link UP interrupts when
 363          * the link operates at 10Mbps, so fallback to polling for
 364          * those versions of GENET.
 365          */
 366         if (priv->internal_phy && !GENET_IS_V5(priv))
 367                 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
 368
 369         return 0;
 370 }
 371
 372 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
 373 {
 374         struct device_node *dn = priv->pdev->dev.of_node;
 375         struct device *kdev = &priv->pdev->dev;
 376         char *compat;
 377
 378         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 379         if (!compat)
 380                 return NULL;
 381
 382         priv->mdio_dn = of_get_compatible_child(dn, compat);
 383         kfree(compat);
 384         if (!priv->mdio_dn) {
 385                 dev_err(kdev, "unable to find MDIO bus node\n");
 386                 return NULL;
 387         }
 388
 389         return priv->mdio_dn;
 390 }
 391
 392 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
 393                                     struct unimac_mdio_pdata *ppd)
 394 {
 395         struct device *kdev = &priv->pdev->dev;
 396         struct bcmgenet_platform_data *pd = kdev->platform_data;
 397
 398         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 399                 /*
 400                  * Internal or external PHY with MDIO access
 401                  */
 402                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 403                         ppd->phy_mask = 1 << pd->phy_address;
 404                 else
 405                         ppd->phy_mask = 0;
 406         }
 407 }
 408
 409 static int bcmgenet_mii_wait(void *wait_func_data)
 410 {
 411         struct bcmgenet_priv *priv = wait_func_data;
 412
 413         wait_event_timeout(priv->wq,
 414                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
 415                            & MDIO_START_BUSY),
 416                            HZ / 100);
 417         return 0;
 418 }
 419
 420 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
 421 {
 422         struct platform_device *pdev = priv->pdev;
 423         struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
 424         struct device_node *dn = pdev->dev.of_node;
 425         struct unimac_mdio_pdata ppd;
 426         struct platform_device *ppdev;
 427         struct resource *pres, res;
 428         int id, ret;
 429
 430         pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 431         if (!pres) {
 432                 dev_err(&pdev->dev, "Invalid resource\n");
 433                 return -EINVAL;
 434         }
 435         memset(&res, 0, sizeof(res));
 436         memset(&ppd, 0, sizeof(ppd));
 437
 438         ppd.wait_func = bcmgenet_mii_wait;
 439         ppd.wait_func_data = priv;
 440         ppd.bus_name = "bcmgenet MII bus";
 441
 442         /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
 443          * and is 2 * 32-bits word long, 8 bytes total.
 444          */
 445         res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
 446         res.end = res.start + 8;
 447         res.flags = IORESOURCE_MEM;
 448
 449         if (dn)
 450                 id = of_alias_get_id(dn, "eth");
 451         else
 452                 id = pdev->id;
 453
 454         ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
 455         if (!ppdev)
 456                 return -ENOMEM;
 457
 458         /* Retain this platform_device pointer for later cleanup */
 459         priv->mii_pdev = ppdev;
 460         ppdev->dev.parent = &pdev->dev;
 461         ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
 462         if (pdata)
 463                 bcmgenet_mii_pdata_init(priv, &ppd);
 464
 465         ret = platform_device_add_resources(ppdev, &res, 1);
 466         if (ret)
 467                 goto out;
 468
 469         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
 470         if (ret)
 471                 goto out;
 472
 473         ret = platform_device_add(ppdev);
 474         if (ret)
 475                 goto out;
 476
 477         return 0;
 478 out:
 479         platform_device_put(ppdev);
 480         return ret;
 481 }
 482
 483 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 484 {
 485         struct device_node *dn = priv->pdev->dev.of_node;
 486         struct device *kdev = &priv->pdev->dev;
 487         struct phy_device *phydev;
 488         int phy_mode;
 489         int ret;
 490
 491         /* Fetch the PHY phandle */
 492         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 493
 494         /* In the case of a fixed PHY, the DT node associated
 495          * to the PHY is the Ethernet MAC DT node.
 496          */
 497         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 498                 ret = of_phy_register_fixed_link(dn);
 499                 if (ret)
 500                         return ret;
 501
 502                 priv->phy_dn = of_node_get(dn);
 503         }
 504
 505         /* Get the link mode */
 506         phy_mode = of_get_phy_mode(dn);
 507         if (phy_mode < 0) {
 508                 dev_err(kdev, "invalid PHY mode property\n");
 509                 return phy_mode;
 510         }
 511
 512         priv->phy_interface = phy_mode;
 513
 514         /* We need to specifically look up whether this PHY interface is internal
 515          * or not *before* we even try to probe the PHY driver over MDIO as we
 516          * may have shut down the internal PHY for power saving purposes.
 517          */
 518         if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
 519                 priv->internal_phy = true;
 520
 521         /* Make sure we initialize MoCA PHYs with a link down */
 522         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 523                 phydev = of_phy_find_device(dn);
 524                 if (phydev) {
 525                         phydev->link = 0;
 526                         put_device(&phydev->mdio.dev);
 527                 }
 528         }
 529
 530         return 0;
 531 }
 532
 533 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 534 {
 535         struct device *kdev = &priv->pdev->dev;
 536         struct bcmgenet_platform_data *pd = kdev->platform_data;
 537         char phy_name[MII_BUS_ID_SIZE + 3];
 538         char mdio_bus_id[MII_BUS_ID_SIZE];
 539         struct phy_device *phydev;
 540
 541         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 542                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 543
 544         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 545                 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
 546                          mdio_bus_id, pd->phy_address);
 547
 548                 /*
 549                  * Internal or external PHY with MDIO access
 550                  */
 551                 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
 552                 if (!phydev) {
 553                         dev_err(kdev, "failed to register PHY device\n");
 554                         return -ENODEV;
 555                 }
 556         } else {
 557                 /*
 558                  * MoCA port or no MDIO access.
 559                  * Use fixed PHY to represent the link layer.
 560                  */
 561                 struct fixed_phy_status fphy_status = {
 562                         .link = 1,
 563                         .speed = pd->phy_speed,
 564                         .duplex = pd->phy_duplex,
 565                         .pause = 0,
 566                         .asym_pause = 0,
 567                 };
 568
 569                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
 570                 if (!phydev || IS_ERR(phydev)) {
 571                         dev_err(kdev, "failed to register fixed PHY device\n");
 572                         return -ENODEV;
 573                 }
 574
 575                 /* Make sure we initialize MoCA PHYs with a link down */
 576                 phydev->link = 0;
 577
 578         }
 579
 580         priv->phy_interface = pd->phy_interface;
 581
 582         return 0;
 583 }
 584
 585 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 586 {
 587         struct device_node *dn = priv->pdev->dev.of_node;
 588
 589         if (dn)
 590                 return bcmgenet_mii_of_init(priv);
 591         else
 592                 return bcmgenet_mii_pd_init(priv);
 593 }
 594
 595 int bcmgenet_mii_init(struct net_device *dev)
 596 {
 597         struct bcmgenet_priv *priv = netdev_priv(dev);
 598         int ret;
 599
 600         ret = bcmgenet_mii_register(priv);
 601         if (ret)
 602                 return ret;
 603
 604         ret = bcmgenet_mii_bus_init(priv);
 605         if (ret)
 606                 goto out;
 607
 608         return 0;
 609
 610 out:
 611         bcmgenet_mii_exit(dev);
 612         return ret;
 613 }
 614
 615 void bcmgenet_mii_exit(struct net_device *dev)
 616 {
 617         struct bcmgenet_priv *priv = netdev_priv(dev);
 618         struct device_node *dn = priv->pdev->dev.of_node;
 619
 620         if (of_phy_is_fixed_link(dn))
 621                 of_phy_deregister_fixed_link(dn);
 622         of_node_put(priv->phy_dn);
 623         clk_prepare_enable(priv->clk);
 624         platform_device_unregister(priv->mii_pdev);
 625         clk_disable_unprepare(priv->clk);
 626 }