1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2020 Broadcom
9 #include <linux/skbuff.h>
10 #include <linux/netdevice.h>
11 #include <linux/spinlock.h>
12 #include <linux/clk.h>
13 #include <linux/mii.h>
14 #include <linux/if_vlan.h>
15 #include <linux/phy.h>
16 #include <linux/dim.h>
17 #include <linux/ethtool.h>
19 #include "../unimac.h"
21 /* total number of Buffer Descriptors, same for Rx/Tx */
22 #define TOTAL_DESC 256
24 /* which ring is descriptor based */
27 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
28 * 1536 is multiple of 256 bytes
30 #define ENET_BRCM_TAG_LEN 6
32 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
33 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
34 #define DMA_MAX_BURST_LENGTH 0x10
36 /* misc. configuration */
37 #define MAX_NUM_OF_FS_RULES 16
38 #define CLEAR_ALL_HFB 0xFF
39 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4)
40 #define DMA_FC_THRESH_LO 5
42 /* 64B receive/transmit status block */
44 u32 length_status; /* length and peripheral status */
45 u32 ext_status; /* Extended status*/
46 u32 rx_csum; /* partial rx checksum */
47 u32 unused1[9]; /* unused */
48 u32 tx_csum_info; /* Tx checksum info. */
49 u32 unused2[3]; /* unused */
53 #define STATUS_RX_EXT_MASK 0x1FFFFF
54 #define STATUS_RX_CSUM_MASK 0xFFFF
55 #define STATUS_RX_CSUM_OK 0x10000
56 #define STATUS_RX_CSUM_FR 0x20000
57 #define STATUS_RX_PROTO_TCP 0
58 #define STATUS_RX_PROTO_UDP 1
59 #define STATUS_RX_PROTO_ICMP 2
60 #define STATUS_RX_PROTO_OTHER 3
61 #define STATUS_RX_PROTO_MASK 3
62 #define STATUS_RX_PROTO_SHIFT 18
63 #define STATUS_FILTER_INDEX_MASK 0xFFFF
65 #define STATUS_TX_CSUM_START_MASK 0X7FFF
66 #define STATUS_TX_CSUM_START_SHIFT 16
67 #define STATUS_TX_CSUM_PROTO_UDP 0x8000
68 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF
69 #define STATUS_TX_CSUM_LV 0x80000000
72 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */
73 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */
74 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */
76 /* Rx/Tx common counter group */
77 struct bcmgenet_pkt_counters {
78 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */
79 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */
80 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */
81 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */
82 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */
83 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */
84 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */
85 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/
86 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/
87 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/
90 /* RSV, Receive Status Vector */
91 struct bcmgenet_rx_counters {
92 struct bcmgenet_pkt_counters pkt_cnt;
93 u32 pkt; /* RO (0x428) Received pkt count*/
94 u32 bytes; /* RO Received byte count */
95 u32 mca; /* RO # of Received multicast pkt */
96 u32 bca; /* RO # of Receive broadcast pkt */
97 u32 fcs; /* RO # of Received FCS error */
98 u32 cf; /* RO # of Received control frame pkt*/
99 u32 pf; /* RO # of Received pause frame pkt */
100 u32 uo; /* RO # of unknown op code pkt */
101 u32 aln; /* RO # of alignment error count */
102 u32 flr; /* RO # of frame length out of range count */
103 u32 cde; /* RO # of code error pkt */
104 u32 fcr; /* RO # of carrier sense error pkt */
105 u32 ovr; /* RO # of oversize pkt*/
106 u32 jbr; /* RO # of jabber count */
107 u32 mtue; /* RO # of MTU error pkt*/
108 u32 pok; /* RO # of Received good pkt */
109 u32 uc; /* RO # of unicast pkt */
110 u32 ppp; /* RO # of PPP pkt */
111 u32 rcrc; /* RO (0x470),# of CRC match pkt */
114 /* TSV, Transmit Status Vector */
115 struct bcmgenet_tx_counters {
116 struct bcmgenet_pkt_counters pkt_cnt;
117 u32 pkts; /* RO (0x4a8) Transmited pkt */
118 u32 mca; /* RO # of xmited multicast pkt */
119 u32 bca; /* RO # of xmited broadcast pkt */
120 u32 pf; /* RO # of xmited pause frame count */
121 u32 cf; /* RO # of xmited control frame count */
122 u32 fcs; /* RO # of xmited FCS error count */
123 u32 ovr; /* RO # of xmited oversize pkt */
124 u32 drf; /* RO # of xmited deferral pkt */
125 u32 edf; /* RO # of xmited Excessive deferral pkt*/
126 u32 scl; /* RO # of xmited single collision pkt */
127 u32 mcl; /* RO # of xmited multiple collision pkt*/
128 u32 lcl; /* RO # of xmited late collision pkt */
129 u32 ecl; /* RO # of xmited excessive collision pkt*/
130 u32 frg; /* RO # of xmited fragments pkt*/
131 u32 ncl; /* RO # of xmited total collision count */
132 u32 jbr; /* RO # of xmited jabber count*/
133 u32 bytes; /* RO # of xmited byte count */
134 u32 pok; /* RO # of xmited good pkt */
135 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */
138 struct bcmgenet_mib_counters {
139 struct bcmgenet_rx_counters rx;
140 struct bcmgenet_tx_counters tx;
143 u32 rx_runt_fcs_align;
148 u32 alloc_rx_buff_failed;
152 u32 tx_realloc_tsb_failed;
155 #define UMAC_MIB_START 0x400
157 #define UMAC_MDIO_CMD 0x614
158 #define MDIO_START_BUSY (1 << 29)
159 #define MDIO_READ_FAIL (1 << 28)
160 #define MDIO_RD (2 << 26)
161 #define MDIO_WR (1 << 26)
162 #define MDIO_PMD_SHIFT 21
163 #define MDIO_PMD_MASK 0x1F
164 #define MDIO_REG_SHIFT 16
165 #define MDIO_REG_MASK 0x1F
167 #define UMAC_RBUF_OVFL_CNT_V1 0x61C
168 #define RBUF_OVFL_CNT_V2 0x80
169 #define RBUF_OVFL_CNT_V3PLUS 0x94
171 #define UMAC_MPD_CTRL 0x620
172 #define MPD_EN (1 << 0)
173 #define MPD_PW_EN (1 << 27)
174 #define MPD_MSEQ_LEN_SHIFT 16
175 #define MPD_MSEQ_LEN_MASK 0xFF
177 #define UMAC_MPD_PW_MS 0x624
178 #define UMAC_MPD_PW_LS 0x628
179 #define UMAC_RBUF_ERR_CNT_V1 0x634
180 #define RBUF_ERR_CNT_V2 0x84
181 #define RBUF_ERR_CNT_V3PLUS 0x98
182 #define UMAC_MDF_ERR_CNT 0x638
183 #define UMAC_MDF_CTRL 0x650
184 #define UMAC_MDF_ADDR 0x654
185 #define UMAC_MIB_CTRL 0x580
186 #define MIB_RESET_RX (1 << 0)
187 #define MIB_RESET_RUNT (1 << 1)
188 #define MIB_RESET_TX (1 << 2)
190 #define RBUF_CTRL 0x00
191 #define RBUF_64B_EN (1 << 0)
192 #define RBUF_ALIGN_2B (1 << 1)
193 #define RBUF_BAD_DIS (1 << 2)
195 #define RBUF_STATUS 0x0C
196 #define RBUF_STATUS_WOL (1 << 0)
197 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1)
198 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2)
200 #define RBUF_CHK_CTRL 0x14
201 #define RBUF_RXCHK_EN (1 << 0)
202 #define RBUF_SKIP_FCS (1 << 4)
203 #define RBUF_L3_PARSE_DIS (1 << 5)
205 #define RBUF_ENERGY_CTRL 0x9c
206 #define RBUF_EEE_EN (1 << 0)
207 #define RBUF_PM_EN (1 << 1)
209 #define RBUF_TBUF_SIZE_CTRL 0xb4
211 #define RBUF_HFB_CTRL_V1 0x38
212 #define RBUF_HFB_FILTER_EN_SHIFT 16
213 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000
214 #define RBUF_HFB_EN (1 << 0)
215 #define RBUF_HFB_256B (1 << 1)
216 #define RBUF_ACPI_EN (1 << 2)
218 #define RBUF_HFB_LEN_V1 0x3C
219 #define RBUF_FLTR_LEN_MASK 0xFF
220 #define RBUF_FLTR_LEN_SHIFT 8
222 #define TBUF_CTRL 0x00
223 #define TBUF_64B_EN (1 << 0)
224 #define TBUF_BP_MC 0x0C
225 #define TBUF_ENERGY_CTRL 0x14
226 #define TBUF_EEE_EN (1 << 0)
227 #define TBUF_PM_EN (1 << 1)
229 #define TBUF_CTRL_V1 0x80
230 #define TBUF_BP_MC_V1 0xA0
232 #define HFB_CTRL 0x00
233 #define HFB_FLT_ENABLE_V3PLUS 0x04
234 #define HFB_FLT_LEN_V2 0x04
235 #define HFB_FLT_LEN_V3PLUS 0x1C
237 /* uniMac intrl2 registers */
238 #define INTRL2_CPU_STAT 0x00
239 #define INTRL2_CPU_SET 0x04
240 #define INTRL2_CPU_CLEAR 0x08
241 #define INTRL2_CPU_MASK_STATUS 0x0C
242 #define INTRL2_CPU_MASK_SET 0x10
243 #define INTRL2_CPU_MASK_CLEAR 0x14
245 /* INTRL2 instance 0 definitions */
246 #define UMAC_IRQ_SCB (1 << 0)
247 #define UMAC_IRQ_EPHY (1 << 1)
248 #define UMAC_IRQ_PHY_DET_R (1 << 2)
249 #define UMAC_IRQ_PHY_DET_F (1 << 3)
250 #define UMAC_IRQ_LINK_UP (1 << 4)
251 #define UMAC_IRQ_LINK_DOWN (1 << 5)
252 #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
253 #define UMAC_IRQ_UMAC (1 << 6)
254 #define UMAC_IRQ_UMAC_TSV (1 << 7)
255 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8)
256 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9)
257 #define UMAC_IRQ_HFB_SM (1 << 10)
258 #define UMAC_IRQ_HFB_MM (1 << 11)
259 #define UMAC_IRQ_MPD_R (1 << 12)
260 #define UMAC_IRQ_WAKE_EVENT (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM | \
262 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
263 #define UMAC_IRQ_RXDMA_PDONE (1 << 14)
264 #define UMAC_IRQ_RXDMA_BDONE (1 << 15)
265 #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE
266 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
267 #define UMAC_IRQ_TXDMA_PDONE (1 << 17)
268 #define UMAC_IRQ_TXDMA_BDONE (1 << 18)
269 #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE
271 /* Only valid for GENETv3+ */
272 #define UMAC_IRQ_MDIO_DONE (1 << 23)
273 #define UMAC_IRQ_MDIO_ERROR (1 << 24)
275 /* INTRL2 instance 1 definitions */
276 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
277 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF
278 #define UMAC_IRQ1_RX_INTR_SHIFT 16
280 /* Register block offsets */
281 #define GENET_SYS_OFF 0x0000
282 #define GENET_GR_BRIDGE_OFF 0x0040
283 #define GENET_EXT_OFF 0x0080
284 #define GENET_INTRL2_0_OFF 0x0200
285 #define GENET_INTRL2_1_OFF 0x0240
286 #define GENET_RBUF_OFF 0x0300
287 #define GENET_UMAC_OFF 0x0800
289 /* SYS block offsets and register definitions */
290 #define SYS_REV_CTRL 0x00
291 #define SYS_PORT_CTRL 0x04
292 #define PORT_MODE_INT_EPHY 0
293 #define PORT_MODE_INT_GPHY 1
294 #define PORT_MODE_EXT_EPHY 2
295 #define PORT_MODE_EXT_GPHY 3
296 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4))
297 #define PORT_MODE_EXT_RVMII_50 4
298 #define LED_ACT_SOURCE_MAC (1 << 9)
300 #define SYS_RBUF_FLUSH_CTRL 0x08
301 #define SYS_TBUF_FLUSH_CTRL 0x0C
302 #define RBUF_FLUSH_CTRL_V1 0x04
304 /* Ext block register offsets and definitions */
305 #define EXT_EXT_PWR_MGMT 0x00
306 #define EXT_PWR_DOWN_BIAS (1 << 0)
307 #define EXT_PWR_DOWN_DLL (1 << 1)
308 #define EXT_PWR_DOWN_PHY (1 << 2)
309 #define EXT_PWR_DN_EN_LD (1 << 3)
310 #define EXT_ENERGY_DET (1 << 4)
311 #define EXT_IDDQ_FROM_PHY (1 << 5)
312 #define EXT_IDDQ_GLBL_PWR (1 << 7)
313 #define EXT_PHY_RESET (1 << 8)
314 #define EXT_ENERGY_DET_MASK (1 << 12)
315 #define EXT_PWR_DOWN_PHY_TX (1 << 16)
316 #define EXT_PWR_DOWN_PHY_RX (1 << 17)
317 #define EXT_PWR_DOWN_PHY_SD (1 << 18)
318 #define EXT_PWR_DOWN_PHY_RD (1 << 19)
319 #define EXT_PWR_DOWN_PHY_EN (1 << 20)
321 #define EXT_RGMII_OOB_CTRL 0x0C
322 #define RGMII_MODE_EN_V123 (1 << 0)
323 #define RGMII_LINK (1 << 4)
324 #define OOB_DISABLE (1 << 5)
325 #define RGMII_MODE_EN (1 << 6)
326 #define ID_MODE_DIS (1 << 16)
328 #define EXT_GPHY_CTRL 0x1C
329 #define EXT_CFG_IDDQ_BIAS (1 << 0)
330 #define EXT_CFG_PWR_DOWN (1 << 1)
331 #define EXT_CK25_DIS (1 << 4)
332 #define EXT_CFG_IDDQ_GLOBAL_PWR (1 << 3)
333 #define EXT_GPHY_RESET (1 << 5)
336 #define DMA_RING_SIZE (0x40)
337 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1))
339 /* DMA registers common definitions */
340 #define DMA_RW_POINTER_MASK 0x1FF
341 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF
342 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16
343 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF
344 #define DMA_BUFFER_DONE_CNT_SHIFT 16
345 #define DMA_P_INDEX_MASK 0xFFFF
346 #define DMA_C_INDEX_MASK 0xFFFF
348 /* DMA ring size register */
349 #define DMA_RING_SIZE_MASK 0xFFFF
350 #define DMA_RING_SIZE_SHIFT 16
351 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
353 /* DMA interrupt threshold register */
354 #define DMA_INTR_THRESHOLD_MASK 0x01FF
356 /* DMA XON/XOFF register */
357 #define DMA_XON_THREHOLD_MASK 0xFFFF
358 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF
359 #define DMA_XOFF_THRESHOLD_SHIFT 16
361 /* DMA flow period register */
362 #define DMA_FLOW_PERIOD_MASK 0xFFFF
363 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF
364 #define DMA_MAX_PKT_SIZE_SHIFT 16
367 /* DMA control register */
368 #define DMA_EN (1 << 0)
369 #define DMA_RING_BUF_EN_SHIFT 0x01
370 #define DMA_RING_BUF_EN_MASK 0xFFFF
371 #define DMA_TSB_SWAP_EN (1 << 20)
373 /* DMA status register */
374 #define DMA_DISABLED (1 << 0)
375 #define DMA_DESC_RAM_INIT_BUSY (1 << 1)
377 /* DMA SCB burst size register */
378 #define DMA_SCB_BURST_SIZE_MASK 0x1F
380 /* DMA activity vector register */
381 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF
383 /* DMA backpressure mask register */
384 #define DMA_BACKPRESSURE_MASK 0x1FFFF
385 #define DMA_PFC_ENABLE (1 << 31)
387 /* DMA backpressure status register */
388 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF
390 /* DMA override register */
391 #define DMA_LITTLE_ENDIAN_MODE (1 << 0)
392 #define DMA_REGISTER_MODE (1 << 1)
394 /* DMA timeout register */
395 #define DMA_TIMEOUT_MASK 0xFFFF
396 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */
398 /* TDMA rate limiting control register */
399 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF
401 /* TDMA arbitration control register */
402 #define DMA_ARBITER_MODE_MASK 0x03
403 #define DMA_RING_BUF_PRIORITY_MASK 0x1F
404 #define DMA_RING_BUF_PRIORITY_SHIFT 5
405 #define DMA_PRIO_REG_INDEX(q) ((q) / 6)
406 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
407 #define DMA_RATE_ADJ_MASK 0xFF
409 /* Tx/Rx Dma Descriptor common bits*/
410 #define DMA_BUFLENGTH_MASK 0x0fff
411 #define DMA_BUFLENGTH_SHIFT 16
412 #define DMA_OWN 0x8000
413 #define DMA_EOP 0x4000
414 #define DMA_SOP 0x2000
415 #define DMA_WRAP 0x1000
416 /* Tx specific Dma descriptor bits */
417 #define DMA_TX_UNDERRUN 0x0200
418 #define DMA_TX_APPEND_CRC 0x0040
419 #define DMA_TX_OW_CRC 0x0020
420 #define DMA_TX_DO_CSUM 0x0010
421 #define DMA_TX_QTAG_SHIFT 7
423 /* Rx Specific Dma descriptor bits */
424 #define DMA_RX_CHK_V3PLUS 0x8000
425 #define DMA_RX_CHK_V12 0x1000
426 #define DMA_RX_BRDCAST 0x0040
427 #define DMA_RX_MULT 0x0020
428 #define DMA_RX_LG 0x0010
429 #define DMA_RX_NO 0x0008
430 #define DMA_RX_RXER 0x0004
431 #define DMA_RX_CRC_ERROR 0x0002
432 #define DMA_RX_OV 0x0001
433 #define DMA_RX_FI_MASK 0x001F
434 #define DMA_RX_FI_SHIFT 0x0007
435 #define DMA_DESC_ALLOC_MASK 0x00FF
437 #define DMA_ARBITER_RR 0x00
438 #define DMA_ARBITER_WRR 0x01
439 #define DMA_ARBITER_SP 0x02
443 void __iomem *bd_addr;
444 DEFINE_DMA_UNMAP_ADDR(dma_addr);
445 DEFINE_DMA_UNMAP_LEN(dma_len);
448 /* power management mode */
449 enum bcmgenet_power_mode {
450 GENET_POWER_CABLE_SENSE = 0,
452 GENET_POWER_WOL_MAGIC,
455 struct bcmgenet_priv;
457 /* We support both runtime GENET detection and compile-time
458 * to optimize code-paths for a given hardware
460 enum bcmgenet_version {
468 #define GENET_IS_V1(p) ((p)->version == GENET_V1)
469 #define GENET_IS_V2(p) ((p)->version == GENET_V2)
470 #define GENET_IS_V3(p) ((p)->version == GENET_V3)
471 #define GENET_IS_V4(p) ((p)->version == GENET_V4)
472 #define GENET_IS_V5(p) ((p)->version == GENET_V5)
475 #define GENET_HAS_40BITS (1 << 0)
476 #define GENET_HAS_EXT (1 << 1)
477 #define GENET_HAS_MDIO_INTR (1 << 2)
478 #define GENET_HAS_MOCA_LINK_DET (1 << 3)
480 /* BCMGENET hardware parameters, keep this structure nicely aligned
481 * since it is going to be used in hot paths
483 struct bcmgenet_hw_params {
502 struct bcmgenet_skb_cb {
503 struct enet_cb *first_cb; /* First control block of SKB */
504 struct enet_cb *last_cb; /* Last control block of SKB */
505 unsigned int bytes_sent; /* bytes on the wire (no TSB) */
508 #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb))
510 struct bcmgenet_tx_ring {
511 spinlock_t lock; /* ring lock */
512 struct napi_struct napi; /* NAPI per tx queue */
513 unsigned long packets;
515 unsigned int index; /* ring index */
516 unsigned int queue; /* queue index */
517 struct enet_cb *cbs; /* tx ring buffer control block*/
518 unsigned int size; /* size of each tx ring */
519 unsigned int clean_ptr; /* Tx ring clean pointer */
520 unsigned int c_index; /* last consumer index of each ring*/
521 unsigned int free_bds; /* # of free bds for each ring */
522 unsigned int write_ptr; /* Tx ring write pointer SW copy */
523 unsigned int prod_index; /* Tx ring producer index SW copy */
524 unsigned int cb_ptr; /* Tx ring initial CB ptr */
525 unsigned int end_ptr; /* Tx ring end CB ptr */
526 void (*int_enable)(struct bcmgenet_tx_ring *);
527 void (*int_disable)(struct bcmgenet_tx_ring *);
528 struct bcmgenet_priv *priv;
531 struct bcmgenet_net_dim {
534 unsigned long packets;
539 struct bcmgenet_rx_ring {
540 struct napi_struct napi; /* Rx NAPI struct */
542 unsigned long packets;
543 unsigned long errors;
544 unsigned long dropped;
545 unsigned int index; /* Rx ring index */
546 struct enet_cb *cbs; /* Rx ring buffer control block */
547 unsigned int size; /* Rx ring size */
548 unsigned int c_index; /* Rx last consumer index */
549 unsigned int read_ptr; /* Rx ring read pointer */
550 unsigned int cb_ptr; /* Rx ring initial CB ptr */
551 unsigned int end_ptr; /* Rx ring end CB ptr */
552 unsigned int old_discards;
553 struct bcmgenet_net_dim dim;
554 u32 rx_max_coalesced_frames;
555 u32 rx_coalesce_usecs;
556 void (*int_enable)(struct bcmgenet_rx_ring *);
557 void (*int_disable)(struct bcmgenet_rx_ring *);
558 struct bcmgenet_priv *priv;
561 enum bcmgenet_rxnfc_state {
562 BCMGENET_RXNFC_STATE_UNUSED = 0,
563 BCMGENET_RXNFC_STATE_DISABLED,
564 BCMGENET_RXNFC_STATE_ENABLED
567 struct bcmgenet_rxnfc_rule {
568 struct list_head list;
569 struct ethtool_rx_flow_spec fs;
570 enum bcmgenet_rxnfc_state state;
574 struct bcmgenet_priv {
576 enum bcmgenet_version version;
577 struct net_device *dev;
579 /* transmit variables */
580 void __iomem *tx_bds;
581 struct enet_cb *tx_cbs;
582 unsigned int num_tx_bds;
584 struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1];
586 /* receive variables */
587 void __iomem *rx_bds;
588 struct enet_cb *rx_cbs;
589 unsigned int num_rx_bds;
590 unsigned int rx_buf_len;
591 struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES];
592 struct list_head rxnfc_list;
594 struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1];
596 /* other misc variables */
597 struct bcmgenet_hw_params *hw_params;
598 unsigned autoneg_pause:1;
602 /* MDIO bus variables */
603 wait_queue_head_t wq;
605 struct device_node *phy_dn;
606 struct device_node *mdio_dn;
607 struct mii_bus *mii_bus;
610 bool clk_eee_enabled;
612 /* PHY device variables */
613 phy_interface_t phy_interface;
618 /* Interrupt variables */
619 struct work_struct bcmgenet_irq_work;
623 bool wol_irq_disabled;
627 unsigned int irq0_stat;
629 /* HW descriptors/checksum variables */
632 u32 dma_max_burst_length;
637 struct platform_device *pdev;
638 struct platform_device *mii_pdev;
643 u8 sopass[SOPASS_MAX];
646 struct bcmgenet_mib_counters mib;
648 struct ethtool_eee eee;
651 #define GENET_IO_MACRO(name, offset) \
652 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \
655 /* MIPS chips strapped for BE will automagically configure the \
656 * peripheral registers for CPU-native byte order. \
658 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
659 return __raw_readl(priv->base + offset + off); \
661 return readl_relaxed(priv->base + offset + off); \
663 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
666 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
667 __raw_writel(val, priv->base + offset + off); \
669 writel_relaxed(val, priv->base + offset + off); \
672 GENET_IO_MACRO(ext, GENET_EXT_OFF);
673 GENET_IO_MACRO(umac, GENET_UMAC_OFF);
674 GENET_IO_MACRO(sys, GENET_SYS_OFF);
676 /* interrupt l2 registers accessors */
677 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
678 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
680 /* HFB register accessors */
681 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
683 /* GENET v2+ HFB control and filter len helpers */
684 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
686 /* RBUF register accessors */
687 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
690 int bcmgenet_mii_init(struct net_device *dev);
691 int bcmgenet_mii_config(struct net_device *dev, bool init);
692 int bcmgenet_mii_probe(struct net_device *dev);
693 void bcmgenet_mii_exit(struct net_device *dev);
694 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx);
695 void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
696 void bcmgenet_mii_setup(struct net_device *dev);
698 /* Wake-on-LAN routines */
699 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
700 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
701 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
702 enum bcmgenet_power_mode mode);
703 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
704 enum bcmgenet_power_mode mode);
706 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
707 bool tx_lpi_enabled);
709 #endif /* __BCMGENET_H__ */