drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 /* Forward declarations */
  76 static void bcmgenet_set_rx_mode(struct net_device *dev);
  77
  78 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  79 {
  80         /* MIPS chips strapped for BE will automagically configure the
  81          * peripheral registers for CPU-native byte order.
  82          */
  83         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  84                 __raw_writel(value, offset);
  85         else
  86                 writel_relaxed(value, offset);
  87 }
  88
  89 static inline u32 bcmgenet_readl(void __iomem *offset)
  90 {
  91         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  92                 return __raw_readl(offset);
  93         else
  94                 return readl_relaxed(offset);
  95 }
  96
  97 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  98                                              void __iomem *d, u32 value)
  99 {
 100         bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
 101 }
 102
 103 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
 104                                             void __iomem *d)
 105 {
 106         return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
 107 }
 108
 109 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
 110                                     void __iomem *d,
 111                                     dma_addr_t addr)
 112 {
 113         bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 114
 115         /* Register writes to GISB bus can take couple hundred nanoseconds
 116          * and are done for each packet, save these expensive writes unless
 117          * the platform is explicitly configured for 64-bits/LPAE.
 118          */
 119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 120         if (priv->hw_params->flags & GENET_HAS_40BITS)
 121                 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 122 #endif
 123 }
 124
 125 /* Combined address + length/status setter */
 126 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 127                                void __iomem *d, dma_addr_t addr, u32 val)
 128 {
 129         dmadesc_set_addr(priv, d, addr);
 130         dmadesc_set_length_status(priv, d, val);
 131 }
 132
 133 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 134                                           void __iomem *d)
 135 {
 136         dma_addr_t addr;
 137
 138         addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
 139
 140         /* Register writes to GISB bus can take couple hundred nanoseconds
 141          * and are done for each packet, save these expensive writes unless
 142          * the platform is explicitly configured for 64-bits/LPAE.
 143          */
 144 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 145         if (priv->hw_params->flags & GENET_HAS_40BITS)
 146                 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 147 #endif
 148         return addr;
 149 }
 150
 151 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 152
 153 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 154                                 NETIF_MSG_LINK)
 155
 156 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 157 {
 158         if (GENET_IS_V1(priv))
 159                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 160         else
 161                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 162 }
 163
 164 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 165 {
 166         if (GENET_IS_V1(priv))
 167                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 168         else
 169                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 170 }
 171
 172 /* These macros are defined to deal with register map change
 173  * between GENET1.1 and GENET2. Only those currently being used
 174  * by driver are defined.
 175  */
 176 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 177 {
 178         if (GENET_IS_V1(priv))
 179                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 180         else
 181                 return bcmgenet_readl(priv->base +
 182                                       priv->hw_params->tbuf_offset + TBUF_CTRL);
 183 }
 184
 185 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 186 {
 187         if (GENET_IS_V1(priv))
 188                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 189         else
 190                 bcmgenet_writel(val, priv->base +
 191                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 192 }
 193
 194 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 195 {
 196         if (GENET_IS_V1(priv))
 197                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 198         else
 199                 return bcmgenet_readl(priv->base +
 200                                       priv->hw_params->tbuf_offset + TBUF_BP_MC);
 201 }
 202
 203 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 204 {
 205         if (GENET_IS_V1(priv))
 206                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 207         else
 208                 bcmgenet_writel(val, priv->base +
 209                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 210 }
 211
 212 /* RX/TX DMA register accessors */
 213 enum dma_reg {
 214         DMA_RING_CFG = 0,
 215         DMA_CTRL,
 216         DMA_STATUS,
 217         DMA_SCB_BURST_SIZE,
 218         DMA_ARB_CTRL,
 219         DMA_PRIORITY_0,
 220         DMA_PRIORITY_1,
 221         DMA_PRIORITY_2,
 222         DMA_INDEX2RING_0,
 223         DMA_INDEX2RING_1,
 224         DMA_INDEX2RING_2,
 225         DMA_INDEX2RING_3,
 226         DMA_INDEX2RING_4,
 227         DMA_INDEX2RING_5,
 228         DMA_INDEX2RING_6,
 229         DMA_INDEX2RING_7,
 230         DMA_RING0_TIMEOUT,
 231         DMA_RING1_TIMEOUT,
 232         DMA_RING2_TIMEOUT,
 233         DMA_RING3_TIMEOUT,
 234         DMA_RING4_TIMEOUT,
 235         DMA_RING5_TIMEOUT,
 236         DMA_RING6_TIMEOUT,
 237         DMA_RING7_TIMEOUT,
 238         DMA_RING8_TIMEOUT,
 239         DMA_RING9_TIMEOUT,
 240         DMA_RING10_TIMEOUT,
 241         DMA_RING11_TIMEOUT,
 242         DMA_RING12_TIMEOUT,
 243         DMA_RING13_TIMEOUT,
 244         DMA_RING14_TIMEOUT,
 245         DMA_RING15_TIMEOUT,
 246         DMA_RING16_TIMEOUT,
 247 };
 248
 249 static const u8 bcmgenet_dma_regs_v3plus[] = {
 250         [DMA_RING_CFG]          = 0x00,
 251         [DMA_CTRL]              = 0x04,
 252         [DMA_STATUS]            = 0x08,
 253         [DMA_SCB_BURST_SIZE]    = 0x0C,
 254         [DMA_ARB_CTRL]          = 0x2C,
 255         [DMA_PRIORITY_0]        = 0x30,
 256         [DMA_PRIORITY_1]        = 0x34,
 257         [DMA_PRIORITY_2]        = 0x38,
 258         [DMA_RING0_TIMEOUT]     = 0x2C,
 259         [DMA_RING1_TIMEOUT]     = 0x30,
 260         [DMA_RING2_TIMEOUT]     = 0x34,
 261         [DMA_RING3_TIMEOUT]     = 0x38,
 262         [DMA_RING4_TIMEOUT]     = 0x3c,
 263         [DMA_RING5_TIMEOUT]     = 0x40,
 264         [DMA_RING6_TIMEOUT]     = 0x44,
 265         [DMA_RING7_TIMEOUT]     = 0x48,
 266         [DMA_RING8_TIMEOUT]     = 0x4c,
 267         [DMA_RING9_TIMEOUT]     = 0x50,
 268         [DMA_RING10_TIMEOUT]    = 0x54,
 269         [DMA_RING11_TIMEOUT]    = 0x58,
 270         [DMA_RING12_TIMEOUT]    = 0x5c,
 271         [DMA_RING13_TIMEOUT]    = 0x60,
 272         [DMA_RING14_TIMEOUT]    = 0x64,
 273         [DMA_RING15_TIMEOUT]    = 0x68,
 274         [DMA_RING16_TIMEOUT]    = 0x6C,
 275         [DMA_INDEX2RING_0]      = 0x70,
 276         [DMA_INDEX2RING_1]      = 0x74,
 277         [DMA_INDEX2RING_2]      = 0x78,
 278         [DMA_INDEX2RING_3]      = 0x7C,
 279         [DMA_INDEX2RING_4]      = 0x80,
 280         [DMA_INDEX2RING_5]      = 0x84,
 281         [DMA_INDEX2RING_6]      = 0x88,
 282         [DMA_INDEX2RING_7]      = 0x8C,
 283 };
 284
 285 static const u8 bcmgenet_dma_regs_v2[] = {
 286         [DMA_RING_CFG]          = 0x00,
 287         [DMA_CTRL]              = 0x04,
 288         [DMA_STATUS]            = 0x08,
 289         [DMA_SCB_BURST_SIZE]    = 0x0C,
 290         [DMA_ARB_CTRL]          = 0x30,
 291         [DMA_PRIORITY_0]        = 0x34,
 292         [DMA_PRIORITY_1]        = 0x38,
 293         [DMA_PRIORITY_2]        = 0x3C,
 294         [DMA_RING0_TIMEOUT]     = 0x2C,
 295         [DMA_RING1_TIMEOUT]     = 0x30,
 296         [DMA_RING2_TIMEOUT]     = 0x34,
 297         [DMA_RING3_TIMEOUT]     = 0x38,
 298         [DMA_RING4_TIMEOUT]     = 0x3c,
 299         [DMA_RING5_TIMEOUT]     = 0x40,
 300         [DMA_RING6_TIMEOUT]     = 0x44,
 301         [DMA_RING7_TIMEOUT]     = 0x48,
 302         [DMA_RING8_TIMEOUT]     = 0x4c,
 303         [DMA_RING9_TIMEOUT]     = 0x50,
 304         [DMA_RING10_TIMEOUT]    = 0x54,
 305         [DMA_RING11_TIMEOUT]    = 0x58,
 306         [DMA_RING12_TIMEOUT]    = 0x5c,
 307         [DMA_RING13_TIMEOUT]    = 0x60,
 308         [DMA_RING14_TIMEOUT]    = 0x64,
 309         [DMA_RING15_TIMEOUT]    = 0x68,
 310         [DMA_RING16_TIMEOUT]    = 0x6C,
 311 };
 312
 313 static const u8 bcmgenet_dma_regs_v1[] = {
 314         [DMA_CTRL]              = 0x00,
 315         [DMA_STATUS]            = 0x04,
 316         [DMA_SCB_BURST_SIZE]    = 0x0C,
 317         [DMA_ARB_CTRL]          = 0x30,
 318         [DMA_PRIORITY_0]        = 0x34,
 319         [DMA_PRIORITY_1]        = 0x38,
 320         [DMA_PRIORITY_2]        = 0x3C,
 321         [DMA_RING0_TIMEOUT]     = 0x2C,
 322         [DMA_RING1_TIMEOUT]     = 0x30,
 323         [DMA_RING2_TIMEOUT]     = 0x34,
 324         [DMA_RING3_TIMEOUT]     = 0x38,
 325         [DMA_RING4_TIMEOUT]     = 0x3c,
 326         [DMA_RING5_TIMEOUT]     = 0x40,
 327         [DMA_RING6_TIMEOUT]     = 0x44,
 328         [DMA_RING7_TIMEOUT]     = 0x48,
 329         [DMA_RING8_TIMEOUT]     = 0x4c,
 330         [DMA_RING9_TIMEOUT]     = 0x50,
 331         [DMA_RING10_TIMEOUT]    = 0x54,
 332         [DMA_RING11_TIMEOUT]    = 0x58,
 333         [DMA_RING12_TIMEOUT]    = 0x5c,
 334         [DMA_RING13_TIMEOUT]    = 0x60,
 335         [DMA_RING14_TIMEOUT]    = 0x64,
 336         [DMA_RING15_TIMEOUT]    = 0x68,
 337         [DMA_RING16_TIMEOUT]    = 0x6C,
 338 };
 339
 340 /* Set at runtime once bcmgenet version is known */
 341 static const u8 *bcmgenet_dma_regs;
 342
 343 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 344 {
 345         return netdev_priv(dev_get_drvdata(dev));
 346 }
 347
 348 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 349                                       enum dma_reg r)
 350 {
 351         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 352                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 353 }
 354
 355 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 356                                         u32 val, enum dma_reg r)
 357 {
 358         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 359                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 360 }
 361
 362 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 363                                       enum dma_reg r)
 364 {
 365         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 366                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 367 }
 368
 369 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 370                                         u32 val, enum dma_reg r)
 371 {
 372         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 373                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 374 }
 375
 376 /* RDMA/TDMA ring registers and accessors
 377  * we merge the common fields and just prefix with T/D the registers
 378  * having different meaning depending on the direction
 379  */
 380 enum dma_ring_reg {
 381         TDMA_READ_PTR = 0,
 382         RDMA_WRITE_PTR = TDMA_READ_PTR,
 383         TDMA_READ_PTR_HI,
 384         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 385         TDMA_CONS_INDEX,
 386         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 387         TDMA_PROD_INDEX,
 388         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 389         DMA_RING_BUF_SIZE,
 390         DMA_START_ADDR,
 391         DMA_START_ADDR_HI,
 392         DMA_END_ADDR,
 393         DMA_END_ADDR_HI,
 394         DMA_MBUF_DONE_THRESH,
 395         TDMA_FLOW_PERIOD,
 396         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 397         TDMA_WRITE_PTR,
 398         RDMA_READ_PTR = TDMA_WRITE_PTR,
 399         TDMA_WRITE_PTR_HI,
 400         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 401 };
 402
 403 /* GENET v4 supports 40-bits pointer addressing
 404  * for obvious reasons the LO and HI word parts
 405  * are contiguous, but this offsets the other
 406  * registers.
 407  */
 408 static const u8 genet_dma_ring_regs_v4[] = {
 409         [TDMA_READ_PTR]                 = 0x00,
 410         [TDMA_READ_PTR_HI]              = 0x04,
 411         [TDMA_CONS_INDEX]               = 0x08,
 412         [TDMA_PROD_INDEX]               = 0x0C,
 413         [DMA_RING_BUF_SIZE]             = 0x10,
 414         [DMA_START_ADDR]                = 0x14,
 415         [DMA_START_ADDR_HI]             = 0x18,
 416         [DMA_END_ADDR]                  = 0x1C,
 417         [DMA_END_ADDR_HI]               = 0x20,
 418         [DMA_MBUF_DONE_THRESH]          = 0x24,
 419         [TDMA_FLOW_PERIOD]              = 0x28,
 420         [TDMA_WRITE_PTR]                = 0x2C,
 421         [TDMA_WRITE_PTR_HI]             = 0x30,
 422 };
 423
 424 static const u8 genet_dma_ring_regs_v123[] = {
 425         [TDMA_READ_PTR]                 = 0x00,
 426         [TDMA_CONS_INDEX]               = 0x04,
 427         [TDMA_PROD_INDEX]               = 0x08,
 428         [DMA_RING_BUF_SIZE]             = 0x0C,
 429         [DMA_START_ADDR]                = 0x10,
 430         [DMA_END_ADDR]                  = 0x14,
 431         [DMA_MBUF_DONE_THRESH]          = 0x18,
 432         [TDMA_FLOW_PERIOD]              = 0x1C,
 433         [TDMA_WRITE_PTR]                = 0x20,
 434 };
 435
 436 /* Set at runtime once GENET version is known */
 437 static const u8 *genet_dma_ring_regs;
 438
 439 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 440                                            unsigned int ring,
 441                                            enum dma_ring_reg r)
 442 {
 443         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 444                               (DMA_RING_SIZE * ring) +
 445                               genet_dma_ring_regs[r]);
 446 }
 447
 448 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 449                                              unsigned int ring, u32 val,
 450                                              enum dma_ring_reg r)
 451 {
 452         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 453                         (DMA_RING_SIZE * ring) +
 454                         genet_dma_ring_regs[r]);
 455 }
 456
 457 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 458                                            unsigned int ring,
 459                                            enum dma_ring_reg r)
 460 {
 461         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 462                               (DMA_RING_SIZE * ring) +
 463                               genet_dma_ring_regs[r]);
 464 }
 465
 466 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 467                                              unsigned int ring, u32 val,
 468                                              enum dma_ring_reg r)
 469 {
 470         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 471                         (DMA_RING_SIZE * ring) +
 472                         genet_dma_ring_regs[r]);
 473 }
 474
 475 static int bcmgenet_begin(struct net_device *dev)
 476 {
 477         struct bcmgenet_priv *priv = netdev_priv(dev);
 478
 479         /* Turn on the clock */
 480         return clk_prepare_enable(priv->clk);
 481 }
 482
 483 static void bcmgenet_complete(struct net_device *dev)
 484 {
 485         struct bcmgenet_priv *priv = netdev_priv(dev);
 486
 487         /* Turn off the clock */
 488         clk_disable_unprepare(priv->clk);
 489 }
 490
 491 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 492                                        struct ethtool_link_ksettings *cmd)
 493 {
 494         struct bcmgenet_priv *priv = netdev_priv(dev);
 495
 496         if (!netif_running(dev))
 497                 return -EINVAL;
 498
 499         if (!priv->phydev)
 500                 return -ENODEV;
 501
 502         phy_ethtool_ksettings_get(priv->phydev, cmd);
 503
 504         return 0;
 505 }
 506
 507 static int bcmgenet_set_link_ksettings(struct net_device *dev,
 508                                        const struct ethtool_link_ksettings *cmd)
 509 {
 510         struct bcmgenet_priv *priv = netdev_priv(dev);
 511
 512         if (!netif_running(dev))
 513                 return -EINVAL;
 514
 515         if (!priv->phydev)
 516                 return -ENODEV;
 517
 518         return phy_ethtool_ksettings_set(priv->phydev, cmd);
 519 }
 520
 521 static int bcmgenet_set_rx_csum(struct net_device *dev,
 522                                 netdev_features_t wanted)
 523 {
 524         struct bcmgenet_priv *priv = netdev_priv(dev);
 525         u32 rbuf_chk_ctrl;
 526         bool rx_csum_en;
 527
 528         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 529
 530         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 531
 532         /* enable rx checksumming */
 533         if (rx_csum_en)
 534                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 535         else
 536                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 537         priv->desc_rxchk_en = rx_csum_en;
 538
 539         /* If UniMAC forwards CRC, we need to skip over it to get
 540          * a valid CHK bit to be set in the per-packet status word
 541         */
 542         if (rx_csum_en && priv->crc_fwd_en)
 543                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 544         else
 545                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 546
 547         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 548
 549         return 0;
 550 }
 551
 552 static int bcmgenet_set_tx_csum(struct net_device *dev,
 553                                 netdev_features_t wanted)
 554 {
 555         struct bcmgenet_priv *priv = netdev_priv(dev);
 556         bool desc_64b_en;
 557         u32 tbuf_ctrl, rbuf_ctrl;
 558
 559         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 560         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 561
 562         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 563
 564         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 565         if (desc_64b_en) {
 566                 tbuf_ctrl |= RBUF_64B_EN;
 567                 rbuf_ctrl |= RBUF_64B_EN;
 568         } else {
 569                 tbuf_ctrl &= ~RBUF_64B_EN;
 570                 rbuf_ctrl &= ~RBUF_64B_EN;
 571         }
 572         priv->desc_64b_en = desc_64b_en;
 573
 574         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 575         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 576
 577         return 0;
 578 }
 579
 580 static int bcmgenet_set_features(struct net_device *dev,
 581                                  netdev_features_t features)
 582 {
 583         netdev_features_t changed = features ^ dev->features;
 584         netdev_features_t wanted = dev->wanted_features;
 585         int ret = 0;
 586
 587         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 588                 ret = bcmgenet_set_tx_csum(dev, wanted);
 589         if (changed & (NETIF_F_RXCSUM))
 590                 ret = bcmgenet_set_rx_csum(dev, wanted);
 591
 592         return ret;
 593 }
 594
 595 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 596 {
 597         struct bcmgenet_priv *priv = netdev_priv(dev);
 598
 599         return priv->msg_enable;
 600 }
 601
 602 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 603 {
 604         struct bcmgenet_priv *priv = netdev_priv(dev);
 605
 606         priv->msg_enable = level;
 607 }
 608
 609 static int bcmgenet_get_coalesce(struct net_device *dev,
 610                                  struct ethtool_coalesce *ec)
 611 {
 612         struct bcmgenet_priv *priv = netdev_priv(dev);
 613
 614         ec->tx_max_coalesced_frames =
 615                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 616                                          DMA_MBUF_DONE_THRESH);
 617         ec->rx_max_coalesced_frames =
 618                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 619                                          DMA_MBUF_DONE_THRESH);
 620         ec->rx_coalesce_usecs =
 621                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 622
 623         return 0;
 624 }
 625
 626 static int bcmgenet_set_coalesce(struct net_device *dev,
 627                                  struct ethtool_coalesce *ec)
 628 {
 629         struct bcmgenet_priv *priv = netdev_priv(dev);
 630         unsigned int i;
 631         u32 reg;
 632
 633         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 634          * divided by 1024, which yields roughly 8.192us, our maximum value
 635          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 636          */
 637         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 638             ec->tx_max_coalesced_frames == 0 ||
 639             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 640             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 641                 return -EINVAL;
 642
 643         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 644                 return -EINVAL;
 645
 646         /* GENET TDMA hardware does not support a configurable timeout, but will
 647          * always generate an interrupt either after MBDONE packets have been
 648          * transmitted, or when the ring is empty.
 649          */
 650         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 651             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 652                 return -EOPNOTSUPP;
 653
 654         /* Program all TX queues with the same values, as there is no
 655          * ethtool knob to do coalescing on a per-queue basis
 656          */
 657         for (i = 0; i < priv->hw_params->tx_queues; i++)
 658                 bcmgenet_tdma_ring_writel(priv, i,
 659                                           ec->tx_max_coalesced_frames,
 660                                           DMA_MBUF_DONE_THRESH);
 661         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 662                                   ec->tx_max_coalesced_frames,
 663                                   DMA_MBUF_DONE_THRESH);
 664
 665         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 666                 bcmgenet_rdma_ring_writel(priv, i,
 667                                           ec->rx_max_coalesced_frames,
 668                                           DMA_MBUF_DONE_THRESH);
 669
 670                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 671                 reg &= ~DMA_TIMEOUT_MASK;
 672                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 673                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 674         }
 675
 676         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 677                                   ec->rx_max_coalesced_frames,
 678                                   DMA_MBUF_DONE_THRESH);
 679
 680         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 681         reg &= ~DMA_TIMEOUT_MASK;
 682         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 683         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 684
 685         return 0;
 686 }
 687
 688 /* standard ethtool support functions. */
 689 enum bcmgenet_stat_type {
 690         BCMGENET_STAT_NETDEV = -1,
 691         BCMGENET_STAT_MIB_RX,
 692         BCMGENET_STAT_MIB_TX,
 693         BCMGENET_STAT_RUNT,
 694         BCMGENET_STAT_MISC,
 695         BCMGENET_STAT_SOFT,
 696 };
 697
 698 struct bcmgenet_stats {
 699         char stat_string[ETH_GSTRING_LEN];
 700         int stat_sizeof;
 701         int stat_offset;
 702         enum bcmgenet_stat_type type;
 703         /* reg offset from UMAC base for misc counters */
 704         u16 reg_offset;
 705 };
 706
 707 #define STAT_NETDEV(m) { \
 708         .stat_string = __stringify(m), \
 709         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 710         .stat_offset = offsetof(struct net_device_stats, m), \
 711         .type = BCMGENET_STAT_NETDEV, \
 712 }
 713
 714 #define STAT_GENET_MIB(str, m, _type) { \
 715         .stat_string = str, \
 716         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 717         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 718         .type = _type, \
 719 }
 720
 721 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 722 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 723 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 724 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 725
 726 #define STAT_GENET_MISC(str, m, offset) { \
 727         .stat_string = str, \
 728         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 729         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 730         .type = BCMGENET_STAT_MISC, \
 731         .reg_offset = offset, \
 732 }
 733
 734 #define STAT_GENET_Q(num) \
 735         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
 736                         tx_rings[num].packets), \
 737         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
 738                         tx_rings[num].bytes), \
 739         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
 740                         rx_rings[num].bytes),    \
 741         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
 742                         rx_rings[num].packets), \
 743         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
 744                         rx_rings[num].errors), \
 745         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
 746                         rx_rings[num].dropped)
 747
 748 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 749  * between the end of TX stats and the beginning of the RX RUNT
 750  */
 751 #define BCMGENET_STAT_OFFSET    0xc
 752
 753 /* Hardware counters must be kept in sync because the order/offset
 754  * is important here (order in structure declaration = order in hardware)
 755  */
 756 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 757         /* general stats */
 758         STAT_NETDEV(rx_packets),
 759         STAT_NETDEV(tx_packets),
 760         STAT_NETDEV(rx_bytes),
 761         STAT_NETDEV(tx_bytes),
 762         STAT_NETDEV(rx_errors),
 763         STAT_NETDEV(tx_errors),
 764         STAT_NETDEV(rx_dropped),
 765         STAT_NETDEV(tx_dropped),
 766         STAT_NETDEV(multicast),
 767         /* UniMAC RSV counters */
 768         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 769         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 770         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 771         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 772         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 773         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 774         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 775         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 776         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 777         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 778         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 779         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 780         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 781         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 782         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 783         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 784         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 785         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 786         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 787         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 788         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 789         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 790         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 791         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 792         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 793         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 794         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 795         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 796         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 797         /* UniMAC TSV counters */
 798         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 799         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 800         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 801         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 802         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 803         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 804         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 805         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 806         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 807         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 808         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 809         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 810         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 811         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 812         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 813         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 814         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 815         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 816         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 817         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 818         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 819         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 820         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 821         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 822         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 823         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 824         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 825         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 826         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 827         /* UniMAC RUNT counters */
 828         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 829         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 830         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 831         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 832         /* Misc UniMAC counters */
 833         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 834                         UMAC_RBUF_OVFL_CNT_V1),
 835         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
 836                         UMAC_RBUF_ERR_CNT_V1),
 837         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 838         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 839         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 840         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 841         /* Per TX queues */
 842         STAT_GENET_Q(0),
 843         STAT_GENET_Q(1),
 844         STAT_GENET_Q(2),
 845         STAT_GENET_Q(3),
 846         STAT_GENET_Q(16),
 847 };
 848
 849 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 850
 851 static void bcmgenet_get_drvinfo(struct net_device *dev,
 852                                  struct ethtool_drvinfo *info)
 853 {
 854         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 855         strlcpy(info->version, "v2.0", sizeof(info->version));
 856 }
 857
 858 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 859 {
 860         switch (string_set) {
 861         case ETH_SS_STATS:
 862                 return BCMGENET_STATS_LEN;
 863         default:
 864                 return -EOPNOTSUPP;
 865         }
 866 }
 867
 868 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 869                                  u8 *data)
 870 {
 871         int i;
 872
 873         switch (stringset) {
 874         case ETH_SS_STATS:
 875                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 876                         memcpy(data + i * ETH_GSTRING_LEN,
 877                                bcmgenet_gstrings_stats[i].stat_string,
 878                                ETH_GSTRING_LEN);
 879                 }
 880                 break;
 881         }
 882 }
 883
 884 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
 885 {
 886         u16 new_offset;
 887         u32 val;
 888
 889         switch (offset) {
 890         case UMAC_RBUF_OVFL_CNT_V1:
 891                 if (GENET_IS_V2(priv))
 892                         new_offset = RBUF_OVFL_CNT_V2;
 893                 else
 894                         new_offset = RBUF_OVFL_CNT_V3PLUS;
 895
 896                 val = bcmgenet_rbuf_readl(priv, new_offset);
 897                 /* clear if overflowed */
 898                 if (val == ~0)
 899                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 900                 break;
 901         case UMAC_RBUF_ERR_CNT_V1:
 902                 if (GENET_IS_V2(priv))
 903                         new_offset = RBUF_ERR_CNT_V2;
 904                 else
 905                         new_offset = RBUF_ERR_CNT_V3PLUS;
 906
 907                 val = bcmgenet_rbuf_readl(priv, new_offset);
 908                 /* clear if overflowed */
 909                 if (val == ~0)
 910                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 911                 break;
 912         default:
 913                 val = bcmgenet_umac_readl(priv, offset);
 914                 /* clear if overflowed */
 915                 if (val == ~0)
 916                         bcmgenet_umac_writel(priv, 0, offset);
 917                 break;
 918         }
 919
 920         return val;
 921 }
 922
 923 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 924 {
 925         int i, j = 0;
 926
 927         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 928                 const struct bcmgenet_stats *s;
 929                 u8 offset = 0;
 930                 u32 val = 0;
 931                 char *p;
 932
 933                 s = &bcmgenet_gstrings_stats[i];
 934                 switch (s->type) {
 935                 case BCMGENET_STAT_NETDEV:
 936                 case BCMGENET_STAT_SOFT:
 937                         continue;
 938                 case BCMGENET_STAT_RUNT:
 939                         offset += BCMGENET_STAT_OFFSET;
 940                         /* fall through */
 941                 case BCMGENET_STAT_MIB_TX:
 942                         offset += BCMGENET_STAT_OFFSET;
 943                         /* fall through */
 944                 case BCMGENET_STAT_MIB_RX:
 945                         val = bcmgenet_umac_readl(priv,
 946                                                   UMAC_MIB_START + j + offset);
 947                         offset = 0;     /* Reset Offset */
 948                         break;
 949                 case BCMGENET_STAT_MISC:
 950                         if (GENET_IS_V1(priv)) {
 951                                 val = bcmgenet_umac_readl(priv, s->reg_offset);
 952                                 /* clear if overflowed */
 953                                 if (val == ~0)
 954                                         bcmgenet_umac_writel(priv, 0,
 955                                                              s->reg_offset);
 956                         } else {
 957                                 val = bcmgenet_update_stat_misc(priv,
 958                                                                 s->reg_offset);
 959                         }
 960                         break;
 961                 }
 962
 963                 j += s->stat_sizeof;
 964                 p = (char *)priv + s->stat_offset;
 965                 *(u32 *)p = val;
 966         }
 967 }
 968
 969 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 970                                        struct ethtool_stats *stats,
 971                                        u64 *data)
 972 {
 973         struct bcmgenet_priv *priv = netdev_priv(dev);
 974         int i;
 975
 976         if (netif_running(dev))
 977                 bcmgenet_update_mib_counters(priv);
 978
 979         dev->netdev_ops->ndo_get_stats(dev);
 980
 981         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 982                 const struct bcmgenet_stats *s;
 983                 char *p;
 984
 985                 s = &bcmgenet_gstrings_stats[i];
 986                 if (s->type == BCMGENET_STAT_NETDEV)
 987                         p = (char *)&dev->stats;
 988                 else
 989                         p = (char *)priv;
 990                 p += s->stat_offset;
 991                 if (sizeof(unsigned long) != sizeof(u32) &&
 992                     s->stat_sizeof == sizeof(unsigned long))
 993                         data[i] = *(unsigned long *)p;
 994                 else
 995                         data[i] = *(u32 *)p;
 996         }
 997 }
 998
 999 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1000 {
1001         struct bcmgenet_priv *priv = netdev_priv(dev);
1002         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1003         u32 reg;
1004
1005         if (enable && !priv->clk_eee_enabled) {
1006                 clk_prepare_enable(priv->clk_eee);
1007                 priv->clk_eee_enabled = true;
1008         }
1009
1010         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1011         if (enable)
1012                 reg |= EEE_EN;
1013         else
1014                 reg &= ~EEE_EN;
1015         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1016
1017         /* Enable EEE and switch to a 27Mhz clock automatically */
1018         reg = bcmgenet_readl(priv->base + off);
1019         if (enable)
1020                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1021         else
1022                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1023         bcmgenet_writel(reg, priv->base + off);
1024
1025         /* Do the same for thing for RBUF */
1026         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1027         if (enable)
1028                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1029         else
1030                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1031         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1032
1033         if (!enable && priv->clk_eee_enabled) {
1034                 clk_disable_unprepare(priv->clk_eee);
1035                 priv->clk_eee_enabled = false;
1036         }
1037
1038         priv->eee.eee_enabled = enable;
1039         priv->eee.eee_active = enable;
1040 }
1041
1042 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1043 {
1044         struct bcmgenet_priv *priv = netdev_priv(dev);
1045         struct ethtool_eee *p = &priv->eee;
1046
1047         if (GENET_IS_V1(priv))
1048                 return -EOPNOTSUPP;
1049
1050         e->eee_enabled = p->eee_enabled;
1051         e->eee_active = p->eee_active;
1052         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1053
1054         return phy_ethtool_get_eee(priv->phydev, e);
1055 }
1056
1057 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1058 {
1059         struct bcmgenet_priv *priv = netdev_priv(dev);
1060         struct ethtool_eee *p = &priv->eee;
1061         int ret = 0;
1062
1063         if (GENET_IS_V1(priv))
1064                 return -EOPNOTSUPP;
1065
1066         p->eee_enabled = e->eee_enabled;
1067
1068         if (!p->eee_enabled) {
1069                 bcmgenet_eee_enable_set(dev, false);
1070         } else {
1071                 ret = phy_init_eee(priv->phydev, 0);
1072                 if (ret) {
1073                         netif_err(priv, hw, dev, "EEE initialization failed\n");
1074                         return ret;
1075                 }
1076
1077                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1078                 bcmgenet_eee_enable_set(dev, true);
1079         }
1080
1081         return phy_ethtool_set_eee(priv->phydev, e);
1082 }
1083
1084 /* standard ethtool support functions. */
1085 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1086         .begin                  = bcmgenet_begin,
1087         .complete               = bcmgenet_complete,
1088         .get_strings            = bcmgenet_get_strings,
1089         .get_sset_count         = bcmgenet_get_sset_count,
1090         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
1091         .get_drvinfo            = bcmgenet_get_drvinfo,
1092         .get_link               = ethtool_op_get_link,
1093         .get_msglevel           = bcmgenet_get_msglevel,
1094         .set_msglevel           = bcmgenet_set_msglevel,
1095         .get_wol                = bcmgenet_get_wol,
1096         .set_wol                = bcmgenet_set_wol,
1097         .get_eee                = bcmgenet_get_eee,
1098         .set_eee                = bcmgenet_set_eee,
1099         .nway_reset             = phy_ethtool_nway_reset,
1100         .get_coalesce           = bcmgenet_get_coalesce,
1101         .set_coalesce           = bcmgenet_set_coalesce,
1102         .get_link_ksettings     = bcmgenet_get_link_ksettings,
1103         .set_link_ksettings     = bcmgenet_set_link_ksettings,
1104 };
1105
1106 /* Power down the unimac, based on mode. */
1107 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1108                                 enum bcmgenet_power_mode mode)
1109 {
1110         int ret = 0;
1111         u32 reg;
1112
1113         switch (mode) {
1114         case GENET_POWER_CABLE_SENSE:
1115                 phy_detach(priv->phydev);
1116                 break;
1117
1118         case GENET_POWER_WOL_MAGIC:
1119                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1120                 break;
1121
1122         case GENET_POWER_PASSIVE:
1123                 /* Power down LED */
1124                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1125                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1126                         if (GENET_IS_V5(priv))
1127                                 reg |= EXT_PWR_DOWN_PHY_EN |
1128                                        EXT_PWR_DOWN_PHY_RD |
1129                                        EXT_PWR_DOWN_PHY_SD |
1130                                        EXT_PWR_DOWN_PHY_RX |
1131                                        EXT_PWR_DOWN_PHY_TX |
1132                                        EXT_IDDQ_GLBL_PWR;
1133                         else
1134                                 reg |= EXT_PWR_DOWN_PHY;
1135
1136                         reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1137                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1138
1139                         bcmgenet_phy_power_set(priv->dev, false);
1140                 }
1141                 break;
1142         default:
1143                 break;
1144         }
1145
1146         return ret;
1147 }
1148
1149 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1150                               enum bcmgenet_power_mode mode)
1151 {
1152         u32 reg;
1153
1154         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1155                 return;
1156
1157         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1158
1159         switch (mode) {
1160         case GENET_POWER_PASSIVE:
1161                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1162                          EXT_ENERGY_DET_MASK);
1163                 if (GENET_IS_V5(priv)) {
1164                         reg &= ~(EXT_PWR_DOWN_PHY_EN |
1165                                  EXT_PWR_DOWN_PHY_RD |
1166                                  EXT_PWR_DOWN_PHY_SD |
1167                                  EXT_PWR_DOWN_PHY_RX |
1168                                  EXT_PWR_DOWN_PHY_TX |
1169                                  EXT_IDDQ_GLBL_PWR);
1170                         reg |=   EXT_PHY_RESET;
1171                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1172                         mdelay(1);
1173
1174                         reg &=  ~EXT_PHY_RESET;
1175                 } else {
1176                         reg &= ~EXT_PWR_DOWN_PHY;
1177                         reg |= EXT_PWR_DN_EN_LD;
1178                 }
1179                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1180                 bcmgenet_phy_power_set(priv->dev, true);
1181                 bcmgenet_mii_reset(priv->dev);
1182                 break;
1183
1184         case GENET_POWER_CABLE_SENSE:
1185                 /* enable APD */
1186                 if (!GENET_IS_V5(priv)) {
1187                         reg |= EXT_PWR_DN_EN_LD;
1188                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1189                 }
1190                 break;
1191         case GENET_POWER_WOL_MAGIC:
1192                 bcmgenet_wol_power_up_cfg(priv, mode);
1193                 return;
1194         default:
1195                 break;
1196         }
1197 }
1198
1199 /* ioctl handle special commands that are not present in ethtool. */
1200 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1201 {
1202         struct bcmgenet_priv *priv = netdev_priv(dev);
1203
1204         if (!netif_running(dev))
1205                 return -EINVAL;
1206
1207         if (!priv->phydev)
1208                 return -ENODEV;
1209
1210         return phy_mii_ioctl(priv->phydev, rq, cmd);
1211 }
1212
1213 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1214                                          struct bcmgenet_tx_ring *ring)
1215 {
1216         struct enet_cb *tx_cb_ptr;
1217
1218         tx_cb_ptr = ring->cbs;
1219         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1220
1221         /* Advancing local write pointer */
1222         if (ring->write_ptr == ring->end_ptr)
1223                 ring->write_ptr = ring->cb_ptr;
1224         else
1225                 ring->write_ptr++;
1226
1227         return tx_cb_ptr;
1228 }
1229
1230 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1231                                          struct bcmgenet_tx_ring *ring)
1232 {
1233         struct enet_cb *tx_cb_ptr;
1234
1235         tx_cb_ptr = ring->cbs;
1236         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1237
1238         /* Rewinding local write pointer */
1239         if (ring->write_ptr == ring->cb_ptr)
1240                 ring->write_ptr = ring->end_ptr;
1241         else
1242                 ring->write_ptr--;
1243
1244         return tx_cb_ptr;
1245 }
1246
1247 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1248 {
1249         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1250                                  INTRL2_CPU_MASK_SET);
1251 }
1252
1253 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1254 {
1255         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1256                                  INTRL2_CPU_MASK_CLEAR);
1257 }
1258
1259 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1260 {
1261         bcmgenet_intrl2_1_writel(ring->priv,
1262                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1263                                  INTRL2_CPU_MASK_SET);
1264 }
1265
1266 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1267 {
1268         bcmgenet_intrl2_1_writel(ring->priv,
1269                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1270                                  INTRL2_CPU_MASK_CLEAR);
1271 }
1272
1273 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1274 {
1275         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1276                                  INTRL2_CPU_MASK_SET);
1277 }
1278
1279 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1280 {
1281         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1282                                  INTRL2_CPU_MASK_CLEAR);
1283 }
1284
1285 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1286 {
1287         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1288                                  INTRL2_CPU_MASK_CLEAR);
1289 }
1290
1291 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1292 {
1293         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1294                                  INTRL2_CPU_MASK_SET);
1295 }
1296
1297 /* Simple helper to free a transmit control block's resources
1298  * Returns an skb when the last transmit control block associated with the
1299  * skb is freed.  The skb should be freed by the caller if necessary.
1300  */
1301 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1302                                            struct enet_cb *cb)
1303 {
1304         struct sk_buff *skb;
1305
1306         skb = cb->skb;
1307
1308         if (skb) {
1309                 cb->skb = NULL;
1310                 if (cb == GENET_CB(skb)->first_cb)
1311                         dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1312                                          dma_unmap_len(cb, dma_len),
1313                                          DMA_TO_DEVICE);
1314                 else
1315                         dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1316                                        dma_unmap_len(cb, dma_len),
1317                                        DMA_TO_DEVICE);
1318                 dma_unmap_addr_set(cb, dma_addr, 0);
1319
1320                 if (cb == GENET_CB(skb)->last_cb)
1321                         return skb;
1322
1323         } else if (dma_unmap_addr(cb, dma_addr)) {
1324                 dma_unmap_page(dev,
1325                                dma_unmap_addr(cb, dma_addr),
1326                                dma_unmap_len(cb, dma_len),
1327                                DMA_TO_DEVICE);
1328                 dma_unmap_addr_set(cb, dma_addr, 0);
1329         }
1330
1331         return 0;
1332 }
1333
1334 /* Simple helper to free a receive control block's resources */
1335 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1336                                            struct enet_cb *cb)
1337 {
1338         struct sk_buff *skb;
1339
1340         skb = cb->skb;
1341         cb->skb = NULL;
1342
1343         if (dma_unmap_addr(cb, dma_addr)) {
1344                 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1345                                  dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1346                 dma_unmap_addr_set(cb, dma_addr, 0);
1347         }
1348
1349         return skb;
1350 }
1351
1352 /* Unlocked version of the reclaim routine */
1353 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1354                                           struct bcmgenet_tx_ring *ring)
1355 {
1356         struct bcmgenet_priv *priv = netdev_priv(dev);
1357         unsigned int txbds_processed = 0;
1358         unsigned int bytes_compl = 0;
1359         unsigned int pkts_compl = 0;
1360         unsigned int txbds_ready;
1361         unsigned int c_index;
1362         struct sk_buff *skb;
1363
1364         /* Clear status before servicing to reduce spurious interrupts */
1365         if (ring->index == DESC_INDEX)
1366                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1367                                          INTRL2_CPU_CLEAR);
1368         else
1369                 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1370                                          INTRL2_CPU_CLEAR);
1371
1372         /* Compute how many buffers are transmitted since last xmit call */
1373         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1374                 & DMA_C_INDEX_MASK;
1375         txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1376
1377         netif_dbg(priv, tx_done, dev,
1378                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1379                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1380
1381         /* Reclaim transmitted buffers */
1382         while (txbds_processed < txbds_ready) {
1383                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1384                                           &priv->tx_cbs[ring->clean_ptr]);
1385                 if (skb) {
1386                         pkts_compl++;
1387                         bytes_compl += GENET_CB(skb)->bytes_sent;
1388                         dev_consume_skb_any(skb);
1389                 }
1390
1391                 txbds_processed++;
1392                 if (likely(ring->clean_ptr < ring->end_ptr))
1393                         ring->clean_ptr++;
1394                 else
1395                         ring->clean_ptr = ring->cb_ptr;
1396         }
1397
1398         ring->free_bds += txbds_processed;
1399         ring->c_index = c_index;
1400
1401         ring->packets += pkts_compl;
1402         ring->bytes += bytes_compl;
1403
1404         netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1405                                   pkts_compl, bytes_compl);
1406
1407         return txbds_processed;
1408 }
1409
1410 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1411                                 struct bcmgenet_tx_ring *ring)
1412 {
1413         unsigned int released;
1414         unsigned long flags;
1415
1416         spin_lock_irqsave(&ring->lock, flags);
1417         released = __bcmgenet_tx_reclaim(dev, ring);
1418         spin_unlock_irqrestore(&ring->lock, flags);
1419
1420         return released;
1421 }
1422
1423 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1424 {
1425         struct bcmgenet_tx_ring *ring =
1426                 container_of(napi, struct bcmgenet_tx_ring, napi);
1427         unsigned int work_done = 0;
1428         struct netdev_queue *txq;
1429         unsigned long flags;
1430
1431         spin_lock_irqsave(&ring->lock, flags);
1432         work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1433         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1434                 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1435                 netif_tx_wake_queue(txq);
1436         }
1437         spin_unlock_irqrestore(&ring->lock, flags);
1438
1439         if (work_done == 0) {
1440                 napi_complete(napi);
1441                 ring->int_enable(ring);
1442
1443                 return 0;
1444         }
1445
1446         return budget;
1447 }
1448
1449 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1450 {
1451         struct bcmgenet_priv *priv = netdev_priv(dev);
1452         int i;
1453
1454         if (netif_is_multiqueue(dev)) {
1455                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1456                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1457         }
1458
1459         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1460 }
1461
1462 /* Reallocate the SKB to put enough headroom in front of it and insert
1463  * the transmit checksum offsets in the descriptors
1464  */
1465 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1466                                             struct sk_buff *skb)
1467 {
1468         struct status_64 *status = NULL;
1469         struct sk_buff *new_skb;
1470         u16 offset;
1471         u8 ip_proto;
1472         u16 ip_ver;
1473         u32 tx_csum_info;
1474
1475         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1476                 /* If 64 byte status block enabled, must make sure skb has
1477                  * enough headroom for us to insert 64B status block.
1478                  */
1479                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1480                 dev_kfree_skb(skb);
1481                 if (!new_skb) {
1482                         dev->stats.tx_dropped++;
1483                         return NULL;
1484                 }
1485                 skb = new_skb;
1486         }
1487
1488         skb_push(skb, sizeof(*status));
1489         status = (struct status_64 *)skb->data;
1490
1491         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1492                 ip_ver = htons(skb->protocol);
1493                 switch (ip_ver) {
1494                 case ETH_P_IP:
1495                         ip_proto = ip_hdr(skb)->protocol;
1496                         break;
1497                 case ETH_P_IPV6:
1498                         ip_proto = ipv6_hdr(skb)->nexthdr;
1499                         break;
1500                 default:
1501                         return skb;
1502                 }
1503
1504                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1505                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1506                                 (offset + skb->csum_offset);
1507
1508                 /* Set the length valid bit for TCP and UDP and just set
1509                  * the special UDP flag for IPv4, else just set to 0.
1510                  */
1511                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1512                         tx_csum_info |= STATUS_TX_CSUM_LV;
1513                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1514                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1515                 } else {
1516                         tx_csum_info = 0;
1517                 }
1518
1519                 status->tx_csum_info = tx_csum_info;
1520         }
1521
1522         return skb;
1523 }
1524
1525 static void bcmgenet_hide_tsb(struct sk_buff *skb)
1526 {
1527         __skb_pull(skb, sizeof(struct status_64));
1528 }
1529
1530 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1531 {
1532         struct bcmgenet_priv *priv = netdev_priv(dev);
1533         struct device *kdev = &priv->pdev->dev;
1534         struct bcmgenet_tx_ring *ring = NULL;
1535         struct enet_cb *tx_cb_ptr;
1536         struct netdev_queue *txq;
1537         unsigned long flags = 0;
1538         int nr_frags, index;
1539         dma_addr_t mapping;
1540         unsigned int size;
1541         skb_frag_t *frag;
1542         u32 len_stat;
1543         int ret;
1544         int i;
1545
1546         index = skb_get_queue_mapping(skb);
1547         /* Mapping strategy:
1548          * queue_mapping = 0, unclassified, packet xmited through ring16
1549          * queue_mapping = 1, goes to ring 0. (highest priority queue
1550          * queue_mapping = 2, goes to ring 1.
1551          * queue_mapping = 3, goes to ring 2.
1552          * queue_mapping = 4, goes to ring 3.
1553          */
1554         if (index == 0)
1555                 index = DESC_INDEX;
1556         else
1557                 index -= 1;
1558
1559         ring = &priv->tx_rings[index];
1560         txq = netdev_get_tx_queue(dev, ring->queue);
1561
1562         nr_frags = skb_shinfo(skb)->nr_frags;
1563
1564         spin_lock_irqsave(&ring->lock, flags);
1565         if (ring->free_bds <= (nr_frags + 1)) {
1566                 if (!netif_tx_queue_stopped(txq)) {
1567                         netif_tx_stop_queue(txq);
1568                         netdev_err(dev,
1569                                    "%s: tx ring %d full when queue %d awake\n",
1570                                    __func__, index, ring->queue);
1571                 }
1572                 ret = NETDEV_TX_BUSY;
1573                 goto out;
1574         }
1575
1576         /* Retain how many bytes will be sent on the wire, without TSB inserted
1577          * by transmit checksum offload
1578          */
1579         GENET_CB(skb)->bytes_sent = skb->len;
1580
1581         /* set the SKB transmit checksum */
1582         if (priv->desc_64b_en) {
1583                 skb = bcmgenet_put_tx_csum(dev, skb);
1584                 if (!skb) {
1585                         ret = NETDEV_TX_OK;
1586                         goto out;
1587                 }
1588         }
1589
1590         for (i = 0; i <= nr_frags; i++) {
1591                 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1592
1593                 if (unlikely(!tx_cb_ptr))
1594                         BUG();
1595
1596                 if (!i) {
1597                         /* Transmit single SKB or head of fragment list */
1598                         GENET_CB(skb)->first_cb = tx_cb_ptr;
1599                         size = skb_headlen(skb);
1600                         mapping = dma_map_single(kdev, skb->data, size,
1601                                                  DMA_TO_DEVICE);
1602                 } else {
1603                         /* xmit fragment */
1604                         frag = &skb_shinfo(skb)->frags[i - 1];
1605                         size = skb_frag_size(frag);
1606                         mapping = skb_frag_dma_map(kdev, frag, 0, size,
1607                                                    DMA_TO_DEVICE);
1608                 }
1609
1610                 ret = dma_mapping_error(kdev, mapping);
1611                 if (ret) {
1612                         priv->mib.tx_dma_failed++;
1613                         netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1614                         ret = NETDEV_TX_OK;
1615                         goto out_unmap_frags;
1616                 }
1617                 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1618                 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1619
1620                 tx_cb_ptr->skb = skb;
1621
1622                 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1623                            (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1624
1625                 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
1626                  * will need to restore software padding of "runt" packets
1627                  */
1628                 if (!i) {
1629                         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1630                         if (skb->ip_summed == CHECKSUM_PARTIAL)
1631                                 len_stat |= DMA_TX_DO_CSUM;
1632                 }
1633                 if (i == nr_frags)
1634                         len_stat |= DMA_EOP;
1635
1636                 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1637         }
1638
1639         GENET_CB(skb)->last_cb = tx_cb_ptr;
1640
1641         bcmgenet_hide_tsb(skb);
1642         skb_tx_timestamp(skb);
1643
1644         /* Decrement total BD count and advance our write pointer */
1645         ring->free_bds -= nr_frags + 1;
1646         ring->prod_index += nr_frags + 1;
1647         ring->prod_index &= DMA_P_INDEX_MASK;
1648
1649         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1650
1651         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1652                 netif_tx_stop_queue(txq);
1653
1654         if (!skb->xmit_more || netif_xmit_stopped(txq))
1655                 /* Packets are ready, update producer index */
1656                 bcmgenet_tdma_ring_writel(priv, ring->index,
1657                                           ring->prod_index, TDMA_PROD_INDEX);
1658 out:
1659         spin_unlock_irqrestore(&ring->lock, flags);
1660
1661         return ret;
1662
1663 out_unmap_frags:
1664         /* Back up for failed control block mapping */
1665         bcmgenet_put_txcb(priv, ring);
1666
1667         /* Unmap successfully mapped control blocks */
1668         while (i-- > 0) {
1669                 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1670                 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1671         }
1672
1673         dev_kfree_skb(skb);
1674         goto out;
1675 }
1676
1677 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1678                                           struct enet_cb *cb)
1679 {
1680         struct device *kdev = &priv->pdev->dev;
1681         struct sk_buff *skb;
1682         struct sk_buff *rx_skb;
1683         dma_addr_t mapping;
1684
1685         /* Allocate a new Rx skb */
1686         skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1687                                  GFP_ATOMIC | __GFP_NOWARN);
1688         if (!skb) {
1689                 priv->mib.alloc_rx_buff_failed++;
1690                 netif_err(priv, rx_err, priv->dev,
1691                           "%s: Rx skb allocation failed\n", __func__);
1692                 return NULL;
1693         }
1694
1695         /* DMA-map the new Rx skb */
1696         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1697                                  DMA_FROM_DEVICE);
1698         if (dma_mapping_error(kdev, mapping)) {
1699                 priv->mib.rx_dma_failed++;
1700                 dev_kfree_skb_any(skb);
1701                 netif_err(priv, rx_err, priv->dev,
1702                           "%s: Rx skb DMA mapping failed\n", __func__);
1703                 return NULL;
1704         }
1705
1706         /* Grab the current Rx skb from the ring and DMA-unmap it */
1707         rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1708
1709         /* Put the new Rx skb on the ring */
1710         cb->skb = skb;
1711         dma_unmap_addr_set(cb, dma_addr, mapping);
1712         dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1713         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1714
1715         /* Return the current Rx skb to caller */
1716         return rx_skb;
1717 }
1718
1719 /* bcmgenet_desc_rx - descriptor based rx process.
1720  * this could be called from bottom half, or from NAPI polling method.
1721  */
1722 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1723                                      unsigned int budget)
1724 {
1725         struct bcmgenet_priv *priv = ring->priv;
1726         struct net_device *dev = priv->dev;
1727         struct enet_cb *cb;
1728         struct sk_buff *skb;
1729         u32 dma_length_status;
1730         unsigned long dma_flag;
1731         int len;
1732         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1733         unsigned int p_index, mask;
1734         unsigned int discards;
1735         unsigned int chksum_ok = 0;
1736
1737         /* Clear status before servicing to reduce spurious interrupts */
1738         if (ring->index == DESC_INDEX) {
1739                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1740                                          INTRL2_CPU_CLEAR);
1741         } else {
1742                 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1743                 bcmgenet_intrl2_1_writel(priv,
1744                                          mask,
1745                                          INTRL2_CPU_CLEAR);
1746         }
1747
1748         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1749
1750         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1751                    DMA_P_INDEX_DISCARD_CNT_MASK;
1752         if (discards > ring->old_discards) {
1753                 discards = discards - ring->old_discards;
1754                 ring->errors += discards;
1755                 ring->old_discards += discards;
1756
1757                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1758                 if (ring->old_discards >= 0xC000) {
1759                         ring->old_discards = 0;
1760                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1761                                                   RDMA_PROD_INDEX);
1762                 }
1763         }
1764
1765         p_index &= DMA_P_INDEX_MASK;
1766         rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1767
1768         netif_dbg(priv, rx_status, dev,
1769                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1770
1771         while ((rxpktprocessed < rxpkttoprocess) &&
1772                (rxpktprocessed < budget)) {
1773                 cb = &priv->rx_cbs[ring->read_ptr];
1774                 skb = bcmgenet_rx_refill(priv, cb);
1775
1776                 if (unlikely(!skb)) {
1777                         ring->dropped++;
1778                         goto next;
1779                 }
1780
1781                 if (!priv->desc_64b_en) {
1782                         dma_length_status =
1783                                 dmadesc_get_length_status(priv, cb->bd_addr);
1784                 } else {
1785                         struct status_64 *status;
1786
1787                         status = (struct status_64 *)skb->data;
1788                         dma_length_status = status->length_status;
1789                 }
1790
1791                 /* DMA flags and length are still valid no matter how
1792                  * we got the Receive Status Vector (64B RSB or register)
1793                  */
1794                 dma_flag = dma_length_status & 0xffff;
1795                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1796
1797                 netif_dbg(priv, rx_status, dev,
1798                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1799                           __func__, p_index, ring->c_index,
1800                           ring->read_ptr, dma_length_status);
1801
1802                 if (unlikely(len > RX_BUF_LENGTH)) {
1803                         netif_err(priv, rx_status, dev, "oversized packet\n");
1804                         dev->stats.rx_length_errors++;
1805                         dev->stats.rx_errors++;
1806                         dev_kfree_skb_any(skb);
1807                         goto next;
1808                 }
1809
1810                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1811                         netif_err(priv, rx_status, dev,
1812                                   "dropping fragmented packet!\n");
1813                         ring->errors++;
1814                         dev_kfree_skb_any(skb);
1815                         goto next;
1816                 }
1817
1818                 /* report errors */
1819                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1820                                                 DMA_RX_OV |
1821                                                 DMA_RX_NO |
1822                                                 DMA_RX_LG |
1823                                                 DMA_RX_RXER))) {
1824                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1825                                   (unsigned int)dma_flag);
1826                         if (dma_flag & DMA_RX_CRC_ERROR)
1827                                 dev->stats.rx_crc_errors++;
1828                         if (dma_flag & DMA_RX_OV)
1829                                 dev->stats.rx_over_errors++;
1830                         if (dma_flag & DMA_RX_NO)
1831                                 dev->stats.rx_frame_errors++;
1832                         if (dma_flag & DMA_RX_LG)
1833                                 dev->stats.rx_length_errors++;
1834                         dev->stats.rx_errors++;
1835                         dev_kfree_skb_any(skb);
1836                         goto next;
1837                 } /* error packet */
1838
1839                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1840                              priv->desc_rxchk_en;
1841
1842                 skb_put(skb, len);
1843                 if (priv->desc_64b_en) {
1844                         skb_pull(skb, 64);
1845                         len -= 64;
1846                 }
1847
1848                 if (likely(chksum_ok))
1849                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1850
1851                 /* remove hardware 2bytes added for IP alignment */
1852                 skb_pull(skb, 2);
1853                 len -= 2;
1854
1855                 if (priv->crc_fwd_en) {
1856                         skb_trim(skb, len - ETH_FCS_LEN);
1857                         len -= ETH_FCS_LEN;
1858                 }
1859
1860                 /*Finish setting up the received SKB and send it to the kernel*/
1861                 skb->protocol = eth_type_trans(skb, priv->dev);
1862                 ring->packets++;
1863                 ring->bytes += len;
1864                 if (dma_flag & DMA_RX_MULT)
1865                         dev->stats.multicast++;
1866
1867                 /* Notify kernel */
1868                 napi_gro_receive(&ring->napi, skb);
1869                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1870
1871 next:
1872                 rxpktprocessed++;
1873                 if (likely(ring->read_ptr < ring->end_ptr))
1874                         ring->read_ptr++;
1875                 else
1876                         ring->read_ptr = ring->cb_ptr;
1877
1878                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1879                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1880         }
1881
1882         return rxpktprocessed;
1883 }
1884
1885 /* Rx NAPI polling method */
1886 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1887 {
1888         struct bcmgenet_rx_ring *ring = container_of(napi,
1889                         struct bcmgenet_rx_ring, napi);
1890         unsigned int work_done;
1891
1892         work_done = bcmgenet_desc_rx(ring, budget);
1893
1894         if (work_done < budget) {
1895                 napi_complete_done(napi, work_done);
1896                 ring->int_enable(ring);
1897         }
1898
1899         return work_done;
1900 }
1901
1902 /* Assign skb to RX DMA descriptor. */
1903 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1904                                      struct bcmgenet_rx_ring *ring)
1905 {
1906         struct enet_cb *cb;
1907         struct sk_buff *skb;
1908         int i;
1909
1910         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1911
1912         /* loop here for each buffer needing assign */
1913         for (i = 0; i < ring->size; i++) {
1914                 cb = ring->cbs + i;
1915                 skb = bcmgenet_rx_refill(priv, cb);
1916                 if (skb)
1917                         dev_consume_skb_any(skb);
1918                 if (!cb->skb)
1919                         return -ENOMEM;
1920         }
1921
1922         return 0;
1923 }
1924
1925 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1926 {
1927         struct sk_buff *skb;
1928         struct enet_cb *cb;
1929         int i;
1930
1931         for (i = 0; i < priv->num_rx_bds; i++) {
1932                 cb = &priv->rx_cbs[i];
1933
1934                 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1935                 if (skb)
1936                         dev_consume_skb_any(skb);
1937         }
1938 }
1939
1940 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1941 {
1942         u32 reg;
1943
1944         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1945         if (enable)
1946                 reg |= mask;
1947         else
1948                 reg &= ~mask;
1949         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1950
1951         /* UniMAC stops on a packet boundary, wait for a full-size packet
1952          * to be processed
1953          */
1954         if (enable == 0)
1955                 usleep_range(1000, 2000);
1956 }
1957
1958 static int reset_umac(struct bcmgenet_priv *priv)
1959 {
1960         struct device *kdev = &priv->pdev->dev;
1961         unsigned int timeout = 0;
1962         u32 reg;
1963
1964         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1965         bcmgenet_rbuf_ctrl_set(priv, 0);
1966         udelay(10);
1967
1968         /* disable MAC while updating its registers */
1969         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1970
1971         /* issue soft reset, wait for it to complete */
1972         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1973         while (timeout++ < 1000) {
1974                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1975                 if (!(reg & CMD_SW_RESET))
1976                         return 0;
1977
1978                 udelay(1);
1979         }
1980
1981         if (timeout == 1000) {
1982                 dev_err(kdev,
1983                         "timeout waiting for MAC to come out of reset\n");
1984                 return -ETIMEDOUT;
1985         }
1986
1987         return 0;
1988 }
1989
1990 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1991 {
1992         /* Mask all interrupts.*/
1993         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1994         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1995         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1996         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1997 }
1998
1999 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2000 {
2001         u32 int0_enable = 0;
2002
2003         /* Monitor cable plug/unplugged event for internal PHY, external PHY
2004          * and MoCA PHY
2005          */
2006         if (priv->internal_phy) {
2007                 int0_enable |= UMAC_IRQ_LINK_EVENT;
2008                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2009                         int0_enable |= UMAC_IRQ_PHY_DET_R;
2010         } else if (priv->ext_phy) {
2011                 int0_enable |= UMAC_IRQ_LINK_EVENT;
2012         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2013                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2014                         int0_enable |= UMAC_IRQ_LINK_EVENT;
2015         }
2016         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2017 }
2018
2019 static int init_umac(struct bcmgenet_priv *priv)
2020 {
2021         struct device *kdev = &priv->pdev->dev;
2022         int ret;
2023         u32 reg;
2024         u32 int0_enable = 0;
2025
2026         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2027
2028         ret = reset_umac(priv);
2029         if (ret)
2030                 return ret;
2031
2032         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2033         /* clear tx/rx counter */
2034         bcmgenet_umac_writel(priv,
2035                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2036                              UMAC_MIB_CTRL);
2037         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2038
2039         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2040
2041         /* init rx registers, enable ip header optimization */
2042         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2043         reg |= RBUF_ALIGN_2B;
2044         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2045
2046         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2047                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2048
2049         bcmgenet_intr_disable(priv);
2050
2051         /* Configure backpressure vectors for MoCA */
2052         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2053                 reg = bcmgenet_bp_mc_get(priv);
2054                 reg |= BIT(priv->hw_params->bp_in_en_shift);
2055
2056                 /* bp_mask: back pressure mask */
2057                 if (netif_is_multiqueue(priv->dev))
2058                         reg |= priv->hw_params->bp_in_mask;
2059                 else
2060                         reg &= ~priv->hw_params->bp_in_mask;
2061                 bcmgenet_bp_mc_set(priv, reg);
2062         }
2063
2064         /* Enable MDIO interrupts on GENET v3+ */
2065         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2066                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2067
2068         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2069
2070         dev_dbg(kdev, "done init umac\n");
2071
2072         return 0;
2073 }
2074
2075 /* Initialize a Tx ring along with corresponding hardware registers */
2076 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2077                                   unsigned int index, unsigned int size,
2078                                   unsigned int start_ptr, unsigned int end_ptr)
2079 {
2080         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2081         u32 words_per_bd = WORDS_PER_BD(priv);
2082         u32 flow_period_val = 0;
2083
2084         spin_lock_init(&ring->lock);
2085         ring->priv = priv;
2086         ring->index = index;
2087         if (index == DESC_INDEX) {
2088                 ring->queue = 0;
2089                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2090                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2091         } else {
2092                 ring->queue = index + 1;
2093                 ring->int_enable = bcmgenet_tx_ring_int_enable;
2094                 ring->int_disable = bcmgenet_tx_ring_int_disable;
2095         }
2096         ring->cbs = priv->tx_cbs + start_ptr;
2097         ring->size = size;
2098         ring->clean_ptr = start_ptr;
2099         ring->c_index = 0;
2100         ring->free_bds = size;
2101         ring->write_ptr = start_ptr;
2102         ring->cb_ptr = start_ptr;
2103         ring->end_ptr = end_ptr - 1;
2104         ring->prod_index = 0;
2105
2106         /* Set flow period for ring != 16 */
2107         if (index != DESC_INDEX)
2108                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2109
2110         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2111         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2112         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2113         /* Disable rate control for now */
2114         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2115                                   TDMA_FLOW_PERIOD);
2116         bcmgenet_tdma_ring_writel(priv, index,
2117                                   ((size << DMA_RING_SIZE_SHIFT) |
2118                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2119
2120         /* Set start and end address, read and write pointers */
2121         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2122                                   DMA_START_ADDR);
2123         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2124                                   TDMA_READ_PTR);
2125         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2126                                   TDMA_WRITE_PTR);
2127         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2128                                   DMA_END_ADDR);
2129 }
2130
2131 /* Initialize a RDMA ring */
2132 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2133                                  unsigned int index, unsigned int size,
2134                                  unsigned int start_ptr, unsigned int end_ptr)
2135 {
2136         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2137         u32 words_per_bd = WORDS_PER_BD(priv);
2138         int ret;
2139
2140         ring->priv = priv;
2141         ring->index = index;
2142         if (index == DESC_INDEX) {
2143                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2144                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2145         } else {
2146                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2147                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2148         }
2149         ring->cbs = priv->rx_cbs + start_ptr;
2150         ring->size = size;
2151         ring->c_index = 0;
2152         ring->read_ptr = start_ptr;
2153         ring->cb_ptr = start_ptr;
2154         ring->end_ptr = end_ptr - 1;
2155
2156         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2157         if (ret)
2158                 return ret;
2159
2160         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2161         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2162         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2163         bcmgenet_rdma_ring_writel(priv, index,
2164                                   ((size << DMA_RING_SIZE_SHIFT) |
2165                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2166         bcmgenet_rdma_ring_writel(priv, index,
2167                                   (DMA_FC_THRESH_LO <<
2168                                    DMA_XOFF_THRESHOLD_SHIFT) |
2169                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2170
2171         /* Set start and end address, read and write pointers */
2172         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2173                                   DMA_START_ADDR);
2174         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2175                                   RDMA_READ_PTR);
2176         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2177                                   RDMA_WRITE_PTR);
2178         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2179                                   DMA_END_ADDR);
2180
2181         return ret;
2182 }
2183
2184 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2185 {
2186         unsigned int i;
2187         struct bcmgenet_tx_ring *ring;
2188
2189         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2190                 ring = &priv->tx_rings[i];
2191                 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2192         }
2193
2194         ring = &priv->tx_rings[DESC_INDEX];
2195         netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2196 }
2197
2198 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2199 {
2200         unsigned int i;
2201         u32 int0_enable = UMAC_IRQ_TXDMA_DONE;
2202         u32 int1_enable = 0;
2203         struct bcmgenet_tx_ring *ring;
2204
2205         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2206                 ring = &priv->tx_rings[i];
2207                 napi_enable(&ring->napi);
2208                 int1_enable |= (1 << i);
2209         }
2210
2211         ring = &priv->tx_rings[DESC_INDEX];
2212         napi_enable(&ring->napi);
2213
2214         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2215         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2216 }
2217
2218 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2219 {
2220         unsigned int i;
2221         u32 int0_disable = UMAC_IRQ_TXDMA_DONE;
2222         u32 int1_disable = 0xffff;
2223         struct bcmgenet_tx_ring *ring;
2224
2225         bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2226         bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2227
2228         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2229                 ring = &priv->tx_rings[i];
2230                 napi_disable(&ring->napi);
2231         }
2232
2233         ring = &priv->tx_rings[DESC_INDEX];
2234         napi_disable(&ring->napi);
2235 }
2236
2237 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2238 {
2239         unsigned int i;
2240         struct bcmgenet_tx_ring *ring;
2241
2242         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2243                 ring = &priv->tx_rings[i];
2244                 netif_napi_del(&ring->napi);
2245         }
2246
2247         ring = &priv->tx_rings[DESC_INDEX];
2248         netif_napi_del(&ring->napi);
2249 }
2250
2251 /* Initialize Tx queues
2252  *
2253  * Queues 0-3 are priority-based, each one has 32 descriptors,
2254  * with queue 0 being the highest priority queue.
2255  *
2256  * Queue 16 is the default Tx queue with
2257  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2258  *
2259  * The transmit control block pool is then partitioned as follows:
2260  * - Tx queue 0 uses tx_cbs[0..31]
2261  * - Tx queue 1 uses tx_cbs[32..63]
2262  * - Tx queue 2 uses tx_cbs[64..95]
2263  * - Tx queue 3 uses tx_cbs[96..127]
2264  * - Tx queue 16 uses tx_cbs[128..255]
2265  */
2266 static void bcmgenet_init_tx_queues(struct net_device *dev)
2267 {
2268         struct bcmgenet_priv *priv = netdev_priv(dev);
2269         u32 i, dma_enable;
2270         u32 dma_ctrl, ring_cfg;
2271         u32 dma_priority[3] = {0, 0, 0};
2272
2273         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2274         dma_enable = dma_ctrl & DMA_EN;
2275         dma_ctrl &= ~DMA_EN;
2276         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2277
2278         dma_ctrl = 0;
2279         ring_cfg = 0;
2280
2281         /* Enable strict priority arbiter mode */
2282         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2283
2284         /* Initialize Tx priority queues */
2285         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2286                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2287                                       i * priv->hw_params->tx_bds_per_q,
2288                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2289                 ring_cfg |= (1 << i);
2290                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2291                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2292                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2293         }
2294
2295         /* Initialize Tx default queue 16 */
2296         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2297                               priv->hw_params->tx_queues *
2298                               priv->hw_params->tx_bds_per_q,
2299                               TOTAL_DESC);
2300         ring_cfg |= (1 << DESC_INDEX);
2301         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2302         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2303                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2304                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2305
2306         /* Set Tx queue priorities */
2307         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2308         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2309         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2310
2311         /* Initialize Tx NAPI */
2312         bcmgenet_init_tx_napi(priv);
2313
2314         /* Enable Tx queues */
2315         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2316
2317         /* Enable Tx DMA */
2318         if (dma_enable)
2319                 dma_ctrl |= DMA_EN;
2320         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2321 }
2322
2323 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2324 {
2325         unsigned int i;
2326         struct bcmgenet_rx_ring *ring;
2327
2328         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2329                 ring = &priv->rx_rings[i];
2330                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2331         }
2332
2333         ring = &priv->rx_rings[DESC_INDEX];
2334         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2335 }
2336
2337 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2338 {
2339         unsigned int i;
2340         u32 int0_enable = UMAC_IRQ_RXDMA_DONE;
2341         u32 int1_enable = 0;
2342         struct bcmgenet_rx_ring *ring;
2343
2344         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2345                 ring = &priv->rx_rings[i];
2346                 napi_enable(&ring->napi);
2347                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
2348         }
2349
2350         ring = &priv->rx_rings[DESC_INDEX];
2351         napi_enable(&ring->napi);
2352
2353         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2354         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2355 }
2356
2357 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2358 {
2359         unsigned int i;
2360         u32 int0_disable = UMAC_IRQ_RXDMA_DONE;
2361         u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT;
2362         struct bcmgenet_rx_ring *ring;
2363
2364         bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2365         bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2366
2367         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2368                 ring = &priv->rx_rings[i];
2369                 napi_disable(&ring->napi);
2370         }
2371
2372         ring = &priv->rx_rings[DESC_INDEX];
2373         napi_disable(&ring->napi);
2374 }
2375
2376 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2377 {
2378         unsigned int i;
2379         struct bcmgenet_rx_ring *ring;
2380
2381         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2382                 ring = &priv->rx_rings[i];
2383                 netif_napi_del(&ring->napi);
2384         }
2385
2386         ring = &priv->rx_rings[DESC_INDEX];
2387         netif_napi_del(&ring->napi);
2388 }
2389
2390 /* Initialize Rx queues
2391  *
2392  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2393  * used to direct traffic to these queues.
2394  *
2395  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2396  */
2397 static int bcmgenet_init_rx_queues(struct net_device *dev)
2398 {
2399         struct bcmgenet_priv *priv = netdev_priv(dev);
2400         u32 i;
2401         u32 dma_enable;
2402         u32 dma_ctrl;
2403         u32 ring_cfg;
2404         int ret;
2405
2406         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2407         dma_enable = dma_ctrl & DMA_EN;
2408         dma_ctrl &= ~DMA_EN;
2409         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2410
2411         dma_ctrl = 0;
2412         ring_cfg = 0;
2413
2414         /* Initialize Rx priority queues */
2415         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2416                 ret = bcmgenet_init_rx_ring(priv, i,
2417                                             priv->hw_params->rx_bds_per_q,
2418                                             i * priv->hw_params->rx_bds_per_q,
2419                                             (i + 1) *
2420                                             priv->hw_params->rx_bds_per_q);
2421                 if (ret)
2422                         return ret;
2423
2424                 ring_cfg |= (1 << i);
2425                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2426         }
2427
2428         /* Initialize Rx default queue 16 */
2429         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2430                                     priv->hw_params->rx_queues *
2431                                     priv->hw_params->rx_bds_per_q,
2432                                     TOTAL_DESC);
2433         if (ret)
2434                 return ret;
2435
2436         ring_cfg |= (1 << DESC_INDEX);
2437         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2438
2439         /* Initialize Rx NAPI */
2440         bcmgenet_init_rx_napi(priv);
2441
2442         /* Enable rings */
2443         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2444
2445         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2446         if (dma_enable)
2447                 dma_ctrl |= DMA_EN;
2448         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2449
2450         return 0;
2451 }
2452
2453 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2454 {
2455         int ret = 0;
2456         int timeout = 0;
2457         u32 reg;
2458         u32 dma_ctrl;
2459         int i;
2460
2461         /* Disable TDMA to stop add more frames in TX DMA */
2462         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2463         reg &= ~DMA_EN;
2464         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2465
2466         /* Check TDMA status register to confirm TDMA is disabled */
2467         while (timeout++ < DMA_TIMEOUT_VAL) {
2468                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2469                 if (reg & DMA_DISABLED)
2470                         break;
2471
2472                 udelay(1);
2473         }
2474
2475         if (timeout == DMA_TIMEOUT_VAL) {
2476                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2477                 ret = -ETIMEDOUT;
2478         }
2479
2480         /* Wait 10ms for packet drain in both tx and rx dma */
2481         usleep_range(10000, 20000);
2482
2483         /* Disable RDMA */
2484         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2485         reg &= ~DMA_EN;
2486         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2487
2488         timeout = 0;
2489         /* Check RDMA status register to confirm RDMA is disabled */
2490         while (timeout++ < DMA_TIMEOUT_VAL) {
2491                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2492                 if (reg & DMA_DISABLED)
2493                         break;
2494
2495                 udelay(1);
2496         }
2497
2498         if (timeout == DMA_TIMEOUT_VAL) {
2499                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2500                 ret = -ETIMEDOUT;
2501         }
2502
2503         dma_ctrl = 0;
2504         for (i = 0; i < priv->hw_params->rx_queues; i++)
2505                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2506         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2507         reg &= ~dma_ctrl;
2508         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2509
2510         dma_ctrl = 0;
2511         for (i = 0; i < priv->hw_params->tx_queues; i++)
2512                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2513         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2514         reg &= ~dma_ctrl;
2515         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2516
2517         return ret;
2518 }
2519
2520 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2521 {
2522         struct netdev_queue *txq;
2523         struct sk_buff *skb;
2524         struct enet_cb *cb;
2525         int i;
2526
2527         bcmgenet_fini_rx_napi(priv);
2528         bcmgenet_fini_tx_napi(priv);
2529
2530         /* disable DMA */
2531         bcmgenet_dma_teardown(priv);
2532
2533         for (i = 0; i < priv->num_tx_bds; i++) {
2534                 cb = priv->tx_cbs + i;
2535                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2536                 if (skb)
2537                         dev_kfree_skb(skb);
2538         }
2539
2540         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2541                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2542                 netdev_tx_reset_queue(txq);
2543         }
2544
2545         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2546         netdev_tx_reset_queue(txq);
2547
2548         bcmgenet_free_rx_buffers(priv);
2549         kfree(priv->rx_cbs);
2550         kfree(priv->tx_cbs);
2551 }
2552
2553 /* init_edma: Initialize DMA control register */
2554 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2555 {
2556         int ret;
2557         unsigned int i;
2558         struct enet_cb *cb;
2559
2560         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2561
2562         /* Initialize common Rx ring structures */
2563         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2564         priv->num_rx_bds = TOTAL_DESC;
2565         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2566                                GFP_KERNEL);
2567         if (!priv->rx_cbs)
2568                 return -ENOMEM;
2569
2570         for (i = 0; i < priv->num_rx_bds; i++) {
2571                 cb = priv->rx_cbs + i;
2572                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2573         }
2574
2575         /* Initialize common TX ring structures */
2576         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2577         priv->num_tx_bds = TOTAL_DESC;
2578         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2579                                GFP_KERNEL);
2580         if (!priv->tx_cbs) {
2581                 kfree(priv->rx_cbs);
2582                 return -ENOMEM;
2583         }
2584
2585         for (i = 0; i < priv->num_tx_bds; i++) {
2586                 cb = priv->tx_cbs + i;
2587                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2588         }
2589
2590         /* Init rDma */
2591         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2592
2593         /* Initialize Rx queues */
2594         ret = bcmgenet_init_rx_queues(priv->dev);
2595         if (ret) {
2596                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2597                 bcmgenet_free_rx_buffers(priv);
2598                 kfree(priv->rx_cbs);
2599                 kfree(priv->tx_cbs);
2600                 return ret;
2601         }
2602
2603         /* Init tDma */
2604         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2605
2606         /* Initialize Tx queues */
2607         bcmgenet_init_tx_queues(priv->dev);
2608
2609         return 0;
2610 }
2611
2612 /* Interrupt bottom half */
2613 static void bcmgenet_irq_task(struct work_struct *work)
2614 {
2615         unsigned long flags;
2616         unsigned int status;
2617         struct bcmgenet_priv *priv = container_of(
2618                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2619
2620         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2621
2622         spin_lock_irqsave(&priv->lock, flags);
2623         status = priv->irq0_stat;
2624         priv->irq0_stat = 0;
2625         spin_unlock_irqrestore(&priv->lock, flags);
2626
2627         if (status & UMAC_IRQ_MPD_R) {
2628                 netif_dbg(priv, wol, priv->dev,
2629                           "magic packet detected, waking up\n");
2630                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2631         }
2632
2633         if (status & UMAC_IRQ_PHY_DET_R &&
2634             priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2635                 phy_init_hw(priv->dev->phydev);
2636                 genphy_config_aneg(priv->dev->phydev);
2637         }
2638
2639         /* Link UP/DOWN event */
2640         if (status & UMAC_IRQ_LINK_EVENT)
2641                 phy_mac_interrupt(priv->phydev,
2642                                   !!(status & UMAC_IRQ_LINK_UP));
2643 }
2644
2645 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2646 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2647 {
2648         struct bcmgenet_priv *priv = dev_id;
2649         struct bcmgenet_rx_ring *rx_ring;
2650         struct bcmgenet_tx_ring *tx_ring;
2651         unsigned int index, status;
2652
2653         /* Read irq status */
2654         status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2655                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2656
2657         /* clear interrupts */
2658         bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2659
2660         netif_dbg(priv, intr, priv->dev,
2661                   "%s: IRQ=0x%x\n", __func__, status);
2662
2663         /* Check Rx priority queue interrupts */
2664         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2665                 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2666                         continue;
2667
2668                 rx_ring = &priv->rx_rings[index];
2669
2670                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2671                         rx_ring->int_disable(rx_ring);
2672                         __napi_schedule_irqoff(&rx_ring->napi);
2673                 }
2674         }
2675
2676         /* Check Tx priority queue interrupts */
2677         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2678                 if (!(status & BIT(index)))
2679                         continue;
2680
2681                 tx_ring = &priv->tx_rings[index];
2682
2683                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2684                         tx_ring->int_disable(tx_ring);
2685                         __napi_schedule_irqoff(&tx_ring->napi);
2686                 }
2687         }
2688
2689         return IRQ_HANDLED;
2690 }
2691
2692 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2693 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2694 {
2695         struct bcmgenet_priv *priv = dev_id;
2696         struct bcmgenet_rx_ring *rx_ring;
2697         struct bcmgenet_tx_ring *tx_ring;
2698         unsigned int status;
2699         unsigned long flags;
2700
2701         /* Read irq status */
2702         status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2703                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2704
2705         /* clear interrupts */
2706         bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2707
2708         netif_dbg(priv, intr, priv->dev,
2709                   "IRQ=0x%x\n", status);
2710
2711         if (status & UMAC_IRQ_RXDMA_DONE) {
2712                 rx_ring = &priv->rx_rings[DESC_INDEX];
2713
2714                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2715                         rx_ring->int_disable(rx_ring);
2716                         __napi_schedule_irqoff(&rx_ring->napi);
2717                 }
2718         }
2719
2720         if (status & UMAC_IRQ_TXDMA_DONE) {
2721                 tx_ring = &priv->tx_rings[DESC_INDEX];
2722
2723                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2724                         tx_ring->int_disable(tx_ring);
2725                         __napi_schedule_irqoff(&tx_ring->napi);
2726                 }
2727         }
2728
2729         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2730                                 UMAC_IRQ_PHY_DET_F |
2731                                 UMAC_IRQ_LINK_EVENT |
2732                                 UMAC_IRQ_HFB_SM |
2733                                 UMAC_IRQ_HFB_MM)) {
2734                 /* all other interested interrupts handled in bottom half */
2735                 schedule_work(&priv->bcmgenet_irq_work);
2736         }
2737
2738         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2739                 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2740                 wake_up(&priv->wq);
2741         }
2742
2743         /* all other interested interrupts handled in bottom half */
2744         status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_MPD_R | UMAC_IRQ_PHY_DET_R);
2745         if (status) {
2746                 /* Save irq status for bottom-half processing. */
2747                 spin_lock_irqsave(&priv->lock, flags);
2748                 priv->irq0_stat |= status;
2749                 spin_unlock_irqrestore(&priv->lock, flags);
2750
2751                 schedule_work(&priv->bcmgenet_irq_work);
2752         }
2753
2754         return IRQ_HANDLED;
2755 }
2756
2757 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2758 {
2759         struct bcmgenet_priv *priv = dev_id;
2760
2761         pm_wakeup_event(&priv->pdev->dev, 0);
2762
2763         return IRQ_HANDLED;
2764 }
2765
2766 #ifdef CONFIG_NET_POLL_CONTROLLER
2767 static void bcmgenet_poll_controller(struct net_device *dev)
2768 {
2769         struct bcmgenet_priv *priv = netdev_priv(dev);
2770
2771         /* Invoke the main RX/TX interrupt handler */
2772         disable_irq(priv->irq0);
2773         bcmgenet_isr0(priv->irq0, priv);
2774         enable_irq(priv->irq0);
2775
2776         /* And the interrupt handler for RX/TX priority queues */
2777         disable_irq(priv->irq1);
2778         bcmgenet_isr1(priv->irq1, priv);
2779         enable_irq(priv->irq1);
2780 }
2781 #endif
2782
2783 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2784 {
2785         u32 reg;
2786
2787         reg = bcmgenet_rbuf_ctrl_get(priv);
2788         reg |= BIT(1);
2789         bcmgenet_rbuf_ctrl_set(priv, reg);
2790         udelay(10);
2791
2792         reg &= ~BIT(1);
2793         bcmgenet_rbuf_ctrl_set(priv, reg);
2794         udelay(10);
2795 }
2796
2797 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2798                                  unsigned char *addr)
2799 {
2800         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2801                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2802         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2803 }
2804
2805 /* Returns a reusable dma control register value */
2806 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2807 {
2808         unsigned int i;
2809         u32 reg;
2810         u32 dma_ctrl;
2811
2812         /* disable DMA */
2813         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2814         for (i = 0; i < priv->hw_params->tx_queues; i++)
2815                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2816         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2817         reg &= ~dma_ctrl;
2818         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2819
2820         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2821         for (i = 0; i < priv->hw_params->rx_queues; i++)
2822                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2823         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2824         reg &= ~dma_ctrl;
2825         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2826
2827         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2828         udelay(10);
2829         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2830
2831         return dma_ctrl;
2832 }
2833
2834 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2835 {
2836         u32 reg;
2837
2838         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2839         reg |= dma_ctrl;
2840         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2841
2842         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2843         reg |= dma_ctrl;
2844         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2845 }
2846
2847 /* bcmgenet_hfb_clear
2848  *
2849  * Clear Hardware Filter Block and disable all filtering.
2850  */
2851 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2852 {
2853         u32 i;
2854
2855         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2856         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2857         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2858
2859         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2860                 bcmgenet_rdma_writel(priv, 0x0, i);
2861
2862         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2863                 bcmgenet_hfb_reg_writel(priv, 0x0,
2864                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2865
2866         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2867                         priv->hw_params->hfb_filter_size; i++)
2868                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2869 }
2870
2871 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2872 {
2873         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2874                 return;
2875
2876         bcmgenet_hfb_clear(priv);
2877 }
2878
2879 static void bcmgenet_netif_start(struct net_device *dev)
2880 {
2881         struct bcmgenet_priv *priv = netdev_priv(dev);
2882
2883         /* Start the network engine */
2884         bcmgenet_set_rx_mode(dev);
2885         bcmgenet_enable_rx_napi(priv);
2886         bcmgenet_enable_tx_napi(priv);
2887
2888         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2889
2890         netif_tx_start_all_queues(dev);
2891
2892         /* Monitor link interrupts now */
2893         bcmgenet_link_intr_enable(priv);
2894
2895         phy_start(priv->phydev);
2896 }
2897
2898 static int bcmgenet_open(struct net_device *dev)
2899 {
2900         struct bcmgenet_priv *priv = netdev_priv(dev);
2901         unsigned long dma_ctrl;
2902         u32 reg;
2903         int ret;
2904
2905         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2906
2907         /* Turn on the clock */
2908         clk_prepare_enable(priv->clk);
2909
2910         /* If this is an internal GPHY, power it back on now, before UniMAC is
2911          * brought out of reset as absolutely no UniMAC activity is allowed
2912          */
2913         if (priv->internal_phy)
2914                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2915
2916         /* take MAC out of reset */
2917         bcmgenet_umac_reset(priv);
2918
2919         ret = init_umac(priv);
2920         if (ret)
2921                 goto err_clk_disable;
2922
2923         /* disable ethernet MAC while updating its registers */
2924         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2925
2926         /* Make sure we reflect the value of CRC_CMD_FWD */
2927         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2928         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2929
2930         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2931
2932         /* Disable RX/TX DMA and flush TX queues */
2933         dma_ctrl = bcmgenet_dma_disable(priv);
2934
2935         /* Reinitialize TDMA and RDMA and SW housekeeping */
2936         ret = bcmgenet_init_dma(priv);
2937         if (ret) {
2938                 netdev_err(dev, "failed to initialize DMA\n");
2939                 goto err_clk_disable;
2940         }
2941
2942         /* Always enable ring 16 - descriptor ring */
2943         bcmgenet_enable_dma(priv, dma_ctrl);
2944
2945         /* HFB init */
2946         bcmgenet_hfb_init(priv);
2947
2948         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2949                           dev->name, priv);
2950         if (ret < 0) {
2951                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2952                 goto err_fini_dma;
2953         }
2954
2955         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2956                           dev->name, priv);
2957         if (ret < 0) {
2958                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2959                 goto err_irq0;
2960         }
2961
2962         ret = bcmgenet_mii_probe(dev);
2963         if (ret) {
2964                 netdev_err(dev, "failed to connect to PHY\n");
2965                 goto err_irq1;
2966         }
2967
2968         bcmgenet_netif_start(dev);
2969
2970         return 0;
2971
2972 err_irq1:
2973         free_irq(priv->irq1, priv);
2974 err_irq0:
2975         free_irq(priv->irq0, priv);
2976 err_fini_dma:
2977         bcmgenet_fini_dma(priv);
2978 err_clk_disable:
2979         if (priv->internal_phy)
2980                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2981         clk_disable_unprepare(priv->clk);
2982         return ret;
2983 }
2984
2985 static void bcmgenet_netif_stop(struct net_device *dev)
2986 {
2987         struct bcmgenet_priv *priv = netdev_priv(dev);
2988
2989         netif_tx_stop_all_queues(dev);
2990         phy_stop(priv->phydev);
2991         bcmgenet_intr_disable(priv);
2992         bcmgenet_disable_rx_napi(priv);
2993         bcmgenet_disable_tx_napi(priv);
2994
2995         /* Wait for pending work items to complete. Since interrupts are
2996          * disabled no new work will be scheduled.
2997          */
2998         cancel_work_sync(&priv->bcmgenet_irq_work);
2999
3000         priv->old_link = -1;
3001         priv->old_speed = -1;
3002         priv->old_duplex = -1;
3003         priv->old_pause = -1;
3004 }
3005
3006 static int bcmgenet_close(struct net_device *dev)
3007 {
3008         struct bcmgenet_priv *priv = netdev_priv(dev);
3009         int ret;
3010
3011         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3012
3013         bcmgenet_netif_stop(dev);
3014
3015         /* Really kill the PHY state machine and disconnect from it */
3016         phy_disconnect(priv->phydev);
3017
3018         /* Disable MAC receive */
3019         umac_enable_set(priv, CMD_RX_EN, false);
3020
3021         ret = bcmgenet_dma_teardown(priv);
3022         if (ret)
3023                 return ret;
3024
3025         /* Disable MAC transmit. TX DMA disabled must be done before this */
3026         umac_enable_set(priv, CMD_TX_EN, false);
3027
3028         /* tx reclaim */
3029         bcmgenet_tx_reclaim_all(dev);
3030         bcmgenet_fini_dma(priv);
3031
3032         free_irq(priv->irq0, priv);
3033         free_irq(priv->irq1, priv);
3034
3035         if (priv->internal_phy)
3036                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3037
3038         clk_disable_unprepare(priv->clk);
3039
3040         return ret;
3041 }
3042
3043 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3044 {
3045         struct bcmgenet_priv *priv = ring->priv;
3046         u32 p_index, c_index, intsts, intmsk;
3047         struct netdev_queue *txq;
3048         unsigned int free_bds;
3049         unsigned long flags;
3050         bool txq_stopped;
3051
3052         if (!netif_msg_tx_err(priv))
3053                 return;
3054
3055         txq = netdev_get_tx_queue(priv->dev, ring->queue);
3056
3057         spin_lock_irqsave(&ring->lock, flags);
3058         if (ring->index == DESC_INDEX) {
3059                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3060                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3061         } else {
3062                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3063                 intmsk = 1 << ring->index;
3064         }
3065         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3066         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3067         txq_stopped = netif_tx_queue_stopped(txq);
3068         free_bds = ring->free_bds;
3069         spin_unlock_irqrestore(&ring->lock, flags);
3070
3071         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3072                   "TX queue status: %s, interrupts: %s\n"
3073                   "(sw)free_bds: %d (sw)size: %d\n"
3074                   "(sw)p_index: %d (hw)p_index: %d\n"
3075                   "(sw)c_index: %d (hw)c_index: %d\n"
3076                   "(sw)clean_p: %d (sw)write_p: %d\n"
3077                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3078                   ring->index, ring->queue,
3079                   txq_stopped ? "stopped" : "active",
3080                   intsts & intmsk ? "enabled" : "disabled",
3081                   free_bds, ring->size,
3082                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
3083                   ring->c_index, c_index & DMA_C_INDEX_MASK,
3084                   ring->clean_ptr, ring->write_ptr,
3085                   ring->cb_ptr, ring->end_ptr);
3086 }
3087
3088 static void bcmgenet_timeout(struct net_device *dev)
3089 {
3090         struct bcmgenet_priv *priv = netdev_priv(dev);
3091         u32 int0_enable = 0;
3092         u32 int1_enable = 0;
3093         unsigned int q;
3094
3095         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3096
3097         for (q = 0; q < priv->hw_params->tx_queues; q++)
3098                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3099         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3100
3101         bcmgenet_tx_reclaim_all(dev);
3102
3103         for (q = 0; q < priv->hw_params->tx_queues; q++)
3104                 int1_enable |= (1 << q);
3105
3106         int0_enable = UMAC_IRQ_TXDMA_DONE;
3107
3108         /* Re-enable TX interrupts if disabled */
3109         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3110         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3111
3112         netif_trans_update(dev);
3113
3114         dev->stats.tx_errors++;
3115
3116         netif_tx_wake_all_queues(dev);
3117 }
3118
3119 #define MAX_MDF_FILTER  17
3120
3121 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3122                                          unsigned char *addr,
3123                                          int *i)
3124 {
3125         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3126                              UMAC_MDF_ADDR + (*i * 4));
3127         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3128                              addr[4] << 8 | addr[5],
3129                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3130         *i += 2;
3131 }
3132
3133 static void bcmgenet_set_rx_mode(struct net_device *dev)
3134 {
3135         struct bcmgenet_priv *priv = netdev_priv(dev);
3136         struct netdev_hw_addr *ha;
3137         int i, nfilter;
3138         u32 reg;
3139
3140         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3141
3142         /* Number of filters needed */
3143         nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3144
3145         /*
3146          * Turn on promicuous mode for three scenarios
3147          * 1. IFF_PROMISC flag is set
3148          * 2. IFF_ALLMULTI flag is set
3149          * 3. The number of filters needed exceeds the number filters
3150          *    supported by the hardware.
3151         */
3152         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3153         if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3154             (nfilter > MAX_MDF_FILTER)) {
3155                 reg |= CMD_PROMISC;
3156                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3157                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3158                 return;
3159         } else {
3160                 reg &= ~CMD_PROMISC;
3161                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3162         }
3163
3164         /* update MDF filter */
3165         i = 0;
3166         /* Broadcast */
3167         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3168         /* my own address.*/
3169         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3170
3171         /* Unicast */
3172         netdev_for_each_uc_addr(ha, dev)
3173                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3174
3175         /* Multicast */
3176         netdev_for_each_mc_addr(ha, dev)
3177                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3178
3179         /* Enable filters */
3180         reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3181         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3182 }
3183
3184 /* Set the hardware MAC address. */
3185 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3186 {
3187         struct sockaddr *addr = p;
3188
3189         /* Setting the MAC address at the hardware level is not possible
3190          * without disabling the UniMAC RX/TX enable bits.
3191          */
3192         if (netif_running(dev))
3193                 return -EBUSY;
3194
3195         ether_addr_copy(dev->dev_addr, addr->sa_data);
3196
3197         return 0;
3198 }
3199
3200 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3201 {
3202         struct bcmgenet_priv *priv = netdev_priv(dev);
3203         unsigned long tx_bytes = 0, tx_packets = 0;
3204         unsigned long rx_bytes = 0, rx_packets = 0;
3205         unsigned long rx_errors = 0, rx_dropped = 0;
3206         struct bcmgenet_tx_ring *tx_ring;
3207         struct bcmgenet_rx_ring *rx_ring;
3208         unsigned int q;
3209
3210         for (q = 0; q < priv->hw_params->tx_queues; q++) {
3211                 tx_ring = &priv->tx_rings[q];
3212                 tx_bytes += tx_ring->bytes;
3213                 tx_packets += tx_ring->packets;
3214         }
3215         tx_ring = &priv->tx_rings[DESC_INDEX];
3216         tx_bytes += tx_ring->bytes;
3217         tx_packets += tx_ring->packets;
3218
3219         for (q = 0; q < priv->hw_params->rx_queues; q++) {
3220                 rx_ring = &priv->rx_rings[q];
3221
3222                 rx_bytes += rx_ring->bytes;
3223                 rx_packets += rx_ring->packets;
3224                 rx_errors += rx_ring->errors;
3225                 rx_dropped += rx_ring->dropped;
3226         }
3227         rx_ring = &priv->rx_rings[DESC_INDEX];
3228         rx_bytes += rx_ring->bytes;
3229         rx_packets += rx_ring->packets;
3230         rx_errors += rx_ring->errors;
3231         rx_dropped += rx_ring->dropped;
3232
3233         dev->stats.tx_bytes = tx_bytes;
3234         dev->stats.tx_packets = tx_packets;
3235         dev->stats.rx_bytes = rx_bytes;
3236         dev->stats.rx_packets = rx_packets;
3237         dev->stats.rx_errors = rx_errors;
3238         dev->stats.rx_missed_errors = rx_errors;
3239         dev->stats.rx_dropped = rx_dropped;
3240         return &dev->stats;
3241 }
3242
3243 static const struct net_device_ops bcmgenet_netdev_ops = {
3244         .ndo_open               = bcmgenet_open,
3245         .ndo_stop               = bcmgenet_close,
3246         .ndo_start_xmit         = bcmgenet_xmit,
3247         .ndo_tx_timeout         = bcmgenet_timeout,
3248         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3249         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3250         .ndo_do_ioctl           = bcmgenet_ioctl,
3251         .ndo_set_features       = bcmgenet_set_features,
3252 #ifdef CONFIG_NET_POLL_CONTROLLER
3253         .ndo_poll_controller    = bcmgenet_poll_controller,
3254 #endif
3255         .ndo_get_stats          = bcmgenet_get_stats,
3256 };
3257
3258 /* Array of GENET hardware parameters/characteristics */
3259 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3260         [GENET_V1] = {
3261                 .tx_queues = 0,
3262                 .tx_bds_per_q = 0,
3263                 .rx_queues = 0,
3264                 .rx_bds_per_q = 0,
3265                 .bp_in_en_shift = 16,
3266                 .bp_in_mask = 0xffff,
3267                 .hfb_filter_cnt = 16,
3268                 .qtag_mask = 0x1F,
3269                 .hfb_offset = 0x1000,
3270                 .rdma_offset = 0x2000,
3271                 .tdma_offset = 0x3000,
3272                 .words_per_bd = 2,
3273         },
3274         [GENET_V2] = {
3275                 .tx_queues = 4,
3276                 .tx_bds_per_q = 32,
3277                 .rx_queues = 0,
3278                 .rx_bds_per_q = 0,
3279                 .bp_in_en_shift = 16,
3280                 .bp_in_mask = 0xffff,
3281                 .hfb_filter_cnt = 16,
3282                 .qtag_mask = 0x1F,
3283                 .tbuf_offset = 0x0600,
3284                 .hfb_offset = 0x1000,
3285                 .hfb_reg_offset = 0x2000,
3286                 .rdma_offset = 0x3000,
3287                 .tdma_offset = 0x4000,
3288                 .words_per_bd = 2,
3289                 .flags = GENET_HAS_EXT,
3290         },
3291         [GENET_V3] = {
3292                 .tx_queues = 4,
3293                 .tx_bds_per_q = 32,
3294                 .rx_queues = 0,
3295                 .rx_bds_per_q = 0,
3296                 .bp_in_en_shift = 17,
3297                 .bp_in_mask = 0x1ffff,
3298                 .hfb_filter_cnt = 48,
3299                 .hfb_filter_size = 128,
3300                 .qtag_mask = 0x3F,
3301                 .tbuf_offset = 0x0600,
3302                 .hfb_offset = 0x8000,
3303                 .hfb_reg_offset = 0xfc00,
3304                 .rdma_offset = 0x10000,
3305                 .tdma_offset = 0x11000,
3306                 .words_per_bd = 2,
3307                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3308                          GENET_HAS_MOCA_LINK_DET,
3309         },
3310         [GENET_V4] = {
3311                 .tx_queues = 4,
3312                 .tx_bds_per_q = 32,
3313                 .rx_queues = 0,
3314                 .rx_bds_per_q = 0,
3315                 .bp_in_en_shift = 17,
3316                 .bp_in_mask = 0x1ffff,
3317                 .hfb_filter_cnt = 48,
3318                 .hfb_filter_size = 128,
3319                 .qtag_mask = 0x3F,
3320                 .tbuf_offset = 0x0600,
3321                 .hfb_offset = 0x8000,
3322                 .hfb_reg_offset = 0xfc00,
3323                 .rdma_offset = 0x2000,
3324                 .tdma_offset = 0x4000,
3325                 .words_per_bd = 3,
3326                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3327                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3328         },
3329         [GENET_V5] = {
3330                 .tx_queues = 4,
3331                 .tx_bds_per_q = 32,
3332                 .rx_queues = 0,
3333                 .rx_bds_per_q = 0,
3334                 .bp_in_en_shift = 17,
3335                 .bp_in_mask = 0x1ffff,
3336                 .hfb_filter_cnt = 48,
3337                 .hfb_filter_size = 128,
3338                 .qtag_mask = 0x3F,
3339                 .tbuf_offset = 0x0600,
3340                 .hfb_offset = 0x8000,
3341                 .hfb_reg_offset = 0xfc00,
3342                 .rdma_offset = 0x2000,
3343                 .tdma_offset = 0x4000,
3344                 .words_per_bd = 3,
3345                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3346                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3347         },
3348 };
3349
3350 /* Infer hardware parameters from the detected GENET version */
3351 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3352 {
3353         struct bcmgenet_hw_params *params;
3354         u32 reg;
3355         u8 major;
3356         u16 gphy_rev;
3357
3358         if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3359                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3360                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3361                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3362         } else if (GENET_IS_V3(priv)) {
3363                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3364                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3365                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3366         } else if (GENET_IS_V2(priv)) {
3367                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3368                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3369                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3370         } else if (GENET_IS_V1(priv)) {
3371                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3372                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3373                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3374         }
3375
3376         /* enum genet_version starts at 1 */
3377         priv->hw_params = &bcmgenet_hw_params[priv->version];
3378         params = priv->hw_params;
3379
3380         /* Read GENET HW version */
3381         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3382         major = (reg >> 24 & 0x0f);
3383         if (major == 6)
3384                 major = 5;
3385         else if (major == 5)
3386                 major = 4;
3387         else if (major == 0)
3388                 major = 1;
3389         if (major != priv->version) {
3390                 dev_err(&priv->pdev->dev,
3391                         "GENET version mismatch, got: %d, configured for: %d\n",
3392                         major, priv->version);
3393         }
3394
3395         /* Print the GENET core version */
3396         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3397                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3398
3399         /* Store the integrated PHY revision for the MDIO probing function
3400          * to pass this information to the PHY driver. The PHY driver expects
3401          * to find the PHY major revision in bits 15:8 while the GENET register
3402          * stores that information in bits 7:0, account for that.
3403          *
3404          * On newer chips, starting with PHY revision G0, a new scheme is
3405          * deployed similar to the Starfighter 2 switch with GPHY major
3406          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3407          * is reserved as well as special value 0x01ff, we have a small
3408          * heuristic to check for the new GPHY revision and re-arrange things
3409          * so the GPHY driver is happy.
3410          */
3411         gphy_rev = reg & 0xffff;
3412
3413         if (GENET_IS_V5(priv)) {
3414                 /* The EPHY revision should come from the MDIO registers of
3415                  * the PHY not from GENET.
3416                  */
3417                 if (gphy_rev != 0) {
3418                         pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3419                                 gphy_rev);
3420                 }
3421         /* This is reserved so should require special treatment */
3422         } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3423                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3424                 return;
3425         /* This is the good old scheme, just GPHY major, no minor nor patch */
3426         } else if ((gphy_rev & 0xf0) != 0) {
3427                 priv->gphy_rev = gphy_rev << 8;
3428         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3429         } else if ((gphy_rev & 0xff00) != 0) {
3430                 priv->gphy_rev = gphy_rev;
3431         }
3432
3433 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3434         if (!(params->flags & GENET_HAS_40BITS))
3435                 pr_warn("GENET does not support 40-bits PA\n");
3436 #endif
3437
3438         pr_debug("Configuration for version: %d\n"
3439                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3440                 "BP << en: %2d, BP msk: 0x%05x\n"
3441                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3442                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3443                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3444                 "Words/BD: %d\n",
3445                 priv->version,
3446                 params->tx_queues, params->tx_bds_per_q,
3447                 params->rx_queues, params->rx_bds_per_q,
3448                 params->bp_in_en_shift, params->bp_in_mask,
3449                 params->hfb_filter_cnt, params->qtag_mask,
3450                 params->tbuf_offset, params->hfb_offset,
3451                 params->hfb_reg_offset,
3452                 params->rdma_offset, params->tdma_offset,
3453                 params->words_per_bd);
3454 }
3455
3456 static const struct of_device_id bcmgenet_match[] = {
3457         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3458         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3459         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3460         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3461         { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3462         { },
3463 };
3464 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3465
3466 static int bcmgenet_probe(struct platform_device *pdev)
3467 {
3468         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3469         struct device_node *dn = pdev->dev.of_node;
3470         const struct of_device_id *of_id = NULL;
3471         struct bcmgenet_priv *priv;
3472         struct net_device *dev;
3473         const void *macaddr;
3474         struct resource *r;
3475         int err = -EIO;
3476         const char *phy_mode_str;
3477
3478         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3479         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3480                                  GENET_MAX_MQ_CNT + 1);
3481         if (!dev) {
3482                 dev_err(&pdev->dev, "can't allocate net device\n");
3483                 return -ENOMEM;
3484         }
3485
3486         if (dn) {
3487                 of_id = of_match_node(bcmgenet_match, dn);
3488                 if (!of_id)
3489                         return -EINVAL;
3490         }
3491
3492         priv = netdev_priv(dev);
3493         priv->irq0 = platform_get_irq(pdev, 0);
3494         priv->irq1 = platform_get_irq(pdev, 1);
3495         priv->wol_irq = platform_get_irq(pdev, 2);
3496         if (!priv->irq0 || !priv->irq1) {
3497                 dev_err(&pdev->dev, "can't find IRQs\n");
3498                 err = -EINVAL;
3499                 goto err;
3500         }
3501
3502         if (dn) {
3503                 macaddr = of_get_mac_address(dn);
3504                 if (!macaddr) {
3505                         dev_err(&pdev->dev, "can't find MAC address\n");
3506                         err = -EINVAL;
3507                         goto err;
3508                 }
3509         } else {
3510                 macaddr = pd->mac_address;
3511         }
3512
3513         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3514         priv->base = devm_ioremap_resource(&pdev->dev, r);
3515         if (IS_ERR(priv->base)) {
3516                 err = PTR_ERR(priv->base);
3517                 goto err;
3518         }
3519
3520         spin_lock_init(&priv->lock);
3521
3522         SET_NETDEV_DEV(dev, &pdev->dev);
3523         dev_set_drvdata(&pdev->dev, dev);
3524         ether_addr_copy(dev->dev_addr, macaddr);
3525         dev->watchdog_timeo = 2 * HZ;
3526         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3527         dev->netdev_ops = &bcmgenet_netdev_ops;
3528
3529         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3530
3531         /* Set hardware features */
3532         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3533                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3534
3535         /* Request the WOL interrupt and advertise suspend if available */
3536         priv->wol_irq_disabled = true;
3537         if (priv->wol_irq > 0) {
3538                 err = devm_request_irq(&pdev->dev, priv->wol_irq,
3539                                        bcmgenet_wol_isr, 0, dev->name, priv);
3540                 if (!err)
3541                         device_set_wakeup_capable(&pdev->dev, 1);
3542         }
3543
3544         /* Set the needed headroom to account for any possible
3545          * features enabling/disabling at runtime
3546          */
3547         dev->needed_headroom += 64;
3548
3549         netdev_boot_setup_check(dev);
3550
3551         priv->dev = dev;
3552         priv->pdev = pdev;
3553         if (of_id)
3554                 priv->version = (enum bcmgenet_version)of_id->data;
3555         else
3556                 priv->version = pd->genet_version;
3557
3558         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3559         if (IS_ERR(priv->clk)) {
3560                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3561                 priv->clk = NULL;
3562         }
3563
3564         clk_prepare_enable(priv->clk);
3565
3566         bcmgenet_set_hw_params(priv);
3567
3568         /* Mii wait queue */
3569         init_waitqueue_head(&priv->wq);
3570         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3571         priv->rx_buf_len = RX_BUF_LENGTH;
3572         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3573
3574         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3575         if (IS_ERR(priv->clk_wol)) {
3576                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3577                 priv->clk_wol = NULL;
3578         }
3579
3580         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3581         if (IS_ERR(priv->clk_eee)) {
3582                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3583                 priv->clk_eee = NULL;
3584         }
3585
3586         /* If this is an internal GPHY, power it on now, before UniMAC is
3587          * brought out of reset as absolutely no UniMAC activity is allowed
3588          */
3589         if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3590             !strcasecmp(phy_mode_str, "internal"))
3591                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3592
3593         err = reset_umac(priv);
3594         if (err)
3595                 goto err_clk_disable;
3596
3597         err = bcmgenet_mii_init(dev);
3598         if (err)
3599                 goto err_clk_disable;
3600
3601         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3602          * just the ring 16 descriptor based TX
3603          */
3604         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3605         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3606
3607         /* libphy will determine the link state */
3608         netif_carrier_off(dev);
3609
3610         /* Turn off the main clock, WOL clock is handled separately */
3611         clk_disable_unprepare(priv->clk);
3612
3613         err = register_netdev(dev);
3614         if (err) {
3615                 bcmgenet_mii_exit(dev);
3616                 goto err;
3617         }
3618
3619         return err;
3620
3621 err_clk_disable:
3622         clk_disable_unprepare(priv->clk);
3623 err:
3624         free_netdev(dev);
3625         return err;
3626 }
3627
3628 static int bcmgenet_remove(struct platform_device *pdev)
3629 {
3630         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3631
3632         dev_set_drvdata(&pdev->dev, NULL);
3633         unregister_netdev(priv->dev);
3634         bcmgenet_mii_exit(priv->dev);
3635         free_netdev(priv->dev);
3636
3637         return 0;
3638 }
3639
3640 #ifdef CONFIG_PM_SLEEP
3641 static int bcmgenet_suspend(struct device *d)
3642 {
3643         struct net_device *dev = dev_get_drvdata(d);
3644         struct bcmgenet_priv *priv = netdev_priv(dev);
3645         int ret;
3646
3647         if (!netif_running(dev))
3648                 return 0;
3649
3650         bcmgenet_netif_stop(dev);
3651
3652         if (!device_may_wakeup(d))
3653                 phy_suspend(priv->phydev);
3654
3655         netif_device_detach(dev);
3656
3657         /* Disable MAC receive */
3658         umac_enable_set(priv, CMD_RX_EN, false);
3659
3660         ret = bcmgenet_dma_teardown(priv);
3661         if (ret)
3662                 return ret;
3663
3664         /* Disable MAC transmit. TX DMA disabled must be done before this */
3665         umac_enable_set(priv, CMD_TX_EN, false);
3666
3667         /* tx reclaim */
3668         bcmgenet_tx_reclaim_all(dev);
3669         bcmgenet_fini_dma(priv);
3670
3671         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3672         if (device_may_wakeup(d) && priv->wolopts) {
3673                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3674                 clk_prepare_enable(priv->clk_wol);
3675         } else if (priv->internal_phy) {
3676                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3677         }
3678
3679         /* Turn off the clocks */
3680         clk_disable_unprepare(priv->clk);
3681
3682         return ret;
3683 }
3684
3685 static int bcmgenet_resume(struct device *d)
3686 {
3687         struct net_device *dev = dev_get_drvdata(d);
3688         struct bcmgenet_priv *priv = netdev_priv(dev);
3689         unsigned long dma_ctrl;
3690         int ret;
3691
3692         if (!netif_running(dev))
3693                 return 0;
3694
3695         /* Turn on the clock */
3696         ret = clk_prepare_enable(priv->clk);
3697         if (ret)
3698                 return ret;
3699
3700         /* If this is an internal GPHY, power it back on now, before UniMAC is
3701          * brought out of reset as absolutely no UniMAC activity is allowed
3702          */
3703         if (priv->internal_phy)
3704                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3705
3706         bcmgenet_umac_reset(priv);
3707
3708         ret = init_umac(priv);
3709         if (ret)
3710                 goto out_clk_disable;
3711
3712         /* From WOL-enabled suspend, switch to regular clock */
3713         if (priv->wolopts)
3714                 clk_disable_unprepare(priv->clk_wol);
3715
3716         phy_init_hw(priv->phydev);
3717         /* Speed settings must be restored */
3718         genphy_config_aneg(dev->phydev);
3719         bcmgenet_mii_config(priv->dev, false);
3720
3721         /* disable ethernet MAC while updating its registers */
3722         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3723
3724         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3725
3726         if (priv->wolopts)
3727                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3728
3729         /* Disable RX/TX DMA and flush TX queues */
3730         dma_ctrl = bcmgenet_dma_disable(priv);
3731
3732         /* Reinitialize TDMA and RDMA and SW housekeeping */
3733         ret = bcmgenet_init_dma(priv);
3734         if (ret) {
3735                 netdev_err(dev, "failed to initialize DMA\n");
3736                 goto out_clk_disable;
3737         }
3738
3739         /* Always enable ring 16 - descriptor ring */
3740         bcmgenet_enable_dma(priv, dma_ctrl);
3741
3742         netif_device_attach(dev);
3743
3744         if (!device_may_wakeup(d))
3745                 phy_resume(priv->phydev);
3746
3747         if (priv->eee.eee_enabled)
3748                 bcmgenet_eee_enable_set(dev, true);
3749
3750         bcmgenet_netif_start(dev);
3751
3752         return 0;
3753
3754 out_clk_disable:
3755         if (priv->internal_phy)
3756                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3757         clk_disable_unprepare(priv->clk);
3758         return ret;
3759 }
3760 #endif /* CONFIG_PM_SLEEP */
3761
3762 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3763
3764 static struct platform_driver bcmgenet_driver = {
3765         .probe  = bcmgenet_probe,
3766         .remove = bcmgenet_remove,
3767         .driver = {
3768                 .name   = "bcmgenet",
3769                 .of_match_table = bcmgenet_match,
3770                 .pm     = &bcmgenet_pm_ops,
3771         },
3772 };
3773 module_platform_driver(bcmgenet_driver);
3774
3775 MODULE_AUTHOR("Broadcom Corporation");
3776 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3777 MODULE_ALIAS("platform:bcmgenet");
3778 MODULE_LICENSE("GPL");
3779 MODULE_SOFTDEP("pre: mdio-bcm-unimac");