1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET (Gigabit Ethernet) controller driver
5 * Copyright (c) 2014-2020 Broadcom
8 #define pr_fmt(fmt) "bcmgenet: " fmt
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/string.h>
18 #include <linux/if_ether.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
25 #include <linux/clk.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/netdevice.h>
31 #include <linux/inetdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
36 #include <linux/ipv6.h>
37 #include <linux/phy.h>
38 #include <linux/platform_data/bcmgenet.h>
40 #include <asm/unaligned.h>
44 /* Maximum number of hardware queues, downsized if needed */
45 #define GENET_MAX_MQ_CNT 4
47 /* Default highest priority queue for multi queue support */
48 #define GENET_Q0_PRIORITY 0
50 #define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
52 #define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
55 #define RX_BUF_LENGTH 2048
56 #define SKB_ALIGNMENT 32
58 /* Tx/Rx DMA register offset, skip 256 descriptors */
59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
68 /* Forward declarations */
69 static void bcmgenet_set_rx_mode(struct net_device *dev);
71 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
73 /* MIPS chips strapped for BE will automagically configure the
74 * peripheral registers for CPU-native byte order.
76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 __raw_writel(value, offset);
79 writel_relaxed(value, offset);
82 static inline u32 bcmgenet_readl(void __iomem *offset)
84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 return __raw_readl(offset);
87 return readl_relaxed(offset);
90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
91 void __iomem *d, u32 value)
93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
102 /* Register writes to GISB bus can take couple hundred nanoseconds
103 * and are done for each packet, save these expensive writes unless
104 * the platform is explicitly configured for 64-bits/LPAE.
106 #ifdef CONFIG_PHYS_ADDR_T_64BIT
107 if (priv->hw_params->flags & GENET_HAS_40BITS)
108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
112 /* Combined address + length/status setter */
113 static inline void dmadesc_set(struct bcmgenet_priv *priv,
114 void __iomem *d, dma_addr_t addr, u32 val)
116 dmadesc_set_addr(priv, d, addr);
117 dmadesc_set_length_status(priv, d, val);
120 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
122 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
125 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
127 if (GENET_IS_V1(priv))
128 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
130 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
133 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
135 if (GENET_IS_V1(priv))
136 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
138 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
141 /* These macros are defined to deal with register map change
142 * between GENET1.1 and GENET2. Only those currently being used
143 * by driver are defined.
145 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
147 if (GENET_IS_V1(priv))
148 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
150 return bcmgenet_readl(priv->base +
151 priv->hw_params->tbuf_offset + TBUF_CTRL);
154 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
156 if (GENET_IS_V1(priv))
157 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
159 bcmgenet_writel(val, priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
163 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
165 if (GENET_IS_V1(priv))
166 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
168 return bcmgenet_readl(priv->base +
169 priv->hw_params->tbuf_offset + TBUF_BP_MC);
172 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
174 if (GENET_IS_V1(priv))
175 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
177 bcmgenet_writel(val, priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
181 /* RX/TX DMA register accessors */
218 static const u8 bcmgenet_dma_regs_v3plus[] = {
219 [DMA_RING_CFG] = 0x00,
222 [DMA_SCB_BURST_SIZE] = 0x0C,
223 [DMA_ARB_CTRL] = 0x2C,
224 [DMA_PRIORITY_0] = 0x30,
225 [DMA_PRIORITY_1] = 0x34,
226 [DMA_PRIORITY_2] = 0x38,
227 [DMA_RING0_TIMEOUT] = 0x2C,
228 [DMA_RING1_TIMEOUT] = 0x30,
229 [DMA_RING2_TIMEOUT] = 0x34,
230 [DMA_RING3_TIMEOUT] = 0x38,
231 [DMA_RING4_TIMEOUT] = 0x3c,
232 [DMA_RING5_TIMEOUT] = 0x40,
233 [DMA_RING6_TIMEOUT] = 0x44,
234 [DMA_RING7_TIMEOUT] = 0x48,
235 [DMA_RING8_TIMEOUT] = 0x4c,
236 [DMA_RING9_TIMEOUT] = 0x50,
237 [DMA_RING10_TIMEOUT] = 0x54,
238 [DMA_RING11_TIMEOUT] = 0x58,
239 [DMA_RING12_TIMEOUT] = 0x5c,
240 [DMA_RING13_TIMEOUT] = 0x60,
241 [DMA_RING14_TIMEOUT] = 0x64,
242 [DMA_RING15_TIMEOUT] = 0x68,
243 [DMA_RING16_TIMEOUT] = 0x6C,
244 [DMA_INDEX2RING_0] = 0x70,
245 [DMA_INDEX2RING_1] = 0x74,
246 [DMA_INDEX2RING_2] = 0x78,
247 [DMA_INDEX2RING_3] = 0x7C,
248 [DMA_INDEX2RING_4] = 0x80,
249 [DMA_INDEX2RING_5] = 0x84,
250 [DMA_INDEX2RING_6] = 0x88,
251 [DMA_INDEX2RING_7] = 0x8C,
254 static const u8 bcmgenet_dma_regs_v2[] = {
255 [DMA_RING_CFG] = 0x00,
258 [DMA_SCB_BURST_SIZE] = 0x0C,
259 [DMA_ARB_CTRL] = 0x30,
260 [DMA_PRIORITY_0] = 0x34,
261 [DMA_PRIORITY_1] = 0x38,
262 [DMA_PRIORITY_2] = 0x3C,
263 [DMA_RING0_TIMEOUT] = 0x2C,
264 [DMA_RING1_TIMEOUT] = 0x30,
265 [DMA_RING2_TIMEOUT] = 0x34,
266 [DMA_RING3_TIMEOUT] = 0x38,
267 [DMA_RING4_TIMEOUT] = 0x3c,
268 [DMA_RING5_TIMEOUT] = 0x40,
269 [DMA_RING6_TIMEOUT] = 0x44,
270 [DMA_RING7_TIMEOUT] = 0x48,
271 [DMA_RING8_TIMEOUT] = 0x4c,
272 [DMA_RING9_TIMEOUT] = 0x50,
273 [DMA_RING10_TIMEOUT] = 0x54,
274 [DMA_RING11_TIMEOUT] = 0x58,
275 [DMA_RING12_TIMEOUT] = 0x5c,
276 [DMA_RING13_TIMEOUT] = 0x60,
277 [DMA_RING14_TIMEOUT] = 0x64,
278 [DMA_RING15_TIMEOUT] = 0x68,
279 [DMA_RING16_TIMEOUT] = 0x6C,
282 static const u8 bcmgenet_dma_regs_v1[] = {
285 [DMA_SCB_BURST_SIZE] = 0x0C,
286 [DMA_ARB_CTRL] = 0x30,
287 [DMA_PRIORITY_0] = 0x34,
288 [DMA_PRIORITY_1] = 0x38,
289 [DMA_PRIORITY_2] = 0x3C,
290 [DMA_RING0_TIMEOUT] = 0x2C,
291 [DMA_RING1_TIMEOUT] = 0x30,
292 [DMA_RING2_TIMEOUT] = 0x34,
293 [DMA_RING3_TIMEOUT] = 0x38,
294 [DMA_RING4_TIMEOUT] = 0x3c,
295 [DMA_RING5_TIMEOUT] = 0x40,
296 [DMA_RING6_TIMEOUT] = 0x44,
297 [DMA_RING7_TIMEOUT] = 0x48,
298 [DMA_RING8_TIMEOUT] = 0x4c,
299 [DMA_RING9_TIMEOUT] = 0x50,
300 [DMA_RING10_TIMEOUT] = 0x54,
301 [DMA_RING11_TIMEOUT] = 0x58,
302 [DMA_RING12_TIMEOUT] = 0x5c,
303 [DMA_RING13_TIMEOUT] = 0x60,
304 [DMA_RING14_TIMEOUT] = 0x64,
305 [DMA_RING15_TIMEOUT] = 0x68,
306 [DMA_RING16_TIMEOUT] = 0x6C,
309 /* Set at runtime once bcmgenet version is known */
310 static const u8 *bcmgenet_dma_regs;
312 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
314 return netdev_priv(dev_get_drvdata(dev));
317 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
320 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
321 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
324 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
325 u32 val, enum dma_reg r)
327 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
328 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
334 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
335 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
339 u32 val, enum dma_reg r)
341 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
342 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345 /* RDMA/TDMA ring registers and accessors
346 * we merge the common fields and just prefix with T/D the registers
347 * having different meaning depending on the direction
351 RDMA_WRITE_PTR = TDMA_READ_PTR,
353 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
355 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
357 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
363 DMA_MBUF_DONE_THRESH,
365 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
367 RDMA_READ_PTR = TDMA_WRITE_PTR,
369 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
372 /* GENET v4 supports 40-bits pointer addressing
373 * for obvious reasons the LO and HI word parts
374 * are contiguous, but this offsets the other
377 static const u8 genet_dma_ring_regs_v4[] = {
378 [TDMA_READ_PTR] = 0x00,
379 [TDMA_READ_PTR_HI] = 0x04,
380 [TDMA_CONS_INDEX] = 0x08,
381 [TDMA_PROD_INDEX] = 0x0C,
382 [DMA_RING_BUF_SIZE] = 0x10,
383 [DMA_START_ADDR] = 0x14,
384 [DMA_START_ADDR_HI] = 0x18,
385 [DMA_END_ADDR] = 0x1C,
386 [DMA_END_ADDR_HI] = 0x20,
387 [DMA_MBUF_DONE_THRESH] = 0x24,
388 [TDMA_FLOW_PERIOD] = 0x28,
389 [TDMA_WRITE_PTR] = 0x2C,
390 [TDMA_WRITE_PTR_HI] = 0x30,
393 static const u8 genet_dma_ring_regs_v123[] = {
394 [TDMA_READ_PTR] = 0x00,
395 [TDMA_CONS_INDEX] = 0x04,
396 [TDMA_PROD_INDEX] = 0x08,
397 [DMA_RING_BUF_SIZE] = 0x0C,
398 [DMA_START_ADDR] = 0x10,
399 [DMA_END_ADDR] = 0x14,
400 [DMA_MBUF_DONE_THRESH] = 0x18,
401 [TDMA_FLOW_PERIOD] = 0x1C,
402 [TDMA_WRITE_PTR] = 0x20,
405 /* Set at runtime once GENET version is known */
406 static const u8 *genet_dma_ring_regs;
408 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
412 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
413 (DMA_RING_SIZE * ring) +
414 genet_dma_ring_regs[r]);
417 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
418 unsigned int ring, u32 val,
421 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
426 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
430 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
435 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
436 unsigned int ring, u32 val,
439 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
444 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
449 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
450 reg = bcmgenet_hfb_reg_readl(priv, offset);
451 reg |= (1 << (f_index % 32));
452 bcmgenet_hfb_reg_writel(priv, reg, offset);
453 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
455 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
458 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
460 u32 offset, reg, reg1;
462 offset = HFB_FLT_ENABLE_V3PLUS;
463 reg = bcmgenet_hfb_reg_readl(priv, offset);
464 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
466 reg1 &= ~(1 << (f_index % 32));
467 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
469 reg &= ~(1 << (f_index % 32));
470 bcmgenet_hfb_reg_writel(priv, reg, offset);
473 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
475 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
479 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
480 u32 f_index, u32 rx_queue)
485 offset = f_index / 8;
486 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
487 reg &= ~(0xF << (4 * (f_index % 8)));
488 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
489 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
492 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
493 u32 f_index, u32 f_length)
498 offset = HFB_FLT_LEN_V3PLUS +
499 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
501 reg = bcmgenet_hfb_reg_readl(priv, offset);
502 reg &= ~(0xFF << (8 * (f_index % 4)));
503 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
504 bcmgenet_hfb_reg_writel(priv, reg, offset);
507 static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
510 switch (*(unsigned char *)mask++) {
525 #define VALIDATE_MASK(x) \
526 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
528 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
529 u32 offset, void *val, void *mask,
534 index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
535 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
540 tmp |= (*(unsigned char *)val++);
541 switch ((*(unsigned char *)mask++)) {
552 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
554 tmp = bcmgenet_hfb_readl(priv,
555 index * sizeof(u32));
558 tmp |= (*(unsigned char *)val++) << 8;
559 switch ((*(unsigned char *)mask++)) {
571 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
578 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
579 struct bcmgenet_rxnfc_rule *rule)
581 struct ethtool_rx_flow_spec *fs = &rule->fs;
582 u32 offset = 0, f_length = 0, f;
589 if (fs->flow_type & FLOW_MAC_EXT) {
590 bcmgenet_hfb_insert_data(priv, f, 0,
591 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
592 sizeof(fs->h_ext.h_dest));
595 if (fs->flow_type & FLOW_EXT) {
596 if (fs->m_ext.vlan_etype ||
597 fs->m_ext.vlan_tci) {
598 bcmgenet_hfb_insert_data(priv, f, 12,
599 &fs->h_ext.vlan_etype,
600 &fs->m_ext.vlan_etype,
601 sizeof(fs->h_ext.vlan_etype));
602 bcmgenet_hfb_insert_data(priv, f, 14,
605 sizeof(fs->h_ext.vlan_tci));
607 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
611 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
613 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
614 bcmgenet_hfb_insert_data(priv, f, 0,
615 &fs->h_u.ether_spec.h_dest,
616 &fs->m_u.ether_spec.h_dest,
617 sizeof(fs->h_u.ether_spec.h_dest));
618 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
619 &fs->h_u.ether_spec.h_source,
620 &fs->m_u.ether_spec.h_source,
621 sizeof(fs->h_u.ether_spec.h_source));
622 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
623 &fs->h_u.ether_spec.h_proto,
624 &fs->m_u.ether_spec.h_proto,
625 sizeof(fs->h_u.ether_spec.h_proto));
628 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
629 /* Specify IP Ether Type */
630 val_16 = htons(ETH_P_IP);
632 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
633 &val_16, &mask_16, sizeof(val_16));
634 bcmgenet_hfb_insert_data(priv, f, 15 + offset,
635 &fs->h_u.usr_ip4_spec.tos,
636 &fs->m_u.usr_ip4_spec.tos,
637 sizeof(fs->h_u.usr_ip4_spec.tos));
638 bcmgenet_hfb_insert_data(priv, f, 23 + offset,
639 &fs->h_u.usr_ip4_spec.proto,
640 &fs->m_u.usr_ip4_spec.proto,
641 sizeof(fs->h_u.usr_ip4_spec.proto));
642 bcmgenet_hfb_insert_data(priv, f, 26 + offset,
643 &fs->h_u.usr_ip4_spec.ip4src,
644 &fs->m_u.usr_ip4_spec.ip4src,
645 sizeof(fs->h_u.usr_ip4_spec.ip4src));
646 bcmgenet_hfb_insert_data(priv, f, 30 + offset,
647 &fs->h_u.usr_ip4_spec.ip4dst,
648 &fs->m_u.usr_ip4_spec.ip4dst,
649 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
650 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
653 /* Only supports 20 byte IPv4 header */
656 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
659 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
660 bcmgenet_hfb_insert_data(priv, f,
661 ETH_HLEN + 20 + offset,
662 &fs->h_u.usr_ip4_spec.l4_4_bytes,
663 &fs->m_u.usr_ip4_spec.l4_4_bytes,
665 f_length += DIV_ROUND_UP(size, 2);
669 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
670 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
671 /* Ring 0 flows can be handled by the default Descriptor Ring
672 * We'll map them to ring 0, but don't enable the filter
674 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0);
675 rule->state = BCMGENET_RXNFC_STATE_DISABLED;
677 /* Other Rx rings are direct mapped here */
678 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f,
680 bcmgenet_hfb_enable_filter(priv, f);
681 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
685 /* bcmgenet_hfb_clear
687 * Clear Hardware Filter Block and disable all filtering.
689 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
693 base = f_index * priv->hw_params->hfb_filter_size;
694 for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
695 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
698 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
702 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
705 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
706 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
707 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
709 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
710 bcmgenet_rdma_writel(priv, 0x0, i);
712 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
713 bcmgenet_hfb_reg_writel(priv, 0x0,
714 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
716 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
717 bcmgenet_hfb_clear_filter(priv, i);
720 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
724 INIT_LIST_HEAD(&priv->rxnfc_list);
725 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
728 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
729 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
730 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
733 bcmgenet_hfb_clear(priv);
736 static int bcmgenet_begin(struct net_device *dev)
738 struct bcmgenet_priv *priv = netdev_priv(dev);
740 /* Turn on the clock */
741 return clk_prepare_enable(priv->clk);
744 static void bcmgenet_complete(struct net_device *dev)
746 struct bcmgenet_priv *priv = netdev_priv(dev);
748 /* Turn off the clock */
749 clk_disable_unprepare(priv->clk);
752 static int bcmgenet_get_link_ksettings(struct net_device *dev,
753 struct ethtool_link_ksettings *cmd)
755 if (!netif_running(dev))
761 phy_ethtool_ksettings_get(dev->phydev, cmd);
766 static int bcmgenet_set_link_ksettings(struct net_device *dev,
767 const struct ethtool_link_ksettings *cmd)
769 if (!netif_running(dev))
775 return phy_ethtool_ksettings_set(dev->phydev, cmd);
778 static int bcmgenet_set_features(struct net_device *dev,
779 netdev_features_t features)
781 struct bcmgenet_priv *priv = netdev_priv(dev);
785 ret = clk_prepare_enable(priv->clk);
789 /* Make sure we reflect the value of CRC_CMD_FWD */
790 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
791 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
793 clk_disable_unprepare(priv->clk);
798 static u32 bcmgenet_get_msglevel(struct net_device *dev)
800 struct bcmgenet_priv *priv = netdev_priv(dev);
802 return priv->msg_enable;
805 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
807 struct bcmgenet_priv *priv = netdev_priv(dev);
809 priv->msg_enable = level;
812 static int bcmgenet_get_coalesce(struct net_device *dev,
813 struct ethtool_coalesce *ec,
814 struct kernel_ethtool_coalesce *kernel_coal,
815 struct netlink_ext_ack *extack)
817 struct bcmgenet_priv *priv = netdev_priv(dev);
818 struct bcmgenet_rx_ring *ring;
821 ec->tx_max_coalesced_frames =
822 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
823 DMA_MBUF_DONE_THRESH);
824 ec->rx_max_coalesced_frames =
825 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
826 DMA_MBUF_DONE_THRESH);
827 ec->rx_coalesce_usecs =
828 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
830 for (i = 0; i < priv->hw_params->rx_queues; i++) {
831 ring = &priv->rx_rings[i];
832 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
834 ring = &priv->rx_rings[DESC_INDEX];
835 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
840 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
843 struct bcmgenet_priv *priv = ring->priv;
844 unsigned int i = ring->index;
847 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
849 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
850 reg &= ~DMA_TIMEOUT_MASK;
851 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
852 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
855 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
856 struct ethtool_coalesce *ec)
858 struct dim_cq_moder moder;
861 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
862 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
863 usecs = ring->rx_coalesce_usecs;
864 pkts = ring->rx_max_coalesced_frames;
866 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
867 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
872 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
873 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
876 static int bcmgenet_set_coalesce(struct net_device *dev,
877 struct ethtool_coalesce *ec,
878 struct kernel_ethtool_coalesce *kernel_coal,
879 struct netlink_ext_ack *extack)
881 struct bcmgenet_priv *priv = netdev_priv(dev);
884 /* Base system clock is 125Mhz, DMA timeout is this reference clock
885 * divided by 1024, which yields roughly 8.192us, our maximum value
886 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
888 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
889 ec->tx_max_coalesced_frames == 0 ||
890 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
891 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
894 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
897 /* GENET TDMA hardware does not support a configurable timeout, but will
898 * always generate an interrupt either after MBDONE packets have been
899 * transmitted, or when the ring is empty.
902 /* Program all TX queues with the same values, as there is no
903 * ethtool knob to do coalescing on a per-queue basis
905 for (i = 0; i < priv->hw_params->tx_queues; i++)
906 bcmgenet_tdma_ring_writel(priv, i,
907 ec->tx_max_coalesced_frames,
908 DMA_MBUF_DONE_THRESH);
909 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
910 ec->tx_max_coalesced_frames,
911 DMA_MBUF_DONE_THRESH);
913 for (i = 0; i < priv->hw_params->rx_queues; i++)
914 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
915 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
920 static void bcmgenet_get_pauseparam(struct net_device *dev,
921 struct ethtool_pauseparam *epause)
923 struct bcmgenet_priv *priv;
926 priv = netdev_priv(dev);
928 epause->autoneg = priv->autoneg_pause;
930 if (netif_carrier_ok(dev)) {
931 /* report active state when link is up */
932 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
933 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
934 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
936 /* otherwise report stored settings */
937 epause->tx_pause = priv->tx_pause;
938 epause->rx_pause = priv->rx_pause;
942 static int bcmgenet_set_pauseparam(struct net_device *dev,
943 struct ethtool_pauseparam *epause)
945 struct bcmgenet_priv *priv = netdev_priv(dev);
950 if (!phy_validate_pause(dev->phydev, epause))
953 priv->autoneg_pause = !!epause->autoneg;
954 priv->tx_pause = !!epause->tx_pause;
955 priv->rx_pause = !!epause->rx_pause;
957 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
962 /* standard ethtool support functions. */
963 enum bcmgenet_stat_type {
964 BCMGENET_STAT_NETDEV = -1,
965 BCMGENET_STAT_MIB_RX,
966 BCMGENET_STAT_MIB_TX,
972 struct bcmgenet_stats {
973 char stat_string[ETH_GSTRING_LEN];
976 enum bcmgenet_stat_type type;
977 /* reg offset from UMAC base for misc counters */
981 #define STAT_NETDEV(m) { \
982 .stat_string = __stringify(m), \
983 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
984 .stat_offset = offsetof(struct net_device_stats, m), \
985 .type = BCMGENET_STAT_NETDEV, \
988 #define STAT_GENET_MIB(str, m, _type) { \
989 .stat_string = str, \
990 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
991 .stat_offset = offsetof(struct bcmgenet_priv, m), \
995 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
996 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
997 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
998 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1000 #define STAT_GENET_MISC(str, m, offset) { \
1001 .stat_string = str, \
1002 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1003 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1004 .type = BCMGENET_STAT_MISC, \
1005 .reg_offset = offset, \
1008 #define STAT_GENET_Q(num) \
1009 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
1010 tx_rings[num].packets), \
1011 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
1012 tx_rings[num].bytes), \
1013 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
1014 rx_rings[num].bytes), \
1015 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
1016 rx_rings[num].packets), \
1017 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1018 rx_rings[num].errors), \
1019 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1020 rx_rings[num].dropped)
1022 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
1023 * between the end of TX stats and the beginning of the RX RUNT
1025 #define BCMGENET_STAT_OFFSET 0xc
1027 /* Hardware counters must be kept in sync because the order/offset
1028 * is important here (order in structure declaration = order in hardware)
1030 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1032 STAT_NETDEV(rx_packets),
1033 STAT_NETDEV(tx_packets),
1034 STAT_NETDEV(rx_bytes),
1035 STAT_NETDEV(tx_bytes),
1036 STAT_NETDEV(rx_errors),
1037 STAT_NETDEV(tx_errors),
1038 STAT_NETDEV(rx_dropped),
1039 STAT_NETDEV(tx_dropped),
1040 STAT_NETDEV(multicast),
1041 /* UniMAC RSV counters */
1042 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1043 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1044 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1045 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1046 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1047 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1048 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1049 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1050 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1051 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1052 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1053 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1054 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1055 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1056 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1057 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1058 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1059 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1060 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1061 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1062 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1063 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1064 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1065 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1066 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1067 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1068 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1069 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1070 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1071 /* UniMAC TSV counters */
1072 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1073 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1074 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1075 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1076 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1077 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1078 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1079 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1080 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1081 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1082 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1083 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1084 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1085 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1086 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1087 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1088 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1089 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1090 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1091 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1092 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1093 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1094 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1095 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1096 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1097 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1098 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1099 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1100 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1101 /* UniMAC RUNT counters */
1102 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1103 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1104 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1105 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1106 /* Misc UniMAC counters */
1107 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
1108 UMAC_RBUF_OVFL_CNT_V1),
1109 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1110 UMAC_RBUF_ERR_CNT_V1),
1111 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
1112 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1113 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1114 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1115 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1116 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1117 mib.tx_realloc_tsb_failed),
1126 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1128 static void bcmgenet_get_drvinfo(struct net_device *dev,
1129 struct ethtool_drvinfo *info)
1131 strscpy(info->driver, "bcmgenet", sizeof(info->driver));
1134 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1136 switch (string_set) {
1138 return BCMGENET_STATS_LEN;
1144 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1149 switch (stringset) {
1151 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1152 memcpy(data + i * ETH_GSTRING_LEN,
1153 bcmgenet_gstrings_stats[i].stat_string,
1160 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1166 case UMAC_RBUF_OVFL_CNT_V1:
1167 if (GENET_IS_V2(priv))
1168 new_offset = RBUF_OVFL_CNT_V2;
1170 new_offset = RBUF_OVFL_CNT_V3PLUS;
1172 val = bcmgenet_rbuf_readl(priv, new_offset);
1173 /* clear if overflowed */
1175 bcmgenet_rbuf_writel(priv, 0, new_offset);
1177 case UMAC_RBUF_ERR_CNT_V1:
1178 if (GENET_IS_V2(priv))
1179 new_offset = RBUF_ERR_CNT_V2;
1181 new_offset = RBUF_ERR_CNT_V3PLUS;
1183 val = bcmgenet_rbuf_readl(priv, new_offset);
1184 /* clear if overflowed */
1186 bcmgenet_rbuf_writel(priv, 0, new_offset);
1189 val = bcmgenet_umac_readl(priv, offset);
1190 /* clear if overflowed */
1192 bcmgenet_umac_writel(priv, 0, offset);
1199 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1203 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1204 const struct bcmgenet_stats *s;
1209 s = &bcmgenet_gstrings_stats[i];
1211 case BCMGENET_STAT_NETDEV:
1212 case BCMGENET_STAT_SOFT:
1214 case BCMGENET_STAT_RUNT:
1215 offset += BCMGENET_STAT_OFFSET;
1217 case BCMGENET_STAT_MIB_TX:
1218 offset += BCMGENET_STAT_OFFSET;
1220 case BCMGENET_STAT_MIB_RX:
1221 val = bcmgenet_umac_readl(priv,
1222 UMAC_MIB_START + j + offset);
1223 offset = 0; /* Reset Offset */
1225 case BCMGENET_STAT_MISC:
1226 if (GENET_IS_V1(priv)) {
1227 val = bcmgenet_umac_readl(priv, s->reg_offset);
1228 /* clear if overflowed */
1230 bcmgenet_umac_writel(priv, 0,
1233 val = bcmgenet_update_stat_misc(priv,
1239 j += s->stat_sizeof;
1240 p = (char *)priv + s->stat_offset;
1245 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
1246 struct ethtool_stats *stats,
1249 struct bcmgenet_priv *priv = netdev_priv(dev);
1252 if (netif_running(dev))
1253 bcmgenet_update_mib_counters(priv);
1255 dev->netdev_ops->ndo_get_stats(dev);
1257 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1258 const struct bcmgenet_stats *s;
1261 s = &bcmgenet_gstrings_stats[i];
1262 if (s->type == BCMGENET_STAT_NETDEV)
1263 p = (char *)&dev->stats;
1266 p += s->stat_offset;
1267 if (sizeof(unsigned long) != sizeof(u32) &&
1268 s->stat_sizeof == sizeof(unsigned long))
1269 data[i] = *(unsigned long *)p;
1271 data[i] = *(u32 *)p;
1275 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
1276 bool tx_lpi_enabled)
1278 struct bcmgenet_priv *priv = netdev_priv(dev);
1279 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1282 if (enable && !priv->clk_eee_enabled) {
1283 clk_prepare_enable(priv->clk_eee);
1284 priv->clk_eee_enabled = true;
1287 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1292 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1294 /* Enable EEE and switch to a 27Mhz clock automatically */
1295 reg = bcmgenet_readl(priv->base + off);
1297 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1299 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1300 bcmgenet_writel(reg, priv->base + off);
1302 /* Do the same for thing for RBUF */
1303 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1305 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1307 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1308 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1310 if (!enable && priv->clk_eee_enabled) {
1311 clk_disable_unprepare(priv->clk_eee);
1312 priv->clk_eee_enabled = false;
1315 priv->eee.eee_enabled = enable;
1316 priv->eee.eee_active = enable;
1317 priv->eee.tx_lpi_enabled = tx_lpi_enabled;
1320 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1322 struct bcmgenet_priv *priv = netdev_priv(dev);
1323 struct ethtool_eee *p = &priv->eee;
1325 if (GENET_IS_V1(priv))
1331 e->eee_enabled = p->eee_enabled;
1332 e->eee_active = p->eee_active;
1333 e->tx_lpi_enabled = p->tx_lpi_enabled;
1334 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1336 return phy_ethtool_get_eee(dev->phydev, e);
1339 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1341 struct bcmgenet_priv *priv = netdev_priv(dev);
1342 struct ethtool_eee *p = &priv->eee;
1344 if (GENET_IS_V1(priv))
1350 p->eee_enabled = e->eee_enabled;
1352 if (!p->eee_enabled) {
1353 bcmgenet_eee_enable_set(dev, false, false);
1355 p->eee_active = phy_init_eee(dev->phydev, false) >= 0;
1356 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1357 bcmgenet_eee_enable_set(dev, p->eee_active, e->tx_lpi_enabled);
1360 return phy_ethtool_set_eee(dev->phydev, e);
1363 static int bcmgenet_validate_flow(struct net_device *dev,
1364 struct ethtool_rxnfc *cmd)
1366 struct ethtool_usrip4_spec *l4_mask;
1367 struct ethhdr *eth_mask;
1369 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES &&
1370 cmd->fs.location != RX_CLS_LOC_ANY) {
1371 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1376 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1378 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1379 /* don't allow mask which isn't valid */
1380 if (VALIDATE_MASK(l4_mask->ip4src) ||
1381 VALIDATE_MASK(l4_mask->ip4dst) ||
1382 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1383 VALIDATE_MASK(l4_mask->proto) ||
1384 VALIDATE_MASK(l4_mask->ip_ver) ||
1385 VALIDATE_MASK(l4_mask->tos)) {
1386 netdev_err(dev, "rxnfc: Unsupported mask\n");
1391 eth_mask = &cmd->fs.m_u.ether_spec;
1392 /* don't allow mask which isn't valid */
1393 if (VALIDATE_MASK(eth_mask->h_dest) ||
1394 VALIDATE_MASK(eth_mask->h_source) ||
1395 VALIDATE_MASK(eth_mask->h_proto)) {
1396 netdev_err(dev, "rxnfc: Unsupported mask\n");
1401 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1406 if ((cmd->fs.flow_type & FLOW_EXT)) {
1407 /* don't allow mask which isn't valid */
1408 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1409 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1410 netdev_err(dev, "rxnfc: Unsupported mask\n");
1413 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1414 netdev_err(dev, "rxnfc: user-def not supported\n");
1419 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1420 /* don't allow mask which isn't valid */
1421 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1422 netdev_err(dev, "rxnfc: Unsupported mask\n");
1430 static int bcmgenet_insert_flow(struct net_device *dev,
1431 struct ethtool_rxnfc *cmd)
1433 struct bcmgenet_priv *priv = netdev_priv(dev);
1434 struct bcmgenet_rxnfc_rule *loc_rule;
1437 if (priv->hw_params->hfb_filter_size < 128) {
1438 netdev_err(dev, "rxnfc: Not supported by this device\n");
1442 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1443 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
1444 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1445 cmd->fs.ring_cookie);
1449 err = bcmgenet_validate_flow(dev, cmd);
1453 if (cmd->fs.location == RX_CLS_LOC_ANY) {
1454 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) {
1455 cmd->fs.location = loc_rule->fs.location;
1456 err = memcmp(&loc_rule->fs, &cmd->fs,
1457 sizeof(struct ethtool_rx_flow_spec));
1459 /* rule exists so return current location */
1462 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1463 loc_rule = &priv->rxnfc_rules[i];
1464 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1465 cmd->fs.location = i;
1469 if (i == MAX_NUM_OF_FS_RULES) {
1470 cmd->fs.location = RX_CLS_LOC_ANY;
1474 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1476 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1477 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1478 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1479 list_del(&loc_rule->list);
1480 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1482 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1483 memcpy(&loc_rule->fs, &cmd->fs,
1484 sizeof(struct ethtool_rx_flow_spec));
1486 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1488 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1493 static int bcmgenet_delete_flow(struct net_device *dev,
1494 struct ethtool_rxnfc *cmd)
1496 struct bcmgenet_priv *priv = netdev_priv(dev);
1497 struct bcmgenet_rxnfc_rule *rule;
1500 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1503 rule = &priv->rxnfc_rules[cmd->fs.location];
1504 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1509 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1510 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1511 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1512 list_del(&rule->list);
1513 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1515 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1516 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1522 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1524 struct bcmgenet_priv *priv = netdev_priv(dev);
1528 case ETHTOOL_SRXCLSRLINS:
1529 err = bcmgenet_insert_flow(dev, cmd);
1531 case ETHTOOL_SRXCLSRLDEL:
1532 err = bcmgenet_delete_flow(dev, cmd);
1535 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1543 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1546 struct bcmgenet_priv *priv = netdev_priv(dev);
1547 struct bcmgenet_rxnfc_rule *rule;
1550 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1553 rule = &priv->rxnfc_rules[loc];
1554 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1557 memcpy(&cmd->fs, &rule->fs,
1558 sizeof(struct ethtool_rx_flow_spec));
1563 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1565 struct list_head *pos;
1568 list_for_each(pos, &priv->rxnfc_list)
1574 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1577 struct bcmgenet_priv *priv = netdev_priv(dev);
1578 struct bcmgenet_rxnfc_rule *rule;
1583 case ETHTOOL_GRXRINGS:
1584 cmd->data = priv->hw_params->rx_queues ?: 1;
1586 case ETHTOOL_GRXCLSRLCNT:
1587 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1588 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL;
1590 case ETHTOOL_GRXCLSRULE:
1591 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1593 case ETHTOOL_GRXCLSRLALL:
1594 list_for_each_entry(rule, &priv->rxnfc_list, list)
1595 if (i < cmd->rule_cnt)
1596 rule_locs[i++] = rule->fs.location;
1598 cmd->data = MAX_NUM_OF_FS_RULES;
1608 /* standard ethtool support functions. */
1609 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1610 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1611 ETHTOOL_COALESCE_MAX_FRAMES |
1612 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1613 .begin = bcmgenet_begin,
1614 .complete = bcmgenet_complete,
1615 .get_strings = bcmgenet_get_strings,
1616 .get_sset_count = bcmgenet_get_sset_count,
1617 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1618 .get_drvinfo = bcmgenet_get_drvinfo,
1619 .get_link = ethtool_op_get_link,
1620 .get_msglevel = bcmgenet_get_msglevel,
1621 .set_msglevel = bcmgenet_set_msglevel,
1622 .get_wol = bcmgenet_get_wol,
1623 .set_wol = bcmgenet_set_wol,
1624 .get_eee = bcmgenet_get_eee,
1625 .set_eee = bcmgenet_set_eee,
1626 .nway_reset = phy_ethtool_nway_reset,
1627 .get_coalesce = bcmgenet_get_coalesce,
1628 .set_coalesce = bcmgenet_set_coalesce,
1629 .get_link_ksettings = bcmgenet_get_link_ksettings,
1630 .set_link_ksettings = bcmgenet_set_link_ksettings,
1631 .get_ts_info = ethtool_op_get_ts_info,
1632 .get_rxnfc = bcmgenet_get_rxnfc,
1633 .set_rxnfc = bcmgenet_set_rxnfc,
1634 .get_pauseparam = bcmgenet_get_pauseparam,
1635 .set_pauseparam = bcmgenet_set_pauseparam,
1638 /* Power down the unimac, based on mode. */
1639 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1640 enum bcmgenet_power_mode mode)
1646 case GENET_POWER_CABLE_SENSE:
1647 phy_detach(priv->dev->phydev);
1650 case GENET_POWER_WOL_MAGIC:
1651 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1654 case GENET_POWER_PASSIVE:
1655 /* Power down LED */
1656 if (priv->hw_params->flags & GENET_HAS_EXT) {
1657 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1658 if (GENET_IS_V5(priv) && !priv->ephy_16nm)
1659 reg |= EXT_PWR_DOWN_PHY_EN |
1660 EXT_PWR_DOWN_PHY_RD |
1661 EXT_PWR_DOWN_PHY_SD |
1662 EXT_PWR_DOWN_PHY_RX |
1663 EXT_PWR_DOWN_PHY_TX |
1666 reg |= EXT_PWR_DOWN_PHY;
1668 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1669 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1671 bcmgenet_phy_power_set(priv->dev, false);
1681 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1682 enum bcmgenet_power_mode mode)
1686 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1689 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1692 case GENET_POWER_PASSIVE:
1693 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1694 EXT_ENERGY_DET_MASK);
1695 if (GENET_IS_V5(priv) && !priv->ephy_16nm) {
1696 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1697 EXT_PWR_DOWN_PHY_RD |
1698 EXT_PWR_DOWN_PHY_SD |
1699 EXT_PWR_DOWN_PHY_RX |
1700 EXT_PWR_DOWN_PHY_TX |
1702 reg |= EXT_PHY_RESET;
1703 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1706 reg &= ~EXT_PHY_RESET;
1708 reg &= ~EXT_PWR_DOWN_PHY;
1709 reg |= EXT_PWR_DN_EN_LD;
1711 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1712 bcmgenet_phy_power_set(priv->dev, true);
1715 case GENET_POWER_CABLE_SENSE:
1717 if (!GENET_IS_V5(priv)) {
1718 reg |= EXT_PWR_DN_EN_LD;
1719 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1722 case GENET_POWER_WOL_MAGIC:
1723 bcmgenet_wol_power_up_cfg(priv, mode);
1730 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1731 struct bcmgenet_tx_ring *ring)
1733 struct enet_cb *tx_cb_ptr;
1735 tx_cb_ptr = ring->cbs;
1736 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1738 /* Advancing local write pointer */
1739 if (ring->write_ptr == ring->end_ptr)
1740 ring->write_ptr = ring->cb_ptr;
1747 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1748 struct bcmgenet_tx_ring *ring)
1750 struct enet_cb *tx_cb_ptr;
1752 tx_cb_ptr = ring->cbs;
1753 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1755 /* Rewinding local write pointer */
1756 if (ring->write_ptr == ring->cb_ptr)
1757 ring->write_ptr = ring->end_ptr;
1764 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1766 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1767 INTRL2_CPU_MASK_SET);
1770 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1772 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1773 INTRL2_CPU_MASK_CLEAR);
1776 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1778 bcmgenet_intrl2_1_writel(ring->priv,
1779 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1780 INTRL2_CPU_MASK_SET);
1783 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1785 bcmgenet_intrl2_1_writel(ring->priv,
1786 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1787 INTRL2_CPU_MASK_CLEAR);
1790 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1792 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1793 INTRL2_CPU_MASK_SET);
1796 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1798 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1799 INTRL2_CPU_MASK_CLEAR);
1802 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1804 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1805 INTRL2_CPU_MASK_CLEAR);
1808 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1810 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1811 INTRL2_CPU_MASK_SET);
1814 /* Simple helper to free a transmit control block's resources
1815 * Returns an skb when the last transmit control block associated with the
1816 * skb is freed. The skb should be freed by the caller if necessary.
1818 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1821 struct sk_buff *skb;
1827 if (cb == GENET_CB(skb)->first_cb)
1828 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1829 dma_unmap_len(cb, dma_len),
1832 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1833 dma_unmap_len(cb, dma_len),
1835 dma_unmap_addr_set(cb, dma_addr, 0);
1837 if (cb == GENET_CB(skb)->last_cb)
1840 } else if (dma_unmap_addr(cb, dma_addr)) {
1842 dma_unmap_addr(cb, dma_addr),
1843 dma_unmap_len(cb, dma_len),
1845 dma_unmap_addr_set(cb, dma_addr, 0);
1851 /* Simple helper to free a receive control block's resources */
1852 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1855 struct sk_buff *skb;
1860 if (dma_unmap_addr(cb, dma_addr)) {
1861 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1862 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1863 dma_unmap_addr_set(cb, dma_addr, 0);
1869 /* Unlocked version of the reclaim routine */
1870 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1871 struct bcmgenet_tx_ring *ring)
1873 struct bcmgenet_priv *priv = netdev_priv(dev);
1874 unsigned int txbds_processed = 0;
1875 unsigned int bytes_compl = 0;
1876 unsigned int pkts_compl = 0;
1877 unsigned int txbds_ready;
1878 unsigned int c_index;
1879 struct sk_buff *skb;
1881 /* Clear status before servicing to reduce spurious interrupts */
1882 if (ring->index == DESC_INDEX)
1883 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1886 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1889 /* Compute how many buffers are transmitted since last xmit call */
1890 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1892 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1894 netif_dbg(priv, tx_done, dev,
1895 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1896 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1898 /* Reclaim transmitted buffers */
1899 while (txbds_processed < txbds_ready) {
1900 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1901 &priv->tx_cbs[ring->clean_ptr]);
1904 bytes_compl += GENET_CB(skb)->bytes_sent;
1905 dev_consume_skb_any(skb);
1909 if (likely(ring->clean_ptr < ring->end_ptr))
1912 ring->clean_ptr = ring->cb_ptr;
1915 ring->free_bds += txbds_processed;
1916 ring->c_index = c_index;
1918 ring->packets += pkts_compl;
1919 ring->bytes += bytes_compl;
1921 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1922 pkts_compl, bytes_compl);
1924 return txbds_processed;
1927 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1928 struct bcmgenet_tx_ring *ring)
1930 unsigned int released;
1932 spin_lock_bh(&ring->lock);
1933 released = __bcmgenet_tx_reclaim(dev, ring);
1934 spin_unlock_bh(&ring->lock);
1939 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1941 struct bcmgenet_tx_ring *ring =
1942 container_of(napi, struct bcmgenet_tx_ring, napi);
1943 unsigned int work_done = 0;
1944 struct netdev_queue *txq;
1946 spin_lock(&ring->lock);
1947 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1948 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1949 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1950 netif_tx_wake_queue(txq);
1952 spin_unlock(&ring->lock);
1954 if (work_done == 0) {
1955 napi_complete(napi);
1956 ring->int_enable(ring);
1964 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1966 struct bcmgenet_priv *priv = netdev_priv(dev);
1969 if (netif_is_multiqueue(dev)) {
1970 for (i = 0; i < priv->hw_params->tx_queues; i++)
1971 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1974 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1977 /* Reallocate the SKB to put enough headroom in front of it and insert
1978 * the transmit checksum offsets in the descriptors
1980 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1981 struct sk_buff *skb)
1983 struct bcmgenet_priv *priv = netdev_priv(dev);
1984 struct status_64 *status = NULL;
1985 struct sk_buff *new_skb;
1991 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1992 /* If 64 byte status block enabled, must make sure skb has
1993 * enough headroom for us to insert 64B status block.
1995 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1997 dev_kfree_skb_any(skb);
1998 priv->mib.tx_realloc_tsb_failed++;
1999 dev->stats.tx_dropped++;
2002 dev_consume_skb_any(skb);
2004 priv->mib.tx_realloc_tsb++;
2007 skb_push(skb, sizeof(*status));
2008 status = (struct status_64 *)skb->data;
2010 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2011 ip_ver = skb->protocol;
2013 case htons(ETH_P_IP):
2014 ip_proto = ip_hdr(skb)->protocol;
2016 case htons(ETH_P_IPV6):
2017 ip_proto = ipv6_hdr(skb)->nexthdr;
2020 /* don't use UDP flag */
2025 offset = skb_checksum_start_offset(skb) - sizeof(*status);
2026 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
2027 (offset + skb->csum_offset) |
2030 /* Set the special UDP flag for UDP */
2031 if (ip_proto == IPPROTO_UDP)
2032 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
2034 status->tx_csum_info = tx_csum_info;
2040 static void bcmgenet_hide_tsb(struct sk_buff *skb)
2042 __skb_pull(skb, sizeof(struct status_64));
2045 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2047 struct bcmgenet_priv *priv = netdev_priv(dev);
2048 struct device *kdev = &priv->pdev->dev;
2049 struct bcmgenet_tx_ring *ring = NULL;
2050 struct enet_cb *tx_cb_ptr;
2051 struct netdev_queue *txq;
2052 int nr_frags, index;
2060 index = skb_get_queue_mapping(skb);
2061 /* Mapping strategy:
2062 * queue_mapping = 0, unclassified, packet xmited through ring16
2063 * queue_mapping = 1, goes to ring 0. (highest priority queue
2064 * queue_mapping = 2, goes to ring 1.
2065 * queue_mapping = 3, goes to ring 2.
2066 * queue_mapping = 4, goes to ring 3.
2073 ring = &priv->tx_rings[index];
2074 txq = netdev_get_tx_queue(dev, ring->queue);
2076 nr_frags = skb_shinfo(skb)->nr_frags;
2078 spin_lock(&ring->lock);
2079 if (ring->free_bds <= (nr_frags + 1)) {
2080 if (!netif_tx_queue_stopped(txq))
2081 netif_tx_stop_queue(txq);
2082 ret = NETDEV_TX_BUSY;
2086 /* Retain how many bytes will be sent on the wire, without TSB inserted
2087 * by transmit checksum offload
2089 GENET_CB(skb)->bytes_sent = skb->len;
2091 /* add the Transmit Status Block */
2092 skb = bcmgenet_add_tsb(dev, skb);
2098 for (i = 0; i <= nr_frags; i++) {
2099 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
2104 /* Transmit single SKB or head of fragment list */
2105 GENET_CB(skb)->first_cb = tx_cb_ptr;
2106 size = skb_headlen(skb);
2107 mapping = dma_map_single(kdev, skb->data, size,
2111 frag = &skb_shinfo(skb)->frags[i - 1];
2112 size = skb_frag_size(frag);
2113 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2117 ret = dma_mapping_error(kdev, mapping);
2119 priv->mib.tx_dma_failed++;
2120 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
2122 goto out_unmap_frags;
2124 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2125 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2127 tx_cb_ptr->skb = skb;
2129 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2130 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2132 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
2133 * will need to restore software padding of "runt" packets
2135 len_stat |= DMA_TX_APPEND_CRC;
2138 len_stat |= DMA_SOP;
2139 if (skb->ip_summed == CHECKSUM_PARTIAL)
2140 len_stat |= DMA_TX_DO_CSUM;
2143 len_stat |= DMA_EOP;
2145 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
2148 GENET_CB(skb)->last_cb = tx_cb_ptr;
2150 bcmgenet_hide_tsb(skb);
2151 skb_tx_timestamp(skb);
2153 /* Decrement total BD count and advance our write pointer */
2154 ring->free_bds -= nr_frags + 1;
2155 ring->prod_index += nr_frags + 1;
2156 ring->prod_index &= DMA_P_INDEX_MASK;
2158 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2160 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
2161 netif_tx_stop_queue(txq);
2163 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
2164 /* Packets are ready, update producer index */
2165 bcmgenet_tdma_ring_writel(priv, ring->index,
2166 ring->prod_index, TDMA_PROD_INDEX);
2168 spin_unlock(&ring->lock);
2173 /* Back up for failed control block mapping */
2174 bcmgenet_put_txcb(priv, ring);
2176 /* Unmap successfully mapped control blocks */
2178 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
2179 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
2186 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2189 struct device *kdev = &priv->pdev->dev;
2190 struct sk_buff *skb;
2191 struct sk_buff *rx_skb;
2194 /* Allocate a new Rx skb */
2195 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2196 GFP_ATOMIC | __GFP_NOWARN);
2198 priv->mib.alloc_rx_buff_failed++;
2199 netif_err(priv, rx_err, priv->dev,
2200 "%s: Rx skb allocation failed\n", __func__);
2204 /* DMA-map the new Rx skb */
2205 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2207 if (dma_mapping_error(kdev, mapping)) {
2208 priv->mib.rx_dma_failed++;
2209 dev_kfree_skb_any(skb);
2210 netif_err(priv, rx_err, priv->dev,
2211 "%s: Rx skb DMA mapping failed\n", __func__);
2215 /* Grab the current Rx skb from the ring and DMA-unmap it */
2216 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
2218 /* Put the new Rx skb on the ring */
2220 dma_unmap_addr_set(cb, dma_addr, mapping);
2221 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
2222 dmadesc_set_addr(priv, cb->bd_addr, mapping);
2224 /* Return the current Rx skb to caller */
2228 /* bcmgenet_desc_rx - descriptor based rx process.
2229 * this could be called from bottom half, or from NAPI polling method.
2231 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
2232 unsigned int budget)
2234 struct bcmgenet_priv *priv = ring->priv;
2235 struct net_device *dev = priv->dev;
2237 struct sk_buff *skb;
2238 u32 dma_length_status;
2239 unsigned long dma_flag;
2241 unsigned int rxpktprocessed = 0, rxpkttoprocess;
2242 unsigned int bytes_processed = 0;
2243 unsigned int p_index, mask;
2244 unsigned int discards;
2246 /* Clear status before servicing to reduce spurious interrupts */
2247 if (ring->index == DESC_INDEX) {
2248 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2251 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2252 bcmgenet_intrl2_1_writel(priv,
2257 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
2259 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2260 DMA_P_INDEX_DISCARD_CNT_MASK;
2261 if (discards > ring->old_discards) {
2262 discards = discards - ring->old_discards;
2263 ring->errors += discards;
2264 ring->old_discards += discards;
2266 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2267 if (ring->old_discards >= 0xC000) {
2268 ring->old_discards = 0;
2269 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
2274 p_index &= DMA_P_INDEX_MASK;
2275 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
2277 netif_dbg(priv, rx_status, dev,
2278 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
2280 while ((rxpktprocessed < rxpkttoprocess) &&
2281 (rxpktprocessed < budget)) {
2282 struct status_64 *status;
2285 cb = &priv->rx_cbs[ring->read_ptr];
2286 skb = bcmgenet_rx_refill(priv, cb);
2288 if (unlikely(!skb)) {
2293 status = (struct status_64 *)skb->data;
2294 dma_length_status = status->length_status;
2295 if (dev->features & NETIF_F_RXCSUM) {
2296 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
2298 skb->csum = (__force __wsum)ntohs(rx_csum);
2299 skb->ip_summed = CHECKSUM_COMPLETE;
2303 /* DMA flags and length are still valid no matter how
2304 * we got the Receive Status Vector (64B RSB or register)
2306 dma_flag = dma_length_status & 0xffff;
2307 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2309 netif_dbg(priv, rx_status, dev,
2310 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
2311 __func__, p_index, ring->c_index,
2312 ring->read_ptr, dma_length_status);
2314 if (unlikely(len > RX_BUF_LENGTH)) {
2315 netif_err(priv, rx_status, dev, "oversized packet\n");
2316 dev->stats.rx_length_errors++;
2317 dev->stats.rx_errors++;
2318 dev_kfree_skb_any(skb);
2322 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2323 netif_err(priv, rx_status, dev,
2324 "dropping fragmented packet!\n");
2326 dev_kfree_skb_any(skb);
2331 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2336 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
2337 (unsigned int)dma_flag);
2338 if (dma_flag & DMA_RX_CRC_ERROR)
2339 dev->stats.rx_crc_errors++;
2340 if (dma_flag & DMA_RX_OV)
2341 dev->stats.rx_over_errors++;
2342 if (dma_flag & DMA_RX_NO)
2343 dev->stats.rx_frame_errors++;
2344 if (dma_flag & DMA_RX_LG)
2345 dev->stats.rx_length_errors++;
2346 dev->stats.rx_errors++;
2347 dev_kfree_skb_any(skb);
2349 } /* error packet */
2353 /* remove RSB and hardware 2bytes added for IP alignment */
2357 if (priv->crc_fwd_en) {
2358 skb_trim(skb, len - ETH_FCS_LEN);
2362 bytes_processed += len;
2364 /*Finish setting up the received SKB and send it to the kernel*/
2365 skb->protocol = eth_type_trans(skb, priv->dev);
2368 if (dma_flag & DMA_RX_MULT)
2369 dev->stats.multicast++;
2372 napi_gro_receive(&ring->napi, skb);
2373 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2377 if (likely(ring->read_ptr < ring->end_ptr))
2380 ring->read_ptr = ring->cb_ptr;
2382 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
2383 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
2386 ring->dim.bytes = bytes_processed;
2387 ring->dim.packets = rxpktprocessed;
2389 return rxpktprocessed;
2392 /* Rx NAPI polling method */
2393 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2395 struct bcmgenet_rx_ring *ring = container_of(napi,
2396 struct bcmgenet_rx_ring, napi);
2397 struct dim_sample dim_sample = {};
2398 unsigned int work_done;
2400 work_done = bcmgenet_desc_rx(ring, budget);
2402 if (work_done < budget) {
2403 napi_complete_done(napi, work_done);
2404 ring->int_enable(ring);
2407 if (ring->dim.use_dim) {
2408 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2409 ring->dim.bytes, &dim_sample);
2410 net_dim(&ring->dim.dim, dim_sample);
2416 static void bcmgenet_dim_work(struct work_struct *work)
2418 struct dim *dim = container_of(work, struct dim, work);
2419 struct bcmgenet_net_dim *ndim =
2420 container_of(dim, struct bcmgenet_net_dim, dim);
2421 struct bcmgenet_rx_ring *ring =
2422 container_of(ndim, struct bcmgenet_rx_ring, dim);
2423 struct dim_cq_moder cur_profile =
2424 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
2426 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
2427 dim->state = DIM_START_MEASURE;
2430 /* Assign skb to RX DMA descriptor. */
2431 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2432 struct bcmgenet_rx_ring *ring)
2435 struct sk_buff *skb;
2438 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2440 /* loop here for each buffer needing assign */
2441 for (i = 0; i < ring->size; i++) {
2443 skb = bcmgenet_rx_refill(priv, cb);
2445 dev_consume_skb_any(skb);
2453 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2455 struct sk_buff *skb;
2459 for (i = 0; i < priv->num_rx_bds; i++) {
2460 cb = &priv->rx_cbs[i];
2462 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2464 dev_consume_skb_any(skb);
2468 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
2472 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2473 if (reg & CMD_SW_RESET)
2479 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2481 /* UniMAC stops on a packet boundary, wait for a full-size packet
2485 usleep_range(1000, 2000);
2488 static void reset_umac(struct bcmgenet_priv *priv)
2490 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2491 bcmgenet_rbuf_ctrl_set(priv, 0);
2494 /* issue soft reset and disable MAC while updating its registers */
2495 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
2499 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2501 /* Mask all interrupts.*/
2502 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2503 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2504 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2505 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2508 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2510 u32 int0_enable = 0;
2512 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2515 if (priv->internal_phy) {
2516 int0_enable |= UMAC_IRQ_LINK_EVENT;
2517 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2518 int0_enable |= UMAC_IRQ_PHY_DET_R;
2519 } else if (priv->ext_phy) {
2520 int0_enable |= UMAC_IRQ_LINK_EVENT;
2521 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2522 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2523 int0_enable |= UMAC_IRQ_LINK_EVENT;
2525 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2528 static void init_umac(struct bcmgenet_priv *priv)
2530 struct device *kdev = &priv->pdev->dev;
2532 u32 int0_enable = 0;
2534 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2538 /* clear tx/rx counter */
2539 bcmgenet_umac_writel(priv,
2540 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2542 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2544 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2546 /* init tx registers, enable TSB */
2547 reg = bcmgenet_tbuf_ctrl_get(priv);
2549 bcmgenet_tbuf_ctrl_set(priv, reg);
2551 /* init rx registers, enable ip header optimization and RSB */
2552 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2553 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
2554 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2556 /* enable rx checksumming */
2557 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2558 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2559 /* If UniMAC forwards CRC, we need to skip over it to get
2560 * a valid CHK bit to be set in the per-packet status word
2562 if (priv->crc_fwd_en)
2563 reg |= RBUF_SKIP_FCS;
2565 reg &= ~RBUF_SKIP_FCS;
2566 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2568 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2569 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2571 bcmgenet_intr_disable(priv);
2573 /* Configure backpressure vectors for MoCA */
2574 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2575 reg = bcmgenet_bp_mc_get(priv);
2576 reg |= BIT(priv->hw_params->bp_in_en_shift);
2578 /* bp_mask: back pressure mask */
2579 if (netif_is_multiqueue(priv->dev))
2580 reg |= priv->hw_params->bp_in_mask;
2582 reg &= ~priv->hw_params->bp_in_mask;
2583 bcmgenet_bp_mc_set(priv, reg);
2586 /* Enable MDIO interrupts on GENET v3+ */
2587 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2588 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2590 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2592 dev_dbg(kdev, "done init umac\n");
2595 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2596 void (*cb)(struct work_struct *work))
2598 struct bcmgenet_net_dim *dim = &ring->dim;
2600 INIT_WORK(&dim->dim.work, cb);
2601 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2607 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2609 struct bcmgenet_net_dim *dim = &ring->dim;
2610 struct dim_cq_moder moder;
2613 usecs = ring->rx_coalesce_usecs;
2614 pkts = ring->rx_max_coalesced_frames;
2616 /* If DIM was enabled, re-apply default parameters */
2618 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2623 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2626 /* Initialize a Tx ring along with corresponding hardware registers */
2627 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2628 unsigned int index, unsigned int size,
2629 unsigned int start_ptr, unsigned int end_ptr)
2631 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2632 u32 words_per_bd = WORDS_PER_BD(priv);
2633 u32 flow_period_val = 0;
2635 spin_lock_init(&ring->lock);
2637 ring->index = index;
2638 if (index == DESC_INDEX) {
2640 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2641 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2643 ring->queue = index + 1;
2644 ring->int_enable = bcmgenet_tx_ring_int_enable;
2645 ring->int_disable = bcmgenet_tx_ring_int_disable;
2647 ring->cbs = priv->tx_cbs + start_ptr;
2649 ring->clean_ptr = start_ptr;
2651 ring->free_bds = size;
2652 ring->write_ptr = start_ptr;
2653 ring->cb_ptr = start_ptr;
2654 ring->end_ptr = end_ptr - 1;
2655 ring->prod_index = 0;
2657 /* Set flow period for ring != 16 */
2658 if (index != DESC_INDEX)
2659 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2661 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2662 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2663 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2664 /* Disable rate control for now */
2665 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2667 bcmgenet_tdma_ring_writel(priv, index,
2668 ((size << DMA_RING_SIZE_SHIFT) |
2669 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2671 /* Set start and end address, read and write pointers */
2672 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2674 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2676 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2678 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2681 /* Initialize Tx NAPI */
2682 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll);
2685 /* Initialize a RDMA ring */
2686 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2687 unsigned int index, unsigned int size,
2688 unsigned int start_ptr, unsigned int end_ptr)
2690 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2691 u32 words_per_bd = WORDS_PER_BD(priv);
2695 ring->index = index;
2696 if (index == DESC_INDEX) {
2697 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2698 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2700 ring->int_enable = bcmgenet_rx_ring_int_enable;
2701 ring->int_disable = bcmgenet_rx_ring_int_disable;
2703 ring->cbs = priv->rx_cbs + start_ptr;
2706 ring->read_ptr = start_ptr;
2707 ring->cb_ptr = start_ptr;
2708 ring->end_ptr = end_ptr - 1;
2710 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2714 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2715 bcmgenet_init_rx_coalesce(ring);
2717 /* Initialize Rx NAPI */
2718 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll);
2720 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2721 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2722 bcmgenet_rdma_ring_writel(priv, index,
2723 ((size << DMA_RING_SIZE_SHIFT) |
2724 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2725 bcmgenet_rdma_ring_writel(priv, index,
2726 (DMA_FC_THRESH_LO <<
2727 DMA_XOFF_THRESHOLD_SHIFT) |
2728 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2730 /* Set start and end address, read and write pointers */
2731 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2733 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2735 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2737 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2743 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2746 struct bcmgenet_tx_ring *ring;
2748 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2749 ring = &priv->tx_rings[i];
2750 napi_enable(&ring->napi);
2751 ring->int_enable(ring);
2754 ring = &priv->tx_rings[DESC_INDEX];
2755 napi_enable(&ring->napi);
2756 ring->int_enable(ring);
2759 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2762 struct bcmgenet_tx_ring *ring;
2764 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2765 ring = &priv->tx_rings[i];
2766 napi_disable(&ring->napi);
2769 ring = &priv->tx_rings[DESC_INDEX];
2770 napi_disable(&ring->napi);
2773 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2776 struct bcmgenet_tx_ring *ring;
2778 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2779 ring = &priv->tx_rings[i];
2780 netif_napi_del(&ring->napi);
2783 ring = &priv->tx_rings[DESC_INDEX];
2784 netif_napi_del(&ring->napi);
2787 /* Initialize Tx queues
2789 * Queues 0-3 are priority-based, each one has 32 descriptors,
2790 * with queue 0 being the highest priority queue.
2792 * Queue 16 is the default Tx queue with
2793 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2795 * The transmit control block pool is then partitioned as follows:
2796 * - Tx queue 0 uses tx_cbs[0..31]
2797 * - Tx queue 1 uses tx_cbs[32..63]
2798 * - Tx queue 2 uses tx_cbs[64..95]
2799 * - Tx queue 3 uses tx_cbs[96..127]
2800 * - Tx queue 16 uses tx_cbs[128..255]
2802 static void bcmgenet_init_tx_queues(struct net_device *dev)
2804 struct bcmgenet_priv *priv = netdev_priv(dev);
2806 u32 dma_ctrl, ring_cfg;
2807 u32 dma_priority[3] = {0, 0, 0};
2809 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2810 dma_enable = dma_ctrl & DMA_EN;
2811 dma_ctrl &= ~DMA_EN;
2812 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2817 /* Enable strict priority arbiter mode */
2818 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2820 /* Initialize Tx priority queues */
2821 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2822 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2823 i * priv->hw_params->tx_bds_per_q,
2824 (i + 1) * priv->hw_params->tx_bds_per_q);
2825 ring_cfg |= (1 << i);
2826 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2827 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2828 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2831 /* Initialize Tx default queue 16 */
2832 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2833 priv->hw_params->tx_queues *
2834 priv->hw_params->tx_bds_per_q,
2836 ring_cfg |= (1 << DESC_INDEX);
2837 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2838 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2839 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2840 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2842 /* Set Tx queue priorities */
2843 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2844 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2845 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2847 /* Enable Tx queues */
2848 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2853 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2856 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2859 struct bcmgenet_rx_ring *ring;
2861 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2862 ring = &priv->rx_rings[i];
2863 napi_enable(&ring->napi);
2864 ring->int_enable(ring);
2867 ring = &priv->rx_rings[DESC_INDEX];
2868 napi_enable(&ring->napi);
2869 ring->int_enable(ring);
2872 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2875 struct bcmgenet_rx_ring *ring;
2877 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2878 ring = &priv->rx_rings[i];
2879 napi_disable(&ring->napi);
2880 cancel_work_sync(&ring->dim.dim.work);
2883 ring = &priv->rx_rings[DESC_INDEX];
2884 napi_disable(&ring->napi);
2885 cancel_work_sync(&ring->dim.dim.work);
2888 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2891 struct bcmgenet_rx_ring *ring;
2893 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2894 ring = &priv->rx_rings[i];
2895 netif_napi_del(&ring->napi);
2898 ring = &priv->rx_rings[DESC_INDEX];
2899 netif_napi_del(&ring->napi);
2902 /* Initialize Rx queues
2904 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2905 * used to direct traffic to these queues.
2907 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2909 static int bcmgenet_init_rx_queues(struct net_device *dev)
2911 struct bcmgenet_priv *priv = netdev_priv(dev);
2918 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2919 dma_enable = dma_ctrl & DMA_EN;
2920 dma_ctrl &= ~DMA_EN;
2921 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2926 /* Initialize Rx priority queues */
2927 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2928 ret = bcmgenet_init_rx_ring(priv, i,
2929 priv->hw_params->rx_bds_per_q,
2930 i * priv->hw_params->rx_bds_per_q,
2932 priv->hw_params->rx_bds_per_q);
2936 ring_cfg |= (1 << i);
2937 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2940 /* Initialize Rx default queue 16 */
2941 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2942 priv->hw_params->rx_queues *
2943 priv->hw_params->rx_bds_per_q,
2948 ring_cfg |= (1 << DESC_INDEX);
2949 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2952 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2954 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2957 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2962 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2970 /* Disable TDMA to stop add more frames in TX DMA */
2971 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2973 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2975 /* Check TDMA status register to confirm TDMA is disabled */
2976 while (timeout++ < DMA_TIMEOUT_VAL) {
2977 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2978 if (reg & DMA_DISABLED)
2984 if (timeout == DMA_TIMEOUT_VAL) {
2985 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2989 /* Wait 10ms for packet drain in both tx and rx dma */
2990 usleep_range(10000, 20000);
2993 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2995 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2998 /* Check RDMA status register to confirm RDMA is disabled */
2999 while (timeout++ < DMA_TIMEOUT_VAL) {
3000 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
3001 if (reg & DMA_DISABLED)
3007 if (timeout == DMA_TIMEOUT_VAL) {
3008 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
3013 for (i = 0; i < priv->hw_params->rx_queues; i++)
3014 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3015 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3017 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3020 for (i = 0; i < priv->hw_params->tx_queues; i++)
3021 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3022 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3024 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3029 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
3031 struct netdev_queue *txq;
3034 bcmgenet_fini_rx_napi(priv);
3035 bcmgenet_fini_tx_napi(priv);
3037 for (i = 0; i < priv->num_tx_bds; i++)
3038 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
3041 for (i = 0; i < priv->hw_params->tx_queues; i++) {
3042 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
3043 netdev_tx_reset_queue(txq);
3046 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
3047 netdev_tx_reset_queue(txq);
3049 bcmgenet_free_rx_buffers(priv);
3050 kfree(priv->rx_cbs);
3051 kfree(priv->tx_cbs);
3054 /* init_edma: Initialize DMA control register */
3055 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
3061 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
3063 /* Initialize common Rx ring structures */
3064 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3065 priv->num_rx_bds = TOTAL_DESC;
3066 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3071 for (i = 0; i < priv->num_rx_bds; i++) {
3072 cb = priv->rx_cbs + i;
3073 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3076 /* Initialize common TX ring structures */
3077 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3078 priv->num_tx_bds = TOTAL_DESC;
3079 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
3081 if (!priv->tx_cbs) {
3082 kfree(priv->rx_cbs);
3086 for (i = 0; i < priv->num_tx_bds; i++) {
3087 cb = priv->tx_cbs + i;
3088 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3092 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3093 DMA_SCB_BURST_SIZE);
3095 /* Initialize Rx queues */
3096 ret = bcmgenet_init_rx_queues(priv->dev);
3098 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3099 bcmgenet_free_rx_buffers(priv);
3100 kfree(priv->rx_cbs);
3101 kfree(priv->tx_cbs);
3106 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3107 DMA_SCB_BURST_SIZE);
3109 /* Initialize Tx queues */
3110 bcmgenet_init_tx_queues(priv->dev);
3115 /* Interrupt bottom half */
3116 static void bcmgenet_irq_task(struct work_struct *work)
3118 unsigned int status;
3119 struct bcmgenet_priv *priv = container_of(
3120 work, struct bcmgenet_priv, bcmgenet_irq_work);
3122 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3124 spin_lock_irq(&priv->lock);
3125 status = priv->irq0_stat;
3126 priv->irq0_stat = 0;
3127 spin_unlock_irq(&priv->lock);
3129 if (status & UMAC_IRQ_PHY_DET_R &&
3130 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
3131 phy_init_hw(priv->dev->phydev);
3132 genphy_config_aneg(priv->dev->phydev);
3135 /* Link UP/DOWN event */
3136 if (status & UMAC_IRQ_LINK_EVENT)
3137 phy_mac_interrupt(priv->dev->phydev);
3141 /* bcmgenet_isr1: handle Rx and Tx priority queues */
3142 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3144 struct bcmgenet_priv *priv = dev_id;
3145 struct bcmgenet_rx_ring *rx_ring;
3146 struct bcmgenet_tx_ring *tx_ring;
3147 unsigned int index, status;
3149 /* Read irq status */
3150 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
3151 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3153 /* clear interrupts */
3154 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
3156 netif_dbg(priv, intr, priv->dev,
3157 "%s: IRQ=0x%x\n", __func__, status);
3159 /* Check Rx priority queue interrupts */
3160 for (index = 0; index < priv->hw_params->rx_queues; index++) {
3161 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
3164 rx_ring = &priv->rx_rings[index];
3165 rx_ring->dim.event_ctr++;
3167 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3168 rx_ring->int_disable(rx_ring);
3169 __napi_schedule_irqoff(&rx_ring->napi);
3173 /* Check Tx priority queue interrupts */
3174 for (index = 0; index < priv->hw_params->tx_queues; index++) {
3175 if (!(status & BIT(index)))
3178 tx_ring = &priv->tx_rings[index];
3180 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3181 tx_ring->int_disable(tx_ring);
3182 __napi_schedule_irqoff(&tx_ring->napi);
3189 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
3190 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3192 struct bcmgenet_priv *priv = dev_id;
3193 struct bcmgenet_rx_ring *rx_ring;
3194 struct bcmgenet_tx_ring *tx_ring;
3195 unsigned int status;
3196 unsigned long flags;
3198 /* Read irq status */
3199 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
3200 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3202 /* clear interrupts */
3203 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
3205 netif_dbg(priv, intr, priv->dev,
3206 "IRQ=0x%x\n", status);
3208 if (status & UMAC_IRQ_RXDMA_DONE) {
3209 rx_ring = &priv->rx_rings[DESC_INDEX];
3210 rx_ring->dim.event_ctr++;
3212 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3213 rx_ring->int_disable(rx_ring);
3214 __napi_schedule_irqoff(&rx_ring->napi);
3218 if (status & UMAC_IRQ_TXDMA_DONE) {
3219 tx_ring = &priv->tx_rings[DESC_INDEX];
3221 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3222 tx_ring->int_disable(tx_ring);
3223 __napi_schedule_irqoff(&tx_ring->napi);
3227 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
3228 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
3232 /* all other interested interrupts handled in bottom half */
3233 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
3235 /* Save irq status for bottom-half processing. */
3236 spin_lock_irqsave(&priv->lock, flags);
3237 priv->irq0_stat |= status;
3238 spin_unlock_irqrestore(&priv->lock, flags);
3240 schedule_work(&priv->bcmgenet_irq_work);
3246 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3248 /* Acknowledge the interrupt */
3252 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3256 reg = bcmgenet_rbuf_ctrl_get(priv);
3258 bcmgenet_rbuf_ctrl_set(priv, reg);
3262 bcmgenet_rbuf_ctrl_set(priv, reg);
3266 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
3267 const unsigned char *addr)
3269 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3270 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
3273 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3274 unsigned char *addr)
3278 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
3279 put_unaligned_be32(addr_tmp, &addr[0]);
3280 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
3281 put_unaligned_be16(addr_tmp, &addr[4]);
3284 /* Returns a reusable dma control register value */
3285 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
3292 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3293 for (i = 0; i < priv->hw_params->tx_queues; i++)
3294 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3295 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3297 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3299 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3300 for (i = 0; i < priv->hw_params->rx_queues; i++)
3301 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3302 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3304 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3306 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3308 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3313 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3317 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3319 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3321 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3323 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3326 static void bcmgenet_netif_start(struct net_device *dev)
3328 struct bcmgenet_priv *priv = netdev_priv(dev);
3330 /* Start the network engine */
3331 bcmgenet_set_rx_mode(dev);
3332 bcmgenet_enable_rx_napi(priv);
3334 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3336 bcmgenet_enable_tx_napi(priv);
3338 /* Monitor link interrupts now */
3339 bcmgenet_link_intr_enable(priv);
3341 phy_start(dev->phydev);
3344 static int bcmgenet_open(struct net_device *dev)
3346 struct bcmgenet_priv *priv = netdev_priv(dev);
3347 unsigned long dma_ctrl;
3350 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3352 /* Turn on the clock */
3353 clk_prepare_enable(priv->clk);
3355 /* If this is an internal GPHY, power it back on now, before UniMAC is
3356 * brought out of reset as absolutely no UniMAC activity is allowed
3358 if (priv->internal_phy)
3359 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3361 /* take MAC out of reset */
3362 bcmgenet_umac_reset(priv);
3366 /* Apply features again in case we changed them while interface was
3369 bcmgenet_set_features(dev, dev->features);
3371 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3373 /* Disable RX/TX DMA and flush TX queues */
3374 dma_ctrl = bcmgenet_dma_disable(priv);
3376 /* Reinitialize TDMA and RDMA and SW housekeeping */
3377 ret = bcmgenet_init_dma(priv);
3379 netdev_err(dev, "failed to initialize DMA\n");
3380 goto err_clk_disable;
3383 /* Always enable ring 16 - descriptor ring */
3384 bcmgenet_enable_dma(priv, dma_ctrl);
3387 bcmgenet_hfb_init(priv);
3389 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
3392 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3396 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
3399 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3403 ret = bcmgenet_mii_probe(dev);
3405 netdev_err(dev, "failed to connect to PHY\n");
3409 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3411 bcmgenet_netif_start(dev);
3413 netif_tx_start_all_queues(dev);
3418 free_irq(priv->irq1, priv);
3420 free_irq(priv->irq0, priv);
3422 bcmgenet_dma_teardown(priv);
3423 bcmgenet_fini_dma(priv);
3425 if (priv->internal_phy)
3426 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3427 clk_disable_unprepare(priv->clk);
3431 static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy)
3433 struct bcmgenet_priv *priv = netdev_priv(dev);
3435 bcmgenet_disable_tx_napi(priv);
3436 netif_tx_disable(dev);
3438 /* Disable MAC receive */
3439 umac_enable_set(priv, CMD_RX_EN, false);
3441 bcmgenet_dma_teardown(priv);
3443 /* Disable MAC transmit. TX DMA disabled must be done before this */
3444 umac_enable_set(priv, CMD_TX_EN, false);
3447 phy_stop(dev->phydev);
3448 bcmgenet_disable_rx_napi(priv);
3449 bcmgenet_intr_disable(priv);
3451 /* Wait for pending work items to complete. Since interrupts are
3452 * disabled no new work will be scheduled.
3454 cancel_work_sync(&priv->bcmgenet_irq_work);
3457 bcmgenet_tx_reclaim_all(dev);
3458 bcmgenet_fini_dma(priv);
3461 static int bcmgenet_close(struct net_device *dev)
3463 struct bcmgenet_priv *priv = netdev_priv(dev);
3466 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3468 bcmgenet_netif_stop(dev, false);
3470 /* Really kill the PHY state machine and disconnect from it */
3471 phy_disconnect(dev->phydev);
3473 free_irq(priv->irq0, priv);
3474 free_irq(priv->irq1, priv);
3476 if (priv->internal_phy)
3477 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3479 clk_disable_unprepare(priv->clk);
3484 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3486 struct bcmgenet_priv *priv = ring->priv;
3487 u32 p_index, c_index, intsts, intmsk;
3488 struct netdev_queue *txq;
3489 unsigned int free_bds;
3492 if (!netif_msg_tx_err(priv))
3495 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3497 spin_lock(&ring->lock);
3498 if (ring->index == DESC_INDEX) {
3499 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3500 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3502 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3503 intmsk = 1 << ring->index;
3505 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3506 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3507 txq_stopped = netif_tx_queue_stopped(txq);
3508 free_bds = ring->free_bds;
3509 spin_unlock(&ring->lock);
3511 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3512 "TX queue status: %s, interrupts: %s\n"
3513 "(sw)free_bds: %d (sw)size: %d\n"
3514 "(sw)p_index: %d (hw)p_index: %d\n"
3515 "(sw)c_index: %d (hw)c_index: %d\n"
3516 "(sw)clean_p: %d (sw)write_p: %d\n"
3517 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3518 ring->index, ring->queue,
3519 txq_stopped ? "stopped" : "active",
3520 intsts & intmsk ? "enabled" : "disabled",
3521 free_bds, ring->size,
3522 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3523 ring->c_index, c_index & DMA_C_INDEX_MASK,
3524 ring->clean_ptr, ring->write_ptr,
3525 ring->cb_ptr, ring->end_ptr);
3528 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3530 struct bcmgenet_priv *priv = netdev_priv(dev);
3531 u32 int0_enable = 0;
3532 u32 int1_enable = 0;
3535 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3537 for (q = 0; q < priv->hw_params->tx_queues; q++)
3538 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3539 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3541 bcmgenet_tx_reclaim_all(dev);
3543 for (q = 0; q < priv->hw_params->tx_queues; q++)
3544 int1_enable |= (1 << q);
3546 int0_enable = UMAC_IRQ_TXDMA_DONE;
3548 /* Re-enable TX interrupts if disabled */
3549 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3550 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3552 netif_trans_update(dev);
3554 dev->stats.tx_errors++;
3556 netif_tx_wake_all_queues(dev);
3559 #define MAX_MDF_FILTER 17
3561 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3562 const unsigned char *addr,
3565 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3566 UMAC_MDF_ADDR + (*i * 4));
3567 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3568 addr[4] << 8 | addr[5],
3569 UMAC_MDF_ADDR + ((*i + 1) * 4));
3573 static void bcmgenet_set_rx_mode(struct net_device *dev)
3575 struct bcmgenet_priv *priv = netdev_priv(dev);
3576 struct netdev_hw_addr *ha;
3580 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3582 /* Number of filters needed */
3583 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3586 * Turn on promicuous mode for three scenarios
3587 * 1. IFF_PROMISC flag is set
3588 * 2. IFF_ALLMULTI flag is set
3589 * 3. The number of filters needed exceeds the number filters
3590 * supported by the hardware.
3592 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3593 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3594 (nfilter > MAX_MDF_FILTER)) {
3596 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3597 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3600 reg &= ~CMD_PROMISC;
3601 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3604 /* update MDF filter */
3607 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3608 /* my own address.*/
3609 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3612 netdev_for_each_uc_addr(ha, dev)
3613 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3616 netdev_for_each_mc_addr(ha, dev)
3617 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3619 /* Enable filters */
3620 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3621 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3624 /* Set the hardware MAC address. */
3625 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3627 struct sockaddr *addr = p;
3629 /* Setting the MAC address at the hardware level is not possible
3630 * without disabling the UniMAC RX/TX enable bits.
3632 if (netif_running(dev))
3635 eth_hw_addr_set(dev, addr->sa_data);
3640 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3642 struct bcmgenet_priv *priv = netdev_priv(dev);
3643 unsigned long tx_bytes = 0, tx_packets = 0;
3644 unsigned long rx_bytes = 0, rx_packets = 0;
3645 unsigned long rx_errors = 0, rx_dropped = 0;
3646 struct bcmgenet_tx_ring *tx_ring;
3647 struct bcmgenet_rx_ring *rx_ring;
3650 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3651 tx_ring = &priv->tx_rings[q];
3652 tx_bytes += tx_ring->bytes;
3653 tx_packets += tx_ring->packets;
3655 tx_ring = &priv->tx_rings[DESC_INDEX];
3656 tx_bytes += tx_ring->bytes;
3657 tx_packets += tx_ring->packets;
3659 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3660 rx_ring = &priv->rx_rings[q];
3662 rx_bytes += rx_ring->bytes;
3663 rx_packets += rx_ring->packets;
3664 rx_errors += rx_ring->errors;
3665 rx_dropped += rx_ring->dropped;
3667 rx_ring = &priv->rx_rings[DESC_INDEX];
3668 rx_bytes += rx_ring->bytes;
3669 rx_packets += rx_ring->packets;
3670 rx_errors += rx_ring->errors;
3671 rx_dropped += rx_ring->dropped;
3673 dev->stats.tx_bytes = tx_bytes;
3674 dev->stats.tx_packets = tx_packets;
3675 dev->stats.rx_bytes = rx_bytes;
3676 dev->stats.rx_packets = rx_packets;
3677 dev->stats.rx_errors = rx_errors;
3678 dev->stats.rx_missed_errors = rx_errors;
3679 dev->stats.rx_dropped = rx_dropped;
3683 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3685 struct bcmgenet_priv *priv = netdev_priv(dev);
3687 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3688 priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3692 netif_carrier_on(dev);
3694 netif_carrier_off(dev);
3699 static const struct net_device_ops bcmgenet_netdev_ops = {
3700 .ndo_open = bcmgenet_open,
3701 .ndo_stop = bcmgenet_close,
3702 .ndo_start_xmit = bcmgenet_xmit,
3703 .ndo_tx_timeout = bcmgenet_timeout,
3704 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3705 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3706 .ndo_eth_ioctl = phy_do_ioctl_running,
3707 .ndo_set_features = bcmgenet_set_features,
3708 .ndo_get_stats = bcmgenet_get_stats,
3709 .ndo_change_carrier = bcmgenet_change_carrier,
3712 /* Array of GENET hardware parameters/characteristics */
3713 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3719 .bp_in_en_shift = 16,
3720 .bp_in_mask = 0xffff,
3721 .hfb_filter_cnt = 16,
3723 .hfb_offset = 0x1000,
3724 .rdma_offset = 0x2000,
3725 .tdma_offset = 0x3000,
3733 .bp_in_en_shift = 16,
3734 .bp_in_mask = 0xffff,
3735 .hfb_filter_cnt = 16,
3737 .tbuf_offset = 0x0600,
3738 .hfb_offset = 0x1000,
3739 .hfb_reg_offset = 0x2000,
3740 .rdma_offset = 0x3000,
3741 .tdma_offset = 0x4000,
3743 .flags = GENET_HAS_EXT,
3750 .bp_in_en_shift = 17,
3751 .bp_in_mask = 0x1ffff,
3752 .hfb_filter_cnt = 48,
3753 .hfb_filter_size = 128,
3755 .tbuf_offset = 0x0600,
3756 .hfb_offset = 0x8000,
3757 .hfb_reg_offset = 0xfc00,
3758 .rdma_offset = 0x10000,
3759 .tdma_offset = 0x11000,
3761 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3762 GENET_HAS_MOCA_LINK_DET,
3769 .bp_in_en_shift = 17,
3770 .bp_in_mask = 0x1ffff,
3771 .hfb_filter_cnt = 48,
3772 .hfb_filter_size = 128,
3774 .tbuf_offset = 0x0600,
3775 .hfb_offset = 0x8000,
3776 .hfb_reg_offset = 0xfc00,
3777 .rdma_offset = 0x2000,
3778 .tdma_offset = 0x4000,
3780 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3781 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3788 .bp_in_en_shift = 17,
3789 .bp_in_mask = 0x1ffff,
3790 .hfb_filter_cnt = 48,
3791 .hfb_filter_size = 128,
3793 .tbuf_offset = 0x0600,
3794 .hfb_offset = 0x8000,
3795 .hfb_reg_offset = 0xfc00,
3796 .rdma_offset = 0x2000,
3797 .tdma_offset = 0x4000,
3799 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3800 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3804 /* Infer hardware parameters from the detected GENET version */
3805 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3807 struct bcmgenet_hw_params *params;
3812 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3813 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3814 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3815 } else if (GENET_IS_V3(priv)) {
3816 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3817 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3818 } else if (GENET_IS_V2(priv)) {
3819 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3820 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3821 } else if (GENET_IS_V1(priv)) {
3822 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3823 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3826 /* enum genet_version starts at 1 */
3827 priv->hw_params = &bcmgenet_hw_params[priv->version];
3828 params = priv->hw_params;
3830 /* Read GENET HW version */
3831 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3832 major = (reg >> 24 & 0x0f);
3835 else if (major == 5)
3837 else if (major == 0)
3839 if (major != priv->version) {
3840 dev_err(&priv->pdev->dev,
3841 "GENET version mismatch, got: %d, configured for: %d\n",
3842 major, priv->version);
3845 /* Print the GENET core version */
3846 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3847 major, (reg >> 16) & 0x0f, reg & 0xffff);
3849 /* Store the integrated PHY revision for the MDIO probing function
3850 * to pass this information to the PHY driver. The PHY driver expects
3851 * to find the PHY major revision in bits 15:8 while the GENET register
3852 * stores that information in bits 7:0, account for that.
3854 * On newer chips, starting with PHY revision G0, a new scheme is
3855 * deployed similar to the Starfighter 2 switch with GPHY major
3856 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3857 * is reserved as well as special value 0x01ff, we have a small
3858 * heuristic to check for the new GPHY revision and re-arrange things
3859 * so the GPHY driver is happy.
3861 gphy_rev = reg & 0xffff;
3863 if (GENET_IS_V5(priv)) {
3864 /* The EPHY revision should come from the MDIO registers of
3865 * the PHY not from GENET.
3867 if (gphy_rev != 0) {
3868 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3871 /* This is reserved so should require special treatment */
3872 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3873 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3875 /* This is the good old scheme, just GPHY major, no minor nor patch */
3876 } else if ((gphy_rev & 0xf0) != 0) {
3877 priv->gphy_rev = gphy_rev << 8;
3878 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3879 } else if ((gphy_rev & 0xff00) != 0) {
3880 priv->gphy_rev = gphy_rev;
3883 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3884 if (!(params->flags & GENET_HAS_40BITS))
3885 pr_warn("GENET does not support 40-bits PA\n");
3888 pr_debug("Configuration for version: %d\n"
3889 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3890 "BP << en: %2d, BP msk: 0x%05x\n"
3891 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3892 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3893 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3896 params->tx_queues, params->tx_bds_per_q,
3897 params->rx_queues, params->rx_bds_per_q,
3898 params->bp_in_en_shift, params->bp_in_mask,
3899 params->hfb_filter_cnt, params->qtag_mask,
3900 params->tbuf_offset, params->hfb_offset,
3901 params->hfb_reg_offset,
3902 params->rdma_offset, params->tdma_offset,
3903 params->words_per_bd);
3906 struct bcmgenet_plat_data {
3907 enum bcmgenet_version version;
3908 u32 dma_max_burst_length;
3912 static const struct bcmgenet_plat_data v1_plat_data = {
3913 .version = GENET_V1,
3914 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3917 static const struct bcmgenet_plat_data v2_plat_data = {
3918 .version = GENET_V2,
3919 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3922 static const struct bcmgenet_plat_data v3_plat_data = {
3923 .version = GENET_V3,
3924 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3927 static const struct bcmgenet_plat_data v4_plat_data = {
3928 .version = GENET_V4,
3929 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3932 static const struct bcmgenet_plat_data v5_plat_data = {
3933 .version = GENET_V5,
3934 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3937 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3938 .version = GENET_V5,
3939 .dma_max_burst_length = 0x08,
3942 static const struct bcmgenet_plat_data bcm7712_plat_data = {
3943 .version = GENET_V5,
3944 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3948 static const struct of_device_id bcmgenet_match[] = {
3949 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3950 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3951 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3952 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3953 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3954 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3955 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data },
3958 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3960 static int bcmgenet_probe(struct platform_device *pdev)
3962 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3963 const struct bcmgenet_plat_data *pdata;
3964 struct bcmgenet_priv *priv;
3965 struct net_device *dev;
3969 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3970 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3971 GENET_MAX_MQ_CNT + 1);
3973 dev_err(&pdev->dev, "can't allocate net device\n");
3977 priv = netdev_priv(dev);
3978 priv->irq0 = platform_get_irq(pdev, 0);
3979 if (priv->irq0 < 0) {
3983 priv->irq1 = platform_get_irq(pdev, 1);
3984 if (priv->irq1 < 0) {
3988 priv->wol_irq = platform_get_irq_optional(pdev, 2);
3989 if (priv->wol_irq == -EPROBE_DEFER) {
3990 err = priv->wol_irq;
3994 priv->base = devm_platform_ioremap_resource(pdev, 0);
3995 if (IS_ERR(priv->base)) {
3996 err = PTR_ERR(priv->base);
4000 spin_lock_init(&priv->lock);
4002 /* Set default pause parameters */
4003 priv->autoneg_pause = 1;
4007 SET_NETDEV_DEV(dev, &pdev->dev);
4008 dev_set_drvdata(&pdev->dev, dev);
4009 dev->watchdog_timeo = 2 * HZ;
4010 dev->ethtool_ops = &bcmgenet_ethtool_ops;
4011 dev->netdev_ops = &bcmgenet_netdev_ops;
4013 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
4015 /* Set default features */
4016 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
4018 dev->hw_features |= dev->features;
4019 dev->vlan_features |= dev->features;
4021 /* Request the WOL interrupt and advertise suspend if available */
4022 priv->wol_irq_disabled = true;
4023 if (priv->wol_irq > 0) {
4024 err = devm_request_irq(&pdev->dev, priv->wol_irq,
4025 bcmgenet_wol_isr, 0, dev->name, priv);
4027 device_set_wakeup_capable(&pdev->dev, 1);
4030 /* Set the needed headroom to account for any possible
4031 * features enabling/disabling at runtime
4033 dev->needed_headroom += 64;
4038 pdata = device_get_match_data(&pdev->dev);
4040 priv->version = pdata->version;
4041 priv->dma_max_burst_length = pdata->dma_max_burst_length;
4042 priv->ephy_16nm = pdata->ephy_16nm;
4044 priv->version = pd->genet_version;
4045 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
4048 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
4049 if (IS_ERR(priv->clk)) {
4050 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
4051 err = PTR_ERR(priv->clk);
4055 err = clk_prepare_enable(priv->clk);
4059 bcmgenet_set_hw_params(priv);
4062 if (priv->hw_params->flags & GENET_HAS_40BITS)
4063 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4065 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4067 goto err_clk_disable;
4069 /* Mii wait queue */
4070 init_waitqueue_head(&priv->wq);
4071 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4072 priv->rx_buf_len = RX_BUF_LENGTH;
4073 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4075 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
4076 if (IS_ERR(priv->clk_wol)) {
4077 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
4078 err = PTR_ERR(priv->clk_wol);
4079 goto err_clk_disable;
4082 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
4083 if (IS_ERR(priv->clk_eee)) {
4084 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
4085 err = PTR_ERR(priv->clk_eee);
4086 goto err_clk_disable;
4089 /* If this is an internal GPHY, power it on now, before UniMAC is
4090 * brought out of reset as absolutely no UniMAC activity is allowed
4092 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
4093 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4095 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
4096 eth_hw_addr_set(dev, pd->mac_address);
4098 if (device_get_ethdev_address(&pdev->dev, dev))
4099 if (has_acpi_companion(&pdev->dev)) {
4102 bcmgenet_get_hw_addr(priv, addr);
4103 eth_hw_addr_set(dev, addr);
4106 if (!is_valid_ether_addr(dev->dev_addr)) {
4107 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4108 eth_hw_addr_random(dev);
4113 err = bcmgenet_mii_init(dev);
4115 goto err_clk_disable;
4117 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
4118 * just the ring 16 descriptor based TX
4120 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4121 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4123 /* Set default coalescing parameters */
4124 for (i = 0; i < priv->hw_params->rx_queues; i++)
4125 priv->rx_rings[i].rx_max_coalesced_frames = 1;
4126 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4128 /* libphy will determine the link state */
4129 netif_carrier_off(dev);
4131 /* Turn off the main clock, WOL clock is handled separately */
4132 clk_disable_unprepare(priv->clk);
4134 err = register_netdev(dev);
4136 bcmgenet_mii_exit(dev);
4143 clk_disable_unprepare(priv->clk);
4149 static void bcmgenet_remove(struct platform_device *pdev)
4151 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4153 dev_set_drvdata(&pdev->dev, NULL);
4154 unregister_netdev(priv->dev);
4155 bcmgenet_mii_exit(priv->dev);
4156 free_netdev(priv->dev);
4159 static void bcmgenet_shutdown(struct platform_device *pdev)
4161 bcmgenet_remove(pdev);
4164 #ifdef CONFIG_PM_SLEEP
4165 static int bcmgenet_resume_noirq(struct device *d)
4167 struct net_device *dev = dev_get_drvdata(d);
4168 struct bcmgenet_priv *priv = netdev_priv(dev);
4172 if (!netif_running(dev))
4175 /* Turn on the clock */
4176 ret = clk_prepare_enable(priv->clk);
4180 if (device_may_wakeup(d) && priv->wolopts) {
4181 /* Account for Wake-on-LAN events and clear those events
4182 * (Some devices need more time between enabling the clocks
4183 * and the interrupt register reflecting the wake event so
4184 * read the register twice)
4186 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4187 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4188 if (reg & UMAC_IRQ_WAKE_EVENT)
4189 pm_wakeup_event(&priv->pdev->dev, 0);
4192 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4197 static int bcmgenet_resume(struct device *d)
4199 struct net_device *dev = dev_get_drvdata(d);
4200 struct bcmgenet_priv *priv = netdev_priv(dev);
4201 struct bcmgenet_rxnfc_rule *rule;
4202 unsigned long dma_ctrl;
4205 if (!netif_running(dev))
4208 /* From WOL-enabled suspend, switch to regular clock */
4209 if (device_may_wakeup(d) && priv->wolopts)
4210 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4212 /* If this is an internal GPHY, power it back on now, before UniMAC is
4213 * brought out of reset as absolutely no UniMAC activity is allowed
4215 if (priv->internal_phy)
4216 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4218 bcmgenet_umac_reset(priv);
4222 phy_init_hw(dev->phydev);
4224 /* Speed settings must be restored */
4225 genphy_config_aneg(dev->phydev);
4226 bcmgenet_mii_config(priv->dev, false);
4228 /* Restore enabled features */
4229 bcmgenet_set_features(dev, dev->features);
4231 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4233 /* Restore hardware filters */
4234 bcmgenet_hfb_clear(priv);
4235 list_for_each_entry(rule, &priv->rxnfc_list, list)
4236 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4237 bcmgenet_hfb_create_rxnfc_filter(priv, rule);
4239 /* Disable RX/TX DMA and flush TX queues */
4240 dma_ctrl = bcmgenet_dma_disable(priv);
4242 /* Reinitialize TDMA and RDMA and SW housekeeping */
4243 ret = bcmgenet_init_dma(priv);
4245 netdev_err(dev, "failed to initialize DMA\n");
4246 goto out_clk_disable;
4249 /* Always enable ring 16 - descriptor ring */
4250 bcmgenet_enable_dma(priv, dma_ctrl);
4252 if (!device_may_wakeup(d))
4253 phy_resume(dev->phydev);
4255 bcmgenet_netif_start(dev);
4257 netif_device_attach(dev);
4262 if (priv->internal_phy)
4263 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4264 clk_disable_unprepare(priv->clk);
4268 static int bcmgenet_suspend(struct device *d)
4270 struct net_device *dev = dev_get_drvdata(d);
4271 struct bcmgenet_priv *priv = netdev_priv(dev);
4273 if (!netif_running(dev))
4276 netif_device_detach(dev);
4278 bcmgenet_netif_stop(dev, true);
4280 if (!device_may_wakeup(d))
4281 phy_suspend(dev->phydev);
4283 /* Disable filtering */
4284 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4289 static int bcmgenet_suspend_noirq(struct device *d)
4291 struct net_device *dev = dev_get_drvdata(d);
4292 struct bcmgenet_priv *priv = netdev_priv(dev);
4295 if (!netif_running(dev))
4298 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
4299 if (device_may_wakeup(d) && priv->wolopts)
4300 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
4301 else if (priv->internal_phy)
4302 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4304 /* Let the framework handle resumption and leave the clocks on */
4308 /* Turn off the clocks */
4309 clk_disable_unprepare(priv->clk);
4314 #define bcmgenet_suspend NULL
4315 #define bcmgenet_suspend_noirq NULL
4316 #define bcmgenet_resume NULL
4317 #define bcmgenet_resume_noirq NULL
4318 #endif /* CONFIG_PM_SLEEP */
4320 static const struct dev_pm_ops bcmgenet_pm_ops = {
4321 .suspend = bcmgenet_suspend,
4322 .suspend_noirq = bcmgenet_suspend_noirq,
4323 .resume = bcmgenet_resume,
4324 .resume_noirq = bcmgenet_resume_noirq,
4327 static const struct acpi_device_id genet_acpi_match[] = {
4328 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4331 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4333 static struct platform_driver bcmgenet_driver = {
4334 .probe = bcmgenet_probe,
4335 .remove_new = bcmgenet_remove,
4336 .shutdown = bcmgenet_shutdown,
4339 .of_match_table = bcmgenet_match,
4340 .pm = &bcmgenet_pm_ops,
4341 .acpi_match_table = genet_acpi_match,
4344 module_platform_driver(bcmgenet_driver);
4346 MODULE_AUTHOR("Broadcom Corporation");
4347 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4348 MODULE_ALIAS("platform:bcmgenet");
4349 MODULE_LICENSE("GPL");
4350 MODULE_SOFTDEP("pre: mdio-bcm-unimac");