drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 /* Forward declarations */
  76 static void bcmgenet_set_rx_mode(struct net_device *dev);
  77
  78 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  79 {
  80         /* MIPS chips strapped for BE will automagically configure the
  81          * peripheral registers for CPU-native byte order.
  82          */
  83         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  84                 __raw_writel(value, offset);
  85         else
  86                 writel_relaxed(value, offset);
  87 }
  88
  89 static inline u32 bcmgenet_readl(void __iomem *offset)
  90 {
  91         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  92                 return __raw_readl(offset);
  93         else
  94                 return readl_relaxed(offset);
  95 }
  96
  97 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  98                                              void __iomem *d, u32 value)
  99 {
 100         bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
 101 }
 102
 103 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
 104                                             void __iomem *d)
 105 {
 106         return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
 107 }
 108
 109 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
 110                                     void __iomem *d,
 111                                     dma_addr_t addr)
 112 {
 113         bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 114
 115         /* Register writes to GISB bus can take couple hundred nanoseconds
 116          * and are done for each packet, save these expensive writes unless
 117          * the platform is explicitly configured for 64-bits/LPAE.
 118          */
 119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 120         if (priv->hw_params->flags & GENET_HAS_40BITS)
 121                 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 122 #endif
 123 }
 124
 125 /* Combined address + length/status setter */
 126 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 127                                void __iomem *d, dma_addr_t addr, u32 val)
 128 {
 129         dmadesc_set_addr(priv, d, addr);
 130         dmadesc_set_length_status(priv, d, val);
 131 }
 132
 133 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 134                                           void __iomem *d)
 135 {
 136         dma_addr_t addr;
 137
 138         addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
 139
 140         /* Register writes to GISB bus can take couple hundred nanoseconds
 141          * and are done for each packet, save these expensive writes unless
 142          * the platform is explicitly configured for 64-bits/LPAE.
 143          */
 144 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 145         if (priv->hw_params->flags & GENET_HAS_40BITS)
 146                 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 147 #endif
 148         return addr;
 149 }
 150
 151 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 152
 153 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 154                                 NETIF_MSG_LINK)
 155
 156 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 157 {
 158         if (GENET_IS_V1(priv))
 159                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 160         else
 161                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 162 }
 163
 164 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 165 {
 166         if (GENET_IS_V1(priv))
 167                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 168         else
 169                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 170 }
 171
 172 /* These macros are defined to deal with register map change
 173  * between GENET1.1 and GENET2. Only those currently being used
 174  * by driver are defined.
 175  */
 176 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 177 {
 178         if (GENET_IS_V1(priv))
 179                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 180         else
 181                 return bcmgenet_readl(priv->base +
 182                                       priv->hw_params->tbuf_offset + TBUF_CTRL);
 183 }
 184
 185 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 186 {
 187         if (GENET_IS_V1(priv))
 188                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 189         else
 190                 bcmgenet_writel(val, priv->base +
 191                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 192 }
 193
 194 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 195 {
 196         if (GENET_IS_V1(priv))
 197                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 198         else
 199                 return bcmgenet_readl(priv->base +
 200                                       priv->hw_params->tbuf_offset + TBUF_BP_MC);
 201 }
 202
 203 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 204 {
 205         if (GENET_IS_V1(priv))
 206                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 207         else
 208                 bcmgenet_writel(val, priv->base +
 209                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 210 }
 211
 212 /* RX/TX DMA register accessors */
 213 enum dma_reg {
 214         DMA_RING_CFG = 0,
 215         DMA_CTRL,
 216         DMA_STATUS,
 217         DMA_SCB_BURST_SIZE,
 218         DMA_ARB_CTRL,
 219         DMA_PRIORITY_0,
 220         DMA_PRIORITY_1,
 221         DMA_PRIORITY_2,
 222         DMA_INDEX2RING_0,
 223         DMA_INDEX2RING_1,
 224         DMA_INDEX2RING_2,
 225         DMA_INDEX2RING_3,
 226         DMA_INDEX2RING_4,
 227         DMA_INDEX2RING_5,
 228         DMA_INDEX2RING_6,
 229         DMA_INDEX2RING_7,
 230         DMA_RING0_TIMEOUT,
 231         DMA_RING1_TIMEOUT,
 232         DMA_RING2_TIMEOUT,
 233         DMA_RING3_TIMEOUT,
 234         DMA_RING4_TIMEOUT,
 235         DMA_RING5_TIMEOUT,
 236         DMA_RING6_TIMEOUT,
 237         DMA_RING7_TIMEOUT,
 238         DMA_RING8_TIMEOUT,
 239         DMA_RING9_TIMEOUT,
 240         DMA_RING10_TIMEOUT,
 241         DMA_RING11_TIMEOUT,
 242         DMA_RING12_TIMEOUT,
 243         DMA_RING13_TIMEOUT,
 244         DMA_RING14_TIMEOUT,
 245         DMA_RING15_TIMEOUT,
 246         DMA_RING16_TIMEOUT,
 247 };
 248
 249 static const u8 bcmgenet_dma_regs_v3plus[] = {
 250         [DMA_RING_CFG]          = 0x00,
 251         [DMA_CTRL]              = 0x04,
 252         [DMA_STATUS]            = 0x08,
 253         [DMA_SCB_BURST_SIZE]    = 0x0C,
 254         [DMA_ARB_CTRL]          = 0x2C,
 255         [DMA_PRIORITY_0]        = 0x30,
 256         [DMA_PRIORITY_1]        = 0x34,
 257         [DMA_PRIORITY_2]        = 0x38,
 258         [DMA_RING0_TIMEOUT]     = 0x2C,
 259         [DMA_RING1_TIMEOUT]     = 0x30,
 260         [DMA_RING2_TIMEOUT]     = 0x34,
 261         [DMA_RING3_TIMEOUT]     = 0x38,
 262         [DMA_RING4_TIMEOUT]     = 0x3c,
 263         [DMA_RING5_TIMEOUT]     = 0x40,
 264         [DMA_RING6_TIMEOUT]     = 0x44,
 265         [DMA_RING7_TIMEOUT]     = 0x48,
 266         [DMA_RING8_TIMEOUT]     = 0x4c,
 267         [DMA_RING9_TIMEOUT]     = 0x50,
 268         [DMA_RING10_TIMEOUT]    = 0x54,
 269         [DMA_RING11_TIMEOUT]    = 0x58,
 270         [DMA_RING12_TIMEOUT]    = 0x5c,
 271         [DMA_RING13_TIMEOUT]    = 0x60,
 272         [DMA_RING14_TIMEOUT]    = 0x64,
 273         [DMA_RING15_TIMEOUT]    = 0x68,
 274         [DMA_RING16_TIMEOUT]    = 0x6C,
 275         [DMA_INDEX2RING_0]      = 0x70,
 276         [DMA_INDEX2RING_1]      = 0x74,
 277         [DMA_INDEX2RING_2]      = 0x78,
 278         [DMA_INDEX2RING_3]      = 0x7C,
 279         [DMA_INDEX2RING_4]      = 0x80,
 280         [DMA_INDEX2RING_5]      = 0x84,
 281         [DMA_INDEX2RING_6]      = 0x88,
 282         [DMA_INDEX2RING_7]      = 0x8C,
 283 };
 284
 285 static const u8 bcmgenet_dma_regs_v2[] = {
 286         [DMA_RING_CFG]          = 0x00,
 287         [DMA_CTRL]              = 0x04,
 288         [DMA_STATUS]            = 0x08,
 289         [DMA_SCB_BURST_SIZE]    = 0x0C,
 290         [DMA_ARB_CTRL]          = 0x30,
 291         [DMA_PRIORITY_0]        = 0x34,
 292         [DMA_PRIORITY_1]        = 0x38,
 293         [DMA_PRIORITY_2]        = 0x3C,
 294         [DMA_RING0_TIMEOUT]     = 0x2C,
 295         [DMA_RING1_TIMEOUT]     = 0x30,
 296         [DMA_RING2_TIMEOUT]     = 0x34,
 297         [DMA_RING3_TIMEOUT]     = 0x38,
 298         [DMA_RING4_TIMEOUT]     = 0x3c,
 299         [DMA_RING5_TIMEOUT]     = 0x40,
 300         [DMA_RING6_TIMEOUT]     = 0x44,
 301         [DMA_RING7_TIMEOUT]     = 0x48,
 302         [DMA_RING8_TIMEOUT]     = 0x4c,
 303         [DMA_RING9_TIMEOUT]     = 0x50,
 304         [DMA_RING10_TIMEOUT]    = 0x54,
 305         [DMA_RING11_TIMEOUT]    = 0x58,
 306         [DMA_RING12_TIMEOUT]    = 0x5c,
 307         [DMA_RING13_TIMEOUT]    = 0x60,
 308         [DMA_RING14_TIMEOUT]    = 0x64,
 309         [DMA_RING15_TIMEOUT]    = 0x68,
 310         [DMA_RING16_TIMEOUT]    = 0x6C,
 311 };
 312
 313 static const u8 bcmgenet_dma_regs_v1[] = {
 314         [DMA_CTRL]              = 0x00,
 315         [DMA_STATUS]            = 0x04,
 316         [DMA_SCB_BURST_SIZE]    = 0x0C,
 317         [DMA_ARB_CTRL]          = 0x30,
 318         [DMA_PRIORITY_0]        = 0x34,
 319         [DMA_PRIORITY_1]        = 0x38,
 320         [DMA_PRIORITY_2]        = 0x3C,
 321         [DMA_RING0_TIMEOUT]     = 0x2C,
 322         [DMA_RING1_TIMEOUT]     = 0x30,
 323         [DMA_RING2_TIMEOUT]     = 0x34,
 324         [DMA_RING3_TIMEOUT]     = 0x38,
 325         [DMA_RING4_TIMEOUT]     = 0x3c,
 326         [DMA_RING5_TIMEOUT]     = 0x40,
 327         [DMA_RING6_TIMEOUT]     = 0x44,
 328         [DMA_RING7_TIMEOUT]     = 0x48,
 329         [DMA_RING8_TIMEOUT]     = 0x4c,
 330         [DMA_RING9_TIMEOUT]     = 0x50,
 331         [DMA_RING10_TIMEOUT]    = 0x54,
 332         [DMA_RING11_TIMEOUT]    = 0x58,
 333         [DMA_RING12_TIMEOUT]    = 0x5c,
 334         [DMA_RING13_TIMEOUT]    = 0x60,
 335         [DMA_RING14_TIMEOUT]    = 0x64,
 336         [DMA_RING15_TIMEOUT]    = 0x68,
 337         [DMA_RING16_TIMEOUT]    = 0x6C,
 338 };
 339
 340 /* Set at runtime once bcmgenet version is known */
 341 static const u8 *bcmgenet_dma_regs;
 342
 343 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 344 {
 345         return netdev_priv(dev_get_drvdata(dev));
 346 }
 347
 348 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 349                                       enum dma_reg r)
 350 {
 351         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 352                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 353 }
 354
 355 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 356                                         u32 val, enum dma_reg r)
 357 {
 358         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 359                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 360 }
 361
 362 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 363                                       enum dma_reg r)
 364 {
 365         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 366                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 367 }
 368
 369 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 370                                         u32 val, enum dma_reg r)
 371 {
 372         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 373                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 374 }
 375
 376 /* RDMA/TDMA ring registers and accessors
 377  * we merge the common fields and just prefix with T/D the registers
 378  * having different meaning depending on the direction
 379  */
 380 enum dma_ring_reg {
 381         TDMA_READ_PTR = 0,
 382         RDMA_WRITE_PTR = TDMA_READ_PTR,
 383         TDMA_READ_PTR_HI,
 384         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 385         TDMA_CONS_INDEX,
 386         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 387         TDMA_PROD_INDEX,
 388         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 389         DMA_RING_BUF_SIZE,
 390         DMA_START_ADDR,
 391         DMA_START_ADDR_HI,
 392         DMA_END_ADDR,
 393         DMA_END_ADDR_HI,
 394         DMA_MBUF_DONE_THRESH,
 395         TDMA_FLOW_PERIOD,
 396         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 397         TDMA_WRITE_PTR,
 398         RDMA_READ_PTR = TDMA_WRITE_PTR,
 399         TDMA_WRITE_PTR_HI,
 400         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 401 };
 402
 403 /* GENET v4 supports 40-bits pointer addressing
 404  * for obvious reasons the LO and HI word parts
 405  * are contiguous, but this offsets the other
 406  * registers.
 407  */
 408 static const u8 genet_dma_ring_regs_v4[] = {
 409         [TDMA_READ_PTR]                 = 0x00,
 410         [TDMA_READ_PTR_HI]              = 0x04,
 411         [TDMA_CONS_INDEX]               = 0x08,
 412         [TDMA_PROD_INDEX]               = 0x0C,
 413         [DMA_RING_BUF_SIZE]             = 0x10,
 414         [DMA_START_ADDR]                = 0x14,
 415         [DMA_START_ADDR_HI]             = 0x18,
 416         [DMA_END_ADDR]                  = 0x1C,
 417         [DMA_END_ADDR_HI]               = 0x20,
 418         [DMA_MBUF_DONE_THRESH]          = 0x24,
 419         [TDMA_FLOW_PERIOD]              = 0x28,
 420         [TDMA_WRITE_PTR]                = 0x2C,
 421         [TDMA_WRITE_PTR_HI]             = 0x30,
 422 };
 423
 424 static const u8 genet_dma_ring_regs_v123[] = {
 425         [TDMA_READ_PTR]                 = 0x00,
 426         [TDMA_CONS_INDEX]               = 0x04,
 427         [TDMA_PROD_INDEX]               = 0x08,
 428         [DMA_RING_BUF_SIZE]             = 0x0C,
 429         [DMA_START_ADDR]                = 0x10,
 430         [DMA_END_ADDR]                  = 0x14,
 431         [DMA_MBUF_DONE_THRESH]          = 0x18,
 432         [TDMA_FLOW_PERIOD]              = 0x1C,
 433         [TDMA_WRITE_PTR]                = 0x20,
 434 };
 435
 436 /* Set at runtime once GENET version is known */
 437 static const u8 *genet_dma_ring_regs;
 438
 439 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 440                                            unsigned int ring,
 441                                            enum dma_ring_reg r)
 442 {
 443         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 444                               (DMA_RING_SIZE * ring) +
 445                               genet_dma_ring_regs[r]);
 446 }
 447
 448 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 449                                              unsigned int ring, u32 val,
 450                                              enum dma_ring_reg r)
 451 {
 452         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 453                         (DMA_RING_SIZE * ring) +
 454                         genet_dma_ring_regs[r]);
 455 }
 456
 457 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 458                                            unsigned int ring,
 459                                            enum dma_ring_reg r)
 460 {
 461         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 462                               (DMA_RING_SIZE * ring) +
 463                               genet_dma_ring_regs[r]);
 464 }
 465
 466 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 467                                              unsigned int ring, u32 val,
 468                                              enum dma_ring_reg r)
 469 {
 470         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 471                         (DMA_RING_SIZE * ring) +
 472                         genet_dma_ring_regs[r]);
 473 }
 474
 475 static int bcmgenet_begin(struct net_device *dev)
 476 {
 477         struct bcmgenet_priv *priv = netdev_priv(dev);
 478
 479         /* Turn on the clock */
 480         return clk_prepare_enable(priv->clk);
 481 }
 482
 483 static void bcmgenet_complete(struct net_device *dev)
 484 {
 485         struct bcmgenet_priv *priv = netdev_priv(dev);
 486
 487         /* Turn off the clock */
 488         clk_disable_unprepare(priv->clk);
 489 }
 490
 491 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 492                                        struct ethtool_link_ksettings *cmd)
 493 {
 494         struct bcmgenet_priv *priv = netdev_priv(dev);
 495
 496         if (!netif_running(dev))
 497                 return -EINVAL;
 498
 499         if (!priv->phydev)
 500                 return -ENODEV;
 501
 502         phy_ethtool_ksettings_get(priv->phydev, cmd);
 503
 504         return 0;
 505 }
 506
 507 static int bcmgenet_set_link_ksettings(struct net_device *dev,
 508                                        const struct ethtool_link_ksettings *cmd)
 509 {
 510         struct bcmgenet_priv *priv = netdev_priv(dev);
 511
 512         if (!netif_running(dev))
 513                 return -EINVAL;
 514
 515         if (!priv->phydev)
 516                 return -ENODEV;
 517
 518         return phy_ethtool_ksettings_set(priv->phydev, cmd);
 519 }
 520
 521 static int bcmgenet_set_rx_csum(struct net_device *dev,
 522                                 netdev_features_t wanted)
 523 {
 524         struct bcmgenet_priv *priv = netdev_priv(dev);
 525         u32 rbuf_chk_ctrl;
 526         bool rx_csum_en;
 527
 528         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 529
 530         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 531
 532         /* enable rx checksumming */
 533         if (rx_csum_en)
 534                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 535         else
 536                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 537         priv->desc_rxchk_en = rx_csum_en;
 538
 539         /* If UniMAC forwards CRC, we need to skip over it to get
 540          * a valid CHK bit to be set in the per-packet status word
 541         */
 542         if (rx_csum_en && priv->crc_fwd_en)
 543                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 544         else
 545                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 546
 547         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 548
 549         return 0;
 550 }
 551
 552 static int bcmgenet_set_tx_csum(struct net_device *dev,
 553                                 netdev_features_t wanted)
 554 {
 555         struct bcmgenet_priv *priv = netdev_priv(dev);
 556         bool desc_64b_en;
 557         u32 tbuf_ctrl, rbuf_ctrl;
 558
 559         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 560         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 561
 562         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 563
 564         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 565         if (desc_64b_en) {
 566                 tbuf_ctrl |= RBUF_64B_EN;
 567                 rbuf_ctrl |= RBUF_64B_EN;
 568         } else {
 569                 tbuf_ctrl &= ~RBUF_64B_EN;
 570                 rbuf_ctrl &= ~RBUF_64B_EN;
 571         }
 572         priv->desc_64b_en = desc_64b_en;
 573
 574         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 575         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 576
 577         return 0;
 578 }
 579
 580 static int bcmgenet_set_features(struct net_device *dev,
 581                                  netdev_features_t features)
 582 {
 583         netdev_features_t changed = features ^ dev->features;
 584         netdev_features_t wanted = dev->wanted_features;
 585         int ret = 0;
 586
 587         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 588                 ret = bcmgenet_set_tx_csum(dev, wanted);
 589         if (changed & (NETIF_F_RXCSUM))
 590                 ret = bcmgenet_set_rx_csum(dev, wanted);
 591
 592         return ret;
 593 }
 594
 595 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 596 {
 597         struct bcmgenet_priv *priv = netdev_priv(dev);
 598
 599         return priv->msg_enable;
 600 }
 601
 602 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 603 {
 604         struct bcmgenet_priv *priv = netdev_priv(dev);
 605
 606         priv->msg_enable = level;
 607 }
 608
 609 static int bcmgenet_get_coalesce(struct net_device *dev,
 610                                  struct ethtool_coalesce *ec)
 611 {
 612         struct bcmgenet_priv *priv = netdev_priv(dev);
 613
 614         ec->tx_max_coalesced_frames =
 615                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 616                                          DMA_MBUF_DONE_THRESH);
 617         ec->rx_max_coalesced_frames =
 618                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 619                                          DMA_MBUF_DONE_THRESH);
 620         ec->rx_coalesce_usecs =
 621                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 622
 623         return 0;
 624 }
 625
 626 static int bcmgenet_set_coalesce(struct net_device *dev,
 627                                  struct ethtool_coalesce *ec)
 628 {
 629         struct bcmgenet_priv *priv = netdev_priv(dev);
 630         unsigned int i;
 631         u32 reg;
 632
 633         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 634          * divided by 1024, which yields roughly 8.192us, our maximum value
 635          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 636          */
 637         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 638             ec->tx_max_coalesced_frames == 0 ||
 639             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 640             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 641                 return -EINVAL;
 642
 643         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 644                 return -EINVAL;
 645
 646         /* GENET TDMA hardware does not support a configurable timeout, but will
 647          * always generate an interrupt either after MBDONE packets have been
 648          * transmitted, or when the ring is empty.
 649          */
 650         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 651             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 652                 return -EOPNOTSUPP;
 653
 654         /* Program all TX queues with the same values, as there is no
 655          * ethtool knob to do coalescing on a per-queue basis
 656          */
 657         for (i = 0; i < priv->hw_params->tx_queues; i++)
 658                 bcmgenet_tdma_ring_writel(priv, i,
 659                                           ec->tx_max_coalesced_frames,
 660                                           DMA_MBUF_DONE_THRESH);
 661         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 662                                   ec->tx_max_coalesced_frames,
 663                                   DMA_MBUF_DONE_THRESH);
 664
 665         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 666                 bcmgenet_rdma_ring_writel(priv, i,
 667                                           ec->rx_max_coalesced_frames,
 668                                           DMA_MBUF_DONE_THRESH);
 669
 670                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 671                 reg &= ~DMA_TIMEOUT_MASK;
 672                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 673                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 674         }
 675
 676         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 677                                   ec->rx_max_coalesced_frames,
 678                                   DMA_MBUF_DONE_THRESH);
 679
 680         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 681         reg &= ~DMA_TIMEOUT_MASK;
 682         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 683         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 684
 685         return 0;
 686 }
 687
 688 /* standard ethtool support functions. */
 689 enum bcmgenet_stat_type {
 690         BCMGENET_STAT_NETDEV = -1,
 691         BCMGENET_STAT_MIB_RX,
 692         BCMGENET_STAT_MIB_TX,
 693         BCMGENET_STAT_RUNT,
 694         BCMGENET_STAT_MISC,
 695         BCMGENET_STAT_SOFT,
 696 };
 697
 698 struct bcmgenet_stats {
 699         char stat_string[ETH_GSTRING_LEN];
 700         int stat_sizeof;
 701         int stat_offset;
 702         enum bcmgenet_stat_type type;
 703         /* reg offset from UMAC base for misc counters */
 704         u16 reg_offset;
 705 };
 706
 707 #define STAT_NETDEV(m) { \
 708         .stat_string = __stringify(m), \
 709         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 710         .stat_offset = offsetof(struct net_device_stats, m), \
 711         .type = BCMGENET_STAT_NETDEV, \
 712 }
 713
 714 #define STAT_GENET_MIB(str, m, _type) { \
 715         .stat_string = str, \
 716         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 717         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 718         .type = _type, \
 719 }
 720
 721 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 722 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 723 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 724 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 725
 726 #define STAT_GENET_MISC(str, m, offset) { \
 727         .stat_string = str, \
 728         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 729         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 730         .type = BCMGENET_STAT_MISC, \
 731         .reg_offset = offset, \
 732 }
 733
 734 #define STAT_GENET_Q(num) \
 735         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
 736                         tx_rings[num].packets), \
 737         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
 738                         tx_rings[num].bytes), \
 739         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
 740                         rx_rings[num].bytes),    \
 741         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
 742                         rx_rings[num].packets), \
 743         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
 744                         rx_rings[num].errors), \
 745         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
 746                         rx_rings[num].dropped)
 747
 748 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 749  * between the end of TX stats and the beginning of the RX RUNT
 750  */
 751 #define BCMGENET_STAT_OFFSET    0xc
 752
 753 /* Hardware counters must be kept in sync because the order/offset
 754  * is important here (order in structure declaration = order in hardware)
 755  */
 756 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 757         /* general stats */
 758         STAT_NETDEV(rx_packets),
 759         STAT_NETDEV(tx_packets),
 760         STAT_NETDEV(rx_bytes),
 761         STAT_NETDEV(tx_bytes),
 762         STAT_NETDEV(rx_errors),
 763         STAT_NETDEV(tx_errors),
 764         STAT_NETDEV(rx_dropped),
 765         STAT_NETDEV(tx_dropped),
 766         STAT_NETDEV(multicast),
 767         /* UniMAC RSV counters */
 768         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 769         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 770         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 771         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 772         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 773         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 774         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 775         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 776         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 777         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 778         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 779         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 780         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 781         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 782         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 783         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 784         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 785         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 786         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 787         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 788         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 789         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 790         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 791         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 792         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 793         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 794         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 795         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 796         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 797         /* UniMAC TSV counters */
 798         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 799         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 800         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 801         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 802         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 803         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 804         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 805         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 806         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 807         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 808         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 809         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 810         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 811         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 812         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 813         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 814         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 815         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 816         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 817         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 818         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 819         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 820         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 821         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 822         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 823         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 824         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 825         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 826         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 827         /* UniMAC RUNT counters */
 828         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 829         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 830         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 831         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 832         /* Misc UniMAC counters */
 833         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 834                         UMAC_RBUF_OVFL_CNT_V1),
 835         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
 836                         UMAC_RBUF_ERR_CNT_V1),
 837         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 838         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 839         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 840         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 841         /* Per TX queues */
 842         STAT_GENET_Q(0),
 843         STAT_GENET_Q(1),
 844         STAT_GENET_Q(2),
 845         STAT_GENET_Q(3),
 846         STAT_GENET_Q(16),
 847 };
 848
 849 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 850
 851 static void bcmgenet_get_drvinfo(struct net_device *dev,
 852                                  struct ethtool_drvinfo *info)
 853 {
 854         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 855         strlcpy(info->version, "v2.0", sizeof(info->version));
 856 }
 857
 858 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 859 {
 860         switch (string_set) {
 861         case ETH_SS_STATS:
 862                 return BCMGENET_STATS_LEN;
 863         default:
 864                 return -EOPNOTSUPP;
 865         }
 866 }
 867
 868 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 869                                  u8 *data)
 870 {
 871         int i;
 872
 873         switch (stringset) {
 874         case ETH_SS_STATS:
 875                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 876                         memcpy(data + i * ETH_GSTRING_LEN,
 877                                bcmgenet_gstrings_stats[i].stat_string,
 878                                ETH_GSTRING_LEN);
 879                 }
 880                 break;
 881         }
 882 }
 883
 884 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
 885 {
 886         u16 new_offset;
 887         u32 val;
 888
 889         switch (offset) {
 890         case UMAC_RBUF_OVFL_CNT_V1:
 891                 if (GENET_IS_V2(priv))
 892                         new_offset = RBUF_OVFL_CNT_V2;
 893                 else
 894                         new_offset = RBUF_OVFL_CNT_V3PLUS;
 895
 896                 val = bcmgenet_rbuf_readl(priv, new_offset);
 897                 /* clear if overflowed */
 898                 if (val == ~0)
 899                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 900                 break;
 901         case UMAC_RBUF_ERR_CNT_V1:
 902                 if (GENET_IS_V2(priv))
 903                         new_offset = RBUF_ERR_CNT_V2;
 904                 else
 905                         new_offset = RBUF_ERR_CNT_V3PLUS;
 906
 907                 val = bcmgenet_rbuf_readl(priv, new_offset);
 908                 /* clear if overflowed */
 909                 if (val == ~0)
 910                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 911                 break;
 912         default:
 913                 val = bcmgenet_umac_readl(priv, offset);
 914                 /* clear if overflowed */
 915                 if (val == ~0)
 916                         bcmgenet_umac_writel(priv, 0, offset);
 917                 break;
 918         }
 919
 920         return val;
 921 }
 922
 923 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 924 {
 925         int i, j = 0;
 926
 927         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 928                 const struct bcmgenet_stats *s;
 929                 u8 offset = 0;
 930                 u32 val = 0;
 931                 char *p;
 932
 933                 s = &bcmgenet_gstrings_stats[i];
 934                 switch (s->type) {
 935                 case BCMGENET_STAT_NETDEV:
 936                 case BCMGENET_STAT_SOFT:
 937                         continue;
 938                 case BCMGENET_STAT_RUNT:
 939                         offset += BCMGENET_STAT_OFFSET;
 940                         /* fall through */
 941                 case BCMGENET_STAT_MIB_TX:
 942                         offset += BCMGENET_STAT_OFFSET;
 943                         /* fall through */
 944                 case BCMGENET_STAT_MIB_RX:
 945                         val = bcmgenet_umac_readl(priv,
 946                                                   UMAC_MIB_START + j + offset);
 947                         offset = 0;     /* Reset Offset */
 948                         break;
 949                 case BCMGENET_STAT_MISC:
 950                         if (GENET_IS_V1(priv)) {
 951                                 val = bcmgenet_umac_readl(priv, s->reg_offset);
 952                                 /* clear if overflowed */
 953                                 if (val == ~0)
 954                                         bcmgenet_umac_writel(priv, 0,
 955                                                              s->reg_offset);
 956                         } else {
 957                                 val = bcmgenet_update_stat_misc(priv,
 958                                                                 s->reg_offset);
 959                         }
 960                         break;
 961                 }
 962
 963                 j += s->stat_sizeof;
 964                 p = (char *)priv + s->stat_offset;
 965                 *(u32 *)p = val;
 966         }
 967 }
 968
 969 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 970                                        struct ethtool_stats *stats,
 971                                        u64 *data)
 972 {
 973         struct bcmgenet_priv *priv = netdev_priv(dev);
 974         int i;
 975
 976         if (netif_running(dev))
 977                 bcmgenet_update_mib_counters(priv);
 978
 979         dev->netdev_ops->ndo_get_stats(dev);
 980
 981         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 982                 const struct bcmgenet_stats *s;
 983                 char *p;
 984
 985                 s = &bcmgenet_gstrings_stats[i];
 986                 if (s->type == BCMGENET_STAT_NETDEV)
 987                         p = (char *)&dev->stats;
 988                 else
 989                         p = (char *)priv;
 990                 p += s->stat_offset;
 991                 if (sizeof(unsigned long) != sizeof(u32) &&
 992                     s->stat_sizeof == sizeof(unsigned long))
 993                         data[i] = *(unsigned long *)p;
 994                 else
 995                         data[i] = *(u32 *)p;
 996         }
 997 }
 998
 999 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1000 {
1001         struct bcmgenet_priv *priv = netdev_priv(dev);
1002         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1003         u32 reg;
1004
1005         if (enable && !priv->clk_eee_enabled) {
1006                 clk_prepare_enable(priv->clk_eee);
1007                 priv->clk_eee_enabled = true;
1008         }
1009
1010         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1011         if (enable)
1012                 reg |= EEE_EN;
1013         else
1014                 reg &= ~EEE_EN;
1015         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1016
1017         /* Enable EEE and switch to a 27Mhz clock automatically */
1018         reg = bcmgenet_readl(priv->base + off);
1019         if (enable)
1020                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1021         else
1022                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1023         bcmgenet_writel(reg, priv->base + off);
1024
1025         /* Do the same for thing for RBUF */
1026         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1027         if (enable)
1028                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1029         else
1030                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1031         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1032
1033         if (!enable && priv->clk_eee_enabled) {
1034                 clk_disable_unprepare(priv->clk_eee);
1035                 priv->clk_eee_enabled = false;
1036         }
1037
1038         priv->eee.eee_enabled = enable;
1039         priv->eee.eee_active = enable;
1040 }
1041
1042 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1043 {
1044         struct bcmgenet_priv *priv = netdev_priv(dev);
1045         struct ethtool_eee *p = &priv->eee;
1046
1047         if (GENET_IS_V1(priv))
1048                 return -EOPNOTSUPP;
1049
1050         e->eee_enabled = p->eee_enabled;
1051         e->eee_active = p->eee_active;
1052         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1053
1054         return phy_ethtool_get_eee(priv->phydev, e);
1055 }
1056
1057 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1058 {
1059         struct bcmgenet_priv *priv = netdev_priv(dev);
1060         struct ethtool_eee *p = &priv->eee;
1061         int ret = 0;
1062
1063         if (GENET_IS_V1(priv))
1064                 return -EOPNOTSUPP;
1065
1066         p->eee_enabled = e->eee_enabled;
1067
1068         if (!p->eee_enabled) {
1069                 bcmgenet_eee_enable_set(dev, false);
1070         } else {
1071                 ret = phy_init_eee(priv->phydev, 0);
1072                 if (ret) {
1073                         netif_err(priv, hw, dev, "EEE initialization failed\n");
1074                         return ret;
1075                 }
1076
1077                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1078                 bcmgenet_eee_enable_set(dev, true);
1079         }
1080
1081         return phy_ethtool_set_eee(priv->phydev, e);
1082 }
1083
1084 /* standard ethtool support functions. */
1085 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1086         .begin                  = bcmgenet_begin,
1087         .complete               = bcmgenet_complete,
1088         .get_strings            = bcmgenet_get_strings,
1089         .get_sset_count         = bcmgenet_get_sset_count,
1090         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
1091         .get_drvinfo            = bcmgenet_get_drvinfo,
1092         .get_link               = ethtool_op_get_link,
1093         .get_msglevel           = bcmgenet_get_msglevel,
1094         .set_msglevel           = bcmgenet_set_msglevel,
1095         .get_wol                = bcmgenet_get_wol,
1096         .set_wol                = bcmgenet_set_wol,
1097         .get_eee                = bcmgenet_get_eee,
1098         .set_eee                = bcmgenet_set_eee,
1099         .nway_reset             = phy_ethtool_nway_reset,
1100         .get_coalesce           = bcmgenet_get_coalesce,
1101         .set_coalesce           = bcmgenet_set_coalesce,
1102         .get_link_ksettings     = bcmgenet_get_link_ksettings,
1103         .set_link_ksettings     = bcmgenet_set_link_ksettings,
1104 };
1105
1106 /* Power down the unimac, based on mode. */
1107 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1108                                 enum bcmgenet_power_mode mode)
1109 {
1110         int ret = 0;
1111         u32 reg;
1112
1113         switch (mode) {
1114         case GENET_POWER_CABLE_SENSE:
1115                 phy_detach(priv->phydev);
1116                 break;
1117
1118         case GENET_POWER_WOL_MAGIC:
1119                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1120                 break;
1121
1122         case GENET_POWER_PASSIVE:
1123                 /* Power down LED */
1124                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1125                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1126                         if (GENET_IS_V5(priv))
1127                                 reg |= EXT_PWR_DOWN_PHY_EN |
1128                                        EXT_PWR_DOWN_PHY_RD |
1129                                        EXT_PWR_DOWN_PHY_SD |
1130                                        EXT_PWR_DOWN_PHY_RX |
1131                                        EXT_PWR_DOWN_PHY_TX |
1132                                        EXT_IDDQ_GLBL_PWR;
1133                         else
1134                                 reg |= EXT_PWR_DOWN_PHY;
1135
1136                         reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1137                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1138
1139                         bcmgenet_phy_power_set(priv->dev, false);
1140                 }
1141                 break;
1142         default:
1143                 break;
1144         }
1145
1146         return ret;
1147 }
1148
1149 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1150                               enum bcmgenet_power_mode mode)
1151 {
1152         u32 reg;
1153
1154         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1155                 return;
1156
1157         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1158
1159         switch (mode) {
1160         case GENET_POWER_PASSIVE:
1161                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1162                          EXT_ENERGY_DET_MASK);
1163                 if (GENET_IS_V5(priv)) {
1164                         reg &= ~(EXT_PWR_DOWN_PHY_EN |
1165                                  EXT_PWR_DOWN_PHY_RD |
1166                                  EXT_PWR_DOWN_PHY_SD |
1167                                  EXT_PWR_DOWN_PHY_RX |
1168                                  EXT_PWR_DOWN_PHY_TX |
1169                                  EXT_IDDQ_GLBL_PWR);
1170                         reg |=   EXT_PHY_RESET;
1171                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1172                         mdelay(1);
1173
1174                         reg &=  ~EXT_PHY_RESET;
1175                 } else {
1176                         reg &= ~EXT_PWR_DOWN_PHY;
1177                         reg |= EXT_PWR_DN_EN_LD;
1178                 }
1179                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1180                 bcmgenet_phy_power_set(priv->dev, true);
1181                 bcmgenet_mii_reset(priv->dev);
1182                 break;
1183
1184         case GENET_POWER_CABLE_SENSE:
1185                 /* enable APD */
1186                 if (!GENET_IS_V5(priv)) {
1187                         reg |= EXT_PWR_DN_EN_LD;
1188                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1189                 }
1190                 break;
1191         case GENET_POWER_WOL_MAGIC:
1192                 bcmgenet_wol_power_up_cfg(priv, mode);
1193                 return;
1194         default:
1195                 break;
1196         }
1197 }
1198
1199 /* ioctl handle special commands that are not present in ethtool. */
1200 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1201 {
1202         struct bcmgenet_priv *priv = netdev_priv(dev);
1203
1204         if (!netif_running(dev))
1205                 return -EINVAL;
1206
1207         if (!priv->phydev)
1208                 return -ENODEV;
1209
1210         return phy_mii_ioctl(priv->phydev, rq, cmd);
1211 }
1212
1213 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1214                                          struct bcmgenet_tx_ring *ring)
1215 {
1216         struct enet_cb *tx_cb_ptr;
1217
1218         tx_cb_ptr = ring->cbs;
1219         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1220
1221         /* Advancing local write pointer */
1222         if (ring->write_ptr == ring->end_ptr)
1223                 ring->write_ptr = ring->cb_ptr;
1224         else
1225                 ring->write_ptr++;
1226
1227         return tx_cb_ptr;
1228 }
1229
1230 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1231                                          struct bcmgenet_tx_ring *ring)
1232 {
1233         struct enet_cb *tx_cb_ptr;
1234
1235         tx_cb_ptr = ring->cbs;
1236         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1237
1238         /* Rewinding local write pointer */
1239         if (ring->write_ptr == ring->cb_ptr)
1240                 ring->write_ptr = ring->end_ptr;
1241         else
1242                 ring->write_ptr--;
1243
1244         return tx_cb_ptr;
1245 }
1246
1247 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1248 {
1249         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1250                                  INTRL2_CPU_MASK_SET);
1251 }
1252
1253 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1254 {
1255         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1256                                  INTRL2_CPU_MASK_CLEAR);
1257 }
1258
1259 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1260 {
1261         bcmgenet_intrl2_1_writel(ring->priv,
1262                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1263                                  INTRL2_CPU_MASK_SET);
1264 }
1265
1266 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1267 {
1268         bcmgenet_intrl2_1_writel(ring->priv,
1269                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1270                                  INTRL2_CPU_MASK_CLEAR);
1271 }
1272
1273 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1274 {
1275         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1276                                  INTRL2_CPU_MASK_SET);
1277 }
1278
1279 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1280 {
1281         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1282                                  INTRL2_CPU_MASK_CLEAR);
1283 }
1284
1285 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1286 {
1287         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1288                                  INTRL2_CPU_MASK_CLEAR);
1289 }
1290
1291 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1292 {
1293         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1294                                  INTRL2_CPU_MASK_SET);
1295 }
1296
1297 /* Simple helper to free a transmit control block's resources
1298  * Returns an skb when the last transmit control block associated with the
1299  * skb is freed.  The skb should be freed by the caller if necessary.
1300  */
1301 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1302                                            struct enet_cb *cb)
1303 {
1304         struct sk_buff *skb;
1305
1306         skb = cb->skb;
1307
1308         if (skb) {
1309                 cb->skb = NULL;
1310                 if (cb == GENET_CB(skb)->first_cb)
1311                         dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1312                                          dma_unmap_len(cb, dma_len),
1313                                          DMA_TO_DEVICE);
1314                 else
1315                         dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1316                                        dma_unmap_len(cb, dma_len),
1317                                        DMA_TO_DEVICE);
1318                 dma_unmap_addr_set(cb, dma_addr, 0);
1319
1320                 if (cb == GENET_CB(skb)->last_cb)
1321                         return skb;
1322
1323         } else if (dma_unmap_addr(cb, dma_addr)) {
1324                 dma_unmap_page(dev,
1325                                dma_unmap_addr(cb, dma_addr),
1326                                dma_unmap_len(cb, dma_len),
1327                                DMA_TO_DEVICE);
1328                 dma_unmap_addr_set(cb, dma_addr, 0);
1329         }
1330
1331         return 0;
1332 }
1333
1334 /* Simple helper to free a receive control block's resources */
1335 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1336                                            struct enet_cb *cb)
1337 {
1338         struct sk_buff *skb;
1339
1340         skb = cb->skb;
1341         cb->skb = NULL;
1342
1343         if (dma_unmap_addr(cb, dma_addr)) {
1344                 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1345                                  dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1346                 dma_unmap_addr_set(cb, dma_addr, 0);
1347         }
1348
1349         return skb;
1350 }
1351
1352 /* Unlocked version of the reclaim routine */
1353 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1354                                           struct bcmgenet_tx_ring *ring)
1355 {
1356         struct bcmgenet_priv *priv = netdev_priv(dev);
1357         unsigned int txbds_processed = 0;
1358         unsigned int bytes_compl = 0;
1359         unsigned int pkts_compl = 0;
1360         unsigned int txbds_ready;
1361         unsigned int c_index;
1362         struct sk_buff *skb;
1363
1364         /* Clear status before servicing to reduce spurious interrupts */
1365         if (ring->index == DESC_INDEX)
1366                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1367                                          INTRL2_CPU_CLEAR);
1368         else
1369                 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1370                                          INTRL2_CPU_CLEAR);
1371
1372         /* Compute how many buffers are transmitted since last xmit call */
1373         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1374                 & DMA_C_INDEX_MASK;
1375         txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1376
1377         netif_dbg(priv, tx_done, dev,
1378                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1379                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1380
1381         /* Reclaim transmitted buffers */
1382         while (txbds_processed < txbds_ready) {
1383                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1384                                           &priv->tx_cbs[ring->clean_ptr]);
1385                 if (skb) {
1386                         pkts_compl++;
1387                         bytes_compl += GENET_CB(skb)->bytes_sent;
1388                         dev_consume_skb_any(skb);
1389                 }
1390
1391                 txbds_processed++;
1392                 if (likely(ring->clean_ptr < ring->end_ptr))
1393                         ring->clean_ptr++;
1394                 else
1395                         ring->clean_ptr = ring->cb_ptr;
1396         }
1397
1398         ring->free_bds += txbds_processed;
1399         ring->c_index = c_index;
1400
1401         ring->packets += pkts_compl;
1402         ring->bytes += bytes_compl;
1403
1404         netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1405                                   pkts_compl, bytes_compl);
1406
1407         return txbds_processed;
1408 }
1409
1410 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1411                                 struct bcmgenet_tx_ring *ring)
1412 {
1413         unsigned int released;
1414         unsigned long flags;
1415
1416         spin_lock_irqsave(&ring->lock, flags);
1417         released = __bcmgenet_tx_reclaim(dev, ring);
1418         spin_unlock_irqrestore(&ring->lock, flags);
1419
1420         return released;
1421 }
1422
1423 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1424 {
1425         struct bcmgenet_tx_ring *ring =
1426                 container_of(napi, struct bcmgenet_tx_ring, napi);
1427         unsigned int work_done = 0;
1428         struct netdev_queue *txq;
1429         unsigned long flags;
1430
1431         spin_lock_irqsave(&ring->lock, flags);
1432         work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1433         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1434                 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1435                 netif_tx_wake_queue(txq);
1436         }
1437         spin_unlock_irqrestore(&ring->lock, flags);
1438
1439         if (work_done == 0) {
1440                 napi_complete(napi);
1441                 ring->int_enable(ring);
1442
1443                 return 0;
1444         }
1445
1446         return budget;
1447 }
1448
1449 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1450 {
1451         struct bcmgenet_priv *priv = netdev_priv(dev);
1452         int i;
1453
1454         if (netif_is_multiqueue(dev)) {
1455                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1456                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1457         }
1458
1459         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1460 }
1461
1462 /* Reallocate the SKB to put enough headroom in front of it and insert
1463  * the transmit checksum offsets in the descriptors
1464  */
1465 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1466                                             struct sk_buff *skb)
1467 {
1468         struct status_64 *status = NULL;
1469         struct sk_buff *new_skb;
1470         u16 offset;
1471         u8 ip_proto;
1472         u16 ip_ver;
1473         u32 tx_csum_info;
1474
1475         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1476                 /* If 64 byte status block enabled, must make sure skb has
1477                  * enough headroom for us to insert 64B status block.
1478                  */
1479                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1480                 dev_kfree_skb(skb);
1481                 if (!new_skb) {
1482                         dev->stats.tx_dropped++;
1483                         return NULL;
1484                 }
1485                 skb = new_skb;
1486         }
1487
1488         skb_push(skb, sizeof(*status));
1489         status = (struct status_64 *)skb->data;
1490
1491         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1492                 ip_ver = htons(skb->protocol);
1493                 switch (ip_ver) {
1494                 case ETH_P_IP:
1495                         ip_proto = ip_hdr(skb)->protocol;
1496                         break;
1497                 case ETH_P_IPV6:
1498                         ip_proto = ipv6_hdr(skb)->nexthdr;
1499                         break;
1500                 default:
1501                         return skb;
1502                 }
1503
1504                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1505                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1506                                 (offset + skb->csum_offset);
1507
1508                 /* Set the length valid bit for TCP and UDP and just set
1509                  * the special UDP flag for IPv4, else just set to 0.
1510                  */
1511                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1512                         tx_csum_info |= STATUS_TX_CSUM_LV;
1513                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1514                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1515                 } else {
1516                         tx_csum_info = 0;
1517                 }
1518
1519                 status->tx_csum_info = tx_csum_info;
1520         }
1521
1522         return skb;
1523 }
1524
1525 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1526 {
1527         struct bcmgenet_priv *priv = netdev_priv(dev);
1528         struct device *kdev = &priv->pdev->dev;
1529         struct bcmgenet_tx_ring *ring = NULL;
1530         struct enet_cb *tx_cb_ptr;
1531         struct netdev_queue *txq;
1532         unsigned long flags = 0;
1533         int nr_frags, index;
1534         dma_addr_t mapping;
1535         unsigned int size;
1536         skb_frag_t *frag;
1537         u32 len_stat;
1538         int ret;
1539         int i;
1540
1541         index = skb_get_queue_mapping(skb);
1542         /* Mapping strategy:
1543          * queue_mapping = 0, unclassified, packet xmited through ring16
1544          * queue_mapping = 1, goes to ring 0. (highest priority queue
1545          * queue_mapping = 2, goes to ring 1.
1546          * queue_mapping = 3, goes to ring 2.
1547          * queue_mapping = 4, goes to ring 3.
1548          */
1549         if (index == 0)
1550                 index = DESC_INDEX;
1551         else
1552                 index -= 1;
1553
1554         ring = &priv->tx_rings[index];
1555         txq = netdev_get_tx_queue(dev, ring->queue);
1556
1557         nr_frags = skb_shinfo(skb)->nr_frags;
1558
1559         spin_lock_irqsave(&ring->lock, flags);
1560         if (ring->free_bds <= (nr_frags + 1)) {
1561                 if (!netif_tx_queue_stopped(txq)) {
1562                         netif_tx_stop_queue(txq);
1563                         netdev_err(dev,
1564                                    "%s: tx ring %d full when queue %d awake\n",
1565                                    __func__, index, ring->queue);
1566                 }
1567                 ret = NETDEV_TX_BUSY;
1568                 goto out;
1569         }
1570
1571         /* Retain how many bytes will be sent on the wire, without TSB inserted
1572          * by transmit checksum offload
1573          */
1574         GENET_CB(skb)->bytes_sent = skb->len;
1575
1576         /* set the SKB transmit checksum */
1577         if (priv->desc_64b_en) {
1578                 skb = bcmgenet_put_tx_csum(dev, skb);
1579                 if (!skb) {
1580                         ret = NETDEV_TX_OK;
1581                         goto out;
1582                 }
1583         }
1584
1585         for (i = 0; i <= nr_frags; i++) {
1586                 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1587
1588                 if (unlikely(!tx_cb_ptr))
1589                         BUG();
1590
1591                 if (!i) {
1592                         /* Transmit single SKB or head of fragment list */
1593                         GENET_CB(skb)->first_cb = tx_cb_ptr;
1594                         size = skb_headlen(skb);
1595                         mapping = dma_map_single(kdev, skb->data, size,
1596                                                  DMA_TO_DEVICE);
1597                 } else {
1598                         /* xmit fragment */
1599                         frag = &skb_shinfo(skb)->frags[i - 1];
1600                         size = skb_frag_size(frag);
1601                         mapping = skb_frag_dma_map(kdev, frag, 0, size,
1602                                                    DMA_TO_DEVICE);
1603                 }
1604
1605                 ret = dma_mapping_error(kdev, mapping);
1606                 if (ret) {
1607                         priv->mib.tx_dma_failed++;
1608                         netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1609                         ret = NETDEV_TX_OK;
1610                         goto out_unmap_frags;
1611                 }
1612                 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1613                 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1614
1615                 tx_cb_ptr->skb = skb;
1616
1617                 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1618                            (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1619
1620                 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
1621                  * will need to restore software padding of "runt" packets
1622                  */
1623                 if (!i) {
1624                         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1625                         if (skb->ip_summed == CHECKSUM_PARTIAL)
1626                                 len_stat |= DMA_TX_DO_CSUM;
1627                 }
1628                 if (i == nr_frags)
1629                         len_stat |= DMA_EOP;
1630
1631                 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1632         }
1633
1634         GENET_CB(skb)->last_cb = tx_cb_ptr;
1635         skb_tx_timestamp(skb);
1636
1637         /* Decrement total BD count and advance our write pointer */
1638         ring->free_bds -= nr_frags + 1;
1639         ring->prod_index += nr_frags + 1;
1640         ring->prod_index &= DMA_P_INDEX_MASK;
1641
1642         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1643
1644         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1645                 netif_tx_stop_queue(txq);
1646
1647         if (!skb->xmit_more || netif_xmit_stopped(txq))
1648                 /* Packets are ready, update producer index */
1649                 bcmgenet_tdma_ring_writel(priv, ring->index,
1650                                           ring->prod_index, TDMA_PROD_INDEX);
1651 out:
1652         spin_unlock_irqrestore(&ring->lock, flags);
1653
1654         return ret;
1655
1656 out_unmap_frags:
1657         /* Back up for failed control block mapping */
1658         bcmgenet_put_txcb(priv, ring);
1659
1660         /* Unmap successfully mapped control blocks */
1661         while (i-- > 0) {
1662                 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1663                 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1664         }
1665
1666         dev_kfree_skb(skb);
1667         goto out;
1668 }
1669
1670 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1671                                           struct enet_cb *cb)
1672 {
1673         struct device *kdev = &priv->pdev->dev;
1674         struct sk_buff *skb;
1675         struct sk_buff *rx_skb;
1676         dma_addr_t mapping;
1677
1678         /* Allocate a new Rx skb */
1679         skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1680                                  GFP_ATOMIC | __GFP_NOWARN);
1681         if (!skb) {
1682                 priv->mib.alloc_rx_buff_failed++;
1683                 netif_err(priv, rx_err, priv->dev,
1684                           "%s: Rx skb allocation failed\n", __func__);
1685                 return NULL;
1686         }
1687
1688         /* DMA-map the new Rx skb */
1689         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1690                                  DMA_FROM_DEVICE);
1691         if (dma_mapping_error(kdev, mapping)) {
1692                 priv->mib.rx_dma_failed++;
1693                 dev_kfree_skb_any(skb);
1694                 netif_err(priv, rx_err, priv->dev,
1695                           "%s: Rx skb DMA mapping failed\n", __func__);
1696                 return NULL;
1697         }
1698
1699         /* Grab the current Rx skb from the ring and DMA-unmap it */
1700         rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1701
1702         /* Put the new Rx skb on the ring */
1703         cb->skb = skb;
1704         dma_unmap_addr_set(cb, dma_addr, mapping);
1705         dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1706         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1707
1708         /* Return the current Rx skb to caller */
1709         return rx_skb;
1710 }
1711
1712 /* bcmgenet_desc_rx - descriptor based rx process.
1713  * this could be called from bottom half, or from NAPI polling method.
1714  */
1715 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1716                                      unsigned int budget)
1717 {
1718         struct bcmgenet_priv *priv = ring->priv;
1719         struct net_device *dev = priv->dev;
1720         struct enet_cb *cb;
1721         struct sk_buff *skb;
1722         u32 dma_length_status;
1723         unsigned long dma_flag;
1724         int len;
1725         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1726         unsigned int p_index, mask;
1727         unsigned int discards;
1728         unsigned int chksum_ok = 0;
1729
1730         /* Clear status before servicing to reduce spurious interrupts */
1731         if (ring->index == DESC_INDEX) {
1732                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1733                                          INTRL2_CPU_CLEAR);
1734         } else {
1735                 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1736                 bcmgenet_intrl2_1_writel(priv,
1737                                          mask,
1738                                          INTRL2_CPU_CLEAR);
1739         }
1740
1741         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1742
1743         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1744                    DMA_P_INDEX_DISCARD_CNT_MASK;
1745         if (discards > ring->old_discards) {
1746                 discards = discards - ring->old_discards;
1747                 ring->errors += discards;
1748                 ring->old_discards += discards;
1749
1750                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1751                 if (ring->old_discards >= 0xC000) {
1752                         ring->old_discards = 0;
1753                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1754                                                   RDMA_PROD_INDEX);
1755                 }
1756         }
1757
1758         p_index &= DMA_P_INDEX_MASK;
1759         rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1760
1761         netif_dbg(priv, rx_status, dev,
1762                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1763
1764         while ((rxpktprocessed < rxpkttoprocess) &&
1765                (rxpktprocessed < budget)) {
1766                 cb = &priv->rx_cbs[ring->read_ptr];
1767                 skb = bcmgenet_rx_refill(priv, cb);
1768
1769                 if (unlikely(!skb)) {
1770                         ring->dropped++;
1771                         goto next;
1772                 }
1773
1774                 if (!priv->desc_64b_en) {
1775                         dma_length_status =
1776                                 dmadesc_get_length_status(priv, cb->bd_addr);
1777                 } else {
1778                         struct status_64 *status;
1779
1780                         status = (struct status_64 *)skb->data;
1781                         dma_length_status = status->length_status;
1782                 }
1783
1784                 /* DMA flags and length are still valid no matter how
1785                  * we got the Receive Status Vector (64B RSB or register)
1786                  */
1787                 dma_flag = dma_length_status & 0xffff;
1788                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1789
1790                 netif_dbg(priv, rx_status, dev,
1791                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1792                           __func__, p_index, ring->c_index,
1793                           ring->read_ptr, dma_length_status);
1794
1795                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1796                         netif_err(priv, rx_status, dev,
1797                                   "dropping fragmented packet!\n");
1798                         ring->errors++;
1799                         dev_kfree_skb_any(skb);
1800                         goto next;
1801                 }
1802
1803                 /* report errors */
1804                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1805                                                 DMA_RX_OV |
1806                                                 DMA_RX_NO |
1807                                                 DMA_RX_LG |
1808                                                 DMA_RX_RXER))) {
1809                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1810                                   (unsigned int)dma_flag);
1811                         if (dma_flag & DMA_RX_CRC_ERROR)
1812                                 dev->stats.rx_crc_errors++;
1813                         if (dma_flag & DMA_RX_OV)
1814                                 dev->stats.rx_over_errors++;
1815                         if (dma_flag & DMA_RX_NO)
1816                                 dev->stats.rx_frame_errors++;
1817                         if (dma_flag & DMA_RX_LG)
1818                                 dev->stats.rx_length_errors++;
1819                         dev->stats.rx_errors++;
1820                         dev_kfree_skb_any(skb);
1821                         goto next;
1822                 } /* error packet */
1823
1824                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1825                              priv->desc_rxchk_en;
1826
1827                 skb_put(skb, len);
1828                 if (priv->desc_64b_en) {
1829                         skb_pull(skb, 64);
1830                         len -= 64;
1831                 }
1832
1833                 if (likely(chksum_ok))
1834                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1835
1836                 /* remove hardware 2bytes added for IP alignment */
1837                 skb_pull(skb, 2);
1838                 len -= 2;
1839
1840                 if (priv->crc_fwd_en) {
1841                         skb_trim(skb, len - ETH_FCS_LEN);
1842                         len -= ETH_FCS_LEN;
1843                 }
1844
1845                 /*Finish setting up the received SKB and send it to the kernel*/
1846                 skb->protocol = eth_type_trans(skb, priv->dev);
1847                 ring->packets++;
1848                 ring->bytes += len;
1849                 if (dma_flag & DMA_RX_MULT)
1850                         dev->stats.multicast++;
1851
1852                 /* Notify kernel */
1853                 napi_gro_receive(&ring->napi, skb);
1854                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1855
1856 next:
1857                 rxpktprocessed++;
1858                 if (likely(ring->read_ptr < ring->end_ptr))
1859                         ring->read_ptr++;
1860                 else
1861                         ring->read_ptr = ring->cb_ptr;
1862
1863                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1864                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1865         }
1866
1867         return rxpktprocessed;
1868 }
1869
1870 /* Rx NAPI polling method */
1871 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1872 {
1873         struct bcmgenet_rx_ring *ring = container_of(napi,
1874                         struct bcmgenet_rx_ring, napi);
1875         unsigned int work_done;
1876
1877         work_done = bcmgenet_desc_rx(ring, budget);
1878
1879         if (work_done < budget) {
1880                 napi_complete_done(napi, work_done);
1881                 ring->int_enable(ring);
1882         }
1883
1884         return work_done;
1885 }
1886
1887 /* Assign skb to RX DMA descriptor. */
1888 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1889                                      struct bcmgenet_rx_ring *ring)
1890 {
1891         struct enet_cb *cb;
1892         struct sk_buff *skb;
1893         int i;
1894
1895         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1896
1897         /* loop here for each buffer needing assign */
1898         for (i = 0; i < ring->size; i++) {
1899                 cb = ring->cbs + i;
1900                 skb = bcmgenet_rx_refill(priv, cb);
1901                 if (skb)
1902                         dev_consume_skb_any(skb);
1903                 if (!cb->skb)
1904                         return -ENOMEM;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1911 {
1912         struct sk_buff *skb;
1913         struct enet_cb *cb;
1914         int i;
1915
1916         for (i = 0; i < priv->num_rx_bds; i++) {
1917                 cb = &priv->rx_cbs[i];
1918
1919                 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1920                 if (skb)
1921                         dev_consume_skb_any(skb);
1922         }
1923 }
1924
1925 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1926 {
1927         u32 reg;
1928
1929         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1930         if (enable)
1931                 reg |= mask;
1932         else
1933                 reg &= ~mask;
1934         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1935
1936         /* UniMAC stops on a packet boundary, wait for a full-size packet
1937          * to be processed
1938          */
1939         if (enable == 0)
1940                 usleep_range(1000, 2000);
1941 }
1942
1943 static int reset_umac(struct bcmgenet_priv *priv)
1944 {
1945         struct device *kdev = &priv->pdev->dev;
1946         unsigned int timeout = 0;
1947         u32 reg;
1948
1949         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1950         bcmgenet_rbuf_ctrl_set(priv, 0);
1951         udelay(10);
1952
1953         /* disable MAC while updating its registers */
1954         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1955
1956         /* issue soft reset, wait for it to complete */
1957         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1958         while (timeout++ < 1000) {
1959                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1960                 if (!(reg & CMD_SW_RESET))
1961                         return 0;
1962
1963                 udelay(1);
1964         }
1965
1966         if (timeout == 1000) {
1967                 dev_err(kdev,
1968                         "timeout waiting for MAC to come out of reset\n");
1969                 return -ETIMEDOUT;
1970         }
1971
1972         return 0;
1973 }
1974
1975 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1976 {
1977         /* Mask all interrupts.*/
1978         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1979         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1980         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1981         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1982 }
1983
1984 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1985 {
1986         u32 int0_enable = 0;
1987
1988         /* Monitor cable plug/unplugged event for internal PHY, external PHY
1989          * and MoCA PHY
1990          */
1991         if (priv->internal_phy) {
1992                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1993                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
1994                         int0_enable |= UMAC_IRQ_PHY_DET_R;
1995         } else if (priv->ext_phy) {
1996                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1997         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1998                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1999                         int0_enable |= UMAC_IRQ_LINK_EVENT;
2000         }
2001         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2002 }
2003
2004 static int init_umac(struct bcmgenet_priv *priv)
2005 {
2006         struct device *kdev = &priv->pdev->dev;
2007         int ret;
2008         u32 reg;
2009         u32 int0_enable = 0;
2010
2011         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2012
2013         ret = reset_umac(priv);
2014         if (ret)
2015                 return ret;
2016
2017         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2018         /* clear tx/rx counter */
2019         bcmgenet_umac_writel(priv,
2020                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2021                              UMAC_MIB_CTRL);
2022         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2023
2024         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2025
2026         /* init rx registers, enable ip header optimization */
2027         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2028         reg |= RBUF_ALIGN_2B;
2029         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2030
2031         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2032                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2033
2034         bcmgenet_intr_disable(priv);
2035
2036         /* Configure backpressure vectors for MoCA */
2037         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2038                 reg = bcmgenet_bp_mc_get(priv);
2039                 reg |= BIT(priv->hw_params->bp_in_en_shift);
2040
2041                 /* bp_mask: back pressure mask */
2042                 if (netif_is_multiqueue(priv->dev))
2043                         reg |= priv->hw_params->bp_in_mask;
2044                 else
2045                         reg &= ~priv->hw_params->bp_in_mask;
2046                 bcmgenet_bp_mc_set(priv, reg);
2047         }
2048
2049         /* Enable MDIO interrupts on GENET v3+ */
2050         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2051                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2052
2053         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2054
2055         dev_dbg(kdev, "done init umac\n");
2056
2057         return 0;
2058 }
2059
2060 /* Initialize a Tx ring along with corresponding hardware registers */
2061 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2062                                   unsigned int index, unsigned int size,
2063                                   unsigned int start_ptr, unsigned int end_ptr)
2064 {
2065         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2066         u32 words_per_bd = WORDS_PER_BD(priv);
2067         u32 flow_period_val = 0;
2068
2069         spin_lock_init(&ring->lock);
2070         ring->priv = priv;
2071         ring->index = index;
2072         if (index == DESC_INDEX) {
2073                 ring->queue = 0;
2074                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2075                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2076         } else {
2077                 ring->queue = index + 1;
2078                 ring->int_enable = bcmgenet_tx_ring_int_enable;
2079                 ring->int_disable = bcmgenet_tx_ring_int_disable;
2080         }
2081         ring->cbs = priv->tx_cbs + start_ptr;
2082         ring->size = size;
2083         ring->clean_ptr = start_ptr;
2084         ring->c_index = 0;
2085         ring->free_bds = size;
2086         ring->write_ptr = start_ptr;
2087         ring->cb_ptr = start_ptr;
2088         ring->end_ptr = end_ptr - 1;
2089         ring->prod_index = 0;
2090
2091         /* Set flow period for ring != 16 */
2092         if (index != DESC_INDEX)
2093                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2094
2095         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2096         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2097         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2098         /* Disable rate control for now */
2099         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2100                                   TDMA_FLOW_PERIOD);
2101         bcmgenet_tdma_ring_writel(priv, index,
2102                                   ((size << DMA_RING_SIZE_SHIFT) |
2103                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2104
2105         /* Set start and end address, read and write pointers */
2106         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2107                                   DMA_START_ADDR);
2108         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2109                                   TDMA_READ_PTR);
2110         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2111                                   TDMA_WRITE_PTR);
2112         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2113                                   DMA_END_ADDR);
2114 }
2115
2116 /* Initialize a RDMA ring */
2117 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2118                                  unsigned int index, unsigned int size,
2119                                  unsigned int start_ptr, unsigned int end_ptr)
2120 {
2121         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2122         u32 words_per_bd = WORDS_PER_BD(priv);
2123         int ret;
2124
2125         ring->priv = priv;
2126         ring->index = index;
2127         if (index == DESC_INDEX) {
2128                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2129                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2130         } else {
2131                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2132                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2133         }
2134         ring->cbs = priv->rx_cbs + start_ptr;
2135         ring->size = size;
2136         ring->c_index = 0;
2137         ring->read_ptr = start_ptr;
2138         ring->cb_ptr = start_ptr;
2139         ring->end_ptr = end_ptr - 1;
2140
2141         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2142         if (ret)
2143                 return ret;
2144
2145         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2146         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2147         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2148         bcmgenet_rdma_ring_writel(priv, index,
2149                                   ((size << DMA_RING_SIZE_SHIFT) |
2150                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2151         bcmgenet_rdma_ring_writel(priv, index,
2152                                   (DMA_FC_THRESH_LO <<
2153                                    DMA_XOFF_THRESHOLD_SHIFT) |
2154                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2155
2156         /* Set start and end address, read and write pointers */
2157         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2158                                   DMA_START_ADDR);
2159         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2160                                   RDMA_READ_PTR);
2161         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2162                                   RDMA_WRITE_PTR);
2163         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2164                                   DMA_END_ADDR);
2165
2166         return ret;
2167 }
2168
2169 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2170 {
2171         unsigned int i;
2172         struct bcmgenet_tx_ring *ring;
2173
2174         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2175                 ring = &priv->tx_rings[i];
2176                 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2177         }
2178
2179         ring = &priv->tx_rings[DESC_INDEX];
2180         netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2181 }
2182
2183 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2184 {
2185         unsigned int i;
2186         u32 int0_enable = UMAC_IRQ_TXDMA_DONE;
2187         u32 int1_enable = 0;
2188         struct bcmgenet_tx_ring *ring;
2189
2190         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2191                 ring = &priv->tx_rings[i];
2192                 napi_enable(&ring->napi);
2193                 int1_enable |= (1 << i);
2194         }
2195
2196         ring = &priv->tx_rings[DESC_INDEX];
2197         napi_enable(&ring->napi);
2198
2199         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2200         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2201 }
2202
2203 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2204 {
2205         unsigned int i;
2206         u32 int0_disable = UMAC_IRQ_TXDMA_DONE;
2207         u32 int1_disable = 0xffff;
2208         struct bcmgenet_tx_ring *ring;
2209
2210         bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2211         bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2212
2213         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2214                 ring = &priv->tx_rings[i];
2215                 napi_disable(&ring->napi);
2216         }
2217
2218         ring = &priv->tx_rings[DESC_INDEX];
2219         napi_disable(&ring->napi);
2220 }
2221
2222 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2223 {
2224         unsigned int i;
2225         struct bcmgenet_tx_ring *ring;
2226
2227         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2228                 ring = &priv->tx_rings[i];
2229                 netif_napi_del(&ring->napi);
2230         }
2231
2232         ring = &priv->tx_rings[DESC_INDEX];
2233         netif_napi_del(&ring->napi);
2234 }
2235
2236 /* Initialize Tx queues
2237  *
2238  * Queues 0-3 are priority-based, each one has 32 descriptors,
2239  * with queue 0 being the highest priority queue.
2240  *
2241  * Queue 16 is the default Tx queue with
2242  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2243  *
2244  * The transmit control block pool is then partitioned as follows:
2245  * - Tx queue 0 uses tx_cbs[0..31]
2246  * - Tx queue 1 uses tx_cbs[32..63]
2247  * - Tx queue 2 uses tx_cbs[64..95]
2248  * - Tx queue 3 uses tx_cbs[96..127]
2249  * - Tx queue 16 uses tx_cbs[128..255]
2250  */
2251 static void bcmgenet_init_tx_queues(struct net_device *dev)
2252 {
2253         struct bcmgenet_priv *priv = netdev_priv(dev);
2254         u32 i, dma_enable;
2255         u32 dma_ctrl, ring_cfg;
2256         u32 dma_priority[3] = {0, 0, 0};
2257
2258         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2259         dma_enable = dma_ctrl & DMA_EN;
2260         dma_ctrl &= ~DMA_EN;
2261         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2262
2263         dma_ctrl = 0;
2264         ring_cfg = 0;
2265
2266         /* Enable strict priority arbiter mode */
2267         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2268
2269         /* Initialize Tx priority queues */
2270         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2271                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2272                                       i * priv->hw_params->tx_bds_per_q,
2273                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2274                 ring_cfg |= (1 << i);
2275                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2276                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2277                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2278         }
2279
2280         /* Initialize Tx default queue 16 */
2281         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2282                               priv->hw_params->tx_queues *
2283                               priv->hw_params->tx_bds_per_q,
2284                               TOTAL_DESC);
2285         ring_cfg |= (1 << DESC_INDEX);
2286         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2287         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2288                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2289                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2290
2291         /* Set Tx queue priorities */
2292         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2293         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2294         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2295
2296         /* Initialize Tx NAPI */
2297         bcmgenet_init_tx_napi(priv);
2298
2299         /* Enable Tx queues */
2300         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2301
2302         /* Enable Tx DMA */
2303         if (dma_enable)
2304                 dma_ctrl |= DMA_EN;
2305         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2306 }
2307
2308 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2309 {
2310         unsigned int i;
2311         struct bcmgenet_rx_ring *ring;
2312
2313         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2314                 ring = &priv->rx_rings[i];
2315                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2316         }
2317
2318         ring = &priv->rx_rings[DESC_INDEX];
2319         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2320 }
2321
2322 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2323 {
2324         unsigned int i;
2325         u32 int0_enable = UMAC_IRQ_RXDMA_DONE;
2326         u32 int1_enable = 0;
2327         struct bcmgenet_rx_ring *ring;
2328
2329         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2330                 ring = &priv->rx_rings[i];
2331                 napi_enable(&ring->napi);
2332                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
2333         }
2334
2335         ring = &priv->rx_rings[DESC_INDEX];
2336         napi_enable(&ring->napi);
2337
2338         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2339         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2340 }
2341
2342 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2343 {
2344         unsigned int i;
2345         u32 int0_disable = UMAC_IRQ_RXDMA_DONE;
2346         u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT;
2347         struct bcmgenet_rx_ring *ring;
2348
2349         bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2350         bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2351
2352         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2353                 ring = &priv->rx_rings[i];
2354                 napi_disable(&ring->napi);
2355         }
2356
2357         ring = &priv->rx_rings[DESC_INDEX];
2358         napi_disable(&ring->napi);
2359 }
2360
2361 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2362 {
2363         unsigned int i;
2364         struct bcmgenet_rx_ring *ring;
2365
2366         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2367                 ring = &priv->rx_rings[i];
2368                 netif_napi_del(&ring->napi);
2369         }
2370
2371         ring = &priv->rx_rings[DESC_INDEX];
2372         netif_napi_del(&ring->napi);
2373 }
2374
2375 /* Initialize Rx queues
2376  *
2377  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2378  * used to direct traffic to these queues.
2379  *
2380  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2381  */
2382 static int bcmgenet_init_rx_queues(struct net_device *dev)
2383 {
2384         struct bcmgenet_priv *priv = netdev_priv(dev);
2385         u32 i;
2386         u32 dma_enable;
2387         u32 dma_ctrl;
2388         u32 ring_cfg;
2389         int ret;
2390
2391         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2392         dma_enable = dma_ctrl & DMA_EN;
2393         dma_ctrl &= ~DMA_EN;
2394         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2395
2396         dma_ctrl = 0;
2397         ring_cfg = 0;
2398
2399         /* Initialize Rx priority queues */
2400         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2401                 ret = bcmgenet_init_rx_ring(priv, i,
2402                                             priv->hw_params->rx_bds_per_q,
2403                                             i * priv->hw_params->rx_bds_per_q,
2404                                             (i + 1) *
2405                                             priv->hw_params->rx_bds_per_q);
2406                 if (ret)
2407                         return ret;
2408
2409                 ring_cfg |= (1 << i);
2410                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2411         }
2412
2413         /* Initialize Rx default queue 16 */
2414         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2415                                     priv->hw_params->rx_queues *
2416                                     priv->hw_params->rx_bds_per_q,
2417                                     TOTAL_DESC);
2418         if (ret)
2419                 return ret;
2420
2421         ring_cfg |= (1 << DESC_INDEX);
2422         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2423
2424         /* Initialize Rx NAPI */
2425         bcmgenet_init_rx_napi(priv);
2426
2427         /* Enable rings */
2428         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2429
2430         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2431         if (dma_enable)
2432                 dma_ctrl |= DMA_EN;
2433         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2434
2435         return 0;
2436 }
2437
2438 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2439 {
2440         int ret = 0;
2441         int timeout = 0;
2442         u32 reg;
2443         u32 dma_ctrl;
2444         int i;
2445
2446         /* Disable TDMA to stop add more frames in TX DMA */
2447         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2448         reg &= ~DMA_EN;
2449         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2450
2451         /* Check TDMA status register to confirm TDMA is disabled */
2452         while (timeout++ < DMA_TIMEOUT_VAL) {
2453                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2454                 if (reg & DMA_DISABLED)
2455                         break;
2456
2457                 udelay(1);
2458         }
2459
2460         if (timeout == DMA_TIMEOUT_VAL) {
2461                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2462                 ret = -ETIMEDOUT;
2463         }
2464
2465         /* Wait 10ms for packet drain in both tx and rx dma */
2466         usleep_range(10000, 20000);
2467
2468         /* Disable RDMA */
2469         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2470         reg &= ~DMA_EN;
2471         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2472
2473         timeout = 0;
2474         /* Check RDMA status register to confirm RDMA is disabled */
2475         while (timeout++ < DMA_TIMEOUT_VAL) {
2476                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2477                 if (reg & DMA_DISABLED)
2478                         break;
2479
2480                 udelay(1);
2481         }
2482
2483         if (timeout == DMA_TIMEOUT_VAL) {
2484                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2485                 ret = -ETIMEDOUT;
2486         }
2487
2488         dma_ctrl = 0;
2489         for (i = 0; i < priv->hw_params->rx_queues; i++)
2490                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2491         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2492         reg &= ~dma_ctrl;
2493         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2494
2495         dma_ctrl = 0;
2496         for (i = 0; i < priv->hw_params->tx_queues; i++)
2497                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2498         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2499         reg &= ~dma_ctrl;
2500         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2501
2502         return ret;
2503 }
2504
2505 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2506 {
2507         struct netdev_queue *txq;
2508         struct sk_buff *skb;
2509         struct enet_cb *cb;
2510         int i;
2511
2512         bcmgenet_fini_rx_napi(priv);
2513         bcmgenet_fini_tx_napi(priv);
2514
2515         /* disable DMA */
2516         bcmgenet_dma_teardown(priv);
2517
2518         for (i = 0; i < priv->num_tx_bds; i++) {
2519                 cb = priv->tx_cbs + i;
2520                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2521                 if (skb)
2522                         dev_kfree_skb(skb);
2523         }
2524
2525         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2526                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2527                 netdev_tx_reset_queue(txq);
2528         }
2529
2530         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2531         netdev_tx_reset_queue(txq);
2532
2533         bcmgenet_free_rx_buffers(priv);
2534         kfree(priv->rx_cbs);
2535         kfree(priv->tx_cbs);
2536 }
2537
2538 /* init_edma: Initialize DMA control register */
2539 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2540 {
2541         int ret;
2542         unsigned int i;
2543         struct enet_cb *cb;
2544
2545         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2546
2547         /* Initialize common Rx ring structures */
2548         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2549         priv->num_rx_bds = TOTAL_DESC;
2550         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2551                                GFP_KERNEL);
2552         if (!priv->rx_cbs)
2553                 return -ENOMEM;
2554
2555         for (i = 0; i < priv->num_rx_bds; i++) {
2556                 cb = priv->rx_cbs + i;
2557                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2558         }
2559
2560         /* Initialize common TX ring structures */
2561         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2562         priv->num_tx_bds = TOTAL_DESC;
2563         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2564                                GFP_KERNEL);
2565         if (!priv->tx_cbs) {
2566                 kfree(priv->rx_cbs);
2567                 return -ENOMEM;
2568         }
2569
2570         for (i = 0; i < priv->num_tx_bds; i++) {
2571                 cb = priv->tx_cbs + i;
2572                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2573         }
2574
2575         /* Init rDma */
2576         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2577
2578         /* Initialize Rx queues */
2579         ret = bcmgenet_init_rx_queues(priv->dev);
2580         if (ret) {
2581                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2582                 bcmgenet_free_rx_buffers(priv);
2583                 kfree(priv->rx_cbs);
2584                 kfree(priv->tx_cbs);
2585                 return ret;
2586         }
2587
2588         /* Init tDma */
2589         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2590
2591         /* Initialize Tx queues */
2592         bcmgenet_init_tx_queues(priv->dev);
2593
2594         return 0;
2595 }
2596
2597 /* Interrupt bottom half */
2598 static void bcmgenet_irq_task(struct work_struct *work)
2599 {
2600         unsigned long flags;
2601         unsigned int status;
2602         struct bcmgenet_priv *priv = container_of(
2603                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2604
2605         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2606
2607         spin_lock_irqsave(&priv->lock, flags);
2608         status = priv->irq0_stat;
2609         priv->irq0_stat = 0;
2610         spin_unlock_irqrestore(&priv->lock, flags);
2611
2612         if (status & UMAC_IRQ_MPD_R) {
2613                 netif_dbg(priv, wol, priv->dev,
2614                           "magic packet detected, waking up\n");
2615                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2616         }
2617
2618         if (status & UMAC_IRQ_PHY_DET_R &&
2619             priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2620                 phy_init_hw(priv->dev->phydev);
2621                 genphy_config_aneg(priv->dev->phydev);
2622         }
2623
2624         /* Link UP/DOWN event */
2625         if (status & UMAC_IRQ_LINK_EVENT)
2626                 phy_mac_interrupt(priv->phydev,
2627                                   !!(status & UMAC_IRQ_LINK_UP));
2628 }
2629
2630 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2631 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2632 {
2633         struct bcmgenet_priv *priv = dev_id;
2634         struct bcmgenet_rx_ring *rx_ring;
2635         struct bcmgenet_tx_ring *tx_ring;
2636         unsigned int index, status;
2637
2638         /* Read irq status */
2639         status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2640                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2641
2642         /* clear interrupts */
2643         bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2644
2645         netif_dbg(priv, intr, priv->dev,
2646                   "%s: IRQ=0x%x\n", __func__, status);
2647
2648         /* Check Rx priority queue interrupts */
2649         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2650                 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2651                         continue;
2652
2653                 rx_ring = &priv->rx_rings[index];
2654
2655                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2656                         rx_ring->int_disable(rx_ring);
2657                         __napi_schedule_irqoff(&rx_ring->napi);
2658                 }
2659         }
2660
2661         /* Check Tx priority queue interrupts */
2662         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2663                 if (!(status & BIT(index)))
2664                         continue;
2665
2666                 tx_ring = &priv->tx_rings[index];
2667
2668                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2669                         tx_ring->int_disable(tx_ring);
2670                         __napi_schedule_irqoff(&tx_ring->napi);
2671                 }
2672         }
2673
2674         return IRQ_HANDLED;
2675 }
2676
2677 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2678 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2679 {
2680         struct bcmgenet_priv *priv = dev_id;
2681         struct bcmgenet_rx_ring *rx_ring;
2682         struct bcmgenet_tx_ring *tx_ring;
2683         unsigned int status;
2684         unsigned long flags;
2685
2686         /* Read irq status */
2687         status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2688                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2689
2690         /* clear interrupts */
2691         bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2692
2693         netif_dbg(priv, intr, priv->dev,
2694                   "IRQ=0x%x\n", status);
2695
2696         if (status & UMAC_IRQ_RXDMA_DONE) {
2697                 rx_ring = &priv->rx_rings[DESC_INDEX];
2698
2699                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2700                         rx_ring->int_disable(rx_ring);
2701                         __napi_schedule_irqoff(&rx_ring->napi);
2702                 }
2703         }
2704
2705         if (status & UMAC_IRQ_TXDMA_DONE) {
2706                 tx_ring = &priv->tx_rings[DESC_INDEX];
2707
2708                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2709                         tx_ring->int_disable(tx_ring);
2710                         __napi_schedule_irqoff(&tx_ring->napi);
2711                 }
2712         }
2713
2714         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2715                                 UMAC_IRQ_PHY_DET_F |
2716                                 UMAC_IRQ_LINK_EVENT |
2717                                 UMAC_IRQ_HFB_SM |
2718                                 UMAC_IRQ_HFB_MM)) {
2719                 /* all other interested interrupts handled in bottom half */
2720                 schedule_work(&priv->bcmgenet_irq_work);
2721         }
2722
2723         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2724                 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2725                 wake_up(&priv->wq);
2726         }
2727
2728         /* all other interested interrupts handled in bottom half */
2729         status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_MPD_R | UMAC_IRQ_PHY_DET_R);
2730         if (status) {
2731                 /* Save irq status for bottom-half processing. */
2732                 spin_lock_irqsave(&priv->lock, flags);
2733                 priv->irq0_stat |= status;
2734                 spin_unlock_irqrestore(&priv->lock, flags);
2735
2736                 schedule_work(&priv->bcmgenet_irq_work);
2737         }
2738
2739         return IRQ_HANDLED;
2740 }
2741
2742 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2743 {
2744         struct bcmgenet_priv *priv = dev_id;
2745
2746         pm_wakeup_event(&priv->pdev->dev, 0);
2747
2748         return IRQ_HANDLED;
2749 }
2750
2751 #ifdef CONFIG_NET_POLL_CONTROLLER
2752 static void bcmgenet_poll_controller(struct net_device *dev)
2753 {
2754         struct bcmgenet_priv *priv = netdev_priv(dev);
2755
2756         /* Invoke the main RX/TX interrupt handler */
2757         disable_irq(priv->irq0);
2758         bcmgenet_isr0(priv->irq0, priv);
2759         enable_irq(priv->irq0);
2760
2761         /* And the interrupt handler for RX/TX priority queues */
2762         disable_irq(priv->irq1);
2763         bcmgenet_isr1(priv->irq1, priv);
2764         enable_irq(priv->irq1);
2765 }
2766 #endif
2767
2768 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2769 {
2770         u32 reg;
2771
2772         reg = bcmgenet_rbuf_ctrl_get(priv);
2773         reg |= BIT(1);
2774         bcmgenet_rbuf_ctrl_set(priv, reg);
2775         udelay(10);
2776
2777         reg &= ~BIT(1);
2778         bcmgenet_rbuf_ctrl_set(priv, reg);
2779         udelay(10);
2780 }
2781
2782 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2783                                  unsigned char *addr)
2784 {
2785         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2786                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2787         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2788 }
2789
2790 /* Returns a reusable dma control register value */
2791 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2792 {
2793         unsigned int i;
2794         u32 reg;
2795         u32 dma_ctrl;
2796
2797         /* disable DMA */
2798         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2799         for (i = 0; i < priv->hw_params->tx_queues; i++)
2800                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2801         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2802         reg &= ~dma_ctrl;
2803         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2804
2805         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2806         for (i = 0; i < priv->hw_params->rx_queues; i++)
2807                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2808         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2809         reg &= ~dma_ctrl;
2810         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2811
2812         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2813         udelay(10);
2814         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2815
2816         return dma_ctrl;
2817 }
2818
2819 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2820 {
2821         u32 reg;
2822
2823         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2824         reg |= dma_ctrl;
2825         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2826
2827         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2828         reg |= dma_ctrl;
2829         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2830 }
2831
2832 /* bcmgenet_hfb_clear
2833  *
2834  * Clear Hardware Filter Block and disable all filtering.
2835  */
2836 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2837 {
2838         u32 i;
2839
2840         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2841         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2842         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2843
2844         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2845                 bcmgenet_rdma_writel(priv, 0x0, i);
2846
2847         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2848                 bcmgenet_hfb_reg_writel(priv, 0x0,
2849                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2850
2851         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2852                         priv->hw_params->hfb_filter_size; i++)
2853                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2854 }
2855
2856 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2857 {
2858         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2859                 return;
2860
2861         bcmgenet_hfb_clear(priv);
2862 }
2863
2864 static void bcmgenet_netif_start(struct net_device *dev)
2865 {
2866         struct bcmgenet_priv *priv = netdev_priv(dev);
2867
2868         /* Start the network engine */
2869         bcmgenet_set_rx_mode(dev);
2870         bcmgenet_enable_rx_napi(priv);
2871         bcmgenet_enable_tx_napi(priv);
2872
2873         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2874
2875         netif_tx_start_all_queues(dev);
2876
2877         /* Monitor link interrupts now */
2878         bcmgenet_link_intr_enable(priv);
2879
2880         phy_start(priv->phydev);
2881 }
2882
2883 static int bcmgenet_open(struct net_device *dev)
2884 {
2885         struct bcmgenet_priv *priv = netdev_priv(dev);
2886         unsigned long dma_ctrl;
2887         u32 reg;
2888         int ret;
2889
2890         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2891
2892         /* Turn on the clock */
2893         clk_prepare_enable(priv->clk);
2894
2895         /* If this is an internal GPHY, power it back on now, before UniMAC is
2896          * brought out of reset as absolutely no UniMAC activity is allowed
2897          */
2898         if (priv->internal_phy)
2899                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2900
2901         /* take MAC out of reset */
2902         bcmgenet_umac_reset(priv);
2903
2904         ret = init_umac(priv);
2905         if (ret)
2906                 goto err_clk_disable;
2907
2908         /* disable ethernet MAC while updating its registers */
2909         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2910
2911         /* Make sure we reflect the value of CRC_CMD_FWD */
2912         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2913         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2914
2915         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2916
2917         /* Disable RX/TX DMA and flush TX queues */
2918         dma_ctrl = bcmgenet_dma_disable(priv);
2919
2920         /* Reinitialize TDMA and RDMA and SW housekeeping */
2921         ret = bcmgenet_init_dma(priv);
2922         if (ret) {
2923                 netdev_err(dev, "failed to initialize DMA\n");
2924                 goto err_clk_disable;
2925         }
2926
2927         /* Always enable ring 16 - descriptor ring */
2928         bcmgenet_enable_dma(priv, dma_ctrl);
2929
2930         /* HFB init */
2931         bcmgenet_hfb_init(priv);
2932
2933         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2934                           dev->name, priv);
2935         if (ret < 0) {
2936                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2937                 goto err_fini_dma;
2938         }
2939
2940         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2941                           dev->name, priv);
2942         if (ret < 0) {
2943                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2944                 goto err_irq0;
2945         }
2946
2947         ret = bcmgenet_mii_probe(dev);
2948         if (ret) {
2949                 netdev_err(dev, "failed to connect to PHY\n");
2950                 goto err_irq1;
2951         }
2952
2953         bcmgenet_netif_start(dev);
2954
2955         return 0;
2956
2957 err_irq1:
2958         free_irq(priv->irq1, priv);
2959 err_irq0:
2960         free_irq(priv->irq0, priv);
2961 err_fini_dma:
2962         bcmgenet_fini_dma(priv);
2963 err_clk_disable:
2964         if (priv->internal_phy)
2965                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2966         clk_disable_unprepare(priv->clk);
2967         return ret;
2968 }
2969
2970 static void bcmgenet_netif_stop(struct net_device *dev)
2971 {
2972         struct bcmgenet_priv *priv = netdev_priv(dev);
2973
2974         netif_tx_stop_all_queues(dev);
2975         phy_stop(priv->phydev);
2976         bcmgenet_intr_disable(priv);
2977         bcmgenet_disable_rx_napi(priv);
2978         bcmgenet_disable_tx_napi(priv);
2979
2980         /* Wait for pending work items to complete. Since interrupts are
2981          * disabled no new work will be scheduled.
2982          */
2983         cancel_work_sync(&priv->bcmgenet_irq_work);
2984
2985         priv->old_link = -1;
2986         priv->old_speed = -1;
2987         priv->old_duplex = -1;
2988         priv->old_pause = -1;
2989 }
2990
2991 static int bcmgenet_close(struct net_device *dev)
2992 {
2993         struct bcmgenet_priv *priv = netdev_priv(dev);
2994         int ret;
2995
2996         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2997
2998         bcmgenet_netif_stop(dev);
2999
3000         /* Really kill the PHY state machine and disconnect from it */
3001         phy_disconnect(priv->phydev);
3002
3003         /* Disable MAC receive */
3004         umac_enable_set(priv, CMD_RX_EN, false);
3005
3006         ret = bcmgenet_dma_teardown(priv);
3007         if (ret)
3008                 return ret;
3009
3010         /* Disable MAC transmit. TX DMA disabled must be done before this */
3011         umac_enable_set(priv, CMD_TX_EN, false);
3012
3013         /* tx reclaim */
3014         bcmgenet_tx_reclaim_all(dev);
3015         bcmgenet_fini_dma(priv);
3016
3017         free_irq(priv->irq0, priv);
3018         free_irq(priv->irq1, priv);
3019
3020         if (priv->internal_phy)
3021                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3022
3023         clk_disable_unprepare(priv->clk);
3024
3025         return ret;
3026 }
3027
3028 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3029 {
3030         struct bcmgenet_priv *priv = ring->priv;
3031         u32 p_index, c_index, intsts, intmsk;
3032         struct netdev_queue *txq;
3033         unsigned int free_bds;
3034         unsigned long flags;
3035         bool txq_stopped;
3036
3037         if (!netif_msg_tx_err(priv))
3038                 return;
3039
3040         txq = netdev_get_tx_queue(priv->dev, ring->queue);
3041
3042         spin_lock_irqsave(&ring->lock, flags);
3043         if (ring->index == DESC_INDEX) {
3044                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3045                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3046         } else {
3047                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3048                 intmsk = 1 << ring->index;
3049         }
3050         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3051         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3052         txq_stopped = netif_tx_queue_stopped(txq);
3053         free_bds = ring->free_bds;
3054         spin_unlock_irqrestore(&ring->lock, flags);
3055
3056         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3057                   "TX queue status: %s, interrupts: %s\n"
3058                   "(sw)free_bds: %d (sw)size: %d\n"
3059                   "(sw)p_index: %d (hw)p_index: %d\n"
3060                   "(sw)c_index: %d (hw)c_index: %d\n"
3061                   "(sw)clean_p: %d (sw)write_p: %d\n"
3062                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3063                   ring->index, ring->queue,
3064                   txq_stopped ? "stopped" : "active",
3065                   intsts & intmsk ? "enabled" : "disabled",
3066                   free_bds, ring->size,
3067                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
3068                   ring->c_index, c_index & DMA_C_INDEX_MASK,
3069                   ring->clean_ptr, ring->write_ptr,
3070                   ring->cb_ptr, ring->end_ptr);
3071 }
3072
3073 static void bcmgenet_timeout(struct net_device *dev)
3074 {
3075         struct bcmgenet_priv *priv = netdev_priv(dev);
3076         u32 int0_enable = 0;
3077         u32 int1_enable = 0;
3078         unsigned int q;
3079
3080         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3081
3082         for (q = 0; q < priv->hw_params->tx_queues; q++)
3083                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3084         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3085
3086         bcmgenet_tx_reclaim_all(dev);
3087
3088         for (q = 0; q < priv->hw_params->tx_queues; q++)
3089                 int1_enable |= (1 << q);
3090
3091         int0_enable = UMAC_IRQ_TXDMA_DONE;
3092
3093         /* Re-enable TX interrupts if disabled */
3094         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3095         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3096
3097         netif_trans_update(dev);
3098
3099         dev->stats.tx_errors++;
3100
3101         netif_tx_wake_all_queues(dev);
3102 }
3103
3104 #define MAX_MDF_FILTER  17
3105
3106 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3107                                          unsigned char *addr,
3108                                          int *i)
3109 {
3110         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3111                              UMAC_MDF_ADDR + (*i * 4));
3112         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3113                              addr[4] << 8 | addr[5],
3114                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3115         *i += 2;
3116 }
3117
3118 static void bcmgenet_set_rx_mode(struct net_device *dev)
3119 {
3120         struct bcmgenet_priv *priv = netdev_priv(dev);
3121         struct netdev_hw_addr *ha;
3122         int i, nfilter;
3123         u32 reg;
3124
3125         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3126
3127         /* Number of filters needed */
3128         nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3129
3130         /*
3131          * Turn on promicuous mode for three scenarios
3132          * 1. IFF_PROMISC flag is set
3133          * 2. IFF_ALLMULTI flag is set
3134          * 3. The number of filters needed exceeds the number filters
3135          *    supported by the hardware.
3136         */
3137         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3138         if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3139             (nfilter > MAX_MDF_FILTER)) {
3140                 reg |= CMD_PROMISC;
3141                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3142                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3143                 return;
3144         } else {
3145                 reg &= ~CMD_PROMISC;
3146                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3147         }
3148
3149         /* update MDF filter */
3150         i = 0;
3151         /* Broadcast */
3152         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3153         /* my own address.*/
3154         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3155
3156         /* Unicast */
3157         netdev_for_each_uc_addr(ha, dev)
3158                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3159
3160         /* Multicast */
3161         netdev_for_each_mc_addr(ha, dev)
3162                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3163
3164         /* Enable filters */
3165         reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3166         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3167 }
3168
3169 /* Set the hardware MAC address. */
3170 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3171 {
3172         struct sockaddr *addr = p;
3173
3174         /* Setting the MAC address at the hardware level is not possible
3175          * without disabling the UniMAC RX/TX enable bits.
3176          */
3177         if (netif_running(dev))
3178                 return -EBUSY;
3179
3180         ether_addr_copy(dev->dev_addr, addr->sa_data);
3181
3182         return 0;
3183 }
3184
3185 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3186 {
3187         struct bcmgenet_priv *priv = netdev_priv(dev);
3188         unsigned long tx_bytes = 0, tx_packets = 0;
3189         unsigned long rx_bytes = 0, rx_packets = 0;
3190         unsigned long rx_errors = 0, rx_dropped = 0;
3191         struct bcmgenet_tx_ring *tx_ring;
3192         struct bcmgenet_rx_ring *rx_ring;
3193         unsigned int q;
3194
3195         for (q = 0; q < priv->hw_params->tx_queues; q++) {
3196                 tx_ring = &priv->tx_rings[q];
3197                 tx_bytes += tx_ring->bytes;
3198                 tx_packets += tx_ring->packets;
3199         }
3200         tx_ring = &priv->tx_rings[DESC_INDEX];
3201         tx_bytes += tx_ring->bytes;
3202         tx_packets += tx_ring->packets;
3203
3204         for (q = 0; q < priv->hw_params->rx_queues; q++) {
3205                 rx_ring = &priv->rx_rings[q];
3206
3207                 rx_bytes += rx_ring->bytes;
3208                 rx_packets += rx_ring->packets;
3209                 rx_errors += rx_ring->errors;
3210                 rx_dropped += rx_ring->dropped;
3211         }
3212         rx_ring = &priv->rx_rings[DESC_INDEX];
3213         rx_bytes += rx_ring->bytes;
3214         rx_packets += rx_ring->packets;
3215         rx_errors += rx_ring->errors;
3216         rx_dropped += rx_ring->dropped;
3217
3218         dev->stats.tx_bytes = tx_bytes;
3219         dev->stats.tx_packets = tx_packets;
3220         dev->stats.rx_bytes = rx_bytes;
3221         dev->stats.rx_packets = rx_packets;
3222         dev->stats.rx_errors = rx_errors;
3223         dev->stats.rx_missed_errors = rx_errors;
3224         dev->stats.rx_dropped = rx_dropped;
3225         return &dev->stats;
3226 }
3227
3228 static const struct net_device_ops bcmgenet_netdev_ops = {
3229         .ndo_open               = bcmgenet_open,
3230         .ndo_stop               = bcmgenet_close,
3231         .ndo_start_xmit         = bcmgenet_xmit,
3232         .ndo_tx_timeout         = bcmgenet_timeout,
3233         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3234         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3235         .ndo_do_ioctl           = bcmgenet_ioctl,
3236         .ndo_set_features       = bcmgenet_set_features,
3237 #ifdef CONFIG_NET_POLL_CONTROLLER
3238         .ndo_poll_controller    = bcmgenet_poll_controller,
3239 #endif
3240         .ndo_get_stats          = bcmgenet_get_stats,
3241 };
3242
3243 /* Array of GENET hardware parameters/characteristics */
3244 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3245         [GENET_V1] = {
3246                 .tx_queues = 0,
3247                 .tx_bds_per_q = 0,
3248                 .rx_queues = 0,
3249                 .rx_bds_per_q = 0,
3250                 .bp_in_en_shift = 16,
3251                 .bp_in_mask = 0xffff,
3252                 .hfb_filter_cnt = 16,
3253                 .qtag_mask = 0x1F,
3254                 .hfb_offset = 0x1000,
3255                 .rdma_offset = 0x2000,
3256                 .tdma_offset = 0x3000,
3257                 .words_per_bd = 2,
3258         },
3259         [GENET_V2] = {
3260                 .tx_queues = 4,
3261                 .tx_bds_per_q = 32,
3262                 .rx_queues = 0,
3263                 .rx_bds_per_q = 0,
3264                 .bp_in_en_shift = 16,
3265                 .bp_in_mask = 0xffff,
3266                 .hfb_filter_cnt = 16,
3267                 .qtag_mask = 0x1F,
3268                 .tbuf_offset = 0x0600,
3269                 .hfb_offset = 0x1000,
3270                 .hfb_reg_offset = 0x2000,
3271                 .rdma_offset = 0x3000,
3272                 .tdma_offset = 0x4000,
3273                 .words_per_bd = 2,
3274                 .flags = GENET_HAS_EXT,
3275         },
3276         [GENET_V3] = {
3277                 .tx_queues = 4,
3278                 .tx_bds_per_q = 32,
3279                 .rx_queues = 0,
3280                 .rx_bds_per_q = 0,
3281                 .bp_in_en_shift = 17,
3282                 .bp_in_mask = 0x1ffff,
3283                 .hfb_filter_cnt = 48,
3284                 .hfb_filter_size = 128,
3285                 .qtag_mask = 0x3F,
3286                 .tbuf_offset = 0x0600,
3287                 .hfb_offset = 0x8000,
3288                 .hfb_reg_offset = 0xfc00,
3289                 .rdma_offset = 0x10000,
3290                 .tdma_offset = 0x11000,
3291                 .words_per_bd = 2,
3292                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3293                          GENET_HAS_MOCA_LINK_DET,
3294         },
3295         [GENET_V4] = {
3296                 .tx_queues = 4,
3297                 .tx_bds_per_q = 32,
3298                 .rx_queues = 0,
3299                 .rx_bds_per_q = 0,
3300                 .bp_in_en_shift = 17,
3301                 .bp_in_mask = 0x1ffff,
3302                 .hfb_filter_cnt = 48,
3303                 .hfb_filter_size = 128,
3304                 .qtag_mask = 0x3F,
3305                 .tbuf_offset = 0x0600,
3306                 .hfb_offset = 0x8000,
3307                 .hfb_reg_offset = 0xfc00,
3308                 .rdma_offset = 0x2000,
3309                 .tdma_offset = 0x4000,
3310                 .words_per_bd = 3,
3311                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3312                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3313         },
3314         [GENET_V5] = {
3315                 .tx_queues = 4,
3316                 .tx_bds_per_q = 32,
3317                 .rx_queues = 0,
3318                 .rx_bds_per_q = 0,
3319                 .bp_in_en_shift = 17,
3320                 .bp_in_mask = 0x1ffff,
3321                 .hfb_filter_cnt = 48,
3322                 .hfb_filter_size = 128,
3323                 .qtag_mask = 0x3F,
3324                 .tbuf_offset = 0x0600,
3325                 .hfb_offset = 0x8000,
3326                 .hfb_reg_offset = 0xfc00,
3327                 .rdma_offset = 0x2000,
3328                 .tdma_offset = 0x4000,
3329                 .words_per_bd = 3,
3330                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3331                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3332         },
3333 };
3334
3335 /* Infer hardware parameters from the detected GENET version */
3336 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3337 {
3338         struct bcmgenet_hw_params *params;
3339         u32 reg;
3340         u8 major;
3341         u16 gphy_rev;
3342
3343         if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3344                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3345                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3346                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3347         } else if (GENET_IS_V3(priv)) {
3348                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3349                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3350                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3351         } else if (GENET_IS_V2(priv)) {
3352                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3353                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3354                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3355         } else if (GENET_IS_V1(priv)) {
3356                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3357                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3358                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3359         }
3360
3361         /* enum genet_version starts at 1 */
3362         priv->hw_params = &bcmgenet_hw_params[priv->version];
3363         params = priv->hw_params;
3364
3365         /* Read GENET HW version */
3366         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3367         major = (reg >> 24 & 0x0f);
3368         if (major == 6)
3369                 major = 5;
3370         else if (major == 5)
3371                 major = 4;
3372         else if (major == 0)
3373                 major = 1;
3374         if (major != priv->version) {
3375                 dev_err(&priv->pdev->dev,
3376                         "GENET version mismatch, got: %d, configured for: %d\n",
3377                         major, priv->version);
3378         }
3379
3380         /* Print the GENET core version */
3381         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3382                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3383
3384         /* Store the integrated PHY revision for the MDIO probing function
3385          * to pass this information to the PHY driver. The PHY driver expects
3386          * to find the PHY major revision in bits 15:8 while the GENET register
3387          * stores that information in bits 7:0, account for that.
3388          *
3389          * On newer chips, starting with PHY revision G0, a new scheme is
3390          * deployed similar to the Starfighter 2 switch with GPHY major
3391          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3392          * is reserved as well as special value 0x01ff, we have a small
3393          * heuristic to check for the new GPHY revision and re-arrange things
3394          * so the GPHY driver is happy.
3395          */
3396         gphy_rev = reg & 0xffff;
3397
3398         if (GENET_IS_V5(priv)) {
3399                 /* The EPHY revision should come from the MDIO registers of
3400                  * the PHY not from GENET.
3401                  */
3402                 if (gphy_rev != 0) {
3403                         pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3404                                 gphy_rev);
3405                 }
3406         /* This is reserved so should require special treatment */
3407         } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3408                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3409                 return;
3410         /* This is the good old scheme, just GPHY major, no minor nor patch */
3411         } else if ((gphy_rev & 0xf0) != 0) {
3412                 priv->gphy_rev = gphy_rev << 8;
3413         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3414         } else if ((gphy_rev & 0xff00) != 0) {
3415                 priv->gphy_rev = gphy_rev;
3416         }
3417
3418 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3419         if (!(params->flags & GENET_HAS_40BITS))
3420                 pr_warn("GENET does not support 40-bits PA\n");
3421 #endif
3422
3423         pr_debug("Configuration for version: %d\n"
3424                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3425                 "BP << en: %2d, BP msk: 0x%05x\n"
3426                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3427                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3428                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3429                 "Words/BD: %d\n",
3430                 priv->version,
3431                 params->tx_queues, params->tx_bds_per_q,
3432                 params->rx_queues, params->rx_bds_per_q,
3433                 params->bp_in_en_shift, params->bp_in_mask,
3434                 params->hfb_filter_cnt, params->qtag_mask,
3435                 params->tbuf_offset, params->hfb_offset,
3436                 params->hfb_reg_offset,
3437                 params->rdma_offset, params->tdma_offset,
3438                 params->words_per_bd);
3439 }
3440
3441 static const struct of_device_id bcmgenet_match[] = {
3442         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3443         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3444         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3445         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3446         { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3447         { },
3448 };
3449 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3450
3451 static int bcmgenet_probe(struct platform_device *pdev)
3452 {
3453         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3454         struct device_node *dn = pdev->dev.of_node;
3455         const struct of_device_id *of_id = NULL;
3456         struct bcmgenet_priv *priv;
3457         struct net_device *dev;
3458         const void *macaddr;
3459         struct resource *r;
3460         int err = -EIO;
3461         const char *phy_mode_str;
3462
3463         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3464         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3465                                  GENET_MAX_MQ_CNT + 1);
3466         if (!dev) {
3467                 dev_err(&pdev->dev, "can't allocate net device\n");
3468                 return -ENOMEM;
3469         }
3470
3471         if (dn) {
3472                 of_id = of_match_node(bcmgenet_match, dn);
3473                 if (!of_id)
3474                         return -EINVAL;
3475         }
3476
3477         priv = netdev_priv(dev);
3478         priv->irq0 = platform_get_irq(pdev, 0);
3479         priv->irq1 = platform_get_irq(pdev, 1);
3480         priv->wol_irq = platform_get_irq(pdev, 2);
3481         if (!priv->irq0 || !priv->irq1) {
3482                 dev_err(&pdev->dev, "can't find IRQs\n");
3483                 err = -EINVAL;
3484                 goto err;
3485         }
3486
3487         if (dn) {
3488                 macaddr = of_get_mac_address(dn);
3489                 if (!macaddr) {
3490                         dev_err(&pdev->dev, "can't find MAC address\n");
3491                         err = -EINVAL;
3492                         goto err;
3493                 }
3494         } else {
3495                 macaddr = pd->mac_address;
3496         }
3497
3498         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3499         priv->base = devm_ioremap_resource(&pdev->dev, r);
3500         if (IS_ERR(priv->base)) {
3501                 err = PTR_ERR(priv->base);
3502                 goto err;
3503         }
3504
3505         spin_lock_init(&priv->lock);
3506
3507         SET_NETDEV_DEV(dev, &pdev->dev);
3508         dev_set_drvdata(&pdev->dev, dev);
3509         ether_addr_copy(dev->dev_addr, macaddr);
3510         dev->watchdog_timeo = 2 * HZ;
3511         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3512         dev->netdev_ops = &bcmgenet_netdev_ops;
3513
3514         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3515
3516         /* Set hardware features */
3517         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3518                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3519
3520         /* Request the WOL interrupt and advertise suspend if available */
3521         priv->wol_irq_disabled = true;
3522         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3523                                dev->name, priv);
3524         if (!err)
3525                 device_set_wakeup_capable(&pdev->dev, 1);
3526
3527         /* Set the needed headroom to account for any possible
3528          * features enabling/disabling at runtime
3529          */
3530         dev->needed_headroom += 64;
3531
3532         netdev_boot_setup_check(dev);
3533
3534         priv->dev = dev;
3535         priv->pdev = pdev;
3536         if (of_id)
3537                 priv->version = (enum bcmgenet_version)of_id->data;
3538         else
3539                 priv->version = pd->genet_version;
3540
3541         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3542         if (IS_ERR(priv->clk)) {
3543                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3544                 priv->clk = NULL;
3545         }
3546
3547         clk_prepare_enable(priv->clk);
3548
3549         bcmgenet_set_hw_params(priv);
3550
3551         /* Mii wait queue */
3552         init_waitqueue_head(&priv->wq);
3553         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3554         priv->rx_buf_len = RX_BUF_LENGTH;
3555         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3556
3557         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3558         if (IS_ERR(priv->clk_wol)) {
3559                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3560                 priv->clk_wol = NULL;
3561         }
3562
3563         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3564         if (IS_ERR(priv->clk_eee)) {
3565                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3566                 priv->clk_eee = NULL;
3567         }
3568
3569         /* If this is an internal GPHY, power it on now, before UniMAC is
3570          * brought out of reset as absolutely no UniMAC activity is allowed
3571          */
3572         if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3573             !strcasecmp(phy_mode_str, "internal"))
3574                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3575
3576         err = reset_umac(priv);
3577         if (err)
3578                 goto err_clk_disable;
3579
3580         err = bcmgenet_mii_init(dev);
3581         if (err)
3582                 goto err_clk_disable;
3583
3584         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3585          * just the ring 16 descriptor based TX
3586          */
3587         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3588         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3589
3590         /* libphy will determine the link state */
3591         netif_carrier_off(dev);
3592
3593         /* Turn off the main clock, WOL clock is handled separately */
3594         clk_disable_unprepare(priv->clk);
3595
3596         err = register_netdev(dev);
3597         if (err) {
3598                 bcmgenet_mii_exit(dev);
3599                 goto err;
3600         }
3601
3602         return err;
3603
3604 err_clk_disable:
3605         clk_disable_unprepare(priv->clk);
3606 err:
3607         free_netdev(dev);
3608         return err;
3609 }
3610
3611 static int bcmgenet_remove(struct platform_device *pdev)
3612 {
3613         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3614
3615         dev_set_drvdata(&pdev->dev, NULL);
3616         unregister_netdev(priv->dev);
3617         bcmgenet_mii_exit(priv->dev);
3618         free_netdev(priv->dev);
3619
3620         return 0;
3621 }
3622
3623 #ifdef CONFIG_PM_SLEEP
3624 static int bcmgenet_suspend(struct device *d)
3625 {
3626         struct net_device *dev = dev_get_drvdata(d);
3627         struct bcmgenet_priv *priv = netdev_priv(dev);
3628         int ret;
3629
3630         if (!netif_running(dev))
3631                 return 0;
3632
3633         bcmgenet_netif_stop(dev);
3634
3635         if (!device_may_wakeup(d))
3636                 phy_suspend(priv->phydev);
3637
3638         netif_device_detach(dev);
3639
3640         /* Disable MAC receive */
3641         umac_enable_set(priv, CMD_RX_EN, false);
3642
3643         ret = bcmgenet_dma_teardown(priv);
3644         if (ret)
3645                 return ret;
3646
3647         /* Disable MAC transmit. TX DMA disabled must be done before this */
3648         umac_enable_set(priv, CMD_TX_EN, false);
3649
3650         /* tx reclaim */
3651         bcmgenet_tx_reclaim_all(dev);
3652         bcmgenet_fini_dma(priv);
3653
3654         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3655         if (device_may_wakeup(d) && priv->wolopts) {
3656                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3657                 clk_prepare_enable(priv->clk_wol);
3658         } else if (priv->internal_phy) {
3659                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3660         }
3661
3662         /* Turn off the clocks */
3663         clk_disable_unprepare(priv->clk);
3664
3665         return ret;
3666 }
3667
3668 static int bcmgenet_resume(struct device *d)
3669 {
3670         struct net_device *dev = dev_get_drvdata(d);
3671         struct bcmgenet_priv *priv = netdev_priv(dev);
3672         unsigned long dma_ctrl;
3673         int ret;
3674
3675         if (!netif_running(dev))
3676                 return 0;
3677
3678         /* Turn on the clock */
3679         ret = clk_prepare_enable(priv->clk);
3680         if (ret)
3681                 return ret;
3682
3683         /* If this is an internal GPHY, power it back on now, before UniMAC is
3684          * brought out of reset as absolutely no UniMAC activity is allowed
3685          */
3686         if (priv->internal_phy)
3687                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3688
3689         bcmgenet_umac_reset(priv);
3690
3691         ret = init_umac(priv);
3692         if (ret)
3693                 goto out_clk_disable;
3694
3695         /* From WOL-enabled suspend, switch to regular clock */
3696         if (priv->wolopts)
3697                 clk_disable_unprepare(priv->clk_wol);
3698
3699         phy_init_hw(priv->phydev);
3700         /* Speed settings must be restored */
3701         genphy_config_aneg(dev->phydev);
3702         bcmgenet_mii_config(priv->dev, false);
3703
3704         /* disable ethernet MAC while updating its registers */
3705         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3706
3707         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3708
3709         if (priv->wolopts)
3710                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3711
3712         /* Disable RX/TX DMA and flush TX queues */
3713         dma_ctrl = bcmgenet_dma_disable(priv);
3714
3715         /* Reinitialize TDMA and RDMA and SW housekeeping */
3716         ret = bcmgenet_init_dma(priv);
3717         if (ret) {
3718                 netdev_err(dev, "failed to initialize DMA\n");
3719                 goto out_clk_disable;
3720         }
3721
3722         /* Always enable ring 16 - descriptor ring */
3723         bcmgenet_enable_dma(priv, dma_ctrl);
3724
3725         netif_device_attach(dev);
3726
3727         if (!device_may_wakeup(d))
3728                 phy_resume(priv->phydev);
3729
3730         if (priv->eee.eee_enabled)
3731                 bcmgenet_eee_enable_set(dev, true);
3732
3733         bcmgenet_netif_start(dev);
3734
3735         return 0;
3736
3737 out_clk_disable:
3738         if (priv->internal_phy)
3739                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3740         clk_disable_unprepare(priv->clk);
3741         return ret;
3742 }
3743 #endif /* CONFIG_PM_SLEEP */
3744
3745 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3746
3747 static struct platform_driver bcmgenet_driver = {
3748         .probe  = bcmgenet_probe,
3749         .remove = bcmgenet_remove,
3750         .driver = {
3751                 .name   = "bcmgenet",
3752                 .of_match_table = bcmgenet_match,
3753                 .pm     = &bcmgenet_pm_ops,
3754         },
3755 };
3756 module_platform_driver(bcmgenet_driver);
3757
3758 MODULE_AUTHOR("Broadcom Corporation");
3759 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3760 MODULE_ALIAS("platform:bcmgenet");
3761 MODULE_LICENSE("GPL");
3762 MODULE_SOFTDEP("pre: mdio-bcm-unimac");