1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
13 /* per-context HW statistics -- chip view */
18 __le64 rx_discard_pkts;
20 __le64 rx_ucast_bytes;
21 __le64 rx_mcast_bytes;
22 __le64 rx_bcast_bytes;
26 __le64 tx_discard_pkts;
28 __le64 tx_ucast_bytes;
29 __le64 tx_mcast_bytes;
30 __le64 tx_bcast_bytes;
37 /* Statistics Ejection Buffer Completion Record (16 bytes) */
40 #define EJECT_CMPL_TYPE_MASK 0x3fUL
41 #define EJECT_CMPL_TYPE_SFT 0
42 #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0)
46 #define EJECT_CMPL_V 0x1UL
50 /* HWRM Completion Record (16 bytes) */
53 #define HWRM_CMPL_TYPE_MASK 0x3fUL
54 #define HWRM_CMPL_TYPE_SFT 0
55 #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0)
59 #define HWRM_CMPL_V 0x1UL
63 /* HWRM Forwarded Request (16 bytes) */
64 struct hwrm_fwd_req_cmpl {
66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL
67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0)
69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
73 __le32 req_buf_addr_v[2];
74 #define HWRM_FWD_REQ_CMPL_V 0x1UL
75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
79 /* HWRM Forwarded Response (16 bytes) */
80 struct hwrm_fwd_resp_cmpl {
82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL
83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0)
88 __le32 resp_buf_addr_v[2];
89 #define HWRM_FWD_RESP_CMPL_V 0x1UL
90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
94 /* HWRM Asynchronous Event Completion Record (16 bytes) */
95 struct hwrm_async_event_cmpl {
97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x20UL << 0)
110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0)
111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0)
115 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL
116 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
117 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
122 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
123 struct hwrm_async_event_cmpl_link_status_change {
125 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
126 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
127 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
129 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
133 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
134 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
137 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_UP 0x1UL
140 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
141 struct hwrm_async_event_cmpl_link_mtu_change {
143 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
144 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
145 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
147 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
150 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
151 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
152 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
155 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
156 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
159 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
160 struct hwrm_async_event_cmpl_link_speed_change {
162 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
163 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
164 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
166 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
169 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
170 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
171 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
174 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
175 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
176 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
179 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
181 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
182 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
183 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
184 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
186 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
187 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
190 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
191 struct hwrm_async_event_cmpl_dcb_config_change {
193 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
194 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
195 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
197 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
200 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
201 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
202 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
205 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
206 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
209 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
210 struct hwrm_async_event_cmpl_port_conn_not_allowed {
212 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
213 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
214 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
216 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
219 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
220 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
221 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
224 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
225 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
228 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
229 struct hwrm_async_event_cmpl_func_drvr_unload {
231 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
232 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
233 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
235 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
238 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
239 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
240 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
243 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
244 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
247 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
248 struct hwrm_async_event_cmpl_func_drvr_load {
250 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
251 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
252 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
254 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
257 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
258 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
259 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
262 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
263 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
266 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
267 struct hwrm_async_event_cmpl_pf_drvr_unload {
269 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
270 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
271 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
273 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
276 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
277 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
278 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
281 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
282 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
285 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
286 struct hwrm_async_event_cmpl_pf_drvr_load {
288 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
289 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
290 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
292 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x20UL << 0)
295 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
296 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
297 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
300 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
301 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
304 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
305 struct hwrm_async_event_cmpl_vf_flr {
307 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
308 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
309 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
311 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0)
314 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
315 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
316 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
319 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
320 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
323 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
324 struct hwrm_async_event_cmpl_vf_mac_addr_change {
326 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
327 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
328 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
330 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
333 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
334 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
335 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
338 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
339 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
342 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
343 struct hwrm_async_event_cmpl_hwrm_error {
345 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
346 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
347 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
349 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0)
351 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
352 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
353 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0)
354 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0)
355 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0)
357 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
358 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
359 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
362 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
365 /* HW Resource Manager Specification 0.7.8 */
366 #define HWRM_VERSION_MAJOR 0
367 #define HWRM_VERSION_MINOR 7
368 #define HWRM_VERSION_UPDATE 8
370 #define HWRM_VERSION_STR "0.7.8"
371 /* Following is the signature for HWRM message field that indicates not
372 * applicable (All F's). Need to cast it the size of the field if needed.
374 #define HWRM_NA_SIGNATURE ((__le32)(-1))
375 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
376 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
377 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
378 #define HW_HASH_KEY_SIZE 40
379 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
380 /* Input (16 bytes) */
389 /* Output (8 bytes) */
397 /* Command numbering (8 bytes) */
400 #define HWRM_VER_GET (0x0UL)
401 #define HWRM_FUNC_DISABLE (0x10UL)
402 #define HWRM_FUNC_RESET (0x11UL)
403 #define HWRM_FUNC_GETFID (0x12UL)
404 #define HWRM_FUNC_VF_ALLOC (0x13UL)
405 #define HWRM_FUNC_VF_FREE (0x14UL)
406 #define HWRM_FUNC_QCAPS (0x15UL)
407 #define HWRM_FUNC_QCFG (0x16UL)
408 #define HWRM_FUNC_CFG (0x17UL)
409 #define HWRM_FUNC_QSTATS (0x18UL)
410 #define HWRM_FUNC_CLR_STATS (0x19UL)
411 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL)
412 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL)
413 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL)
414 #define HWRM_FUNC_DRV_RGTR (0x1dUL)
415 #define HWRM_FUNC_DRV_QVER (0x1eUL)
416 #define HWRM_FUNC_BUF_RGTR (0x1fUL)
417 #define HWRM_FUNC_VF_CFG (0x20UL)
418 #define HWRM_PORT_PHY_CFG (0x20UL)
419 #define HWRM_PORT_MAC_CFG (0x21UL)
420 #define HWRM_PORT_ENABLE (0x22UL)
421 #define HWRM_PORT_QSTATS (0x23UL)
422 #define HWRM_PORT_LPBK_QSTATS (0x24UL)
423 #define HWRM_PORT_CLR_STATS (0x25UL)
424 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL)
425 #define HWRM_PORT_PHY_QCFG (0x27UL)
426 #define HWRM_PORT_MAC_QCFG (0x28UL)
427 #define HWRM_PORT_BLINK_LED (0x29UL)
428 #define HWRM_QUEUE_QPORTCFG (0x30UL)
429 #define HWRM_QUEUE_QCFG (0x31UL)
430 #define HWRM_QUEUE_CFG (0x32UL)
431 #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL)
432 #define HWRM_QUEUE_BUFFERS_CFG (0x34UL)
433 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL)
434 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL)
435 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL)
436 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL)
437 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL)
438 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL)
439 #define HWRM_VNIC_ALLOC (0x40UL)
440 #define HWRM_VNIC_FREE (0x41UL)
441 #define HWRM_VNIC_CFG (0x42UL)
442 #define HWRM_VNIC_QCFG (0x43UL)
443 #define HWRM_VNIC_TPA_CFG (0x44UL)
444 #define HWRM_VNIC_TPA_QCFG (0x45UL)
445 #define HWRM_VNIC_RSS_CFG (0x46UL)
446 #define HWRM_VNIC_RSS_QCFG (0x47UL)
447 #define HWRM_VNIC_PLCMODES_CFG (0x48UL)
448 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL)
449 #define HWRM_RING_ALLOC (0x50UL)
450 #define HWRM_RING_FREE (0x51UL)
451 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL)
452 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL)
453 #define HWRM_RING_RESET (0x5eUL)
454 #define HWRM_RING_GRP_ALLOC (0x60UL)
455 #define HWRM_RING_GRP_FREE (0x61UL)
456 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL)
457 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL)
458 #define HWRM_ARB_GRP_ALLOC (0x80UL)
459 #define HWRM_ARB_GRP_CFG (0x81UL)
460 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL)
461 #define HWRM_CFA_L2_FILTER_FREE (0x91UL)
462 #define HWRM_CFA_L2_FILTER_CFG (0x92UL)
463 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL)
464 #define HWRM_CFA_L2_SET_BCASTMCAST_MIRRORING (0x94UL)
465 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL)
466 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL)
467 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL)
468 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL)
469 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL)
470 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL)
471 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL)
472 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL)
473 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL)
474 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL)
475 #define HWRM_STAT_CTX_ALLOC (0xb0UL)
476 #define HWRM_STAT_CTX_FREE (0xb1UL)
477 #define HWRM_STAT_CTX_QUERY (0xb2UL)
478 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL)
479 #define HWRM_FW_RESET (0xc0UL)
480 #define HWRM_FW_QSTATUS (0xc1UL)
481 #define HWRM_EXEC_FWD_RESP (0xd0UL)
482 #define HWRM_REJECT_FWD_RESP (0xd1UL)
483 #define HWRM_FWD_RESP (0xd2UL)
484 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL)
485 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL)
486 #define HWRM_MGMT_L2_FILTER_ALLOC (0x100UL)
487 #define HWRM_MGMT_L2_FILTER_FREE (0x101UL)
488 #define HWRM_DBG_READ_DIRECT (0xff10UL)
489 #define HWRM_DBG_READ_INDIRECT (0xff11UL)
490 #define HWRM_DBG_WRITE_DIRECT (0xff12UL)
491 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL)
492 #define HWRM_DBG_DUMP (0xff14UL)
493 #define HWRM_NVM_MODIFY (0xfff4UL)
494 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL)
495 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL)
496 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL)
497 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL)
498 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL)
499 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL)
500 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL)
501 #define HWRM_NVM_RAW_DUMP (0xfffcUL)
502 #define HWRM_NVM_READ (0xfffdUL)
503 #define HWRM_NVM_WRITE (0xfffeUL)
504 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL)
508 /* Return Codes (8 bytes) */
511 #define HWRM_ERR_CODE_SUCCESS (0x0UL)
512 #define HWRM_ERR_CODE_FAIL (0x1UL)
513 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL)
514 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL)
515 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL)
516 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL)
517 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL)
518 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL)
519 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL)
520 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL)
524 /* Output (16 bytes) */
525 struct hwrm_err_output {
536 /* Port Tx Statistics Formats (408 bytes) */
537 struct tx_port_stats {
538 __le64 tx_64b_frames;
539 __le64 tx_65b_127b_frames;
540 __le64 tx_128b_255b_frames;
541 __le64 tx_256b_511b_frames;
542 __le64 tx_512b_1023b_frames;
543 __le64 tx_1024b_1518_frames;
544 __le64 tx_good_vlan_frames;
545 __le64 tx_1519b_2047_frames;
546 __le64 tx_2048b_4095b_frames;
547 __le64 tx_4096b_9216b_frames;
548 __le64 tx_9217b_16383b_frames;
549 __le64 tx_good_frames;
550 __le64 tx_total_frames;
551 __le64 tx_ucast_frames;
552 __le64 tx_mcast_frames;
553 __le64 tx_bcast_frames;
554 __le64 tx_pause_frames;
555 __le64 tx_pfc_frames;
556 __le64 tx_jabber_frames;
557 __le64 tx_fcs_err_frames;
558 __le64 tx_control_frames;
559 __le64 tx_oversz_frames;
560 __le64 tx_single_dfrl_frames;
561 __le64 tx_multi_dfrl_frames;
562 __le64 tx_single_coll_frames;
563 __le64 tx_multi_coll_frames;
564 __le64 tx_late_coll_frames;
565 __le64 tx_excessive_coll_frames;
566 __le64 tx_frag_frames;
568 __le64 tx_tagged_frames;
569 __le64 tx_dbl_tagged_frames;
570 __le64 tx_runt_frames;
571 __le64 tx_fifo_underruns;
572 __le64 tx_pfc_ena_frames_pri0;
573 __le64 tx_pfc_ena_frames_pri1;
574 __le64 tx_pfc_ena_frames_pri2;
575 __le64 tx_pfc_ena_frames_pri3;
576 __le64 tx_pfc_ena_frames_pri4;
577 __le64 tx_pfc_ena_frames_pri5;
578 __le64 tx_pfc_ena_frames_pri6;
579 __le64 tx_pfc_ena_frames_pri7;
580 __le64 tx_eee_lpi_events;
581 __le64 tx_eee_lpi_duration;
582 __le64 tx_llfc_logical_msgs;
584 __le64 tx_total_collisions;
586 __le64 tx_xthol_frames;
587 __le64 tx_stat_discard;
588 __le64 tx_stat_error;
591 /* Port Rx Statistics Formats (528 bytes) */
592 struct rx_port_stats {
593 __le64 rx_64b_frames;
594 __le64 rx_65b_127b_frames;
595 __le64 rx_128b_255b_frames;
596 __le64 rx_256b_511b_frames;
597 __le64 rx_512b_1023b_frames;
598 __le64 rx_1024b_1518_frames;
599 __le64 rx_good_vlan_frames;
600 __le64 rx_1519b_2047b_frames;
601 __le64 rx_2048b_4095b_frames;
602 __le64 rx_4096b_9216b_frames;
603 __le64 rx_9217b_16383b_frames;
604 __le64 rx_total_frames;
605 __le64 rx_ucast_frames;
606 __le64 rx_mcast_frames;
607 __le64 rx_bcast_frames;
608 __le64 rx_fcs_err_frames;
609 __le64 rx_ctrl_frames;
610 __le64 rx_pause_frames;
611 __le64 rx_pfc_frames;
612 __le64 rx_unsupported_opcode_frames;
613 __le64 rx_unsupported_da_pausepfc_frames;
614 __le64 rx_wrong_sa_frames;
615 __le64 rx_align_err_frames;
616 __le64 rx_oor_len_frames;
617 __le64 rx_code_err_frames;
618 __le64 rx_false_carrier_frames;
619 __le64 rx_ovrsz_frames;
620 __le64 rx_jbr_frames;
621 __le64 rx_mtu_err_frames;
622 __le64 rx_match_crc_frames;
623 __le64 rx_promiscuous_frames;
624 __le64 rx_tagged_frames;
625 __le64 rx_double_tagged_frames;
626 __le64 rx_trunc_frames;
627 __le64 rx_good_frames;
628 __le64 rx_pfc_xon2xoff_frames_pri0;
629 __le64 rx_pfc_xon2xoff_frames_pri1;
630 __le64 rx_pfc_xon2xoff_frames_pri2;
631 __le64 rx_pfc_xon2xoff_frames_pri3;
632 __le64 rx_pfc_xon2xoff_frames_pri4;
633 __le64 rx_pfc_xon2xoff_frames_pri5;
634 __le64 rx_pfc_xon2xoff_frames_pri6;
635 __le64 rx_pfc_xon2xoff_frames_pri7;
636 __le64 rx_pfc_ena_frames_pri0;
637 __le64 rx_pfc_ena_frames_pri1;
638 __le64 rx_pfc_ena_frames_pri2;
639 __le64 rx_pfc_ena_frames_pri3;
640 __le64 rx_pfc_ena_frames_pri4;
641 __le64 rx_pfc_ena_frames_pri5;
642 __le64 rx_pfc_ena_frames_pri6;
643 __le64 rx_pfc_ena_frames_pri7;
644 __le64 rx_sch_crc_err_frames;
645 __le64 rx_undrsz_frames;
646 __le64 rx_frag_frames;
647 __le64 rx_eee_lpi_events;
648 __le64 rx_eee_lpi_duration;
649 __le64 rx_llfc_physical_msgs;
650 __le64 rx_llfc_logical_msgs;
651 __le64 rx_llfc_msgs_with_crc_err;
653 __le64 rx_hcfc_msgs_with_crc_err;
655 __le64 rx_runt_bytes;
656 __le64 rx_runt_frames;
657 __le64 rx_stat_discard;
662 /* Input (24 bytes) */
663 struct hwrm_ver_get_input {
675 /* Output (128 bytes) */
676 struct hwrm_ver_get_output {
705 char hwrm_fw_name[16];
706 char ape_fw_name[16];
707 char kong_fw_name[16];
708 char tang_fw_name[16];
709 char bono_fw_name[16];
715 __le16 max_req_win_len;
717 __le16 def_req_timeout;
724 /* hwrm_func_disable */
725 /* Input (24 bytes) */
726 struct hwrm_func_disable_input {
733 #define FUNC_DISABLE_REQ_ENABLES_VF_ID_VALID 0x1UL
738 /* Output (16 bytes) */
739 struct hwrm_func_disable_output {
751 /* hwrm_func_reset */
752 /* Input (24 bytes) */
753 struct hwrm_func_reset_input {
760 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
765 /* Output (16 bytes) */
766 struct hwrm_func_reset_output {
778 /* hwrm_func_getfid */
779 /* Input (24 bytes) */
780 struct hwrm_func_getfid_input {
787 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
792 /* Output (16 bytes) */
793 struct hwrm_func_getfid_output {
807 /* hwrm_func_vf_alloc */
808 /* Input (24 bytes) */
809 struct hwrm_func_vf_alloc_input {
816 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
821 /* Output (16 bytes) */
822 struct hwrm_func_vf_alloc_output {
836 /* hwrm_func_vf_free */
837 /* Input (24 bytes) */
838 struct hwrm_func_vf_free_input {
845 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
850 /* Output (16 bytes) */
851 struct hwrm_func_vf_free_output {
863 /* hwrm_func_vf_cfg */
864 /* Input (24 bytes) */
865 struct hwrm_func_vf_cfg_input {
872 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
873 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
878 /* Output (16 bytes) */
879 struct hwrm_func_vf_cfg_output {
891 /* hwrm_func_qcaps */
892 /* Input (24 bytes) */
893 struct hwrm_func_qcaps_input {
903 /* Output (80 bytes) */
904 struct hwrm_func_qcaps_output {
912 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
913 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
914 u8 perm_mac_address[6];
915 __le16 max_rsscos_ctx;
916 __le16 max_cmpl_rings;
924 __le32 max_encap_records;
925 __le32 max_decap_records;
926 __le32 max_tx_em_flows;
927 __le32 max_tx_wm_flows;
928 __le32 max_rx_em_flows;
929 __le32 max_rx_wm_flows;
930 __le32 max_mcast_filters;
932 __le32 max_hw_ring_grps;
940 /* Input (88 bytes) */
941 struct hwrm_func_cfg_input {
951 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL
952 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL
953 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL
954 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL
955 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL
956 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL
957 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL
958 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL
959 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL
961 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
962 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
963 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
964 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
965 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
966 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
967 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
968 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
969 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
970 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
971 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
972 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
973 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
974 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
975 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
976 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
977 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
978 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
979 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
980 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
983 __le16 num_rsscos_ctxs;
984 __le16 num_cmpl_rings;
989 __le16 num_stat_ctxs;
990 __le16 num_hw_ring_grps;
993 __be32 dflt_ip_addr[4];
996 __le16 async_event_cr;
997 u8 vlan_antispoof_mode;
998 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0)
999 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0)
1000 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0)
1001 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0)
1002 u8 allowed_vlan_pris;
1003 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_NOCHECK (0x0UL << 0)
1004 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_VALIDATE_VLAN (0x1UL << 0)
1005 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_INSERT_IF_VLANDNE (0x2UL << 0)
1006 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0)
1008 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0)
1009 #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0)
1010 #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0)
1012 __le16 num_mcast_filters;
1015 /* Output (16 bytes) */
1016 struct hwrm_func_cfg_output {
1028 /* hwrm_func_qstats */
1029 /* Input (24 bytes) */
1030 struct hwrm_func_qstats_input {
1040 /* Output (176 bytes) */
1041 struct hwrm_func_qstats_output {
1046 __le64 tx_ucast_pkts;
1047 __le64 tx_mcast_pkts;
1048 __le64 tx_bcast_pkts;
1050 __le64 tx_drop_pkts;
1051 __le64 tx_ucast_bytes;
1052 __le64 tx_mcast_bytes;
1053 __le64 tx_bcast_bytes;
1054 __le64 rx_ucast_pkts;
1055 __le64 rx_mcast_pkts;
1056 __le64 rx_bcast_pkts;
1058 __le64 rx_drop_pkts;
1059 __le64 rx_ucast_bytes;
1060 __le64 rx_mcast_bytes;
1061 __le64 rx_bcast_bytes;
1063 __le64 rx_agg_bytes;
1064 __le64 rx_agg_events;
1065 __le64 rx_agg_aborts;
1073 /* hwrm_func_clr_stats */
1074 /* Input (24 bytes) */
1075 struct hwrm_func_clr_stats_input {
1085 /* Output (16 bytes) */
1086 struct hwrm_func_clr_stats_output {
1098 /* hwrm_func_vf_resc_free */
1099 /* Input (24 bytes) */
1100 struct hwrm_func_vf_resc_free_input {
1110 /* Output (16 bytes) */
1111 struct hwrm_func_vf_resc_free_output {
1123 /* hwrm_func_vf_vnic_ids_query */
1124 /* Input (32 bytes) */
1125 struct hwrm_func_vf_vnic_ids_query_input {
1134 __le32 max_vnic_id_cnt;
1135 __le64 vnic_id_tbl_addr;
1138 /* Output (16 bytes) */
1139 struct hwrm_func_vf_vnic_ids_query_output {
1151 /* hwrm_func_drv_rgtr */
1152 /* Input (80 bytes) */
1153 struct hwrm_func_drv_rgtr_input {
1160 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1161 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1163 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1164 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1165 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1166 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1167 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1176 __le32 vf_req_fwd[8];
1177 __le32 async_event_fwd[8];
1180 /* Output (16 bytes) */
1181 struct hwrm_func_drv_rgtr_output {
1193 /* hwrm_func_drv_unrgtr */
1194 /* Input (24 bytes) */
1195 struct hwrm_func_drv_unrgtr_input {
1202 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1206 /* Output (16 bytes) */
1207 struct hwrm_func_drv_unrgtr_output {
1219 /* hwrm_func_buf_rgtr */
1220 /* Input (128 bytes) */
1221 struct hwrm_func_buf_rgtr_input {
1228 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1229 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1231 __le16 req_buf_num_pages;
1232 __le16 req_buf_page_size;
1233 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0)
1234 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0)
1235 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0)
1236 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0)
1237 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x16UL << 0)
1238 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x17UL << 0)
1239 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0)
1241 __le16 resp_buf_len;
1244 __le64 req_buf_page_addr0;
1245 __le64 req_buf_page_addr1;
1246 __le64 req_buf_page_addr2;
1247 __le64 req_buf_page_addr3;
1248 __le64 req_buf_page_addr4;
1249 __le64 req_buf_page_addr5;
1250 __le64 req_buf_page_addr6;
1251 __le64 req_buf_page_addr7;
1252 __le64 req_buf_page_addr8;
1253 __le64 req_buf_page_addr9;
1254 __le64 error_buf_addr;
1255 __le64 resp_buf_addr;
1258 /* Output (16 bytes) */
1259 struct hwrm_func_buf_rgtr_output {
1271 /* hwrm_func_drv_qver */
1272 /* Input (24 bytes) */
1273 struct hwrm_func_drv_qver_input {
1280 #define FUNC_DRV_QVER_REQ_ENABLES_OS_TYPE_VALID 0x1UL
1281 #define FUNC_DRV_QVER_REQ_ENABLES_VER_VALID 0x2UL
1286 /* Output (16 bytes) */
1287 struct hwrm_func_drv_qver_output {
1301 /* hwrm_port_phy_cfg */
1302 /* Input (48 bytes) */
1303 struct hwrm_port_phy_cfg_input {
1310 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1311 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL
1312 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1313 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1315 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1316 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1317 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1318 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1319 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1320 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1321 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1322 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1323 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1325 __le16 force_link_speed;
1326 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1327 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1328 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1329 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1330 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1331 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1332 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1333 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1334 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1336 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0)
1337 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1338 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1339 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1340 #define PORT_PHY_CFG_REQ_AUTO_MODE_MASK (0x4UL << 0)
1342 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0)
1343 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0)
1344 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0)
1346 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
1347 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
1349 __le16 auto_link_speed;
1350 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1351 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1352 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1353 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1354 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1355 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1356 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1359 __le16 auto_link_speed_mask;
1360 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1361 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1362 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1363 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1364 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1365 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1366 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1367 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1368 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1372 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0)
1373 #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0)
1375 #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0)
1376 #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1377 #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1379 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1380 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
1386 /* Output (16 bytes) */
1387 struct hwrm_port_phy_cfg_output {
1399 /* hwrm_port_phy_qcfg */
1400 /* Input (24 bytes) */
1401 struct hwrm_port_phy_qcfg_input {
1411 /* Output (48 bytes) */
1412 struct hwrm_port_phy_qcfg_output {
1418 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0)
1419 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0)
1420 #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0)
1423 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0)
1424 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0)
1425 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0)
1426 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0)
1427 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0)
1428 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0)
1429 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0)
1430 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0)
1431 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0)
1433 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0)
1434 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0)
1436 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
1437 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
1438 __le16 support_speeds;
1439 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
1440 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
1441 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
1442 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
1443 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
1444 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
1445 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
1446 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
1447 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
1448 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
1449 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
1450 __le16 force_link_speed;
1451 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1452 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1453 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1454 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1455 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1456 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1457 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1458 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1459 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1461 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0)
1462 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1463 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1464 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1465 #define PORT_PHY_QCFG_RESP_AUTO_MODE_MASK (0x4UL << 0)
1467 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
1468 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
1469 __le16 auto_link_speed;
1470 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1471 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1472 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1473 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1474 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1475 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1476 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1477 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1478 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1479 __le16 auto_link_speed_mask;
1480 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1481 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1482 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1483 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1484 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1485 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1486 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1487 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1488 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1489 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1490 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1492 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0)
1493 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0)
1495 #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0)
1496 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0)
1497 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0)
1499 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
1500 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
1502 #define PORT_PHY_QCFG_RESP_DUPLEX_SETTING_HALF (0x0UL << 0)
1503 #define PORT_PHY_QCFG_RESP_DUPLEX_SETTING_FULL (0x1UL << 0)
1509 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR4 (0x1UL << 0)
1510 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0)
1511 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR4 (0x3UL << 0)
1512 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR4 (0x4UL << 0)
1513 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0)
1514 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX4 (0x6UL << 0)
1515 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0)
1516 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0)
1518 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0)
1519 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0)
1520 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0)
1521 u8 transceiver_type;
1522 #define PORT_PHY_QCFG_RESP_TRANSCEIVER_TYPE_XCVR_INTERNAL (0x1UL << 0)
1523 #define PORT_PHY_QCFG_RESP_TRANSCEIVER_TYPE_XCVR_EXTERNAL (0x2UL << 0)
1525 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
1526 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
1528 __le16 link_partner_adv_speeds;
1529 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
1530 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
1531 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
1532 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
1533 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
1534 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
1535 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
1536 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
1537 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
1538 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
1539 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
1540 u8 link_partner_adv_auto_mode;
1541 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0)
1542 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1543 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1544 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1545 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_MASK (0x4UL << 0)
1546 u8 link_partner_adv_pause;
1547 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
1548 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
1555 /* hwrm_port_mac_cfg */
1556 /* Input (32 bytes) */
1557 struct hwrm_port_mac_cfg_input {
1564 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
1565 #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL
1566 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
1567 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
1569 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
1570 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
1571 #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL
1572 #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL
1573 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
1574 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
1578 #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0)
1579 #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1580 #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1581 u8 ivlan_pri2cos_map_pri;
1583 u8 tunnel_pri2cos_map_pri;
1584 u8 dscp2pri_map_pri;
1587 /* Output (16 bytes) */
1588 struct hwrm_port_mac_cfg_output {
1597 #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0)
1598 #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0)
1599 #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0)
1604 /* hwrm_port_enable */
1605 /* Input (24 bytes) */
1606 struct hwrm_port_enable_input {
1613 #define PORT_ENABLE_REQ_FLAGS_FORWARD_TRAFFIC 0x1UL
1618 /* Output (16 bytes) */
1619 struct hwrm_port_enable_output {
1631 /* hwrm_port_qstats */
1632 /* Input (40 bytes) */
1633 struct hwrm_port_qstats_input {
1644 __le64 tx_stat_host_addr;
1645 __le64 rx_stat_host_addr;
1648 /* Output (16 bytes) */
1649 struct hwrm_port_qstats_output {
1661 /* hwrm_port_lpbk_qstats */
1662 /* Input (16 bytes) */
1663 struct hwrm_port_lpbk_qstats_input {
1671 /* Output (64 bytes) */
1672 struct hwrm_port_lpbk_qstats_output {
1677 __le64 lpbk_ucast_frames;
1678 __le64 lpbk_mcast_frames;
1679 __le64 lpbk_bcast_frames;
1680 __le64 lpbk_ucast_bytes;
1681 __le64 lpbk_mcast_bytes;
1682 __le64 lpbk_bcast_bytes;
1690 /* hwrm_port_clr_stats */
1691 /* Input (24 bytes) */
1692 struct hwrm_port_clr_stats_input {
1702 /* Output (16 bytes) */
1703 struct hwrm_port_clr_stats_output {
1715 /* hwrm_port_lpbk_clr_stats */
1716 /* Input (16 bytes) */
1717 struct hwrm_port_lpbk_clr_stats_input {
1725 /* Output (16 bytes) */
1726 struct hwrm_port_lpbk_clr_stats_output {
1738 /* hwrm_port_blink_led */
1739 /* Input (24 bytes) */
1740 struct hwrm_port_blink_led_input {
1750 /* Output (16 bytes) */
1751 struct hwrm_port_blink_led_output {
1763 /* hwrm_queue_qportcfg */
1764 /* Input (24 bytes) */
1765 struct hwrm_queue_qportcfg_input {
1772 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
1773 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1774 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1779 /* Output (32 bytes) */
1780 struct hwrm_queue_qportcfg_output {
1785 u8 max_configurable_queues;
1786 u8 max_configurable_lossless_queues;
1787 u8 queue_cfg_allowed;
1788 u8 queue_buffers_cfg_allowed;
1789 u8 queue_pfcenable_cfg_allowed;
1790 u8 queue_pri2cos_cfg_allowed;
1791 u8 queue_cos2bw_cfg_allowed;
1793 u8 queue_id0_service_profile;
1794 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1795 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1796 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1798 u8 queue_id1_service_profile;
1799 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1800 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1801 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1803 u8 queue_id2_service_profile;
1804 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1805 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1806 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1808 u8 queue_id3_service_profile;
1809 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1810 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1811 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1813 u8 queue_id4_service_profile;
1814 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1815 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1816 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1818 u8 queue_id5_service_profile;
1819 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1820 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1821 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1823 u8 queue_id6_service_profile;
1824 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1825 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1826 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1828 u8 queue_id7_service_profile;
1829 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1830 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1831 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1835 /* hwrm_queue_cfg */
1836 /* Input (40 bytes) */
1837 struct hwrm_queue_cfg_input {
1844 #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL
1845 #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1846 #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1848 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
1849 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
1853 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1854 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1855 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1859 /* Output (16 bytes) */
1860 struct hwrm_queue_cfg_output {
1872 /* hwrm_queue_buffers_cfg */
1873 /* Input (56 bytes) */
1874 struct hwrm_queue_buffers_cfg_input {
1881 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL
1882 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1883 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1885 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL
1886 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL
1887 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_GROUP 0x4UL
1888 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x8UL
1889 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x10UL
1890 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x20UL
1891 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x40UL
1892 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x80UL
1903 /* Output (16 bytes) */
1904 struct hwrm_queue_buffers_cfg_output {
1916 /* hwrm_queue_pfcenable_cfg */
1917 /* Input (24 bytes) */
1918 struct hwrm_queue_pfcenable_cfg_input {
1925 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI0_PFC_ENABLED 0x1UL
1926 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI1_PFC_ENABLED 0x2UL
1927 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI2_PFC_ENABLED 0x4UL
1928 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI3_PFC_ENABLED 0x8UL
1929 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI4_PFC_ENABLED 0x10UL
1930 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI5_PFC_ENABLED 0x20UL
1931 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI6_PFC_ENABLED 0x40UL
1932 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI7_PFC_ENABLED 0x80UL
1937 /* Output (16 bytes) */
1938 struct hwrm_queue_pfcenable_cfg_output {
1950 /* hwrm_queue_pri2cos_cfg */
1951 /* Input (40 bytes) */
1952 struct hwrm_queue_pri2cos_cfg_input {
1959 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL
1960 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1961 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1962 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL
1976 /* Output (16 bytes) */
1977 struct hwrm_queue_pri2cos_cfg_output {
1989 /* hwrm_queue_cos2bw_cfg */
1990 /* Input (128 bytes) */
1991 struct hwrm_queue_cos2bw_cfg_input {
1999 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
2000 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
2001 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
2002 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
2003 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
2004 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
2005 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
2006 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
2010 __le32 queue_id0_min_bw;
2011 __le32 queue_id0_max_bw;
2012 u8 queue_id0_tsa_assign;
2013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0)
2014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0)
2015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2017 u8 queue_id0_pri_lvl;
2018 u8 queue_id0_bw_weight;
2020 __le32 queue_id1_min_bw;
2021 __le32 queue_id1_max_bw;
2022 u8 queue_id1_tsa_assign;
2023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0)
2024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0)
2025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2027 u8 queue_id1_pri_lvl;
2028 u8 queue_id1_bw_weight;
2030 __le32 queue_id2_min_bw;
2031 __le32 queue_id2_max_bw;
2032 u8 queue_id2_tsa_assign;
2033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0)
2034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0)
2035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2037 u8 queue_id2_pri_lvl;
2038 u8 queue_id2_bw_weight;
2040 __le32 queue_id3_min_bw;
2041 __le32 queue_id3_max_bw;
2042 u8 queue_id3_tsa_assign;
2043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0)
2044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0)
2045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2047 u8 queue_id3_pri_lvl;
2048 u8 queue_id3_bw_weight;
2050 __le32 queue_id4_min_bw;
2051 __le32 queue_id4_max_bw;
2052 u8 queue_id4_tsa_assign;
2053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0)
2054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0)
2055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2057 u8 queue_id4_pri_lvl;
2058 u8 queue_id4_bw_weight;
2060 __le32 queue_id5_min_bw;
2061 __le32 queue_id5_max_bw;
2062 u8 queue_id5_tsa_assign;
2063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0)
2064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0)
2065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2067 u8 queue_id5_pri_lvl;
2068 u8 queue_id5_bw_weight;
2070 __le32 queue_id6_min_bw;
2071 __le32 queue_id6_max_bw;
2072 u8 queue_id6_tsa_assign;
2073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0)
2074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0)
2075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2077 u8 queue_id6_pri_lvl;
2078 u8 queue_id6_bw_weight;
2080 __le32 queue_id7_min_bw;
2081 __le32 queue_id7_max_bw;
2082 u8 queue_id7_tsa_assign;
2083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0)
2084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0)
2085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2087 u8 queue_id7_pri_lvl;
2088 u8 queue_id7_bw_weight;
2092 /* Output (16 bytes) */
2093 struct hwrm_queue_cos2bw_cfg_output {
2105 /* hwrm_vnic_alloc */
2106 /* Input (24 bytes) */
2107 struct hwrm_vnic_alloc_input {
2114 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
2118 /* Output (16 bytes) */
2119 struct hwrm_vnic_alloc_output {
2131 /* hwrm_vnic_free */
2132 /* Input (24 bytes) */
2133 struct hwrm_vnic_free_input {
2143 /* Output (16 bytes) */
2144 struct hwrm_vnic_free_output {
2157 /* Input (40 bytes) */
2158 struct hwrm_vnic_cfg_input {
2165 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
2166 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
2168 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
2169 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
2170 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
2171 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
2172 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
2174 __le16 dflt_ring_grp;
2182 /* Output (16 bytes) */
2183 struct hwrm_vnic_cfg_output {
2195 /* hwrm_vnic_tpa_cfg */
2196 /* Input (40 bytes) */
2197 struct hwrm_vnic_tpa_cfg_input {
2204 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
2205 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
2206 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
2207 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
2208 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
2209 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
2210 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
2211 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
2213 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
2214 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
2215 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
2216 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
2218 __le16 max_agg_segs;
2219 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0)
2220 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0)
2221 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0)
2222 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0)
2223 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0)
2225 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0)
2226 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0)
2227 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0)
2228 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0)
2229 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0)
2230 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0)
2233 __le32 max_agg_timer;
2237 /* Output (16 bytes) */
2238 struct hwrm_vnic_tpa_cfg_output {
2250 /* hwrm_vnic_rss_cfg */
2251 /* Input (48 bytes) */
2252 struct hwrm_vnic_rss_cfg_input {
2259 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
2260 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
2261 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
2262 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
2263 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
2264 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
2266 __le64 ring_grp_tbl_addr;
2267 __le64 hash_key_tbl_addr;
2272 /* Output (16 bytes) */
2273 struct hwrm_vnic_rss_cfg_output {
2285 /* hwrm_vnic_plcmodes_cfg */
2286 /* Input (40 bytes) */
2287 struct hwrm_vnic_plcmodes_cfg_input {
2294 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
2295 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
2296 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
2297 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
2298 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
2299 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
2301 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
2302 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
2303 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
2305 __le16 jumbo_thresh;
2307 __le16 hds_threshold;
2311 /* Output (16 bytes) */
2312 struct hwrm_vnic_plcmodes_cfg_output {
2324 /* hwrm_vnic_rss_cos_lb_ctx_alloc */
2325 /* Input (16 bytes) */
2326 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
2334 /* Output (16 bytes) */
2335 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
2340 __le16 rss_cos_lb_ctx_id;
2349 /* hwrm_vnic_rss_cos_lb_ctx_free */
2350 /* Input (24 bytes) */
2351 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
2357 __le16 rss_cos_lb_ctx_id;
2361 /* Output (16 bytes) */
2362 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
2374 /* hwrm_ring_alloc */
2375 /* Input (80 bytes) */
2376 struct hwrm_ring_alloc_input {
2383 #define RING_ALLOC_REQ_ENABLES_ARB_GRP_ID_VALID 0x1UL
2384 #define RING_ALLOC_REQ_ENABLES_INPUT_NUM_VALID 0x2UL
2385 #define RING_ALLOC_REQ_ENABLES_WEIGHT_VALID 0x4UL
2386 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
2387 #define RING_ALLOC_REQ_ENABLES_MIN_BW_VALID 0x10UL
2388 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
2390 #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0)
2391 #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0)
2392 #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0)
2393 #define RING_ALLOC_REQ_RING_TYPE_STATUS (0x3UL << 0)
2394 #define RING_ALLOC_REQ_RING_TYPE_CMD (0x4UL << 0)
2397 __le64 page_tbl_addr;
2405 __le16 cmpl_ring_id;
2410 __le16 input_number;
2418 #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0)
2419 #define RING_ALLOC_REQ_INT_MODE_MSI (0x1UL << 0)
2420 #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0)
2421 #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0)
2425 /* Output (16 bytes) */
2426 struct hwrm_ring_alloc_output {
2432 __le16 logical_ring_id;
2439 /* hwrm_ring_free */
2440 /* Input (24 bytes) */
2441 struct hwrm_ring_free_input {
2448 #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0)
2449 #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0)
2450 #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0)
2451 #define RING_FREE_REQ_RING_TYPE_STATUS (0x3UL << 0)
2452 #define RING_FREE_REQ_RING_TYPE_CMD (0x4UL << 0)
2458 /* Output (16 bytes) */
2459 struct hwrm_ring_free_output {
2471 /* hwrm_ring_cmpl_ring_qaggint_params */
2472 /* Input (24 bytes) */
2473 struct hwrm_ring_cmpl_ring_qaggint_params_input {
2483 /* Output (32 bytes) */
2484 struct hwrm_ring_cmpl_ring_qaggint_params_output {
2490 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
2491 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
2492 __le16 num_cmpl_dma_aggr;
2493 __le16 num_cmpl_dma_aggr_during_int;
2494 __le16 cmpl_aggr_dma_tmr;
2495 __le16 cmpl_aggr_dma_tmr_during_int;
2496 __le16 int_lat_tmr_min;
2497 __le16 int_lat_tmr_max;
2498 __le16 num_cmpl_aggr_int;
2506 /* hwrm_ring_cmpl_ring_cfg_aggint_params */
2507 /* Input (40 bytes) */
2508 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
2516 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
2517 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
2518 __le16 num_cmpl_dma_aggr;
2519 __le16 num_cmpl_dma_aggr_during_int;
2520 __le16 cmpl_aggr_dma_tmr;
2521 __le16 cmpl_aggr_dma_tmr_during_int;
2522 __le16 int_lat_tmr_min;
2523 __le16 int_lat_tmr_max;
2524 __le16 num_cmpl_aggr_int;
2528 /* Output (16 bytes) */
2529 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
2541 /* hwrm_ring_reset */
2542 /* Input (24 bytes) */
2543 struct hwrm_ring_reset_input {
2550 #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0)
2551 #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0)
2552 #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0)
2553 #define RING_RESET_REQ_RING_TYPE_STATUS (0x3UL << 0)
2554 #define RING_RESET_REQ_RING_TYPE_CMD (0x4UL << 0)
2560 /* Output (16 bytes) */
2561 struct hwrm_ring_reset_output {
2573 /* hwrm_ring_grp_alloc */
2574 /* Input (24 bytes) */
2575 struct hwrm_ring_grp_alloc_input {
2587 /* Output (16 bytes) */
2588 struct hwrm_ring_grp_alloc_output {
2593 __le32 ring_group_id;
2600 /* hwrm_ring_grp_free */
2601 /* Input (24 bytes) */
2602 struct hwrm_ring_grp_free_input {
2608 __le32 ring_group_id;
2612 /* Output (16 bytes) */
2613 struct hwrm_ring_grp_free_output {
2625 /* hwrm_arb_grp_alloc */
2626 /* Input (24 bytes) */
2627 struct hwrm_arb_grp_alloc_input {
2633 __le16 input_number;
2637 /* Output (16 bytes) */
2638 struct hwrm_arb_grp_alloc_output {
2652 /* hwrm_arb_grp_cfg */
2653 /* Input (32 bytes) */
2654 struct hwrm_arb_grp_cfg_input {
2661 __le16 input_number;
2667 /* Output (16 bytes) */
2668 struct hwrm_arb_grp_cfg_output {
2680 /* hwrm_cfa_l2_filter_alloc */
2681 /* Input (96 bytes) */
2682 struct hwrm_cfa_l2_filter_alloc_input {
2689 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
2690 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0)
2691 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0)
2692 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
2693 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
2694 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
2696 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
2697 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
2698 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
2699 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
2700 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
2701 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
2702 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
2703 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
2704 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
2705 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
2706 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
2707 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
2708 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
2709 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
2710 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
2711 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x8000UL
2712 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
2718 __le16 l2_ovlan_mask;
2720 __le16 l2_ivlan_mask;
2726 u8 t_l2_addr_mask[6];
2728 __le16 t_l2_ovlan_mask;
2730 __le16 t_l2_ivlan_mask;
2732 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0)
2733 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0)
2734 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0)
2735 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0)
2736 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0)
2737 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0)
2738 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0)
2739 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0)
2743 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
2744 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
2745 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
2746 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
2747 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
2748 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
2749 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
2750 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
2751 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
2752 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
2755 __le16 mirror_vnic_id;
2757 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
2758 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0)
2759 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0)
2760 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0)
2761 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0)
2764 __le64 l2_filter_id_hint;
2767 /* Output (24 bytes) */
2768 struct hwrm_cfa_l2_filter_alloc_output {
2773 __le64 l2_filter_id;
2781 /* hwrm_cfa_l2_filter_free */
2782 /* Input (24 bytes) */
2783 struct hwrm_cfa_l2_filter_free_input {
2789 __le64 l2_filter_id;
2792 /* Output (16 bytes) */
2793 struct hwrm_cfa_l2_filter_free_output {
2805 /* hwrm_cfa_l2_filter_cfg */
2806 /* Input (40 bytes) */
2807 struct hwrm_cfa_l2_filter_cfg_input {
2814 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
2815 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2816 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2817 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
2819 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_VNIC_ID_VALID 0x1UL
2820 __le64 l2_filter_id;
2825 /* Output (16 bytes) */
2826 struct hwrm_cfa_l2_filter_cfg_output {
2838 /* hwrm_cfa_l2_set_rx_mask */
2839 /* Input (40 bytes) */
2840 struct hwrm_cfa_l2_set_rx_mask_input {
2846 __le32 dflt_vnic_id;
2848 #define CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST 0x1UL
2849 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
2850 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
2851 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
2852 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
2853 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
2855 __le32 num_mc_entries;
2859 /* Output (16 bytes) */
2860 struct hwrm_cfa_l2_set_rx_mask_output {
2872 /* hwrm_cfa_l2_set_bcastmcast_mirroring */
2873 /* Input (32 bytes) */
2874 struct hwrm_cfa_l2_set_bcastmcast_mirroring_input {
2880 __le32 dflt_vnic_id;
2881 __le32 mirroring_flags;
2882 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_BCAST_MIRRORING 0x1UL
2883 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_MCAST_MIRRORING 0x2UL
2884 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_BCAST_SRC_KNOCKOUT 0x4UL
2885 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_MCAST_SRC_KNOCKOUT 0x8UL
2886 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_VLAN_ID_VALID 0x10UL
2889 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_PFONLY (0x0UL << 0)
2890 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_ALLPFS (0x1UL << 0)
2891 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_ALLPFSVFS (0x2UL << 0)
2893 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_PFONLY (0x0UL << 0)
2894 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_ALLPFS (0x1UL << 0)
2895 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_ALLPFSVFS (0x2UL << 0)
2899 /* Output (16 bytes) */
2900 struct hwrm_cfa_l2_set_bcastmcast_mirroring_output {
2912 /* hwrm_cfa_tunnel_filter_alloc */
2913 /* Input (88 bytes) */
2914 struct hwrm_cfa_tunnel_filter_alloc_input {
2921 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
2923 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
2924 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
2925 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
2926 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
2927 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
2928 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
2929 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
2930 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
2931 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
2932 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
2933 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
2934 __le64 l2_filter_id;
2938 __le32 t_l3_addr[4];
2942 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
2943 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
2944 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
2945 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
2946 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
2947 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
2948 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
2949 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
2950 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
2951 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
2955 __le32 mirror_vnic_id;
2958 /* Output (24 bytes) */
2959 struct hwrm_cfa_tunnel_filter_alloc_output {
2964 __le64 tunnel_filter_id;
2972 /* hwrm_cfa_tunnel_filter_free */
2973 /* Input (24 bytes) */
2974 struct hwrm_cfa_tunnel_filter_free_input {
2980 __le64 tunnel_filter_id;
2983 /* Output (16 bytes) */
2984 struct hwrm_cfa_tunnel_filter_free_output {
2996 /* hwrm_cfa_encap_record_alloc */
2997 /* Input (32 bytes) */
2998 struct hwrm_cfa_encap_record_alloc_input {
3005 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3007 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0)
3008 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0)
3009 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0)
3010 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0)
3011 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0)
3012 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0)
3013 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0)
3014 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0)
3017 __le32 encap_data[16];
3020 /* Output (24 bytes) */
3021 struct hwrm_cfa_encap_record_alloc_output {
3026 __le64 encap_record_id;
3034 /* hwrm_cfa_encap_record_free */
3035 /* Input (24 bytes) */
3036 struct hwrm_cfa_encap_record_free_input {
3042 __le64 encap_record_id;
3045 /* Output (16 bytes) */
3046 struct hwrm_cfa_encap_record_free_output {
3058 /* hwrm_cfa_ntuple_filter_alloc */
3059 /* Input (128 bytes) */
3060 struct hwrm_cfa_ntuple_filter_alloc_input {
3067 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3068 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
3070 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
3071 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
3072 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
3073 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
3074 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
3075 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
3076 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
3077 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
3078 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
3079 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
3080 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
3081 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
3082 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
3083 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
3084 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
3085 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
3086 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x10000UL
3087 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
3088 __le64 l2_filter_id;
3094 __le16 mirror_vnic_id;
3096 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3097 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3098 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3099 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3100 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3101 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3102 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3103 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3104 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3105 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3107 __be32 src_ipaddr[4];
3108 __be32 src_ipaddr_mask[4];
3109 __be32 dst_ipaddr[4];
3110 __be32 dst_ipaddr_mask[4];
3112 __be16 src_port_mask;
3114 __be16 dst_port_mask;
3115 __le64 ntuple_filter_id_hint;
3118 /* Output (24 bytes) */
3119 struct hwrm_cfa_ntuple_filter_alloc_output {
3124 __le64 ntuple_filter_id;
3132 /* hwrm_cfa_ntuple_filter_free */
3133 /* Input (24 bytes) */
3134 struct hwrm_cfa_ntuple_filter_free_input {
3140 __le64 ntuple_filter_id;
3143 /* Output (16 bytes) */
3144 struct hwrm_cfa_ntuple_filter_free_output {
3156 /* hwrm_cfa_ntuple_filter_cfg */
3157 /* Input (40 bytes) */
3158 struct hwrm_cfa_ntuple_filter_cfg_input {
3165 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_VNIC_ID_VALID 0x1UL
3166 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID_VALID 0x2UL
3168 __le64 ntuple_filter_id;
3169 __le32 new_dst_vnic_id;
3170 __le32 new_mirror_vnic_id;
3173 /* Output (16 bytes) */
3174 struct hwrm_cfa_ntuple_filter_cfg_output {
3186 /* hwrm_tunnel_dst_port_query */
3187 /* Input (24 bytes) */
3188 struct hwrm_tunnel_dst_port_query_input {
3195 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3196 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3197 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3198 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3199 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3200 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3201 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3202 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3203 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3204 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3208 /* Output (16 bytes) */
3209 struct hwrm_tunnel_dst_port_query_output {
3214 __le16 tunnel_dst_port_id;
3215 __be16 tunnel_dst_port_val;
3222 /* hwrm_tunnel_dst_port_alloc */
3223 /* Input (24 bytes) */
3224 struct hwrm_tunnel_dst_port_alloc_input {
3231 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3232 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3233 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3234 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3235 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3236 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3237 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3238 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3239 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3240 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3242 __be16 tunnel_dst_port_val;
3246 /* Output (16 bytes) */
3247 struct hwrm_tunnel_dst_port_alloc_output {
3252 __le16 tunnel_dst_port_id;
3261 /* hwrm_tunnel_dst_port_free */
3262 /* Input (24 bytes) */
3263 struct hwrm_tunnel_dst_port_free_input {
3270 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3271 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3272 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3273 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3274 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3275 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3276 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3277 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3278 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3279 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3281 __le16 tunnel_dst_port_id;
3285 /* Output (16 bytes) */
3286 struct hwrm_tunnel_dst_port_free_output {
3298 /* hwrm_stat_ctx_alloc */
3299 /* Input (32 bytes) */
3300 struct hwrm_stat_ctx_alloc_input {
3306 __le64 stats_dma_addr;
3307 __le32 update_period_ms;
3311 /* Output (16 bytes) */
3312 struct hwrm_stat_ctx_alloc_output {
3324 /* hwrm_stat_ctx_free */
3325 /* Input (24 bytes) */
3326 struct hwrm_stat_ctx_free_input {
3336 /* Output (16 bytes) */
3337 struct hwrm_stat_ctx_free_output {
3349 /* hwrm_stat_ctx_query */
3350 /* Input (24 bytes) */
3351 struct hwrm_stat_ctx_query_input {
3361 /* Output (176 bytes) */
3362 struct hwrm_stat_ctx_query_output {
3367 __le64 tx_ucast_pkts;
3368 __le64 tx_mcast_pkts;
3369 __le64 tx_bcast_pkts;
3371 __le64 tx_drop_pkts;
3372 __le64 tx_ucast_bytes;
3373 __le64 tx_mcast_bytes;
3374 __le64 tx_bcast_bytes;
3375 __le64 rx_ucast_pkts;
3376 __le64 rx_mcast_pkts;
3377 __le64 rx_bcast_pkts;
3379 __le64 rx_drop_pkts;
3380 __le64 rx_ucast_bytes;
3381 __le64 rx_mcast_bytes;
3382 __le64 rx_bcast_bytes;
3384 __le64 rx_agg_bytes;
3385 __le64 rx_agg_events;
3386 __le64 rx_agg_aborts;
3394 /* hwrm_stat_ctx_clr_stats */
3395 /* Input (24 bytes) */
3396 struct hwrm_stat_ctx_clr_stats_input {
3406 /* Output (16 bytes) */
3407 struct hwrm_stat_ctx_clr_stats_output {
3419 /* hwrm_mgmt_l2_filter_alloc */
3420 /* Input (56 bytes) */
3421 struct hwrm_mgmt_l2_filter_alloc_input {
3428 #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
3429 #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0)
3430 #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0)
3432 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDRESS 0x1UL
3433 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_OVLAN 0x2UL
3434 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_IVLAN 0x4UL
3435 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_ACTION_ID 0x8UL
3439 u8 l2_address_mask[6];
3448 #define MGMT_L2_FILTER_ALLOC_REQ_ACTION_BYPASS 0x1UL
3452 /* Output (16 bytes) */
3453 struct hwrm_mgmt_l2_filter_alloc_output {
3458 __le16 mgmt_l2_filter_id;
3467 /* hwrm_mgmt_l2_filter_free */
3468 /* Input (24 bytes) */
3469 struct hwrm_mgmt_l2_filter_free_input {
3475 __le16 mgmt_l2_filter_id;
3479 /* Output (16 bytes) */
3480 struct hwrm_mgmt_l2_filter_free_output {
3492 /* hwrm_nvm_raw_write_blk */
3493 /* Input (32 bytes) */
3494 struct hwrm_nvm_raw_write_blk_input {
3500 __le64 host_src_addr;
3505 /* Output (16 bytes) */
3506 struct hwrm_nvm_raw_write_blk_output {
3519 /* Input (40 bytes) */
3520 struct hwrm_nvm_read_input {
3526 __le64 host_dest_addr;
3535 /* Output (16 bytes) */
3536 struct hwrm_nvm_read_output {
3548 /* hwrm_nvm_raw_dump */
3549 /* Input (32 bytes) */
3550 struct hwrm_nvm_raw_dump_input {
3556 __le64 host_dest_addr;
3561 /* Output (16 bytes) */
3562 struct hwrm_nvm_raw_dump_output {
3574 /* hwrm_nvm_get_dir_entries */
3575 /* Input (24 bytes) */
3576 struct hwrm_nvm_get_dir_entries_input {
3582 __le64 host_dest_addr;
3585 /* Output (16 bytes) */
3586 struct hwrm_nvm_get_dir_entries_output {
3598 /* hwrm_nvm_get_dir_info */
3599 /* Input (16 bytes) */
3600 struct hwrm_nvm_get_dir_info_input {
3608 /* Output (24 bytes) */
3609 struct hwrm_nvm_get_dir_info_output {
3615 __le32 entry_length;
3623 /* hwrm_nvm_write */
3624 /* Input (40 bytes) */
3625 struct hwrm_nvm_write_input {
3631 __le64 host_src_addr;
3636 __le32 dir_data_length;
3639 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
3642 /* Output (16 bytes) */
3643 struct hwrm_nvm_write_output {
3655 /* hwrm_nvm_modify */
3656 /* Input (40 bytes) */
3657 struct hwrm_nvm_modify_input {
3663 __le64 host_src_addr;
3672 /* Output (16 bytes) */
3673 struct hwrm_nvm_modify_output {
3685 /* hwrm_nvm_find_dir_entry */
3686 /* Input (32 bytes) */
3687 struct hwrm_nvm_find_dir_entry_input {
3694 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
3700 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
3701 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
3702 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0)
3703 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0)
3704 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0)
3708 /* Output (32 bytes) */
3709 struct hwrm_nvm_find_dir_entry_output {
3714 __le32 dir_item_length;
3715 __le32 dir_data_length;
3726 /* hwrm_nvm_erase_dir_entry */
3727 /* Input (24 bytes) */
3728 struct hwrm_nvm_erase_dir_entry_input {
3738 /* Output (16 bytes) */
3739 struct hwrm_nvm_erase_dir_entry_output {
3751 /* hwrm_nvm_get_dev_info */
3752 /* Input (16 bytes) */
3753 struct hwrm_nvm_get_dev_info_input {
3761 /* Output (32 bytes) */
3762 struct hwrm_nvm_get_dev_info_output {
3767 __le16 manufacturer_id;
3771 __le32 reserved_size;
3772 __le32 available_size;
3779 /* hwrm_nvm_mod_dir_entry */
3780 /* Input (32 bytes) */
3781 struct hwrm_nvm_mod_dir_entry_input {
3788 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
3796 /* Output (16 bytes) */
3797 struct hwrm_nvm_mod_dir_entry_output {
3809 /* hwrm_nvm_verify_update */
3810 /* Input (24 bytes) */
3811 struct hwrm_nvm_verify_update_input {
3823 /* Output (16 bytes) */
3824 struct hwrm_nvm_verify_update_output {
3836 /* hwrm_exec_fwd_resp */
3837 /* Input (120 bytes) */
3838 struct hwrm_exec_fwd_resp_input {
3844 __le32 encap_request[24];
3845 __le16 encap_resp_target_id;
3849 /* Output (16 bytes) */
3850 struct hwrm_exec_fwd_resp_output {
3862 /* hwrm_reject_fwd_resp */
3863 /* Input (120 bytes) */
3864 struct hwrm_reject_fwd_resp_input {
3870 __le32 encap_request[24];
3871 __le16 encap_resp_target_id;
3875 /* Output (16 bytes) */
3876 struct hwrm_reject_fwd_resp_output {
3889 /* Input (40 bytes) */
3890 struct hwrm_fwd_resp_input {
3896 __le16 encap_resp_target_id;
3897 __le16 encap_resp_cmpl_ring;
3898 __le16 encap_resp_len;
3901 __le64 encap_resp_addr;
3902 __le32 encap_resp[24];
3905 /* Output (16 bytes) */
3906 struct hwrm_fwd_resp_output {
3918 /* hwrm_fwd_async_event_cmpl */
3919 /* Input (32 bytes) */
3920 struct hwrm_fwd_async_event_cmpl_input {
3926 __le16 encap_async_event_target_id;
3931 __le32 encap_async_event_cmpl[4];
3934 /* Output (16 bytes) */
3935 struct hwrm_fwd_async_event_cmpl_output {
3948 /* Input (24 bytes) */
3949 struct hwrm_fw_reset_input {
3955 u8 embedded_proc_type;
3956 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIMP (0x0UL << 0)
3957 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_APE (0x1UL << 0)
3958 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_KONG (0x2UL << 0)
3959 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BONO (0x3UL << 0)
3960 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_TANG (0x4UL << 0)
3962 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3963 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3964 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3968 /* Output (16 bytes) */
3969 struct hwrm_fw_reset_output {
3975 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3976 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3977 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3986 /* hwrm_fw_qstatus */
3987 /* Input (24 bytes) */
3988 struct hwrm_fw_qstatus_input {
3994 u8 embedded_proc_type;
3995 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIMP (0x0UL << 0)
3996 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_APE (0x1UL << 0)
3997 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_KONG (0x2UL << 0)
3998 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BONO (0x3UL << 0)
3999 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_TANG (0x4UL << 0)
4003 /* Output (16 bytes) */
4004 struct hwrm_fw_qstatus_output {
4010 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
4011 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
4012 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
4021 /* hwrm_temp_monitor_query */
4022 /* Input (16 bytes) */
4023 struct hwrm_temp_monitor_query_input {
4031 /* Output (16 bytes) */
4032 struct hwrm_temp_monitor_query_output {