drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15
  16 /* DO NOT CHANGE DRV_VER_* defines
  17  * FIXME: Delete them
  18  */
  19 #define DRV_VER_MAJ     1
  20 #define DRV_VER_MIN     10
  21 #define DRV_VER_UPD     1
  22
  23 #include <linux/interrupt.h>
  24 #include <linux/rhashtable.h>
  25 #include <linux/crash_dump.h>
  26 #include <net/devlink.h>
  27 #include <net/dst_metadata.h>
  28 #include <net/xdp.h>
  29 #include <linux/dim.h>
  30 #ifdef CONFIG_TEE_BNXT_FW
  31 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
  32 #endif
  33
  34 extern struct list_head bnxt_block_cb_list;
  35
  36 struct page_pool;
  37
  38 struct tx_bd {
  39         __le32 tx_bd_len_flags_type;
  40         #define TX_BD_TYPE                                      (0x3f << 0)
  41          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  42          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  43         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  44         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  45         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  46          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  47         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  48          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  49          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  50          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  51          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  52          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  53         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  54         #define TX_BD_LEN                                       (0xffff << 16)
  55          #define TX_BD_LEN_SHIFT                                 16
  56
  57         u32 tx_bd_opaque;
  58         __le64 tx_bd_haddr;
  59 } __packed;
  60
  61 struct tx_bd_ext {
  62         __le32 tx_bd_hsize_lflags;
  63         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  64         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  65         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  66         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  67         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  68         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  69         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  70         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  71         #define TX_BD_HSIZE                                     (0xff << 16)
  72          #define TX_BD_HSIZE_SHIFT                               16
  73
  74         __le32 tx_bd_mss;
  75         __le32 tx_bd_cfa_action;
  76         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  77          #define TX_BD_CFA_ACTION_SHIFT                          16
  78
  79         __le32 tx_bd_cfa_meta;
  80         #define TX_BD_CFA_META_MASK                             0xfffffff
  81         #define TX_BD_CFA_META_VID_MASK                         0xfff
  82         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  83          #define TX_BD_CFA_META_PRI_SHIFT                        12
  84         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  85          #define TX_BD_CFA_META_TPID_SHIFT                       16
  86         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  87          #define TX_BD_CFA_META_KEY_SHIFT                        28
  88         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  89 };
  90
  91 struct rx_bd {
  92         __le32 rx_bd_len_flags_type;
  93         #define RX_BD_TYPE                                      (0x3f << 0)
  94          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  95          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  96          #define RX_BD_TYPE_RX_AGG_BD                            0x6
  97          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
  98          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
  99          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
 100          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
 101         #define RX_BD_FLAGS_SOP                                 (1 << 6)
 102         #define RX_BD_FLAGS_EOP                                 (1 << 7)
 103         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
 104          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
 105          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
 106          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
 107          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
 108         #define RX_BD_LEN                                       (0xffff << 16)
 109          #define RX_BD_LEN_SHIFT                                 16
 110
 111         u32 rx_bd_opaque;
 112         __le64 rx_bd_haddr;
 113 };
 114
 115 struct tx_cmp {
 116         __le32 tx_cmp_flags_type;
 117         #define CMP_TYPE                                        (0x3f << 0)
 118          #define CMP_TYPE_TX_L2_CMP                              0
 119          #define CMP_TYPE_RX_L2_CMP                              17
 120          #define CMP_TYPE_RX_AGG_CMP                             18
 121          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 122          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 123          #define CMP_TYPE_RX_TPA_AGG_CMP                         22
 124          #define CMP_TYPE_STATUS_CMP                             32
 125          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 126          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 127          #define CMP_TYPE_ERROR_STATUS                           48
 128          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 129          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 130          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 131          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 132          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 133
 134         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 135         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 136
 137         u32 tx_cmp_opaque;
 138         __le32 tx_cmp_errors_v;
 139         #define TX_CMP_V                                        (1 << 0)
 140         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 141          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 142          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 143          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 144          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 145          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 146          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 147          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 148          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 149
 150         __le32 tx_cmp_unsed_3;
 151 };
 152
 153 struct rx_cmp {
 154         __le32 rx_cmp_len_flags_type;
 155         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 156         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 157         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 158         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 159         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 160          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 161          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 162          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 163          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 164          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 165          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 166          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 167          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 168          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 169         #define RX_CMP_LEN                                      (0xffff << 16)
 170          #define RX_CMP_LEN_SHIFT                                16
 171
 172         u32 rx_cmp_opaque;
 173         __le32 rx_cmp_misc_v1;
 174         #define RX_CMP_V1                                       (1 << 0)
 175         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 176          #define RX_CMP_AGG_BUFS_SHIFT                           1
 177         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 178          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 179         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 180          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 181
 182         __le32 rx_cmp_rss_hash;
 183 };
 184
 185 #define RX_CMP_HASH_VALID(rxcmp)                                \
 186         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 187
 188 #define RSS_PROFILE_ID_MASK     0x1f
 189
 190 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 191         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 192           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 193
 194 struct rx_cmp_ext {
 195         __le32 rx_cmp_flags2;
 196         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 197         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 198         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 199         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 200         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 201         __le32 rx_cmp_meta_data;
 202         #define RX_CMP_FLAGS2_METADATA_TCI_MASK                 0xffff
 203         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 204         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 205          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 206         __le32 rx_cmp_cfa_code_errors_v2;
 207         #define RX_CMP_V                                        (1 << 0)
 208         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 209          #define RX_CMPL_ERRORS_SFT                              1
 210         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 211          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 212          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 213          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 214          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 215         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 216         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 217         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 218         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 219         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 220         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 221          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 222          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 223          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 224          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 225          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 226          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 227          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 228         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 229          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 230          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 231          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 232          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 233          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 234          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 235          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 236          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 237          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 238
 239         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 240          #define RX_CMPL_CFA_CODE_SFT                            16
 241
 242         __le32 rx_cmp_unused3;
 243 };
 244
 245 #define RX_CMP_L2_ERRORS                                                \
 246         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 247
 248 #define RX_CMP_L4_CS_BITS                                               \
 249         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 250
 251 #define RX_CMP_L4_CS_ERR_BITS                                           \
 252         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 253
 254 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 255             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 256              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 257
 258 #define RX_CMP_ENCAP(rxcmp1)                                            \
 259             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 260              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 261
 262 #define RX_CMP_CFA_CODE(rxcmpl1)                                        \
 263         ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &           \
 264           RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
 265
 266 struct rx_agg_cmp {
 267         __le32 rx_agg_cmp_len_flags_type;
 268         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 269         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 270          #define RX_AGG_CMP_LEN_SHIFT                            16
 271         u32 rx_agg_cmp_opaque;
 272         __le32 rx_agg_cmp_v;
 273         #define RX_AGG_CMP_V                                    (1 << 0)
 274         #define RX_AGG_CMP_AGG_ID                               (0xffff << 16)
 275          #define RX_AGG_CMP_AGG_ID_SHIFT                         16
 276         __le32 rx_agg_cmp_unused;
 277 };
 278
 279 #define TPA_AGG_AGG_ID(rx_agg)                          \
 280         ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &         \
 281          RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
 282
 283 struct rx_tpa_start_cmp {
 284         __le32 rx_tpa_start_cmp_len_flags_type;
 285         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 286         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 287          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 288         #define RX_TPA_START_CMP_FLAGS_ERROR                    (0x1 << 6)
 289         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 290          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 291          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 292          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 293          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 294          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 295         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 296         #define RX_TPA_START_CMP_FLAGS_TIMESTAMP                (0x1 << 11)
 297         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 298          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 299          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 300         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 301          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 302
 303         u32 rx_tpa_start_cmp_opaque;
 304         __le32 rx_tpa_start_cmp_misc_v1;
 305         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 306         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 307          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 308         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 309          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 310         #define RX_TPA_START_CMP_AGG_ID_P5                      (0xffff << 16)
 311          #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5                16
 312
 313         __le32 rx_tpa_start_cmp_rss_hash;
 314 };
 315
 316 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 317         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 318          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 319
 320 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 321         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 322            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 323           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 324
 325 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 326         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 327          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 328
 329 #define TPA_START_AGG_ID_P5(rx_tpa_start)                               \
 330         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 331          RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
 332
 333 #define TPA_START_ERROR(rx_tpa_start)                                   \
 334         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 335          cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
 336
 337 struct rx_tpa_start_cmp_ext {
 338         __le32 rx_tpa_start_cmp_flags2;
 339         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 340         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 341         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 342         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 343         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 344         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID         (0x1 << 9)
 345         #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT         (0x3 << 10)
 346          #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT   10
 347         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL               (0xffff << 16)
 348          #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT         16
 349
 350         __le32 rx_tpa_start_cmp_metadata;
 351         __le32 rx_tpa_start_cmp_cfa_code_v2;
 352         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 353         #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK       (0x7 << 1)
 354          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT      1
 355          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER  (0x0 << 1)
 356          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
 357          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH      (0x5 << 1)
 358         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 359          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 360         __le32 rx_tpa_start_cmp_hdr_info;
 361 };
 362
 363 #define TPA_START_CFA_CODE(rx_tpa_start)                                \
 364         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 365          RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
 366
 367 #define TPA_START_IS_IPV6(rx_tpa_start)                         \
 368         (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &           \
 369             cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
 370
 371 #define TPA_START_ERROR_CODE(rx_tpa_start)                              \
 372         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 373           RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>                 \
 374          RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
 375
 376 struct rx_tpa_end_cmp {
 377         __le32 rx_tpa_end_cmp_len_flags_type;
 378         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 379         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 380          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 381         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 382          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 383          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 384          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 385          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 386          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 387         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 388         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 389          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 390          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 391         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 392          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 393
 394         u32 rx_tpa_end_cmp_opaque;
 395         __le32 rx_tpa_end_cmp_misc_v1;
 396         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 397         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 398          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 399         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 400          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 401         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 402          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 403         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 404          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 405         #define RX_TPA_END_CMP_AGG_ID_P5                        (0xffff << 16)
 406          #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5                  16
 407
 408         __le32 rx_tpa_end_cmp_tsdelta;
 409         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 410 };
 411
 412 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 413         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 414          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 415
 416 #define TPA_END_AGG_ID_P5(rx_tpa_end)                                   \
 417         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 418          RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
 419
 420 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)                                 \
 421         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 422          RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
 423
 424 #define TPA_END_AGG_BUFS(rx_tpa_end)                                    \
 425         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 426          RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
 427
 428 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 429         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 430          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 431
 432 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 433         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 434                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 435
 436 #define TPA_END_GRO(rx_tpa_end)                                         \
 437         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 438          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 439
 440 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 441         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 442             cpu_to_le32(RX_TPA_END_GRO_TS)))
 443
 444 struct rx_tpa_end_cmp_ext {
 445         __le32 rx_tpa_end_cmp_dup_acks;
 446         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 447         #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5                (0xff << 16)
 448          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5          16
 449         #define RX_TPA_END_CMP_AGG_BUFS_P5                      (0xff << 24)
 450          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5                24
 451
 452         __le32 rx_tpa_end_cmp_seg_len;
 453         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 454
 455         __le32 rx_tpa_end_cmp_errors_v2;
 456         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 457         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 458         #define RX_TPA_END_CMP_ERRORS_P5                        (0x7 << 1)
 459         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 460          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER    (0x0 << 1)
 461          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP  (0x2 << 1)
 462          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT   (0x3 << 1)
 463          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR    (0x4 << 1)
 464          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH        (0x5 << 1)
 465
 466         u32 rx_tpa_end_cmp_start_opaque;
 467 };
 468
 469 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 470         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 471          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 472
 473 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)                          \
 474         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 475          RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>                           \
 476         RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
 477
 478 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)                             \
 479         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 480          RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
 481
 482 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)                           \
 483         (((data1) &                                                     \
 484           ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
 485          ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
 486
 487 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)                         \
 488         !!((data1) &                                                    \
 489            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
 490
 491 #define EVENT_DATA1_RECOVERY_ENABLED(data1)                             \
 492         !!((data1) &                                                    \
 493            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
 494
 495 struct nqe_cn {
 496         __le16  type;
 497         #define NQ_CN_TYPE_MASK           0x3fUL
 498         #define NQ_CN_TYPE_SFT            0
 499         #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
 500         #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
 501         __le16  reserved16;
 502         __le32  cq_handle_low;
 503         __le32  v;
 504         #define NQ_CN_V     0x1UL
 505         __le32  cq_handle_high;
 506 };
 507
 508 #define DB_IDX_MASK                                             0xffffff
 509 #define DB_IDX_VALID                                            (0x1 << 26)
 510 #define DB_IRQ_DIS                                              (0x1 << 27)
 511 #define DB_KEY_TX                                               (0x0 << 28)
 512 #define DB_KEY_RX                                               (0x1 << 28)
 513 #define DB_KEY_CP                                               (0x2 << 28)
 514 #define DB_KEY_ST                                               (0x3 << 28)
 515 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 516 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 517
 518 #define BNXT_MIN_ROCE_CP_RINGS  2
 519 #define BNXT_MIN_ROCE_STAT_CTXS 1
 520
 521 /* 64-bit doorbell */
 522 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
 523 #define DBR_XID_MASK                                    0x000fffff00000000ULL
 524 #define DBR_XID_SFT                                     32
 525 #define DBR_PATH_L2                                     (0x1ULL << 56)
 526 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
 527 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
 528 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
 529 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
 530 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
 531 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
 532 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
 533 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
 534 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
 535 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
 536 #define DBR_TYPE_NQ                                     (0xaULL << 60)
 537 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
 538 #define DBR_TYPE_NULL                                   (0xfULL << 60)
 539
 540 #define DB_PF_OFFSET_P5                                 0x10000
 541 #define DB_VF_OFFSET_P5                                 0x4000
 542
 543 #define INVALID_HW_RING_ID      ((u16)-1)
 544
 545 /* The hardware supports certain page sizes.  Use the supported page sizes
 546  * to allocate the rings.
 547  */
 548 #if (PAGE_SHIFT < 12)
 549 #define BNXT_PAGE_SHIFT 12
 550 #elif (PAGE_SHIFT <= 13)
 551 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 552 #elif (PAGE_SHIFT < 16)
 553 #define BNXT_PAGE_SHIFT 13
 554 #else
 555 #define BNXT_PAGE_SHIFT 16
 556 #endif
 557
 558 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 559
 560 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 561 #if (PAGE_SHIFT > 15)
 562 #define BNXT_RX_PAGE_SHIFT 15
 563 #else
 564 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 565 #endif
 566
 567 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 568
 569 #define BNXT_MAX_MTU            9500
 570 #define BNXT_MAX_PAGE_MODE_MTU  \
 571         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 572          XDP_PACKET_HEADROOM - \
 573          SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
 574
 575 #define BNXT_MIN_PKT_SIZE       52
 576
 577 #define BNXT_DEFAULT_RX_RING_SIZE       511
 578 #define BNXT_DEFAULT_TX_RING_SIZE       511
 579
 580 #define MAX_TPA         64
 581 #define MAX_TPA_P5      256
 582 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
 583 #define MAX_TPA_SEGS_P5 0x3f
 584
 585 #if (BNXT_PAGE_SHIFT == 16)
 586 #define MAX_RX_PAGES    1
 587 #define MAX_RX_AGG_PAGES        4
 588 #define MAX_TX_PAGES    1
 589 #define MAX_CP_PAGES    8
 590 #else
 591 #define MAX_RX_PAGES    8
 592 #define MAX_RX_AGG_PAGES        32
 593 #define MAX_TX_PAGES    8
 594 #define MAX_CP_PAGES    64
 595 #endif
 596
 597 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 598 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 599 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 600
 601 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 602 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 603
 604 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 605
 606 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 607 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 608
 609 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 610
 611 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 612 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 613 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 614
 615 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra
 616  * BD because the first TX BD is always a long BD.
 617  */
 618 #define BNXT_MIN_TX_DESC_CNT            (MAX_SKB_FRAGS + 2)
 619
 620 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 621 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 622
 623 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 624 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 625
 626 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 627 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 628
 629 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 630         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 631          !((raw_cons) & bp->cp_bit))
 632
 633 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 634         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 635          !((raw_cons) & bp->cp_bit))
 636
 637 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 638         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 639          !((raw_cons) & bp->cp_bit))
 640
 641 #define NQ_CMP_VALID(nqcmp, raw_cons)                           \
 642         (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
 643
 644 #define TX_CMP_TYPE(txcmp)                                      \
 645         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 646
 647 #define RX_CMP_TYPE(rxcmp)                                      \
 648         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 649
 650 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 651
 652 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 653
 654 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 655
 656 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 657 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 658 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 659 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 660
 661 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
 662 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 663 #define DFLT_HWRM_CMD_TIMEOUT           500
 664 #define SHORT_HWRM_CMD_TIMEOUT          20
 665 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
 666 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 667 #define HWRM_COREDUMP_TIMEOUT           ((HWRM_CMD_TIMEOUT) * 12)
 668 #define BNXT_HWRM_REQ_MAX_SIZE          128
 669 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 670                                          BNXT_HWRM_REQ_MAX_SIZE)
 671 #define HWRM_SHORT_MIN_TIMEOUT          3
 672 #define HWRM_SHORT_MAX_TIMEOUT          10
 673 #define HWRM_SHORT_TIMEOUT_COUNTER      5
 674
 675 #define HWRM_MIN_TIMEOUT                25
 676 #define HWRM_MAX_TIMEOUT                40
 677
 678 #define HWRM_TOTAL_TIMEOUT(n)   (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?  \
 679         ((n) * HWRM_SHORT_MIN_TIMEOUT) :                                \
 680         (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +          \
 681          ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
 682
 683 #define HWRM_VALID_BIT_DELAY_USEC       150
 684
 685 #define BNXT_HWRM_CHNL_CHIMP    0
 686 #define BNXT_HWRM_CHNL_KONG     1
 687
 688 #define BNXT_RX_EVENT           1
 689 #define BNXT_AGG_EVENT          2
 690 #define BNXT_TX_EVENT           4
 691 #define BNXT_REDIRECT_EVENT     8
 692
 693 struct bnxt_sw_tx_bd {
 694         union {
 695                 struct sk_buff          *skb;
 696                 struct xdp_frame        *xdpf;
 697         };
 698         DEFINE_DMA_UNMAP_ADDR(mapping);
 699         DEFINE_DMA_UNMAP_LEN(len);
 700         u8                      is_gso;
 701         u8                      is_push;
 702         u8                      action;
 703         union {
 704                 unsigned short          nr_frags;
 705                 u16                     rx_prod;
 706         };
 707 };
 708
 709 struct bnxt_sw_rx_bd {
 710         void                    *data;
 711         u8                      *data_ptr;
 712         dma_addr_t              mapping;
 713 };
 714
 715 struct bnxt_sw_rx_agg_bd {
 716         struct page             *page;
 717         unsigned int            offset;
 718         dma_addr_t              mapping;
 719 };
 720
 721 struct bnxt_ring_mem_info {
 722         int                     nr_pages;
 723         int                     page_size;
 724         u16                     flags;
 725 #define BNXT_RMEM_VALID_PTE_FLAG        1
 726 #define BNXT_RMEM_RING_PTE_FLAG         2
 727 #define BNXT_RMEM_USE_FULL_PAGE_FLAG    4
 728
 729         u16                     depth;
 730         u8                      init_val;
 731
 732         void                    **pg_arr;
 733         dma_addr_t              *dma_arr;
 734
 735         __le64                  *pg_tbl;
 736         dma_addr_t              pg_tbl_map;
 737
 738         int                     vmem_size;
 739         void                    **vmem;
 740 };
 741
 742 struct bnxt_ring_struct {
 743         struct bnxt_ring_mem_info       ring_mem;
 744
 745         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 746         union {
 747                 u16             grp_idx;
 748                 u16             map_idx; /* Used by cmpl rings */
 749         };
 750         u32                     handle;
 751         u8                      queue_id;
 752 };
 753
 754 struct tx_push_bd {
 755         __le32                  doorbell;
 756         __le32                  tx_bd_len_flags_type;
 757         u32                     tx_bd_opaque;
 758         struct tx_bd_ext        txbd2;
 759 };
 760
 761 struct tx_push_buffer {
 762         struct tx_push_bd       push_bd;
 763         u32                     data[25];
 764 };
 765
 766 struct bnxt_db_info {
 767         void __iomem            *doorbell;
 768         union {
 769                 u64             db_key64;
 770                 u32             db_key32;
 771         };
 772 };
 773
 774 struct bnxt_tx_ring_info {
 775         struct bnxt_napi        *bnapi;
 776         u16                     tx_prod;
 777         u16                     tx_cons;
 778         u16                     txq_index;
 779         u8                      kick_pending;
 780         struct bnxt_db_info     tx_db;
 781
 782         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 783         struct bnxt_sw_tx_bd    *tx_buf_ring;
 784
 785         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 786
 787         struct tx_push_buffer   *tx_push;
 788         dma_addr_t              tx_push_mapping;
 789         __le64                  data_mapping;
 790
 791 #define BNXT_DEV_STATE_CLOSING  0x1
 792         u32                     dev_state;
 793
 794         struct bnxt_ring_struct tx_ring_struct;
 795 };
 796
 797 #define BNXT_LEGACY_COAL_CMPL_PARAMS                                    \
 798         (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |           \
 799          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |           \
 800          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |               \
 801          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |                 \
 802          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |         \
 803          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
 804          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |         \
 805          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
 806          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
 807
 808 #define BNXT_COAL_CMPL_ENABLES                                          \
 809         (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
 810          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
 811          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
 812          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
 813
 814 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE                                   \
 815         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
 816
 817 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE                       \
 818         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
 819
 820 struct bnxt_coal_cap {
 821         u32                     cmpl_params;
 822         u32                     nq_params;
 823         u16                     num_cmpl_dma_aggr_max;
 824         u16                     num_cmpl_dma_aggr_during_int_max;
 825         u16                     cmpl_aggr_dma_tmr_max;
 826         u16                     cmpl_aggr_dma_tmr_during_int_max;
 827         u16                     int_lat_tmr_min_max;
 828         u16                     int_lat_tmr_max_max;
 829         u16                     num_cmpl_aggr_int_max;
 830         u16                     timer_units;
 831 };
 832
 833 struct bnxt_coal {
 834         u16                     coal_ticks;
 835         u16                     coal_ticks_irq;
 836         u16                     coal_bufs;
 837         u16                     coal_bufs_irq;
 838                         /* RING_IDLE enabled when coal ticks < idle_thresh  */
 839         u16                     idle_thresh;
 840         u8                      bufs_per_record;
 841         u8                      budget;
 842 };
 843
 844 struct bnxt_tpa_info {
 845         void                    *data;
 846         u8                      *data_ptr;
 847         dma_addr_t              mapping;
 848         u16                     len;
 849         unsigned short          gso_type;
 850         u32                     flags2;
 851         u32                     metadata;
 852         enum pkt_hash_types     hash_type;
 853         u32                     rss_hash;
 854         u32                     hdr_info;
 855
 856 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 857         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 858
 859 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 860         (((hdr_info) >> 18) & 0x1ff)
 861
 862 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 863         (((hdr_info) >> 9) & 0x1ff)
 864
 865 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 866         ((hdr_info) & 0x1ff)
 867
 868         u16                     cfa_code; /* cfa_code in TPA start compl */
 869         u8                      agg_count;
 870         struct rx_agg_cmp       *agg_arr;
 871 };
 872
 873 #define BNXT_AGG_IDX_BMAP_SIZE  (MAX_TPA_P5 / BITS_PER_LONG)
 874
 875 struct bnxt_tpa_idx_map {
 876         u16             agg_id_tbl[1024];
 877         unsigned long   agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
 878 };
 879
 880 struct bnxt_rx_ring_info {
 881         struct bnxt_napi        *bnapi;
 882         u16                     rx_prod;
 883         u16                     rx_agg_prod;
 884         u16                     rx_sw_agg_prod;
 885         u16                     rx_next_cons;
 886         struct bnxt_db_info     rx_db;
 887         struct bnxt_db_info     rx_agg_db;
 888
 889         struct bpf_prog         *xdp_prog;
 890
 891         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 892         struct bnxt_sw_rx_bd    *rx_buf_ring;
 893
 894         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 895         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 896
 897         unsigned long           *rx_agg_bmap;
 898         u16                     rx_agg_bmap_size;
 899
 900         struct page             *rx_page;
 901         unsigned int            rx_page_offset;
 902
 903         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 904         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 905
 906         struct bnxt_tpa_info    *rx_tpa;
 907         struct bnxt_tpa_idx_map *rx_tpa_idx_map;
 908
 909         struct bnxt_ring_struct rx_ring_struct;
 910         struct bnxt_ring_struct rx_agg_ring_struct;
 911         struct xdp_rxq_info     xdp_rxq;
 912         struct page_pool        *page_pool;
 913 };
 914
 915 struct bnxt_rx_sw_stats {
 916         u64                     rx_l4_csum_errors;
 917         u64                     rx_resets;
 918         u64                     rx_buf_errors;
 919 };
 920
 921 struct bnxt_cmn_sw_stats {
 922         u64                     missed_irqs;
 923 };
 924
 925 struct bnxt_sw_stats {
 926         struct bnxt_rx_sw_stats rx;
 927         struct bnxt_cmn_sw_stats cmn;
 928 };
 929
 930 struct bnxt_stats_mem {
 931         u64             *sw_stats;
 932         u64             *hw_masks;
 933         void            *hw_stats;
 934         dma_addr_t      hw_stats_map;
 935         int             len;
 936 };
 937
 938 struct bnxt_cp_ring_info {
 939         struct bnxt_napi        *bnapi;
 940         u32                     cp_raw_cons;
 941         struct bnxt_db_info     cp_db;
 942
 943         u8                      had_work_done:1;
 944         u8                      has_more_work:1;
 945
 946         u32                     last_cp_raw_cons;
 947
 948         struct bnxt_coal        rx_ring_coal;
 949         u64                     rx_packets;
 950         u64                     rx_bytes;
 951         u64                     event_ctr;
 952
 953         struct dim              dim;
 954
 955         union {
 956                 struct tx_cmp   *cp_desc_ring[MAX_CP_PAGES];
 957                 struct nqe_cn   *nq_desc_ring[MAX_CP_PAGES];
 958         };
 959
 960         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 961
 962         struct bnxt_stats_mem   stats;
 963         u32                     hw_stats_ctx_id;
 964
 965         struct bnxt_sw_stats    sw_stats;
 966
 967         struct bnxt_ring_struct cp_ring_struct;
 968
 969         struct bnxt_cp_ring_info *cp_ring_arr[2];
 970 #define BNXT_RX_HDL     0
 971 #define BNXT_TX_HDL     1
 972 };
 973
 974 struct bnxt_napi {
 975         struct napi_struct      napi;
 976         struct bnxt             *bp;
 977
 978         int                     index;
 979         struct bnxt_cp_ring_info        cp_ring;
 980         struct bnxt_rx_ring_info        *rx_ring;
 981         struct bnxt_tx_ring_info        *tx_ring;
 982
 983         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 984                                           int);
 985         int                     tx_pkts;
 986         u8                      events;
 987
 988         u32                     flags;
 989 #define BNXT_NAPI_FLAG_XDP      0x1
 990
 991         bool                    in_reset;
 992 };
 993
 994 struct bnxt_irq {
 995         irq_handler_t   handler;
 996         unsigned int    vector;
 997         u8              requested:1;
 998         u8              have_cpumask:1;
 999         char            name[IFNAMSIZ + 2];
1000         cpumask_var_t   cpu_mask;
1001 };
1002
1003 #define HWRM_RING_ALLOC_TX      0x1
1004 #define HWRM_RING_ALLOC_RX      0x2
1005 #define HWRM_RING_ALLOC_AGG     0x4
1006 #define HWRM_RING_ALLOC_CMPL    0x8
1007 #define HWRM_RING_ALLOC_NQ      0x10
1008
1009 #define INVALID_STATS_CTX_ID    -1
1010
1011 struct bnxt_ring_grp_info {
1012         u16     fw_stats_ctx;
1013         u16     fw_grp_id;
1014         u16     rx_fw_ring_id;
1015         u16     agg_fw_ring_id;
1016         u16     cp_fw_ring_id;
1017 };
1018
1019 struct bnxt_vnic_info {
1020         u16             fw_vnic_id; /* returned by Chimp during alloc */
1021 #define BNXT_MAX_CTX_PER_VNIC   8
1022         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1023         u16             fw_l2_ctx_id;
1024 #define BNXT_MAX_UC_ADDRS       4
1025         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1026                                 /* index 0 always dev_addr */
1027         u16             uc_filter_count;
1028         u8              *uc_list;
1029
1030         u16             *fw_grp_ids;
1031         dma_addr_t      rss_table_dma_addr;
1032         __le16          *rss_table;
1033         dma_addr_t      rss_hash_key_dma_addr;
1034         u64             *rss_hash_key;
1035         int             rss_table_size;
1036 #define BNXT_RSS_TABLE_ENTRIES_P5       64
1037 #define BNXT_RSS_TABLE_SIZE_P5          (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1038 #define BNXT_RSS_TABLE_MAX_TBL_P5       8
1039 #define BNXT_MAX_RSS_TABLE_SIZE_P5                              \
1040         (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1041 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5                           \
1042         (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1043
1044         u32             rx_mask;
1045
1046         u8              *mc_list;
1047         int             mc_list_size;
1048         int             mc_list_count;
1049         dma_addr_t      mc_list_mapping;
1050 #define BNXT_MAX_MC_ADDRS       16
1051
1052         u32             flags;
1053 #define BNXT_VNIC_RSS_FLAG      1
1054 #define BNXT_VNIC_RFS_FLAG      2
1055 #define BNXT_VNIC_MCAST_FLAG    4
1056 #define BNXT_VNIC_UCAST_FLAG    8
1057 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
1058 };
1059
1060 struct bnxt_hw_resc {
1061         u16     min_rsscos_ctxs;
1062         u16     max_rsscos_ctxs;
1063         u16     min_cp_rings;
1064         u16     max_cp_rings;
1065         u16     resv_cp_rings;
1066         u16     min_tx_rings;
1067         u16     max_tx_rings;
1068         u16     resv_tx_rings;
1069         u16     max_tx_sch_inputs;
1070         u16     min_rx_rings;
1071         u16     max_rx_rings;
1072         u16     resv_rx_rings;
1073         u16     min_hw_ring_grps;
1074         u16     max_hw_ring_grps;
1075         u16     resv_hw_ring_grps;
1076         u16     min_l2_ctxs;
1077         u16     max_l2_ctxs;
1078         u16     min_vnics;
1079         u16     max_vnics;
1080         u16     resv_vnics;
1081         u16     min_stat_ctxs;
1082         u16     max_stat_ctxs;
1083         u16     resv_stat_ctxs;
1084         u16     max_nqs;
1085         u16     max_irqs;
1086         u16     resv_irqs;
1087 };
1088
1089 #if defined(CONFIG_BNXT_SRIOV)
1090 struct bnxt_vf_info {
1091         u16     fw_fid;
1092         u8      mac_addr[ETH_ALEN];     /* PF assigned MAC Address */
1093         u8      vf_mac_addr[ETH_ALEN];  /* VF assigned MAC address, only
1094                                          * stored by PF.
1095                                          */
1096         u16     vlan;
1097         u16     func_qcfg_flags;
1098         u32     flags;
1099 #define BNXT_VF_QOS             0x1
1100 #define BNXT_VF_SPOOFCHK        0x2
1101 #define BNXT_VF_LINK_FORCED     0x4
1102 #define BNXT_VF_LINK_UP         0x8
1103 #define BNXT_VF_TRUST           0x10
1104         u32     min_tx_rate;
1105         u32     max_tx_rate;
1106         void    *hwrm_cmd_req_addr;
1107         dma_addr_t      hwrm_cmd_req_dma_addr;
1108 };
1109 #endif
1110
1111 struct bnxt_pf_info {
1112 #define BNXT_FIRST_PF_FID       1
1113 #define BNXT_FIRST_VF_FID       128
1114         u16     fw_fid;
1115         u16     port_id;
1116         u8      mac_addr[ETH_ALEN];
1117         u32     first_vf_id;
1118         u16     active_vfs;
1119         u16     registered_vfs;
1120         u16     max_vfs;
1121         u32     max_encap_records;
1122         u32     max_decap_records;
1123         u32     max_tx_em_flows;
1124         u32     max_tx_wm_flows;
1125         u32     max_rx_em_flows;
1126         u32     max_rx_wm_flows;
1127         unsigned long   *vf_event_bmap;
1128         u16     hwrm_cmd_req_pages;
1129         u8      vf_resv_strategy;
1130 #define BNXT_VF_RESV_STRATEGY_MAXIMAL   0
1131 #define BNXT_VF_RESV_STRATEGY_MINIMAL   1
1132 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC    2
1133         void                    *hwrm_cmd_req_addr[4];
1134         dma_addr_t              hwrm_cmd_req_dma_addr[4];
1135         struct bnxt_vf_info     *vf;
1136 };
1137
1138 struct bnxt_ntuple_filter {
1139         struct hlist_node       hash;
1140         u8                      dst_mac_addr[ETH_ALEN];
1141         u8                      src_mac_addr[ETH_ALEN];
1142         struct flow_keys        fkeys;
1143         __le64                  filter_id;
1144         u16                     sw_id;
1145         u8                      l2_fltr_idx;
1146         u16                     rxq;
1147         u32                     flow_id;
1148         unsigned long           state;
1149 #define BNXT_FLTR_VALID         0
1150 #define BNXT_FLTR_UPDATE        1
1151 };
1152
1153 struct bnxt_link_info {
1154         u8                      phy_type;
1155         u8                      media_type;
1156         u8                      transceiver;
1157         u8                      phy_addr;
1158         u8                      phy_link_status;
1159 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
1160 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
1161 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
1162         u8                      wire_speed;
1163         u8                      phy_state;
1164 #define BNXT_PHY_STATE_ENABLED          0
1165 #define BNXT_PHY_STATE_DISABLED         1
1166
1167         u8                      link_up;
1168         u8                      duplex;
1169 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1170 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1171         u8                      pause;
1172 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
1173 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
1174 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1175                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
1176         u8                      lp_pause;
1177         u8                      auto_pause_setting;
1178         u8                      force_pause_setting;
1179         u8                      duplex_setting;
1180         u8                      auto_mode;
1181 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
1182                                  (mode) <= BNXT_LINK_AUTO_MSK)
1183 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1184 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1185 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1186 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1187 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1188 #define PHY_VER_LEN             3
1189         u8                      phy_ver[PHY_VER_LEN];
1190         u16                     link_speed;
1191 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1192 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1193 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1194 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1195 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1196 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1197 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1198 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1199 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1200 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1201 #define BNXT_LINK_SPEED_200GB   PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1202         u16                     support_speeds;
1203         u16                     support_pam4_speeds;
1204         u16                     auto_link_speeds;       /* fw adv setting */
1205 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1206 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1207 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1208 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1209 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1210 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1211 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1212 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1213 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1214 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1215         u16                     auto_pam4_link_speeds;
1216 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1217 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1218 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1219         u16                     support_auto_speeds;
1220         u16                     support_pam4_auto_speeds;
1221         u16                     lp_auto_link_speeds;
1222         u16                     lp_auto_pam4_link_speeds;
1223         u16                     force_link_speed;
1224         u16                     force_pam4_link_speed;
1225         u32                     preemphasis;
1226         u8                      module_status;
1227         u8                      active_fec_sig_mode;
1228         u16                     fec_cfg;
1229 #define BNXT_FEC_NONE           PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1230 #define BNXT_FEC_AUTONEG_CAP    PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1231 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1232 #define BNXT_FEC_ENC_BASE_R_CAP \
1233         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1234 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1235 #define BNXT_FEC_ENC_RS_CAP     \
1236         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1237 #define BNXT_FEC_ENC_LLRS_CAP   \
1238         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |   \
1239          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1240 #define BNXT_FEC_ENC_RS         \
1241         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |      \
1242          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |     \
1243          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1244 #define BNXT_FEC_ENC_LLRS       \
1245         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |     \
1246          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1247
1248         /* copy of requested setting from ethtool cmd */
1249         u8                      autoneg;
1250 #define BNXT_AUTONEG_SPEED              1
1251 #define BNXT_AUTONEG_FLOW_CTRL          2
1252         u8                      req_signal_mode;
1253 #define BNXT_SIG_MODE_NRZ       PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1254 #define BNXT_SIG_MODE_PAM4      PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1255         u8                      req_duplex;
1256         u8                      req_flow_ctrl;
1257         u16                     req_link_speed;
1258         u16                     advertising;    /* user adv setting */
1259         u16                     advertising_pam4;
1260         bool                    force_link_chng;
1261
1262         bool                    phy_retry;
1263         unsigned long           phy_retry_expires;
1264
1265         /* a copy of phy_qcfg output used to report link
1266          * info to VF
1267          */
1268         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1269 };
1270
1271 #define BNXT_FEC_RS544_ON                                       \
1272          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |         \
1273           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1274
1275 #define BNXT_FEC_RS544_OFF                                      \
1276          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |        \
1277           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1278
1279 #define BNXT_FEC_RS272_ON                                       \
1280          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |         \
1281           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1282
1283 #define BNXT_FEC_RS272_OFF                                      \
1284          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |        \
1285           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1286
1287 #define BNXT_PAM4_SUPPORTED(link_info)                          \
1288         ((link_info)->support_pam4_speeds)
1289
1290 #define BNXT_FEC_RS_ON(link_info)                               \
1291         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1292          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1293          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1294           (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1295
1296 #define BNXT_FEC_LLRS_ON                                        \
1297         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1298          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1299          BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1300
1301 #define BNXT_FEC_RS_OFF(link_info)                              \
1302         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |          \
1303          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1304           (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1305
1306 #define BNXT_FEC_BASE_R_ON(link_info)                           \
1307         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |           \
1308          BNXT_FEC_RS_OFF(link_info))
1309
1310 #define BNXT_FEC_ALL_OFF(link_info)                             \
1311         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1312          BNXT_FEC_RS_OFF(link_info))
1313
1314 #define BNXT_MAX_QUEUE  8
1315
1316 struct bnxt_queue_info {
1317         u8      queue_id;
1318         u8      queue_profile;
1319 };
1320
1321 #define BNXT_MAX_LED                    4
1322
1323 struct bnxt_led_info {
1324         u8      led_id;
1325         u8      led_type;
1326         u8      led_group_id;
1327         u8      unused;
1328         __le16  led_state_caps;
1329 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
1330         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1331
1332         __le16  led_color_caps;
1333 };
1334
1335 #define BNXT_MAX_TEST   8
1336
1337 struct bnxt_test_info {
1338         u8 offline_mask;
1339         u8 flags;
1340 #define BNXT_TEST_FL_EXT_LPBK           0x1
1341 #define BNXT_TEST_FL_AN_PHY_LPBK        0x2
1342         u16 timeout;
1343         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1344 };
1345
1346 #define CHIMP_REG_VIEW_ADDR                             \
1347         ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1348
1349 #define BNXT_GRCPF_REG_CHIMP_COMM               0x0
1350 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER       0x100
1351 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT          0x400
1352 #define BNXT_CAG_REG_LEGACY_INT_STATUS          0x4014
1353 #define BNXT_CAG_REG_BASE                       0x300000
1354
1355 #define BNXT_GRCPF_REG_KONG_COMM                0xA00
1356 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER        0xB00
1357
1358 #define BNXT_GRC_BASE_MASK                      0xfffff000
1359 #define BNXT_GRC_OFFSET_MASK                    0x00000ffc
1360
1361 struct bnxt_tc_flow_stats {
1362         u64             packets;
1363         u64             bytes;
1364 };
1365
1366 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1367 struct bnxt_flower_indr_block_cb_priv {
1368         struct net_device *tunnel_netdev;
1369         struct bnxt *bp;
1370         struct list_head list;
1371 };
1372 #endif
1373
1374 struct bnxt_tc_info {
1375         bool                            enabled;
1376
1377         /* hash table to store TC offloaded flows */
1378         struct rhashtable               flow_table;
1379         struct rhashtable_params        flow_ht_params;
1380
1381         /* hash table to store L2 keys of TC flows */
1382         struct rhashtable               l2_table;
1383         struct rhashtable_params        l2_ht_params;
1384         /* hash table to store L2 keys for TC tunnel decap */
1385         struct rhashtable               decap_l2_table;
1386         struct rhashtable_params        decap_l2_ht_params;
1387         /* hash table to store tunnel decap entries */
1388         struct rhashtable               decap_table;
1389         struct rhashtable_params        decap_ht_params;
1390         /* hash table to store tunnel encap entries */
1391         struct rhashtable               encap_table;
1392         struct rhashtable_params        encap_ht_params;
1393
1394         /* lock to atomically add/del an l2 node when a flow is
1395          * added or deleted.
1396          */
1397         struct mutex                    lock;
1398
1399         /* Fields used for batching stats query */
1400         struct rhashtable_iter          iter;
1401 #define BNXT_FLOW_STATS_BATCH_MAX       10
1402         struct bnxt_tc_stats_batch {
1403                 void                      *flow_node;
1404                 struct bnxt_tc_flow_stats hw_stats;
1405         } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1406
1407         /* Stat counter mask (width) */
1408         u64                             bytes_mask;
1409         u64                             packets_mask;
1410 };
1411
1412 struct bnxt_vf_rep_stats {
1413         u64                     packets;
1414         u64                     bytes;
1415         u64                     dropped;
1416 };
1417
1418 struct bnxt_vf_rep {
1419         struct bnxt                     *bp;
1420         struct net_device               *dev;
1421         struct metadata_dst             *dst;
1422         u16                             vf_idx;
1423         u16                             tx_cfa_action;
1424         u16                             rx_cfa_code;
1425
1426         struct bnxt_vf_rep_stats        rx_stats;
1427         struct bnxt_vf_rep_stats        tx_stats;
1428 };
1429
1430 #define PTU_PTE_VALID             0x1UL
1431 #define PTU_PTE_LAST              0x2UL
1432 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1433
1434 #define MAX_CTX_PAGES   (BNXT_PAGE_SIZE / 8)
1435 #define MAX_CTX_TOTAL_PAGES     (MAX_CTX_PAGES * MAX_CTX_PAGES)
1436
1437 struct bnxt_ctx_pg_info {
1438         u32             entries;
1439         u32             nr_pages;
1440         void            *ctx_pg_arr[MAX_CTX_PAGES];
1441         dma_addr_t      ctx_dma_arr[MAX_CTX_PAGES];
1442         struct bnxt_ring_mem_info ring_mem;
1443         struct bnxt_ctx_pg_info **ctx_pg_tbl;
1444 };
1445
1446 #define BNXT_MAX_TQM_SP_RINGS           1
1447 #define BNXT_MAX_TQM_FP_RINGS           8
1448 #define BNXT_MAX_TQM_RINGS              \
1449         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1450
1451 #define BNXT_SET_CTX_PAGE_ATTR(attr)                                    \
1452 do {                                                                    \
1453         if (BNXT_PAGE_SIZE == 0x2000)                                   \
1454                 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;    \
1455         else if (BNXT_PAGE_SIZE == 0x10000)                             \
1456                 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;   \
1457         else                                                            \
1458                 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;    \
1459 } while (0)
1460
1461 struct bnxt_ctx_mem_info {
1462         u32     qp_max_entries;
1463         u16     qp_min_qp1_entries;
1464         u16     qp_max_l2_entries;
1465         u16     qp_entry_size;
1466         u16     srq_max_l2_entries;
1467         u32     srq_max_entries;
1468         u16     srq_entry_size;
1469         u16     cq_max_l2_entries;
1470         u32     cq_max_entries;
1471         u16     cq_entry_size;
1472         u16     vnic_max_vnic_entries;
1473         u16     vnic_max_ring_table_entries;
1474         u16     vnic_entry_size;
1475         u32     stat_max_entries;
1476         u16     stat_entry_size;
1477         u16     tqm_entry_size;
1478         u32     tqm_min_entries_per_ring;
1479         u32     tqm_max_entries_per_ring;
1480         u32     mrav_max_entries;
1481         u16     mrav_entry_size;
1482         u16     tim_entry_size;
1483         u32     tim_max_entries;
1484         u16     mrav_num_entries_units;
1485         u8      tqm_entries_multiple;
1486         u8      ctx_kind_initializer;
1487         u8      tqm_fp_rings_count;
1488
1489         u32     flags;
1490         #define BNXT_CTX_FLAG_INITED    0x01
1491
1492         struct bnxt_ctx_pg_info qp_mem;
1493         struct bnxt_ctx_pg_info srq_mem;
1494         struct bnxt_ctx_pg_info cq_mem;
1495         struct bnxt_ctx_pg_info vnic_mem;
1496         struct bnxt_ctx_pg_info stat_mem;
1497         struct bnxt_ctx_pg_info mrav_mem;
1498         struct bnxt_ctx_pg_info tim_mem;
1499         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1500 };
1501
1502 struct bnxt_fw_health {
1503         u32 flags;
1504         u32 polling_dsecs;
1505         u32 master_func_wait_dsecs;
1506         u32 normal_func_wait_dsecs;
1507         u32 post_reset_wait_dsecs;
1508         u32 post_reset_max_wait_dsecs;
1509         u32 regs[4];
1510         u32 mapped_regs[4];
1511 #define BNXT_FW_HEALTH_REG              0
1512 #define BNXT_FW_HEARTBEAT_REG           1
1513 #define BNXT_FW_RESET_CNT_REG           2
1514 #define BNXT_FW_RESET_INPROG_REG        3
1515         u32 fw_reset_inprog_reg_mask;
1516         u32 last_fw_heartbeat;
1517         u32 last_fw_reset_cnt;
1518         u8 enabled:1;
1519         u8 master:1;
1520         u8 fatal:1;
1521         u8 status_reliable:1;
1522         u8 tmr_multiplier;
1523         u8 tmr_counter;
1524         u8 fw_reset_seq_cnt;
1525         u32 fw_reset_seq_regs[16];
1526         u32 fw_reset_seq_vals[16];
1527         u32 fw_reset_seq_delay_msec[16];
1528         struct devlink_health_reporter  *fw_reporter;
1529         struct devlink_health_reporter *fw_reset_reporter;
1530         struct devlink_health_reporter *fw_fatal_reporter;
1531 };
1532
1533 struct bnxt_fw_reporter_ctx {
1534         unsigned long sp_event;
1535 };
1536
1537 #define BNXT_FW_HEALTH_REG_TYPE_MASK    3
1538 #define BNXT_FW_HEALTH_REG_TYPE_CFG     0
1539 #define BNXT_FW_HEALTH_REG_TYPE_GRC     1
1540 #define BNXT_FW_HEALTH_REG_TYPE_BAR0    2
1541 #define BNXT_FW_HEALTH_REG_TYPE_BAR1    3
1542
1543 #define BNXT_FW_HEALTH_REG_TYPE(reg)    ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1544 #define BNXT_FW_HEALTH_REG_OFF(reg)     ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1545
1546 #define BNXT_FW_HEALTH_WIN_BASE         0x3000
1547 #define BNXT_FW_HEALTH_WIN_MAP_OFF      8
1548
1549 #define BNXT_FW_HEALTH_WIN_OFF(reg)     (BNXT_FW_HEALTH_WIN_BASE +      \
1550                                          ((reg) & BNXT_GRC_OFFSET_MASK))
1551
1552 #define BNXT_FW_STATUS_HEALTHY          0x8000
1553 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
1554
1555 struct bnxt {
1556         void __iomem            *bar0;
1557         void __iomem            *bar1;
1558         void __iomem            *bar2;
1559
1560         u32                     reg_base;
1561         u16                     chip_num;
1562 #define CHIP_NUM_57301          0x16c8
1563 #define CHIP_NUM_57302          0x16c9
1564 #define CHIP_NUM_57304          0x16ca
1565 #define CHIP_NUM_58700          0x16cd
1566 #define CHIP_NUM_57402          0x16d0
1567 #define CHIP_NUM_57404          0x16d1
1568 #define CHIP_NUM_57406          0x16d2
1569 #define CHIP_NUM_57407          0x16d5
1570
1571 #define CHIP_NUM_57311          0x16ce
1572 #define CHIP_NUM_57312          0x16cf
1573 #define CHIP_NUM_57314          0x16df
1574 #define CHIP_NUM_57317          0x16e0
1575 #define CHIP_NUM_57412          0x16d6
1576 #define CHIP_NUM_57414          0x16d7
1577 #define CHIP_NUM_57416          0x16d8
1578 #define CHIP_NUM_57417          0x16d9
1579 #define CHIP_NUM_57412L         0x16da
1580 #define CHIP_NUM_57414L         0x16db
1581
1582 #define CHIP_NUM_5745X          0xd730
1583 #define CHIP_NUM_57452          0xc452
1584 #define CHIP_NUM_57454          0xc454
1585
1586 #define CHIP_NUM_57508          0x1750
1587 #define CHIP_NUM_57504          0x1751
1588 #define CHIP_NUM_57502          0x1752
1589
1590 #define CHIP_NUM_58802          0xd802
1591 #define CHIP_NUM_58804          0xd804
1592 #define CHIP_NUM_58808          0xd808
1593
1594         u8                      chip_rev;
1595
1596 #define CHIP_NUM_58818          0xd818
1597
1598 #define BNXT_CHIP_NUM_5730X(chip_num)           \
1599         ((chip_num) >= CHIP_NUM_57301 &&        \
1600          (chip_num) <= CHIP_NUM_57304)
1601
1602 #define BNXT_CHIP_NUM_5740X(chip_num)           \
1603         (((chip_num) >= CHIP_NUM_57402 &&       \
1604           (chip_num) <= CHIP_NUM_57406) ||      \
1605          (chip_num) == CHIP_NUM_57407)
1606
1607 #define BNXT_CHIP_NUM_5731X(chip_num)           \
1608         ((chip_num) == CHIP_NUM_57311 ||        \
1609          (chip_num) == CHIP_NUM_57312 ||        \
1610          (chip_num) == CHIP_NUM_57314 ||        \
1611          (chip_num) == CHIP_NUM_57317)
1612
1613 #define BNXT_CHIP_NUM_5741X(chip_num)           \
1614         ((chip_num) >= CHIP_NUM_57412 &&        \
1615          (chip_num) <= CHIP_NUM_57414L)
1616
1617 #define BNXT_CHIP_NUM_58700(chip_num)           \
1618          ((chip_num) == CHIP_NUM_58700)
1619
1620 #define BNXT_CHIP_NUM_5745X(chip_num)           \
1621         ((chip_num) == CHIP_NUM_5745X ||        \
1622          (chip_num) == CHIP_NUM_57452 ||        \
1623          (chip_num) == CHIP_NUM_57454)
1624
1625
1626 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
1627         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1628
1629 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
1630         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1631
1632 #define BNXT_CHIP_NUM_588XX(chip_num)           \
1633         ((chip_num) == CHIP_NUM_58802 ||        \
1634          (chip_num) == CHIP_NUM_58804 ||        \
1635          (chip_num) == CHIP_NUM_58808)
1636
1637 #define BNXT_VPD_FLD_LEN        32
1638         char                    board_partno[BNXT_VPD_FLD_LEN];
1639         char                    board_serialno[BNXT_VPD_FLD_LEN];
1640
1641         struct net_device       *dev;
1642         struct pci_dev          *pdev;
1643
1644         atomic_t                intr_sem;
1645
1646         u32                     flags;
1647         #define BNXT_FLAG_CHIP_P5       0x1
1648         #define BNXT_FLAG_VF            0x2
1649         #define BNXT_FLAG_LRO           0x4
1650 #ifdef CONFIG_INET
1651         #define BNXT_FLAG_GRO           0x8
1652 #else
1653         /* Cannot support hardware GRO if CONFIG_INET is not set */
1654         #define BNXT_FLAG_GRO           0x0
1655 #endif
1656         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1657         #define BNXT_FLAG_JUMBO         0x10
1658         #define BNXT_FLAG_STRIP_VLAN    0x20
1659         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1660                                          BNXT_FLAG_LRO)
1661         #define BNXT_FLAG_USING_MSIX    0x40
1662         #define BNXT_FLAG_MSIX_CAP      0x80
1663         #define BNXT_FLAG_RFS           0x100
1664         #define BNXT_FLAG_SHARED_RINGS  0x200
1665         #define BNXT_FLAG_PORT_STATS    0x400
1666         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1667         #define BNXT_FLAG_EEE_CAP       0x1000
1668         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1669         #define BNXT_FLAG_WOL_CAP       0x4000
1670         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1671         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1672         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1673                                          BNXT_FLAG_ROCEV2_CAP)
1674         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1675         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1676         #define BNXT_FLAG_CHIP_SR2      0x80000
1677         #define BNXT_FLAG_MULTI_HOST    0x100000
1678         #define BNXT_FLAG_DSN_VALID     0x200000
1679         #define BNXT_FLAG_DOUBLE_DB     0x400000
1680         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1681         #define BNXT_FLAG_DIM           0x2000000
1682         #define BNXT_FLAG_ROCE_MIRROR_CAP       0x4000000
1683         #define BNXT_FLAG_PORT_STATS_EXT        0x10000000
1684
1685         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1686                                             BNXT_FLAG_RFS |             \
1687                                             BNXT_FLAG_STRIP_VLAN)
1688
1689 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1690 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1691 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1692 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1693 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1694 #define BNXT_PHY_CFG_ABLE(bp)   ((BNXT_SINGLE_PF(bp) ||                 \
1695                                   ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) && \
1696                                  (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1697 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1698 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1699 #define BNXT_SUPPORTS_TPA(bp)   (!BNXT_CHIP_TYPE_NITRO_A0(bp) &&        \
1700                                  (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1701                                   (bp)->max_tpa_v2) && !is_kdump_kernel())
1702
1703 #define BNXT_CHIP_SR2(bp)                       \
1704         ((bp)->chip_num == CHIP_NUM_58818)
1705
1706 #define BNXT_CHIP_P5_THOR(bp)                   \
1707         ((bp)->chip_num == CHIP_NUM_57508 ||    \
1708          (bp)->chip_num == CHIP_NUM_57504 ||    \
1709          (bp)->chip_num == CHIP_NUM_57502)
1710
1711 /* Chip class phase 5 */
1712 #define BNXT_CHIP_P5(bp)                        \
1713         (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1714
1715 /* Chip class phase 4.x */
1716 #define BNXT_CHIP_P4(bp)                        \
1717         (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1718          BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1719          BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1720          (BNXT_CHIP_NUM_58700((bp)->chip_num) &&        \
1721           !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1722
1723 #define BNXT_CHIP_P4_PLUS(bp)                   \
1724         (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1725
1726         struct bnxt_en_dev      *edev;
1727         struct bnxt_en_dev *    (*ulp_probe)(struct net_device *);
1728
1729         struct bnxt_napi        **bnapi;
1730
1731         struct bnxt_rx_ring_info        *rx_ring;
1732         struct bnxt_tx_ring_info        *tx_ring;
1733         u16                     *tx_ring_map;
1734
1735         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1736                                             struct sk_buff *);
1737
1738         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1739                                                struct bnxt_rx_ring_info *,
1740                                                u16, void *, u8 *, dma_addr_t,
1741                                                unsigned int);
1742
1743         u16                     max_tpa_v2;
1744         u16                     max_tpa;
1745         u32                     rx_buf_size;
1746         u32                     rx_buf_use_size;        /* useable size */
1747         u16                     rx_offset;
1748         u16                     rx_dma_offset;
1749         enum dma_data_direction rx_dir;
1750         u32                     rx_ring_size;
1751         u32                     rx_agg_ring_size;
1752         u32                     rx_copy_thresh;
1753         u32                     rx_ring_mask;
1754         u32                     rx_agg_ring_mask;
1755         int                     rx_nr_pages;
1756         int                     rx_agg_nr_pages;
1757         int                     rx_nr_rings;
1758         int                     rsscos_nr_ctxs;
1759
1760         u32                     tx_ring_size;
1761         u32                     tx_ring_mask;
1762         int                     tx_nr_pages;
1763         int                     tx_nr_rings;
1764         int                     tx_nr_rings_per_tc;
1765         int                     tx_nr_rings_xdp;
1766
1767         int                     tx_wake_thresh;
1768         int                     tx_push_thresh;
1769         int                     tx_push_size;
1770
1771         u32                     cp_ring_size;
1772         u32                     cp_ring_mask;
1773         u32                     cp_bit;
1774         int                     cp_nr_pages;
1775         int                     cp_nr_rings;
1776
1777         /* grp_info indexed by completion ring index */
1778         struct bnxt_ring_grp_info       *grp_info;
1779         struct bnxt_vnic_info   *vnic_info;
1780         int                     nr_vnics;
1781         u16                     *rss_indir_tbl;
1782         u16                     rss_indir_tbl_entries;
1783         u32                     rss_hash_cfg;
1784
1785         u16                     max_mtu;
1786         u8                      max_tc;
1787         u8                      max_lltc;       /* lossless TCs */
1788         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1789         u8                      tc_to_qidx[BNXT_MAX_QUEUE];
1790         u8                      q_ids[BNXT_MAX_QUEUE];
1791         u8                      max_q;
1792
1793         unsigned int            current_interval;
1794 #define BNXT_TIMER_INTERVAL     HZ
1795
1796         struct timer_list       timer;
1797
1798         unsigned long           state;
1799 #define BNXT_STATE_OPEN         0
1800 #define BNXT_STATE_IN_SP_TASK   1
1801 #define BNXT_STATE_READ_STATS   2
1802 #define BNXT_STATE_FW_RESET_DET 3
1803 #define BNXT_STATE_IN_FW_RESET  4
1804 #define BNXT_STATE_ABORT_ERR    5
1805 #define BNXT_STATE_FW_FATAL_COND        6
1806 #define BNXT_STATE_DRV_REGISTERED       7
1807 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN        8
1808
1809 #define BNXT_NO_FW_ACCESS(bp)                                   \
1810         (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||    \
1811          pci_channel_offline((bp)->pdev))
1812
1813         struct bnxt_irq *irq_tbl;
1814         int                     total_irqs;
1815         u8                      mac_addr[ETH_ALEN];
1816
1817 #ifdef CONFIG_BNXT_DCB
1818         struct ieee_pfc         *ieee_pfc;
1819         struct ieee_ets         *ieee_ets;
1820         u8                      dcbx_cap;
1821         u8                      default_pri;
1822         u8                      max_dscp_value;
1823 #endif /* CONFIG_BNXT_DCB */
1824
1825         u32                     msg_enable;
1826
1827         u32                     fw_cap;
1828         #define BNXT_FW_CAP_SHORT_CMD                   0x00000001
1829         #define BNXT_FW_CAP_LLDP_AGENT                  0x00000002
1830         #define BNXT_FW_CAP_DCBX_AGENT                  0x00000004
1831         #define BNXT_FW_CAP_NEW_RM                      0x00000008
1832         #define BNXT_FW_CAP_IF_CHANGE                   0x00000010
1833         #define BNXT_FW_CAP_KONG_MB_CHNL                0x00000080
1834         #define BNXT_FW_CAP_OVS_64BIT_HANDLE            0x00000400
1835         #define BNXT_FW_CAP_TRUSTED_VF                  0x00000800
1836         #define BNXT_FW_CAP_ERROR_RECOVERY              0x00002000
1837         #define BNXT_FW_CAP_PKG_VER                     0x00004000
1838         #define BNXT_FW_CAP_CFA_ADV_FLOW                0x00008000
1839         #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2     0x00010000
1840         #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED        0x00020000
1841         #define BNXT_FW_CAP_EXT_STATS_SUPPORTED         0x00040000
1842         #define BNXT_FW_CAP_ERR_RECOVER_RELOAD          0x00100000
1843         #define BNXT_FW_CAP_HOT_RESET                   0x00200000
1844         #define BNXT_FW_CAP_SHARED_PORT_CFG             0x00400000
1845         #define BNXT_FW_CAP_VLAN_RX_STRIP               0x01000000
1846         #define BNXT_FW_CAP_VLAN_TX_INSERT              0x02000000
1847         #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED      0x04000000
1848         #define BNXT_FW_CAP_PORT_STATS_NO_RESET         0x10000000
1849         #define BNXT_FW_CAP_RING_MONITOR                0x40000000
1850
1851 #define BNXT_NEW_RM(bp)         ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1852         u32                     hwrm_spec_code;
1853         u16                     hwrm_cmd_seq;
1854         u16                     hwrm_cmd_kong_seq;
1855         u16                     hwrm_intr_seq_id;
1856         void                    *hwrm_short_cmd_req_addr;
1857         dma_addr_t              hwrm_short_cmd_req_dma_addr;
1858         void                    *hwrm_cmd_resp_addr;
1859         dma_addr_t              hwrm_cmd_resp_dma_addr;
1860         void                    *hwrm_cmd_kong_resp_addr;
1861         dma_addr_t              hwrm_cmd_kong_resp_dma_addr;
1862
1863         struct rtnl_link_stats64        net_stats_prev;
1864         struct bnxt_stats_mem   port_stats;
1865         struct bnxt_stats_mem   rx_port_stats_ext;
1866         struct bnxt_stats_mem   tx_port_stats_ext;
1867         u16                     fw_rx_stats_ext_size;
1868         u16                     fw_tx_stats_ext_size;
1869         u16                     hw_ring_stats_size;
1870         u8                      pri2cos_idx[8];
1871         u8                      pri2cos_valid;
1872
1873         u16                     hwrm_max_req_len;
1874         u16                     hwrm_max_ext_req_len;
1875         int                     hwrm_cmd_timeout;
1876         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1877         struct hwrm_ver_get_output      ver_resp;
1878 #define FW_VER_STR_LEN          32
1879 #define BC_HWRM_STR_LEN         21
1880 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1881         char                    fw_ver_str[FW_VER_STR_LEN];
1882         char                    hwrm_ver_supp[FW_VER_STR_LEN];
1883         char                    nvm_cfg_ver[FW_VER_STR_LEN];
1884         u64                     fw_ver_code;
1885 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)                    \
1886         ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
1887 #define BNXT_FW_MAJ(bp)         ((bp)->fw_ver_code >> 48)
1888
1889         u16                     vxlan_fw_dst_port_id;
1890         u16                     nge_fw_dst_port_id;
1891         u8                      port_partition_type;
1892         u8                      port_count;
1893         u16                     br_mode;
1894
1895         struct bnxt_coal_cap    coal_cap;
1896         struct bnxt_coal        rx_coal;
1897         struct bnxt_coal        tx_coal;
1898
1899         u32                     stats_coal_ticks;
1900 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1901 #define BNXT_MIN_STATS_COAL_TICKS         250000
1902 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1903
1904         struct work_struct      sp_task;
1905         unsigned long           sp_event;
1906 #define BNXT_RX_MASK_SP_EVENT           0
1907 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1908 #define BNXT_LINK_CHNG_SP_EVENT         2
1909 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1910 #define BNXT_RESET_TASK_SP_EVENT        6
1911 #define BNXT_RST_RING_SP_EVENT          7
1912 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1913 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1914 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1915 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1916 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1917 #define BNXT_FLOW_STATS_SP_EVENT        15
1918 #define BNXT_UPDATE_PHY_SP_EVENT        16
1919 #define BNXT_RING_COAL_NOW_SP_EVENT     17
1920 #define BNXT_FW_RESET_NOTIFY_SP_EVENT   18
1921 #define BNXT_FW_EXCEPTION_SP_EVENT      19
1922 #define BNXT_LINK_CFG_CHANGE_SP_EVENT   21
1923
1924         struct delayed_work     fw_reset_task;
1925         int                     fw_reset_state;
1926 #define BNXT_FW_RESET_STATE_POLL_VF     1
1927 #define BNXT_FW_RESET_STATE_RESET_FW    2
1928 #define BNXT_FW_RESET_STATE_ENABLE_DEV  3
1929 #define BNXT_FW_RESET_STATE_POLL_FW     4
1930 #define BNXT_FW_RESET_STATE_OPENING     5
1931 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN        6
1932
1933         u16                     fw_reset_min_dsecs;
1934 #define BNXT_DFLT_FW_RST_MIN_DSECS      20
1935         u16                     fw_reset_max_dsecs;
1936 #define BNXT_DFLT_FW_RST_MAX_DSECS      60
1937         unsigned long           fw_reset_timestamp;
1938
1939         struct bnxt_fw_health   *fw_health;
1940
1941         struct bnxt_hw_resc     hw_resc;
1942         struct bnxt_pf_info     pf;
1943         struct bnxt_ctx_mem_info        *ctx;
1944 #ifdef CONFIG_BNXT_SRIOV
1945         int                     nr_vfs;
1946         struct bnxt_vf_info     vf;
1947         wait_queue_head_t       sriov_cfg_wait;
1948         bool                    sriov_cfg;
1949 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1950
1951         /* lock to protect VF-rep creation/cleanup via
1952          * multiple paths such as ->sriov_configure() and
1953          * devlink ->eswitch_mode_set()
1954          */
1955         struct mutex            sriov_lock;
1956 #endif
1957
1958 #if BITS_PER_LONG == 32
1959         /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1960         spinlock_t              db_lock;
1961 #endif
1962         int                     db_size;
1963
1964 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1965 #define BNXT_NTP_FLTR_HASH_SIZE 512
1966 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1967         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1968         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1969
1970         unsigned long           *ntp_fltr_bmap;
1971         int                     ntp_fltr_count;
1972
1973         /* To protect link related settings during link changes and
1974          * ethtool settings changes.
1975          */
1976         struct mutex            link_lock;
1977         struct bnxt_link_info   link_info;
1978         struct ethtool_eee      eee;
1979         u32                     lpi_tmr_lo;
1980         u32                     lpi_tmr_hi;
1981
1982         u8                      num_tests;
1983         struct bnxt_test_info   *test_info;
1984
1985         u8                      wol_filter_id;
1986         u8                      wol;
1987
1988         u8                      num_leds;
1989         struct bnxt_led_info    leds[BNXT_MAX_LED];
1990         u16                     dump_flag;
1991 #define BNXT_DUMP_LIVE          0
1992 #define BNXT_DUMP_CRASH         1
1993
1994         struct bpf_prog         *xdp_prog;
1995
1996         /* devlink interface and vf-rep structs */
1997         struct devlink          *dl;
1998         struct devlink_port     dl_port;
1999         enum devlink_eswitch_mode eswitch_mode;
2000         struct bnxt_vf_rep      **vf_reps; /* array of vf-rep ptrs */
2001         u16                     *cfa_code_map; /* cfa_code -> vf_idx map */
2002         u8                      dsn[8];
2003         struct bnxt_tc_info     *tc_info;
2004         struct list_head        tc_indr_block_list;
2005         struct dentry           *debugfs_pdev;
2006         struct device           *hwmon_dev;
2007 };
2008
2009 #define BNXT_NUM_RX_RING_STATS                  8
2010 #define BNXT_NUM_TX_RING_STATS                  8
2011 #define BNXT_NUM_TPA_RING_STATS                 4
2012 #define BNXT_NUM_TPA_RING_STATS_P5              5
2013 #define BNXT_NUM_TPA_RING_STATS_P5_SR2          6
2014
2015 #define BNXT_RING_STATS_SIZE_P5                                 \
2016         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2017           BNXT_NUM_TPA_RING_STATS_P5) * 8)
2018
2019 #define BNXT_RING_STATS_SIZE_P5_SR2                             \
2020         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2021           BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2022
2023 #define BNXT_GET_RING_STATS64(sw, counter)              \
2024         (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2025
2026 #define BNXT_GET_RX_PORT_STATS64(sw, counter)           \
2027         (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2028
2029 #define BNXT_GET_TX_PORT_STATS64(sw, counter)           \
2030         (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2031
2032 #define BNXT_PORT_STATS_SIZE                            \
2033         (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2034
2035 #define BNXT_TX_PORT_STATS_BYTE_OFFSET                  \
2036         (sizeof(struct rx_port_stats) + 512)
2037
2038 #define BNXT_RX_STATS_OFFSET(counter)                   \
2039         (offsetof(struct rx_port_stats, counter) / 8)
2040
2041 #define BNXT_TX_STATS_OFFSET(counter)                   \
2042         ((offsetof(struct tx_port_stats, counter) +     \
2043           BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2044
2045 #define BNXT_RX_STATS_EXT_OFFSET(counter)               \
2046         (offsetof(struct rx_port_stats_ext, counter) / 8)
2047
2048 #define BNXT_TX_STATS_EXT_OFFSET(counter)               \
2049         (offsetof(struct tx_port_stats_ext, counter) / 8)
2050
2051 #define BNXT_HW_FEATURE_VLAN_ALL_RX                             \
2052         (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2053 #define BNXT_HW_FEATURE_VLAN_ALL_TX                             \
2054         (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2055
2056 #define I2C_DEV_ADDR_A0                         0xa0
2057 #define I2C_DEV_ADDR_A2                         0xa2
2058 #define SFF_DIAG_SUPPORT_OFFSET                 0x5c
2059 #define SFF_MODULE_ID_SFP                       0x3
2060 #define SFF_MODULE_ID_QSFP                      0xc
2061 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
2062 #define SFF_MODULE_ID_QSFP28                    0x11
2063 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
2064
2065 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2066 {
2067         /* Tell compiler to fetch tx indices from memory. */
2068         barrier();
2069
2070         return bp->tx_ring_size -
2071                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2072 }
2073
2074 #if BITS_PER_LONG == 32
2075 #define writeq(val64, db)                       \
2076 do {                                            \
2077         spin_lock(&bp->db_lock);                \
2078         writel((val64) & 0xffffffff, db);       \
2079         writel((val64) >> 32, (db) + 4);        \
2080         spin_unlock(&bp->db_lock);              \
2081 } while (0)
2082
2083 #define writeq_relaxed writeq
2084 #endif
2085
2086 /* For TX and RX ring doorbells with no ordering guarantee*/
2087 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2088                                          struct bnxt_db_info *db, u32 idx)
2089 {
2090         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2091                 writeq_relaxed(db->db_key64 | idx, db->doorbell);
2092         } else {
2093                 u32 db_val = db->db_key32 | idx;
2094
2095                 writel_relaxed(db_val, db->doorbell);
2096                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2097                         writel_relaxed(db_val, db->doorbell);
2098         }
2099 }
2100
2101 /* For TX and RX ring doorbells */
2102 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2103                                  u32 idx)
2104 {
2105         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2106                 writeq(db->db_key64 | idx, db->doorbell);
2107         } else {
2108                 u32 db_val = db->db_key32 | idx;
2109
2110                 writel(db_val, db->doorbell);
2111                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2112                         writel(db_val, db->doorbell);
2113         }
2114 }
2115
2116 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
2117 {
2118         switch (req_type) {
2119         case HWRM_CFA_ENCAP_RECORD_ALLOC:
2120         case HWRM_CFA_ENCAP_RECORD_FREE:
2121         case HWRM_CFA_DECAP_FILTER_ALLOC:
2122         case HWRM_CFA_DECAP_FILTER_FREE:
2123         case HWRM_CFA_EM_FLOW_ALLOC:
2124         case HWRM_CFA_EM_FLOW_FREE:
2125         case HWRM_CFA_EM_FLOW_CFG:
2126         case HWRM_CFA_FLOW_ALLOC:
2127         case HWRM_CFA_FLOW_FREE:
2128         case HWRM_CFA_FLOW_INFO:
2129         case HWRM_CFA_FLOW_FLUSH:
2130         case HWRM_CFA_FLOW_STATS:
2131         case HWRM_CFA_METER_PROFILE_ALLOC:
2132         case HWRM_CFA_METER_PROFILE_FREE:
2133         case HWRM_CFA_METER_PROFILE_CFG:
2134         case HWRM_CFA_METER_INSTANCE_ALLOC:
2135         case HWRM_CFA_METER_INSTANCE_FREE:
2136                 return true;
2137         default:
2138                 return false;
2139         }
2140 }
2141
2142 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
2143 {
2144         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2145                 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
2146 }
2147
2148 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
2149 {
2150         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2151                 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
2152 }
2153
2154 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
2155 {
2156         if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
2157                 return bp->hwrm_cmd_kong_resp_addr;
2158         else
2159                 return bp->hwrm_cmd_resp_addr;
2160 }
2161
2162 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
2163 {
2164         u16 seq_id;
2165
2166         if (dst == BNXT_HWRM_CHNL_CHIMP)
2167                 seq_id = bp->hwrm_cmd_seq++;
2168         else
2169                 seq_id = bp->hwrm_cmd_kong_seq++;
2170         return seq_id;
2171 }
2172
2173 extern const u16 bnxt_lhint_arr[];
2174
2175 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2176                        u16 prod, gfp_t gfp);
2177 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2178 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2179 void bnxt_set_tpa_flags(struct bnxt *bp);
2180 void bnxt_set_ring_params(struct bnxt *);
2181 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2182 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
2183 int _hwrm_send_message(struct bnxt *, void *, u32, int);
2184 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
2185 int hwrm_send_message(struct bnxt *, void *, u32, int);
2186 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
2187 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2188                             int bmap_size, bool async_only);
2189 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2190 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2191 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2192 int bnxt_nq_rings_in_use(struct bnxt *bp);
2193 int bnxt_hwrm_set_coal(struct bnxt *);
2194 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2195 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2196 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2197 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2198 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2199 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2200 void bnxt_tx_disable(struct bnxt *bp);
2201 void bnxt_tx_enable(struct bnxt *bp);
2202 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2203 int bnxt_hwrm_set_pause(struct bnxt *);
2204 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2205 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2206 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2207 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2208 int bnxt_hwrm_fw_set_time(struct bnxt *);
2209 int bnxt_open_nic(struct bnxt *, bool, bool);
2210 int bnxt_half_open_nic(struct bnxt *bp);
2211 void bnxt_half_close_nic(struct bnxt *bp);
2212 int bnxt_close_nic(struct bnxt *, bool, bool);
2213 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2214                          u32 *reg_buf);
2215 void bnxt_fw_exception(struct bnxt *bp);
2216 void bnxt_fw_reset(struct bnxt *bp);
2217 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2218                      int tx_xdp);
2219 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2220 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2221 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2222 int bnxt_get_port_parent_id(struct net_device *dev,
2223                             struct netdev_phys_item_id *ppid);
2224 void bnxt_dim_work(struct work_struct *work);
2225 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2226
2227 #endif