1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.8.0"
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <net/devlink.h>
24 #include <net/dst_metadata.h>
25 #include <net/switchdev.h>
28 __le32 tx_bd_len_flags_type;
29 #define TX_BD_TYPE (0x3f << 0)
30 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
31 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
32 #define TX_BD_FLAGS_PACKET_END (1 << 6)
33 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
34 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
35 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
36 #define TX_BD_FLAGS_LHINT (3 << 13)
37 #define TX_BD_FLAGS_LHINT_SHIFT 13
38 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
39 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
40 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
41 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
42 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
43 #define TX_BD_LEN (0xffff << 16)
44 #define TX_BD_LEN_SHIFT 16
51 __le32 tx_bd_hsize_lflags;
52 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
53 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
54 #define TX_BD_FLAGS_NO_CRC (1 << 2)
55 #define TX_BD_FLAGS_STAMP (1 << 3)
56 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
57 #define TX_BD_FLAGS_LSO (1 << 5)
58 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
59 #define TX_BD_FLAGS_T_IPID (1 << 7)
60 #define TX_BD_HSIZE (0xff << 16)
61 #define TX_BD_HSIZE_SHIFT 16
64 __le32 tx_bd_cfa_action;
65 #define TX_BD_CFA_ACTION (0xffff << 16)
66 #define TX_BD_CFA_ACTION_SHIFT 16
68 __le32 tx_bd_cfa_meta;
69 #define TX_BD_CFA_META_MASK 0xfffffff
70 #define TX_BD_CFA_META_VID_MASK 0xfff
71 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
72 #define TX_BD_CFA_META_PRI_SHIFT 12
73 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
74 #define TX_BD_CFA_META_TPID_SHIFT 16
75 #define TX_BD_CFA_META_KEY (0xf << 28)
76 #define TX_BD_CFA_META_KEY_SHIFT 28
77 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
81 __le32 rx_bd_len_flags_type;
82 #define RX_BD_TYPE (0x3f << 0)
83 #define RX_BD_TYPE_RX_PACKET_BD 0x4
84 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
85 #define RX_BD_TYPE_RX_AGG_BD 0x6
86 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
87 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
88 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
89 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
90 #define RX_BD_FLAGS_SOP (1 << 6)
91 #define RX_BD_FLAGS_EOP (1 << 7)
92 #define RX_BD_FLAGS_BUFFERS (3 << 8)
93 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
94 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
95 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
96 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
97 #define RX_BD_LEN (0xffff << 16)
98 #define RX_BD_LEN_SHIFT 16
105 __le32 tx_cmp_flags_type;
106 #define CMP_TYPE (0x3f << 0)
107 #define CMP_TYPE_TX_L2_CMP 0
108 #define CMP_TYPE_RX_L2_CMP 17
109 #define CMP_TYPE_RX_AGG_CMP 18
110 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
111 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
112 #define CMP_TYPE_STATUS_CMP 32
113 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
114 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
115 #define CMP_TYPE_ERROR_STATUS 48
116 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
117 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
118 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
119 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
120 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
122 #define TX_CMP_FLAGS_ERROR (1 << 6)
123 #define TX_CMP_FLAGS_PUSH (1 << 7)
126 __le32 tx_cmp_errors_v;
127 #define TX_CMP_V (1 << 0)
128 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
129 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
130 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
131 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
132 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
133 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
134 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
135 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
136 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
138 __le32 tx_cmp_unsed_3;
142 __le32 rx_cmp_len_flags_type;
143 #define RX_CMP_CMP_TYPE (0x3f << 0)
144 #define RX_CMP_FLAGS_ERROR (1 << 6)
145 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
146 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
147 #define RX_CMP_FLAGS_UNUSED (1 << 11)
148 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
149 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
150 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
151 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
152 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
153 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
154 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
155 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
156 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
157 #define RX_CMP_LEN (0xffff << 16)
158 #define RX_CMP_LEN_SHIFT 16
161 __le32 rx_cmp_misc_v1;
162 #define RX_CMP_V1 (1 << 0)
163 #define RX_CMP_AGG_BUFS (0x1f << 1)
164 #define RX_CMP_AGG_BUFS_SHIFT 1
165 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
166 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
167 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
168 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
170 __le32 rx_cmp_rss_hash;
173 #define RX_CMP_HASH_VALID(rxcmp) \
174 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
176 #define RSS_PROFILE_ID_MASK 0x1f
178 #define RX_CMP_HASH_TYPE(rxcmp) \
179 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
180 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
183 __le32 rx_cmp_flags2;
184 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
185 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
186 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
187 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
188 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
189 __le32 rx_cmp_meta_data;
190 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
191 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
192 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
193 __le32 rx_cmp_cfa_code_errors_v2;
194 #define RX_CMP_V (1 << 0)
195 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
196 #define RX_CMPL_ERRORS_SFT 1
197 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
198 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
199 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
200 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
201 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
202 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
203 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
204 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
205 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
206 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
207 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
208 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
209 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
210 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
211 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
215 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
216 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
217 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
218 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
219 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
220 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
221 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
226 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
227 #define RX_CMPL_CFA_CODE_SFT 16
229 __le32 rx_cmp_unused3;
232 #define RX_CMP_L2_ERRORS \
233 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
235 #define RX_CMP_L4_CS_BITS \
236 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
238 #define RX_CMP_L4_CS_ERR_BITS \
239 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
241 #define RX_CMP_L4_CS_OK(rxcmp1) \
242 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
243 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
245 #define RX_CMP_ENCAP(rxcmp1) \
246 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
247 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
249 #define RX_CMP_CFA_CODE(rxcmpl1) \
250 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
251 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
254 __le32 rx_agg_cmp_len_flags_type;
255 #define RX_AGG_CMP_TYPE (0x3f << 0)
256 #define RX_AGG_CMP_LEN (0xffff << 16)
257 #define RX_AGG_CMP_LEN_SHIFT 16
258 u32 rx_agg_cmp_opaque;
260 #define RX_AGG_CMP_V (1 << 0)
261 __le32 rx_agg_cmp_unused;
264 struct rx_tpa_start_cmp {
265 __le32 rx_tpa_start_cmp_len_flags_type;
266 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
267 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
268 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
269 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
270 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
271 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
275 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
276 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
277 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
278 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
279 #define RX_TPA_START_CMP_LEN (0xffff << 16)
280 #define RX_TPA_START_CMP_LEN_SHIFT 16
282 u32 rx_tpa_start_cmp_opaque;
283 __le32 rx_tpa_start_cmp_misc_v1;
284 #define RX_TPA_START_CMP_V1 (0x1 << 0)
285 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
286 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
287 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
288 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
290 __le32 rx_tpa_start_cmp_rss_hash;
293 #define TPA_START_HASH_VALID(rx_tpa_start) \
294 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
295 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
297 #define TPA_START_HASH_TYPE(rx_tpa_start) \
298 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
299 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
300 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
302 #define TPA_START_AGG_ID(rx_tpa_start) \
303 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
304 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
306 struct rx_tpa_start_cmp_ext {
307 __le32 rx_tpa_start_cmp_flags2;
308 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
309 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
310 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
311 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
312 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
314 __le32 rx_tpa_start_cmp_metadata;
315 __le32 rx_tpa_start_cmp_cfa_code_v2;
316 #define RX_TPA_START_CMP_V2 (0x1 << 0)
317 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
318 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
319 __le32 rx_tpa_start_cmp_hdr_info;
322 #define TPA_START_CFA_CODE(rx_tpa_start) \
323 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
324 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
326 struct rx_tpa_end_cmp {
327 __le32 rx_tpa_end_cmp_len_flags_type;
328 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
329 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
330 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
331 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
332 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
333 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
334 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
335 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
336 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
337 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
338 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
339 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
340 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
341 #define RX_TPA_END_CMP_LEN (0xffff << 16)
342 #define RX_TPA_END_CMP_LEN_SHIFT 16
344 u32 rx_tpa_end_cmp_opaque;
345 __le32 rx_tpa_end_cmp_misc_v1;
346 #define RX_TPA_END_CMP_V1 (0x1 << 0)
347 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
348 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
349 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
350 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
351 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
352 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
353 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
354 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
356 __le32 rx_tpa_end_cmp_tsdelta;
357 #define RX_TPA_END_GRO_TS (0x1 << 31)
360 #define TPA_END_AGG_ID(rx_tpa_end) \
361 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
362 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
364 #define TPA_END_TPA_SEGS(rx_tpa_end) \
365 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
366 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
368 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
369 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
370 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
372 #define TPA_END_GRO(rx_tpa_end) \
373 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
374 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
376 #define TPA_END_GRO_TS(rx_tpa_end) \
377 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
378 cpu_to_le32(RX_TPA_END_GRO_TS)))
380 struct rx_tpa_end_cmp_ext {
381 __le32 rx_tpa_end_cmp_dup_acks;
382 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
384 __le32 rx_tpa_end_cmp_seg_len;
385 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
387 __le32 rx_tpa_end_cmp_errors_v2;
388 #define RX_TPA_END_CMP_V2 (0x1 << 0)
389 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
390 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
392 u32 rx_tpa_end_cmp_start_opaque;
395 #define TPA_END_ERRORS(rx_tpa_end_ext) \
396 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
397 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
399 #define DB_IDX_MASK 0xffffff
400 #define DB_IDX_VALID (0x1 << 26)
401 #define DB_IRQ_DIS (0x1 << 27)
402 #define DB_KEY_TX (0x0 << 28)
403 #define DB_KEY_RX (0x1 << 28)
404 #define DB_KEY_CP (0x2 << 28)
405 #define DB_KEY_ST (0x3 << 28)
406 #define DB_KEY_TX_PUSH (0x4 << 28)
407 #define DB_LONG_TX_PUSH (0x2 << 24)
409 #define BNXT_MIN_ROCE_CP_RINGS 2
410 #define BNXT_MIN_ROCE_STAT_CTXS 1
412 #define INVALID_HW_RING_ID ((u16)-1)
414 /* The hardware supports certain page sizes. Use the supported page sizes
415 * to allocate the rings.
417 #if (PAGE_SHIFT < 12)
418 #define BNXT_PAGE_SHIFT 12
419 #elif (PAGE_SHIFT <= 13)
420 #define BNXT_PAGE_SHIFT PAGE_SHIFT
421 #elif (PAGE_SHIFT < 16)
422 #define BNXT_PAGE_SHIFT 13
424 #define BNXT_PAGE_SHIFT 16
427 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
429 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
430 #if (PAGE_SHIFT > 15)
431 #define BNXT_RX_PAGE_SHIFT 15
433 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
436 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
438 #define BNXT_MAX_MTU 9500
439 #define BNXT_MAX_PAGE_MODE_MTU \
440 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
443 #define BNXT_MIN_PKT_SIZE 52
445 #define BNXT_DEFAULT_RX_RING_SIZE 511
446 #define BNXT_DEFAULT_TX_RING_SIZE 511
450 #if (BNXT_PAGE_SHIFT == 16)
451 #define MAX_RX_PAGES 1
452 #define MAX_RX_AGG_PAGES 4
453 #define MAX_TX_PAGES 1
454 #define MAX_CP_PAGES 8
456 #define MAX_RX_PAGES 8
457 #define MAX_RX_AGG_PAGES 32
458 #define MAX_TX_PAGES 8
459 #define MAX_CP_PAGES 64
462 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
463 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
464 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
466 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
467 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
469 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
471 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
472 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
474 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
476 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
477 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
478 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
480 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
481 * BD because the first TX BD is always a long BD.
483 #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
485 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
486 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
488 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
489 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
491 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
492 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
494 #define TX_CMP_VALID(txcmp, raw_cons) \
495 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
496 !((raw_cons) & bp->cp_bit))
498 #define RX_CMP_VALID(rxcmp1, raw_cons) \
499 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
500 !((raw_cons) & bp->cp_bit))
502 #define RX_AGG_CMP_VALID(agg, raw_cons) \
503 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
504 !((raw_cons) & bp->cp_bit))
506 #define TX_CMP_TYPE(txcmp) \
507 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
509 #define RX_CMP_TYPE(rxcmp) \
510 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
512 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
514 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
516 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
518 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
519 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
520 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
521 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
523 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
524 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
525 #define DFLT_HWRM_CMD_TIMEOUT 500
526 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
527 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
528 #define HWRM_RESP_ERR_CODE_MASK 0xffff
529 #define HWRM_RESP_LEN_OFFSET 4
530 #define HWRM_RESP_LEN_MASK 0xffff0000
531 #define HWRM_RESP_LEN_SFT 16
532 #define HWRM_RESP_VALID_MASK 0xff000000
533 #define HWRM_SEQ_ID_INVALID -1
534 #define BNXT_HWRM_REQ_MAX_SIZE 128
535 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
536 BNXT_HWRM_REQ_MAX_SIZE)
538 #define BNXT_RX_EVENT 1
539 #define BNXT_AGG_EVENT 2
540 #define BNXT_TX_EVENT 4
542 struct bnxt_sw_tx_bd {
544 DEFINE_DMA_UNMAP_ADDR(mapping);
548 unsigned short nr_frags;
553 struct bnxt_sw_rx_bd {
559 struct bnxt_sw_rx_agg_bd {
565 struct bnxt_ring_struct {
572 dma_addr_t pg_tbl_map;
577 u16 fw_ring_id; /* Ring id filled by Chimp FW */
583 __le32 tx_bd_len_flags_type;
585 struct tx_bd_ext txbd2;
588 struct tx_push_buffer {
589 struct tx_push_bd push_bd;
593 struct bnxt_tx_ring_info {
594 struct bnxt_napi *bnapi;
598 void __iomem *tx_doorbell;
600 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
601 struct bnxt_sw_tx_bd *tx_buf_ring;
603 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
605 struct tx_push_buffer *tx_push;
606 dma_addr_t tx_push_mapping;
609 #define BNXT_DEV_STATE_CLOSING 0x1
612 struct bnxt_ring_struct tx_ring_struct;
615 struct bnxt_tpa_info {
620 unsigned short gso_type;
623 enum pkt_hash_types hash_type;
627 #define BNXT_TPA_L4_SIZE(hdr_info) \
628 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
630 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
631 (((hdr_info) >> 18) & 0x1ff)
633 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
634 (((hdr_info) >> 9) & 0x1ff)
636 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
639 u16 cfa_code; /* cfa_code in TPA start compl */
642 struct bnxt_rx_ring_info {
643 struct bnxt_napi *bnapi;
648 void __iomem *rx_doorbell;
649 void __iomem *rx_agg_doorbell;
651 struct bpf_prog *xdp_prog;
653 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
654 struct bnxt_sw_rx_bd *rx_buf_ring;
656 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
657 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
659 unsigned long *rx_agg_bmap;
660 u16 rx_agg_bmap_size;
662 struct page *rx_page;
663 unsigned int rx_page_offset;
665 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
666 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
668 struct bnxt_tpa_info *rx_tpa;
670 struct bnxt_ring_struct rx_ring_struct;
671 struct bnxt_ring_struct rx_agg_ring_struct;
674 struct bnxt_cp_ring_info {
676 void __iomem *cp_doorbell;
678 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
680 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
682 struct ctx_hw_stats *hw_stats;
683 dma_addr_t hw_stats_map;
685 u64 rx_l4_csum_errors;
687 struct bnxt_ring_struct cp_ring_struct;
691 struct napi_struct napi;
695 struct bnxt_cp_ring_info cp_ring;
696 struct bnxt_rx_ring_info *rx_ring;
697 struct bnxt_tx_ring_info *tx_ring;
699 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
702 #define BNXT_NAPI_FLAG_XDP 0x1
708 irq_handler_t handler;
712 char name[IFNAMSIZ + 2];
713 cpumask_var_t cpu_mask;
716 #define HWRM_RING_ALLOC_TX 0x1
717 #define HWRM_RING_ALLOC_RX 0x2
718 #define HWRM_RING_ALLOC_AGG 0x4
719 #define HWRM_RING_ALLOC_CMPL 0x8
721 #define INVALID_STATS_CTX_ID -1
723 struct bnxt_ring_grp_info {
731 struct bnxt_vnic_info {
732 u16 fw_vnic_id; /* returned by Chimp during alloc */
733 #define BNXT_MAX_CTX_PER_VNIC 2
734 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
736 #define BNXT_MAX_UC_ADDRS 4
737 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
738 /* index 0 always dev_addr */
743 dma_addr_t rss_table_dma_addr;
745 dma_addr_t rss_hash_key_dma_addr;
752 dma_addr_t mc_list_mapping;
753 #define BNXT_MAX_MC_ADDRS 16
756 #define BNXT_VNIC_RSS_FLAG 1
757 #define BNXT_VNIC_RFS_FLAG 2
758 #define BNXT_VNIC_MCAST_FLAG 4
759 #define BNXT_VNIC_UCAST_FLAG 8
760 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
763 #if defined(CONFIG_BNXT_SRIOV)
764 struct bnxt_vf_info {
766 u8 mac_addr[ETH_ALEN];
771 u16 max_hw_ring_grps;
778 #define BNXT_VF_QOS 0x1
779 #define BNXT_VF_SPOOFCHK 0x2
780 #define BNXT_VF_LINK_FORCED 0x4
781 #define BNXT_VF_LINK_UP 0x8
784 void *hwrm_cmd_req_addr;
785 dma_addr_t hwrm_cmd_req_dma_addr;
789 struct bnxt_pf_info {
790 #define BNXT_FIRST_PF_FID 1
791 #define BNXT_FIRST_VF_FID 128
794 u8 mac_addr[ETH_ALEN];
797 u16 max_tx_rings; /* HW assigned max tx rings for this PF */
798 u16 max_rx_rings; /* HW assigned max rx rings for this PF */
799 u16 max_hw_ring_grps;
807 u32 max_encap_records;
808 u32 max_decap_records;
813 unsigned long *vf_event_bmap;
814 u16 hwrm_cmd_req_pages;
815 void *hwrm_cmd_req_addr[4];
816 dma_addr_t hwrm_cmd_req_dma_addr[4];
817 struct bnxt_vf_info *vf;
820 struct bnxt_ntuple_filter {
821 struct hlist_node hash;
822 u8 dst_mac_addr[ETH_ALEN];
823 u8 src_mac_addr[ETH_ALEN];
824 struct flow_keys fkeys;
831 #define BNXT_FLTR_VALID 0
832 #define BNXT_FLTR_UPDATE 1
835 struct bnxt_link_info {
841 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
842 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
843 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
848 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
849 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
851 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
852 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
853 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
854 PORT_PHY_QCFG_RESP_PAUSE_TX)
856 u8 auto_pause_setting;
857 u8 force_pause_setting;
860 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
861 (mode) <= BNXT_LINK_AUTO_MSK)
862 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
863 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
864 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
865 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
866 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
867 #define PHY_VER_LEN 3
868 u8 phy_ver[PHY_VER_LEN];
870 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
871 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
872 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
873 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
874 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
875 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
876 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
877 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
878 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
879 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
881 u16 auto_link_speeds; /* fw adv setting */
882 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
883 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
884 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
885 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
886 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
887 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
888 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
889 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
890 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
891 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
892 u16 support_auto_speeds;
893 u16 lp_auto_link_speeds;
894 u16 force_link_speed;
898 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
899 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
900 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
902 /* copy of requested setting from ethtool cmd */
904 #define BNXT_AUTONEG_SPEED 1
905 #define BNXT_AUTONEG_FLOW_CTRL 2
909 u16 advertising; /* user adv setting */
910 bool force_link_chng;
912 /* a copy of phy_qcfg output used to report link
915 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
918 #define BNXT_MAX_QUEUE 8
920 struct bnxt_queue_info {
925 #define BNXT_MAX_LED 4
927 struct bnxt_led_info {
932 __le16 led_state_caps;
933 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
934 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
936 __le16 led_color_caps;
939 #define BNXT_MAX_TEST 8
941 struct bnxt_test_info {
944 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
947 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
948 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
949 #define BNXT_CAG_REG_BASE 0x300000
951 struct bnxt_tc_info {
954 /* hash table to store TC offloaded flows */
955 struct rhashtable flow_table;
956 struct rhashtable_params flow_ht_params;
958 /* hash table to store L2 keys of TC flows */
959 struct rhashtable l2_table;
960 struct rhashtable_params l2_ht_params;
962 /* lock to atomically add/del an l2 node when a flow is
967 /* Stat counter mask (width) */
972 struct bnxt_vf_rep_stats {
980 struct net_device *dev;
981 struct metadata_dst *dst;
986 struct bnxt_vf_rep_stats rx_stats;
987 struct bnxt_vf_rep_stats tx_stats;
997 #define CHIP_NUM_57301 0x16c8
998 #define CHIP_NUM_57302 0x16c9
999 #define CHIP_NUM_57304 0x16ca
1000 #define CHIP_NUM_58700 0x16cd
1001 #define CHIP_NUM_57402 0x16d0
1002 #define CHIP_NUM_57404 0x16d1
1003 #define CHIP_NUM_57406 0x16d2
1004 #define CHIP_NUM_57407 0x16d5
1006 #define CHIP_NUM_57311 0x16ce
1007 #define CHIP_NUM_57312 0x16cf
1008 #define CHIP_NUM_57314 0x16df
1009 #define CHIP_NUM_57317 0x16e0
1010 #define CHIP_NUM_57412 0x16d6
1011 #define CHIP_NUM_57414 0x16d7
1012 #define CHIP_NUM_57416 0x16d8
1013 #define CHIP_NUM_57417 0x16d9
1014 #define CHIP_NUM_57412L 0x16da
1015 #define CHIP_NUM_57414L 0x16db
1017 #define CHIP_NUM_5745X 0xd730
1019 #define CHIP_NUM_58802 0xd802
1020 #define CHIP_NUM_58808 0xd808
1022 #define BNXT_CHIP_NUM_5730X(chip_num) \
1023 ((chip_num) >= CHIP_NUM_57301 && \
1024 (chip_num) <= CHIP_NUM_57304)
1026 #define BNXT_CHIP_NUM_5740X(chip_num) \
1027 (((chip_num) >= CHIP_NUM_57402 && \
1028 (chip_num) <= CHIP_NUM_57406) || \
1029 (chip_num) == CHIP_NUM_57407)
1031 #define BNXT_CHIP_NUM_5731X(chip_num) \
1032 ((chip_num) == CHIP_NUM_57311 || \
1033 (chip_num) == CHIP_NUM_57312 || \
1034 (chip_num) == CHIP_NUM_57314 || \
1035 (chip_num) == CHIP_NUM_57317)
1037 #define BNXT_CHIP_NUM_5741X(chip_num) \
1038 ((chip_num) >= CHIP_NUM_57412 && \
1039 (chip_num) <= CHIP_NUM_57414L)
1041 #define BNXT_CHIP_NUM_58700(chip_num) \
1042 ((chip_num) == CHIP_NUM_58700)
1044 #define BNXT_CHIP_NUM_5745X(chip_num) \
1045 ((chip_num) == CHIP_NUM_5745X)
1047 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1048 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1050 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1051 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1053 #define BNXT_CHIP_NUM_588XX(chip_num) \
1054 ((chip_num) == CHIP_NUM_58802 || \
1055 (chip_num) == CHIP_NUM_58808)
1057 struct net_device *dev;
1058 struct pci_dev *pdev;
1063 #define BNXT_FLAG_DCB_ENABLED 0x1
1064 #define BNXT_FLAG_VF 0x2
1065 #define BNXT_FLAG_LRO 0x4
1067 #define BNXT_FLAG_GRO 0x8
1069 /* Cannot support hardware GRO if CONFIG_INET is not set */
1070 #define BNXT_FLAG_GRO 0x0
1072 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1073 #define BNXT_FLAG_JUMBO 0x10
1074 #define BNXT_FLAG_STRIP_VLAN 0x20
1075 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1077 #define BNXT_FLAG_USING_MSIX 0x40
1078 #define BNXT_FLAG_MSIX_CAP 0x80
1079 #define BNXT_FLAG_RFS 0x100
1080 #define BNXT_FLAG_SHARED_RINGS 0x200
1081 #define BNXT_FLAG_PORT_STATS 0x400
1082 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1083 #define BNXT_FLAG_EEE_CAP 0x1000
1084 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1085 #define BNXT_FLAG_WOL_CAP 0x4000
1086 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1087 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1088 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1089 BNXT_FLAG_ROCEV2_CAP)
1090 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1091 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1092 #define BNXT_FLAG_FW_LLDP_AGENT 0x80000
1093 #define BNXT_FLAG_MULTI_HOST 0x100000
1094 #define BNXT_FLAG_SHORT_CMD 0x200000
1095 #define BNXT_FLAG_DOUBLE_DB 0x400000
1096 #define BNXT_FLAG_FW_DCBX_AGENT 0x800000
1097 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1099 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1101 BNXT_FLAG_STRIP_VLAN)
1103 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1104 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1105 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1106 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1107 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1108 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1109 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1111 /* Chip class phase 4 and later */
1112 #define BNXT_CHIP_P4_PLUS(bp) \
1113 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1114 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1115 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1116 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1117 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1119 struct bnxt_en_dev *edev;
1120 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1122 struct bnxt_napi **bnapi;
1124 struct bnxt_rx_ring_info *rx_ring;
1125 struct bnxt_tx_ring_info *tx_ring;
1128 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1131 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1132 struct bnxt_rx_ring_info *,
1133 u16, void *, u8 *, dma_addr_t,
1137 u32 rx_buf_use_size; /* useable size */
1140 enum dma_data_direction rx_dir;
1142 u32 rx_agg_ring_size;
1145 u32 rx_agg_ring_mask;
1147 int rx_agg_nr_pages;
1155 int tx_nr_rings_per_tc;
1156 int tx_nr_rings_xdp;
1157 int tx_reserved_rings;
1171 /* grp_info indexed by completion ring index */
1172 struct bnxt_ring_grp_info *grp_info;
1173 struct bnxt_vnic_info *vnic_info;
1178 u8 max_lltc; /* lossless TCs */
1179 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1181 unsigned int current_interval;
1182 #define BNXT_TIMER_INTERVAL HZ
1184 struct timer_list timer;
1186 unsigned long state;
1187 #define BNXT_STATE_OPEN 0
1188 #define BNXT_STATE_IN_SP_TASK 1
1189 #define BNXT_STATE_READ_STATS 2
1191 struct bnxt_irq *irq_tbl;
1193 u8 mac_addr[ETH_ALEN];
1195 #ifdef CONFIG_BNXT_DCB
1196 struct ieee_pfc *ieee_pfc;
1197 struct ieee_ets *ieee_ets;
1200 #endif /* CONFIG_BNXT_DCB */
1206 u32 hwrm_intr_seq_id;
1207 void *hwrm_short_cmd_req_addr;
1208 dma_addr_t hwrm_short_cmd_req_dma_addr;
1209 void *hwrm_cmd_resp_addr;
1210 dma_addr_t hwrm_cmd_resp_dma_addr;
1211 void *hwrm_dbg_resp_addr;
1212 dma_addr_t hwrm_dbg_resp_dma_addr;
1213 #define HWRM_DBG_REG_BUF_SIZE 128
1215 struct rx_port_stats *hw_rx_port_stats;
1216 struct tx_port_stats *hw_tx_port_stats;
1217 dma_addr_t hw_rx_port_stats_map;
1218 dma_addr_t hw_tx_port_stats_map;
1219 int hw_port_stats_size;
1221 u16 hwrm_max_req_len;
1222 int hwrm_cmd_timeout;
1223 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1224 struct hwrm_ver_get_output ver_resp;
1225 #define FW_VER_STR_LEN 32
1226 #define BC_HWRM_STR_LEN 21
1227 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1228 char fw_ver_str[FW_VER_STR_LEN];
1231 __le16 vxlan_fw_dst_port_id;
1234 __le16 nge_fw_dst_port_id;
1235 u8 port_partition_type;
1240 u16 rx_coal_ticks_irq;
1242 u16 rx_coal_bufs_irq;
1244 u16 tx_coal_ticks_irq;
1246 u16 tx_coal_bufs_irq;
1248 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
1250 u32 stats_coal_ticks;
1251 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1252 #define BNXT_MIN_STATS_COAL_TICKS 250000
1253 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1255 struct work_struct sp_task;
1256 unsigned long sp_event;
1257 #define BNXT_RX_MASK_SP_EVENT 0
1258 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1259 #define BNXT_LINK_CHNG_SP_EVENT 2
1260 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1261 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1262 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1263 #define BNXT_RESET_TASK_SP_EVENT 6
1264 #define BNXT_RST_RING_SP_EVENT 7
1265 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1266 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1267 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1268 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1269 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1270 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1271 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1273 struct bnxt_pf_info pf;
1274 #ifdef CONFIG_BNXT_SRIOV
1276 struct bnxt_vf_info vf;
1277 wait_queue_head_t sriov_cfg_wait;
1279 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1281 /* lock to protect VF-rep creation/cleanup via
1282 * multiple paths such as ->sriov_configure() and
1283 * devlink ->eswitch_mode_set()
1285 struct mutex sriov_lock;
1288 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1289 #define BNXT_NTP_FLTR_HASH_SIZE 512
1290 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1291 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1292 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1294 unsigned long *ntp_fltr_bmap;
1297 /* To protect link related settings during link changes and
1298 * ethtool settings changes.
1300 struct mutex link_lock;
1301 struct bnxt_link_info link_info;
1302 struct ethtool_eee eee;
1307 struct bnxt_test_info *test_info;
1313 struct bnxt_led_info leds[BNXT_MAX_LED];
1315 struct bpf_prog *xdp_prog;
1317 /* devlink interface and vf-rep structs */
1319 enum devlink_eswitch_mode eswitch_mode;
1320 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
1321 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
1322 struct bnxt_tc_info tc_info;
1325 #define BNXT_RX_STATS_OFFSET(counter) \
1326 (offsetof(struct rx_port_stats, counter) / 8)
1328 #define BNXT_TX_STATS_OFFSET(counter) \
1329 ((offsetof(struct tx_port_stats, counter) + \
1330 sizeof(struct rx_port_stats) + 512) / 8)
1332 #define I2C_DEV_ADDR_A0 0xa0
1333 #define I2C_DEV_ADDR_A2 0xa2
1334 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
1335 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1
1336 #define SFF_MODULE_ID_SFP 0x3
1337 #define SFF_MODULE_ID_QSFP 0xc
1338 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1339 #define SFF_MODULE_ID_QSFP28 0x11
1340 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1342 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1344 /* Tell compiler to fetch tx indices from memory. */
1347 return bp->tx_ring_size -
1348 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1351 /* For TX and RX ring doorbells */
1352 static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val)
1355 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1359 extern const u16 bnxt_lhint_arr[];
1361 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1362 u16 prod, gfp_t gfp);
1363 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1364 void bnxt_set_tpa_flags(struct bnxt *bp);
1365 void bnxt_set_ring_params(struct bnxt *);
1366 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1367 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1368 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1369 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1370 int hwrm_send_message(struct bnxt *, void *, u32, int);
1371 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1372 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1374 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1375 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1376 int bnxt_hwrm_set_coal(struct bnxt *);
1377 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1378 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
1379 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1380 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max);
1381 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max);
1382 void bnxt_tx_disable(struct bnxt *bp);
1383 void bnxt_tx_enable(struct bnxt *bp);
1384 int bnxt_hwrm_set_pause(struct bnxt *);
1385 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1386 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1387 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1388 int bnxt_hwrm_fw_set_time(struct bnxt *);
1389 int bnxt_open_nic(struct bnxt *, bool, bool);
1390 int bnxt_half_open_nic(struct bnxt *bp);
1391 void bnxt_half_close_nic(struct bnxt *bp);
1392 int bnxt_close_nic(struct bnxt *, bool, bool);
1393 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1395 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1396 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1397 void bnxt_restore_pf_fw_resources(struct bnxt *bp);
1398 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr);