drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/if_bridge.h>
  37 #include <linux/rtc.h>
  38 #include <linux/bpf.h>
  39 #include <net/ip.h>
  40 #include <net/tcp.h>
  41 #include <net/udp.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <net/udp_tunnel.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/prefetch.h>
  47 #include <linux/cache.h>
  48 #include <linux/log2.h>
  49 #include <linux/aer.h>
  50 #include <linux/bitmap.h>
  51 #include <linux/cpu_rmap.h>
  52 #include <linux/cpumask.h>
  53 #include <net/pkt_cls.h>
  54 #include <linux/hwmon.h>
  55 #include <linux/hwmon-sysfs.h>
  56
  57 #include "bnxt_hsi.h"
  58 #include "bnxt.h"
  59 #include "bnxt_ulp.h"
  60 #include "bnxt_sriov.h"
  61 #include "bnxt_ethtool.h"
  62 #include "bnxt_dcb.h"
  63 #include "bnxt_xdp.h"
  64 #include "bnxt_vfr.h"
  65 #include "bnxt_tc.h"
  66 #include "bnxt_devlink.h"
  67 #include "bnxt_debugfs.h"
  68
  69 #define BNXT_TX_TIMEOUT         (5 * HZ)
  70
  71 static const char version[] =
  72         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  73
  74 MODULE_LICENSE("GPL");
  75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  76 MODULE_VERSION(DRV_MODULE_VERSION);
  77
  78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  80 #define BNXT_RX_COPY_THRESH 256
  81
  82 #define BNXT_TX_PUSH_THRESH 164
  83
  84 enum board_idx {
  85         BCM57301,
  86         BCM57302,
  87         BCM57304,
  88         BCM57417_NPAR,
  89         BCM58700,
  90         BCM57311,
  91         BCM57312,
  92         BCM57402,
  93         BCM57404,
  94         BCM57406,
  95         BCM57402_NPAR,
  96         BCM57407,
  97         BCM57412,
  98         BCM57414,
  99         BCM57416,
 100         BCM57417,
 101         BCM57412_NPAR,
 102         BCM57314,
 103         BCM57417_SFP,
 104         BCM57416_SFP,
 105         BCM57404_NPAR,
 106         BCM57406_NPAR,
 107         BCM57407_SFP,
 108         BCM57407_NPAR,
 109         BCM57414_NPAR,
 110         BCM57416_NPAR,
 111         BCM57452,
 112         BCM57454,
 113         BCM5745x_NPAR,
 114         BCM58802,
 115         BCM58804,
 116         BCM58808,
 117         NETXTREME_E_VF,
 118         NETXTREME_C_VF,
 119         NETXTREME_S_VF,
 120 };
 121
 122 /* indexed by enum above */
 123 static const struct {
 124         char *name;
 125 } board_info[] = {
 126         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 127         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 128         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 129         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 130         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 131         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 132         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 133         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 134         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 135         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 136         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 137         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 138         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 139         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 140         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 141         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 142         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 143         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 144         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 145         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 146         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 147         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 148         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 149         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 150         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 151         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 152         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 153         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 154         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 155         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 156         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 157         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 158         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 159         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 160         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 161 };
 162
 163 static const struct pci_device_id bnxt_pci_tbl[] = {
 164         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 167         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 169         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 170         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 171         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 173         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 174         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 175         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 176         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 177         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 178         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 180         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 181         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 182         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 183         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 184         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 185         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 186         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 187         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 188         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 189         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 190         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 191         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 192         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 193         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 194         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 195         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 196         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 197         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 198         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 199         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 200         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 201 #ifdef CONFIG_BNXT_SRIOV
 202         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 203         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 205         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 206         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 207         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 208         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 209         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 210         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 211 #endif
 212         { 0 }
 213 };
 214
 215 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 216
 217 static const u16 bnxt_vf_req_snif[] = {
 218         HWRM_FUNC_CFG,
 219         HWRM_FUNC_VF_CFG,
 220         HWRM_PORT_PHY_QCFG,
 221         HWRM_CFA_L2_FILTER_ALLOC,
 222 };
 223
 224 static const u16 bnxt_async_events_arr[] = {
 225         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 226         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 227         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 228         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 229         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 230 };
 231
 232 static struct workqueue_struct *bnxt_pf_wq;
 233
 234 static bool bnxt_vf_pciid(enum board_idx idx)
 235 {
 236         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 237                 idx == NETXTREME_S_VF);
 238 }
 239
 240 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 241 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 242 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 243
 244 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 245                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 246
 247 #define BNXT_CP_DB(db, raw_cons)                                        \
 248                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 249
 250 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 251                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 252
 253 const u16 bnxt_lhint_arr[] = {
 254         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 255         TX_BD_FLAGS_LHINT_512_TO_1023,
 256         TX_BD_FLAGS_LHINT_1024_TO_2047,
 257         TX_BD_FLAGS_LHINT_1024_TO_2047,
 258         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 259         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 260         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 261         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 262         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 263         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 264         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 265         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 266         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 267         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 268         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 269         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 270         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 271         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 272         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 273 };
 274
 275 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 276 {
 277         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 278
 279         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 280                 return 0;
 281
 282         return md_dst->u.port_info.port_id;
 283 }
 284
 285 static bool bnxt_txr_netif_try_stop_queue(struct bnxt *bp,
 286                                           struct bnxt_tx_ring_info *txr,
 287                                           struct netdev_queue *txq)
 288 {
 289         netif_tx_stop_queue(txq);
 290
 291         /* netif_tx_stop_queue() must be done before checking
 292          * tx index in bnxt_tx_avail() below, because in
 293          * bnxt_tx_int(), we update tx index before checking for
 294          * netif_tx_queue_stopped().
 295          */
 296         smp_mb();
 297         if (bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh) {
 298                 netif_tx_wake_queue(txq);
 299                 return false;
 300         }
 301
 302         return true;
 303 }
 304
 305 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 306 {
 307         struct bnxt *bp = netdev_priv(dev);
 308         struct tx_bd *txbd;
 309         struct tx_bd_ext *txbd1;
 310         struct netdev_queue *txq;
 311         int i;
 312         dma_addr_t mapping;
 313         unsigned int length, pad = 0;
 314         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 315         u16 prod, last_frag;
 316         struct pci_dev *pdev = bp->pdev;
 317         struct bnxt_tx_ring_info *txr;
 318         struct bnxt_sw_tx_bd *tx_buf;
 319
 320         i = skb_get_queue_mapping(skb);
 321         if (unlikely(i >= bp->tx_nr_rings)) {
 322                 dev_kfree_skb_any(skb);
 323                 return NETDEV_TX_OK;
 324         }
 325
 326         txq = netdev_get_tx_queue(dev, i);
 327         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 328         prod = txr->tx_prod;
 329
 330         free_size = bnxt_tx_avail(bp, txr);
 331         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 332                 if (bnxt_txr_netif_try_stop_queue(bp, txr, txq))
 333                         return NETDEV_TX_BUSY;
 334         }
 335
 336         length = skb->len;
 337         len = skb_headlen(skb);
 338         last_frag = skb_shinfo(skb)->nr_frags;
 339
 340         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 341
 342         txbd->tx_bd_opaque = prod;
 343
 344         tx_buf = &txr->tx_buf_ring[prod];
 345         tx_buf->skb = skb;
 346         tx_buf->nr_frags = last_frag;
 347
 348         vlan_tag_flags = 0;
 349         cfa_action = bnxt_xmit_get_cfa_action(skb);
 350         if (skb_vlan_tag_present(skb)) {
 351                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 352                                  skb_vlan_tag_get(skb);
 353                 /* Currently supports 8021Q, 8021AD vlan offloads
 354                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 355                  */
 356                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 357                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 358         }
 359
 360         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 361                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 362                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 363                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 364                 void *pdata = tx_push_buf->data;
 365                 u64 *end;
 366                 int j, push_len;
 367
 368                 /* Set COAL_NOW to be ready quickly for the next push */
 369                 tx_push->tx_bd_len_flags_type =
 370                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 371                                         TX_BD_TYPE_LONG_TX_BD |
 372                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 373                                         TX_BD_FLAGS_COAL_NOW |
 374                                         TX_BD_FLAGS_PACKET_END |
 375                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 376
 377                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 378                         tx_push1->tx_bd_hsize_lflags =
 379                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 380                 else
 381                         tx_push1->tx_bd_hsize_lflags = 0;
 382
 383                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 384                 tx_push1->tx_bd_cfa_action =
 385                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 386
 387                 end = pdata + length;
 388                 end = PTR_ALIGN(end, 8) - 1;
 389                 *end = 0;
 390
 391                 skb_copy_from_linear_data(skb, pdata, len);
 392                 pdata += len;
 393                 for (j = 0; j < last_frag; j++) {
 394                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 395                         void *fptr;
 396
 397                         fptr = skb_frag_address_safe(frag);
 398                         if (!fptr)
 399                                 goto normal_tx;
 400
 401                         memcpy(pdata, fptr, skb_frag_size(frag));
 402                         pdata += skb_frag_size(frag);
 403                 }
 404
 405                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 406                 txbd->tx_bd_haddr = txr->data_mapping;
 407                 prod = NEXT_TX(prod);
 408                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 409                 memcpy(txbd, tx_push1, sizeof(*txbd));
 410                 prod = NEXT_TX(prod);
 411                 tx_push->doorbell =
 412                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 413                 txr->tx_prod = prod;
 414
 415                 tx_buf->is_push = 1;
 416                 netdev_tx_sent_queue(txq, skb->len);
 417                 wmb();  /* Sync is_push and byte queue before pushing data */
 418
 419                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 420                 if (push_len > 16) {
 421                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 422                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 423                                          (push_len - 16) << 1);
 424                 } else {
 425                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 426                                          push_len);
 427                 }
 428
 429                 goto tx_done;
 430         }
 431
 432 normal_tx:
 433         if (length < BNXT_MIN_PKT_SIZE) {
 434                 pad = BNXT_MIN_PKT_SIZE - length;
 435                 if (skb_pad(skb, pad)) {
 436                         /* SKB already freed. */
 437                         tx_buf->skb = NULL;
 438                         return NETDEV_TX_OK;
 439                 }
 440                 length = BNXT_MIN_PKT_SIZE;
 441         }
 442
 443         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 444
 445         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 446                 dev_kfree_skb_any(skb);
 447                 tx_buf->skb = NULL;
 448                 return NETDEV_TX_OK;
 449         }
 450
 451         dma_unmap_addr_set(tx_buf, mapping, mapping);
 452         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 453                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 454
 455         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 456
 457         prod = NEXT_TX(prod);
 458         txbd1 = (struct tx_bd_ext *)
 459                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 460
 461         txbd1->tx_bd_hsize_lflags = 0;
 462         if (skb_is_gso(skb)) {
 463                 u32 hdr_len;
 464
 465                 if (skb->encapsulation)
 466                         hdr_len = skb_inner_network_offset(skb) +
 467                                 skb_inner_network_header_len(skb) +
 468                                 inner_tcp_hdrlen(skb);
 469                 else
 470                         hdr_len = skb_transport_offset(skb) +
 471                                 tcp_hdrlen(skb);
 472
 473                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 474                                         TX_BD_FLAGS_T_IPID |
 475                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 476                 length = skb_shinfo(skb)->gso_size;
 477                 txbd1->tx_bd_mss = cpu_to_le32(length);
 478                 length += hdr_len;
 479         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 480                 txbd1->tx_bd_hsize_lflags =
 481                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 482                 txbd1->tx_bd_mss = 0;
 483         }
 484
 485         length >>= 9;
 486         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 487                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 488                                      skb->len);
 489                 i = 0;
 490                 goto tx_dma_error;
 491         }
 492         flags |= bnxt_lhint_arr[length];
 493         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 494
 495         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 496         txbd1->tx_bd_cfa_action =
 497                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 498         for (i = 0; i < last_frag; i++) {
 499                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 500
 501                 prod = NEXT_TX(prod);
 502                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 503
 504                 len = skb_frag_size(frag);
 505                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 506                                            DMA_TO_DEVICE);
 507
 508                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 509                         goto tx_dma_error;
 510
 511                 tx_buf = &txr->tx_buf_ring[prod];
 512                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 513
 514                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 515
 516                 flags = len << TX_BD_LEN_SHIFT;
 517                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 518         }
 519
 520         flags &= ~TX_BD_LEN;
 521         txbd->tx_bd_len_flags_type =
 522                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 523                             TX_BD_FLAGS_PACKET_END);
 524
 525         netdev_tx_sent_queue(txq, skb->len);
 526
 527         /* Sync BD data before updating doorbell */
 528         wmb();
 529
 530         prod = NEXT_TX(prod);
 531         txr->tx_prod = prod;
 532
 533         if (!skb->xmit_more || netif_xmit_stopped(txq))
 534                 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 535
 536 tx_done:
 537
 538         mmiowb();
 539
 540         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 541                 if (skb->xmit_more && !tx_buf->is_push)
 542                         bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 543
 544                 bnxt_txr_netif_try_stop_queue(bp, txr, txq);
 545         }
 546         return NETDEV_TX_OK;
 547
 548 tx_dma_error:
 549         last_frag = i;
 550
 551         /* start back at beginning and unmap skb */
 552         prod = txr->tx_prod;
 553         tx_buf = &txr->tx_buf_ring[prod];
 554         tx_buf->skb = NULL;
 555         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 556                          skb_headlen(skb), PCI_DMA_TODEVICE);
 557         prod = NEXT_TX(prod);
 558
 559         /* unmap remaining mapped pages */
 560         for (i = 0; i < last_frag; i++) {
 561                 prod = NEXT_TX(prod);
 562                 tx_buf = &txr->tx_buf_ring[prod];
 563                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 564                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 565                                PCI_DMA_TODEVICE);
 566         }
 567
 568         dev_kfree_skb_any(skb);
 569         return NETDEV_TX_OK;
 570 }
 571
 572 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 573 {
 574         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 575         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 576         u16 cons = txr->tx_cons;
 577         struct pci_dev *pdev = bp->pdev;
 578         int i;
 579         unsigned int tx_bytes = 0;
 580
 581         for (i = 0; i < nr_pkts; i++) {
 582                 struct bnxt_sw_tx_bd *tx_buf;
 583                 struct sk_buff *skb;
 584                 int j, last;
 585
 586                 tx_buf = &txr->tx_buf_ring[cons];
 587                 cons = NEXT_TX(cons);
 588                 skb = tx_buf->skb;
 589                 tx_buf->skb = NULL;
 590
 591                 if (tx_buf->is_push) {
 592                         tx_buf->is_push = 0;
 593                         goto next_tx_int;
 594                 }
 595
 596                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 597                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 598                 last = tx_buf->nr_frags;
 599
 600                 for (j = 0; j < last; j++) {
 601                         cons = NEXT_TX(cons);
 602                         tx_buf = &txr->tx_buf_ring[cons];
 603                         dma_unmap_page(
 604                                 &pdev->dev,
 605                                 dma_unmap_addr(tx_buf, mapping),
 606                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 607                                 PCI_DMA_TODEVICE);
 608                 }
 609
 610 next_tx_int:
 611                 cons = NEXT_TX(cons);
 612
 613                 tx_bytes += skb->len;
 614                 dev_kfree_skb_any(skb);
 615         }
 616
 617         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 618         txr->tx_cons = cons;
 619
 620         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 621          * before checking for netif_tx_queue_stopped().  Without the
 622          * memory barrier, there is a small possibility that bnxt_start_xmit()
 623          * will miss it and cause the queue to be stopped forever.
 624          */
 625         smp_mb();
 626
 627         if (unlikely(netif_tx_queue_stopped(txq)) &&
 628             bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh &&
 629             READ_ONCE(txr->dev_state) != BNXT_DEV_STATE_CLOSING)
 630                 netif_tx_wake_queue(txq);
 631 }
 632
 633 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 634                                          gfp_t gfp)
 635 {
 636         struct device *dev = &bp->pdev->dev;
 637         struct page *page;
 638
 639         page = alloc_page(gfp);
 640         if (!page)
 641                 return NULL;
 642
 643         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 644                                       DMA_ATTR_WEAK_ORDERING);
 645         if (dma_mapping_error(dev, *mapping)) {
 646                 __free_page(page);
 647                 return NULL;
 648         }
 649         *mapping += bp->rx_dma_offset;
 650         return page;
 651 }
 652
 653 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 654                                        gfp_t gfp)
 655 {
 656         u8 *data;
 657         struct pci_dev *pdev = bp->pdev;
 658
 659         data = kmalloc(bp->rx_buf_size, gfp);
 660         if (!data)
 661                 return NULL;
 662
 663         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 664                                         bp->rx_buf_use_size, bp->rx_dir,
 665                                         DMA_ATTR_WEAK_ORDERING);
 666
 667         if (dma_mapping_error(&pdev->dev, *mapping)) {
 668                 kfree(data);
 669                 data = NULL;
 670         }
 671         return data;
 672 }
 673
 674 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 675                        u16 prod, gfp_t gfp)
 676 {
 677         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 678         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 679         dma_addr_t mapping;
 680
 681         if (BNXT_RX_PAGE_MODE(bp)) {
 682                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 683
 684                 if (!page)
 685                         return -ENOMEM;
 686
 687                 rx_buf->data = page;
 688                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 689         } else {
 690                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 691
 692                 if (!data)
 693                         return -ENOMEM;
 694
 695                 rx_buf->data = data;
 696                 rx_buf->data_ptr = data + bp->rx_offset;
 697         }
 698         rx_buf->mapping = mapping;
 699
 700         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 701         return 0;
 702 }
 703
 704 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 705 {
 706         u16 prod = rxr->rx_prod;
 707         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 708         struct rx_bd *cons_bd, *prod_bd;
 709
 710         prod_rx_buf = &rxr->rx_buf_ring[prod];
 711         cons_rx_buf = &rxr->rx_buf_ring[cons];
 712
 713         prod_rx_buf->data = data;
 714         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 715
 716         prod_rx_buf->mapping = cons_rx_buf->mapping;
 717
 718         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 719         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 720
 721         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 722 }
 723
 724 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 725 {
 726         u16 next, max = rxr->rx_agg_bmap_size;
 727
 728         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 729         if (next >= max)
 730                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 731         return next;
 732 }
 733
 734 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 735                                      struct bnxt_rx_ring_info *rxr,
 736                                      u16 prod, gfp_t gfp)
 737 {
 738         struct rx_bd *rxbd =
 739                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 740         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 741         struct pci_dev *pdev = bp->pdev;
 742         struct page *page;
 743         dma_addr_t mapping;
 744         u16 sw_prod = rxr->rx_sw_agg_prod;
 745         unsigned int offset = 0;
 746
 747         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 748                 page = rxr->rx_page;
 749                 if (!page) {
 750                         page = alloc_page(gfp);
 751                         if (!page)
 752                                 return -ENOMEM;
 753                         rxr->rx_page = page;
 754                         rxr->rx_page_offset = 0;
 755                 }
 756                 offset = rxr->rx_page_offset;
 757                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 758                 if (rxr->rx_page_offset == PAGE_SIZE)
 759                         rxr->rx_page = NULL;
 760                 else
 761                         get_page(page);
 762         } else {
 763                 page = alloc_page(gfp);
 764                 if (!page)
 765                         return -ENOMEM;
 766         }
 767
 768         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 769                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 770                                      DMA_ATTR_WEAK_ORDERING);
 771         if (dma_mapping_error(&pdev->dev, mapping)) {
 772                 __free_page(page);
 773                 return -EIO;
 774         }
 775
 776         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 777                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 778
 779         __set_bit(sw_prod, rxr->rx_agg_bmap);
 780         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 781         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 782
 783         rx_agg_buf->page = page;
 784         rx_agg_buf->offset = offset;
 785         rx_agg_buf->mapping = mapping;
 786         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 787         rxbd->rx_bd_opaque = sw_prod;
 788         return 0;
 789 }
 790
 791 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 792                                    u32 agg_bufs)
 793 {
 794         struct bnxt *bp = bnapi->bp;
 795         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 796         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 797         u16 prod = rxr->rx_agg_prod;
 798         u16 sw_prod = rxr->rx_sw_agg_prod;
 799         u32 i;
 800
 801         for (i = 0; i < agg_bufs; i++) {
 802                 u16 cons;
 803                 struct rx_agg_cmp *agg;
 804                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 805                 struct rx_bd *prod_bd;
 806                 struct page *page;
 807
 808                 agg = (struct rx_agg_cmp *)
 809                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 810                 cons = agg->rx_agg_cmp_opaque;
 811                 __clear_bit(cons, rxr->rx_agg_bmap);
 812
 813                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 814                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 815
 816                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 817                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 818                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 819
 820                 /* It is possible for sw_prod to be equal to cons, so
 821                  * set cons_rx_buf->page to NULL first.
 822                  */
 823                 page = cons_rx_buf->page;
 824                 cons_rx_buf->page = NULL;
 825                 prod_rx_buf->page = page;
 826                 prod_rx_buf->offset = cons_rx_buf->offset;
 827
 828                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 829
 830                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 831
 832                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 833                 prod_bd->rx_bd_opaque = sw_prod;
 834
 835                 prod = NEXT_RX_AGG(prod);
 836                 sw_prod = NEXT_RX_AGG(sw_prod);
 837                 cp_cons = NEXT_CMP(cp_cons);
 838         }
 839         rxr->rx_agg_prod = prod;
 840         rxr->rx_sw_agg_prod = sw_prod;
 841 }
 842
 843 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 844                                         struct bnxt_rx_ring_info *rxr,
 845                                         u16 cons, void *data, u8 *data_ptr,
 846                                         dma_addr_t dma_addr,
 847                                         unsigned int offset_and_len)
 848 {
 849         unsigned int payload = offset_and_len >> 16;
 850         unsigned int len = offset_and_len & 0xffff;
 851         struct skb_frag_struct *frag;
 852         struct page *page = data;
 853         u16 prod = rxr->rx_prod;
 854         struct sk_buff *skb;
 855         int off, err;
 856
 857         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 858         if (unlikely(err)) {
 859                 bnxt_reuse_rx_data(rxr, cons, data);
 860                 return NULL;
 861         }
 862         dma_addr -= bp->rx_dma_offset;
 863         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 864                              DMA_ATTR_WEAK_ORDERING);
 865
 866         if (unlikely(!payload))
 867                 payload = eth_get_headlen(data_ptr, len);
 868
 869         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 870         if (!skb) {
 871                 __free_page(page);
 872                 return NULL;
 873         }
 874
 875         off = (void *)data_ptr - page_address(page);
 876         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 877         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 878                payload + NET_IP_ALIGN);
 879
 880         frag = &skb_shinfo(skb)->frags[0];
 881         skb_frag_size_sub(frag, payload);
 882         frag->page_offset += payload;
 883         skb->data_len -= payload;
 884         skb->tail += payload;
 885
 886         return skb;
 887 }
 888
 889 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 890                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 891                                    void *data, u8 *data_ptr,
 892                                    dma_addr_t dma_addr,
 893                                    unsigned int offset_and_len)
 894 {
 895         u16 prod = rxr->rx_prod;
 896         struct sk_buff *skb;
 897         int err;
 898
 899         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 900         if (unlikely(err)) {
 901                 bnxt_reuse_rx_data(rxr, cons, data);
 902                 return NULL;
 903         }
 904
 905         skb = build_skb(data, 0);
 906         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 907                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 908         if (!skb) {
 909                 kfree(data);
 910                 return NULL;
 911         }
 912
 913         skb_reserve(skb, bp->rx_offset);
 914         skb_put(skb, offset_and_len & 0xffff);
 915         return skb;
 916 }
 917
 918 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 919                                      struct sk_buff *skb, u16 cp_cons,
 920                                      u32 agg_bufs)
 921 {
 922         struct pci_dev *pdev = bp->pdev;
 923         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 924         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 925         u16 prod = rxr->rx_agg_prod;
 926         u32 i;
 927
 928         for (i = 0; i < agg_bufs; i++) {
 929                 u16 cons, frag_len;
 930                 struct rx_agg_cmp *agg;
 931                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 932                 struct page *page;
 933                 dma_addr_t mapping;
 934
 935                 agg = (struct rx_agg_cmp *)
 936                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 937                 cons = agg->rx_agg_cmp_opaque;
 938                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 939                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 940
 941                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 942                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 943                                    cons_rx_buf->offset, frag_len);
 944                 __clear_bit(cons, rxr->rx_agg_bmap);
 945
 946                 /* It is possible for bnxt_alloc_rx_page() to allocate
 947                  * a sw_prod index that equals the cons index, so we
 948                  * need to clear the cons entry now.
 949                  */
 950                 mapping = cons_rx_buf->mapping;
 951                 page = cons_rx_buf->page;
 952                 cons_rx_buf->page = NULL;
 953
 954                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 955                         struct skb_shared_info *shinfo;
 956                         unsigned int nr_frags;
 957
 958                         shinfo = skb_shinfo(skb);
 959                         nr_frags = --shinfo->nr_frags;
 960                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 961
 962                         dev_kfree_skb(skb);
 963
 964                         cons_rx_buf->page = page;
 965
 966                         /* Update prod since possibly some pages have been
 967                          * allocated already.
 968                          */
 969                         rxr->rx_agg_prod = prod;
 970                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 971                         return NULL;
 972                 }
 973
 974                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 975                                      PCI_DMA_FROMDEVICE,
 976                                      DMA_ATTR_WEAK_ORDERING);
 977
 978                 skb->data_len += frag_len;
 979                 skb->len += frag_len;
 980                 skb->truesize += PAGE_SIZE;
 981
 982                 prod = NEXT_RX_AGG(prod);
 983                 cp_cons = NEXT_CMP(cp_cons);
 984         }
 985         rxr->rx_agg_prod = prod;
 986         return skb;
 987 }
 988
 989 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 990                                u8 agg_bufs, u32 *raw_cons)
 991 {
 992         u16 last;
 993         struct rx_agg_cmp *agg;
 994
 995         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 996         last = RING_CMP(*raw_cons);
 997         agg = (struct rx_agg_cmp *)
 998                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 999         return RX_AGG_CMP_VALID(agg, *raw_cons);
1000 }
1001
1002 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1003                                             unsigned int len,
1004                                             dma_addr_t mapping)
1005 {
1006         struct bnxt *bp = bnapi->bp;
1007         struct pci_dev *pdev = bp->pdev;
1008         struct sk_buff *skb;
1009
1010         skb = napi_alloc_skb(&bnapi->napi, len);
1011         if (!skb)
1012                 return NULL;
1013
1014         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1015                                 bp->rx_dir);
1016
1017         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1018                len + NET_IP_ALIGN);
1019
1020         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1021                                    bp->rx_dir);
1022
1023         skb_put(skb, len);
1024         return skb;
1025 }
1026
1027 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1028                            u32 *raw_cons, void *cmp)
1029 {
1030         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1031         struct rx_cmp *rxcmp = cmp;
1032         u32 tmp_raw_cons = *raw_cons;
1033         u8 cmp_type, agg_bufs = 0;
1034
1035         cmp_type = RX_CMP_TYPE(rxcmp);
1036
1037         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1038                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1039                             RX_CMP_AGG_BUFS) >>
1040                            RX_CMP_AGG_BUFS_SHIFT;
1041         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1042                 struct rx_tpa_end_cmp *tpa_end = cmp;
1043
1044                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1045                             RX_TPA_END_CMP_AGG_BUFS) >>
1046                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1047         }
1048
1049         if (agg_bufs) {
1050                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1051                         return -EBUSY;
1052         }
1053         *raw_cons = tmp_raw_cons;
1054         return 0;
1055 }
1056
1057 static void bnxt_queue_sp_work(struct bnxt *bp)
1058 {
1059         if (BNXT_PF(bp))
1060                 queue_work(bnxt_pf_wq, &bp->sp_task);
1061         else
1062                 schedule_work(&bp->sp_task);
1063 }
1064
1065 static void bnxt_cancel_sp_work(struct bnxt *bp)
1066 {
1067         if (BNXT_PF(bp))
1068                 flush_workqueue(bnxt_pf_wq);
1069         else
1070                 cancel_work_sync(&bp->sp_task);
1071 }
1072
1073 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1074 {
1075         if (!rxr->bnapi->in_reset) {
1076                 rxr->bnapi->in_reset = true;
1077                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1078                 bnxt_queue_sp_work(bp);
1079         }
1080         rxr->rx_next_cons = 0xffff;
1081 }
1082
1083 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1084                            struct rx_tpa_start_cmp *tpa_start,
1085                            struct rx_tpa_start_cmp_ext *tpa_start1)
1086 {
1087         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1088         u16 cons, prod;
1089         struct bnxt_tpa_info *tpa_info;
1090         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1091         struct rx_bd *prod_bd;
1092         dma_addr_t mapping;
1093
1094         cons = tpa_start->rx_tpa_start_cmp_opaque;
1095         prod = rxr->rx_prod;
1096         cons_rx_buf = &rxr->rx_buf_ring[cons];
1097         prod_rx_buf = &rxr->rx_buf_ring[prod];
1098         tpa_info = &rxr->rx_tpa[agg_id];
1099
1100         if (unlikely(cons != rxr->rx_next_cons)) {
1101                 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1102                             cons, rxr->rx_next_cons);
1103                 bnxt_sched_reset(bp, rxr);
1104                 return;
1105         }
1106         /* Store cfa_code in tpa_info to use in tpa_end
1107          * completion processing.
1108          */
1109         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1110         prod_rx_buf->data = tpa_info->data;
1111         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1112
1113         mapping = tpa_info->mapping;
1114         prod_rx_buf->mapping = mapping;
1115
1116         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1117
1118         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1119
1120         tpa_info->data = cons_rx_buf->data;
1121         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1122         cons_rx_buf->data = NULL;
1123         tpa_info->mapping = cons_rx_buf->mapping;
1124
1125         tpa_info->len =
1126                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1127                                 RX_TPA_START_CMP_LEN_SHIFT;
1128         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1129                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1130
1131                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1132                 tpa_info->gso_type = SKB_GSO_TCPV4;
1133                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1134                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1135                         tpa_info->gso_type = SKB_GSO_TCPV6;
1136                 tpa_info->rss_hash =
1137                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1138         } else {
1139                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1140                 tpa_info->gso_type = 0;
1141                 if (netif_msg_rx_err(bp))
1142                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1143         }
1144         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1145         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1146         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1147
1148         rxr->rx_prod = NEXT_RX(prod);
1149         cons = NEXT_RX(cons);
1150         rxr->rx_next_cons = NEXT_RX(cons);
1151         cons_rx_buf = &rxr->rx_buf_ring[cons];
1152
1153         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1154         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1155         cons_rx_buf->data = NULL;
1156 }
1157
1158 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1159                            u16 cp_cons, u32 agg_bufs)
1160 {
1161         if (agg_bufs)
1162                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1163 }
1164
1165 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1166                                            int payload_off, int tcp_ts,
1167                                            struct sk_buff *skb)
1168 {
1169 #ifdef CONFIG_INET
1170         struct tcphdr *th;
1171         int len, nw_off;
1172         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1173         u32 hdr_info = tpa_info->hdr_info;
1174         bool loopback = false;
1175
1176         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1177         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1178         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1179
1180         /* If the packet is an internal loopback packet, the offsets will
1181          * have an extra 4 bytes.
1182          */
1183         if (inner_mac_off == 4) {
1184                 loopback = true;
1185         } else if (inner_mac_off > 4) {
1186                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1187                                             ETH_HLEN - 2));
1188
1189                 /* We only support inner iPv4/ipv6.  If we don't see the
1190                  * correct protocol ID, it must be a loopback packet where
1191                  * the offsets are off by 4.
1192                  */
1193                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1194                         loopback = true;
1195         }
1196         if (loopback) {
1197                 /* internal loopback packet, subtract all offsets by 4 */
1198                 inner_ip_off -= 4;
1199                 inner_mac_off -= 4;
1200                 outer_ip_off -= 4;
1201         }
1202
1203         nw_off = inner_ip_off - ETH_HLEN;
1204         skb_set_network_header(skb, nw_off);
1205         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1206                 struct ipv6hdr *iph = ipv6_hdr(skb);
1207
1208                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1209                 len = skb->len - skb_transport_offset(skb);
1210                 th = tcp_hdr(skb);
1211                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1212         } else {
1213                 struct iphdr *iph = ip_hdr(skb);
1214
1215                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1216                 len = skb->len - skb_transport_offset(skb);
1217                 th = tcp_hdr(skb);
1218                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1219         }
1220
1221         if (inner_mac_off) { /* tunnel */
1222                 struct udphdr *uh = NULL;
1223                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1224                                             ETH_HLEN - 2));
1225
1226                 if (proto == htons(ETH_P_IP)) {
1227                         struct iphdr *iph = (struct iphdr *)skb->data;
1228
1229                         if (iph->protocol == IPPROTO_UDP)
1230                                 uh = (struct udphdr *)(iph + 1);
1231                 } else {
1232                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1233
1234                         if (iph->nexthdr == IPPROTO_UDP)
1235                                 uh = (struct udphdr *)(iph + 1);
1236                 }
1237                 if (uh) {
1238                         if (uh->check)
1239                                 skb_shinfo(skb)->gso_type |=
1240                                         SKB_GSO_UDP_TUNNEL_CSUM;
1241                         else
1242                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1243                 }
1244         }
1245 #endif
1246         return skb;
1247 }
1248
1249 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1250 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1251
1252 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1253                                            int payload_off, int tcp_ts,
1254                                            struct sk_buff *skb)
1255 {
1256 #ifdef CONFIG_INET
1257         struct tcphdr *th;
1258         int len, nw_off, tcp_opt_len = 0;
1259
1260         if (tcp_ts)
1261                 tcp_opt_len = 12;
1262
1263         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1264                 struct iphdr *iph;
1265
1266                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1267                          ETH_HLEN;
1268                 skb_set_network_header(skb, nw_off);
1269                 iph = ip_hdr(skb);
1270                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1271                 len = skb->len - skb_transport_offset(skb);
1272                 th = tcp_hdr(skb);
1273                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1274         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1275                 struct ipv6hdr *iph;
1276
1277                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1278                          ETH_HLEN;
1279                 skb_set_network_header(skb, nw_off);
1280                 iph = ipv6_hdr(skb);
1281                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1282                 len = skb->len - skb_transport_offset(skb);
1283                 th = tcp_hdr(skb);
1284                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1285         } else {
1286                 dev_kfree_skb_any(skb);
1287                 return NULL;
1288         }
1289
1290         if (nw_off) { /* tunnel */
1291                 struct udphdr *uh = NULL;
1292
1293                 if (skb->protocol == htons(ETH_P_IP)) {
1294                         struct iphdr *iph = (struct iphdr *)skb->data;
1295
1296                         if (iph->protocol == IPPROTO_UDP)
1297                                 uh = (struct udphdr *)(iph + 1);
1298                 } else {
1299                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1300
1301                         if (iph->nexthdr == IPPROTO_UDP)
1302                                 uh = (struct udphdr *)(iph + 1);
1303                 }
1304                 if (uh) {
1305                         if (uh->check)
1306                                 skb_shinfo(skb)->gso_type |=
1307                                         SKB_GSO_UDP_TUNNEL_CSUM;
1308                         else
1309                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1310                 }
1311         }
1312 #endif
1313         return skb;
1314 }
1315
1316 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1317                                            struct bnxt_tpa_info *tpa_info,
1318                                            struct rx_tpa_end_cmp *tpa_end,
1319                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1320                                            struct sk_buff *skb)
1321 {
1322 #ifdef CONFIG_INET
1323         int payload_off;
1324         u16 segs;
1325
1326         segs = TPA_END_TPA_SEGS(tpa_end);
1327         if (segs == 1)
1328                 return skb;
1329
1330         NAPI_GRO_CB(skb)->count = segs;
1331         skb_shinfo(skb)->gso_size =
1332                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1333         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1334         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1335                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1336                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1337         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1338         if (likely(skb))
1339                 tcp_gro_complete(skb);
1340 #endif
1341         return skb;
1342 }
1343
1344 /* Given the cfa_code of a received packet determine which
1345  * netdev (vf-rep or PF) the packet is destined to.
1346  */
1347 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1348 {
1349         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1350
1351         /* if vf-rep dev is NULL, the must belongs to the PF */
1352         return dev ? dev : bp->dev;
1353 }
1354
1355 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1356                                            struct bnxt_napi *bnapi,
1357                                            u32 *raw_cons,
1358                                            struct rx_tpa_end_cmp *tpa_end,
1359                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1360                                            u8 *event)
1361 {
1362         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1363         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1364         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1365         u8 *data_ptr, agg_bufs;
1366         u16 cp_cons = RING_CMP(*raw_cons);
1367         unsigned int len;
1368         struct bnxt_tpa_info *tpa_info;
1369         dma_addr_t mapping;
1370         struct sk_buff *skb;
1371         void *data;
1372
1373         if (unlikely(bnapi->in_reset)) {
1374                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1375
1376                 if (rc < 0)
1377                         return ERR_PTR(-EBUSY);
1378                 return NULL;
1379         }
1380
1381         tpa_info = &rxr->rx_tpa[agg_id];
1382         data = tpa_info->data;
1383         data_ptr = tpa_info->data_ptr;
1384         prefetch(data_ptr);
1385         len = tpa_info->len;
1386         mapping = tpa_info->mapping;
1387
1388         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1389                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1390
1391         if (agg_bufs) {
1392                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1393                         return ERR_PTR(-EBUSY);
1394
1395                 *event |= BNXT_AGG_EVENT;
1396                 cp_cons = NEXT_CMP(cp_cons);
1397         }
1398
1399         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1400                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1401                 if (agg_bufs > MAX_SKB_FRAGS)
1402                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1403                                     agg_bufs, (int)MAX_SKB_FRAGS);
1404                 return NULL;
1405         }
1406
1407         if (len <= bp->rx_copy_thresh) {
1408                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1409                 if (!skb) {
1410                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1411                         return NULL;
1412                 }
1413         } else {
1414                 u8 *new_data;
1415                 dma_addr_t new_mapping;
1416
1417                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1418                 if (!new_data) {
1419                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1420                         return NULL;
1421                 }
1422
1423                 tpa_info->data = new_data;
1424                 tpa_info->data_ptr = new_data + bp->rx_offset;
1425                 tpa_info->mapping = new_mapping;
1426
1427                 skb = build_skb(data, 0);
1428                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1429                                        bp->rx_buf_use_size, bp->rx_dir,
1430                                        DMA_ATTR_WEAK_ORDERING);
1431
1432                 if (!skb) {
1433                         kfree(data);
1434                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1435                         return NULL;
1436                 }
1437                 skb_reserve(skb, bp->rx_offset);
1438                 skb_put(skb, len);
1439         }
1440
1441         if (agg_bufs) {
1442                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1443                 if (!skb) {
1444                         /* Page reuse already handled by bnxt_rx_pages(). */
1445                         return NULL;
1446                 }
1447         }
1448
1449         skb->protocol =
1450                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1451
1452         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1453                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1454
1455         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1456             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1457                 u16 vlan_proto = tpa_info->metadata >>
1458                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1459                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1460
1461                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1462         }
1463
1464         skb_checksum_none_assert(skb);
1465         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1466                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1467                 skb->csum_level =
1468                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1469         }
1470
1471         if (TPA_END_GRO(tpa_end))
1472                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1473
1474         return skb;
1475 }
1476
1477 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1478                              struct sk_buff *skb)
1479 {
1480         if (skb->dev != bp->dev) {
1481                 /* this packet belongs to a vf-rep */
1482                 bnxt_vf_rep_rx(bp, skb);
1483                 return;
1484         }
1485         skb_record_rx_queue(skb, bnapi->index);
1486         napi_gro_receive(&bnapi->napi, skb);
1487 }
1488
1489 /* returns the following:
1490  * 1       - 1 packet successfully received
1491  * 0       - successful TPA_START, packet not completed yet
1492  * -EBUSY  - completion ring does not have all the agg buffers yet
1493  * -ENOMEM - packet aborted due to out of memory
1494  * -EIO    - packet aborted due to hw error indicated in BD
1495  */
1496 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1497                        u8 *event)
1498 {
1499         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1500         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1501         struct net_device *dev = bp->dev;
1502         struct rx_cmp *rxcmp;
1503         struct rx_cmp_ext *rxcmp1;
1504         u32 tmp_raw_cons = *raw_cons;
1505         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1506         struct bnxt_sw_rx_bd *rx_buf;
1507         unsigned int len;
1508         u8 *data_ptr, agg_bufs, cmp_type;
1509         dma_addr_t dma_addr;
1510         struct sk_buff *skb;
1511         void *data;
1512         int rc = 0;
1513         u32 misc;
1514
1515         rxcmp = (struct rx_cmp *)
1516                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1517
1518         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1519         cp_cons = RING_CMP(tmp_raw_cons);
1520         rxcmp1 = (struct rx_cmp_ext *)
1521                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1522
1523         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1524                 return -EBUSY;
1525
1526         cmp_type = RX_CMP_TYPE(rxcmp);
1527
1528         prod = rxr->rx_prod;
1529
1530         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1531                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1532                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1533
1534                 *event |= BNXT_RX_EVENT;
1535                 goto next_rx_no_prod_no_len;
1536
1537         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1538                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1539                                    (struct rx_tpa_end_cmp *)rxcmp,
1540                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1541
1542                 if (IS_ERR(skb))
1543                         return -EBUSY;
1544
1545                 rc = -ENOMEM;
1546                 if (likely(skb)) {
1547                         bnxt_deliver_skb(bp, bnapi, skb);
1548                         rc = 1;
1549                 }
1550                 *event |= BNXT_RX_EVENT;
1551                 goto next_rx_no_prod_no_len;
1552         }
1553
1554         cons = rxcmp->rx_cmp_opaque;
1555         if (unlikely(cons != rxr->rx_next_cons)) {
1556                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1557
1558                 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1559                             cons, rxr->rx_next_cons);
1560                 bnxt_sched_reset(bp, rxr);
1561                 return rc1;
1562         }
1563         rx_buf = &rxr->rx_buf_ring[cons];
1564         data = rx_buf->data;
1565         data_ptr = rx_buf->data_ptr;
1566         prefetch(data_ptr);
1567
1568         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1569         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1570
1571         if (agg_bufs) {
1572                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1573                         return -EBUSY;
1574
1575                 cp_cons = NEXT_CMP(cp_cons);
1576                 *event |= BNXT_AGG_EVENT;
1577         }
1578         *event |= BNXT_RX_EVENT;
1579
1580         rx_buf->data = NULL;
1581         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1582                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1583
1584                 bnxt_reuse_rx_data(rxr, cons, data);
1585                 if (agg_bufs)
1586                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1587
1588                 rc = -EIO;
1589                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1590                         netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1591                         bnxt_sched_reset(bp, rxr);
1592                 }
1593                 goto next_rx_no_len;
1594         }
1595
1596         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1597         dma_addr = rx_buf->mapping;
1598
1599         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1600                 rc = 1;
1601                 goto next_rx;
1602         }
1603
1604         if (len <= bp->rx_copy_thresh) {
1605                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1606                 bnxt_reuse_rx_data(rxr, cons, data);
1607                 if (!skb) {
1608                         if (agg_bufs)
1609                                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1610                         rc = -ENOMEM;
1611                         goto next_rx;
1612                 }
1613         } else {
1614                 u32 payload;
1615
1616                 if (rx_buf->data_ptr == data_ptr)
1617                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1618                 else
1619                         payload = 0;
1620                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1621                                       payload | len);
1622                 if (!skb) {
1623                         rc = -ENOMEM;
1624                         goto next_rx;
1625                 }
1626         }
1627
1628         if (agg_bufs) {
1629                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1630                 if (!skb) {
1631                         rc = -ENOMEM;
1632                         goto next_rx;
1633                 }
1634         }
1635
1636         if (RX_CMP_HASH_VALID(rxcmp)) {
1637                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1638                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1639
1640                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1641                 if (hash_type != 1 && hash_type != 3)
1642                         type = PKT_HASH_TYPE_L3;
1643                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1644         }
1645
1646         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1647         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1648
1649         if ((rxcmp1->rx_cmp_flags2 &
1650              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1651             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1652                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1653                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1654                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1655
1656                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1657         }
1658
1659         skb_checksum_none_assert(skb);
1660         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1661                 if (dev->features & NETIF_F_RXCSUM) {
1662                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1663                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1664                 }
1665         } else {
1666                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1667                         if (dev->features & NETIF_F_RXCSUM)
1668                                 cpr->rx_l4_csum_errors++;
1669                 }
1670         }
1671
1672         bnxt_deliver_skb(bp, bnapi, skb);
1673         rc = 1;
1674
1675 next_rx:
1676         cpr->rx_packets += 1;
1677         cpr->rx_bytes += len;
1678
1679 next_rx_no_len:
1680         rxr->rx_prod = NEXT_RX(prod);
1681         rxr->rx_next_cons = NEXT_RX(cons);
1682
1683 next_rx_no_prod_no_len:
1684         *raw_cons = tmp_raw_cons;
1685
1686         return rc;
1687 }
1688
1689 /* In netpoll mode, if we are using a combined completion ring, we need to
1690  * discard the rx packets and recycle the buffers.
1691  */
1692 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1693                                  u32 *raw_cons, u8 *event)
1694 {
1695         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1696         u32 tmp_raw_cons = *raw_cons;
1697         struct rx_cmp_ext *rxcmp1;
1698         struct rx_cmp *rxcmp;
1699         u16 cp_cons;
1700         u8 cmp_type;
1701
1702         cp_cons = RING_CMP(tmp_raw_cons);
1703         rxcmp = (struct rx_cmp *)
1704                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1705
1706         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1707         cp_cons = RING_CMP(tmp_raw_cons);
1708         rxcmp1 = (struct rx_cmp_ext *)
1709                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1710
1711         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1712                 return -EBUSY;
1713
1714         cmp_type = RX_CMP_TYPE(rxcmp);
1715         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1716                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1717                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1718         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1719                 struct rx_tpa_end_cmp_ext *tpa_end1;
1720
1721                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1722                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1723                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1724         }
1725         return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1726 }
1727
1728 #define BNXT_GET_EVENT_PORT(data)       \
1729         ((data) &                       \
1730          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1731
1732 static int bnxt_async_event_process(struct bnxt *bp,
1733                                     struct hwrm_async_event_cmpl *cmpl)
1734 {
1735         u16 event_id = le16_to_cpu(cmpl->event_id);
1736
1737         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1738         switch (event_id) {
1739         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1740                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1741                 struct bnxt_link_info *link_info = &bp->link_info;
1742
1743                 if (BNXT_VF(bp))
1744                         goto async_event_process_exit;
1745
1746                 /* print unsupported speed warning in forced speed mode only */
1747                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1748                     (data1 & 0x20000)) {
1749                         u16 fw_speed = link_info->force_link_speed;
1750                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1751
1752                         if (speed != SPEED_UNKNOWN)
1753                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1754                                             speed);
1755                 }
1756                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1757         }
1758         /* fall through */
1759         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1760                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1761                 break;
1762         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1763                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1764                 break;
1765         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1766                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1767                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1768
1769                 if (BNXT_VF(bp))
1770                         break;
1771
1772                 if (bp->pf.port_id != port_id)
1773                         break;
1774
1775                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1776                 break;
1777         }
1778         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1779                 if (BNXT_PF(bp))
1780                         goto async_event_process_exit;
1781                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1782                 break;
1783         default:
1784                 goto async_event_process_exit;
1785         }
1786         bnxt_queue_sp_work(bp);
1787 async_event_process_exit:
1788         bnxt_ulp_async_events(bp, cmpl);
1789         return 0;
1790 }
1791
1792 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1793 {
1794         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1795         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1796         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1797                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1798
1799         switch (cmpl_type) {
1800         case CMPL_BASE_TYPE_HWRM_DONE:
1801                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1802                 if (seq_id == bp->hwrm_intr_seq_id)
1803                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1804                 else
1805                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1806                 break;
1807
1808         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1809                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1810
1811                 if ((vf_id < bp->pf.first_vf_id) ||
1812                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1813                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1814                                    vf_id);
1815                         return -EINVAL;
1816                 }
1817
1818                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1819                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1820                 bnxt_queue_sp_work(bp);
1821                 break;
1822
1823         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1824                 bnxt_async_event_process(bp,
1825                                          (struct hwrm_async_event_cmpl *)txcmp);
1826
1827         default:
1828                 break;
1829         }
1830
1831         return 0;
1832 }
1833
1834 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1835 {
1836         struct bnxt_napi *bnapi = dev_instance;
1837         struct bnxt *bp = bnapi->bp;
1838         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1839         u32 cons = RING_CMP(cpr->cp_raw_cons);
1840
1841         cpr->event_ctr++;
1842         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1843         napi_schedule(&bnapi->napi);
1844         return IRQ_HANDLED;
1845 }
1846
1847 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1848 {
1849         u32 raw_cons = cpr->cp_raw_cons;
1850         u16 cons = RING_CMP(raw_cons);
1851         struct tx_cmp *txcmp;
1852
1853         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1854
1855         return TX_CMP_VALID(txcmp, raw_cons);
1856 }
1857
1858 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1859 {
1860         struct bnxt_napi *bnapi = dev_instance;
1861         struct bnxt *bp = bnapi->bp;
1862         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1863         u32 cons = RING_CMP(cpr->cp_raw_cons);
1864         u32 int_status;
1865
1866         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1867
1868         if (!bnxt_has_work(bp, cpr)) {
1869                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1870                 /* return if erroneous interrupt */
1871                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1872                         return IRQ_NONE;
1873         }
1874
1875         /* disable ring IRQ */
1876         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1877
1878         /* Return here if interrupt is shared and is disabled. */
1879         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1880                 return IRQ_HANDLED;
1881
1882         napi_schedule(&bnapi->napi);
1883         return IRQ_HANDLED;
1884 }
1885
1886 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1887 {
1888         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1889         u32 raw_cons = cpr->cp_raw_cons;
1890         u32 cons;
1891         int tx_pkts = 0;
1892         int rx_pkts = 0;
1893         u8 event = 0;
1894         struct tx_cmp *txcmp;
1895
1896         while (1) {
1897                 int rc;
1898
1899                 cons = RING_CMP(raw_cons);
1900                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1901
1902                 if (!TX_CMP_VALID(txcmp, raw_cons))
1903                         break;
1904
1905                 /* The valid test of the entry must be done first before
1906                  * reading any further.
1907                  */
1908                 dma_rmb();
1909                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1910                         tx_pkts++;
1911                         /* return full budget so NAPI will complete. */
1912                         if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
1913                                 rx_pkts = budget;
1914                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1915                                 break;
1916                         }
1917                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1918                         if (likely(budget))
1919                                 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1920                         else
1921                                 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1922                                                            &event);
1923                         if (likely(rc >= 0))
1924                                 rx_pkts += rc;
1925                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1926                          * the NAPI budget.  Otherwise, we may potentially loop
1927                          * here forever if we consistently cannot allocate
1928                          * buffers.
1929                          */
1930                         else if (rc == -ENOMEM && budget)
1931                                 rx_pkts++;
1932                         else if (rc == -EBUSY)  /* partial completion */
1933                                 break;
1934                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1935                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1936                                     (TX_CMP_TYPE(txcmp) ==
1937                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1938                                     (TX_CMP_TYPE(txcmp) ==
1939                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1940                         bnxt_hwrm_handler(bp, txcmp);
1941                 }
1942                 raw_cons = NEXT_RAW_CMP(raw_cons);
1943
1944                 if (rx_pkts && rx_pkts == budget)
1945                         break;
1946         }
1947
1948         if (event & BNXT_TX_EVENT) {
1949                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1950                 void __iomem *db = txr->tx_doorbell;
1951                 u16 prod = txr->tx_prod;
1952
1953                 /* Sync BD data before updating doorbell */
1954                 wmb();
1955
1956                 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod);
1957         }
1958
1959         cpr->cp_raw_cons = raw_cons;
1960         /* ACK completion ring before freeing tx ring and producing new
1961          * buffers in rx/agg rings to prevent overflowing the completion
1962          * ring.
1963          */
1964         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1965
1966         if (tx_pkts)
1967                 bnapi->tx_int(bp, bnapi, tx_pkts);
1968
1969         if (event & BNXT_RX_EVENT) {
1970                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1971
1972                 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1973                 if (event & BNXT_AGG_EVENT)
1974                         bnxt_db_write(bp, rxr->rx_agg_doorbell,
1975                                       DB_KEY_RX | rxr->rx_agg_prod);
1976         }
1977         return rx_pkts;
1978 }
1979
1980 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1981 {
1982         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1983         struct bnxt *bp = bnapi->bp;
1984         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1985         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1986         struct tx_cmp *txcmp;
1987         struct rx_cmp_ext *rxcmp1;
1988         u32 cp_cons, tmp_raw_cons;
1989         u32 raw_cons = cpr->cp_raw_cons;
1990         u32 rx_pkts = 0;
1991         u8 event = 0;
1992
1993         while (1) {
1994                 int rc;
1995
1996                 cp_cons = RING_CMP(raw_cons);
1997                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1998
1999                 if (!TX_CMP_VALID(txcmp, raw_cons))
2000                         break;
2001
2002                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2003                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2004                         cp_cons = RING_CMP(tmp_raw_cons);
2005                         rxcmp1 = (struct rx_cmp_ext *)
2006                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2007
2008                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2009                                 break;
2010
2011                         /* force an error to recycle the buffer */
2012                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2013                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2014
2015                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
2016                         if (likely(rc == -EIO) && budget)
2017                                 rx_pkts++;
2018                         else if (rc == -EBUSY)  /* partial completion */
2019                                 break;
2020                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2021                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2022                         bnxt_hwrm_handler(bp, txcmp);
2023                 } else {
2024                         netdev_err(bp->dev,
2025                                    "Invalid completion received on special ring\n");
2026                 }
2027                 raw_cons = NEXT_RAW_CMP(raw_cons);
2028
2029                 if (rx_pkts == budget)
2030                         break;
2031         }
2032
2033         cpr->cp_raw_cons = raw_cons;
2034         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2035         bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2036
2037         if (event & BNXT_AGG_EVENT)
2038                 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2039                               DB_KEY_RX | rxr->rx_agg_prod);
2040
2041         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2042                 napi_complete_done(napi, rx_pkts);
2043                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2044         }
2045         return rx_pkts;
2046 }
2047
2048 static int bnxt_poll(struct napi_struct *napi, int budget)
2049 {
2050         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2051         struct bnxt *bp = bnapi->bp;
2052         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2053         int work_done = 0;
2054
2055         while (1) {
2056                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2057
2058                 if (work_done >= budget) {
2059                         if (!budget)
2060                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2061                                                  cpr->cp_raw_cons);
2062                         break;
2063                 }
2064
2065                 if (!bnxt_has_work(bp, cpr)) {
2066                         if (napi_complete_done(napi, work_done))
2067                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2068                                                  cpr->cp_raw_cons);
2069                         break;
2070                 }
2071         }
2072         if (bp->flags & BNXT_FLAG_DIM) {
2073                 struct net_dim_sample dim_sample;
2074
2075                 net_dim_sample(cpr->event_ctr,
2076                                cpr->rx_packets,
2077                                cpr->rx_bytes,
2078                                &dim_sample);
2079                 net_dim(&cpr->dim, dim_sample);
2080         }
2081         mmiowb();
2082         return work_done;
2083 }
2084
2085 static void bnxt_free_tx_skbs(struct bnxt *bp)
2086 {
2087         int i, max_idx;
2088         struct pci_dev *pdev = bp->pdev;
2089
2090         if (!bp->tx_ring)
2091                 return;
2092
2093         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2094         for (i = 0; i < bp->tx_nr_rings; i++) {
2095                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2096                 int j;
2097
2098                 for (j = 0; j < max_idx;) {
2099                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2100                         struct sk_buff *skb = tx_buf->skb;
2101                         int k, last;
2102
2103                         if (!skb) {
2104                                 j++;
2105                                 continue;
2106                         }
2107
2108                         tx_buf->skb = NULL;
2109
2110                         if (tx_buf->is_push) {
2111                                 dev_kfree_skb(skb);
2112                                 j += 2;
2113                                 continue;
2114                         }
2115
2116                         dma_unmap_single(&pdev->dev,
2117                                          dma_unmap_addr(tx_buf, mapping),
2118                                          skb_headlen(skb),
2119                                          PCI_DMA_TODEVICE);
2120
2121                         last = tx_buf->nr_frags;
2122                         j += 2;
2123                         for (k = 0; k < last; k++, j++) {
2124                                 int ring_idx = j & bp->tx_ring_mask;
2125                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2126
2127                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2128                                 dma_unmap_page(
2129                                         &pdev->dev,
2130                                         dma_unmap_addr(tx_buf, mapping),
2131                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2132                         }
2133                         dev_kfree_skb(skb);
2134                 }
2135                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2136         }
2137 }
2138
2139 static void bnxt_free_rx_skbs(struct bnxt *bp)
2140 {
2141         int i, max_idx, max_agg_idx;
2142         struct pci_dev *pdev = bp->pdev;
2143
2144         if (!bp->rx_ring)
2145                 return;
2146
2147         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2148         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2149         for (i = 0; i < bp->rx_nr_rings; i++) {
2150                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2151                 int j;
2152
2153                 if (rxr->rx_tpa) {
2154                         for (j = 0; j < MAX_TPA; j++) {
2155                                 struct bnxt_tpa_info *tpa_info =
2156                                                         &rxr->rx_tpa[j];
2157                                 u8 *data = tpa_info->data;
2158
2159                                 if (!data)
2160                                         continue;
2161
2162                                 dma_unmap_single_attrs(&pdev->dev,
2163                                                        tpa_info->mapping,
2164                                                        bp->rx_buf_use_size,
2165                                                        bp->rx_dir,
2166                                                        DMA_ATTR_WEAK_ORDERING);
2167
2168                                 tpa_info->data = NULL;
2169
2170                                 kfree(data);
2171                         }
2172                 }
2173
2174                 for (j = 0; j < max_idx; j++) {
2175                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2176                         dma_addr_t mapping = rx_buf->mapping;
2177                         void *data = rx_buf->data;
2178
2179                         if (!data)
2180                                 continue;
2181
2182                         rx_buf->data = NULL;
2183
2184                         if (BNXT_RX_PAGE_MODE(bp)) {
2185                                 mapping -= bp->rx_dma_offset;
2186                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2187                                                      PAGE_SIZE, bp->rx_dir,
2188                                                      DMA_ATTR_WEAK_ORDERING);
2189                                 __free_page(data);
2190                         } else {
2191                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2192                                                        bp->rx_buf_use_size,
2193                                                        bp->rx_dir,
2194                                                        DMA_ATTR_WEAK_ORDERING);
2195                                 kfree(data);
2196                         }
2197                 }
2198
2199                 for (j = 0; j < max_agg_idx; j++) {
2200                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2201                                 &rxr->rx_agg_ring[j];
2202                         struct page *page = rx_agg_buf->page;
2203
2204                         if (!page)
2205                                 continue;
2206
2207                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2208                                              BNXT_RX_PAGE_SIZE,
2209                                              PCI_DMA_FROMDEVICE,
2210                                              DMA_ATTR_WEAK_ORDERING);
2211
2212                         rx_agg_buf->page = NULL;
2213                         __clear_bit(j, rxr->rx_agg_bmap);
2214
2215                         __free_page(page);
2216                 }
2217                 if (rxr->rx_page) {
2218                         __free_page(rxr->rx_page);
2219                         rxr->rx_page = NULL;
2220                 }
2221         }
2222 }
2223
2224 static void bnxt_free_skbs(struct bnxt *bp)
2225 {
2226         bnxt_free_tx_skbs(bp);
2227         bnxt_free_rx_skbs(bp);
2228 }
2229
2230 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2231 {
2232         struct pci_dev *pdev = bp->pdev;
2233         int i;
2234
2235         for (i = 0; i < ring->nr_pages; i++) {
2236                 if (!ring->pg_arr[i])
2237                         continue;
2238
2239                 dma_free_coherent(&pdev->dev, ring->page_size,
2240                                   ring->pg_arr[i], ring->dma_arr[i]);
2241
2242                 ring->pg_arr[i] = NULL;
2243         }
2244         if (ring->pg_tbl) {
2245                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2246                                   ring->pg_tbl, ring->pg_tbl_map);
2247                 ring->pg_tbl = NULL;
2248         }
2249         if (ring->vmem_size && *ring->vmem) {
2250                 vfree(*ring->vmem);
2251                 *ring->vmem = NULL;
2252         }
2253 }
2254
2255 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2256 {
2257         int i;
2258         struct pci_dev *pdev = bp->pdev;
2259
2260         if (ring->nr_pages > 1) {
2261                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2262                                                   ring->nr_pages * 8,
2263                                                   &ring->pg_tbl_map,
2264                                                   GFP_KERNEL);
2265                 if (!ring->pg_tbl)
2266                         return -ENOMEM;
2267         }
2268
2269         for (i = 0; i < ring->nr_pages; i++) {
2270                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2271                                                      ring->page_size,
2272                                                      &ring->dma_arr[i],
2273                                                      GFP_KERNEL);
2274                 if (!ring->pg_arr[i])
2275                         return -ENOMEM;
2276
2277                 if (ring->nr_pages > 1)
2278                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2279         }
2280
2281         if (ring->vmem_size) {
2282                 *ring->vmem = vzalloc(ring->vmem_size);
2283                 if (!(*ring->vmem))
2284                         return -ENOMEM;
2285         }
2286         return 0;
2287 }
2288
2289 static void bnxt_free_rx_rings(struct bnxt *bp)
2290 {
2291         int i;
2292
2293         if (!bp->rx_ring)
2294                 return;
2295
2296         for (i = 0; i < bp->rx_nr_rings; i++) {
2297                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2298                 struct bnxt_ring_struct *ring;
2299
2300                 if (rxr->xdp_prog)
2301                         bpf_prog_put(rxr->xdp_prog);
2302
2303                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2304                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2305
2306                 kfree(rxr->rx_tpa);
2307                 rxr->rx_tpa = NULL;
2308
2309                 kfree(rxr->rx_agg_bmap);
2310                 rxr->rx_agg_bmap = NULL;
2311
2312                 ring = &rxr->rx_ring_struct;
2313                 bnxt_free_ring(bp, ring);
2314
2315                 ring = &rxr->rx_agg_ring_struct;
2316                 bnxt_free_ring(bp, ring);
2317         }
2318 }
2319
2320 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2321 {
2322         int i, rc, agg_rings = 0, tpa_rings = 0;
2323
2324         if (!bp->rx_ring)
2325                 return -ENOMEM;
2326
2327         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2328                 agg_rings = 1;
2329
2330         if (bp->flags & BNXT_FLAG_TPA)
2331                 tpa_rings = 1;
2332
2333         for (i = 0; i < bp->rx_nr_rings; i++) {
2334                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2335                 struct bnxt_ring_struct *ring;
2336
2337                 ring = &rxr->rx_ring_struct;
2338
2339                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2340                 if (rc < 0)
2341                         return rc;
2342
2343                 rc = bnxt_alloc_ring(bp, ring);
2344                 if (rc)
2345                         return rc;
2346
2347                 if (agg_rings) {
2348                         u16 mem_size;
2349
2350                         ring = &rxr->rx_agg_ring_struct;
2351                         rc = bnxt_alloc_ring(bp, ring);
2352                         if (rc)
2353                                 return rc;
2354
2355                         ring->grp_idx = i;
2356                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2357                         mem_size = rxr->rx_agg_bmap_size / 8;
2358                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2359                         if (!rxr->rx_agg_bmap)
2360                                 return -ENOMEM;
2361
2362                         if (tpa_rings) {
2363                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2364                                                 sizeof(struct bnxt_tpa_info),
2365                                                 GFP_KERNEL);
2366                                 if (!rxr->rx_tpa)
2367                                         return -ENOMEM;
2368                         }
2369                 }
2370         }
2371         return 0;
2372 }
2373
2374 static void bnxt_free_tx_rings(struct bnxt *bp)
2375 {
2376         int i;
2377         struct pci_dev *pdev = bp->pdev;
2378
2379         if (!bp->tx_ring)
2380                 return;
2381
2382         for (i = 0; i < bp->tx_nr_rings; i++) {
2383                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2384                 struct bnxt_ring_struct *ring;
2385
2386                 if (txr->tx_push) {
2387                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2388                                           txr->tx_push, txr->tx_push_mapping);
2389                         txr->tx_push = NULL;
2390                 }
2391
2392                 ring = &txr->tx_ring_struct;
2393
2394                 bnxt_free_ring(bp, ring);
2395         }
2396 }
2397
2398 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2399 {
2400         int i, j, rc;
2401         struct pci_dev *pdev = bp->pdev;
2402
2403         bp->tx_push_size = 0;
2404         if (bp->tx_push_thresh) {
2405                 int push_size;
2406
2407                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2408                                         bp->tx_push_thresh);
2409
2410                 if (push_size > 256) {
2411                         push_size = 0;
2412                         bp->tx_push_thresh = 0;
2413                 }
2414
2415                 bp->tx_push_size = push_size;
2416         }
2417
2418         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2419                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2420                 struct bnxt_ring_struct *ring;
2421                 u8 qidx;
2422
2423                 ring = &txr->tx_ring_struct;
2424
2425                 rc = bnxt_alloc_ring(bp, ring);
2426                 if (rc)
2427                         return rc;
2428
2429                 ring->grp_idx = txr->bnapi->index;
2430                 if (bp->tx_push_size) {
2431                         dma_addr_t mapping;
2432
2433                         /* One pre-allocated DMA buffer to backup
2434                          * TX push operation
2435                          */
2436                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2437                                                 bp->tx_push_size,
2438                                                 &txr->tx_push_mapping,
2439                                                 GFP_KERNEL);
2440
2441                         if (!txr->tx_push)
2442                                 return -ENOMEM;
2443
2444                         mapping = txr->tx_push_mapping +
2445                                 sizeof(struct tx_push_bd);
2446                         txr->data_mapping = cpu_to_le64(mapping);
2447
2448                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2449                 }
2450                 qidx = bp->tc_to_qidx[j];
2451                 ring->queue_id = bp->q_info[qidx].queue_id;
2452                 if (i < bp->tx_nr_rings_xdp)
2453                         continue;
2454                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2455                         j++;
2456         }
2457         return 0;
2458 }
2459
2460 static void bnxt_free_cp_rings(struct bnxt *bp)
2461 {
2462         int i;
2463
2464         if (!bp->bnapi)
2465                 return;
2466
2467         for (i = 0; i < bp->cp_nr_rings; i++) {
2468                 struct bnxt_napi *bnapi = bp->bnapi[i];
2469                 struct bnxt_cp_ring_info *cpr;
2470                 struct bnxt_ring_struct *ring;
2471
2472                 if (!bnapi)
2473                         continue;
2474
2475                 cpr = &bnapi->cp_ring;
2476                 ring = &cpr->cp_ring_struct;
2477
2478                 bnxt_free_ring(bp, ring);
2479         }
2480 }
2481
2482 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2483 {
2484         int i, rc, ulp_base_vec, ulp_msix;
2485
2486         ulp_msix = bnxt_get_ulp_msix_num(bp);
2487         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2488         for (i = 0; i < bp->cp_nr_rings; i++) {
2489                 struct bnxt_napi *bnapi = bp->bnapi[i];
2490                 struct bnxt_cp_ring_info *cpr;
2491                 struct bnxt_ring_struct *ring;
2492
2493                 if (!bnapi)
2494                         continue;
2495
2496                 cpr = &bnapi->cp_ring;
2497                 ring = &cpr->cp_ring_struct;
2498
2499                 rc = bnxt_alloc_ring(bp, ring);
2500                 if (rc)
2501                         return rc;
2502
2503                 if (ulp_msix && i >= ulp_base_vec)
2504                         ring->map_idx = i + ulp_msix;
2505                 else
2506                         ring->map_idx = i;
2507         }
2508         return 0;
2509 }
2510
2511 static void bnxt_init_ring_struct(struct bnxt *bp)
2512 {
2513         int i;
2514
2515         for (i = 0; i < bp->cp_nr_rings; i++) {
2516                 struct bnxt_napi *bnapi = bp->bnapi[i];
2517                 struct bnxt_cp_ring_info *cpr;
2518                 struct bnxt_rx_ring_info *rxr;
2519                 struct bnxt_tx_ring_info *txr;
2520                 struct bnxt_ring_struct *ring;
2521
2522                 if (!bnapi)
2523                         continue;
2524
2525                 cpr = &bnapi->cp_ring;
2526                 ring = &cpr->cp_ring_struct;
2527                 ring->nr_pages = bp->cp_nr_pages;
2528                 ring->page_size = HW_CMPD_RING_SIZE;
2529                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2530                 ring->dma_arr = cpr->cp_desc_mapping;
2531                 ring->vmem_size = 0;
2532
2533                 rxr = bnapi->rx_ring;
2534                 if (!rxr)
2535                         goto skip_rx;
2536
2537                 ring = &rxr->rx_ring_struct;
2538                 ring->nr_pages = bp->rx_nr_pages;
2539                 ring->page_size = HW_RXBD_RING_SIZE;
2540                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2541                 ring->dma_arr = rxr->rx_desc_mapping;
2542                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2543                 ring->vmem = (void **)&rxr->rx_buf_ring;
2544
2545                 ring = &rxr->rx_agg_ring_struct;
2546                 ring->nr_pages = bp->rx_agg_nr_pages;
2547                 ring->page_size = HW_RXBD_RING_SIZE;
2548                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2549                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2550                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2551                 ring->vmem = (void **)&rxr->rx_agg_ring;
2552
2553 skip_rx:
2554                 txr = bnapi->tx_ring;
2555                 if (!txr)
2556                         continue;
2557
2558                 ring = &txr->tx_ring_struct;
2559                 ring->nr_pages = bp->tx_nr_pages;
2560                 ring->page_size = HW_RXBD_RING_SIZE;
2561                 ring->pg_arr = (void **)txr->tx_desc_ring;
2562                 ring->dma_arr = txr->tx_desc_mapping;
2563                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2564                 ring->vmem = (void **)&txr->tx_buf_ring;
2565         }
2566 }
2567
2568 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2569 {
2570         int i;
2571         u32 prod;
2572         struct rx_bd **rx_buf_ring;
2573
2574         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2575         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2576                 int j;
2577                 struct rx_bd *rxbd;
2578
2579                 rxbd = rx_buf_ring[i];
2580                 if (!rxbd)
2581                         continue;
2582
2583                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2584                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2585                         rxbd->rx_bd_opaque = prod;
2586                 }
2587         }
2588 }
2589
2590 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2591 {
2592         struct net_device *dev = bp->dev;
2593         struct bnxt_rx_ring_info *rxr;
2594         struct bnxt_ring_struct *ring;
2595         u32 prod, type;
2596         int i;
2597
2598         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2599                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2600
2601         if (NET_IP_ALIGN == 2)
2602                 type |= RX_BD_FLAGS_SOP;
2603
2604         rxr = &bp->rx_ring[ring_nr];
2605         ring = &rxr->rx_ring_struct;
2606         bnxt_init_rxbd_pages(ring, type);
2607
2608         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2609                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2610                 if (IS_ERR(rxr->xdp_prog)) {
2611                         int rc = PTR_ERR(rxr->xdp_prog);
2612
2613                         rxr->xdp_prog = NULL;
2614                         return rc;
2615                 }
2616         }
2617         prod = rxr->rx_prod;
2618         for (i = 0; i < bp->rx_ring_size; i++) {
2619                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2620                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2621                                     ring_nr, i, bp->rx_ring_size);
2622                         break;
2623                 }
2624                 prod = NEXT_RX(prod);
2625         }
2626         rxr->rx_prod = prod;
2627         ring->fw_ring_id = INVALID_HW_RING_ID;
2628
2629         ring = &rxr->rx_agg_ring_struct;
2630         ring->fw_ring_id = INVALID_HW_RING_ID;
2631
2632         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2633                 return 0;
2634
2635         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2636                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2637
2638         bnxt_init_rxbd_pages(ring, type);
2639
2640         prod = rxr->rx_agg_prod;
2641         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2642                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2643                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2644                                     ring_nr, i, bp->rx_ring_size);
2645                         break;
2646                 }
2647                 prod = NEXT_RX_AGG(prod);
2648         }
2649         rxr->rx_agg_prod = prod;
2650
2651         if (bp->flags & BNXT_FLAG_TPA) {
2652                 if (rxr->rx_tpa) {
2653                         u8 *data;
2654                         dma_addr_t mapping;
2655
2656                         for (i = 0; i < MAX_TPA; i++) {
2657                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2658                                                             GFP_KERNEL);
2659                                 if (!data)
2660                                         return -ENOMEM;
2661
2662                                 rxr->rx_tpa[i].data = data;
2663                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2664                                 rxr->rx_tpa[i].mapping = mapping;
2665                         }
2666                 } else {
2667                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2668                         return -ENOMEM;
2669                 }
2670         }
2671
2672         return 0;
2673 }
2674
2675 static void bnxt_init_cp_rings(struct bnxt *bp)
2676 {
2677         int i;
2678
2679         for (i = 0; i < bp->cp_nr_rings; i++) {
2680                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2681                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2682
2683                 ring->fw_ring_id = INVALID_HW_RING_ID;
2684                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2685                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2686         }
2687 }
2688
2689 static int bnxt_init_rx_rings(struct bnxt *bp)
2690 {
2691         int i, rc = 0;
2692
2693         if (BNXT_RX_PAGE_MODE(bp)) {
2694                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2695                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2696         } else {
2697                 bp->rx_offset = BNXT_RX_OFFSET;
2698                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2699         }
2700
2701         for (i = 0; i < bp->rx_nr_rings; i++) {
2702                 rc = bnxt_init_one_rx_ring(bp, i);
2703                 if (rc)
2704                         break;
2705         }
2706
2707         return rc;
2708 }
2709
2710 static int bnxt_init_tx_rings(struct bnxt *bp)
2711 {
2712         u16 i;
2713
2714         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2715                                    BNXT_MIN_TX_DESC_CNT);
2716
2717         for (i = 0; i < bp->tx_nr_rings; i++) {
2718                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2719                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2720
2721                 ring->fw_ring_id = INVALID_HW_RING_ID;
2722         }
2723
2724         return 0;
2725 }
2726
2727 static void bnxt_free_ring_grps(struct bnxt *bp)
2728 {
2729         kfree(bp->grp_info);
2730         bp->grp_info = NULL;
2731 }
2732
2733 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2734 {
2735         int i;
2736
2737         if (irq_re_init) {
2738                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2739                                        sizeof(struct bnxt_ring_grp_info),
2740                                        GFP_KERNEL);
2741                 if (!bp->grp_info)
2742                         return -ENOMEM;
2743         }
2744         for (i = 0; i < bp->cp_nr_rings; i++) {
2745                 if (irq_re_init)
2746                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2747                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2748                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2749                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2750                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2751         }
2752         return 0;
2753 }
2754
2755 static void bnxt_free_vnics(struct bnxt *bp)
2756 {
2757         kfree(bp->vnic_info);
2758         bp->vnic_info = NULL;
2759         bp->nr_vnics = 0;
2760 }
2761
2762 static int bnxt_alloc_vnics(struct bnxt *bp)
2763 {
2764         int num_vnics = 1;
2765
2766 #ifdef CONFIG_RFS_ACCEL
2767         if (bp->flags & BNXT_FLAG_RFS)
2768                 num_vnics += bp->rx_nr_rings;
2769 #endif
2770
2771         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2772                 num_vnics++;
2773
2774         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2775                                 GFP_KERNEL);
2776         if (!bp->vnic_info)
2777                 return -ENOMEM;
2778
2779         bp->nr_vnics = num_vnics;
2780         return 0;
2781 }
2782
2783 static void bnxt_init_vnics(struct bnxt *bp)
2784 {
2785         int i;
2786
2787         for (i = 0; i < bp->nr_vnics; i++) {
2788                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2789
2790                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2791                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2792                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2793                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2794
2795                 if (bp->vnic_info[i].rss_hash_key) {
2796                         if (i == 0)
2797                                 prandom_bytes(vnic->rss_hash_key,
2798                                               HW_HASH_KEY_SIZE);
2799                         else
2800                                 memcpy(vnic->rss_hash_key,
2801                                        bp->vnic_info[0].rss_hash_key,
2802                                        HW_HASH_KEY_SIZE);
2803                 }
2804         }
2805 }
2806
2807 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2808 {
2809         int pages;
2810
2811         pages = ring_size / desc_per_pg;
2812
2813         if (!pages)
2814                 return 1;
2815
2816         pages++;
2817
2818         while (pages & (pages - 1))
2819                 pages++;
2820
2821         return pages;
2822 }
2823
2824 void bnxt_set_tpa_flags(struct bnxt *bp)
2825 {
2826         bp->flags &= ~BNXT_FLAG_TPA;
2827         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2828                 return;
2829         if (bp->dev->features & NETIF_F_LRO)
2830                 bp->flags |= BNXT_FLAG_LRO;
2831         else if (bp->dev->features & NETIF_F_GRO_HW)
2832                 bp->flags |= BNXT_FLAG_GRO;
2833 }
2834
2835 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2836  * be set on entry.
2837  */
2838 void bnxt_set_ring_params(struct bnxt *bp)
2839 {
2840         u32 ring_size, rx_size, rx_space;
2841         u32 agg_factor = 0, agg_ring_size = 0;
2842
2843         /* 8 for CRC and VLAN */
2844         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2845
2846         rx_space = rx_size + NET_SKB_PAD +
2847                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2848
2849         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2850         ring_size = bp->rx_ring_size;
2851         bp->rx_agg_ring_size = 0;
2852         bp->rx_agg_nr_pages = 0;
2853
2854         if (bp->flags & BNXT_FLAG_TPA)
2855                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2856
2857         bp->flags &= ~BNXT_FLAG_JUMBO;
2858         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2859                 u32 jumbo_factor;
2860
2861                 bp->flags |= BNXT_FLAG_JUMBO;
2862                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2863                 if (jumbo_factor > agg_factor)
2864                         agg_factor = jumbo_factor;
2865         }
2866         agg_ring_size = ring_size * agg_factor;
2867
2868         if (agg_ring_size) {
2869                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2870                                                         RX_DESC_CNT);
2871                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2872                         u32 tmp = agg_ring_size;
2873
2874                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2875                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2876                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2877                                     tmp, agg_ring_size);
2878                 }
2879                 bp->rx_agg_ring_size = agg_ring_size;
2880                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2881                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2882                 rx_space = rx_size + NET_SKB_PAD +
2883                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2884         }
2885
2886         bp->rx_buf_use_size = rx_size;
2887         bp->rx_buf_size = rx_space;
2888
2889         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2890         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2891
2892         ring_size = bp->tx_ring_size;
2893         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2894         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2895
2896         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2897         bp->cp_ring_size = ring_size;
2898
2899         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2900         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2901                 bp->cp_nr_pages = MAX_CP_PAGES;
2902                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2903                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2904                             ring_size, bp->cp_ring_size);
2905         }
2906         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2907         bp->cp_ring_mask = bp->cp_bit - 1;
2908 }
2909
2910 /* Changing allocation mode of RX rings.
2911  * TODO: Update when extending xdp_rxq_info to support allocation modes.
2912  */
2913 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2914 {
2915         if (page_mode) {
2916                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2917                         return -EOPNOTSUPP;
2918                 bp->dev->max_mtu =
2919                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2920                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2921                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2922                 bp->rx_dir = DMA_BIDIRECTIONAL;
2923                 bp->rx_skb_func = bnxt_rx_page_skb;
2924                 /* Disable LRO or GRO_HW */
2925                 netdev_update_features(bp->dev);
2926         } else {
2927                 bp->dev->max_mtu = bp->max_mtu;
2928                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2929                 bp->rx_dir = DMA_FROM_DEVICE;
2930                 bp->rx_skb_func = bnxt_rx_skb;
2931         }
2932         return 0;
2933 }
2934
2935 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2936 {
2937         int i;
2938         struct bnxt_vnic_info *vnic;
2939         struct pci_dev *pdev = bp->pdev;
2940
2941         if (!bp->vnic_info)
2942                 return;
2943
2944         for (i = 0; i < bp->nr_vnics; i++) {
2945                 vnic = &bp->vnic_info[i];
2946
2947                 kfree(vnic->fw_grp_ids);
2948                 vnic->fw_grp_ids = NULL;
2949
2950                 kfree(vnic->uc_list);
2951                 vnic->uc_list = NULL;
2952
2953                 if (vnic->mc_list) {
2954                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2955                                           vnic->mc_list, vnic->mc_list_mapping);
2956                         vnic->mc_list = NULL;
2957                 }
2958
2959                 if (vnic->rss_table) {
2960                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2961                                           vnic->rss_table,
2962                                           vnic->rss_table_dma_addr);
2963                         vnic->rss_table = NULL;
2964                 }
2965
2966                 vnic->rss_hash_key = NULL;
2967                 vnic->flags = 0;
2968         }
2969 }
2970
2971 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2972 {
2973         int i, rc = 0, size;
2974         struct bnxt_vnic_info *vnic;
2975         struct pci_dev *pdev = bp->pdev;
2976         int max_rings;
2977
2978         for (i = 0; i < bp->nr_vnics; i++) {
2979                 vnic = &bp->vnic_info[i];
2980
2981                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2982                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2983
2984                         if (mem_size > 0) {
2985                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2986                                 if (!vnic->uc_list) {
2987                                         rc = -ENOMEM;
2988                                         goto out;
2989                                 }
2990                         }
2991                 }
2992
2993                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2994                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2995                         vnic->mc_list =
2996                                 dma_alloc_coherent(&pdev->dev,
2997                                                    vnic->mc_list_size,
2998                                                    &vnic->mc_list_mapping,
2999                                                    GFP_KERNEL);
3000                         if (!vnic->mc_list) {
3001                                 rc = -ENOMEM;
3002                                 goto out;
3003                         }
3004                 }
3005
3006                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3007                         max_rings = bp->rx_nr_rings;
3008                 else
3009                         max_rings = 1;
3010
3011                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3012                 if (!vnic->fw_grp_ids) {
3013                         rc = -ENOMEM;
3014                         goto out;
3015                 }
3016
3017                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3018                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3019                         continue;
3020
3021                 /* Allocate rss table and hash key */
3022                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3023                                                      &vnic->rss_table_dma_addr,
3024                                                      GFP_KERNEL);
3025                 if (!vnic->rss_table) {
3026                         rc = -ENOMEM;
3027                         goto out;
3028                 }
3029
3030                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3031
3032                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3033                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3034         }
3035         return 0;
3036
3037 out:
3038         return rc;
3039 }
3040
3041 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3042 {
3043         struct pci_dev *pdev = bp->pdev;
3044
3045         if (bp->hwrm_cmd_resp_addr) {
3046                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3047                                   bp->hwrm_cmd_resp_dma_addr);
3048                 bp->hwrm_cmd_resp_addr = NULL;
3049         }
3050 }
3051
3052 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3053 {
3054         struct pci_dev *pdev = bp->pdev;
3055
3056         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3057                                                    &bp->hwrm_cmd_resp_dma_addr,
3058                                                    GFP_KERNEL);
3059         if (!bp->hwrm_cmd_resp_addr)
3060                 return -ENOMEM;
3061
3062         return 0;
3063 }
3064
3065 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3066 {
3067         if (bp->hwrm_short_cmd_req_addr) {
3068                 struct pci_dev *pdev = bp->pdev;
3069
3070                 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3071                                   bp->hwrm_short_cmd_req_addr,
3072                                   bp->hwrm_short_cmd_req_dma_addr);
3073                 bp->hwrm_short_cmd_req_addr = NULL;
3074         }
3075 }
3076
3077 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3078 {
3079         struct pci_dev *pdev = bp->pdev;
3080
3081         bp->hwrm_short_cmd_req_addr =
3082                 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3083                                    &bp->hwrm_short_cmd_req_dma_addr,
3084                                    GFP_KERNEL);
3085         if (!bp->hwrm_short_cmd_req_addr)
3086                 return -ENOMEM;
3087
3088         return 0;
3089 }
3090
3091 static void bnxt_free_stats(struct bnxt *bp)
3092 {
3093         u32 size, i;
3094         struct pci_dev *pdev = bp->pdev;
3095
3096         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3097         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3098
3099         if (bp->hw_rx_port_stats) {
3100                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3101                                   bp->hw_rx_port_stats,
3102                                   bp->hw_rx_port_stats_map);
3103                 bp->hw_rx_port_stats = NULL;
3104         }
3105
3106         if (bp->hw_rx_port_stats_ext) {
3107                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3108                                   bp->hw_rx_port_stats_ext,
3109                                   bp->hw_rx_port_stats_ext_map);
3110                 bp->hw_rx_port_stats_ext = NULL;
3111         }
3112
3113         if (!bp->bnapi)
3114                 return;
3115
3116         size = sizeof(struct ctx_hw_stats);
3117
3118         for (i = 0; i < bp->cp_nr_rings; i++) {
3119                 struct bnxt_napi *bnapi = bp->bnapi[i];
3120                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3121
3122                 if (cpr->hw_stats) {
3123                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3124                                           cpr->hw_stats_map);
3125                         cpr->hw_stats = NULL;
3126                 }
3127         }
3128 }
3129
3130 static int bnxt_alloc_stats(struct bnxt *bp)
3131 {
3132         u32 size, i;
3133         struct pci_dev *pdev = bp->pdev;
3134
3135         size = sizeof(struct ctx_hw_stats);
3136
3137         for (i = 0; i < bp->cp_nr_rings; i++) {
3138                 struct bnxt_napi *bnapi = bp->bnapi[i];
3139                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3140
3141                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3142                                                    &cpr->hw_stats_map,
3143                                                    GFP_KERNEL);
3144                 if (!cpr->hw_stats)
3145                         return -ENOMEM;
3146
3147                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3148         }
3149
3150         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3151                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3152                                          sizeof(struct tx_port_stats) + 1024;
3153
3154                 bp->hw_rx_port_stats =
3155                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3156                                            &bp->hw_rx_port_stats_map,
3157                                            GFP_KERNEL);
3158                 if (!bp->hw_rx_port_stats)
3159                         return -ENOMEM;
3160
3161                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3162                                        512;
3163                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3164                                            sizeof(struct rx_port_stats) + 512;
3165                 bp->flags |= BNXT_FLAG_PORT_STATS;
3166
3167                 /* Display extended statistics only if FW supports it */
3168                 if (bp->hwrm_spec_code < 0x10804 ||
3169                     bp->hwrm_spec_code == 0x10900)
3170                         return 0;
3171
3172                 bp->hw_rx_port_stats_ext =
3173                         dma_zalloc_coherent(&pdev->dev,
3174                                             sizeof(struct rx_port_stats_ext),
3175                                             &bp->hw_rx_port_stats_ext_map,
3176                                             GFP_KERNEL);
3177                 if (!bp->hw_rx_port_stats_ext)
3178                         return 0;
3179
3180                 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3181         }
3182         return 0;
3183 }
3184
3185 static void bnxt_clear_ring_indices(struct bnxt *bp)
3186 {
3187         int i;
3188
3189         if (!bp->bnapi)
3190                 return;
3191
3192         for (i = 0; i < bp->cp_nr_rings; i++) {
3193                 struct bnxt_napi *bnapi = bp->bnapi[i];
3194                 struct bnxt_cp_ring_info *cpr;
3195                 struct bnxt_rx_ring_info *rxr;
3196                 struct bnxt_tx_ring_info *txr;
3197
3198                 if (!bnapi)
3199                         continue;
3200
3201                 cpr = &bnapi->cp_ring;
3202                 cpr->cp_raw_cons = 0;
3203
3204                 txr = bnapi->tx_ring;
3205                 if (txr) {
3206                         txr->tx_prod = 0;
3207                         txr->tx_cons = 0;
3208                 }
3209
3210                 rxr = bnapi->rx_ring;
3211                 if (rxr) {
3212                         rxr->rx_prod = 0;
3213                         rxr->rx_agg_prod = 0;
3214                         rxr->rx_sw_agg_prod = 0;
3215                         rxr->rx_next_cons = 0;
3216                 }
3217         }
3218 }
3219
3220 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3221 {
3222 #ifdef CONFIG_RFS_ACCEL
3223         int i;
3224
3225         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3226          * safe to delete the hash table.
3227          */
3228         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3229                 struct hlist_head *head;
3230                 struct hlist_node *tmp;
3231                 struct bnxt_ntuple_filter *fltr;
3232
3233                 head = &bp->ntp_fltr_hash_tbl[i];
3234                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3235                         hlist_del(&fltr->hash);
3236                         kfree(fltr);
3237                 }
3238         }
3239         if (irq_reinit) {
3240                 kfree(bp->ntp_fltr_bmap);
3241                 bp->ntp_fltr_bmap = NULL;
3242         }
3243         bp->ntp_fltr_count = 0;
3244 #endif
3245 }
3246
3247 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3248 {
3249 #ifdef CONFIG_RFS_ACCEL
3250         int i, rc = 0;
3251
3252         if (!(bp->flags & BNXT_FLAG_RFS))
3253                 return 0;
3254
3255         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3256                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3257
3258         bp->ntp_fltr_count = 0;
3259         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3260                                     sizeof(long),
3261                                     GFP_KERNEL);
3262
3263         if (!bp->ntp_fltr_bmap)
3264                 rc = -ENOMEM;
3265
3266         return rc;
3267 #else
3268         return 0;
3269 #endif
3270 }
3271
3272 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3273 {
3274         bnxt_free_vnic_attributes(bp);
3275         bnxt_free_tx_rings(bp);
3276         bnxt_free_rx_rings(bp);
3277         bnxt_free_cp_rings(bp);
3278         bnxt_free_ntp_fltrs(bp, irq_re_init);
3279         if (irq_re_init) {
3280                 bnxt_free_stats(bp);
3281                 bnxt_free_ring_grps(bp);
3282                 bnxt_free_vnics(bp);
3283                 kfree(bp->tx_ring_map);
3284                 bp->tx_ring_map = NULL;
3285                 kfree(bp->tx_ring);
3286                 bp->tx_ring = NULL;
3287                 kfree(bp->rx_ring);
3288                 bp->rx_ring = NULL;
3289                 kfree(bp->bnapi);
3290                 bp->bnapi = NULL;
3291         } else {
3292                 bnxt_clear_ring_indices(bp);
3293         }
3294 }
3295
3296 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3297 {
3298         int i, j, rc, size, arr_size;
3299         void *bnapi;
3300
3301         if (irq_re_init) {
3302                 /* Allocate bnapi mem pointer array and mem block for
3303                  * all queues
3304                  */
3305                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3306                                 bp->cp_nr_rings);
3307                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3308                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3309                 if (!bnapi)
3310                         return -ENOMEM;
3311
3312                 bp->bnapi = bnapi;
3313                 bnapi += arr_size;
3314                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3315                         bp->bnapi[i] = bnapi;
3316                         bp->bnapi[i]->index = i;
3317                         bp->bnapi[i]->bp = bp;
3318                 }
3319
3320                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3321                                       sizeof(struct bnxt_rx_ring_info),
3322                                       GFP_KERNEL);
3323                 if (!bp->rx_ring)
3324                         return -ENOMEM;
3325
3326                 for (i = 0; i < bp->rx_nr_rings; i++) {
3327                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3328                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3329                 }
3330
3331                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3332                                       sizeof(struct bnxt_tx_ring_info),
3333                                       GFP_KERNEL);
3334                 if (!bp->tx_ring)
3335                         return -ENOMEM;
3336
3337                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3338                                           GFP_KERNEL);
3339
3340                 if (!bp->tx_ring_map)
3341                         return -ENOMEM;
3342
3343                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3344                         j = 0;
3345                 else
3346                         j = bp->rx_nr_rings;
3347
3348                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3349                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3350                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3351                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3352                         if (i >= bp->tx_nr_rings_xdp) {
3353                                 bp->tx_ring[i].txq_index = i -
3354                                         bp->tx_nr_rings_xdp;
3355                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3356                         } else {
3357                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3358                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3359                         }
3360                 }
3361
3362                 rc = bnxt_alloc_stats(bp);
3363                 if (rc)
3364                         goto alloc_mem_err;
3365
3366                 rc = bnxt_alloc_ntp_fltrs(bp);
3367                 if (rc)
3368                         goto alloc_mem_err;
3369
3370                 rc = bnxt_alloc_vnics(bp);
3371                 if (rc)
3372                         goto alloc_mem_err;
3373         }
3374
3375         bnxt_init_ring_struct(bp);
3376
3377         rc = bnxt_alloc_rx_rings(bp);
3378         if (rc)
3379                 goto alloc_mem_err;
3380
3381         rc = bnxt_alloc_tx_rings(bp);
3382         if (rc)
3383                 goto alloc_mem_err;
3384
3385         rc = bnxt_alloc_cp_rings(bp);
3386         if (rc)
3387                 goto alloc_mem_err;
3388
3389         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3390                                   BNXT_VNIC_UCAST_FLAG;
3391         rc = bnxt_alloc_vnic_attributes(bp);
3392         if (rc)
3393                 goto alloc_mem_err;
3394         return 0;
3395
3396 alloc_mem_err:
3397         bnxt_free_mem(bp, true);
3398         return rc;
3399 }
3400
3401 static void bnxt_disable_int(struct bnxt *bp)
3402 {
3403         int i;
3404
3405         if (!bp->bnapi)
3406                 return;
3407
3408         for (i = 0; i < bp->cp_nr_rings; i++) {
3409                 struct bnxt_napi *bnapi = bp->bnapi[i];
3410                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3411                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3412
3413                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3414                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3415         }
3416 }
3417
3418 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3419 {
3420         struct bnxt_napi *bnapi = bp->bnapi[n];
3421         struct bnxt_cp_ring_info *cpr;
3422
3423         cpr = &bnapi->cp_ring;
3424         return cpr->cp_ring_struct.map_idx;
3425 }
3426
3427 static void bnxt_disable_int_sync(struct bnxt *bp)
3428 {
3429         int i;
3430
3431         atomic_inc(&bp->intr_sem);
3432
3433         bnxt_disable_int(bp);
3434         for (i = 0; i < bp->cp_nr_rings; i++) {
3435                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3436
3437                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3438         }
3439 }
3440
3441 static void bnxt_enable_int(struct bnxt *bp)
3442 {
3443         int i;
3444
3445         atomic_set(&bp->intr_sem, 0);
3446         for (i = 0; i < bp->cp_nr_rings; i++) {
3447                 struct bnxt_napi *bnapi = bp->bnapi[i];
3448                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3449
3450                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3451         }
3452 }
3453
3454 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3455                             u16 cmpl_ring, u16 target_id)
3456 {
3457         struct input *req = request;
3458
3459         req->req_type = cpu_to_le16(req_type);
3460         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3461         req->target_id = cpu_to_le16(target_id);
3462         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3463 }
3464
3465 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3466                                  int timeout, bool silent)
3467 {
3468         int i, intr_process, rc, tmo_count;
3469         struct input *req = msg;
3470         u32 *data = msg;
3471         __le32 *resp_len;
3472         u8 *valid;
3473         u16 cp_ring_id, len = 0;
3474         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3475         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3476         struct hwrm_short_input short_input = {0};
3477
3478         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3479         memset(resp, 0, PAGE_SIZE);
3480         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3481         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3482
3483         if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
3484                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3485
3486                 memcpy(short_cmd_req, req, msg_len);
3487                 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3488                                                    msg_len);
3489
3490                 short_input.req_type = req->req_type;
3491                 short_input.signature =
3492                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3493                 short_input.size = cpu_to_le16(msg_len);
3494                 short_input.req_addr =
3495                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3496
3497                 data = (u32 *)&short_input;
3498                 msg_len = sizeof(short_input);
3499
3500                 /* Sync memory write before updating doorbell */
3501                 wmb();
3502
3503                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3504         }
3505
3506         /* Write request msg to hwrm channel */
3507         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3508
3509         for (i = msg_len; i < max_req_len; i += 4)
3510                 writel(0, bp->bar0 + i);
3511
3512         /* currently supports only one outstanding message */
3513         if (intr_process)
3514                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3515
3516         /* Ring channel doorbell */
3517         writel(1, bp->bar0 + 0x100);
3518
3519         if (!timeout)
3520                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3521         /* convert timeout to usec */
3522         timeout *= 1000;
3523
3524         i = 0;
3525         /* Short timeout for the first few iterations:
3526          * number of loops = number of loops for short timeout +
3527          * number of loops for standard timeout.
3528          */
3529         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3530         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3531         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3532         resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3533         if (intr_process) {
3534                 /* Wait until hwrm response cmpl interrupt is processed */
3535                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3536                        i++ < tmo_count) {
3537                         /* on first few passes, just barely sleep */
3538                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3539                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3540                                              HWRM_SHORT_MAX_TIMEOUT);
3541                         else
3542                                 usleep_range(HWRM_MIN_TIMEOUT,
3543                                              HWRM_MAX_TIMEOUT);
3544                 }
3545
3546                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3547                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3548                                    le16_to_cpu(req->req_type));
3549                         return -1;
3550                 }
3551                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3552                       HWRM_RESP_LEN_SFT;
3553                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3554         } else {
3555                 int j;
3556
3557                 /* Check if response len is updated */
3558                 for (i = 0; i < tmo_count; i++) {
3559                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3560                               HWRM_RESP_LEN_SFT;
3561                         if (len)
3562                                 break;
3563                         /* on first few passes, just barely sleep */
3564                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3565                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3566                                              HWRM_SHORT_MAX_TIMEOUT);
3567                         else
3568                                 usleep_range(HWRM_MIN_TIMEOUT,
3569                                              HWRM_MAX_TIMEOUT);
3570                 }
3571
3572                 if (i >= tmo_count) {
3573                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3574                                    HWRM_TOTAL_TIMEOUT(i),
3575                                    le16_to_cpu(req->req_type),
3576                                    le16_to_cpu(req->seq_id), len);
3577                         return -1;
3578                 }
3579
3580                 /* Last byte of resp contains valid bit */
3581                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3582                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3583                         /* make sure we read from updated DMA memory */
3584                         dma_rmb();
3585                         if (*valid)
3586                                 break;
3587                         usleep_range(1, 5);
3588                 }
3589
3590                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3591                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3592                                    HWRM_TOTAL_TIMEOUT(i),
3593                                    le16_to_cpu(req->req_type),
3594                                    le16_to_cpu(req->seq_id), len, *valid);
3595                         return -1;
3596                 }
3597         }
3598
3599         /* Zero valid bit for compatibility.  Valid bit in an older spec
3600          * may become a new field in a newer spec.  We must make sure that
3601          * a new field not implemented by old spec will read zero.
3602          */
3603         *valid = 0;
3604         rc = le16_to_cpu(resp->error_code);
3605         if (rc && !silent)
3606                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3607                            le16_to_cpu(resp->req_type),
3608                            le16_to_cpu(resp->seq_id), rc);
3609         return rc;
3610 }
3611
3612 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3613 {
3614         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3615 }
3616
3617 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3618                               int timeout)
3619 {
3620         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3621 }
3622
3623 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3624 {
3625         int rc;
3626
3627         mutex_lock(&bp->hwrm_cmd_lock);
3628         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3629         mutex_unlock(&bp->hwrm_cmd_lock);
3630         return rc;
3631 }
3632
3633 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3634                              int timeout)
3635 {
3636         int rc;
3637
3638         mutex_lock(&bp->hwrm_cmd_lock);
3639         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3640         mutex_unlock(&bp->hwrm_cmd_lock);
3641         return rc;
3642 }
3643
3644 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3645                                      int bmap_size)
3646 {
3647         struct hwrm_func_drv_rgtr_input req = {0};
3648         DECLARE_BITMAP(async_events_bmap, 256);
3649         u32 *events = (u32 *)async_events_bmap;
3650         int i;
3651
3652         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3653
3654         req.enables =
3655                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3656
3657         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3658         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3659                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3660
3661         if (bmap && bmap_size) {
3662                 for (i = 0; i < bmap_size; i++) {
3663                         if (test_bit(i, bmap))
3664                                 __set_bit(i, async_events_bmap);
3665                 }
3666         }
3667
3668         for (i = 0; i < 8; i++)
3669                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3670
3671         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3672 }
3673
3674 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3675 {
3676         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3677         struct hwrm_func_drv_rgtr_input req = {0};
3678         int rc;
3679
3680         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3681
3682         req.enables =
3683                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3684                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3685
3686         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3687         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3688         req.ver_maj_8b = DRV_VER_MAJ;
3689         req.ver_min_8b = DRV_VER_MIN;
3690         req.ver_upd_8b = DRV_VER_UPD;
3691         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3692         req.ver_min = cpu_to_le16(DRV_VER_MIN);
3693         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
3694
3695         if (BNXT_PF(bp)) {
3696                 u32 data[8];
3697                 int i;
3698
3699                 memset(data, 0, sizeof(data));
3700                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3701                         u16 cmd = bnxt_vf_req_snif[i];
3702                         unsigned int bit, idx;
3703
3704                         idx = cmd / 32;
3705                         bit = cmd % 32;
3706                         data[idx] |= 1 << bit;
3707                 }
3708
3709                 for (i = 0; i < 8; i++)
3710                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3711
3712                 req.enables |=
3713                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3714         }
3715
3716         mutex_lock(&bp->hwrm_cmd_lock);
3717         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3718         if (rc)
3719                 rc = -EIO;
3720         else if (resp->flags &
3721                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3722                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
3723         mutex_unlock(&bp->hwrm_cmd_lock);
3724         return rc;
3725 }
3726
3727 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3728 {
3729         struct hwrm_func_drv_unrgtr_input req = {0};
3730
3731         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3732         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3733 }
3734
3735 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3736 {
3737         u32 rc = 0;
3738         struct hwrm_tunnel_dst_port_free_input req = {0};
3739
3740         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3741         req.tunnel_type = tunnel_type;
3742
3743         switch (tunnel_type) {
3744         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3745                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3746                 break;
3747         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3748                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3749                 break;
3750         default:
3751                 break;
3752         }
3753
3754         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3755         if (rc)
3756                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3757                            rc);
3758         return rc;
3759 }
3760
3761 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3762                                            u8 tunnel_type)
3763 {
3764         u32 rc = 0;
3765         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3766         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3767
3768         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3769
3770         req.tunnel_type = tunnel_type;
3771         req.tunnel_dst_port_val = port;
3772
3773         mutex_lock(&bp->hwrm_cmd_lock);
3774         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3775         if (rc) {
3776                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3777                            rc);
3778                 goto err_out;
3779         }
3780
3781         switch (tunnel_type) {
3782         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3783                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3784                 break;
3785         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3786                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3787                 break;
3788         default:
3789                 break;
3790         }
3791
3792 err_out:
3793         mutex_unlock(&bp->hwrm_cmd_lock);
3794         return rc;
3795 }
3796
3797 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3798 {
3799         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3800         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3801
3802         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3803         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3804
3805         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3806         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3807         req.mask = cpu_to_le32(vnic->rx_mask);
3808         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3809 }
3810
3811 #ifdef CONFIG_RFS_ACCEL
3812 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3813                                             struct bnxt_ntuple_filter *fltr)
3814 {
3815         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3816
3817         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3818         req.ntuple_filter_id = fltr->filter_id;
3819         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3820 }
3821
3822 #define BNXT_NTP_FLTR_FLAGS                                     \
3823         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3824          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3825          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3826          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3827          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3828          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3829          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3830          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3831          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3832          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3833          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3834          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3835          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3836          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3837
3838 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3839                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3840
3841 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3842                                              struct bnxt_ntuple_filter *fltr)
3843 {
3844         int rc = 0;
3845         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3846         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3847                 bp->hwrm_cmd_resp_addr;
3848         struct flow_keys *keys = &fltr->fkeys;
3849         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3850
3851         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3852         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3853
3854         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3855
3856         req.ethertype = htons(ETH_P_IP);
3857         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3858         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3859         req.ip_protocol = keys->basic.ip_proto;
3860
3861         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3862                 int i;
3863
3864                 req.ethertype = htons(ETH_P_IPV6);
3865                 req.ip_addr_type =
3866                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3867                 *(struct in6_addr *)&req.src_ipaddr[0] =
3868                         keys->addrs.v6addrs.src;
3869                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3870                         keys->addrs.v6addrs.dst;
3871                 for (i = 0; i < 4; i++) {
3872                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3873                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3874                 }
3875         } else {
3876                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3877                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3878                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3879                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3880         }
3881         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3882                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3883                 req.tunnel_type =
3884                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3885         }
3886
3887         req.src_port = keys->ports.src;
3888         req.src_port_mask = cpu_to_be16(0xffff);
3889         req.dst_port = keys->ports.dst;
3890         req.dst_port_mask = cpu_to_be16(0xffff);
3891
3892         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3893         mutex_lock(&bp->hwrm_cmd_lock);
3894         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3895         if (!rc)
3896                 fltr->filter_id = resp->ntuple_filter_id;
3897         mutex_unlock(&bp->hwrm_cmd_lock);
3898         return rc;
3899 }
3900 #endif
3901
3902 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3903                                      u8 *mac_addr)
3904 {
3905         u32 rc = 0;
3906         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3907         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3908
3909         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3910         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3911         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3912                 req.flags |=
3913                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3914         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3915         req.enables =
3916                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3917                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3918                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3919         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3920         req.l2_addr_mask[0] = 0xff;
3921         req.l2_addr_mask[1] = 0xff;
3922         req.l2_addr_mask[2] = 0xff;
3923         req.l2_addr_mask[3] = 0xff;
3924         req.l2_addr_mask[4] = 0xff;
3925         req.l2_addr_mask[5] = 0xff;
3926
3927         mutex_lock(&bp->hwrm_cmd_lock);
3928         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3929         if (!rc)
3930                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3931                                                         resp->l2_filter_id;
3932         mutex_unlock(&bp->hwrm_cmd_lock);
3933         return rc;
3934 }
3935
3936 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3937 {
3938         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3939         int rc = 0;
3940
3941         /* Any associated ntuple filters will also be cleared by firmware. */
3942         mutex_lock(&bp->hwrm_cmd_lock);
3943         for (i = 0; i < num_of_vnics; i++) {
3944                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3945
3946                 for (j = 0; j < vnic->uc_filter_count; j++) {
3947                         struct hwrm_cfa_l2_filter_free_input req = {0};
3948
3949                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3950                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3951
3952                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3953
3954                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3955                                                 HWRM_CMD_TIMEOUT);
3956                 }
3957                 vnic->uc_filter_count = 0;
3958         }
3959         mutex_unlock(&bp->hwrm_cmd_lock);
3960
3961         return rc;
3962 }
3963
3964 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3965 {
3966         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3967         struct hwrm_vnic_tpa_cfg_input req = {0};
3968
3969         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3970                 return 0;
3971
3972         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3973
3974         if (tpa_flags) {
3975                 u16 mss = bp->dev->mtu - 40;
3976                 u32 nsegs, n, segs = 0, flags;
3977
3978                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3979                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3980                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3981                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3982                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3983                 if (tpa_flags & BNXT_FLAG_GRO)
3984                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3985
3986                 req.flags = cpu_to_le32(flags);
3987
3988                 req.enables =
3989                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3990                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3991                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3992
3993                 /* Number of segs are log2 units, and first packet is not
3994                  * included as part of this units.
3995                  */
3996                 if (mss <= BNXT_RX_PAGE_SIZE) {
3997                         n = BNXT_RX_PAGE_SIZE / mss;
3998                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3999                 } else {
4000                         n = mss / BNXT_RX_PAGE_SIZE;
4001                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
4002                                 n++;
4003                         nsegs = (MAX_SKB_FRAGS - n) / n;
4004                 }
4005
4006                 segs = ilog2(nsegs);
4007                 req.max_agg_segs = cpu_to_le16(segs);
4008                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4009
4010                 req.min_agg_len = cpu_to_le32(512);
4011         }
4012         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4013
4014         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4015 }
4016
4017 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4018 {
4019         u32 i, j, max_rings;
4020         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4021         struct hwrm_vnic_rss_cfg_input req = {0};
4022
4023         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4024                 return 0;
4025
4026         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4027         if (set_rss) {
4028                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4029                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4030                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4031                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4032                                 max_rings = bp->rx_nr_rings - 1;
4033                         else
4034                                 max_rings = bp->rx_nr_rings;
4035                 } else {
4036                         max_rings = 1;
4037                 }
4038
4039                 /* Fill the RSS indirection table with ring group ids */
4040                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4041                         if (j == max_rings)
4042                                 j = 0;
4043                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4044                 }
4045
4046                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4047                 req.hash_key_tbl_addr =
4048                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4049         }
4050         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4051         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4052 }
4053
4054 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4055 {
4056         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4057         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4058
4059         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4060         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4061                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4062                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4063         req.enables =
4064                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4065                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4066         /* thresholds not implemented in firmware yet */
4067         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4068         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4069         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4070         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4071 }
4072
4073 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4074                                         u16 ctx_idx)
4075 {
4076         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4077
4078         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4079         req.rss_cos_lb_ctx_id =
4080                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4081
4082         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4083         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4084 }
4085
4086 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4087 {
4088         int i, j;
4089
4090         for (i = 0; i < bp->nr_vnics; i++) {
4091                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4092
4093                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4094                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4095                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4096                 }
4097         }
4098         bp->rsscos_nr_ctxs = 0;
4099 }
4100
4101 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4102 {
4103         int rc;
4104         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4105         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4106                                                 bp->hwrm_cmd_resp_addr;
4107
4108         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4109                                -1);
4110
4111         mutex_lock(&bp->hwrm_cmd_lock);
4112         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4113         if (!rc)
4114                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4115                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4116         mutex_unlock(&bp->hwrm_cmd_lock);
4117
4118         return rc;
4119 }
4120
4121 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4122 {
4123         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4124                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4125         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4126 }
4127
4128 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4129 {
4130         unsigned int ring = 0, grp_idx;
4131         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4132         struct hwrm_vnic_cfg_input req = {0};
4133         u16 def_vlan = 0;
4134
4135         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4136
4137         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4138         /* Only RSS support for now TBD: COS & LB */
4139         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4140                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4141                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4142                                            VNIC_CFG_REQ_ENABLES_MRU);
4143         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4144                 req.rss_rule =
4145                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4146                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4147                                            VNIC_CFG_REQ_ENABLES_MRU);
4148                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4149         } else {
4150                 req.rss_rule = cpu_to_le16(0xffff);
4151         }
4152
4153         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4154             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4155                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4156                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4157         } else {
4158                 req.cos_rule = cpu_to_le16(0xffff);
4159         }
4160
4161         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4162                 ring = 0;
4163         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4164                 ring = vnic_id - 1;
4165         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4166                 ring = bp->rx_nr_rings - 1;
4167
4168         grp_idx = bp->rx_ring[ring].bnapi->index;
4169         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4170         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4171
4172         req.lb_rule = cpu_to_le16(0xffff);
4173         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4174                               VLAN_HLEN);
4175
4176 #ifdef CONFIG_BNXT_SRIOV
4177         if (BNXT_VF(bp))
4178                 def_vlan = bp->vf.vlan;
4179 #endif
4180         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4181                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4182         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4183                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4184
4185         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4186 }
4187
4188 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4189 {
4190         u32 rc = 0;
4191
4192         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4193                 struct hwrm_vnic_free_input req = {0};
4194
4195                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4196                 req.vnic_id =
4197                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4198
4199                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4200                 if (rc)
4201                         return rc;
4202                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4203         }
4204         return rc;
4205 }
4206
4207 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4208 {
4209         u16 i;
4210
4211         for (i = 0; i < bp->nr_vnics; i++)
4212                 bnxt_hwrm_vnic_free_one(bp, i);
4213 }
4214
4215 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4216                                 unsigned int start_rx_ring_idx,
4217                                 unsigned int nr_rings)
4218 {
4219         int rc = 0;
4220         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4221         struct hwrm_vnic_alloc_input req = {0};
4222         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4223
4224         /* map ring groups to this vnic */
4225         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4226                 grp_idx = bp->rx_ring[i].bnapi->index;
4227                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4228                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4229                                    j, nr_rings);
4230                         break;
4231                 }
4232                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4233                                         bp->grp_info[grp_idx].fw_grp_id;
4234         }
4235
4236         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4237         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4238         if (vnic_id == 0)
4239                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4240
4241         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4242
4243         mutex_lock(&bp->hwrm_cmd_lock);
4244         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4245         if (!rc)
4246                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4247         mutex_unlock(&bp->hwrm_cmd_lock);
4248         return rc;
4249 }
4250
4251 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4252 {
4253         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4254         struct hwrm_vnic_qcaps_input req = {0};
4255         int rc;
4256
4257         if (bp->hwrm_spec_code < 0x10600)
4258                 return 0;
4259
4260         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4261         mutex_lock(&bp->hwrm_cmd_lock);
4262         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4263         if (!rc) {
4264                 u32 flags = le32_to_cpu(resp->flags);
4265
4266                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
4267                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4268                 if (flags &
4269                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4270                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4271         }
4272         mutex_unlock(&bp->hwrm_cmd_lock);
4273         return rc;
4274 }
4275
4276 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4277 {
4278         u16 i;
4279         u32 rc = 0;
4280
4281         mutex_lock(&bp->hwrm_cmd_lock);
4282         for (i = 0; i < bp->rx_nr_rings; i++) {
4283                 struct hwrm_ring_grp_alloc_input req = {0};
4284                 struct hwrm_ring_grp_alloc_output *resp =
4285                                         bp->hwrm_cmd_resp_addr;
4286                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4287
4288                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4289
4290                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4291                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4292                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4293                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4294
4295                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4296                                         HWRM_CMD_TIMEOUT);
4297                 if (rc)
4298                         break;
4299
4300                 bp->grp_info[grp_idx].fw_grp_id =
4301                         le32_to_cpu(resp->ring_group_id);
4302         }
4303         mutex_unlock(&bp->hwrm_cmd_lock);
4304         return rc;
4305 }
4306
4307 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4308 {
4309         u16 i;
4310         u32 rc = 0;
4311         struct hwrm_ring_grp_free_input req = {0};
4312
4313         if (!bp->grp_info)
4314                 return 0;
4315
4316         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4317
4318         mutex_lock(&bp->hwrm_cmd_lock);
4319         for (i = 0; i < bp->cp_nr_rings; i++) {
4320                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4321                         continue;
4322                 req.ring_group_id =
4323                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4324
4325                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4326                                         HWRM_CMD_TIMEOUT);
4327                 if (rc)
4328                         break;
4329                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4330         }
4331         mutex_unlock(&bp->hwrm_cmd_lock);
4332         return rc;
4333 }
4334
4335 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4336                                     struct bnxt_ring_struct *ring,
4337                                     u32 ring_type, u32 map_index)
4338 {
4339         int rc = 0, err = 0;
4340         struct hwrm_ring_alloc_input req = {0};
4341         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4342         struct bnxt_ring_grp_info *grp_info;
4343         u16 ring_id;
4344
4345         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4346
4347         req.enables = 0;
4348         if (ring->nr_pages > 1) {
4349                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4350                 /* Page size is in log2 units */
4351                 req.page_size = BNXT_PAGE_SHIFT;
4352                 req.page_tbl_depth = 1;
4353         } else {
4354                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
4355         }
4356         req.fbo = 0;
4357         /* Association of ring index with doorbell index and MSIX number */
4358         req.logical_id = cpu_to_le16(map_index);
4359
4360         switch (ring_type) {
4361         case HWRM_RING_ALLOC_TX:
4362                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4363                 /* Association of transmit ring with completion ring */
4364                 grp_info = &bp->grp_info[ring->grp_idx];
4365                 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4366                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4367                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4368                 req.queue_id = cpu_to_le16(ring->queue_id);
4369                 break;
4370         case HWRM_RING_ALLOC_RX:
4371                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4372                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4373                 break;
4374         case HWRM_RING_ALLOC_AGG:
4375                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4376                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4377                 break;
4378         case HWRM_RING_ALLOC_CMPL:
4379                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4380                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4381                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4382                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4383                 break;
4384         default:
4385                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4386                            ring_type);
4387                 return -1;
4388         }
4389
4390         mutex_lock(&bp->hwrm_cmd_lock);
4391         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4392         err = le16_to_cpu(resp->error_code);
4393         ring_id = le16_to_cpu(resp->ring_id);
4394         mutex_unlock(&bp->hwrm_cmd_lock);
4395
4396         if (rc || err) {
4397                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4398                            ring_type, rc, err);
4399                 return -EIO;
4400         }
4401         ring->fw_ring_id = ring_id;
4402         return rc;
4403 }
4404
4405 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4406 {
4407         int rc;
4408
4409         if (BNXT_PF(bp)) {
4410                 struct hwrm_func_cfg_input req = {0};
4411
4412                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4413                 req.fid = cpu_to_le16(0xffff);
4414                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4415                 req.async_event_cr = cpu_to_le16(idx);
4416                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4417         } else {
4418                 struct hwrm_func_vf_cfg_input req = {0};
4419
4420                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4421                 req.enables =
4422                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4423                 req.async_event_cr = cpu_to_le16(idx);
4424                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4425         }
4426         return rc;
4427 }
4428
4429 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4430 {
4431         int i, rc = 0;
4432
4433         for (i = 0; i < bp->cp_nr_rings; i++) {
4434                 struct bnxt_napi *bnapi = bp->bnapi[i];
4435                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4436                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4437                 u32 map_idx = ring->map_idx;
4438
4439                 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4440                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4441                                               map_idx);
4442                 if (rc)
4443                         goto err_out;
4444                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4445                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4446
4447                 if (!i) {
4448                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4449                         if (rc)
4450                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4451                 }
4452         }
4453
4454         for (i = 0; i < bp->tx_nr_rings; i++) {
4455                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4456                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4457                 u32 map_idx = i;
4458
4459                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4460                                               map_idx);
4461                 if (rc)
4462                         goto err_out;
4463                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4464         }
4465
4466         for (i = 0; i < bp->rx_nr_rings; i++) {
4467                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4468                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4469                 u32 map_idx = rxr->bnapi->index;
4470
4471                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4472                                               map_idx);
4473                 if (rc)
4474                         goto err_out;
4475                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4476                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4477                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4478         }
4479
4480         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4481                 for (i = 0; i < bp->rx_nr_rings; i++) {
4482                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4483                         struct bnxt_ring_struct *ring =
4484                                                 &rxr->rx_agg_ring_struct;
4485                         u32 grp_idx = ring->grp_idx;
4486                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4487
4488                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4489                                                       HWRM_RING_ALLOC_AGG,
4490                                                       map_idx);
4491                         if (rc)
4492                                 goto err_out;
4493
4494                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4495                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4496                                rxr->rx_agg_doorbell);
4497                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4498                 }
4499         }
4500 err_out:
4501         return rc;
4502 }
4503
4504 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4505                                    struct bnxt_ring_struct *ring,
4506                                    u32 ring_type, int cmpl_ring_id)
4507 {
4508         int rc;
4509         struct hwrm_ring_free_input req = {0};
4510         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4511         u16 error_code;
4512
4513         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4514         req.ring_type = ring_type;
4515         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4516
4517         mutex_lock(&bp->hwrm_cmd_lock);
4518         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4519         error_code = le16_to_cpu(resp->error_code);
4520         mutex_unlock(&bp->hwrm_cmd_lock);
4521
4522         if (rc || error_code) {
4523                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4524                            ring_type, rc, error_code);
4525                 return -EIO;
4526         }
4527         return 0;
4528 }
4529
4530 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4531 {
4532         int i;
4533
4534         if (!bp->bnapi)
4535                 return;
4536
4537         for (i = 0; i < bp->tx_nr_rings; i++) {
4538                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4539                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4540                 u32 grp_idx = txr->bnapi->index;
4541                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4542
4543                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4544                         hwrm_ring_free_send_msg(bp, ring,
4545                                                 RING_FREE_REQ_RING_TYPE_TX,
4546                                                 close_path ? cmpl_ring_id :
4547                                                 INVALID_HW_RING_ID);
4548                         ring->fw_ring_id = INVALID_HW_RING_ID;
4549                 }
4550         }
4551
4552         for (i = 0; i < bp->rx_nr_rings; i++) {
4553                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4554                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4555                 u32 grp_idx = rxr->bnapi->index;
4556                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4557
4558                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4559                         hwrm_ring_free_send_msg(bp, ring,
4560                                                 RING_FREE_REQ_RING_TYPE_RX,
4561                                                 close_path ? cmpl_ring_id :
4562                                                 INVALID_HW_RING_ID);
4563                         ring->fw_ring_id = INVALID_HW_RING_ID;
4564                         bp->grp_info[grp_idx].rx_fw_ring_id =
4565                                 INVALID_HW_RING_ID;
4566                 }
4567         }
4568
4569         for (i = 0; i < bp->rx_nr_rings; i++) {
4570                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4571                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4572                 u32 grp_idx = rxr->bnapi->index;
4573                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4574
4575                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4576                         hwrm_ring_free_send_msg(bp, ring,
4577                                                 RING_FREE_REQ_RING_TYPE_RX,
4578                                                 close_path ? cmpl_ring_id :
4579                                                 INVALID_HW_RING_ID);
4580                         ring->fw_ring_id = INVALID_HW_RING_ID;
4581                         bp->grp_info[grp_idx].agg_fw_ring_id =
4582                                 INVALID_HW_RING_ID;
4583                 }
4584         }
4585
4586         /* The completion rings are about to be freed.  After that the
4587          * IRQ doorbell will not work anymore.  So we need to disable
4588          * IRQ here.
4589          */
4590         bnxt_disable_int_sync(bp);
4591
4592         for (i = 0; i < bp->cp_nr_rings; i++) {
4593                 struct bnxt_napi *bnapi = bp->bnapi[i];
4594                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4595                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4596
4597                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4598                         hwrm_ring_free_send_msg(bp, ring,
4599                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4600                                                 INVALID_HW_RING_ID);
4601                         ring->fw_ring_id = INVALID_HW_RING_ID;
4602                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4603                 }
4604         }
4605 }
4606
4607 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4608 {
4609         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4610         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4611         struct hwrm_func_qcfg_input req = {0};
4612         int rc;
4613
4614         if (bp->hwrm_spec_code < 0x10601)
4615                 return 0;
4616
4617         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4618         req.fid = cpu_to_le16(0xffff);
4619         mutex_lock(&bp->hwrm_cmd_lock);
4620         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4621         if (rc) {
4622                 mutex_unlock(&bp->hwrm_cmd_lock);
4623                 return -EIO;
4624         }
4625
4626         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4627         if (BNXT_NEW_RM(bp)) {
4628                 u16 cp, stats;
4629
4630                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4631                 hw_resc->resv_hw_ring_grps =
4632                         le32_to_cpu(resp->alloc_hw_ring_grps);
4633                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4634                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4635                 stats = le16_to_cpu(resp->alloc_stat_ctx);
4636                 cp = min_t(u16, cp, stats);
4637                 hw_resc->resv_cp_rings = cp;
4638         }
4639         mutex_unlock(&bp->hwrm_cmd_lock);
4640         return 0;
4641 }
4642
4643 /* Caller must hold bp->hwrm_cmd_lock */
4644 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4645 {
4646         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4647         struct hwrm_func_qcfg_input req = {0};
4648         int rc;
4649
4650         if (bp->hwrm_spec_code < 0x10601)
4651                 return 0;
4652
4653         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4654         req.fid = cpu_to_le16(fid);
4655         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4656         if (!rc)
4657                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4658
4659         return rc;
4660 }
4661
4662 static void
4663 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4664                              int tx_rings, int rx_rings, int ring_grps,
4665                              int cp_rings, int vnics)
4666 {
4667         u32 enables = 0;
4668
4669         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4670         req->fid = cpu_to_le16(0xffff);
4671         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4672         req->num_tx_rings = cpu_to_le16(tx_rings);
4673         if (BNXT_NEW_RM(bp)) {
4674                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4675                 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4676                                       FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4677                 enables |= ring_grps ?
4678                            FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4679                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
4680
4681                 req->num_rx_rings = cpu_to_le16(rx_rings);
4682                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4683                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4684                 req->num_stat_ctxs = req->num_cmpl_rings;
4685                 req->num_vnics = cpu_to_le16(vnics);
4686         }
4687         req->enables = cpu_to_le32(enables);
4688 }
4689
4690 static void
4691 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4692                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
4693                              int rx_rings, int ring_grps, int cp_rings,
4694                              int vnics)
4695 {
4696         u32 enables = 0;
4697
4698         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4699         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4700         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4701         enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4702                               FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4703         enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4704         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4705
4706         req->num_tx_rings = cpu_to_le16(tx_rings);
4707         req->num_rx_rings = cpu_to_le16(rx_rings);
4708         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4709         req->num_cmpl_rings = cpu_to_le16(cp_rings);
4710         req->num_stat_ctxs = req->num_cmpl_rings;
4711         req->num_vnics = cpu_to_le16(vnics);
4712
4713         req->enables = cpu_to_le32(enables);
4714 }
4715
4716 static int
4717 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4718                            int ring_grps, int cp_rings, int vnics)
4719 {
4720         struct hwrm_func_cfg_input req = {0};
4721         int rc;
4722
4723         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4724                                      cp_rings, vnics);
4725         if (!req.enables)
4726                 return 0;
4727
4728         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4729         if (rc)
4730                 return -ENOMEM;
4731
4732         if (bp->hwrm_spec_code < 0x10601)
4733                 bp->hw_resc.resv_tx_rings = tx_rings;
4734
4735         rc = bnxt_hwrm_get_rings(bp);
4736         return rc;
4737 }
4738
4739 static int
4740 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4741                            int ring_grps, int cp_rings, int vnics)
4742 {
4743         struct hwrm_func_vf_cfg_input req = {0};
4744         int rc;
4745
4746         if (!BNXT_NEW_RM(bp)) {
4747                 bp->hw_resc.resv_tx_rings = tx_rings;
4748                 return 0;
4749         }
4750
4751         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4752                                      cp_rings, vnics);
4753         req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
4754                                    FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
4755         req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
4756         req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4757         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4758         if (rc)
4759                 return -ENOMEM;
4760
4761         rc = bnxt_hwrm_get_rings(bp);
4762         return rc;
4763 }
4764
4765 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4766                                    int cp, int vnic)
4767 {
4768         if (BNXT_PF(bp))
4769                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4770         else
4771                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4772 }
4773
4774 static int bnxt_cp_rings_in_use(struct bnxt *bp)
4775 {
4776         int cp = bp->cp_nr_rings;
4777         int ulp_msix, ulp_base;
4778
4779         ulp_msix = bnxt_get_ulp_msix_num(bp);
4780         if (ulp_msix) {
4781                 ulp_base = bnxt_get_ulp_msix_base(bp);
4782                 cp += ulp_msix;
4783                 if ((ulp_base + ulp_msix) > cp)
4784                         cp = ulp_base + ulp_msix;
4785         }
4786         return cp;
4787 }
4788
4789 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4790 {
4791         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4792         int cp = bnxt_cp_rings_in_use(bp);
4793         int rx = bp->rx_nr_rings;
4794         int vnic = 1, grp = rx;
4795
4796         if (bp->hwrm_spec_code < 0x10601)
4797                 return false;
4798
4799         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4800                 return true;
4801
4802         if (bp->flags & BNXT_FLAG_RFS)
4803                 vnic = rx + 1;
4804         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4805                 rx <<= 1;
4806         if (BNXT_NEW_RM(bp) &&
4807             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4808              hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4809                 return true;
4810         return false;
4811 }
4812
4813 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4814                            bool shared);
4815
4816 static int __bnxt_reserve_rings(struct bnxt *bp)
4817 {
4818         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4819         int cp = bnxt_cp_rings_in_use(bp);
4820         int tx = bp->tx_nr_rings;
4821         int rx = bp->rx_nr_rings;
4822         int grp, rx_rings, rc;
4823         bool sh = false;
4824         int vnic = 1;
4825
4826         if (!bnxt_need_reserve_rings(bp))
4827                 return 0;
4828
4829         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4830                 sh = true;
4831         if (bp->flags & BNXT_FLAG_RFS)
4832                 vnic = rx + 1;
4833         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4834                 rx <<= 1;
4835         grp = bp->rx_nr_rings;
4836
4837         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4838         if (rc)
4839                 return rc;
4840
4841         tx = hw_resc->resv_tx_rings;
4842         if (BNXT_NEW_RM(bp)) {
4843                 rx = hw_resc->resv_rx_rings;
4844                 cp = hw_resc->resv_cp_rings;
4845                 grp = hw_resc->resv_hw_ring_grps;
4846                 vnic = hw_resc->resv_vnics;
4847         }
4848
4849         rx_rings = rx;
4850         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4851                 if (rx >= 2) {
4852                         rx_rings = rx >> 1;
4853                 } else {
4854                         if (netif_running(bp->dev))
4855                                 return -ENOMEM;
4856
4857                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4858                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4859                         bp->dev->hw_features &= ~NETIF_F_LRO;
4860                         bp->dev->features &= ~NETIF_F_LRO;
4861                         bnxt_set_ring_params(bp);
4862                 }
4863         }
4864         rx_rings = min_t(int, rx_rings, grp);
4865         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4866         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4867                 rx = rx_rings << 1;
4868         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4869         bp->tx_nr_rings = tx;
4870         bp->rx_nr_rings = rx_rings;
4871         bp->cp_nr_rings = cp;
4872
4873         if (!tx || !rx || !cp || !grp || !vnic)
4874                 return -ENOMEM;
4875
4876         return rc;
4877 }
4878
4879 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4880                                     int ring_grps, int cp_rings, int vnics)
4881 {
4882         struct hwrm_func_vf_cfg_input req = {0};
4883         u32 flags;
4884         int rc;
4885
4886         if (!BNXT_NEW_RM(bp))
4887                 return 0;
4888
4889         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4890                                      cp_rings, vnics);
4891         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4892                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4893                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4894                 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4895                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4896                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4897
4898         req.flags = cpu_to_le32(flags);
4899         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4900         if (rc)
4901                 return -ENOMEM;
4902         return 0;
4903 }
4904
4905 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4906                                     int ring_grps, int cp_rings, int vnics)
4907 {
4908         struct hwrm_func_cfg_input req = {0};
4909         u32 flags;
4910         int rc;
4911
4912         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4913                                      cp_rings, vnics);
4914         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4915         if (BNXT_NEW_RM(bp))
4916                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4917                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4918                          FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4919                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4920                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4921
4922         req.flags = cpu_to_le32(flags);
4923         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4924         if (rc)
4925                 return -ENOMEM;
4926         return 0;
4927 }
4928
4929 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4930                                  int ring_grps, int cp_rings, int vnics)
4931 {
4932         if (bp->hwrm_spec_code < 0x10801)
4933                 return 0;
4934
4935         if (BNXT_PF(bp))
4936                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4937                                                 ring_grps, cp_rings, vnics);
4938
4939         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4940                                         cp_rings, vnics);
4941 }
4942
4943 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4944         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4945 {
4946         u16 val, tmr, max, flags;
4947
4948         max = hw_coal->bufs_per_record * 128;
4949         if (hw_coal->budget)
4950                 max = hw_coal->bufs_per_record * hw_coal->budget;
4951
4952         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4953         req->num_cmpl_aggr_int = cpu_to_le16(val);
4954
4955         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4956         val = min_t(u16, val, 63);
4957         req->num_cmpl_dma_aggr = cpu_to_le16(val);
4958
4959         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4960         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4961         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4962
4963         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4964         tmr = max_t(u16, tmr, 1);
4965         req->int_lat_tmr_max = cpu_to_le16(tmr);
4966
4967         /* min timer set to 1/2 of interrupt timer */
4968         val = tmr / 2;
4969         req->int_lat_tmr_min = cpu_to_le16(val);
4970
4971         /* buf timer set to 1/4 of interrupt timer */
4972         val = max_t(u16, tmr / 4, 1);
4973         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4974
4975         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4976         tmr = max_t(u16, tmr, 1);
4977         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4978
4979         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4980         if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4981                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4982         req->flags = cpu_to_le16(flags);
4983 }
4984
4985 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4986 {
4987         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4988         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4989         struct bnxt_coal coal;
4990         unsigned int grp_idx;
4991
4992         /* Tick values in micro seconds.
4993          * 1 coal_buf x bufs_per_record = 1 completion record.
4994          */
4995         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4996
4997         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4998         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4999
5000         if (!bnapi->rx_ring)
5001                 return -ENODEV;
5002
5003         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5004                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5005
5006         bnxt_hwrm_set_coal_params(&coal, &req_rx);
5007
5008         grp_idx = bnapi->index;
5009         req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5010
5011         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5012                                  HWRM_CMD_TIMEOUT);
5013 }
5014
5015 int bnxt_hwrm_set_coal(struct bnxt *bp)
5016 {
5017         int i, rc = 0;
5018         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5019                                                            req_tx = {0}, *req;
5020
5021         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5022                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5023         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5024                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5025
5026         bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
5027         bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
5028
5029         mutex_lock(&bp->hwrm_cmd_lock);
5030         for (i = 0; i < bp->cp_nr_rings; i++) {
5031                 struct bnxt_napi *bnapi = bp->bnapi[i];
5032
5033                 req = &req_rx;
5034                 if (!bnapi->rx_ring)
5035                         req = &req_tx;
5036                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
5037
5038                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5039                                         HWRM_CMD_TIMEOUT);
5040                 if (rc)
5041                         break;
5042         }
5043         mutex_unlock(&bp->hwrm_cmd_lock);
5044         return rc;
5045 }
5046
5047 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5048 {
5049         int rc = 0, i;
5050         struct hwrm_stat_ctx_free_input req = {0};
5051
5052         if (!bp->bnapi)
5053                 return 0;
5054
5055         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5056                 return 0;
5057
5058         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5059
5060         mutex_lock(&bp->hwrm_cmd_lock);
5061         for (i = 0; i < bp->cp_nr_rings; i++) {
5062                 struct bnxt_napi *bnapi = bp->bnapi[i];
5063                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5064
5065                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5066                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5067
5068                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5069                                                 HWRM_CMD_TIMEOUT);
5070                         if (rc)
5071                                 break;
5072
5073                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5074                 }
5075         }
5076         mutex_unlock(&bp->hwrm_cmd_lock);
5077         return rc;
5078 }
5079
5080 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5081 {
5082         int rc = 0, i;
5083         struct hwrm_stat_ctx_alloc_input req = {0};
5084         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5085
5086         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5087                 return 0;
5088
5089         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5090
5091         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5092
5093         mutex_lock(&bp->hwrm_cmd_lock);
5094         for (i = 0; i < bp->cp_nr_rings; i++) {
5095                 struct bnxt_napi *bnapi = bp->bnapi[i];
5096                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5097
5098                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5099
5100                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5101                                         HWRM_CMD_TIMEOUT);
5102                 if (rc)
5103                         break;
5104
5105                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5106
5107                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5108         }
5109         mutex_unlock(&bp->hwrm_cmd_lock);
5110         return rc;
5111 }
5112
5113 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5114 {
5115         struct hwrm_func_qcfg_input req = {0};
5116         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5117         u16 flags;
5118         int rc;
5119
5120         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5121         req.fid = cpu_to_le16(0xffff);
5122         mutex_lock(&bp->hwrm_cmd_lock);
5123         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5124         if (rc)
5125                 goto func_qcfg_exit;
5126
5127 #ifdef CONFIG_BNXT_SRIOV
5128         if (BNXT_VF(bp)) {
5129                 struct bnxt_vf_info *vf = &bp->vf;
5130
5131                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5132         }
5133 #endif
5134         flags = le16_to_cpu(resp->flags);
5135         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5136                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5137                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5138                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5139                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5140         }
5141         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5142                 bp->flags |= BNXT_FLAG_MULTI_HOST;
5143
5144         switch (resp->port_partition_type) {
5145         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5146         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5147         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5148                 bp->port_partition_type = resp->port_partition_type;
5149                 break;
5150         }
5151         if (bp->hwrm_spec_code < 0x10707 ||
5152             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5153                 bp->br_mode = BRIDGE_MODE_VEB;
5154         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5155                 bp->br_mode = BRIDGE_MODE_VEPA;
5156         else
5157                 bp->br_mode = BRIDGE_MODE_UNDEF;
5158
5159         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5160         if (!bp->max_mtu)
5161                 bp->max_mtu = BNXT_MAX_MTU;
5162
5163 func_qcfg_exit:
5164         mutex_unlock(&bp->hwrm_cmd_lock);
5165         return rc;
5166 }
5167
5168 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5169 {
5170         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5171         struct hwrm_func_resource_qcaps_input req = {0};
5172         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5173         int rc;
5174
5175         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5176         req.fid = cpu_to_le16(0xffff);
5177
5178         mutex_lock(&bp->hwrm_cmd_lock);
5179         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5180         if (rc) {
5181                 rc = -EIO;
5182                 goto hwrm_func_resc_qcaps_exit;
5183         }
5184
5185         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5186         if (!all)
5187                 goto hwrm_func_resc_qcaps_exit;
5188
5189         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5190         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5191         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5192         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5193         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5194         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5195         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5196         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5197         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5198         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5199         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5200         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5201         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5202         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5203         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5204         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5205
5206         if (BNXT_PF(bp)) {
5207                 struct bnxt_pf_info *pf = &bp->pf;
5208
5209                 pf->vf_resv_strategy =
5210                         le16_to_cpu(resp->vf_reservation_strategy);
5211                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
5212                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5213         }
5214 hwrm_func_resc_qcaps_exit:
5215         mutex_unlock(&bp->hwrm_cmd_lock);
5216         return rc;
5217 }
5218
5219 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5220 {
5221         int rc = 0;
5222         struct hwrm_func_qcaps_input req = {0};
5223         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5224         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5225         u32 flags;
5226
5227         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5228         req.fid = cpu_to_le16(0xffff);
5229
5230         mutex_lock(&bp->hwrm_cmd_lock);
5231         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5232         if (rc)
5233                 goto hwrm_func_qcaps_exit;
5234
5235         flags = le32_to_cpu(resp->flags);
5236         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5237                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5238         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5239                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5240
5241         bp->tx_push_thresh = 0;
5242         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5243                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5244
5245         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5246         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5247         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5248         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5249         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5250         if (!hw_resc->max_hw_ring_grps)
5251                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5252         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5253         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5254         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5255
5256         if (BNXT_PF(bp)) {
5257                 struct bnxt_pf_info *pf = &bp->pf;
5258
5259                 pf->fw_fid = le16_to_cpu(resp->fid);
5260                 pf->port_id = le16_to_cpu(resp->port_id);
5261                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5262                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5263                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5264                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5265                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5266                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5267                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5268                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5269                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5270                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5271                         bp->flags |= BNXT_FLAG_WOL_CAP;
5272         } else {
5273 #ifdef CONFIG_BNXT_SRIOV
5274                 struct bnxt_vf_info *vf = &bp->vf;
5275
5276                 vf->fw_fid = le16_to_cpu(resp->fid);
5277                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5278 #endif
5279         }
5280
5281 hwrm_func_qcaps_exit:
5282         mutex_unlock(&bp->hwrm_cmd_lock);
5283         return rc;
5284 }
5285
5286 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5287 {
5288         int rc;
5289
5290         rc = __bnxt_hwrm_func_qcaps(bp);
5291         if (rc)
5292                 return rc;
5293         if (bp->hwrm_spec_code >= 0x10803) {
5294                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5295                 if (!rc)
5296                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
5297         }
5298         return 0;
5299 }
5300
5301 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5302 {
5303         struct hwrm_func_reset_input req = {0};
5304
5305         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5306         req.enables = 0;
5307
5308         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5309 }
5310
5311 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5312 {
5313         int rc = 0;
5314         struct hwrm_queue_qportcfg_input req = {0};
5315         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5316         u8 i, j, *qptr;
5317         bool no_rdma;
5318
5319         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5320
5321         mutex_lock(&bp->hwrm_cmd_lock);
5322         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5323         if (rc)
5324                 goto qportcfg_exit;
5325
5326         if (!resp->max_configurable_queues) {
5327                 rc = -EINVAL;
5328                 goto qportcfg_exit;
5329         }
5330         bp->max_tc = resp->max_configurable_queues;
5331         bp->max_lltc = resp->max_configurable_lossless_queues;
5332         if (bp->max_tc > BNXT_MAX_QUEUE)
5333                 bp->max_tc = BNXT_MAX_QUEUE;
5334
5335         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
5336         qptr = &resp->queue_id0;
5337         for (i = 0, j = 0; i < bp->max_tc; i++) {
5338                 bp->q_info[j].queue_id = *qptr++;
5339                 bp->q_info[j].queue_profile = *qptr++;
5340                 bp->tc_to_qidx[j] = j;
5341                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
5342                     (no_rdma && BNXT_PF(bp)))
5343                         j++;
5344         }
5345         bp->max_tc = max_t(u8, j, 1);
5346
5347         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5348                 bp->max_tc = 1;
5349
5350         if (bp->max_lltc > bp->max_tc)
5351                 bp->max_lltc = bp->max_tc;
5352
5353 qportcfg_exit:
5354         mutex_unlock(&bp->hwrm_cmd_lock);
5355         return rc;
5356 }
5357
5358 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5359 {
5360         int rc;
5361         struct hwrm_ver_get_input req = {0};
5362         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5363         u32 dev_caps_cfg;
5364
5365         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5366         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5367         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5368         req.hwrm_intf_min = HWRM_VERSION_MINOR;
5369         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5370         mutex_lock(&bp->hwrm_cmd_lock);
5371         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5372         if (rc)
5373                 goto hwrm_ver_get_exit;
5374
5375         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5376
5377         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5378                              resp->hwrm_intf_min_8b << 8 |
5379                              resp->hwrm_intf_upd_8b;
5380         if (resp->hwrm_intf_maj_8b < 1) {
5381                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5382                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5383                             resp->hwrm_intf_upd_8b);
5384                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5385         }
5386         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5387                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5388                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5389
5390         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5391         if (!bp->hwrm_cmd_timeout)
5392                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5393
5394         if (resp->hwrm_intf_maj_8b >= 1)
5395                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5396
5397         bp->chip_num = le16_to_cpu(resp->chip_num);
5398         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5399             !resp->chip_metal)
5400                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5401
5402         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5403         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5404             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5405                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
5406
5407 hwrm_ver_get_exit:
5408         mutex_unlock(&bp->hwrm_cmd_lock);
5409         return rc;
5410 }
5411
5412 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5413 {
5414         struct hwrm_fw_set_time_input req = {0};
5415         struct tm tm;
5416         time64_t now = ktime_get_real_seconds();
5417
5418         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
5419             bp->hwrm_spec_code < 0x10400)
5420                 return -EOPNOTSUPP;
5421
5422         time64_to_tm(now, 0, &tm);
5423         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5424         req.year = cpu_to_le16(1900 + tm.tm_year);
5425         req.month = 1 + tm.tm_mon;
5426         req.day = tm.tm_mday;
5427         req.hour = tm.tm_hour;
5428         req.minute = tm.tm_min;
5429         req.second = tm.tm_sec;
5430         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5431 }
5432
5433 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5434 {
5435         int rc;
5436         struct bnxt_pf_info *pf = &bp->pf;
5437         struct hwrm_port_qstats_input req = {0};
5438
5439         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5440                 return 0;
5441
5442         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5443         req.port_id = cpu_to_le16(pf->port_id);
5444         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5445         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5446         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5447         return rc;
5448 }
5449
5450 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
5451 {
5452         struct hwrm_port_qstats_ext_input req = {0};
5453         struct bnxt_pf_info *pf = &bp->pf;
5454
5455         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5456                 return 0;
5457
5458         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
5459         req.port_id = cpu_to_le16(pf->port_id);
5460         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5461         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5462         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5463 }
5464
5465 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5466 {
5467         if (bp->vxlan_port_cnt) {
5468                 bnxt_hwrm_tunnel_dst_port_free(
5469                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5470         }
5471         bp->vxlan_port_cnt = 0;
5472         if (bp->nge_port_cnt) {
5473                 bnxt_hwrm_tunnel_dst_port_free(
5474                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5475         }
5476         bp->nge_port_cnt = 0;
5477 }
5478
5479 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5480 {
5481         int rc, i;
5482         u32 tpa_flags = 0;
5483
5484         if (set_tpa)
5485                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5486         for (i = 0; i < bp->nr_vnics; i++) {
5487                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5488                 if (rc) {
5489                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5490                                    i, rc);
5491                         return rc;
5492                 }
5493         }
5494         return 0;
5495 }
5496
5497 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5498 {
5499         int i;
5500
5501         for (i = 0; i < bp->nr_vnics; i++)
5502                 bnxt_hwrm_vnic_set_rss(bp, i, false);
5503 }
5504
5505 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5506                                     bool irq_re_init)
5507 {
5508         if (bp->vnic_info) {
5509                 bnxt_hwrm_clear_vnic_filter(bp);
5510                 /* clear all RSS setting before free vnic ctx */
5511                 bnxt_hwrm_clear_vnic_rss(bp);
5512                 bnxt_hwrm_vnic_ctx_free(bp);
5513                 /* before free the vnic, undo the vnic tpa settings */
5514                 if (bp->flags & BNXT_FLAG_TPA)
5515                         bnxt_set_tpa(bp, false);
5516                 bnxt_hwrm_vnic_free(bp);
5517         }
5518         bnxt_hwrm_ring_free(bp, close_path);
5519         bnxt_hwrm_ring_grp_free(bp);
5520         if (irq_re_init) {
5521                 bnxt_hwrm_stat_ctx_free(bp);
5522                 bnxt_hwrm_free_tunnel_ports(bp);
5523         }
5524 }
5525
5526 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5527 {
5528         struct hwrm_func_cfg_input req = {0};
5529         int rc;
5530
5531         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5532         req.fid = cpu_to_le16(0xffff);
5533         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5534         if (br_mode == BRIDGE_MODE_VEB)
5535                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5536         else if (br_mode == BRIDGE_MODE_VEPA)
5537                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5538         else
5539                 return -EINVAL;
5540         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5541         if (rc)
5542                 rc = -EIO;
5543         return rc;
5544 }
5545
5546 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5547 {
5548         struct hwrm_func_cfg_input req = {0};
5549         int rc;
5550
5551         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5552                 return 0;
5553
5554         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5555         req.fid = cpu_to_le16(0xffff);
5556         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5557         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
5558         if (size == 128)
5559                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5560
5561         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5562         if (rc)
5563                 rc = -EIO;
5564         return rc;
5565 }
5566
5567 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5568 {
5569         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5570         int rc;
5571
5572         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5573                 goto skip_rss_ctx;
5574
5575         /* allocate context for vnic */
5576         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5577         if (rc) {
5578                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5579                            vnic_id, rc);
5580                 goto vnic_setup_err;
5581         }
5582         bp->rsscos_nr_ctxs++;
5583
5584         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5585                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5586                 if (rc) {
5587                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5588                                    vnic_id, rc);
5589                         goto vnic_setup_err;
5590                 }
5591                 bp->rsscos_nr_ctxs++;
5592         }
5593
5594 skip_rss_ctx:
5595         /* configure default vnic, ring grp */
5596         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5597         if (rc) {
5598                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5599                            vnic_id, rc);
5600                 goto vnic_setup_err;
5601         }
5602
5603         /* Enable RSS hashing on vnic */
5604         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5605         if (rc) {
5606                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5607                            vnic_id, rc);
5608                 goto vnic_setup_err;
5609         }
5610
5611         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5612                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5613                 if (rc) {
5614                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5615                                    vnic_id, rc);
5616                 }
5617         }
5618
5619 vnic_setup_err:
5620         return rc;
5621 }
5622
5623 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5624 {
5625 #ifdef CONFIG_RFS_ACCEL
5626         int i, rc = 0;
5627
5628         for (i = 0; i < bp->rx_nr_rings; i++) {
5629                 struct bnxt_vnic_info *vnic;
5630                 u16 vnic_id = i + 1;
5631                 u16 ring_id = i;
5632
5633                 if (vnic_id >= bp->nr_vnics)
5634                         break;
5635
5636                 vnic = &bp->vnic_info[vnic_id];
5637                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5638                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5639                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5640                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5641                 if (rc) {
5642                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5643                                    vnic_id, rc);
5644                         break;
5645                 }
5646                 rc = bnxt_setup_vnic(bp, vnic_id);
5647                 if (rc)
5648                         break;
5649         }
5650         return rc;
5651 #else
5652         return 0;
5653 #endif
5654 }
5655
5656 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5657 static bool bnxt_promisc_ok(struct bnxt *bp)
5658 {
5659 #ifdef CONFIG_BNXT_SRIOV
5660         if (BNXT_VF(bp) && !bp->vf.vlan)
5661                 return false;
5662 #endif
5663         return true;
5664 }
5665
5666 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5667 {
5668         unsigned int rc = 0;
5669
5670         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5671         if (rc) {
5672                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5673                            rc);
5674                 return rc;
5675         }
5676
5677         rc = bnxt_hwrm_vnic_cfg(bp, 1);
5678         if (rc) {
5679                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5680                            rc);
5681                 return rc;
5682         }
5683         return rc;
5684 }
5685
5686 static int bnxt_cfg_rx_mode(struct bnxt *);
5687 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5688
5689 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5690 {
5691         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5692         int rc = 0;
5693         unsigned int rx_nr_rings = bp->rx_nr_rings;
5694
5695         if (irq_re_init) {
5696                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5697                 if (rc) {
5698                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5699                                    rc);
5700                         goto err_out;
5701                 }
5702         }
5703
5704         rc = bnxt_hwrm_ring_alloc(bp);
5705         if (rc) {
5706                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5707                 goto err_out;
5708         }
5709
5710         rc = bnxt_hwrm_ring_grp_alloc(bp);
5711         if (rc) {
5712                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5713                 goto err_out;
5714         }
5715
5716         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5717                 rx_nr_rings--;
5718
5719         /* default vnic 0 */
5720         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5721         if (rc) {
5722                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5723                 goto err_out;
5724         }
5725
5726         rc = bnxt_setup_vnic(bp, 0);
5727         if (rc)
5728                 goto err_out;
5729
5730         if (bp->flags & BNXT_FLAG_RFS) {
5731                 rc = bnxt_alloc_rfs_vnics(bp);
5732                 if (rc)
5733                         goto err_out;
5734         }
5735
5736         if (bp->flags & BNXT_FLAG_TPA) {
5737                 rc = bnxt_set_tpa(bp, true);
5738                 if (rc)
5739                         goto err_out;
5740         }
5741
5742         if (BNXT_VF(bp))
5743                 bnxt_update_vf_mac(bp);
5744
5745         /* Filter for default vnic 0 */
5746         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5747         if (rc) {
5748                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5749                 goto err_out;
5750         }
5751         vnic->uc_filter_count = 1;
5752
5753         vnic->rx_mask = 0;
5754         if (bp->dev->flags & IFF_BROADCAST)
5755                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5756
5757         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5758                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5759
5760         if (bp->dev->flags & IFF_ALLMULTI) {
5761                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5762                 vnic->mc_list_count = 0;
5763         } else {
5764                 u32 mask = 0;
5765
5766                 bnxt_mc_list_updated(bp, &mask);
5767                 vnic->rx_mask |= mask;
5768         }
5769
5770         rc = bnxt_cfg_rx_mode(bp);
5771         if (rc)
5772                 goto err_out;
5773
5774         rc = bnxt_hwrm_set_coal(bp);
5775         if (rc)
5776                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5777                                 rc);
5778
5779         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5780                 rc = bnxt_setup_nitroa0_vnic(bp);
5781                 if (rc)
5782                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5783                                    rc);
5784         }
5785
5786         if (BNXT_VF(bp)) {
5787                 bnxt_hwrm_func_qcfg(bp);
5788                 netdev_update_features(bp->dev);
5789         }
5790
5791         return 0;
5792
5793 err_out:
5794         bnxt_hwrm_resource_free(bp, 0, true);
5795
5796         return rc;
5797 }
5798
5799 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5800 {
5801         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5802         return 0;
5803 }
5804
5805 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5806 {
5807         bnxt_init_cp_rings(bp);
5808         bnxt_init_rx_rings(bp);
5809         bnxt_init_tx_rings(bp);
5810         bnxt_init_ring_grps(bp, irq_re_init);
5811         bnxt_init_vnics(bp);
5812
5813         return bnxt_init_chip(bp, irq_re_init);
5814 }
5815
5816 static int bnxt_set_real_num_queues(struct bnxt *bp)
5817 {
5818         int rc;
5819         struct net_device *dev = bp->dev;
5820
5821         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5822                                           bp->tx_nr_rings_xdp);
5823         if (rc)
5824                 return rc;
5825
5826         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5827         if (rc)
5828                 return rc;
5829
5830 #ifdef CONFIG_RFS_ACCEL
5831         if (bp->flags & BNXT_FLAG_RFS)
5832                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5833 #endif
5834
5835         return rc;
5836 }
5837
5838 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5839                            bool shared)
5840 {
5841         int _rx = *rx, _tx = *tx;
5842
5843         if (shared) {
5844                 *rx = min_t(int, _rx, max);
5845                 *tx = min_t(int, _tx, max);
5846         } else {
5847                 if (max < 2)
5848                         return -ENOMEM;
5849
5850                 while (_rx + _tx > max) {
5851                         if (_rx > _tx && _rx > 1)
5852                                 _rx--;
5853                         else if (_tx > 1)
5854                                 _tx--;
5855                 }
5856                 *rx = _rx;
5857                 *tx = _tx;
5858         }
5859         return 0;
5860 }
5861
5862 static void bnxt_setup_msix(struct bnxt *bp)
5863 {
5864         const int len = sizeof(bp->irq_tbl[0].name);
5865         struct net_device *dev = bp->dev;
5866         int tcs, i;
5867
5868         tcs = netdev_get_num_tc(dev);
5869         if (tcs) {
5870                 int i, off, count;
5871
5872                 for (i = 0; i < tcs; i++) {
5873                         count = bp->tx_nr_rings_per_tc;
5874                         off = i * count;
5875                         netdev_set_tc_queue(dev, i, count, off);
5876                 }
5877         }
5878
5879         for (i = 0; i < bp->cp_nr_rings; i++) {
5880                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
5881                 char *attr;
5882
5883                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5884                         attr = "TxRx";
5885                 else if (i < bp->rx_nr_rings)
5886                         attr = "rx";
5887                 else
5888                         attr = "tx";
5889
5890                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
5891                          attr, i);
5892                 bp->irq_tbl[map_idx].handler = bnxt_msix;
5893         }
5894 }
5895
5896 static void bnxt_setup_inta(struct bnxt *bp)
5897 {
5898         const int len = sizeof(bp->irq_tbl[0].name);
5899
5900         if (netdev_get_num_tc(bp->dev))
5901                 netdev_reset_tc(bp->dev);
5902
5903         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5904                  0);
5905         bp->irq_tbl[0].handler = bnxt_inta;
5906 }
5907
5908 static int bnxt_setup_int_mode(struct bnxt *bp)
5909 {
5910         int rc;
5911
5912         if (bp->flags & BNXT_FLAG_USING_MSIX)
5913                 bnxt_setup_msix(bp);
5914         else
5915                 bnxt_setup_inta(bp);
5916
5917         rc = bnxt_set_real_num_queues(bp);
5918         return rc;
5919 }
5920
5921 #ifdef CONFIG_RFS_ACCEL
5922 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5923 {
5924         return bp->hw_resc.max_rsscos_ctxs;
5925 }
5926
5927 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5928 {
5929         return bp->hw_resc.max_vnics;
5930 }
5931 #endif
5932
5933 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5934 {
5935         return bp->hw_resc.max_stat_ctxs;
5936 }
5937
5938 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5939 {
5940         bp->hw_resc.max_stat_ctxs = max;
5941 }
5942
5943 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5944 {
5945         return bp->hw_resc.max_cp_rings;
5946 }
5947
5948 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
5949 {
5950         return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp);
5951 }
5952
5953 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5954 {
5955         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5956
5957         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5958 }
5959
5960 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5961 {
5962         bp->hw_resc.max_irqs = max_irqs;
5963 }
5964
5965 int bnxt_get_avail_msix(struct bnxt *bp, int num)
5966 {
5967         int max_cp = bnxt_get_max_func_cp_rings(bp);
5968         int max_irq = bnxt_get_max_func_irqs(bp);
5969         int total_req = bp->cp_nr_rings + num;
5970         int max_idx, avail_msix;
5971
5972         max_idx = min_t(int, bp->total_irqs, max_cp);
5973         avail_msix = max_idx - bp->cp_nr_rings;
5974         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
5975                 return avail_msix;
5976
5977         if (max_irq < total_req) {
5978                 num = max_irq - bp->cp_nr_rings;
5979                 if (num <= 0)
5980                         return 0;
5981         }
5982         return num;
5983 }
5984
5985 static int bnxt_get_num_msix(struct bnxt *bp)
5986 {
5987         if (!BNXT_NEW_RM(bp))
5988                 return bnxt_get_max_func_irqs(bp);
5989
5990         return bnxt_cp_rings_in_use(bp);
5991 }
5992
5993 static int bnxt_init_msix(struct bnxt *bp)
5994 {
5995         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
5996         struct msix_entry *msix_ent;
5997
5998         total_vecs = bnxt_get_num_msix(bp);
5999         max = bnxt_get_max_func_irqs(bp);
6000         if (total_vecs > max)
6001                 total_vecs = max;
6002
6003         if (!total_vecs)
6004                 return 0;
6005
6006         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
6007         if (!msix_ent)
6008                 return -ENOMEM;
6009
6010         for (i = 0; i < total_vecs; i++) {
6011                 msix_ent[i].entry = i;
6012                 msix_ent[i].vector = 0;
6013         }
6014
6015         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6016                 min = 2;
6017
6018         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
6019         ulp_msix = bnxt_get_ulp_msix_num(bp);
6020         if (total_vecs < 0 || total_vecs < ulp_msix) {
6021                 rc = -ENODEV;
6022                 goto msix_setup_exit;
6023         }
6024
6025         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
6026         if (bp->irq_tbl) {
6027                 for (i = 0; i < total_vecs; i++)
6028                         bp->irq_tbl[i].vector = msix_ent[i].vector;
6029
6030                 bp->total_irqs = total_vecs;
6031                 /* Trim rings based upon num of vectors allocated */
6032                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
6033                                      total_vecs - ulp_msix, min == 1);
6034                 if (rc)
6035                         goto msix_setup_exit;
6036
6037                 bp->cp_nr_rings = (min == 1) ?
6038                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6039                                   bp->tx_nr_rings + bp->rx_nr_rings;
6040
6041         } else {
6042                 rc = -ENOMEM;
6043                 goto msix_setup_exit;
6044         }
6045         bp->flags |= BNXT_FLAG_USING_MSIX;
6046         kfree(msix_ent);
6047         return 0;
6048
6049 msix_setup_exit:
6050         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
6051         kfree(bp->irq_tbl);
6052         bp->irq_tbl = NULL;
6053         pci_disable_msix(bp->pdev);
6054         kfree(msix_ent);
6055         return rc;
6056 }
6057
6058 static int bnxt_init_inta(struct bnxt *bp)
6059 {
6060         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
6061         if (!bp->irq_tbl)
6062                 return -ENOMEM;
6063
6064         bp->total_irqs = 1;
6065         bp->rx_nr_rings = 1;
6066         bp->tx_nr_rings = 1;
6067         bp->cp_nr_rings = 1;
6068         bp->flags |= BNXT_FLAG_SHARED_RINGS;
6069         bp->irq_tbl[0].vector = bp->pdev->irq;
6070         return 0;
6071 }
6072
6073 static int bnxt_init_int_mode(struct bnxt *bp)
6074 {
6075         int rc = 0;
6076
6077         if (bp->flags & BNXT_FLAG_MSIX_CAP)
6078                 rc = bnxt_init_msix(bp);
6079
6080         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
6081                 /* fallback to INTA */
6082                 rc = bnxt_init_inta(bp);
6083         }
6084         return rc;
6085 }
6086
6087 static void bnxt_clear_int_mode(struct bnxt *bp)
6088 {
6089         if (bp->flags & BNXT_FLAG_USING_MSIX)
6090                 pci_disable_msix(bp->pdev);
6091
6092         kfree(bp->irq_tbl);
6093         bp->irq_tbl = NULL;
6094         bp->flags &= ~BNXT_FLAG_USING_MSIX;
6095 }
6096
6097 int bnxt_reserve_rings(struct bnxt *bp)
6098 {
6099         int tcs = netdev_get_num_tc(bp->dev);
6100         bool reinit_irq = false;
6101         int rc;
6102
6103         if (!bnxt_need_reserve_rings(bp))
6104                 return 0;
6105
6106         if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6107                 bnxt_ulp_irq_stop(bp);
6108                 bnxt_clear_int_mode(bp);
6109                 reinit_irq = true;
6110         }
6111         rc = __bnxt_reserve_rings(bp);
6112         if (reinit_irq) {
6113                 if (!rc)
6114                         rc = bnxt_init_int_mode(bp);
6115                 bnxt_ulp_irq_restart(bp, rc);
6116         }
6117         if (rc) {
6118                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
6119                 return rc;
6120         }
6121         if (tcs && (bp->tx_nr_rings_per_tc * tcs !=
6122                     bp->tx_nr_rings - bp->tx_nr_rings_xdp)) {
6123                 netdev_err(bp->dev, "tx ring reservation failure\n");
6124                 netdev_reset_tc(bp->dev);
6125                 if (bp->tx_nr_rings_xdp)
6126                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp;
6127                 else
6128                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6129                 return -ENOMEM;
6130         }
6131         bp->num_stat_ctxs = bp->cp_nr_rings;
6132         return 0;
6133 }
6134
6135 static void bnxt_free_irq(struct bnxt *bp)
6136 {
6137         struct bnxt_irq *irq;
6138         int i;
6139
6140 #ifdef CONFIG_RFS_ACCEL
6141         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
6142         bp->dev->rx_cpu_rmap = NULL;
6143 #endif
6144         if (!bp->irq_tbl || !bp->bnapi)
6145                 return;
6146
6147         for (i = 0; i < bp->cp_nr_rings; i++) {
6148                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6149
6150                 irq = &bp->irq_tbl[map_idx];
6151                 if (irq->requested) {
6152                         if (irq->have_cpumask) {
6153                                 irq_set_affinity_hint(irq->vector, NULL);
6154                                 free_cpumask_var(irq->cpu_mask);
6155                                 irq->have_cpumask = 0;
6156                         }
6157                         free_irq(irq->vector, bp->bnapi[i]);
6158                 }
6159
6160                 irq->requested = 0;
6161         }
6162 }
6163
6164 static int bnxt_request_irq(struct bnxt *bp)
6165 {
6166         int i, j, rc = 0;
6167         unsigned long flags = 0;
6168 #ifdef CONFIG_RFS_ACCEL
6169         struct cpu_rmap *rmap;
6170 #endif
6171
6172         rc = bnxt_setup_int_mode(bp);
6173         if (rc) {
6174                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6175                            rc);
6176                 return rc;
6177         }
6178 #ifdef CONFIG_RFS_ACCEL
6179         rmap = bp->dev->rx_cpu_rmap;
6180 #endif
6181         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
6182                 flags = IRQF_SHARED;
6183
6184         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
6185                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6186                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
6187
6188 #ifdef CONFIG_RFS_ACCEL
6189                 if (rmap && bp->bnapi[i]->rx_ring) {
6190                         rc = irq_cpu_rmap_add(rmap, irq->vector);
6191                         if (rc)
6192                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
6193                                             j);
6194                         j++;
6195                 }
6196 #endif
6197                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6198                                  bp->bnapi[i]);
6199                 if (rc)
6200                         break;
6201
6202                 irq->requested = 1;
6203
6204                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6205                         int numa_node = dev_to_node(&bp->pdev->dev);
6206
6207                         irq->have_cpumask = 1;
6208                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6209                                         irq->cpu_mask);
6210                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6211                         if (rc) {
6212                                 netdev_warn(bp->dev,
6213                                             "Set affinity failed, IRQ = %d\n",
6214                                             irq->vector);
6215                                 break;
6216                         }
6217                 }
6218         }
6219         return rc;
6220 }
6221
6222 static void bnxt_del_napi(struct bnxt *bp)
6223 {
6224         int i;
6225
6226         if (!bp->bnapi)
6227                 return;
6228
6229         for (i = 0; i < bp->cp_nr_rings; i++) {
6230                 struct bnxt_napi *bnapi = bp->bnapi[i];
6231
6232                 napi_hash_del(&bnapi->napi);
6233                 netif_napi_del(&bnapi->napi);
6234         }
6235         /* We called napi_hash_del() before netif_napi_del(), we need
6236          * to respect an RCU grace period before freeing napi structures.
6237          */
6238         synchronize_net();
6239 }
6240
6241 static void bnxt_init_napi(struct bnxt *bp)
6242 {
6243         int i;
6244         unsigned int cp_nr_rings = bp->cp_nr_rings;
6245         struct bnxt_napi *bnapi;
6246
6247         if (bp->flags & BNXT_FLAG_USING_MSIX) {
6248                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6249                         cp_nr_rings--;
6250                 for (i = 0; i < cp_nr_rings; i++) {
6251                         bnapi = bp->bnapi[i];
6252                         netif_napi_add(bp->dev, &bnapi->napi,
6253                                        bnxt_poll, 64);
6254                 }
6255                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6256                         bnapi = bp->bnapi[cp_nr_rings];
6257                         netif_napi_add(bp->dev, &bnapi->napi,
6258                                        bnxt_poll_nitroa0, 64);
6259                 }
6260         } else {
6261                 bnapi = bp->bnapi[0];
6262                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6263         }
6264 }
6265
6266 static void bnxt_disable_napi(struct bnxt *bp)
6267 {
6268         int i;
6269
6270         if (!bp->bnapi)
6271                 return;
6272
6273         for (i = 0; i < bp->cp_nr_rings; i++) {
6274                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6275
6276                 napi_disable(&bp->bnapi[i]->napi);
6277                 if (bp->bnapi[i]->rx_ring)
6278                         cancel_work_sync(&cpr->dim.work);
6279         }
6280 }
6281
6282 static void bnxt_enable_napi(struct bnxt *bp)
6283 {
6284         int i;
6285
6286         for (i = 0; i < bp->cp_nr_rings; i++) {
6287                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6288                 bp->bnapi[i]->in_reset = false;
6289
6290                 if (bp->bnapi[i]->rx_ring) {
6291                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6292                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6293                 }
6294                 napi_enable(&bp->bnapi[i]->napi);
6295         }
6296 }
6297
6298 void bnxt_tx_disable(struct bnxt *bp)
6299 {
6300         int i;
6301         struct bnxt_tx_ring_info *txr;
6302
6303         if (bp->tx_ring) {
6304                 for (i = 0; i < bp->tx_nr_rings; i++) {
6305                         txr = &bp->tx_ring[i];
6306                         WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
6307                 }
6308         }
6309         /* Make sure napi polls see @dev_state change */
6310         synchronize_net();
6311         /* Drop carrier first to prevent TX timeout */
6312         netif_carrier_off(bp->dev);
6313         /* Stop all TX queues */
6314         netif_tx_disable(bp->dev);
6315 }
6316
6317 void bnxt_tx_enable(struct bnxt *bp)
6318 {
6319         int i;
6320         struct bnxt_tx_ring_info *txr;
6321
6322         for (i = 0; i < bp->tx_nr_rings; i++) {
6323                 txr = &bp->tx_ring[i];
6324                 WRITE_ONCE(txr->dev_state, 0);
6325         }
6326         /* Make sure napi polls see @dev_state change */
6327         synchronize_net();
6328         netif_tx_wake_all_queues(bp->dev);
6329         if (bp->link_info.link_up)
6330                 netif_carrier_on(bp->dev);
6331 }
6332
6333 static void bnxt_report_link(struct bnxt *bp)
6334 {
6335         if (bp->link_info.link_up) {
6336                 const char *duplex;
6337                 const char *flow_ctrl;
6338                 u32 speed;
6339                 u16 fec;
6340
6341                 netif_carrier_on(bp->dev);
6342                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6343                 if (speed == SPEED_UNKNOWN) {
6344                         netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
6345                         return;
6346                 }
6347                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6348                         duplex = "full";
6349                 else
6350                         duplex = "half";
6351                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6352                         flow_ctrl = "ON - receive & transmit";
6353                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6354                         flow_ctrl = "ON - transmit";
6355                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6356                         flow_ctrl = "ON - receive";
6357                 else
6358                         flow_ctrl = "none";
6359                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6360                             speed, duplex, flow_ctrl);
6361                 if (bp->flags & BNXT_FLAG_EEE_CAP)
6362                         netdev_info(bp->dev, "EEE is %s\n",
6363                                     bp->eee.eee_active ? "active" :
6364                                                          "not active");
6365                 fec = bp->link_info.fec_cfg;
6366                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6367                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6368                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6369                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6370                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6371         } else {
6372                 netif_carrier_off(bp->dev);
6373                 netdev_err(bp->dev, "NIC Link is Down\n");
6374         }
6375 }
6376
6377 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6378 {
6379         int rc = 0;
6380         struct hwrm_port_phy_qcaps_input req = {0};
6381         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6382         struct bnxt_link_info *link_info = &bp->link_info;
6383
6384         if (bp->hwrm_spec_code < 0x10201)
6385                 return 0;
6386
6387         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6388
6389         mutex_lock(&bp->hwrm_cmd_lock);
6390         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6391         if (rc)
6392                 goto hwrm_phy_qcaps_exit;
6393
6394         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6395                 struct ethtool_eee *eee = &bp->eee;
6396                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6397
6398                 bp->flags |= BNXT_FLAG_EEE_CAP;
6399                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6400                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6401                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6402                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6403                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6404         }
6405         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
6406                 if (bp->test_info)
6407                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
6408         }
6409         if (resp->supported_speeds_auto_mode)
6410                 link_info->support_auto_speeds =
6411                         le16_to_cpu(resp->supported_speeds_auto_mode);
6412
6413         bp->port_count = resp->port_cnt;
6414
6415 hwrm_phy_qcaps_exit:
6416         mutex_unlock(&bp->hwrm_cmd_lock);
6417         return rc;
6418 }
6419
6420 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6421 {
6422         int rc = 0;
6423         struct bnxt_link_info *link_info = &bp->link_info;
6424         struct hwrm_port_phy_qcfg_input req = {0};
6425         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6426         u8 link_up = link_info->link_up;
6427         u16 diff;
6428
6429         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6430
6431         mutex_lock(&bp->hwrm_cmd_lock);
6432         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6433         if (rc) {
6434                 mutex_unlock(&bp->hwrm_cmd_lock);
6435                 return rc;
6436         }
6437
6438         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6439         link_info->phy_link_status = resp->link;
6440         link_info->duplex = resp->duplex_cfg;
6441         if (bp->hwrm_spec_code >= 0x10800)
6442                 link_info->duplex = resp->duplex_state;
6443         link_info->pause = resp->pause;
6444         link_info->auto_mode = resp->auto_mode;
6445         link_info->auto_pause_setting = resp->auto_pause;
6446         link_info->lp_pause = resp->link_partner_adv_pause;
6447         link_info->force_pause_setting = resp->force_pause;
6448         link_info->duplex_setting = resp->duplex_cfg;
6449         if (link_info->phy_link_status == BNXT_LINK_LINK)
6450                 link_info->link_speed = le16_to_cpu(resp->link_speed);
6451         else
6452                 link_info->link_speed = 0;
6453         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6454         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6455         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6456         link_info->lp_auto_link_speeds =
6457                 le16_to_cpu(resp->link_partner_adv_speeds);
6458         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6459         link_info->phy_ver[0] = resp->phy_maj;
6460         link_info->phy_ver[1] = resp->phy_min;
6461         link_info->phy_ver[2] = resp->phy_bld;
6462         link_info->media_type = resp->media_type;
6463         link_info->phy_type = resp->phy_type;
6464         link_info->transceiver = resp->xcvr_pkg_type;
6465         link_info->phy_addr = resp->eee_config_phy_addr &
6466                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6467         link_info->module_status = resp->module_status;
6468
6469         if (bp->flags & BNXT_FLAG_EEE_CAP) {
6470                 struct ethtool_eee *eee = &bp->eee;
6471                 u16 fw_speeds;
6472
6473                 eee->eee_active = 0;
6474                 if (resp->eee_config_phy_addr &
6475                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6476                         eee->eee_active = 1;
6477                         fw_speeds = le16_to_cpu(
6478                                 resp->link_partner_adv_eee_link_speed_mask);
6479                         eee->lp_advertised =
6480                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6481                 }
6482
6483                 /* Pull initial EEE config */
6484                 if (!chng_link_state) {
6485                         if (resp->eee_config_phy_addr &
6486                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6487                                 eee->eee_enabled = 1;
6488
6489                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6490                         eee->advertised =
6491                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6492
6493                         if (resp->eee_config_phy_addr &
6494                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6495                                 __le32 tmr;
6496
6497                                 eee->tx_lpi_enabled = 1;
6498                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6499                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6500                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6501                         }
6502                 }
6503         }
6504
6505         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6506         if (bp->hwrm_spec_code >= 0x10504)
6507                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6508
6509         /* TODO: need to add more logic to report VF link */
6510         if (chng_link_state) {
6511                 if (link_info->phy_link_status == BNXT_LINK_LINK)
6512                         link_info->link_up = 1;
6513                 else
6514                         link_info->link_up = 0;
6515                 if (link_up != link_info->link_up)
6516                         bnxt_report_link(bp);
6517         } else {
6518                 /* alwasy link down if not require to update link state */
6519                 link_info->link_up = 0;
6520         }
6521         mutex_unlock(&bp->hwrm_cmd_lock);
6522
6523         if (!BNXT_SINGLE_PF(bp))
6524                 return 0;
6525
6526         diff = link_info->support_auto_speeds ^ link_info->advertising;
6527         if ((link_info->support_auto_speeds | diff) !=
6528             link_info->support_auto_speeds) {
6529                 /* An advertised speed is no longer supported, so we need to
6530                  * update the advertisement settings.  Caller holds RTNL
6531                  * so we can modify link settings.
6532                  */
6533                 link_info->advertising = link_info->support_auto_speeds;
6534                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6535                         bnxt_hwrm_set_link_setting(bp, true, false);
6536         }
6537         return 0;
6538 }
6539
6540 static void bnxt_get_port_module_status(struct bnxt *bp)
6541 {
6542         struct bnxt_link_info *link_info = &bp->link_info;
6543         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6544         u8 module_status;
6545
6546         if (bnxt_update_link(bp, true))
6547                 return;
6548
6549         module_status = link_info->module_status;
6550         switch (module_status) {
6551         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6552         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6553         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6554                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6555                             bp->pf.port_id);
6556                 if (bp->hwrm_spec_code >= 0x10201) {
6557                         netdev_warn(bp->dev, "Module part number %s\n",
6558                                     resp->phy_vendor_partnumber);
6559                 }
6560                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6561                         netdev_warn(bp->dev, "TX is disabled\n");
6562                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6563                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6564         }
6565 }
6566
6567 static void
6568 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6569 {
6570         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6571                 if (bp->hwrm_spec_code >= 0x10201)
6572                         req->auto_pause =
6573                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6574                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6575                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6576                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6577                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6578                 req->enables |=
6579                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6580         } else {
6581                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6582                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6583                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6584                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6585                 req->enables |=
6586                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6587                 if (bp->hwrm_spec_code >= 0x10201) {
6588                         req->auto_pause = req->force_pause;
6589                         req->enables |= cpu_to_le32(
6590                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6591                 }
6592         }
6593 }
6594
6595 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6596                                       struct hwrm_port_phy_cfg_input *req)
6597 {
6598         u8 autoneg = bp->link_info.autoneg;
6599         u16 fw_link_speed = bp->link_info.req_link_speed;
6600         u16 advertising = bp->link_info.advertising;
6601
6602         if (autoneg & BNXT_AUTONEG_SPEED) {
6603                 req->auto_mode |=
6604                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6605
6606                 req->enables |= cpu_to_le32(
6607                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6608                 req->auto_link_speed_mask = cpu_to_le16(advertising);
6609
6610                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6611                 req->flags |=
6612                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6613         } else {
6614                 req->force_link_speed = cpu_to_le16(fw_link_speed);
6615                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6616         }
6617
6618         /* tell chimp that the setting takes effect immediately */
6619         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6620 }
6621
6622 int bnxt_hwrm_set_pause(struct bnxt *bp)
6623 {
6624         struct hwrm_port_phy_cfg_input req = {0};
6625         int rc;
6626
6627         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6628         bnxt_hwrm_set_pause_common(bp, &req);
6629
6630         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6631             bp->link_info.force_link_chng)
6632                 bnxt_hwrm_set_link_common(bp, &req);
6633
6634         mutex_lock(&bp->hwrm_cmd_lock);
6635         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6636         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6637                 /* since changing of pause setting doesn't trigger any link
6638                  * change event, the driver needs to update the current pause
6639                  * result upon successfully return of the phy_cfg command
6640                  */
6641                 bp->link_info.pause =
6642                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6643                 bp->link_info.auto_pause_setting = 0;
6644                 if (!bp->link_info.force_link_chng)
6645                         bnxt_report_link(bp);
6646         }
6647         bp->link_info.force_link_chng = false;
6648         mutex_unlock(&bp->hwrm_cmd_lock);
6649         return rc;
6650 }
6651
6652 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6653                               struct hwrm_port_phy_cfg_input *req)
6654 {
6655         struct ethtool_eee *eee = &bp->eee;
6656
6657         if (eee->eee_enabled) {
6658                 u16 eee_speeds;
6659                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6660
6661                 if (eee->tx_lpi_enabled)
6662                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6663                 else
6664                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6665
6666                 req->flags |= cpu_to_le32(flags);
6667                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6668                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6669                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6670         } else {
6671                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6672         }
6673 }
6674
6675 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6676 {
6677         struct hwrm_port_phy_cfg_input req = {0};
6678
6679         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6680         if (set_pause)
6681                 bnxt_hwrm_set_pause_common(bp, &req);
6682
6683         bnxt_hwrm_set_link_common(bp, &req);
6684
6685         if (set_eee)
6686                 bnxt_hwrm_set_eee(bp, &req);
6687         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6688 }
6689
6690 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6691 {
6692         struct hwrm_port_phy_cfg_input req = {0};
6693
6694         if (!BNXT_SINGLE_PF(bp))
6695                 return 0;
6696
6697         if (pci_num_vf(bp->pdev))
6698                 return 0;
6699
6700         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6701         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6702         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6703 }
6704
6705 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
6706 {
6707         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
6708         struct hwrm_func_drv_if_change_input req = {0};
6709         bool resc_reinit = false;
6710         int rc;
6711
6712         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
6713                 return 0;
6714
6715         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
6716         if (up)
6717                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
6718         mutex_lock(&bp->hwrm_cmd_lock);
6719         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6720         if (!rc && (resp->flags &
6721                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
6722                 resc_reinit = true;
6723         mutex_unlock(&bp->hwrm_cmd_lock);
6724
6725         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
6726                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6727
6728                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6729                 hw_resc->resv_cp_rings = 0;
6730                 hw_resc->resv_tx_rings = 0;
6731                 hw_resc->resv_rx_rings = 0;
6732                 hw_resc->resv_hw_ring_grps = 0;
6733                 hw_resc->resv_vnics = 0;
6734                 bp->tx_nr_rings = 0;
6735                 bp->rx_nr_rings = 0;
6736         }
6737         return rc;
6738 }
6739
6740 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6741 {
6742         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6743         struct hwrm_port_led_qcaps_input req = {0};
6744         struct bnxt_pf_info *pf = &bp->pf;
6745         int rc;
6746
6747         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6748                 return 0;
6749
6750         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6751         req.port_id = cpu_to_le16(pf->port_id);
6752         mutex_lock(&bp->hwrm_cmd_lock);
6753         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6754         if (rc) {
6755                 mutex_unlock(&bp->hwrm_cmd_lock);
6756                 return rc;
6757         }
6758         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6759                 int i;
6760
6761                 bp->num_leds = resp->num_leds;
6762                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6763                                                  bp->num_leds);
6764                 for (i = 0; i < bp->num_leds; i++) {
6765                         struct bnxt_led_info *led = &bp->leds[i];
6766                         __le16 caps = led->led_state_caps;
6767
6768                         if (!led->led_group_id ||
6769                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
6770                                 bp->num_leds = 0;
6771                                 break;
6772                         }
6773                 }
6774         }
6775         mutex_unlock(&bp->hwrm_cmd_lock);
6776         return 0;
6777 }
6778
6779 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6780 {
6781         struct hwrm_wol_filter_alloc_input req = {0};
6782         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6783         int rc;
6784
6785         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6786         req.port_id = cpu_to_le16(bp->pf.port_id);
6787         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6788         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6789         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6790         mutex_lock(&bp->hwrm_cmd_lock);
6791         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6792         if (!rc)
6793                 bp->wol_filter_id = resp->wol_filter_id;
6794         mutex_unlock(&bp->hwrm_cmd_lock);
6795         return rc;
6796 }
6797
6798 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6799 {
6800         struct hwrm_wol_filter_free_input req = {0};
6801         int rc;
6802
6803         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6804         req.port_id = cpu_to_le16(bp->pf.port_id);
6805         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6806         req.wol_filter_id = bp->wol_filter_id;
6807         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6808         return rc;
6809 }
6810
6811 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6812 {
6813         struct hwrm_wol_filter_qcfg_input req = {0};
6814         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6815         u16 next_handle = 0;
6816         int rc;
6817
6818         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6819         req.port_id = cpu_to_le16(bp->pf.port_id);
6820         req.handle = cpu_to_le16(handle);
6821         mutex_lock(&bp->hwrm_cmd_lock);
6822         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6823         if (!rc) {
6824                 next_handle = le16_to_cpu(resp->next_handle);
6825                 if (next_handle != 0) {
6826                         if (resp->wol_type ==
6827                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6828                                 bp->wol = 1;
6829                                 bp->wol_filter_id = resp->wol_filter_id;
6830                         }
6831                 }
6832         }
6833         mutex_unlock(&bp->hwrm_cmd_lock);
6834         return next_handle;
6835 }
6836
6837 static void bnxt_get_wol_settings(struct bnxt *bp)
6838 {
6839         u16 handle = 0;
6840
6841         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6842                 return;
6843
6844         do {
6845                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6846         } while (handle && handle != 0xffff);
6847 }
6848
6849 #ifdef CONFIG_BNXT_HWMON
6850 static ssize_t bnxt_show_temp(struct device *dev,
6851                               struct device_attribute *devattr, char *buf)
6852 {
6853         struct hwrm_temp_monitor_query_input req = {0};
6854         struct hwrm_temp_monitor_query_output *resp;
6855         struct bnxt *bp = dev_get_drvdata(dev);
6856         u32 len = 0;
6857         int rc;
6858
6859         resp = bp->hwrm_cmd_resp_addr;
6860         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
6861         mutex_lock(&bp->hwrm_cmd_lock);
6862         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6863         if (!rc)
6864                 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
6865         mutex_unlock(&bp->hwrm_cmd_lock);
6866         if (rc)
6867                 return rc;
6868         return len;
6869 }
6870 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
6871
6872 static struct attribute *bnxt_attrs[] = {
6873         &sensor_dev_attr_temp1_input.dev_attr.attr,
6874         NULL
6875 };
6876 ATTRIBUTE_GROUPS(bnxt);
6877
6878 static void bnxt_hwmon_close(struct bnxt *bp)
6879 {
6880         if (bp->hwmon_dev) {
6881                 hwmon_device_unregister(bp->hwmon_dev);
6882                 bp->hwmon_dev = NULL;
6883         }
6884 }
6885
6886 static void bnxt_hwmon_open(struct bnxt *bp)
6887 {
6888         struct hwrm_temp_monitor_query_input req = {0};
6889         struct pci_dev *pdev = bp->pdev;
6890         int rc;
6891
6892         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
6893         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6894         if (rc == -EACCES || rc == -EOPNOTSUPP) {
6895                 bnxt_hwmon_close(bp);
6896                 return;
6897         }
6898
6899         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
6900                                                           DRV_MODULE_NAME, bp,
6901                                                           bnxt_groups);
6902         if (IS_ERR(bp->hwmon_dev)) {
6903                 bp->hwmon_dev = NULL;
6904                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
6905         }
6906 }
6907 #else
6908 static void bnxt_hwmon_close(struct bnxt *bp)
6909 {
6910 }
6911
6912 static void bnxt_hwmon_open(struct bnxt *bp)
6913 {
6914 }
6915 #endif
6916
6917 static bool bnxt_eee_config_ok(struct bnxt *bp)
6918 {
6919         struct ethtool_eee *eee = &bp->eee;
6920         struct bnxt_link_info *link_info = &bp->link_info;
6921
6922         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6923                 return true;
6924
6925         if (eee->eee_enabled) {
6926                 u32 advertising =
6927                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6928
6929                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6930                         eee->eee_enabled = 0;
6931                         return false;
6932                 }
6933                 if (eee->advertised & ~advertising) {
6934                         eee->advertised = advertising & eee->supported;
6935                         return false;
6936                 }
6937         }
6938         return true;
6939 }
6940
6941 static int bnxt_update_phy_setting(struct bnxt *bp)
6942 {
6943         int rc;
6944         bool update_link = false;
6945         bool update_pause = false;
6946         bool update_eee = false;
6947         struct bnxt_link_info *link_info = &bp->link_info;
6948
6949         rc = bnxt_update_link(bp, true);
6950         if (rc) {
6951                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6952                            rc);
6953                 return rc;
6954         }
6955         if (!BNXT_SINGLE_PF(bp))
6956                 return 0;
6957
6958         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6959             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6960             link_info->req_flow_ctrl)
6961                 update_pause = true;
6962         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6963             link_info->force_pause_setting != link_info->req_flow_ctrl)
6964                 update_pause = true;
6965         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6966                 if (BNXT_AUTO_MODE(link_info->auto_mode))
6967                         update_link = true;
6968                 if (link_info->req_link_speed != link_info->force_link_speed)
6969                         update_link = true;
6970                 if (link_info->req_duplex != link_info->duplex_setting)
6971                         update_link = true;
6972         } else {
6973                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6974                         update_link = true;
6975                 if (link_info->advertising != link_info->auto_link_speeds)
6976                         update_link = true;
6977         }
6978
6979         /* The last close may have shutdown the link, so need to call
6980          * PHY_CFG to bring it back up.
6981          */
6982         if (!netif_carrier_ok(bp->dev))
6983                 update_link = true;
6984
6985         if (!bnxt_eee_config_ok(bp))
6986                 update_eee = true;
6987
6988         if (update_link)
6989                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6990         else if (update_pause)
6991                 rc = bnxt_hwrm_set_pause(bp);
6992         if (rc) {
6993                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6994                            rc);
6995                 return rc;
6996         }
6997
6998         return rc;
6999 }
7000
7001 /* Common routine to pre-map certain register block to different GRC window.
7002  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
7003  * in PF and 3 windows in VF that can be customized to map in different
7004  * register blocks.
7005  */
7006 static void bnxt_preset_reg_win(struct bnxt *bp)
7007 {
7008         if (BNXT_PF(bp)) {
7009                 /* CAG registers map to GRC window #4 */
7010                 writel(BNXT_CAG_REG_BASE,
7011                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
7012         }
7013 }
7014
7015 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
7016
7017 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7018 {
7019         int rc = 0;
7020
7021         bnxt_preset_reg_win(bp);
7022         netif_carrier_off(bp->dev);
7023         if (irq_re_init) {
7024                 /* Reserve rings now if none were reserved at driver probe. */
7025                 rc = bnxt_init_dflt_ring_mode(bp);
7026                 if (rc) {
7027                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
7028                         return rc;
7029                 }
7030                 rc = bnxt_reserve_rings(bp);
7031                 if (rc)
7032                         return rc;
7033         }
7034         if ((bp->flags & BNXT_FLAG_RFS) &&
7035             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
7036                 /* disable RFS if falling back to INTA */
7037                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
7038                 bp->flags &= ~BNXT_FLAG_RFS;
7039         }
7040
7041         rc = bnxt_alloc_mem(bp, irq_re_init);
7042         if (rc) {
7043                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7044                 goto open_err_free_mem;
7045         }
7046
7047         if (irq_re_init) {
7048                 bnxt_init_napi(bp);
7049                 rc = bnxt_request_irq(bp);
7050                 if (rc) {
7051                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
7052                         goto open_err_irq;
7053                 }
7054         }
7055
7056         rc = bnxt_init_nic(bp, irq_re_init);
7057         if (rc) {
7058                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7059                 goto open_err_irq;
7060         }
7061
7062         bnxt_enable_napi(bp);
7063         bnxt_debug_dev_init(bp);
7064
7065         if (link_re_init) {
7066                 mutex_lock(&bp->link_lock);
7067                 rc = bnxt_update_phy_setting(bp);
7068                 mutex_unlock(&bp->link_lock);
7069                 if (rc) {
7070                         netdev_warn(bp->dev, "failed to update phy settings\n");
7071                         if (BNXT_SINGLE_PF(bp)) {
7072                                 bp->link_info.phy_retry = true;
7073                                 bp->link_info.phy_retry_expires =
7074                                         jiffies + 5 * HZ;
7075                         }
7076                 }
7077         }
7078
7079         if (irq_re_init)
7080                 udp_tunnel_get_rx_info(bp->dev);
7081
7082         set_bit(BNXT_STATE_OPEN, &bp->state);
7083         bnxt_enable_int(bp);
7084         /* Enable TX queues */
7085         bnxt_tx_enable(bp);
7086         mod_timer(&bp->timer, jiffies + bp->current_interval);
7087         /* Poll link status and check for SFP+ module status */
7088         bnxt_get_port_module_status(bp);
7089
7090         /* VF-reps may need to be re-opened after the PF is re-opened */
7091         if (BNXT_PF(bp))
7092                 bnxt_vf_reps_open(bp);
7093         return 0;
7094
7095 open_err_irq:
7096         bnxt_del_napi(bp);
7097
7098 open_err_free_mem:
7099         bnxt_free_skbs(bp);
7100         bnxt_free_irq(bp);
7101         bnxt_free_mem(bp, true);
7102         return rc;
7103 }
7104
7105 /* rtnl_lock held */
7106 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7107 {
7108         int rc = 0;
7109
7110         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
7111         if (rc) {
7112                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
7113                 dev_close(bp->dev);
7114         }
7115         return rc;
7116 }
7117
7118 /* rtnl_lock held, open the NIC half way by allocating all resources, but
7119  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
7120  * self tests.
7121  */
7122 int bnxt_half_open_nic(struct bnxt *bp)
7123 {
7124         int rc = 0;
7125
7126         rc = bnxt_alloc_mem(bp, false);
7127         if (rc) {
7128                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7129                 goto half_open_err;
7130         }
7131         rc = bnxt_init_nic(bp, false);
7132         if (rc) {
7133                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7134                 goto half_open_err;
7135         }
7136         return 0;
7137
7138 half_open_err:
7139         bnxt_free_skbs(bp);
7140         bnxt_free_mem(bp, false);
7141         dev_close(bp->dev);
7142         return rc;
7143 }
7144
7145 /* rtnl_lock held, this call can only be made after a previous successful
7146  * call to bnxt_half_open_nic().
7147  */
7148 void bnxt_half_close_nic(struct bnxt *bp)
7149 {
7150         bnxt_hwrm_resource_free(bp, false, false);
7151         bnxt_free_skbs(bp);
7152         bnxt_free_mem(bp, false);
7153 }
7154
7155 static int bnxt_open(struct net_device *dev)
7156 {
7157         struct bnxt *bp = netdev_priv(dev);
7158         int rc;
7159
7160         bnxt_hwrm_if_change(bp, true);
7161         rc = __bnxt_open_nic(bp, true, true);
7162         if (rc)
7163                 bnxt_hwrm_if_change(bp, false);
7164
7165         bnxt_hwmon_open(bp);
7166
7167         return rc;
7168 }
7169
7170 static bool bnxt_drv_busy(struct bnxt *bp)
7171 {
7172         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
7173                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
7174 }
7175
7176 static void bnxt_get_ring_stats(struct bnxt *bp,
7177                                 struct rtnl_link_stats64 *stats);
7178
7179 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
7180                              bool link_re_init)
7181 {
7182         /* Close the VF-reps before closing PF */
7183         if (BNXT_PF(bp))
7184                 bnxt_vf_reps_close(bp);
7185
7186         /* Change device state to avoid TX queue wake up's */
7187         bnxt_tx_disable(bp);
7188
7189         clear_bit(BNXT_STATE_OPEN, &bp->state);
7190         smp_mb__after_atomic();
7191         while (bnxt_drv_busy(bp))
7192                 msleep(20);
7193
7194         /* Flush rings and and disable interrupts */
7195         bnxt_shutdown_nic(bp, irq_re_init);
7196
7197         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
7198
7199         bnxt_debug_dev_exit(bp);
7200         bnxt_disable_napi(bp);
7201         del_timer_sync(&bp->timer);
7202         bnxt_free_skbs(bp);
7203
7204         /* Save ring stats before shutdown */
7205         if (bp->bnapi && irq_re_init)
7206                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
7207         if (irq_re_init) {
7208                 bnxt_free_irq(bp);
7209                 bnxt_del_napi(bp);
7210         }
7211         bnxt_free_mem(bp, irq_re_init);
7212 }
7213
7214 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7215 {
7216         int rc = 0;
7217
7218 #ifdef CONFIG_BNXT_SRIOV
7219         if (bp->sriov_cfg) {
7220                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
7221                                                       !bp->sriov_cfg,
7222                                                       BNXT_SRIOV_CFG_WAIT_TMO);
7223                 if (rc)
7224                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
7225         }
7226 #endif
7227         __bnxt_close_nic(bp, irq_re_init, link_re_init);
7228         return rc;
7229 }
7230
7231 static int bnxt_close(struct net_device *dev)
7232 {
7233         struct bnxt *bp = netdev_priv(dev);
7234
7235         bnxt_hwmon_close(bp);
7236         bnxt_close_nic(bp, true, true);
7237         bnxt_hwrm_shutdown_link(bp);
7238         bnxt_hwrm_if_change(bp, false);
7239         return 0;
7240 }
7241
7242 /* rtnl_lock held */
7243 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7244 {
7245         switch (cmd) {
7246         case SIOCGMIIPHY:
7247                 /* fallthru */
7248         case SIOCGMIIREG: {
7249                 if (!netif_running(dev))
7250                         return -EAGAIN;
7251
7252                 return 0;
7253         }
7254
7255         case SIOCSMIIREG:
7256                 if (!netif_running(dev))
7257                         return -EAGAIN;
7258
7259                 return 0;
7260
7261         default:
7262                 /* do nothing */
7263                 break;
7264         }
7265         return -EOPNOTSUPP;
7266 }
7267
7268 static void bnxt_get_ring_stats(struct bnxt *bp,
7269                                 struct rtnl_link_stats64 *stats)
7270 {
7271         int i;
7272
7273
7274         for (i = 0; i < bp->cp_nr_rings; i++) {
7275                 struct bnxt_napi *bnapi = bp->bnapi[i];
7276                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7277                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
7278
7279                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7280                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7281                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
7282
7283                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7284                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7285                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
7286
7287                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7288                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7289                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
7290
7291                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7292                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7293                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
7294
7295                 stats->rx_missed_errors +=
7296                         le64_to_cpu(hw_stats->rx_discard_pkts);
7297
7298                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
7299
7300                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
7301         }
7302 }
7303
7304 static void bnxt_add_prev_stats(struct bnxt *bp,
7305                                 struct rtnl_link_stats64 *stats)
7306 {
7307         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
7308
7309         stats->rx_packets += prev_stats->rx_packets;
7310         stats->tx_packets += prev_stats->tx_packets;
7311         stats->rx_bytes += prev_stats->rx_bytes;
7312         stats->tx_bytes += prev_stats->tx_bytes;
7313         stats->rx_missed_errors += prev_stats->rx_missed_errors;
7314         stats->multicast += prev_stats->multicast;
7315         stats->tx_dropped += prev_stats->tx_dropped;
7316 }
7317
7318 static void
7319 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7320 {
7321         struct bnxt *bp = netdev_priv(dev);
7322
7323         set_bit(BNXT_STATE_READ_STATS, &bp->state);
7324         /* Make sure bnxt_close_nic() sees that we are reading stats before
7325          * we check the BNXT_STATE_OPEN flag.
7326          */
7327         smp_mb__after_atomic();
7328         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7329                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7330                 *stats = bp->net_stats_prev;
7331                 return;
7332         }
7333
7334         bnxt_get_ring_stats(bp, stats);
7335         bnxt_add_prev_stats(bp, stats);
7336
7337         if (bp->flags & BNXT_FLAG_PORT_STATS) {
7338                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
7339                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
7340
7341                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7342                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7343                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7344                                           le64_to_cpu(rx->rx_ovrsz_frames) +
7345                                           le64_to_cpu(rx->rx_runt_frames);
7346                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7347                                    le64_to_cpu(rx->rx_jbr_frames);
7348                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7349                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7350                 stats->tx_errors = le64_to_cpu(tx->tx_err);
7351         }
7352         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7353 }
7354
7355 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
7356 {
7357         struct net_device *dev = bp->dev;
7358         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7359         struct netdev_hw_addr *ha;
7360         u8 *haddr;
7361         int mc_count = 0;
7362         bool update = false;
7363         int off = 0;
7364
7365         netdev_for_each_mc_addr(ha, dev) {
7366                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7367                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7368                         vnic->mc_list_count = 0;
7369                         return false;
7370                 }
7371                 haddr = ha->addr;
7372                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7373                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7374                         update = true;
7375                 }
7376                 off += ETH_ALEN;
7377                 mc_count++;
7378         }
7379         if (mc_count)
7380                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7381
7382         if (mc_count != vnic->mc_list_count) {
7383                 vnic->mc_list_count = mc_count;
7384                 update = true;
7385         }
7386         return update;
7387 }
7388
7389 static bool bnxt_uc_list_updated(struct bnxt *bp)
7390 {
7391         struct net_device *dev = bp->dev;
7392         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7393         struct netdev_hw_addr *ha;
7394         int off = 0;
7395
7396         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7397                 return true;
7398
7399         netdev_for_each_uc_addr(ha, dev) {
7400                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7401                         return true;
7402
7403                 off += ETH_ALEN;
7404         }
7405         return false;
7406 }
7407
7408 static void bnxt_set_rx_mode(struct net_device *dev)
7409 {
7410         struct bnxt *bp = netdev_priv(dev);
7411         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7412         u32 mask = vnic->rx_mask;
7413         bool mc_update = false;
7414         bool uc_update;
7415
7416         if (!netif_running(dev))
7417                 return;
7418
7419         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7420                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7421                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
7422                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
7423
7424         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7425                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7426
7427         uc_update = bnxt_uc_list_updated(bp);
7428
7429         if (dev->flags & IFF_BROADCAST)
7430                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7431         if (dev->flags & IFF_ALLMULTI) {
7432                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7433                 vnic->mc_list_count = 0;
7434         } else {
7435                 mc_update = bnxt_mc_list_updated(bp, &mask);
7436         }
7437
7438         if (mask != vnic->rx_mask || uc_update || mc_update) {
7439                 vnic->rx_mask = mask;
7440
7441                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7442                 bnxt_queue_sp_work(bp);
7443         }
7444 }
7445
7446 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7447 {
7448         struct net_device *dev = bp->dev;
7449         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7450         struct netdev_hw_addr *ha;
7451         int i, off = 0, rc;
7452         bool uc_update;
7453
7454         netif_addr_lock_bh(dev);
7455         uc_update = bnxt_uc_list_updated(bp);
7456         netif_addr_unlock_bh(dev);
7457
7458         if (!uc_update)
7459                 goto skip_uc;
7460
7461         mutex_lock(&bp->hwrm_cmd_lock);
7462         for (i = 1; i < vnic->uc_filter_count; i++) {
7463                 struct hwrm_cfa_l2_filter_free_input req = {0};
7464
7465                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7466                                        -1);
7467
7468                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7469
7470                 rc = _hwrm_send_message(bp, &req, sizeof(req),
7471                                         HWRM_CMD_TIMEOUT);
7472         }
7473         mutex_unlock(&bp->hwrm_cmd_lock);
7474
7475         vnic->uc_filter_count = 1;
7476
7477         netif_addr_lock_bh(dev);
7478         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7479                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7480         } else {
7481                 netdev_for_each_uc_addr(ha, dev) {
7482                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7483                         off += ETH_ALEN;
7484                         vnic->uc_filter_count++;
7485                 }
7486         }
7487         netif_addr_unlock_bh(dev);
7488
7489         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7490                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7491                 if (rc) {
7492                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7493                                    rc);
7494                         vnic->uc_filter_count = i;
7495                         return rc;
7496                 }
7497         }
7498
7499 skip_uc:
7500         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7501         if (rc && vnic->mc_list_count) {
7502                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
7503                             rc);
7504                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7505                 vnic->mc_list_count = 0;
7506                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7507         }
7508         if (rc)
7509                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
7510                            rc);
7511
7512         return rc;
7513 }
7514
7515 static bool bnxt_can_reserve_rings(struct bnxt *bp)
7516 {
7517 #ifdef CONFIG_BNXT_SRIOV
7518         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
7519                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7520
7521                 /* No minimum rings were provisioned by the PF.  Don't
7522                  * reserve rings by default when device is down.
7523                  */
7524                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
7525                         return true;
7526
7527                 if (!netif_running(bp->dev))
7528                         return false;
7529         }
7530 #endif
7531         return true;
7532 }
7533
7534 /* If the chip and firmware supports RFS */
7535 static bool bnxt_rfs_supported(struct bnxt *bp)
7536 {
7537         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7538                 return true;
7539         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7540                 return true;
7541         return false;
7542 }
7543
7544 /* If runtime conditions support RFS */
7545 static bool bnxt_rfs_capable(struct bnxt *bp)
7546 {
7547 #ifdef CONFIG_RFS_ACCEL
7548         int vnics, max_vnics, max_rss_ctxs;
7549
7550         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
7551                 return false;
7552
7553         vnics = 1 + bp->rx_nr_rings;
7554         max_vnics = bnxt_get_max_func_vnics(bp);
7555         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7556
7557         /* RSS contexts not a limiting factor */
7558         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7559                 max_rss_ctxs = max_vnics;
7560         if (vnics > max_vnics || vnics > max_rss_ctxs) {
7561                 if (bp->rx_nr_rings > 1)
7562                         netdev_warn(bp->dev,
7563                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7564                                     min(max_rss_ctxs - 1, max_vnics - 1));
7565                 return false;
7566         }
7567
7568         if (!BNXT_NEW_RM(bp))
7569                 return true;
7570
7571         if (vnics == bp->hw_resc.resv_vnics)
7572                 return true;
7573
7574         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7575         if (vnics <= bp->hw_resc.resv_vnics)
7576                 return true;
7577
7578         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7579         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7580         return false;
7581 #else
7582         return false;
7583 #endif
7584 }
7585
7586 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7587                                            netdev_features_t features)
7588 {
7589         struct bnxt *bp = netdev_priv(dev);
7590         netdev_features_t vlan_features;
7591
7592         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7593                 features &= ~NETIF_F_NTUPLE;
7594
7595         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7596                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7597
7598         if (!(features & NETIF_F_GRO))
7599                 features &= ~NETIF_F_GRO_HW;
7600
7601         if (features & NETIF_F_GRO_HW)
7602                 features &= ~NETIF_F_LRO;
7603
7604         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7605          * turned on or off together.
7606          */
7607         vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX |
7608                                     NETIF_F_HW_VLAN_STAG_RX);
7609         if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX |
7610                               NETIF_F_HW_VLAN_STAG_RX)) {
7611                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7612                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7613                                       NETIF_F_HW_VLAN_STAG_RX);
7614                 else if (vlan_features)
7615                         features |= NETIF_F_HW_VLAN_CTAG_RX |
7616                                     NETIF_F_HW_VLAN_STAG_RX;
7617         }
7618 #ifdef CONFIG_BNXT_SRIOV
7619         if (BNXT_VF(bp)) {
7620                 if (bp->vf.vlan) {
7621                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7622                                       NETIF_F_HW_VLAN_STAG_RX);
7623                 }
7624         }
7625 #endif
7626         return features;
7627 }
7628
7629 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7630 {
7631         struct bnxt *bp = netdev_priv(dev);
7632         u32 flags = bp->flags;
7633         u32 changes;
7634         int rc = 0;
7635         bool re_init = false;
7636         bool update_tpa = false;
7637
7638         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7639         if (features & NETIF_F_GRO_HW)
7640                 flags |= BNXT_FLAG_GRO;
7641         else if (features & NETIF_F_LRO)
7642                 flags |= BNXT_FLAG_LRO;
7643
7644         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7645                 flags &= ~BNXT_FLAG_TPA;
7646
7647         if (features & NETIF_F_HW_VLAN_CTAG_RX)
7648                 flags |= BNXT_FLAG_STRIP_VLAN;
7649
7650         if (features & NETIF_F_NTUPLE)
7651                 flags |= BNXT_FLAG_RFS;
7652
7653         changes = flags ^ bp->flags;
7654         if (changes & BNXT_FLAG_TPA) {
7655                 update_tpa = true;
7656                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7657                     (flags & BNXT_FLAG_TPA) == 0)
7658                         re_init = true;
7659         }
7660
7661         if (changes & ~BNXT_FLAG_TPA)
7662                 re_init = true;
7663
7664         if (flags != bp->flags) {
7665                 u32 old_flags = bp->flags;
7666
7667                 bp->flags = flags;
7668
7669                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7670                         if (update_tpa)
7671                                 bnxt_set_ring_params(bp);
7672                         return rc;
7673                 }
7674
7675                 if (re_init) {
7676                         bnxt_close_nic(bp, false, false);
7677                         if (update_tpa)
7678                                 bnxt_set_ring_params(bp);
7679
7680                         return bnxt_open_nic(bp, false, false);
7681                 }
7682                 if (update_tpa) {
7683                         rc = bnxt_set_tpa(bp,
7684                                           (flags & BNXT_FLAG_TPA) ?
7685                                           true : false);
7686                         if (rc)
7687                                 bp->flags = old_flags;
7688                 }
7689         }
7690         return rc;
7691 }
7692
7693 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7694 {
7695         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7696         int i = bnapi->index;
7697
7698         if (!txr)
7699                 return;
7700
7701         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7702                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7703                     txr->tx_cons);
7704 }
7705
7706 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7707 {
7708         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7709         int i = bnapi->index;
7710
7711         if (!rxr)
7712                 return;
7713
7714         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7715                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7716                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7717                     rxr->rx_sw_agg_prod);
7718 }
7719
7720 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7721 {
7722         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7723         int i = bnapi->index;
7724
7725         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7726                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7727 }
7728
7729 static void bnxt_dbg_dump_states(struct bnxt *bp)
7730 {
7731         int i;
7732         struct bnxt_napi *bnapi;
7733
7734         for (i = 0; i < bp->cp_nr_rings; i++) {
7735                 bnapi = bp->bnapi[i];
7736                 if (netif_msg_drv(bp)) {
7737                         bnxt_dump_tx_sw_state(bnapi);
7738                         bnxt_dump_rx_sw_state(bnapi);
7739                         bnxt_dump_cp_sw_state(bnapi);
7740                 }
7741         }
7742 }
7743
7744 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7745 {
7746         if (!silent)
7747                 bnxt_dbg_dump_states(bp);
7748         if (netif_running(bp->dev)) {
7749                 int rc;
7750
7751                 if (!silent)
7752                         bnxt_ulp_stop(bp);
7753                 bnxt_close_nic(bp, false, false);
7754                 rc = bnxt_open_nic(bp, false, false);
7755                 if (!silent && !rc)
7756                         bnxt_ulp_start(bp);
7757         }
7758 }
7759
7760 static void bnxt_tx_timeout(struct net_device *dev)
7761 {
7762         struct bnxt *bp = netdev_priv(dev);
7763
7764         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
7765         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7766         bnxt_queue_sp_work(bp);
7767 }
7768
7769 static void bnxt_timer(struct timer_list *t)
7770 {
7771         struct bnxt *bp = from_timer(bp, t, timer);
7772         struct net_device *dev = bp->dev;
7773
7774         if (!netif_running(dev))
7775                 return;
7776
7777         if (atomic_read(&bp->intr_sem) != 0)
7778                 goto bnxt_restart_timer;
7779
7780         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7781             bp->stats_coal_ticks) {
7782                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7783                 bnxt_queue_sp_work(bp);
7784         }
7785
7786         if (bnxt_tc_flower_enabled(bp)) {
7787                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7788                 bnxt_queue_sp_work(bp);
7789         }
7790
7791         if (bp->link_info.phy_retry) {
7792                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
7793                         bp->link_info.phy_retry = 0;
7794                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
7795                 } else {
7796                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
7797                         bnxt_queue_sp_work(bp);
7798                 }
7799         }
7800 bnxt_restart_timer:
7801         mod_timer(&bp->timer, jiffies + bp->current_interval);
7802 }
7803
7804 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7805 {
7806         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7807          * set.  If the device is being closed, bnxt_close() may be holding
7808          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
7809          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7810          */
7811         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7812         rtnl_lock();
7813 }
7814
7815 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7816 {
7817         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7818         rtnl_unlock();
7819 }
7820
7821 /* Only called from bnxt_sp_task() */
7822 static void bnxt_reset(struct bnxt *bp, bool silent)
7823 {
7824         bnxt_rtnl_lock_sp(bp);
7825         if (test_bit(BNXT_STATE_OPEN, &bp->state))
7826                 bnxt_reset_task(bp, silent);
7827         bnxt_rtnl_unlock_sp(bp);
7828 }
7829
7830 static void bnxt_cfg_ntp_filters(struct bnxt *);
7831
7832 static void bnxt_sp_task(struct work_struct *work)
7833 {
7834         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7835
7836         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7837         smp_mb__after_atomic();
7838         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7839                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7840                 return;
7841         }
7842
7843         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7844                 bnxt_cfg_rx_mode(bp);
7845
7846         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7847                 bnxt_cfg_ntp_filters(bp);
7848         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7849                 bnxt_hwrm_exec_fwd_req(bp);
7850         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7851                 bnxt_hwrm_tunnel_dst_port_alloc(
7852                         bp, bp->vxlan_port,
7853                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7854         }
7855         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7856                 bnxt_hwrm_tunnel_dst_port_free(
7857                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7858         }
7859         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7860                 bnxt_hwrm_tunnel_dst_port_alloc(
7861                         bp, bp->nge_port,
7862                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7863         }
7864         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7865                 bnxt_hwrm_tunnel_dst_port_free(
7866                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7867         }
7868         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
7869                 bnxt_hwrm_port_qstats(bp);
7870                 bnxt_hwrm_port_qstats_ext(bp);
7871         }
7872
7873         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7874                 int rc;
7875
7876                 mutex_lock(&bp->link_lock);
7877                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7878                                        &bp->sp_event))
7879                         bnxt_hwrm_phy_qcaps(bp);
7880
7881                 rc = bnxt_update_link(bp, true);
7882                 mutex_unlock(&bp->link_lock);
7883                 if (rc)
7884                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7885                                    rc);
7886         }
7887         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
7888                 int rc;
7889
7890                 mutex_lock(&bp->link_lock);
7891                 rc = bnxt_update_phy_setting(bp);
7892                 mutex_unlock(&bp->link_lock);
7893                 if (rc) {
7894                         netdev_warn(bp->dev, "update phy settings retry failed\n");
7895                 } else {
7896                         bp->link_info.phy_retry = false;
7897                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
7898                 }
7899         }
7900         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7901                 mutex_lock(&bp->link_lock);
7902                 bnxt_get_port_module_status(bp);
7903                 mutex_unlock(&bp->link_lock);
7904         }
7905
7906         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7907                 bnxt_tc_flow_stats_work(bp);
7908
7909         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
7910          * must be the last functions to be called before exiting.
7911          */
7912         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7913                 bnxt_reset(bp, false);
7914
7915         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7916                 bnxt_reset(bp, true);
7917
7918         smp_mb__before_atomic();
7919         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7920 }
7921
7922 /* Under rtnl_lock */
7923 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7924                      int tx_xdp)
7925 {
7926         int max_rx, max_tx, tx_sets = 1;
7927         int tx_rings_needed;
7928         int rx_rings = rx;
7929         int cp, vnics, rc;
7930
7931         if (tcs)
7932                 tx_sets = tcs;
7933
7934         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7935         if (rc)
7936                 return rc;
7937
7938         if (max_rx < rx)
7939                 return -ENOMEM;
7940
7941         tx_rings_needed = tx * tx_sets + tx_xdp;
7942         if (max_tx < tx_rings_needed)
7943                 return -ENOMEM;
7944
7945         vnics = 1;
7946         if (bp->flags & BNXT_FLAG_RFS)
7947                 vnics += rx_rings;
7948
7949         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7950                 rx_rings <<= 1;
7951         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7952         if (BNXT_NEW_RM(bp))
7953                 cp += bnxt_get_ulp_msix_num(bp);
7954         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7955                                      vnics);
7956 }
7957
7958 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7959 {
7960         if (bp->bar2) {
7961                 pci_iounmap(pdev, bp->bar2);
7962                 bp->bar2 = NULL;
7963         }
7964
7965         if (bp->bar1) {
7966                 pci_iounmap(pdev, bp->bar1);
7967                 bp->bar1 = NULL;
7968         }
7969
7970         if (bp->bar0) {
7971                 pci_iounmap(pdev, bp->bar0);
7972                 bp->bar0 = NULL;
7973         }
7974 }
7975
7976 static void bnxt_cleanup_pci(struct bnxt *bp)
7977 {
7978         bnxt_unmap_bars(bp, bp->pdev);
7979         pci_release_regions(bp->pdev);
7980         pci_disable_device(bp->pdev);
7981 }
7982
7983 static void bnxt_init_dflt_coal(struct bnxt *bp)
7984 {
7985         struct bnxt_coal *coal;
7986
7987         /* Tick values in micro seconds.
7988          * 1 coal_buf x bufs_per_record = 1 completion record.
7989          */
7990         coal = &bp->rx_coal;
7991         coal->coal_ticks = 14;
7992         coal->coal_bufs = 30;
7993         coal->coal_ticks_irq = 1;
7994         coal->coal_bufs_irq = 2;
7995         coal->idle_thresh = 50;
7996         coal->bufs_per_record = 2;
7997         coal->budget = 64;              /* NAPI budget */
7998
7999         coal = &bp->tx_coal;
8000         coal->coal_ticks = 28;
8001         coal->coal_bufs = 30;
8002         coal->coal_ticks_irq = 2;
8003         coal->coal_bufs_irq = 2;
8004         coal->bufs_per_record = 1;
8005
8006         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
8007 }
8008
8009 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
8010 {
8011         int rc;
8012         struct bnxt *bp = netdev_priv(dev);
8013
8014         SET_NETDEV_DEV(dev, &pdev->dev);
8015
8016         /* enable device (incl. PCI PM wakeup), and bus-mastering */
8017         rc = pci_enable_device(pdev);
8018         if (rc) {
8019                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
8020                 goto init_err;
8021         }
8022
8023         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8024                 dev_err(&pdev->dev,
8025                         "Cannot find PCI device base address, aborting\n");
8026                 rc = -ENODEV;
8027                 goto init_err_disable;
8028         }
8029
8030         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8031         if (rc) {
8032                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
8033                 goto init_err_disable;
8034         }
8035
8036         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
8037             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
8038                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8039                 rc = -EIO;
8040                 goto init_err_release;
8041         }
8042
8043         pci_set_master(pdev);
8044
8045         bp->dev = dev;
8046         bp->pdev = pdev;
8047
8048         bp->bar0 = pci_ioremap_bar(pdev, 0);
8049         if (!bp->bar0) {
8050                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
8051                 rc = -ENOMEM;
8052                 goto init_err_release;
8053         }
8054
8055         bp->bar1 = pci_ioremap_bar(pdev, 2);
8056         if (!bp->bar1) {
8057                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
8058                 rc = -ENOMEM;
8059                 goto init_err_release;
8060         }
8061
8062         bp->bar2 = pci_ioremap_bar(pdev, 4);
8063         if (!bp->bar2) {
8064                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
8065                 rc = -ENOMEM;
8066                 goto init_err_release;
8067         }
8068
8069         pci_enable_pcie_error_reporting(pdev);
8070
8071         INIT_WORK(&bp->sp_task, bnxt_sp_task);
8072
8073         spin_lock_init(&bp->ntp_fltr_lock);
8074
8075         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
8076         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
8077
8078         bnxt_init_dflt_coal(bp);
8079
8080         timer_setup(&bp->timer, bnxt_timer, 0);
8081         bp->current_interval = BNXT_TIMER_INTERVAL;
8082
8083         clear_bit(BNXT_STATE_OPEN, &bp->state);
8084         return 0;
8085
8086 init_err_release:
8087         bnxt_unmap_bars(bp, pdev);
8088         pci_release_regions(pdev);
8089
8090 init_err_disable:
8091         pci_disable_device(pdev);
8092
8093 init_err:
8094         return rc;
8095 }
8096
8097 /* rtnl_lock held */
8098 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
8099 {
8100         struct sockaddr *addr = p;
8101         struct bnxt *bp = netdev_priv(dev);
8102         int rc = 0;
8103
8104         if (!is_valid_ether_addr(addr->sa_data))
8105                 return -EADDRNOTAVAIL;
8106
8107         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
8108                 return 0;
8109
8110         rc = bnxt_approve_mac(bp, addr->sa_data, true);
8111         if (rc)
8112                 return rc;
8113
8114         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8115         if (netif_running(dev)) {
8116                 bnxt_close_nic(bp, false, false);
8117                 rc = bnxt_open_nic(bp, false, false);
8118         }
8119
8120         return rc;
8121 }
8122
8123 /* rtnl_lock held */
8124 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
8125 {
8126         struct bnxt *bp = netdev_priv(dev);
8127
8128         if (netif_running(dev))
8129                 bnxt_close_nic(bp, true, false);
8130
8131         dev->mtu = new_mtu;
8132         bnxt_set_ring_params(bp);
8133
8134         if (netif_running(dev))
8135                 return bnxt_open_nic(bp, true, false);
8136
8137         return 0;
8138 }
8139
8140 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
8141 {
8142         struct bnxt *bp = netdev_priv(dev);
8143         bool sh = false;
8144         int rc;
8145
8146         if (tc > bp->max_tc) {
8147                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
8148                            tc, bp->max_tc);
8149                 return -EINVAL;
8150         }
8151
8152         if (netdev_get_num_tc(dev) == tc)
8153                 return 0;
8154
8155         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8156                 sh = true;
8157
8158         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
8159                               sh, tc, bp->tx_nr_rings_xdp);
8160         if (rc)
8161                 return rc;
8162
8163         /* Needs to close the device and do hw resource re-allocations */
8164         if (netif_running(bp->dev))
8165                 bnxt_close_nic(bp, true, false);
8166
8167         if (tc) {
8168                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
8169                 netdev_set_num_tc(dev, tc);
8170         } else {
8171                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8172                 netdev_reset_tc(dev);
8173         }
8174         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
8175         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8176                                bp->tx_nr_rings + bp->rx_nr_rings;
8177         bp->num_stat_ctxs = bp->cp_nr_rings;
8178
8179         if (netif_running(bp->dev))
8180                 return bnxt_open_nic(bp, true, false);
8181
8182         return 0;
8183 }
8184
8185 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
8186                                   void *cb_priv)
8187 {
8188         struct bnxt *bp = cb_priv;
8189
8190         if (!bnxt_tc_flower_enabled(bp) ||
8191             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
8192                 return -EOPNOTSUPP;
8193
8194         switch (type) {
8195         case TC_SETUP_CLSFLOWER:
8196                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
8197         default:
8198                 return -EOPNOTSUPP;
8199         }
8200 }
8201
8202 static int bnxt_setup_tc_block(struct net_device *dev,
8203                                struct tc_block_offload *f)
8204 {
8205         struct bnxt *bp = netdev_priv(dev);
8206
8207         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
8208                 return -EOPNOTSUPP;
8209
8210         switch (f->command) {
8211         case TC_BLOCK_BIND:
8212                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
8213                                              bp, bp, f->extack);
8214         case TC_BLOCK_UNBIND:
8215                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
8216                 return 0;
8217         default:
8218                 return -EOPNOTSUPP;
8219         }
8220 }
8221
8222 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
8223                          void *type_data)
8224 {
8225         switch (type) {
8226         case TC_SETUP_BLOCK:
8227                 return bnxt_setup_tc_block(dev, type_data);
8228         case TC_SETUP_QDISC_MQPRIO: {
8229                 struct tc_mqprio_qopt *mqprio = type_data;
8230
8231                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
8232
8233                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
8234         }
8235         default:
8236                 return -EOPNOTSUPP;
8237         }
8238 }
8239
8240 #ifdef CONFIG_RFS_ACCEL
8241 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
8242                             struct bnxt_ntuple_filter *f2)
8243 {
8244         struct flow_keys *keys1 = &f1->fkeys;
8245         struct flow_keys *keys2 = &f2->fkeys;
8246
8247         if (keys1->basic.n_proto != keys2->basic.n_proto ||
8248             keys1->basic.ip_proto != keys2->basic.ip_proto)
8249                 return false;
8250
8251         if (keys1->basic.n_proto == htons(ETH_P_IP)) {
8252                 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
8253                     keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
8254                         return false;
8255         } else {
8256                 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
8257                            sizeof(keys1->addrs.v6addrs.src)) ||
8258                     memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
8259                            sizeof(keys1->addrs.v6addrs.dst)))
8260                         return false;
8261         }
8262
8263         if (keys1->ports.ports == keys2->ports.ports &&
8264             keys1->control.flags == keys2->control.flags &&
8265             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
8266             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
8267                 return true;
8268
8269         return false;
8270 }
8271
8272 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
8273                               u16 rxq_index, u32 flow_id)
8274 {
8275         struct bnxt *bp = netdev_priv(dev);
8276         struct bnxt_ntuple_filter *fltr, *new_fltr;
8277         struct flow_keys *fkeys;
8278         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
8279         int rc = 0, idx, bit_id, l2_idx = 0;
8280         struct hlist_head *head;
8281
8282         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8283                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8284                 int off = 0, j;
8285
8286                 netif_addr_lock_bh(dev);
8287                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
8288                         if (ether_addr_equal(eth->h_dest,
8289                                              vnic->uc_list + off)) {
8290                                 l2_idx = j + 1;
8291                                 break;
8292                         }
8293                 }
8294                 netif_addr_unlock_bh(dev);
8295                 if (!l2_idx)
8296                         return -EINVAL;
8297         }
8298         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
8299         if (!new_fltr)
8300                 return -ENOMEM;
8301
8302         fkeys = &new_fltr->fkeys;
8303         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
8304                 rc = -EPROTONOSUPPORT;
8305                 goto err_free;
8306         }
8307
8308         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
8309              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
8310             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
8311              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
8312                 rc = -EPROTONOSUPPORT;
8313                 goto err_free;
8314         }
8315         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
8316             bp->hwrm_spec_code < 0x10601) {
8317                 rc = -EPROTONOSUPPORT;
8318                 goto err_free;
8319         }
8320         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8321             bp->hwrm_spec_code < 0x10601) {
8322                 rc = -EPROTONOSUPPORT;
8323                 goto err_free;
8324         }
8325
8326         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
8327         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
8328
8329         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
8330         head = &bp->ntp_fltr_hash_tbl[idx];
8331         rcu_read_lock();
8332         hlist_for_each_entry_rcu(fltr, head, hash) {
8333                 if (bnxt_fltr_match(fltr, new_fltr)) {
8334                         rc = fltr->sw_id;
8335                         rcu_read_unlock();
8336                         goto err_free;
8337                 }
8338         }
8339         rcu_read_unlock();
8340
8341         spin_lock_bh(&bp->ntp_fltr_lock);
8342         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
8343                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
8344         if (bit_id < 0) {
8345                 spin_unlock_bh(&bp->ntp_fltr_lock);
8346                 rc = -ENOMEM;
8347                 goto err_free;
8348         }
8349
8350         new_fltr->sw_id = (u16)bit_id;
8351         new_fltr->flow_id = flow_id;
8352         new_fltr->l2_fltr_idx = l2_idx;
8353         new_fltr->rxq = rxq_index;
8354         hlist_add_head_rcu(&new_fltr->hash, head);
8355         bp->ntp_fltr_count++;
8356         spin_unlock_bh(&bp->ntp_fltr_lock);
8357
8358         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
8359         bnxt_queue_sp_work(bp);
8360
8361         return new_fltr->sw_id;
8362
8363 err_free:
8364         kfree(new_fltr);
8365         return rc;
8366 }
8367
8368 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8369 {
8370         int i;
8371
8372         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
8373                 struct hlist_head *head;
8374                 struct hlist_node *tmp;
8375                 struct bnxt_ntuple_filter *fltr;
8376                 int rc;
8377
8378                 head = &bp->ntp_fltr_hash_tbl[i];
8379                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
8380                         bool del = false;
8381
8382                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
8383                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
8384                                                         fltr->flow_id,
8385                                                         fltr->sw_id)) {
8386                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
8387                                                                          fltr);
8388                                         del = true;
8389                                 }
8390                         } else {
8391                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
8392                                                                        fltr);
8393                                 if (rc)
8394                                         del = true;
8395                                 else
8396                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
8397                         }
8398
8399                         if (del) {
8400                                 spin_lock_bh(&bp->ntp_fltr_lock);
8401                                 hlist_del_rcu(&fltr->hash);
8402                                 bp->ntp_fltr_count--;
8403                                 spin_unlock_bh(&bp->ntp_fltr_lock);
8404                                 synchronize_rcu();
8405                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
8406                                 kfree(fltr);
8407                         }
8408                 }
8409         }
8410         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8411                 netdev_info(bp->dev, "Receive PF driver unload event!");
8412 }
8413
8414 #else
8415
8416 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8417 {
8418 }
8419
8420 #endif /* CONFIG_RFS_ACCEL */
8421
8422 static void bnxt_udp_tunnel_add(struct net_device *dev,
8423                                 struct udp_tunnel_info *ti)
8424 {
8425         struct bnxt *bp = netdev_priv(dev);
8426
8427         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8428                 return;
8429
8430         if (!netif_running(dev))
8431                 return;
8432
8433         switch (ti->type) {
8434         case UDP_TUNNEL_TYPE_VXLAN:
8435                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8436                         return;
8437
8438                 bp->vxlan_port_cnt++;
8439                 if (bp->vxlan_port_cnt == 1) {
8440                         bp->vxlan_port = ti->port;
8441                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8442                         bnxt_queue_sp_work(bp);
8443                 }
8444                 break;
8445         case UDP_TUNNEL_TYPE_GENEVE:
8446                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8447                         return;
8448
8449                 bp->nge_port_cnt++;
8450                 if (bp->nge_port_cnt == 1) {
8451                         bp->nge_port = ti->port;
8452                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8453                 }
8454                 break;
8455         default:
8456                 return;
8457         }
8458
8459         bnxt_queue_sp_work(bp);
8460 }
8461
8462 static void bnxt_udp_tunnel_del(struct net_device *dev,
8463                                 struct udp_tunnel_info *ti)
8464 {
8465         struct bnxt *bp = netdev_priv(dev);
8466
8467         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8468                 return;
8469
8470         if (!netif_running(dev))
8471                 return;
8472
8473         switch (ti->type) {
8474         case UDP_TUNNEL_TYPE_VXLAN:
8475                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8476                         return;
8477                 bp->vxlan_port_cnt--;
8478
8479                 if (bp->vxlan_port_cnt != 0)
8480                         return;
8481
8482                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8483                 break;
8484         case UDP_TUNNEL_TYPE_GENEVE:
8485                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8486                         return;
8487                 bp->nge_port_cnt--;
8488
8489                 if (bp->nge_port_cnt != 0)
8490                         return;
8491
8492                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8493                 break;
8494         default:
8495                 return;
8496         }
8497
8498         bnxt_queue_sp_work(bp);
8499 }
8500
8501 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8502                                struct net_device *dev, u32 filter_mask,
8503                                int nlflags)
8504 {
8505         struct bnxt *bp = netdev_priv(dev);
8506
8507         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8508                                        nlflags, filter_mask, NULL);
8509 }
8510
8511 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8512                                u16 flags)
8513 {
8514         struct bnxt *bp = netdev_priv(dev);
8515         struct nlattr *attr, *br_spec;
8516         int rem, rc = 0;
8517
8518         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8519                 return -EOPNOTSUPP;
8520
8521         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8522         if (!br_spec)
8523                 return -EINVAL;
8524
8525         nla_for_each_nested(attr, br_spec, rem) {
8526                 u16 mode;
8527
8528                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8529                         continue;
8530
8531                 if (nla_len(attr) < sizeof(mode))
8532                         return -EINVAL;
8533
8534                 mode = nla_get_u16(attr);
8535                 if (mode == bp->br_mode)
8536                         break;
8537
8538                 rc = bnxt_hwrm_set_br_mode(bp, mode);
8539                 if (!rc)
8540                         bp->br_mode = mode;
8541                 break;
8542         }
8543         return rc;
8544 }
8545
8546 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8547                                    size_t len)
8548 {
8549         struct bnxt *bp = netdev_priv(dev);
8550         int rc;
8551
8552         /* The PF and it's VF-reps only support the switchdev framework */
8553         if (!BNXT_PF(bp))
8554                 return -EOPNOTSUPP;
8555
8556         rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8557
8558         if (rc >= len)
8559                 return -EOPNOTSUPP;
8560         return 0;
8561 }
8562
8563 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8564 {
8565         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8566                 return -EOPNOTSUPP;
8567
8568         /* The PF and it's VF-reps only support the switchdev framework */
8569         if (!BNXT_PF(bp))
8570                 return -EOPNOTSUPP;
8571
8572         switch (attr->id) {
8573         case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8574                 attr->u.ppid.id_len = sizeof(bp->switch_id);
8575                 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8576                 break;
8577         default:
8578                 return -EOPNOTSUPP;
8579         }
8580         return 0;
8581 }
8582
8583 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8584                                     struct switchdev_attr *attr)
8585 {
8586         return bnxt_port_attr_get(netdev_priv(dev), attr);
8587 }
8588
8589 static const struct switchdev_ops bnxt_switchdev_ops = {
8590         .switchdev_port_attr_get        = bnxt_swdev_port_attr_get
8591 };
8592
8593 static const struct net_device_ops bnxt_netdev_ops = {
8594         .ndo_open               = bnxt_open,
8595         .ndo_start_xmit         = bnxt_start_xmit,
8596         .ndo_stop               = bnxt_close,
8597         .ndo_get_stats64        = bnxt_get_stats64,
8598         .ndo_set_rx_mode        = bnxt_set_rx_mode,
8599         .ndo_do_ioctl           = bnxt_ioctl,
8600         .ndo_validate_addr      = eth_validate_addr,
8601         .ndo_set_mac_address    = bnxt_change_mac_addr,
8602         .ndo_change_mtu         = bnxt_change_mtu,
8603         .ndo_fix_features       = bnxt_fix_features,
8604         .ndo_set_features       = bnxt_set_features,
8605         .ndo_tx_timeout         = bnxt_tx_timeout,
8606 #ifdef CONFIG_BNXT_SRIOV
8607         .ndo_get_vf_config      = bnxt_get_vf_config,
8608         .ndo_set_vf_mac         = bnxt_set_vf_mac,
8609         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
8610         .ndo_set_vf_rate        = bnxt_set_vf_bw,
8611         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
8612         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
8613         .ndo_set_vf_trust       = bnxt_set_vf_trust,
8614 #endif
8615         .ndo_setup_tc           = bnxt_setup_tc,
8616 #ifdef CONFIG_RFS_ACCEL
8617         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
8618 #endif
8619         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
8620         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
8621         .ndo_bpf                = bnxt_xdp,
8622         .ndo_bridge_getlink     = bnxt_bridge_getlink,
8623         .ndo_bridge_setlink     = bnxt_bridge_setlink,
8624         .ndo_get_phys_port_name = bnxt_get_phys_port_name
8625 };
8626
8627 static void bnxt_remove_one(struct pci_dev *pdev)
8628 {
8629         struct net_device *dev = pci_get_drvdata(pdev);
8630         struct bnxt *bp = netdev_priv(dev);
8631
8632         if (BNXT_PF(bp)) {
8633                 bnxt_sriov_disable(bp);
8634                 bnxt_dl_unregister(bp);
8635         }
8636
8637         pci_disable_pcie_error_reporting(pdev);
8638         unregister_netdev(dev);
8639         bnxt_shutdown_tc(bp);
8640         bnxt_cancel_sp_work(bp);
8641         bp->sp_event = 0;
8642
8643         bnxt_clear_int_mode(bp);
8644         bnxt_hwrm_func_drv_unrgtr(bp);
8645         bnxt_free_hwrm_resources(bp);
8646         bnxt_free_hwrm_short_cmd_req(bp);
8647         bnxt_ethtool_free(bp);
8648         bnxt_dcb_free(bp);
8649         kfree(bp->edev);
8650         bp->edev = NULL;
8651         bnxt_cleanup_pci(bp);
8652         free_netdev(dev);
8653 }
8654
8655 static int bnxt_probe_phy(struct bnxt *bp)
8656 {
8657         int rc = 0;
8658         struct bnxt_link_info *link_info = &bp->link_info;
8659
8660         rc = bnxt_hwrm_phy_qcaps(bp);
8661         if (rc) {
8662                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8663                            rc);
8664                 return rc;
8665         }
8666         mutex_init(&bp->link_lock);
8667
8668         rc = bnxt_update_link(bp, false);
8669         if (rc) {
8670                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8671                            rc);
8672                 return rc;
8673         }
8674
8675         /* Older firmware does not have supported_auto_speeds, so assume
8676          * that all supported speeds can be autonegotiated.
8677          */
8678         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8679                 link_info->support_auto_speeds = link_info->support_speeds;
8680
8681         /*initialize the ethool setting copy with NVM settings */
8682         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8683                 link_info->autoneg = BNXT_AUTONEG_SPEED;
8684                 if (bp->hwrm_spec_code >= 0x10201) {
8685                         if (link_info->auto_pause_setting &
8686                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8687                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8688                 } else {
8689                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8690                 }
8691                 link_info->advertising = link_info->auto_link_speeds;
8692         } else {
8693                 link_info->req_link_speed = link_info->force_link_speed;
8694                 link_info->req_duplex = link_info->duplex_setting;
8695         }
8696         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8697                 link_info->req_flow_ctrl =
8698                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8699         else
8700                 link_info->req_flow_ctrl = link_info->force_pause_setting;
8701         return rc;
8702 }
8703
8704 static int bnxt_get_max_irq(struct pci_dev *pdev)
8705 {
8706         u16 ctrl;
8707
8708         if (!pdev->msix_cap)
8709                 return 1;
8710
8711         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8712         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8713 }
8714
8715 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8716                                 int *max_cp)
8717 {
8718         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8719         int max_ring_grps = 0;
8720
8721         *max_tx = hw_resc->max_tx_rings;
8722         *max_rx = hw_resc->max_rx_rings;
8723         *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp),
8724                         hw_resc->max_irqs - bnxt_get_ulp_msix_num(bp));
8725         *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8726         max_ring_grps = hw_resc->max_hw_ring_grps;
8727         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8728                 *max_cp -= 1;
8729                 *max_rx -= 2;
8730         }
8731         if (bp->flags & BNXT_FLAG_AGG_RINGS)
8732                 *max_rx >>= 1;
8733         *max_rx = min_t(int, *max_rx, max_ring_grps);
8734 }
8735
8736 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8737 {
8738         int rx, tx, cp;
8739
8740         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8741         *max_rx = rx;
8742         *max_tx = tx;
8743         if (!rx || !tx || !cp)
8744                 return -ENOMEM;
8745
8746         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8747 }
8748
8749 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8750                                bool shared)
8751 {
8752         int rc;
8753
8754         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8755         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8756                 /* Not enough rings, try disabling agg rings. */
8757                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8758                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8759                 if (rc) {
8760                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
8761                         bp->flags |= BNXT_FLAG_AGG_RINGS;
8762                         return rc;
8763                 }
8764                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8765                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8766                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8767                 bnxt_set_ring_params(bp);
8768         }
8769
8770         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8771                 int max_cp, max_stat, max_irq;
8772
8773                 /* Reserve minimum resources for RoCE */
8774                 max_cp = bnxt_get_max_func_cp_rings(bp);
8775                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8776                 max_irq = bnxt_get_max_func_irqs(bp);
8777                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8778                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8779                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8780                         return 0;
8781
8782                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8783                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8784                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8785                 max_cp = min_t(int, max_cp, max_irq);
8786                 max_cp = min_t(int, max_cp, max_stat);
8787                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8788                 if (rc)
8789                         rc = 0;
8790         }
8791         return rc;
8792 }
8793
8794 /* In initial default shared ring setting, each shared ring must have a
8795  * RX/TX ring pair.
8796  */
8797 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8798 {
8799         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8800         bp->rx_nr_rings = bp->cp_nr_rings;
8801         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8802         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8803 }
8804
8805 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8806 {
8807         int dflt_rings, max_rx_rings, max_tx_rings, rc;
8808
8809         if (!bnxt_can_reserve_rings(bp))
8810                 return 0;
8811
8812         if (sh)
8813                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8814         dflt_rings = netif_get_num_default_rss_queues();
8815         /* Reduce default rings on multi-port cards so that total default
8816          * rings do not exceed CPU count.
8817          */
8818         if (bp->port_count > 1) {
8819                 int max_rings =
8820                         max_t(int, num_online_cpus() / bp->port_count, 1);
8821
8822                 dflt_rings = min_t(int, dflt_rings, max_rings);
8823         }
8824         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8825         if (rc)
8826                 return rc;
8827         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8828         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8829         if (sh)
8830                 bnxt_trim_dflt_sh_rings(bp);
8831         else
8832                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8833         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8834
8835         rc = __bnxt_reserve_rings(bp);
8836         if (rc)
8837                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8838         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8839         if (sh)
8840                 bnxt_trim_dflt_sh_rings(bp);
8841
8842         /* Rings may have been trimmed, re-reserve the trimmed rings. */
8843         if (bnxt_need_reserve_rings(bp)) {
8844                 rc = __bnxt_reserve_rings(bp);
8845                 if (rc)
8846                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8847                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8848         }
8849         bp->num_stat_ctxs = bp->cp_nr_rings;
8850         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8851                 bp->rx_nr_rings++;
8852                 bp->cp_nr_rings++;
8853         }
8854         if (rc) {
8855                 bp->tx_nr_rings = 0;
8856                 bp->rx_nr_rings = 0;
8857         }
8858         return rc;
8859 }
8860
8861 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
8862 {
8863         int rc;
8864
8865         if (bp->tx_nr_rings)
8866                 return 0;
8867
8868         bnxt_ulp_irq_stop(bp);
8869         bnxt_clear_int_mode(bp);
8870         rc = bnxt_set_dflt_rings(bp, true);
8871         if (rc) {
8872                 netdev_err(bp->dev, "Not enough rings available.\n");
8873                 goto init_dflt_ring_err;
8874         }
8875         rc = bnxt_init_int_mode(bp);
8876         if (rc)
8877                 goto init_dflt_ring_err;
8878
8879         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8880         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
8881                 bp->flags |= BNXT_FLAG_RFS;
8882                 bp->dev->features |= NETIF_F_NTUPLE;
8883         }
8884 init_dflt_ring_err:
8885         bnxt_ulp_irq_restart(bp, rc);
8886         return rc;
8887 }
8888
8889 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
8890 {
8891         int rc;
8892
8893         ASSERT_RTNL();
8894         bnxt_hwrm_func_qcaps(bp);
8895
8896         if (netif_running(bp->dev))
8897                 __bnxt_close_nic(bp, true, false);
8898
8899         bnxt_ulp_irq_stop(bp);
8900         bnxt_clear_int_mode(bp);
8901         rc = bnxt_init_int_mode(bp);
8902         bnxt_ulp_irq_restart(bp, rc);
8903
8904         if (netif_running(bp->dev)) {
8905                 if (rc)
8906                         dev_close(bp->dev);
8907                 else
8908                         rc = bnxt_open_nic(bp, true, false);
8909         }
8910
8911         return rc;
8912 }
8913
8914 static int bnxt_init_mac_addr(struct bnxt *bp)
8915 {
8916         int rc = 0;
8917
8918         if (BNXT_PF(bp)) {
8919                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8920         } else {
8921 #ifdef CONFIG_BNXT_SRIOV
8922                 struct bnxt_vf_info *vf = &bp->vf;
8923                 bool strict_approval = true;
8924
8925                 if (is_valid_ether_addr(vf->mac_addr)) {
8926                         /* overwrite netdev dev_addr with admin VF MAC */
8927                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8928                         /* Older PF driver or firmware may not approve this
8929                          * correctly.
8930                          */
8931                         strict_approval = false;
8932                 } else {
8933                         eth_hw_addr_random(bp->dev);
8934                 }
8935                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
8936 #endif
8937         }
8938         return rc;
8939 }
8940
8941 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8942 {
8943         static int version_printed;
8944         struct net_device *dev;
8945         struct bnxt *bp;
8946         int rc, max_irqs;
8947
8948         if (pci_is_bridge(pdev))
8949                 return -ENODEV;
8950
8951         if (version_printed++ == 0)
8952                 pr_info("%s", version);
8953
8954         max_irqs = bnxt_get_max_irq(pdev);
8955         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8956         if (!dev)
8957                 return -ENOMEM;
8958
8959         bp = netdev_priv(dev);
8960
8961         if (bnxt_vf_pciid(ent->driver_data))
8962                 bp->flags |= BNXT_FLAG_VF;
8963
8964         if (pdev->msix_cap)
8965                 bp->flags |= BNXT_FLAG_MSIX_CAP;
8966
8967         rc = bnxt_init_board(pdev, dev);
8968         if (rc < 0)
8969                 goto init_err_free;
8970
8971         dev->netdev_ops = &bnxt_netdev_ops;
8972         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8973         dev->ethtool_ops = &bnxt_ethtool_ops;
8974         SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8975         pci_set_drvdata(pdev, dev);
8976
8977         rc = bnxt_alloc_hwrm_resources(bp);
8978         if (rc)
8979                 goto init_err_pci_clean;
8980
8981         mutex_init(&bp->hwrm_cmd_lock);
8982         rc = bnxt_hwrm_ver_get(bp);
8983         if (rc)
8984                 goto init_err_pci_clean;
8985
8986         if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
8987                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8988                 if (rc)
8989                         goto init_err_pci_clean;
8990         }
8991
8992         rc = bnxt_hwrm_func_reset(bp);
8993         if (rc)
8994                 goto init_err_pci_clean;
8995
8996         bnxt_hwrm_fw_set_time(bp);
8997
8998         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8999                            NETIF_F_TSO | NETIF_F_TSO6 |
9000                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
9001                            NETIF_F_GSO_IPXIP4 |
9002                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
9003                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
9004                            NETIF_F_RXCSUM | NETIF_F_GRO;
9005
9006         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
9007                 dev->hw_features |= NETIF_F_LRO;
9008
9009         dev->hw_enc_features =
9010                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
9011                         NETIF_F_TSO | NETIF_F_TSO6 |
9012                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
9013                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
9014                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
9015         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
9016                                     NETIF_F_GSO_GRE_CSUM;
9017         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
9018         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
9019                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
9020         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
9021                 dev->hw_features |= NETIF_F_GRO_HW;
9022         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
9023         if (dev->features & NETIF_F_GRO_HW)
9024                 dev->features &= ~NETIF_F_LRO;
9025         dev->priv_flags |= IFF_UNICAST_FLT;
9026
9027 #ifdef CONFIG_BNXT_SRIOV
9028         init_waitqueue_head(&bp->sriov_cfg_wait);
9029         mutex_init(&bp->sriov_lock);
9030 #endif
9031         bp->gro_func = bnxt_gro_func_5730x;
9032         if (BNXT_CHIP_P4_PLUS(bp))
9033                 bp->gro_func = bnxt_gro_func_5731x;
9034         else
9035                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
9036
9037         rc = bnxt_hwrm_func_drv_rgtr(bp);
9038         if (rc)
9039                 goto init_err_pci_clean;
9040
9041         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
9042         if (rc)
9043                 goto init_err_pci_clean;
9044
9045         bp->ulp_probe = bnxt_ulp_probe;
9046
9047         /* Get the MAX capabilities for this function */
9048         rc = bnxt_hwrm_func_qcaps(bp);
9049         if (rc) {
9050                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
9051                            rc);
9052                 rc = -1;
9053                 goto init_err_pci_clean;
9054         }
9055         rc = bnxt_init_mac_addr(bp);
9056         if (rc) {
9057                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
9058                 rc = -EADDRNOTAVAIL;
9059                 goto init_err_pci_clean;
9060         }
9061         rc = bnxt_hwrm_queue_qportcfg(bp);
9062         if (rc) {
9063                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
9064                            rc);
9065                 rc = -1;
9066                 goto init_err_pci_clean;
9067         }
9068
9069         bnxt_hwrm_func_qcfg(bp);
9070         bnxt_hwrm_port_led_qcaps(bp);
9071         bnxt_ethtool_init(bp);
9072         bnxt_dcb_init(bp);
9073
9074         /* MTU range: 60 - FW defined max */
9075         dev->min_mtu = ETH_ZLEN;
9076         dev->max_mtu = bp->max_mtu;
9077
9078         rc = bnxt_probe_phy(bp);
9079         if (rc)
9080                 goto init_err_pci_clean;
9081
9082         bnxt_set_rx_skb_mode(bp, false);
9083         bnxt_set_tpa_flags(bp);
9084         bnxt_set_ring_params(bp);
9085         bnxt_set_max_func_irqs(bp, max_irqs);
9086         rc = bnxt_set_dflt_rings(bp, true);
9087         if (rc) {
9088                 netdev_err(bp->dev, "Not enough rings available.\n");
9089                 rc = -ENOMEM;
9090                 goto init_err_pci_clean;
9091         }
9092
9093         /* Default RSS hash cfg. */
9094         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
9095                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
9096                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
9097                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
9098         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
9099                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
9100                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
9101                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
9102         }
9103
9104         bnxt_hwrm_vnic_qcaps(bp);
9105         if (bnxt_rfs_supported(bp)) {
9106                 dev->hw_features |= NETIF_F_NTUPLE;
9107                 if (bnxt_rfs_capable(bp)) {
9108                         bp->flags |= BNXT_FLAG_RFS;
9109                         dev->features |= NETIF_F_NTUPLE;
9110                 }
9111         }
9112
9113         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
9114                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
9115
9116         rc = bnxt_init_int_mode(bp);
9117         if (rc)
9118                 goto init_err_pci_clean;
9119
9120         /* No TC has been set yet and rings may have been trimmed due to
9121          * limited MSIX, so we re-initialize the TX rings per TC.
9122          */
9123         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9124
9125         bnxt_get_wol_settings(bp);
9126         if (bp->flags & BNXT_FLAG_WOL_CAP)
9127                 device_set_wakeup_enable(&pdev->dev, bp->wol);
9128         else
9129                 device_set_wakeup_capable(&pdev->dev, false);
9130
9131         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
9132
9133         if (BNXT_PF(bp)) {
9134                 if (!bnxt_pf_wq) {
9135                         bnxt_pf_wq =
9136                                 create_singlethread_workqueue("bnxt_pf_wq");
9137                         if (!bnxt_pf_wq) {
9138                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
9139                                 rc = -ENOMEM;
9140                                 goto init_err_pci_clean;
9141                         }
9142                 }
9143                 bnxt_init_tc(bp);
9144         }
9145
9146         rc = register_netdev(dev);
9147         if (rc)
9148                 goto init_err_cleanup_tc;
9149
9150         if (BNXT_PF(bp))
9151                 bnxt_dl_register(bp);
9152
9153         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
9154                     board_info[ent->driver_data].name,
9155                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
9156         pcie_print_link_status(pdev);
9157
9158         pci_save_state(pdev);
9159         return 0;
9160
9161 init_err_cleanup_tc:
9162         bnxt_shutdown_tc(bp);
9163         bnxt_clear_int_mode(bp);
9164
9165 init_err_pci_clean:
9166         bnxt_free_hwrm_short_cmd_req(bp);
9167         bnxt_free_hwrm_resources(bp);
9168         bnxt_cleanup_pci(bp);
9169
9170 init_err_free:
9171         free_netdev(dev);
9172         return rc;
9173 }
9174
9175 static void bnxt_shutdown(struct pci_dev *pdev)
9176 {
9177         struct net_device *dev = pci_get_drvdata(pdev);
9178         struct bnxt *bp;
9179
9180         if (!dev)
9181                 return;
9182
9183         rtnl_lock();
9184         bp = netdev_priv(dev);
9185         if (!bp)
9186                 goto shutdown_exit;
9187
9188         if (netif_running(dev))
9189                 dev_close(dev);
9190
9191         bnxt_ulp_shutdown(bp);
9192
9193         if (system_state == SYSTEM_POWER_OFF) {
9194                 bnxt_clear_int_mode(bp);
9195                 pci_wake_from_d3(pdev, bp->wol);
9196                 pci_set_power_state(pdev, PCI_D3hot);
9197         }
9198
9199 shutdown_exit:
9200         rtnl_unlock();
9201 }
9202
9203 #ifdef CONFIG_PM_SLEEP
9204 static int bnxt_suspend(struct device *device)
9205 {
9206         struct pci_dev *pdev = to_pci_dev(device);
9207         struct net_device *dev = pci_get_drvdata(pdev);
9208         struct bnxt *bp = netdev_priv(dev);
9209         int rc = 0;
9210
9211         rtnl_lock();
9212         if (netif_running(dev)) {
9213                 netif_device_detach(dev);
9214                 rc = bnxt_close(dev);
9215         }
9216         bnxt_hwrm_func_drv_unrgtr(bp);
9217         rtnl_unlock();
9218         return rc;
9219 }
9220
9221 static int bnxt_resume(struct device *device)
9222 {
9223         struct pci_dev *pdev = to_pci_dev(device);
9224         struct net_device *dev = pci_get_drvdata(pdev);
9225         struct bnxt *bp = netdev_priv(dev);
9226         int rc = 0;
9227
9228         rtnl_lock();
9229         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
9230                 rc = -ENODEV;
9231                 goto resume_exit;
9232         }
9233         rc = bnxt_hwrm_func_reset(bp);
9234         if (rc) {
9235                 rc = -EBUSY;
9236                 goto resume_exit;
9237         }
9238         bnxt_get_wol_settings(bp);
9239         if (netif_running(dev)) {
9240                 rc = bnxt_open(dev);
9241                 if (!rc)
9242                         netif_device_attach(dev);
9243         }
9244
9245 resume_exit:
9246         rtnl_unlock();
9247         return rc;
9248 }
9249
9250 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
9251 #define BNXT_PM_OPS (&bnxt_pm_ops)
9252
9253 #else
9254
9255 #define BNXT_PM_OPS NULL
9256
9257 #endif /* CONFIG_PM_SLEEP */
9258
9259 /**
9260  * bnxt_io_error_detected - called when PCI error is detected
9261  * @pdev: Pointer to PCI device
9262  * @state: The current pci connection state
9263  *
9264  * This function is called after a PCI bus error affecting
9265  * this device has been detected.
9266  */
9267 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
9268                                                pci_channel_state_t state)
9269 {
9270         struct net_device *netdev = pci_get_drvdata(pdev);
9271         struct bnxt *bp = netdev_priv(netdev);
9272
9273         netdev_info(netdev, "PCI I/O error detected\n");
9274
9275         rtnl_lock();
9276         netif_device_detach(netdev);
9277
9278         bnxt_ulp_stop(bp);
9279
9280         if (state == pci_channel_io_perm_failure) {
9281                 rtnl_unlock();
9282                 return PCI_ERS_RESULT_DISCONNECT;
9283         }
9284
9285         if (netif_running(netdev))
9286                 bnxt_close(netdev);
9287
9288         pci_disable_device(pdev);
9289         rtnl_unlock();
9290
9291         /* Request a slot slot reset. */
9292         return PCI_ERS_RESULT_NEED_RESET;
9293 }
9294
9295 /**
9296  * bnxt_io_slot_reset - called after the pci bus has been reset.
9297  * @pdev: Pointer to PCI device
9298  *
9299  * Restart the card from scratch, as if from a cold-boot.
9300  * At this point, the card has exprienced a hard reset,
9301  * followed by fixups by BIOS, and has its config space
9302  * set up identically to what it was at cold boot.
9303  */
9304 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
9305 {
9306         struct net_device *netdev = pci_get_drvdata(pdev);
9307         struct bnxt *bp = netdev_priv(netdev);
9308         int err = 0;
9309         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
9310
9311         netdev_info(bp->dev, "PCI Slot Reset\n");
9312
9313         rtnl_lock();
9314
9315         if (pci_enable_device(pdev)) {
9316                 dev_err(&pdev->dev,
9317                         "Cannot re-enable PCI device after reset.\n");
9318         } else {
9319                 pci_set_master(pdev);
9320                 pci_restore_state(pdev);
9321                 pci_save_state(pdev);
9322
9323                 err = bnxt_hwrm_func_reset(bp);
9324                 if (!err && netif_running(netdev))
9325                         err = bnxt_open(netdev);
9326
9327                 if (!err) {
9328                         result = PCI_ERS_RESULT_RECOVERED;
9329                         bnxt_ulp_start(bp);
9330                 }
9331         }
9332
9333         if (result != PCI_ERS_RESULT_RECOVERED) {
9334                 if (netif_running(netdev))
9335                         dev_close(netdev);
9336                 pci_disable_device(pdev);
9337         }
9338
9339         rtnl_unlock();
9340
9341         err = pci_cleanup_aer_uncorrect_error_status(pdev);
9342         if (err) {
9343                 dev_err(&pdev->dev,
9344                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9345                          err); /* non-fatal, continue */
9346         }
9347
9348         return result;
9349 }
9350
9351 /**
9352  * bnxt_io_resume - called when traffic can start flowing again.
9353  * @pdev: Pointer to PCI device
9354  *
9355  * This callback is called when the error recovery driver tells
9356  * us that its OK to resume normal operation.
9357  */
9358 static void bnxt_io_resume(struct pci_dev *pdev)
9359 {
9360         struct net_device *netdev = pci_get_drvdata(pdev);
9361
9362         rtnl_lock();
9363
9364         netif_device_attach(netdev);
9365
9366         rtnl_unlock();
9367 }
9368
9369 static const struct pci_error_handlers bnxt_err_handler = {
9370         .error_detected = bnxt_io_error_detected,
9371         .slot_reset     = bnxt_io_slot_reset,
9372         .resume         = bnxt_io_resume
9373 };
9374
9375 static struct pci_driver bnxt_pci_driver = {
9376         .name           = DRV_MODULE_NAME,
9377         .id_table       = bnxt_pci_tbl,
9378         .probe          = bnxt_init_one,
9379         .remove         = bnxt_remove_one,
9380         .shutdown       = bnxt_shutdown,
9381         .driver.pm      = BNXT_PM_OPS,
9382         .err_handler    = &bnxt_err_handler,
9383 #if defined(CONFIG_BNXT_SRIOV)
9384         .sriov_configure = bnxt_sriov_configure,
9385 #endif
9386 };
9387
9388 static int __init bnxt_init(void)
9389 {
9390         int err;
9391
9392         bnxt_debug_init();
9393         err = pci_register_driver(&bnxt_pci_driver);
9394         if (err) {
9395                 bnxt_debug_exit();
9396                 return err;
9397         }
9398
9399         return 0;
9400 }
9401
9402 static void __exit bnxt_exit(void)
9403 {
9404         pci_unregister_driver(&bnxt_pci_driver);
9405         if (bnxt_pf_wq)
9406                 destroy_workqueue(bnxt_pf_wq);
9407         bnxt_debug_exit();
9408 }
9409
9410 module_init(bnxt_init);
9411 module_exit(bnxt_exit);