drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2017 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/if_bridge.h>
  37 #include <linux/rtc.h>
  38 #include <linux/bpf.h>
  39 #include <net/ip.h>
  40 #include <net/tcp.h>
  41 #include <net/udp.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <net/udp_tunnel.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/prefetch.h>
  47 #include <linux/cache.h>
  48 #include <linux/log2.h>
  49 #include <linux/aer.h>
  50 #include <linux/bitmap.h>
  51 #include <linux/cpu_rmap.h>
  52 #include <linux/cpumask.h>
  53 #include <net/pkt_cls.h>
  54
  55 #include "bnxt_hsi.h"
  56 #include "bnxt.h"
  57 #include "bnxt_ulp.h"
  58 #include "bnxt_sriov.h"
  59 #include "bnxt_ethtool.h"
  60 #include "bnxt_dcb.h"
  61 #include "bnxt_xdp.h"
  62 #include "bnxt_vfr.h"
  63 #include "bnxt_tc.h"
  64
  65 #define BNXT_TX_TIMEOUT         (5 * HZ)
  66
  67 static const char version[] =
  68         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  69
  70 MODULE_LICENSE("GPL");
  71 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  72 MODULE_VERSION(DRV_MODULE_VERSION);
  73
  74 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  75 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  76 #define BNXT_RX_COPY_THRESH 256
  77
  78 #define BNXT_TX_PUSH_THRESH 164
  79
  80 enum board_idx {
  81         BCM57301,
  82         BCM57302,
  83         BCM57304,
  84         BCM57417_NPAR,
  85         BCM58700,
  86         BCM57311,
  87         BCM57312,
  88         BCM57402,
  89         BCM57404,
  90         BCM57406,
  91         BCM57402_NPAR,
  92         BCM57407,
  93         BCM57412,
  94         BCM57414,
  95         BCM57416,
  96         BCM57417,
  97         BCM57412_NPAR,
  98         BCM57314,
  99         BCM57417_SFP,
 100         BCM57416_SFP,
 101         BCM57404_NPAR,
 102         BCM57406_NPAR,
 103         BCM57407_SFP,
 104         BCM57407_NPAR,
 105         BCM57414_NPAR,
 106         BCM57416_NPAR,
 107         BCM57452,
 108         BCM57454,
 109         BCM58802,
 110         BCM58808,
 111         NETXTREME_E_VF,
 112         NETXTREME_C_VF,
 113 };
 114
 115 /* indexed by enum above */
 116 static const struct {
 117         char *name;
 118 } board_info[] = {
 119         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 120         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 121         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 122         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 123         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 124         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 125         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 126         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 127         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 128         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 129         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 130         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 131         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 132         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 133         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 134         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 135         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 136         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 137         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 138         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 139         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 140         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 141         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 142         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 143         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 144         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 145         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 146         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 147         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 148         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 149         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 150         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 151 };
 152
 153 static const struct pci_device_id bnxt_pci_tbl[] = {
 154         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 155         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 156         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 157         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 158         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 159         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 160         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 161         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 162         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 163         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 164         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 165         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 166         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 168         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 169         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 170         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 171         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 172         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 174         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 175         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 176         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 177         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 178         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 179         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 180         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 181         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 183         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 184         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 185         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 186         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 187         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 188 #ifdef CONFIG_BNXT_SRIOV
 189         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 190         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 191         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 192         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 193         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 194         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 195         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 196         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 197 #endif
 198         { 0 }
 199 };
 200
 201 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 202
 203 static const u16 bnxt_vf_req_snif[] = {
 204         HWRM_FUNC_CFG,
 205         HWRM_PORT_PHY_QCFG,
 206         HWRM_CFA_L2_FILTER_ALLOC,
 207 };
 208
 209 static const u16 bnxt_async_events_arr[] = {
 210         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 211         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 212         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 213         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 214         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 215 };
 216
 217 static struct workqueue_struct *bnxt_pf_wq;
 218
 219 static bool bnxt_vf_pciid(enum board_idx idx)
 220 {
 221         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 222 }
 223
 224 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 225 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 226 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 227
 228 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 229                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 230
 231 #define BNXT_CP_DB(db, raw_cons)                                        \
 232                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 233
 234 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 235                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 236
 237 const u16 bnxt_lhint_arr[] = {
 238         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 239         TX_BD_FLAGS_LHINT_512_TO_1023,
 240         TX_BD_FLAGS_LHINT_1024_TO_2047,
 241         TX_BD_FLAGS_LHINT_1024_TO_2047,
 242         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 243         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 244         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 245         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 246         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 247         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 248         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 249         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 250         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 251         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 252         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 253         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 254         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 255         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 256         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 257 };
 258
 259 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 260 {
 261         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 262
 263         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 264                 return 0;
 265
 266         return md_dst->u.port_info.port_id;
 267 }
 268
 269 static bool bnxt_txr_netif_try_stop_queue(struct bnxt *bp,
 270                                           struct bnxt_tx_ring_info *txr,
 271                                           struct netdev_queue *txq)
 272 {
 273         netif_tx_stop_queue(txq);
 274
 275         /* netif_tx_stop_queue() must be done before checking
 276          * tx index in bnxt_tx_avail() below, because in
 277          * bnxt_tx_int(), we update tx index before checking for
 278          * netif_tx_queue_stopped().
 279          */
 280         smp_mb();
 281         if (bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh) {
 282                 netif_tx_wake_queue(txq);
 283                 return false;
 284         }
 285
 286         return true;
 287 }
 288
 289 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 290 {
 291         struct bnxt *bp = netdev_priv(dev);
 292         struct tx_bd *txbd;
 293         struct tx_bd_ext *txbd1;
 294         struct netdev_queue *txq;
 295         int i;
 296         dma_addr_t mapping;
 297         unsigned int length, pad = 0;
 298         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 299         u16 prod, last_frag;
 300         struct pci_dev *pdev = bp->pdev;
 301         struct bnxt_tx_ring_info *txr;
 302         struct bnxt_sw_tx_bd *tx_buf;
 303
 304         i = skb_get_queue_mapping(skb);
 305         if (unlikely(i >= bp->tx_nr_rings)) {
 306                 dev_kfree_skb_any(skb);
 307                 return NETDEV_TX_OK;
 308         }
 309
 310         txq = netdev_get_tx_queue(dev, i);
 311         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 312         prod = txr->tx_prod;
 313
 314         free_size = bnxt_tx_avail(bp, txr);
 315         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 316                 if (bnxt_txr_netif_try_stop_queue(bp, txr, txq))
 317                         return NETDEV_TX_BUSY;
 318         }
 319
 320         length = skb->len;
 321         len = skb_headlen(skb);
 322         last_frag = skb_shinfo(skb)->nr_frags;
 323
 324         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 325
 326         txbd->tx_bd_opaque = prod;
 327
 328         tx_buf = &txr->tx_buf_ring[prod];
 329         tx_buf->skb = skb;
 330         tx_buf->nr_frags = last_frag;
 331
 332         vlan_tag_flags = 0;
 333         cfa_action = bnxt_xmit_get_cfa_action(skb);
 334         if (skb_vlan_tag_present(skb)) {
 335                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 336                                  skb_vlan_tag_get(skb);
 337                 /* Currently supports 8021Q, 8021AD vlan offloads
 338                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 339                  */
 340                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 341                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 342         }
 343
 344         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 345                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 346                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 347                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 348                 void *pdata = tx_push_buf->data;
 349                 u64 *end;
 350                 int j, push_len;
 351
 352                 /* Set COAL_NOW to be ready quickly for the next push */
 353                 tx_push->tx_bd_len_flags_type =
 354                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 355                                         TX_BD_TYPE_LONG_TX_BD |
 356                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 357                                         TX_BD_FLAGS_COAL_NOW |
 358                                         TX_BD_FLAGS_PACKET_END |
 359                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 360
 361                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 362                         tx_push1->tx_bd_hsize_lflags =
 363                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 364                 else
 365                         tx_push1->tx_bd_hsize_lflags = 0;
 366
 367                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 368                 tx_push1->tx_bd_cfa_action =
 369                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 370
 371                 end = pdata + length;
 372                 end = PTR_ALIGN(end, 8) - 1;
 373                 *end = 0;
 374
 375                 skb_copy_from_linear_data(skb, pdata, len);
 376                 pdata += len;
 377                 for (j = 0; j < last_frag; j++) {
 378                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 379                         void *fptr;
 380
 381                         fptr = skb_frag_address_safe(frag);
 382                         if (!fptr)
 383                                 goto normal_tx;
 384
 385                         memcpy(pdata, fptr, skb_frag_size(frag));
 386                         pdata += skb_frag_size(frag);
 387                 }
 388
 389                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 390                 txbd->tx_bd_haddr = txr->data_mapping;
 391                 prod = NEXT_TX(prod);
 392                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 393                 memcpy(txbd, tx_push1, sizeof(*txbd));
 394                 prod = NEXT_TX(prod);
 395                 tx_push->doorbell =
 396                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 397                 txr->tx_prod = prod;
 398
 399                 tx_buf->is_push = 1;
 400                 netdev_tx_sent_queue(txq, skb->len);
 401                 wmb();  /* Sync is_push and byte queue before pushing data */
 402
 403                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 404                 if (push_len > 16) {
 405                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 406                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 407                                          (push_len - 16) << 1);
 408                 } else {
 409                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 410                                          push_len);
 411                 }
 412
 413                 goto tx_done;
 414         }
 415
 416 normal_tx:
 417         if (length < BNXT_MIN_PKT_SIZE) {
 418                 pad = BNXT_MIN_PKT_SIZE - length;
 419                 if (skb_pad(skb, pad)) {
 420                         /* SKB already freed. */
 421                         tx_buf->skb = NULL;
 422                         return NETDEV_TX_OK;
 423                 }
 424                 length = BNXT_MIN_PKT_SIZE;
 425         }
 426
 427         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 428
 429         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 430                 dev_kfree_skb_any(skb);
 431                 tx_buf->skb = NULL;
 432                 return NETDEV_TX_OK;
 433         }
 434
 435         dma_unmap_addr_set(tx_buf, mapping, mapping);
 436         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 437                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 438
 439         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 440
 441         prod = NEXT_TX(prod);
 442         txbd1 = (struct tx_bd_ext *)
 443                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 444
 445         txbd1->tx_bd_hsize_lflags = 0;
 446         if (skb_is_gso(skb)) {
 447                 u32 hdr_len;
 448
 449                 if (skb->encapsulation)
 450                         hdr_len = skb_inner_network_offset(skb) +
 451                                 skb_inner_network_header_len(skb) +
 452                                 inner_tcp_hdrlen(skb);
 453                 else
 454                         hdr_len = skb_transport_offset(skb) +
 455                                 tcp_hdrlen(skb);
 456
 457                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 458                                         TX_BD_FLAGS_T_IPID |
 459                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 460                 length = skb_shinfo(skb)->gso_size;
 461                 txbd1->tx_bd_mss = cpu_to_le32(length);
 462                 length += hdr_len;
 463         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 464                 txbd1->tx_bd_hsize_lflags =
 465                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 466                 txbd1->tx_bd_mss = 0;
 467         }
 468
 469         length >>= 9;
 470         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 471                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 472                                      skb->len);
 473                 i = 0;
 474                 goto tx_dma_error;
 475         }
 476         flags |= bnxt_lhint_arr[length];
 477         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 478
 479         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 480         txbd1->tx_bd_cfa_action =
 481                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 482         for (i = 0; i < last_frag; i++) {
 483                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 484
 485                 prod = NEXT_TX(prod);
 486                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 487
 488                 len = skb_frag_size(frag);
 489                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 490                                            DMA_TO_DEVICE);
 491
 492                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 493                         goto tx_dma_error;
 494
 495                 tx_buf = &txr->tx_buf_ring[prod];
 496                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 497
 498                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 499
 500                 flags = len << TX_BD_LEN_SHIFT;
 501                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 502         }
 503
 504         flags &= ~TX_BD_LEN;
 505         txbd->tx_bd_len_flags_type =
 506                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 507                             TX_BD_FLAGS_PACKET_END);
 508
 509         netdev_tx_sent_queue(txq, skb->len);
 510
 511         /* Sync BD data before updating doorbell */
 512         wmb();
 513
 514         prod = NEXT_TX(prod);
 515         txr->tx_prod = prod;
 516
 517         if (!skb->xmit_more || netif_xmit_stopped(txq))
 518                 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 519
 520 tx_done:
 521
 522         mmiowb();
 523
 524         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 525                 if (skb->xmit_more && !tx_buf->is_push)
 526                         bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 527
 528                 bnxt_txr_netif_try_stop_queue(bp, txr, txq);
 529         }
 530         return NETDEV_TX_OK;
 531
 532 tx_dma_error:
 533         last_frag = i;
 534
 535         /* start back at beginning and unmap skb */
 536         prod = txr->tx_prod;
 537         tx_buf = &txr->tx_buf_ring[prod];
 538         tx_buf->skb = NULL;
 539         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 540                          skb_headlen(skb), PCI_DMA_TODEVICE);
 541         prod = NEXT_TX(prod);
 542
 543         /* unmap remaining mapped pages */
 544         for (i = 0; i < last_frag; i++) {
 545                 prod = NEXT_TX(prod);
 546                 tx_buf = &txr->tx_buf_ring[prod];
 547                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 548                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 549                                PCI_DMA_TODEVICE);
 550         }
 551
 552         dev_kfree_skb_any(skb);
 553         return NETDEV_TX_OK;
 554 }
 555
 556 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 557 {
 558         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 559         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 560         u16 cons = txr->tx_cons;
 561         struct pci_dev *pdev = bp->pdev;
 562         int i;
 563         unsigned int tx_bytes = 0;
 564
 565         for (i = 0; i < nr_pkts; i++) {
 566                 struct bnxt_sw_tx_bd *tx_buf;
 567                 struct sk_buff *skb;
 568                 int j, last;
 569
 570                 tx_buf = &txr->tx_buf_ring[cons];
 571                 cons = NEXT_TX(cons);
 572                 skb = tx_buf->skb;
 573                 tx_buf->skb = NULL;
 574
 575                 if (tx_buf->is_push) {
 576                         tx_buf->is_push = 0;
 577                         goto next_tx_int;
 578                 }
 579
 580                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 581                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 582                 last = tx_buf->nr_frags;
 583
 584                 for (j = 0; j < last; j++) {
 585                         cons = NEXT_TX(cons);
 586                         tx_buf = &txr->tx_buf_ring[cons];
 587                         dma_unmap_page(
 588                                 &pdev->dev,
 589                                 dma_unmap_addr(tx_buf, mapping),
 590                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 591                                 PCI_DMA_TODEVICE);
 592                 }
 593
 594 next_tx_int:
 595                 cons = NEXT_TX(cons);
 596
 597                 tx_bytes += skb->len;
 598                 dev_kfree_skb_any(skb);
 599         }
 600
 601         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 602         txr->tx_cons = cons;
 603
 604         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 605          * before checking for netif_tx_queue_stopped().  Without the
 606          * memory barrier, there is a small possibility that bnxt_start_xmit()
 607          * will miss it and cause the queue to be stopped forever.
 608          */
 609         smp_mb();
 610
 611         if (unlikely(netif_tx_queue_stopped(txq)) &&
 612             bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh &&
 613             READ_ONCE(txr->dev_state) != BNXT_DEV_STATE_CLOSING)
 614                 netif_tx_wake_queue(txq);
 615 }
 616
 617 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 618                                          gfp_t gfp)
 619 {
 620         struct device *dev = &bp->pdev->dev;
 621         struct page *page;
 622
 623         page = alloc_page(gfp);
 624         if (!page)
 625                 return NULL;
 626
 627         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 628                                       DMA_ATTR_WEAK_ORDERING);
 629         if (dma_mapping_error(dev, *mapping)) {
 630                 __free_page(page);
 631                 return NULL;
 632         }
 633         *mapping += bp->rx_dma_offset;
 634         return page;
 635 }
 636
 637 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 638                                        gfp_t gfp)
 639 {
 640         u8 *data;
 641         struct pci_dev *pdev = bp->pdev;
 642
 643         data = kmalloc(bp->rx_buf_size, gfp);
 644         if (!data)
 645                 return NULL;
 646
 647         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 648                                         bp->rx_buf_use_size, bp->rx_dir,
 649                                         DMA_ATTR_WEAK_ORDERING);
 650
 651         if (dma_mapping_error(&pdev->dev, *mapping)) {
 652                 kfree(data);
 653                 data = NULL;
 654         }
 655         return data;
 656 }
 657
 658 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 659                        u16 prod, gfp_t gfp)
 660 {
 661         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 662         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 663         dma_addr_t mapping;
 664
 665         if (BNXT_RX_PAGE_MODE(bp)) {
 666                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 667
 668                 if (!page)
 669                         return -ENOMEM;
 670
 671                 rx_buf->data = page;
 672                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 673         } else {
 674                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 675
 676                 if (!data)
 677                         return -ENOMEM;
 678
 679                 rx_buf->data = data;
 680                 rx_buf->data_ptr = data + bp->rx_offset;
 681         }
 682         rx_buf->mapping = mapping;
 683
 684         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 685         return 0;
 686 }
 687
 688 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 689 {
 690         u16 prod = rxr->rx_prod;
 691         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 692         struct rx_bd *cons_bd, *prod_bd;
 693
 694         prod_rx_buf = &rxr->rx_buf_ring[prod];
 695         cons_rx_buf = &rxr->rx_buf_ring[cons];
 696
 697         prod_rx_buf->data = data;
 698         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 699
 700         prod_rx_buf->mapping = cons_rx_buf->mapping;
 701
 702         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 703         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 704
 705         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 706 }
 707
 708 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 709 {
 710         u16 next, max = rxr->rx_agg_bmap_size;
 711
 712         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 713         if (next >= max)
 714                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 715         return next;
 716 }
 717
 718 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 719                                      struct bnxt_rx_ring_info *rxr,
 720                                      u16 prod, gfp_t gfp)
 721 {
 722         struct rx_bd *rxbd =
 723                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 724         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 725         struct pci_dev *pdev = bp->pdev;
 726         struct page *page;
 727         dma_addr_t mapping;
 728         u16 sw_prod = rxr->rx_sw_agg_prod;
 729         unsigned int offset = 0;
 730
 731         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 732                 page = rxr->rx_page;
 733                 if (!page) {
 734                         page = alloc_page(gfp);
 735                         if (!page)
 736                                 return -ENOMEM;
 737                         rxr->rx_page = page;
 738                         rxr->rx_page_offset = 0;
 739                 }
 740                 offset = rxr->rx_page_offset;
 741                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 742                 if (rxr->rx_page_offset == PAGE_SIZE)
 743                         rxr->rx_page = NULL;
 744                 else
 745                         get_page(page);
 746         } else {
 747                 page = alloc_page(gfp);
 748                 if (!page)
 749                         return -ENOMEM;
 750         }
 751
 752         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 753                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 754                                      DMA_ATTR_WEAK_ORDERING);
 755         if (dma_mapping_error(&pdev->dev, mapping)) {
 756                 __free_page(page);
 757                 return -EIO;
 758         }
 759
 760         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 761                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 762
 763         __set_bit(sw_prod, rxr->rx_agg_bmap);
 764         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 765         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 766
 767         rx_agg_buf->page = page;
 768         rx_agg_buf->offset = offset;
 769         rx_agg_buf->mapping = mapping;
 770         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 771         rxbd->rx_bd_opaque = sw_prod;
 772         return 0;
 773 }
 774
 775 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 776                                    u32 agg_bufs)
 777 {
 778         struct bnxt *bp = bnapi->bp;
 779         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 780         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 781         u16 prod = rxr->rx_agg_prod;
 782         u16 sw_prod = rxr->rx_sw_agg_prod;
 783         u32 i;
 784
 785         for (i = 0; i < agg_bufs; i++) {
 786                 u16 cons;
 787                 struct rx_agg_cmp *agg;
 788                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 789                 struct rx_bd *prod_bd;
 790                 struct page *page;
 791
 792                 agg = (struct rx_agg_cmp *)
 793                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 794                 cons = agg->rx_agg_cmp_opaque;
 795                 __clear_bit(cons, rxr->rx_agg_bmap);
 796
 797                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 798                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 799
 800                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 801                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 802                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 803
 804                 /* It is possible for sw_prod to be equal to cons, so
 805                  * set cons_rx_buf->page to NULL first.
 806                  */
 807                 page = cons_rx_buf->page;
 808                 cons_rx_buf->page = NULL;
 809                 prod_rx_buf->page = page;
 810                 prod_rx_buf->offset = cons_rx_buf->offset;
 811
 812                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 813
 814                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 815
 816                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 817                 prod_bd->rx_bd_opaque = sw_prod;
 818
 819                 prod = NEXT_RX_AGG(prod);
 820                 sw_prod = NEXT_RX_AGG(sw_prod);
 821                 cp_cons = NEXT_CMP(cp_cons);
 822         }
 823         rxr->rx_agg_prod = prod;
 824         rxr->rx_sw_agg_prod = sw_prod;
 825 }
 826
 827 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 828                                         struct bnxt_rx_ring_info *rxr,
 829                                         u16 cons, void *data, u8 *data_ptr,
 830                                         dma_addr_t dma_addr,
 831                                         unsigned int offset_and_len)
 832 {
 833         unsigned int payload = offset_and_len >> 16;
 834         unsigned int len = offset_and_len & 0xffff;
 835         struct skb_frag_struct *frag;
 836         struct page *page = data;
 837         u16 prod = rxr->rx_prod;
 838         struct sk_buff *skb;
 839         int off, err;
 840
 841         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 842         if (unlikely(err)) {
 843                 bnxt_reuse_rx_data(rxr, cons, data);
 844                 return NULL;
 845         }
 846         dma_addr -= bp->rx_dma_offset;
 847         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 848                              DMA_ATTR_WEAK_ORDERING);
 849
 850         if (unlikely(!payload))
 851                 payload = eth_get_headlen(data_ptr, len);
 852
 853         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 854         if (!skb) {
 855                 __free_page(page);
 856                 return NULL;
 857         }
 858
 859         off = (void *)data_ptr - page_address(page);
 860         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 861         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 862                payload + NET_IP_ALIGN);
 863
 864         frag = &skb_shinfo(skb)->frags[0];
 865         skb_frag_size_sub(frag, payload);
 866         frag->page_offset += payload;
 867         skb->data_len -= payload;
 868         skb->tail += payload;
 869
 870         return skb;
 871 }
 872
 873 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 874                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 875                                    void *data, u8 *data_ptr,
 876                                    dma_addr_t dma_addr,
 877                                    unsigned int offset_and_len)
 878 {
 879         u16 prod = rxr->rx_prod;
 880         struct sk_buff *skb;
 881         int err;
 882
 883         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 884         if (unlikely(err)) {
 885                 bnxt_reuse_rx_data(rxr, cons, data);
 886                 return NULL;
 887         }
 888
 889         skb = build_skb(data, 0);
 890         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 891                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 892         if (!skb) {
 893                 kfree(data);
 894                 return NULL;
 895         }
 896
 897         skb_reserve(skb, bp->rx_offset);
 898         skb_put(skb, offset_and_len & 0xffff);
 899         return skb;
 900 }
 901
 902 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 903                                      struct sk_buff *skb, u16 cp_cons,
 904                                      u32 agg_bufs)
 905 {
 906         struct pci_dev *pdev = bp->pdev;
 907         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 908         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 909         u16 prod = rxr->rx_agg_prod;
 910         u32 i;
 911
 912         for (i = 0; i < agg_bufs; i++) {
 913                 u16 cons, frag_len;
 914                 struct rx_agg_cmp *agg;
 915                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 916                 struct page *page;
 917                 dma_addr_t mapping;
 918
 919                 agg = (struct rx_agg_cmp *)
 920                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 921                 cons = agg->rx_agg_cmp_opaque;
 922                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 923                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 924
 925                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 926                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 927                                    cons_rx_buf->offset, frag_len);
 928                 __clear_bit(cons, rxr->rx_agg_bmap);
 929
 930                 /* It is possible for bnxt_alloc_rx_page() to allocate
 931                  * a sw_prod index that equals the cons index, so we
 932                  * need to clear the cons entry now.
 933                  */
 934                 mapping = cons_rx_buf->mapping;
 935                 page = cons_rx_buf->page;
 936                 cons_rx_buf->page = NULL;
 937
 938                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 939                         struct skb_shared_info *shinfo;
 940                         unsigned int nr_frags;
 941
 942                         shinfo = skb_shinfo(skb);
 943                         nr_frags = --shinfo->nr_frags;
 944                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 945
 946                         dev_kfree_skb(skb);
 947
 948                         cons_rx_buf->page = page;
 949
 950                         /* Update prod since possibly some pages have been
 951                          * allocated already.
 952                          */
 953                         rxr->rx_agg_prod = prod;
 954                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 955                         return NULL;
 956                 }
 957
 958                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 959                                      PCI_DMA_FROMDEVICE,
 960                                      DMA_ATTR_WEAK_ORDERING);
 961
 962                 skb->data_len += frag_len;
 963                 skb->len += frag_len;
 964                 skb->truesize += PAGE_SIZE;
 965
 966                 prod = NEXT_RX_AGG(prod);
 967                 cp_cons = NEXT_CMP(cp_cons);
 968         }
 969         rxr->rx_agg_prod = prod;
 970         return skb;
 971 }
 972
 973 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 974                                u8 agg_bufs, u32 *raw_cons)
 975 {
 976         u16 last;
 977         struct rx_agg_cmp *agg;
 978
 979         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 980         last = RING_CMP(*raw_cons);
 981         agg = (struct rx_agg_cmp *)
 982                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 983         return RX_AGG_CMP_VALID(agg, *raw_cons);
 984 }
 985
 986 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 987                                             unsigned int len,
 988                                             dma_addr_t mapping)
 989 {
 990         struct bnxt *bp = bnapi->bp;
 991         struct pci_dev *pdev = bp->pdev;
 992         struct sk_buff *skb;
 993
 994         skb = napi_alloc_skb(&bnapi->napi, len);
 995         if (!skb)
 996                 return NULL;
 997
 998         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
 999                                 bp->rx_dir);
1000
1001         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1002                len + NET_IP_ALIGN);
1003
1004         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1005                                    bp->rx_dir);
1006
1007         skb_put(skb, len);
1008         return skb;
1009 }
1010
1011 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1012                            u32 *raw_cons, void *cmp)
1013 {
1014         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1015         struct rx_cmp *rxcmp = cmp;
1016         u32 tmp_raw_cons = *raw_cons;
1017         u8 cmp_type, agg_bufs = 0;
1018
1019         cmp_type = RX_CMP_TYPE(rxcmp);
1020
1021         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1022                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1023                             RX_CMP_AGG_BUFS) >>
1024                            RX_CMP_AGG_BUFS_SHIFT;
1025         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1026                 struct rx_tpa_end_cmp *tpa_end = cmp;
1027
1028                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1029                             RX_TPA_END_CMP_AGG_BUFS) >>
1030                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1031         }
1032
1033         if (agg_bufs) {
1034                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1035                         return -EBUSY;
1036         }
1037         *raw_cons = tmp_raw_cons;
1038         return 0;
1039 }
1040
1041 static void bnxt_queue_sp_work(struct bnxt *bp)
1042 {
1043         if (BNXT_PF(bp))
1044                 queue_work(bnxt_pf_wq, &bp->sp_task);
1045         else
1046                 schedule_work(&bp->sp_task);
1047 }
1048
1049 static void bnxt_cancel_sp_work(struct bnxt *bp)
1050 {
1051         if (BNXT_PF(bp))
1052                 flush_workqueue(bnxt_pf_wq);
1053         else
1054                 cancel_work_sync(&bp->sp_task);
1055 }
1056
1057 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1058 {
1059         if (!rxr->bnapi->in_reset) {
1060                 rxr->bnapi->in_reset = true;
1061                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1062                 bnxt_queue_sp_work(bp);
1063         }
1064         rxr->rx_next_cons = 0xffff;
1065 }
1066
1067 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1068                            struct rx_tpa_start_cmp *tpa_start,
1069                            struct rx_tpa_start_cmp_ext *tpa_start1)
1070 {
1071         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1072         u16 cons, prod;
1073         struct bnxt_tpa_info *tpa_info;
1074         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1075         struct rx_bd *prod_bd;
1076         dma_addr_t mapping;
1077
1078         cons = tpa_start->rx_tpa_start_cmp_opaque;
1079         prod = rxr->rx_prod;
1080         cons_rx_buf = &rxr->rx_buf_ring[cons];
1081         prod_rx_buf = &rxr->rx_buf_ring[prod];
1082         tpa_info = &rxr->rx_tpa[agg_id];
1083
1084         if (unlikely(cons != rxr->rx_next_cons)) {
1085                 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1086                             cons, rxr->rx_next_cons);
1087                 bnxt_sched_reset(bp, rxr);
1088                 return;
1089         }
1090         /* Store cfa_code in tpa_info to use in tpa_end
1091          * completion processing.
1092          */
1093         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1094         prod_rx_buf->data = tpa_info->data;
1095         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1096
1097         mapping = tpa_info->mapping;
1098         prod_rx_buf->mapping = mapping;
1099
1100         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1101
1102         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1103
1104         tpa_info->data = cons_rx_buf->data;
1105         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1106         cons_rx_buf->data = NULL;
1107         tpa_info->mapping = cons_rx_buf->mapping;
1108
1109         tpa_info->len =
1110                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1111                                 RX_TPA_START_CMP_LEN_SHIFT;
1112         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1113                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1114
1115                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1116                 tpa_info->gso_type = SKB_GSO_TCPV4;
1117                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1118                 if (hash_type == 3)
1119                         tpa_info->gso_type = SKB_GSO_TCPV6;
1120                 tpa_info->rss_hash =
1121                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1122         } else {
1123                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1124                 tpa_info->gso_type = 0;
1125                 if (netif_msg_rx_err(bp))
1126                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1127         }
1128         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1129         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1130         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1131
1132         rxr->rx_prod = NEXT_RX(prod);
1133         cons = NEXT_RX(cons);
1134         rxr->rx_next_cons = NEXT_RX(cons);
1135         cons_rx_buf = &rxr->rx_buf_ring[cons];
1136
1137         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1138         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1139         cons_rx_buf->data = NULL;
1140 }
1141
1142 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1143                            u16 cp_cons, u32 agg_bufs)
1144 {
1145         if (agg_bufs)
1146                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1147 }
1148
1149 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1150                                            int payload_off, int tcp_ts,
1151                                            struct sk_buff *skb)
1152 {
1153 #ifdef CONFIG_INET
1154         struct tcphdr *th;
1155         int len, nw_off;
1156         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1157         u32 hdr_info = tpa_info->hdr_info;
1158         bool loopback = false;
1159
1160         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1161         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1162         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1163
1164         /* If the packet is an internal loopback packet, the offsets will
1165          * have an extra 4 bytes.
1166          */
1167         if (inner_mac_off == 4) {
1168                 loopback = true;
1169         } else if (inner_mac_off > 4) {
1170                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1171                                             ETH_HLEN - 2));
1172
1173                 /* We only support inner iPv4/ipv6.  If we don't see the
1174                  * correct protocol ID, it must be a loopback packet where
1175                  * the offsets are off by 4.
1176                  */
1177                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1178                         loopback = true;
1179         }
1180         if (loopback) {
1181                 /* internal loopback packet, subtract all offsets by 4 */
1182                 inner_ip_off -= 4;
1183                 inner_mac_off -= 4;
1184                 outer_ip_off -= 4;
1185         }
1186
1187         nw_off = inner_ip_off - ETH_HLEN;
1188         skb_set_network_header(skb, nw_off);
1189         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1190                 struct ipv6hdr *iph = ipv6_hdr(skb);
1191
1192                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1193                 len = skb->len - skb_transport_offset(skb);
1194                 th = tcp_hdr(skb);
1195                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1196         } else {
1197                 struct iphdr *iph = ip_hdr(skb);
1198
1199                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1200                 len = skb->len - skb_transport_offset(skb);
1201                 th = tcp_hdr(skb);
1202                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1203         }
1204
1205         if (inner_mac_off) { /* tunnel */
1206                 struct udphdr *uh = NULL;
1207                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1208                                             ETH_HLEN - 2));
1209
1210                 if (proto == htons(ETH_P_IP)) {
1211                         struct iphdr *iph = (struct iphdr *)skb->data;
1212
1213                         if (iph->protocol == IPPROTO_UDP)
1214                                 uh = (struct udphdr *)(iph + 1);
1215                 } else {
1216                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1217
1218                         if (iph->nexthdr == IPPROTO_UDP)
1219                                 uh = (struct udphdr *)(iph + 1);
1220                 }
1221                 if (uh) {
1222                         if (uh->check)
1223                                 skb_shinfo(skb)->gso_type |=
1224                                         SKB_GSO_UDP_TUNNEL_CSUM;
1225                         else
1226                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1227                 }
1228         }
1229 #endif
1230         return skb;
1231 }
1232
1233 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1234 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1235
1236 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1237                                            int payload_off, int tcp_ts,
1238                                            struct sk_buff *skb)
1239 {
1240 #ifdef CONFIG_INET
1241         struct tcphdr *th;
1242         int len, nw_off, tcp_opt_len = 0;
1243
1244         if (tcp_ts)
1245                 tcp_opt_len = 12;
1246
1247         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1248                 struct iphdr *iph;
1249
1250                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1251                          ETH_HLEN;
1252                 skb_set_network_header(skb, nw_off);
1253                 iph = ip_hdr(skb);
1254                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1255                 len = skb->len - skb_transport_offset(skb);
1256                 th = tcp_hdr(skb);
1257                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1258         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1259                 struct ipv6hdr *iph;
1260
1261                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1262                          ETH_HLEN;
1263                 skb_set_network_header(skb, nw_off);
1264                 iph = ipv6_hdr(skb);
1265                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1266                 len = skb->len - skb_transport_offset(skb);
1267                 th = tcp_hdr(skb);
1268                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1269         } else {
1270                 dev_kfree_skb_any(skb);
1271                 return NULL;
1272         }
1273
1274         if (nw_off) { /* tunnel */
1275                 struct udphdr *uh = NULL;
1276
1277                 if (skb->protocol == htons(ETH_P_IP)) {
1278                         struct iphdr *iph = (struct iphdr *)skb->data;
1279
1280                         if (iph->protocol == IPPROTO_UDP)
1281                                 uh = (struct udphdr *)(iph + 1);
1282                 } else {
1283                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1284
1285                         if (iph->nexthdr == IPPROTO_UDP)
1286                                 uh = (struct udphdr *)(iph + 1);
1287                 }
1288                 if (uh) {
1289                         if (uh->check)
1290                                 skb_shinfo(skb)->gso_type |=
1291                                         SKB_GSO_UDP_TUNNEL_CSUM;
1292                         else
1293                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1294                 }
1295         }
1296 #endif
1297         return skb;
1298 }
1299
1300 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1301                                            struct bnxt_tpa_info *tpa_info,
1302                                            struct rx_tpa_end_cmp *tpa_end,
1303                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1304                                            struct sk_buff *skb)
1305 {
1306 #ifdef CONFIG_INET
1307         int payload_off;
1308         u16 segs;
1309
1310         segs = TPA_END_TPA_SEGS(tpa_end);
1311         if (segs == 1)
1312                 return skb;
1313
1314         NAPI_GRO_CB(skb)->count = segs;
1315         skb_shinfo(skb)->gso_size =
1316                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1317         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1318         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1319                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1320                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1321         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1322         if (likely(skb))
1323                 tcp_gro_complete(skb);
1324 #endif
1325         return skb;
1326 }
1327
1328 /* Given the cfa_code of a received packet determine which
1329  * netdev (vf-rep or PF) the packet is destined to.
1330  */
1331 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1332 {
1333         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1334
1335         /* if vf-rep dev is NULL, the must belongs to the PF */
1336         return dev ? dev : bp->dev;
1337 }
1338
1339 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1340                                            struct bnxt_napi *bnapi,
1341                                            u32 *raw_cons,
1342                                            struct rx_tpa_end_cmp *tpa_end,
1343                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1344                                            u8 *event)
1345 {
1346         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1347         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1348         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1349         u8 *data_ptr, agg_bufs;
1350         u16 cp_cons = RING_CMP(*raw_cons);
1351         unsigned int len;
1352         struct bnxt_tpa_info *tpa_info;
1353         dma_addr_t mapping;
1354         struct sk_buff *skb;
1355         void *data;
1356
1357         if (unlikely(bnapi->in_reset)) {
1358                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1359
1360                 if (rc < 0)
1361                         return ERR_PTR(-EBUSY);
1362                 return NULL;
1363         }
1364
1365         tpa_info = &rxr->rx_tpa[agg_id];
1366         data = tpa_info->data;
1367         data_ptr = tpa_info->data_ptr;
1368         prefetch(data_ptr);
1369         len = tpa_info->len;
1370         mapping = tpa_info->mapping;
1371
1372         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1373                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1374
1375         if (agg_bufs) {
1376                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1377                         return ERR_PTR(-EBUSY);
1378
1379                 *event |= BNXT_AGG_EVENT;
1380                 cp_cons = NEXT_CMP(cp_cons);
1381         }
1382
1383         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1384                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1385                 if (agg_bufs > MAX_SKB_FRAGS)
1386                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1387                                     agg_bufs, (int)MAX_SKB_FRAGS);
1388                 return NULL;
1389         }
1390
1391         if (len <= bp->rx_copy_thresh) {
1392                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1393                 if (!skb) {
1394                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1395                         return NULL;
1396                 }
1397         } else {
1398                 u8 *new_data;
1399                 dma_addr_t new_mapping;
1400
1401                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1402                 if (!new_data) {
1403                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1404                         return NULL;
1405                 }
1406
1407                 tpa_info->data = new_data;
1408                 tpa_info->data_ptr = new_data + bp->rx_offset;
1409                 tpa_info->mapping = new_mapping;
1410
1411                 skb = build_skb(data, 0);
1412                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1413                                        bp->rx_buf_use_size, bp->rx_dir,
1414                                        DMA_ATTR_WEAK_ORDERING);
1415
1416                 if (!skb) {
1417                         kfree(data);
1418                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1419                         return NULL;
1420                 }
1421                 skb_reserve(skb, bp->rx_offset);
1422                 skb_put(skb, len);
1423         }
1424
1425         if (agg_bufs) {
1426                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1427                 if (!skb) {
1428                         /* Page reuse already handled by bnxt_rx_pages(). */
1429                         return NULL;
1430                 }
1431         }
1432
1433         skb->protocol =
1434                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1435
1436         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1437                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1438
1439         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1440             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1441                 u16 vlan_proto = tpa_info->metadata >>
1442                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1443                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1444
1445                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1446         }
1447
1448         skb_checksum_none_assert(skb);
1449         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1450                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1451                 skb->csum_level =
1452                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1453         }
1454
1455         if (TPA_END_GRO(tpa_end))
1456                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1457
1458         return skb;
1459 }
1460
1461 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1462                              struct sk_buff *skb)
1463 {
1464         if (skb->dev != bp->dev) {
1465                 /* this packet belongs to a vf-rep */
1466                 bnxt_vf_rep_rx(bp, skb);
1467                 return;
1468         }
1469         skb_record_rx_queue(skb, bnapi->index);
1470         napi_gro_receive(&bnapi->napi, skb);
1471 }
1472
1473 /* returns the following:
1474  * 1       - 1 packet successfully received
1475  * 0       - successful TPA_START, packet not completed yet
1476  * -EBUSY  - completion ring does not have all the agg buffers yet
1477  * -ENOMEM - packet aborted due to out of memory
1478  * -EIO    - packet aborted due to hw error indicated in BD
1479  */
1480 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1481                        u8 *event)
1482 {
1483         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1484         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1485         struct net_device *dev = bp->dev;
1486         struct rx_cmp *rxcmp;
1487         struct rx_cmp_ext *rxcmp1;
1488         u32 tmp_raw_cons = *raw_cons;
1489         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1490         struct bnxt_sw_rx_bd *rx_buf;
1491         unsigned int len;
1492         u8 *data_ptr, agg_bufs, cmp_type;
1493         dma_addr_t dma_addr;
1494         struct sk_buff *skb;
1495         void *data;
1496         int rc = 0;
1497         u32 misc;
1498
1499         rxcmp = (struct rx_cmp *)
1500                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1501
1502         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1503         cp_cons = RING_CMP(tmp_raw_cons);
1504         rxcmp1 = (struct rx_cmp_ext *)
1505                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1506
1507         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1508                 return -EBUSY;
1509
1510         cmp_type = RX_CMP_TYPE(rxcmp);
1511
1512         prod = rxr->rx_prod;
1513
1514         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1515                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1516                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1517
1518                 *event |= BNXT_RX_EVENT;
1519                 goto next_rx_no_prod;
1520
1521         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1522                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1523                                    (struct rx_tpa_end_cmp *)rxcmp,
1524                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1525
1526                 if (unlikely(IS_ERR(skb)))
1527                         return -EBUSY;
1528
1529                 rc = -ENOMEM;
1530                 if (likely(skb)) {
1531                         bnxt_deliver_skb(bp, bnapi, skb);
1532                         rc = 1;
1533                 }
1534                 *event |= BNXT_RX_EVENT;
1535                 goto next_rx_no_prod;
1536         }
1537
1538         cons = rxcmp->rx_cmp_opaque;
1539         if (unlikely(cons != rxr->rx_next_cons)) {
1540                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1541
1542                 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1543                             cons, rxr->rx_next_cons);
1544                 bnxt_sched_reset(bp, rxr);
1545                 return rc1;
1546         }
1547         rx_buf = &rxr->rx_buf_ring[cons];
1548         data = rx_buf->data;
1549         data_ptr = rx_buf->data_ptr;
1550         prefetch(data_ptr);
1551
1552         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1553         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1554
1555         if (agg_bufs) {
1556                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1557                         return -EBUSY;
1558
1559                 cp_cons = NEXT_CMP(cp_cons);
1560                 *event |= BNXT_AGG_EVENT;
1561         }
1562         *event |= BNXT_RX_EVENT;
1563
1564         rx_buf->data = NULL;
1565         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1566                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1567
1568                 bnxt_reuse_rx_data(rxr, cons, data);
1569                 if (agg_bufs)
1570                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1571
1572                 rc = -EIO;
1573                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1574                         netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1575                         bnxt_sched_reset(bp, rxr);
1576                 }
1577                 goto next_rx;
1578         }
1579
1580         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1581         dma_addr = rx_buf->mapping;
1582
1583         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1584                 rc = 1;
1585                 goto next_rx;
1586         }
1587
1588         if (len <= bp->rx_copy_thresh) {
1589                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1590                 bnxt_reuse_rx_data(rxr, cons, data);
1591                 if (!skb) {
1592                         if (agg_bufs)
1593                                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1594                         rc = -ENOMEM;
1595                         goto next_rx;
1596                 }
1597         } else {
1598                 u32 payload;
1599
1600                 if (rx_buf->data_ptr == data_ptr)
1601                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1602                 else
1603                         payload = 0;
1604                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1605                                       payload | len);
1606                 if (!skb) {
1607                         rc = -ENOMEM;
1608                         goto next_rx;
1609                 }
1610         }
1611
1612         if (agg_bufs) {
1613                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1614                 if (!skb) {
1615                         rc = -ENOMEM;
1616                         goto next_rx;
1617                 }
1618         }
1619
1620         if (RX_CMP_HASH_VALID(rxcmp)) {
1621                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1622                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1623
1624                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1625                 if (hash_type != 1 && hash_type != 3)
1626                         type = PKT_HASH_TYPE_L3;
1627                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1628         }
1629
1630         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1631         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1632
1633         if ((rxcmp1->rx_cmp_flags2 &
1634              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1635             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1636                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1637                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1638                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1639
1640                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1641         }
1642
1643         skb_checksum_none_assert(skb);
1644         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1645                 if (dev->features & NETIF_F_RXCSUM) {
1646                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1647                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1648                 }
1649         } else {
1650                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1651                         if (dev->features & NETIF_F_RXCSUM)
1652                                 cpr->rx_l4_csum_errors++;
1653                 }
1654         }
1655
1656         bnxt_deliver_skb(bp, bnapi, skb);
1657         rc = 1;
1658
1659 next_rx:
1660         rxr->rx_prod = NEXT_RX(prod);
1661         rxr->rx_next_cons = NEXT_RX(cons);
1662
1663 next_rx_no_prod:
1664         *raw_cons = tmp_raw_cons;
1665
1666         return rc;
1667 }
1668
1669 /* In netpoll mode, if we are using a combined completion ring, we need to
1670  * discard the rx packets and recycle the buffers.
1671  */
1672 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1673                                  u32 *raw_cons, u8 *event)
1674 {
1675         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1676         u32 tmp_raw_cons = *raw_cons;
1677         struct rx_cmp_ext *rxcmp1;
1678         struct rx_cmp *rxcmp;
1679         u16 cp_cons;
1680         u8 cmp_type;
1681
1682         cp_cons = RING_CMP(tmp_raw_cons);
1683         rxcmp = (struct rx_cmp *)
1684                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1685
1686         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1687         cp_cons = RING_CMP(tmp_raw_cons);
1688         rxcmp1 = (struct rx_cmp_ext *)
1689                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1690
1691         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1692                 return -EBUSY;
1693
1694         cmp_type = RX_CMP_TYPE(rxcmp);
1695         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1696                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1697                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1698         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1699                 struct rx_tpa_end_cmp_ext *tpa_end1;
1700
1701                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1702                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1703                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1704         }
1705         return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1706 }
1707
1708 #define BNXT_GET_EVENT_PORT(data)       \
1709         ((data) &                       \
1710          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1711
1712 static int bnxt_async_event_process(struct bnxt *bp,
1713                                     struct hwrm_async_event_cmpl *cmpl)
1714 {
1715         u16 event_id = le16_to_cpu(cmpl->event_id);
1716
1717         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1718         switch (event_id) {
1719         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1720                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1721                 struct bnxt_link_info *link_info = &bp->link_info;
1722
1723                 if (BNXT_VF(bp))
1724                         goto async_event_process_exit;
1725
1726                 /* print unsupported speed warning in forced speed mode only */
1727                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1728                     (data1 & 0x20000)) {
1729                         u16 fw_speed = link_info->force_link_speed;
1730                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1731
1732                         if (speed != SPEED_UNKNOWN)
1733                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1734                                             speed);
1735                 }
1736                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1737                 /* fall thru */
1738         }
1739         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1740                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1741                 break;
1742         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1743                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1744                 break;
1745         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1746                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1747                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1748
1749                 if (BNXT_VF(bp))
1750                         break;
1751
1752                 if (bp->pf.port_id != port_id)
1753                         break;
1754
1755                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1756                 break;
1757         }
1758         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1759                 if (BNXT_PF(bp))
1760                         goto async_event_process_exit;
1761                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1762                 break;
1763         default:
1764                 goto async_event_process_exit;
1765         }
1766         bnxt_queue_sp_work(bp);
1767 async_event_process_exit:
1768         bnxt_ulp_async_events(bp, cmpl);
1769         return 0;
1770 }
1771
1772 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1773 {
1774         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1775         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1776         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1777                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1778
1779         switch (cmpl_type) {
1780         case CMPL_BASE_TYPE_HWRM_DONE:
1781                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1782                 if (seq_id == bp->hwrm_intr_seq_id)
1783                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1784                 else
1785                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1786                 break;
1787
1788         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1789                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1790
1791                 if ((vf_id < bp->pf.first_vf_id) ||
1792                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1793                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1794                                    vf_id);
1795                         return -EINVAL;
1796                 }
1797
1798                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1799                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1800                 bnxt_queue_sp_work(bp);
1801                 break;
1802
1803         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1804                 bnxt_async_event_process(bp,
1805                                          (struct hwrm_async_event_cmpl *)txcmp);
1806
1807         default:
1808                 break;
1809         }
1810
1811         return 0;
1812 }
1813
1814 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1815 {
1816         struct bnxt_napi *bnapi = dev_instance;
1817         struct bnxt *bp = bnapi->bp;
1818         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1819         u32 cons = RING_CMP(cpr->cp_raw_cons);
1820
1821         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1822         napi_schedule(&bnapi->napi);
1823         return IRQ_HANDLED;
1824 }
1825
1826 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1827 {
1828         u32 raw_cons = cpr->cp_raw_cons;
1829         u16 cons = RING_CMP(raw_cons);
1830         struct tx_cmp *txcmp;
1831
1832         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1833
1834         return TX_CMP_VALID(txcmp, raw_cons);
1835 }
1836
1837 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1838 {
1839         struct bnxt_napi *bnapi = dev_instance;
1840         struct bnxt *bp = bnapi->bp;
1841         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1842         u32 cons = RING_CMP(cpr->cp_raw_cons);
1843         u32 int_status;
1844
1845         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1846
1847         if (!bnxt_has_work(bp, cpr)) {
1848                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1849                 /* return if erroneous interrupt */
1850                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1851                         return IRQ_NONE;
1852         }
1853
1854         /* disable ring IRQ */
1855         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1856
1857         /* Return here if interrupt is shared and is disabled. */
1858         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1859                 return IRQ_HANDLED;
1860
1861         napi_schedule(&bnapi->napi);
1862         return IRQ_HANDLED;
1863 }
1864
1865 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1866 {
1867         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1868         u32 raw_cons = cpr->cp_raw_cons;
1869         u32 cons;
1870         int tx_pkts = 0;
1871         int rx_pkts = 0;
1872         u8 event = 0;
1873         struct tx_cmp *txcmp;
1874
1875         while (1) {
1876                 int rc;
1877
1878                 cons = RING_CMP(raw_cons);
1879                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1880
1881                 if (!TX_CMP_VALID(txcmp, raw_cons))
1882                         break;
1883
1884                 /* The valid test of the entry must be done first before
1885                  * reading any further.
1886                  */
1887                 dma_rmb();
1888                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1889                         tx_pkts++;
1890                         /* return full budget so NAPI will complete. */
1891                         if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
1892                                 rx_pkts = budget;
1893                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1894                                 break;
1895                         }
1896                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1897                         if (likely(budget))
1898                                 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1899                         else
1900                                 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1901                                                            &event);
1902                         if (likely(rc >= 0))
1903                                 rx_pkts += rc;
1904                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1905                          * the NAPI budget.  Otherwise, we may potentially loop
1906                          * here forever if we consistently cannot allocate
1907                          * buffers.
1908                          */
1909                         else if (rc == -ENOMEM && budget)
1910                                 rx_pkts++;
1911                         else if (rc == -EBUSY)  /* partial completion */
1912                                 break;
1913                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1914                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1915                                     (TX_CMP_TYPE(txcmp) ==
1916                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1917                                     (TX_CMP_TYPE(txcmp) ==
1918                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1919                         bnxt_hwrm_handler(bp, txcmp);
1920                 }
1921                 raw_cons = NEXT_RAW_CMP(raw_cons);
1922
1923                 if (rx_pkts && rx_pkts == budget)
1924                         break;
1925         }
1926
1927         if (event & BNXT_TX_EVENT) {
1928                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1929                 void __iomem *db = txr->tx_doorbell;
1930                 u16 prod = txr->tx_prod;
1931
1932                 /* Sync BD data before updating doorbell */
1933                 wmb();
1934
1935                 bnxt_db_write(bp, db, DB_KEY_TX | prod);
1936         }
1937
1938         cpr->cp_raw_cons = raw_cons;
1939         /* ACK completion ring before freeing tx ring and producing new
1940          * buffers in rx/agg rings to prevent overflowing the completion
1941          * ring.
1942          */
1943         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1944
1945         if (tx_pkts)
1946                 bnapi->tx_int(bp, bnapi, tx_pkts);
1947
1948         if (event & BNXT_RX_EVENT) {
1949                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1950
1951                 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1952                 if (event & BNXT_AGG_EVENT)
1953                         bnxt_db_write(bp, rxr->rx_agg_doorbell,
1954                                       DB_KEY_RX | rxr->rx_agg_prod);
1955         }
1956         return rx_pkts;
1957 }
1958
1959 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1960 {
1961         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1962         struct bnxt *bp = bnapi->bp;
1963         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1964         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1965         struct tx_cmp *txcmp;
1966         struct rx_cmp_ext *rxcmp1;
1967         u32 cp_cons, tmp_raw_cons;
1968         u32 raw_cons = cpr->cp_raw_cons;
1969         u32 rx_pkts = 0;
1970         u8 event = 0;
1971
1972         while (1) {
1973                 int rc;
1974
1975                 cp_cons = RING_CMP(raw_cons);
1976                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1977
1978                 if (!TX_CMP_VALID(txcmp, raw_cons))
1979                         break;
1980
1981                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1982                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1983                         cp_cons = RING_CMP(tmp_raw_cons);
1984                         rxcmp1 = (struct rx_cmp_ext *)
1985                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1986
1987                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1988                                 break;
1989
1990                         /* force an error to recycle the buffer */
1991                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1992                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1993
1994                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1995                         if (likely(rc == -EIO) && budget)
1996                                 rx_pkts++;
1997                         else if (rc == -EBUSY)  /* partial completion */
1998                                 break;
1999                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2000                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2001                         bnxt_hwrm_handler(bp, txcmp);
2002                 } else {
2003                         netdev_err(bp->dev,
2004                                    "Invalid completion received on special ring\n");
2005                 }
2006                 raw_cons = NEXT_RAW_CMP(raw_cons);
2007
2008                 if (rx_pkts == budget)
2009                         break;
2010         }
2011
2012         cpr->cp_raw_cons = raw_cons;
2013         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2014         bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2015
2016         if (event & BNXT_AGG_EVENT)
2017                 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2018                               DB_KEY_RX | rxr->rx_agg_prod);
2019
2020         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2021                 napi_complete_done(napi, rx_pkts);
2022                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2023         }
2024         return rx_pkts;
2025 }
2026
2027 static int bnxt_poll(struct napi_struct *napi, int budget)
2028 {
2029         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2030         struct bnxt *bp = bnapi->bp;
2031         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2032         int work_done = 0;
2033
2034         while (1) {
2035                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2036
2037                 if (work_done >= budget) {
2038                         if (!budget)
2039                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2040                                                  cpr->cp_raw_cons);
2041                         break;
2042                 }
2043
2044                 if (!bnxt_has_work(bp, cpr)) {
2045                         if (napi_complete_done(napi, work_done))
2046                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2047                                                  cpr->cp_raw_cons);
2048                         break;
2049                 }
2050         }
2051         mmiowb();
2052         return work_done;
2053 }
2054
2055 static void bnxt_free_tx_skbs(struct bnxt *bp)
2056 {
2057         int i, max_idx;
2058         struct pci_dev *pdev = bp->pdev;
2059
2060         if (!bp->tx_ring)
2061                 return;
2062
2063         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2064         for (i = 0; i < bp->tx_nr_rings; i++) {
2065                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2066                 int j;
2067
2068                 for (j = 0; j < max_idx;) {
2069                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2070                         struct sk_buff *skb = tx_buf->skb;
2071                         int k, last;
2072
2073                         if (!skb) {
2074                                 j++;
2075                                 continue;
2076                         }
2077
2078                         tx_buf->skb = NULL;
2079
2080                         if (tx_buf->is_push) {
2081                                 dev_kfree_skb(skb);
2082                                 j += 2;
2083                                 continue;
2084                         }
2085
2086                         dma_unmap_single(&pdev->dev,
2087                                          dma_unmap_addr(tx_buf, mapping),
2088                                          skb_headlen(skb),
2089                                          PCI_DMA_TODEVICE);
2090
2091                         last = tx_buf->nr_frags;
2092                         j += 2;
2093                         for (k = 0; k < last; k++, j++) {
2094                                 int ring_idx = j & bp->tx_ring_mask;
2095                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2096
2097                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2098                                 dma_unmap_page(
2099                                         &pdev->dev,
2100                                         dma_unmap_addr(tx_buf, mapping),
2101                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2102                         }
2103                         dev_kfree_skb(skb);
2104                 }
2105                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2106         }
2107 }
2108
2109 static void bnxt_free_rx_skbs(struct bnxt *bp)
2110 {
2111         int i, max_idx, max_agg_idx;
2112         struct pci_dev *pdev = bp->pdev;
2113
2114         if (!bp->rx_ring)
2115                 return;
2116
2117         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2118         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2119         for (i = 0; i < bp->rx_nr_rings; i++) {
2120                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2121                 int j;
2122
2123                 if (rxr->rx_tpa) {
2124                         for (j = 0; j < MAX_TPA; j++) {
2125                                 struct bnxt_tpa_info *tpa_info =
2126                                                         &rxr->rx_tpa[j];
2127                                 u8 *data = tpa_info->data;
2128
2129                                 if (!data)
2130                                         continue;
2131
2132                                 dma_unmap_single_attrs(&pdev->dev,
2133                                                        tpa_info->mapping,
2134                                                        bp->rx_buf_use_size,
2135                                                        bp->rx_dir,
2136                                                        DMA_ATTR_WEAK_ORDERING);
2137
2138                                 tpa_info->data = NULL;
2139
2140                                 kfree(data);
2141                         }
2142                 }
2143
2144                 for (j = 0; j < max_idx; j++) {
2145                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2146                         dma_addr_t mapping = rx_buf->mapping;
2147                         void *data = rx_buf->data;
2148
2149                         if (!data)
2150                                 continue;
2151
2152                         rx_buf->data = NULL;
2153
2154                         if (BNXT_RX_PAGE_MODE(bp)) {
2155                                 mapping -= bp->rx_dma_offset;
2156                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2157                                                      PAGE_SIZE, bp->rx_dir,
2158                                                      DMA_ATTR_WEAK_ORDERING);
2159                                 __free_page(data);
2160                         } else {
2161                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2162                                                        bp->rx_buf_use_size,
2163                                                        bp->rx_dir,
2164                                                        DMA_ATTR_WEAK_ORDERING);
2165                                 kfree(data);
2166                         }
2167                 }
2168
2169                 for (j = 0; j < max_agg_idx; j++) {
2170                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2171                                 &rxr->rx_agg_ring[j];
2172                         struct page *page = rx_agg_buf->page;
2173
2174                         if (!page)
2175                                 continue;
2176
2177                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2178                                              BNXT_RX_PAGE_SIZE,
2179                                              PCI_DMA_FROMDEVICE,
2180                                              DMA_ATTR_WEAK_ORDERING);
2181
2182                         rx_agg_buf->page = NULL;
2183                         __clear_bit(j, rxr->rx_agg_bmap);
2184
2185                         __free_page(page);
2186                 }
2187                 if (rxr->rx_page) {
2188                         __free_page(rxr->rx_page);
2189                         rxr->rx_page = NULL;
2190                 }
2191         }
2192 }
2193
2194 static void bnxt_free_skbs(struct bnxt *bp)
2195 {
2196         bnxt_free_tx_skbs(bp);
2197         bnxt_free_rx_skbs(bp);
2198 }
2199
2200 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2201 {
2202         struct pci_dev *pdev = bp->pdev;
2203         int i;
2204
2205         for (i = 0; i < ring->nr_pages; i++) {
2206                 if (!ring->pg_arr[i])
2207                         continue;
2208
2209                 dma_free_coherent(&pdev->dev, ring->page_size,
2210                                   ring->pg_arr[i], ring->dma_arr[i]);
2211
2212                 ring->pg_arr[i] = NULL;
2213         }
2214         if (ring->pg_tbl) {
2215                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2216                                   ring->pg_tbl, ring->pg_tbl_map);
2217                 ring->pg_tbl = NULL;
2218         }
2219         if (ring->vmem_size && *ring->vmem) {
2220                 vfree(*ring->vmem);
2221                 *ring->vmem = NULL;
2222         }
2223 }
2224
2225 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2226 {
2227         int i;
2228         struct pci_dev *pdev = bp->pdev;
2229
2230         if (ring->nr_pages > 1) {
2231                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2232                                                   ring->nr_pages * 8,
2233                                                   &ring->pg_tbl_map,
2234                                                   GFP_KERNEL);
2235                 if (!ring->pg_tbl)
2236                         return -ENOMEM;
2237         }
2238
2239         for (i = 0; i < ring->nr_pages; i++) {
2240                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2241                                                      ring->page_size,
2242                                                      &ring->dma_arr[i],
2243                                                      GFP_KERNEL);
2244                 if (!ring->pg_arr[i])
2245                         return -ENOMEM;
2246
2247                 if (ring->nr_pages > 1)
2248                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2249         }
2250
2251         if (ring->vmem_size) {
2252                 *ring->vmem = vzalloc(ring->vmem_size);
2253                 if (!(*ring->vmem))
2254                         return -ENOMEM;
2255         }
2256         return 0;
2257 }
2258
2259 static void bnxt_free_rx_rings(struct bnxt *bp)
2260 {
2261         int i;
2262
2263         if (!bp->rx_ring)
2264                 return;
2265
2266         for (i = 0; i < bp->rx_nr_rings; i++) {
2267                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2268                 struct bnxt_ring_struct *ring;
2269
2270                 if (rxr->xdp_prog)
2271                         bpf_prog_put(rxr->xdp_prog);
2272
2273                 kfree(rxr->rx_tpa);
2274                 rxr->rx_tpa = NULL;
2275
2276                 kfree(rxr->rx_agg_bmap);
2277                 rxr->rx_agg_bmap = NULL;
2278
2279                 ring = &rxr->rx_ring_struct;
2280                 bnxt_free_ring(bp, ring);
2281
2282                 ring = &rxr->rx_agg_ring_struct;
2283                 bnxt_free_ring(bp, ring);
2284         }
2285 }
2286
2287 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2288 {
2289         int i, rc, agg_rings = 0, tpa_rings = 0;
2290
2291         if (!bp->rx_ring)
2292                 return -ENOMEM;
2293
2294         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2295                 agg_rings = 1;
2296
2297         if (bp->flags & BNXT_FLAG_TPA)
2298                 tpa_rings = 1;
2299
2300         for (i = 0; i < bp->rx_nr_rings; i++) {
2301                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2302                 struct bnxt_ring_struct *ring;
2303
2304                 ring = &rxr->rx_ring_struct;
2305
2306                 rc = bnxt_alloc_ring(bp, ring);
2307                 if (rc)
2308                         return rc;
2309
2310                 if (agg_rings) {
2311                         u16 mem_size;
2312
2313                         ring = &rxr->rx_agg_ring_struct;
2314                         rc = bnxt_alloc_ring(bp, ring);
2315                         if (rc)
2316                                 return rc;
2317
2318                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2319                         mem_size = rxr->rx_agg_bmap_size / 8;
2320                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2321                         if (!rxr->rx_agg_bmap)
2322                                 return -ENOMEM;
2323
2324                         if (tpa_rings) {
2325                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2326                                                 sizeof(struct bnxt_tpa_info),
2327                                                 GFP_KERNEL);
2328                                 if (!rxr->rx_tpa)
2329                                         return -ENOMEM;
2330                         }
2331                 }
2332         }
2333         return 0;
2334 }
2335
2336 static void bnxt_free_tx_rings(struct bnxt *bp)
2337 {
2338         int i;
2339         struct pci_dev *pdev = bp->pdev;
2340
2341         if (!bp->tx_ring)
2342                 return;
2343
2344         for (i = 0; i < bp->tx_nr_rings; i++) {
2345                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2346                 struct bnxt_ring_struct *ring;
2347
2348                 if (txr->tx_push) {
2349                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2350                                           txr->tx_push, txr->tx_push_mapping);
2351                         txr->tx_push = NULL;
2352                 }
2353
2354                 ring = &txr->tx_ring_struct;
2355
2356                 bnxt_free_ring(bp, ring);
2357         }
2358 }
2359
2360 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2361 {
2362         int i, j, rc;
2363         struct pci_dev *pdev = bp->pdev;
2364
2365         bp->tx_push_size = 0;
2366         if (bp->tx_push_thresh) {
2367                 int push_size;
2368
2369                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2370                                         bp->tx_push_thresh);
2371
2372                 if (push_size > 256) {
2373                         push_size = 0;
2374                         bp->tx_push_thresh = 0;
2375                 }
2376
2377                 bp->tx_push_size = push_size;
2378         }
2379
2380         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2381                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2382                 struct bnxt_ring_struct *ring;
2383
2384                 ring = &txr->tx_ring_struct;
2385
2386                 rc = bnxt_alloc_ring(bp, ring);
2387                 if (rc)
2388                         return rc;
2389
2390                 if (bp->tx_push_size) {
2391                         dma_addr_t mapping;
2392
2393                         /* One pre-allocated DMA buffer to backup
2394                          * TX push operation
2395                          */
2396                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2397                                                 bp->tx_push_size,
2398                                                 &txr->tx_push_mapping,
2399                                                 GFP_KERNEL);
2400
2401                         if (!txr->tx_push)
2402                                 return -ENOMEM;
2403
2404                         mapping = txr->tx_push_mapping +
2405                                 sizeof(struct tx_push_bd);
2406                         txr->data_mapping = cpu_to_le64(mapping);
2407
2408                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2409                 }
2410                 ring->queue_id = bp->q_info[j].queue_id;
2411                 if (i < bp->tx_nr_rings_xdp)
2412                         continue;
2413                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2414                         j++;
2415         }
2416         return 0;
2417 }
2418
2419 static void bnxt_free_cp_rings(struct bnxt *bp)
2420 {
2421         int i;
2422
2423         if (!bp->bnapi)
2424                 return;
2425
2426         for (i = 0; i < bp->cp_nr_rings; i++) {
2427                 struct bnxt_napi *bnapi = bp->bnapi[i];
2428                 struct bnxt_cp_ring_info *cpr;
2429                 struct bnxt_ring_struct *ring;
2430
2431                 if (!bnapi)
2432                         continue;
2433
2434                 cpr = &bnapi->cp_ring;
2435                 ring = &cpr->cp_ring_struct;
2436
2437                 bnxt_free_ring(bp, ring);
2438         }
2439 }
2440
2441 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2442 {
2443         int i, rc;
2444
2445         for (i = 0; i < bp->cp_nr_rings; i++) {
2446                 struct bnxt_napi *bnapi = bp->bnapi[i];
2447                 struct bnxt_cp_ring_info *cpr;
2448                 struct bnxt_ring_struct *ring;
2449
2450                 if (!bnapi)
2451                         continue;
2452
2453                 cpr = &bnapi->cp_ring;
2454                 ring = &cpr->cp_ring_struct;
2455
2456                 rc = bnxt_alloc_ring(bp, ring);
2457                 if (rc)
2458                         return rc;
2459         }
2460         return 0;
2461 }
2462
2463 static void bnxt_init_ring_struct(struct bnxt *bp)
2464 {
2465         int i;
2466
2467         for (i = 0; i < bp->cp_nr_rings; i++) {
2468                 struct bnxt_napi *bnapi = bp->bnapi[i];
2469                 struct bnxt_cp_ring_info *cpr;
2470                 struct bnxt_rx_ring_info *rxr;
2471                 struct bnxt_tx_ring_info *txr;
2472                 struct bnxt_ring_struct *ring;
2473
2474                 if (!bnapi)
2475                         continue;
2476
2477                 cpr = &bnapi->cp_ring;
2478                 ring = &cpr->cp_ring_struct;
2479                 ring->nr_pages = bp->cp_nr_pages;
2480                 ring->page_size = HW_CMPD_RING_SIZE;
2481                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2482                 ring->dma_arr = cpr->cp_desc_mapping;
2483                 ring->vmem_size = 0;
2484
2485                 rxr = bnapi->rx_ring;
2486                 if (!rxr)
2487                         goto skip_rx;
2488
2489                 ring = &rxr->rx_ring_struct;
2490                 ring->nr_pages = bp->rx_nr_pages;
2491                 ring->page_size = HW_RXBD_RING_SIZE;
2492                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2493                 ring->dma_arr = rxr->rx_desc_mapping;
2494                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2495                 ring->vmem = (void **)&rxr->rx_buf_ring;
2496
2497                 ring = &rxr->rx_agg_ring_struct;
2498                 ring->nr_pages = bp->rx_agg_nr_pages;
2499                 ring->page_size = HW_RXBD_RING_SIZE;
2500                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2501                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2502                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2503                 ring->vmem = (void **)&rxr->rx_agg_ring;
2504
2505 skip_rx:
2506                 txr = bnapi->tx_ring;
2507                 if (!txr)
2508                         continue;
2509
2510                 ring = &txr->tx_ring_struct;
2511                 ring->nr_pages = bp->tx_nr_pages;
2512                 ring->page_size = HW_RXBD_RING_SIZE;
2513                 ring->pg_arr = (void **)txr->tx_desc_ring;
2514                 ring->dma_arr = txr->tx_desc_mapping;
2515                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2516                 ring->vmem = (void **)&txr->tx_buf_ring;
2517         }
2518 }
2519
2520 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2521 {
2522         int i;
2523         u32 prod;
2524         struct rx_bd **rx_buf_ring;
2525
2526         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2527         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2528                 int j;
2529                 struct rx_bd *rxbd;
2530
2531                 rxbd = rx_buf_ring[i];
2532                 if (!rxbd)
2533                         continue;
2534
2535                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2536                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2537                         rxbd->rx_bd_opaque = prod;
2538                 }
2539         }
2540 }
2541
2542 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2543 {
2544         struct net_device *dev = bp->dev;
2545         struct bnxt_rx_ring_info *rxr;
2546         struct bnxt_ring_struct *ring;
2547         u32 prod, type;
2548         int i;
2549
2550         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2551                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2552
2553         if (NET_IP_ALIGN == 2)
2554                 type |= RX_BD_FLAGS_SOP;
2555
2556         rxr = &bp->rx_ring[ring_nr];
2557         ring = &rxr->rx_ring_struct;
2558         bnxt_init_rxbd_pages(ring, type);
2559
2560         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2561                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2562                 if (IS_ERR(rxr->xdp_prog)) {
2563                         int rc = PTR_ERR(rxr->xdp_prog);
2564
2565                         rxr->xdp_prog = NULL;
2566                         return rc;
2567                 }
2568         }
2569         prod = rxr->rx_prod;
2570         for (i = 0; i < bp->rx_ring_size; i++) {
2571                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2572                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2573                                     ring_nr, i, bp->rx_ring_size);
2574                         break;
2575                 }
2576                 prod = NEXT_RX(prod);
2577         }
2578         rxr->rx_prod = prod;
2579         ring->fw_ring_id = INVALID_HW_RING_ID;
2580
2581         ring = &rxr->rx_agg_ring_struct;
2582         ring->fw_ring_id = INVALID_HW_RING_ID;
2583
2584         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2585                 return 0;
2586
2587         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2588                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2589
2590         bnxt_init_rxbd_pages(ring, type);
2591
2592         prod = rxr->rx_agg_prod;
2593         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2594                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2595                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2596                                     ring_nr, i, bp->rx_ring_size);
2597                         break;
2598                 }
2599                 prod = NEXT_RX_AGG(prod);
2600         }
2601         rxr->rx_agg_prod = prod;
2602
2603         if (bp->flags & BNXT_FLAG_TPA) {
2604                 if (rxr->rx_tpa) {
2605                         u8 *data;
2606                         dma_addr_t mapping;
2607
2608                         for (i = 0; i < MAX_TPA; i++) {
2609                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2610                                                             GFP_KERNEL);
2611                                 if (!data)
2612                                         return -ENOMEM;
2613
2614                                 rxr->rx_tpa[i].data = data;
2615                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2616                                 rxr->rx_tpa[i].mapping = mapping;
2617                         }
2618                 } else {
2619                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2620                         return -ENOMEM;
2621                 }
2622         }
2623
2624         return 0;
2625 }
2626
2627 static void bnxt_init_cp_rings(struct bnxt *bp)
2628 {
2629         int i;
2630
2631         for (i = 0; i < bp->cp_nr_rings; i++) {
2632                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2633                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2634
2635                 ring->fw_ring_id = INVALID_HW_RING_ID;
2636         }
2637 }
2638
2639 static int bnxt_init_rx_rings(struct bnxt *bp)
2640 {
2641         int i, rc = 0;
2642
2643         if (BNXT_RX_PAGE_MODE(bp)) {
2644                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2645                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2646         } else {
2647                 bp->rx_offset = BNXT_RX_OFFSET;
2648                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2649         }
2650
2651         for (i = 0; i < bp->rx_nr_rings; i++) {
2652                 rc = bnxt_init_one_rx_ring(bp, i);
2653                 if (rc)
2654                         break;
2655         }
2656
2657         return rc;
2658 }
2659
2660 static int bnxt_init_tx_rings(struct bnxt *bp)
2661 {
2662         u16 i;
2663
2664         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2665                                    BNXT_MIN_TX_DESC_CNT);
2666
2667         for (i = 0; i < bp->tx_nr_rings; i++) {
2668                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2669                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2670
2671                 ring->fw_ring_id = INVALID_HW_RING_ID;
2672         }
2673
2674         return 0;
2675 }
2676
2677 static void bnxt_free_ring_grps(struct bnxt *bp)
2678 {
2679         kfree(bp->grp_info);
2680         bp->grp_info = NULL;
2681 }
2682
2683 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2684 {
2685         int i;
2686
2687         if (irq_re_init) {
2688                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2689                                        sizeof(struct bnxt_ring_grp_info),
2690                                        GFP_KERNEL);
2691                 if (!bp->grp_info)
2692                         return -ENOMEM;
2693         }
2694         for (i = 0; i < bp->cp_nr_rings; i++) {
2695                 if (irq_re_init)
2696                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2697                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2698                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2699                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2700                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2701         }
2702         return 0;
2703 }
2704
2705 static void bnxt_free_vnics(struct bnxt *bp)
2706 {
2707         kfree(bp->vnic_info);
2708         bp->vnic_info = NULL;
2709         bp->nr_vnics = 0;
2710 }
2711
2712 static int bnxt_alloc_vnics(struct bnxt *bp)
2713 {
2714         int num_vnics = 1;
2715
2716 #ifdef CONFIG_RFS_ACCEL
2717         if (bp->flags & BNXT_FLAG_RFS)
2718                 num_vnics += bp->rx_nr_rings;
2719 #endif
2720
2721         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2722                 num_vnics++;
2723
2724         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2725                                 GFP_KERNEL);
2726         if (!bp->vnic_info)
2727                 return -ENOMEM;
2728
2729         bp->nr_vnics = num_vnics;
2730         return 0;
2731 }
2732
2733 static void bnxt_init_vnics(struct bnxt *bp)
2734 {
2735         int i;
2736
2737         for (i = 0; i < bp->nr_vnics; i++) {
2738                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2739
2740                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2741                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2742                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2743                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2744
2745                 if (bp->vnic_info[i].rss_hash_key) {
2746                         if (i == 0)
2747                                 prandom_bytes(vnic->rss_hash_key,
2748                                               HW_HASH_KEY_SIZE);
2749                         else
2750                                 memcpy(vnic->rss_hash_key,
2751                                        bp->vnic_info[0].rss_hash_key,
2752                                        HW_HASH_KEY_SIZE);
2753                 }
2754         }
2755 }
2756
2757 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2758 {
2759         int pages;
2760
2761         pages = ring_size / desc_per_pg;
2762
2763         if (!pages)
2764                 return 1;
2765
2766         pages++;
2767
2768         while (pages & (pages - 1))
2769                 pages++;
2770
2771         return pages;
2772 }
2773
2774 void bnxt_set_tpa_flags(struct bnxt *bp)
2775 {
2776         bp->flags &= ~BNXT_FLAG_TPA;
2777         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2778                 return;
2779         if (bp->dev->features & NETIF_F_LRO)
2780                 bp->flags |= BNXT_FLAG_LRO;
2781         if (bp->dev->features & NETIF_F_GRO)
2782                 bp->flags |= BNXT_FLAG_GRO;
2783 }
2784
2785 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2786  * be set on entry.
2787  */
2788 void bnxt_set_ring_params(struct bnxt *bp)
2789 {
2790         u32 ring_size, rx_size, rx_space;
2791         u32 agg_factor = 0, agg_ring_size = 0;
2792
2793         /* 8 for CRC and VLAN */
2794         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2795
2796         rx_space = rx_size + NET_SKB_PAD +
2797                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2798
2799         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2800         ring_size = bp->rx_ring_size;
2801         bp->rx_agg_ring_size = 0;
2802         bp->rx_agg_nr_pages = 0;
2803
2804         if (bp->flags & BNXT_FLAG_TPA)
2805                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2806
2807         bp->flags &= ~BNXT_FLAG_JUMBO;
2808         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2809                 u32 jumbo_factor;
2810
2811                 bp->flags |= BNXT_FLAG_JUMBO;
2812                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2813                 if (jumbo_factor > agg_factor)
2814                         agg_factor = jumbo_factor;
2815         }
2816         agg_ring_size = ring_size * agg_factor;
2817
2818         if (agg_ring_size) {
2819                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2820                                                         RX_DESC_CNT);
2821                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2822                         u32 tmp = agg_ring_size;
2823
2824                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2825                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2826                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2827                                     tmp, agg_ring_size);
2828                 }
2829                 bp->rx_agg_ring_size = agg_ring_size;
2830                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2831                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2832                 rx_space = rx_size + NET_SKB_PAD +
2833                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2834         }
2835
2836         bp->rx_buf_use_size = rx_size;
2837         bp->rx_buf_size = rx_space;
2838
2839         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2840         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2841
2842         ring_size = bp->tx_ring_size;
2843         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2844         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2845
2846         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2847         bp->cp_ring_size = ring_size;
2848
2849         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2850         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2851                 bp->cp_nr_pages = MAX_CP_PAGES;
2852                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2853                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2854                             ring_size, bp->cp_ring_size);
2855         }
2856         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2857         bp->cp_ring_mask = bp->cp_bit - 1;
2858 }
2859
2860 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2861 {
2862         if (page_mode) {
2863                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2864                         return -EOPNOTSUPP;
2865                 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2866                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2867                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2868                 bp->dev->hw_features &= ~NETIF_F_LRO;
2869                 bp->dev->features &= ~NETIF_F_LRO;
2870                 bp->rx_dir = DMA_BIDIRECTIONAL;
2871                 bp->rx_skb_func = bnxt_rx_page_skb;
2872         } else {
2873                 bp->dev->max_mtu = BNXT_MAX_MTU;
2874                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2875                 bp->rx_dir = DMA_FROM_DEVICE;
2876                 bp->rx_skb_func = bnxt_rx_skb;
2877         }
2878         return 0;
2879 }
2880
2881 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2882 {
2883         int i;
2884         struct bnxt_vnic_info *vnic;
2885         struct pci_dev *pdev = bp->pdev;
2886
2887         if (!bp->vnic_info)
2888                 return;
2889
2890         for (i = 0; i < bp->nr_vnics; i++) {
2891                 vnic = &bp->vnic_info[i];
2892
2893                 kfree(vnic->fw_grp_ids);
2894                 vnic->fw_grp_ids = NULL;
2895
2896                 kfree(vnic->uc_list);
2897                 vnic->uc_list = NULL;
2898
2899                 if (vnic->mc_list) {
2900                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2901                                           vnic->mc_list, vnic->mc_list_mapping);
2902                         vnic->mc_list = NULL;
2903                 }
2904
2905                 if (vnic->rss_table) {
2906                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2907                                           vnic->rss_table,
2908                                           vnic->rss_table_dma_addr);
2909                         vnic->rss_table = NULL;
2910                 }
2911
2912                 vnic->rss_hash_key = NULL;
2913                 vnic->flags = 0;
2914         }
2915 }
2916
2917 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2918 {
2919         int i, rc = 0, size;
2920         struct bnxt_vnic_info *vnic;
2921         struct pci_dev *pdev = bp->pdev;
2922         int max_rings;
2923
2924         for (i = 0; i < bp->nr_vnics; i++) {
2925                 vnic = &bp->vnic_info[i];
2926
2927                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2928                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2929
2930                         if (mem_size > 0) {
2931                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2932                                 if (!vnic->uc_list) {
2933                                         rc = -ENOMEM;
2934                                         goto out;
2935                                 }
2936                         }
2937                 }
2938
2939                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2940                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2941                         vnic->mc_list =
2942                                 dma_alloc_coherent(&pdev->dev,
2943                                                    vnic->mc_list_size,
2944                                                    &vnic->mc_list_mapping,
2945                                                    GFP_KERNEL);
2946                         if (!vnic->mc_list) {
2947                                 rc = -ENOMEM;
2948                                 goto out;
2949                         }
2950                 }
2951
2952                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2953                         max_rings = bp->rx_nr_rings;
2954                 else
2955                         max_rings = 1;
2956
2957                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2958                 if (!vnic->fw_grp_ids) {
2959                         rc = -ENOMEM;
2960                         goto out;
2961                 }
2962
2963                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2964                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2965                         continue;
2966
2967                 /* Allocate rss table and hash key */
2968                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2969                                                      &vnic->rss_table_dma_addr,
2970                                                      GFP_KERNEL);
2971                 if (!vnic->rss_table) {
2972                         rc = -ENOMEM;
2973                         goto out;
2974                 }
2975
2976                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2977
2978                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2979                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2980         }
2981         return 0;
2982
2983 out:
2984         return rc;
2985 }
2986
2987 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2988 {
2989         struct pci_dev *pdev = bp->pdev;
2990
2991         if (bp->hwrm_cmd_resp_addr) {
2992                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2993                                   bp->hwrm_cmd_resp_dma_addr);
2994                 bp->hwrm_cmd_resp_addr = NULL;
2995         }
2996         if (bp->hwrm_dbg_resp_addr) {
2997                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2998                                   bp->hwrm_dbg_resp_addr,
2999                                   bp->hwrm_dbg_resp_dma_addr);
3000
3001                 bp->hwrm_dbg_resp_addr = NULL;
3002         }
3003 }
3004
3005 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3006 {
3007         struct pci_dev *pdev = bp->pdev;
3008
3009         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3010                                                    &bp->hwrm_cmd_resp_dma_addr,
3011                                                    GFP_KERNEL);
3012         if (!bp->hwrm_cmd_resp_addr)
3013                 return -ENOMEM;
3014         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
3015                                                     HWRM_DBG_REG_BUF_SIZE,
3016                                                     &bp->hwrm_dbg_resp_dma_addr,
3017                                                     GFP_KERNEL);
3018         if (!bp->hwrm_dbg_resp_addr)
3019                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
3020
3021         return 0;
3022 }
3023
3024 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3025 {
3026         if (bp->hwrm_short_cmd_req_addr) {
3027                 struct pci_dev *pdev = bp->pdev;
3028
3029                 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3030                                   bp->hwrm_short_cmd_req_addr,
3031                                   bp->hwrm_short_cmd_req_dma_addr);
3032                 bp->hwrm_short_cmd_req_addr = NULL;
3033         }
3034 }
3035
3036 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3037 {
3038         struct pci_dev *pdev = bp->pdev;
3039
3040         bp->hwrm_short_cmd_req_addr =
3041                 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3042                                    &bp->hwrm_short_cmd_req_dma_addr,
3043                                    GFP_KERNEL);
3044         if (!bp->hwrm_short_cmd_req_addr)
3045                 return -ENOMEM;
3046
3047         return 0;
3048 }
3049
3050 static void bnxt_free_stats(struct bnxt *bp)
3051 {
3052         u32 size, i;
3053         struct pci_dev *pdev = bp->pdev;
3054
3055         if (bp->hw_rx_port_stats) {
3056                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3057                                   bp->hw_rx_port_stats,
3058                                   bp->hw_rx_port_stats_map);
3059                 bp->hw_rx_port_stats = NULL;
3060                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3061         }
3062
3063         if (!bp->bnapi)
3064                 return;
3065
3066         size = sizeof(struct ctx_hw_stats);
3067
3068         for (i = 0; i < bp->cp_nr_rings; i++) {
3069                 struct bnxt_napi *bnapi = bp->bnapi[i];
3070                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3071
3072                 if (cpr->hw_stats) {
3073                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3074                                           cpr->hw_stats_map);
3075                         cpr->hw_stats = NULL;
3076                 }
3077         }
3078 }
3079
3080 static int bnxt_alloc_stats(struct bnxt *bp)
3081 {
3082         u32 size, i;
3083         struct pci_dev *pdev = bp->pdev;
3084
3085         size = sizeof(struct ctx_hw_stats);
3086
3087         for (i = 0; i < bp->cp_nr_rings; i++) {
3088                 struct bnxt_napi *bnapi = bp->bnapi[i];
3089                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3090
3091                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3092                                                    &cpr->hw_stats_map,
3093                                                    GFP_KERNEL);
3094                 if (!cpr->hw_stats)
3095                         return -ENOMEM;
3096
3097                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3098         }
3099
3100         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3101                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3102                                          sizeof(struct tx_port_stats) + 1024;
3103
3104                 bp->hw_rx_port_stats =
3105                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3106                                            &bp->hw_rx_port_stats_map,
3107                                            GFP_KERNEL);
3108                 if (!bp->hw_rx_port_stats)
3109                         return -ENOMEM;
3110
3111                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3112                                        512;
3113                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3114                                            sizeof(struct rx_port_stats) + 512;
3115                 bp->flags |= BNXT_FLAG_PORT_STATS;
3116         }
3117         return 0;
3118 }
3119
3120 static void bnxt_clear_ring_indices(struct bnxt *bp)
3121 {
3122         int i;
3123
3124         if (!bp->bnapi)
3125                 return;
3126
3127         for (i = 0; i < bp->cp_nr_rings; i++) {
3128                 struct bnxt_napi *bnapi = bp->bnapi[i];
3129                 struct bnxt_cp_ring_info *cpr;
3130                 struct bnxt_rx_ring_info *rxr;
3131                 struct bnxt_tx_ring_info *txr;
3132
3133                 if (!bnapi)
3134                         continue;
3135
3136                 cpr = &bnapi->cp_ring;
3137                 cpr->cp_raw_cons = 0;
3138
3139                 txr = bnapi->tx_ring;
3140                 if (txr) {
3141                         txr->tx_prod = 0;
3142                         txr->tx_cons = 0;
3143                 }
3144
3145                 rxr = bnapi->rx_ring;
3146                 if (rxr) {
3147                         rxr->rx_prod = 0;
3148                         rxr->rx_agg_prod = 0;
3149                         rxr->rx_sw_agg_prod = 0;
3150                         rxr->rx_next_cons = 0;
3151                 }
3152         }
3153 }
3154
3155 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3156 {
3157 #ifdef CONFIG_RFS_ACCEL
3158         int i;
3159
3160         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3161          * safe to delete the hash table.
3162          */
3163         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3164                 struct hlist_head *head;
3165                 struct hlist_node *tmp;
3166                 struct bnxt_ntuple_filter *fltr;
3167
3168                 head = &bp->ntp_fltr_hash_tbl[i];
3169                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3170                         hlist_del(&fltr->hash);
3171                         kfree(fltr);
3172                 }
3173         }
3174         if (irq_reinit) {
3175                 kfree(bp->ntp_fltr_bmap);
3176                 bp->ntp_fltr_bmap = NULL;
3177         }
3178         bp->ntp_fltr_count = 0;
3179 #endif
3180 }
3181
3182 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3183 {
3184 #ifdef CONFIG_RFS_ACCEL
3185         int i, rc = 0;
3186
3187         if (!(bp->flags & BNXT_FLAG_RFS))
3188                 return 0;
3189
3190         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3191                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3192
3193         bp->ntp_fltr_count = 0;
3194         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3195                                     sizeof(long),
3196                                     GFP_KERNEL);
3197
3198         if (!bp->ntp_fltr_bmap)
3199                 rc = -ENOMEM;
3200
3201         return rc;
3202 #else
3203         return 0;
3204 #endif
3205 }
3206
3207 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3208 {
3209         bnxt_free_vnic_attributes(bp);
3210         bnxt_free_tx_rings(bp);
3211         bnxt_free_rx_rings(bp);
3212         bnxt_free_cp_rings(bp);
3213         bnxt_free_ntp_fltrs(bp, irq_re_init);
3214         if (irq_re_init) {
3215                 bnxt_free_stats(bp);
3216                 bnxt_free_ring_grps(bp);
3217                 bnxt_free_vnics(bp);
3218                 kfree(bp->tx_ring_map);
3219                 bp->tx_ring_map = NULL;
3220                 kfree(bp->tx_ring);
3221                 bp->tx_ring = NULL;
3222                 kfree(bp->rx_ring);
3223                 bp->rx_ring = NULL;
3224                 kfree(bp->bnapi);
3225                 bp->bnapi = NULL;
3226         } else {
3227                 bnxt_clear_ring_indices(bp);
3228         }
3229 }
3230
3231 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3232 {
3233         int i, j, rc, size, arr_size;
3234         void *bnapi;
3235
3236         if (irq_re_init) {
3237                 /* Allocate bnapi mem pointer array and mem block for
3238                  * all queues
3239                  */
3240                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3241                                 bp->cp_nr_rings);
3242                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3243                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3244                 if (!bnapi)
3245                         return -ENOMEM;
3246
3247                 bp->bnapi = bnapi;
3248                 bnapi += arr_size;
3249                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3250                         bp->bnapi[i] = bnapi;
3251                         bp->bnapi[i]->index = i;
3252                         bp->bnapi[i]->bp = bp;
3253                 }
3254
3255                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3256                                       sizeof(struct bnxt_rx_ring_info),
3257                                       GFP_KERNEL);
3258                 if (!bp->rx_ring)
3259                         return -ENOMEM;
3260
3261                 for (i = 0; i < bp->rx_nr_rings; i++) {
3262                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3263                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3264                 }
3265
3266                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3267                                       sizeof(struct bnxt_tx_ring_info),
3268                                       GFP_KERNEL);
3269                 if (!bp->tx_ring)
3270                         return -ENOMEM;
3271
3272                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3273                                           GFP_KERNEL);
3274
3275                 if (!bp->tx_ring_map)
3276                         return -ENOMEM;
3277
3278                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3279                         j = 0;
3280                 else
3281                         j = bp->rx_nr_rings;
3282
3283                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3284                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3285                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3286                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3287                         if (i >= bp->tx_nr_rings_xdp) {
3288                                 bp->tx_ring[i].txq_index = i -
3289                                         bp->tx_nr_rings_xdp;
3290                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3291                         } else {
3292                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3293                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3294                         }
3295                 }
3296
3297                 rc = bnxt_alloc_stats(bp);
3298                 if (rc)
3299                         goto alloc_mem_err;
3300
3301                 rc = bnxt_alloc_ntp_fltrs(bp);
3302                 if (rc)
3303                         goto alloc_mem_err;
3304
3305                 rc = bnxt_alloc_vnics(bp);
3306                 if (rc)
3307                         goto alloc_mem_err;
3308         }
3309
3310         bnxt_init_ring_struct(bp);
3311
3312         rc = bnxt_alloc_rx_rings(bp);
3313         if (rc)
3314                 goto alloc_mem_err;
3315
3316         rc = bnxt_alloc_tx_rings(bp);
3317         if (rc)
3318                 goto alloc_mem_err;
3319
3320         rc = bnxt_alloc_cp_rings(bp);
3321         if (rc)
3322                 goto alloc_mem_err;
3323
3324         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3325                                   BNXT_VNIC_UCAST_FLAG;
3326         rc = bnxt_alloc_vnic_attributes(bp);
3327         if (rc)
3328                 goto alloc_mem_err;
3329         return 0;
3330
3331 alloc_mem_err:
3332         bnxt_free_mem(bp, true);
3333         return rc;
3334 }
3335
3336 static void bnxt_disable_int(struct bnxt *bp)
3337 {
3338         int i;
3339
3340         if (!bp->bnapi)
3341                 return;
3342
3343         for (i = 0; i < bp->cp_nr_rings; i++) {
3344                 struct bnxt_napi *bnapi = bp->bnapi[i];
3345                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3346                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3347
3348                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3349                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3350         }
3351 }
3352
3353 static void bnxt_disable_int_sync(struct bnxt *bp)
3354 {
3355         int i;
3356
3357         atomic_inc(&bp->intr_sem);
3358
3359         bnxt_disable_int(bp);
3360         for (i = 0; i < bp->cp_nr_rings; i++)
3361                 synchronize_irq(bp->irq_tbl[i].vector);
3362 }
3363
3364 static void bnxt_enable_int(struct bnxt *bp)
3365 {
3366         int i;
3367
3368         atomic_set(&bp->intr_sem, 0);
3369         for (i = 0; i < bp->cp_nr_rings; i++) {
3370                 struct bnxt_napi *bnapi = bp->bnapi[i];
3371                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3372
3373                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3374         }
3375 }
3376
3377 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3378                             u16 cmpl_ring, u16 target_id)
3379 {
3380         struct input *req = request;
3381
3382         req->req_type = cpu_to_le16(req_type);
3383         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3384         req->target_id = cpu_to_le16(target_id);
3385         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3386 }
3387
3388 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3389                                  int timeout, bool silent)
3390 {
3391         int i, intr_process, rc, tmo_count;
3392         struct input *req = msg;
3393         u32 *data = msg;
3394         __le32 *resp_len, *valid;
3395         u16 cp_ring_id, len = 0;
3396         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3397         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3398
3399         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3400         memset(resp, 0, PAGE_SIZE);
3401         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3402         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3403
3404         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3405                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3406                 struct hwrm_short_input short_input = {0};
3407
3408                 memcpy(short_cmd_req, req, msg_len);
3409                 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3410                                                    msg_len);
3411
3412                 short_input.req_type = req->req_type;
3413                 short_input.signature =
3414                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3415                 short_input.size = cpu_to_le16(msg_len);
3416                 short_input.req_addr =
3417                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3418
3419                 data = (u32 *)&short_input;
3420                 msg_len = sizeof(short_input);
3421
3422                 /* Sync memory write before updating doorbell */
3423                 wmb();
3424
3425                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3426         }
3427
3428         /* Write request msg to hwrm channel */
3429         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3430
3431         for (i = msg_len; i < max_req_len; i += 4)
3432                 writel(0, bp->bar0 + i);
3433
3434         /* currently supports only one outstanding message */
3435         if (intr_process)
3436                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3437
3438         /* Ring channel doorbell */
3439         writel(1, bp->bar0 + 0x100);
3440
3441         if (!timeout)
3442                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3443
3444         i = 0;
3445         tmo_count = timeout * 40;
3446         if (intr_process) {
3447                 /* Wait until hwrm response cmpl interrupt is processed */
3448                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3449                        i++ < tmo_count) {
3450                         usleep_range(25, 40);
3451                 }
3452
3453                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3454                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3455                                    le16_to_cpu(req->req_type));
3456                         return -1;
3457                 }
3458         } else {
3459                 /* Check if response len is updated */
3460                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3461                 for (i = 0; i < tmo_count; i++) {
3462                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3463                               HWRM_RESP_LEN_SFT;
3464                         if (len)
3465                                 break;
3466                         usleep_range(25, 40);
3467                 }
3468
3469                 if (i >= tmo_count) {
3470                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3471                                    timeout, le16_to_cpu(req->req_type),
3472                                    le16_to_cpu(req->seq_id), len);
3473                         return -1;
3474                 }
3475
3476                 /* Last word of resp contains valid bit */
3477                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3478                 for (i = 0; i < 5; i++) {
3479                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3480                                 break;
3481                         udelay(1);
3482                 }
3483
3484                 if (i >= 5) {
3485                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3486                                    timeout, le16_to_cpu(req->req_type),
3487                                    le16_to_cpu(req->seq_id), len, *valid);
3488                         return -1;
3489                 }
3490         }
3491
3492         rc = le16_to_cpu(resp->error_code);
3493         if (rc && !silent)
3494                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3495                            le16_to_cpu(resp->req_type),
3496                            le16_to_cpu(resp->seq_id), rc);
3497         return rc;
3498 }
3499
3500 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3501 {
3502         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3503 }
3504
3505 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3506                               int timeout)
3507 {
3508         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3509 }
3510
3511 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3512 {
3513         int rc;
3514
3515         mutex_lock(&bp->hwrm_cmd_lock);
3516         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3517         mutex_unlock(&bp->hwrm_cmd_lock);
3518         return rc;
3519 }
3520
3521 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3522                              int timeout)
3523 {
3524         int rc;
3525
3526         mutex_lock(&bp->hwrm_cmd_lock);
3527         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3528         mutex_unlock(&bp->hwrm_cmd_lock);
3529         return rc;
3530 }
3531
3532 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3533                                      int bmap_size)
3534 {
3535         struct hwrm_func_drv_rgtr_input req = {0};
3536         DECLARE_BITMAP(async_events_bmap, 256);
3537         u32 *events = (u32 *)async_events_bmap;
3538         int i;
3539
3540         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3541
3542         req.enables =
3543                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3544
3545         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3546         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3547                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3548
3549         if (bmap && bmap_size) {
3550                 for (i = 0; i < bmap_size; i++) {
3551                         if (test_bit(i, bmap))
3552                                 __set_bit(i, async_events_bmap);
3553                 }
3554         }
3555
3556         for (i = 0; i < 8; i++)
3557                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3558
3559         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3560 }
3561
3562 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3563 {
3564         struct hwrm_func_drv_rgtr_input req = {0};
3565
3566         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3567
3568         req.enables =
3569                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3570                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3571
3572         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3573         req.ver_maj = DRV_VER_MAJ;
3574         req.ver_min = DRV_VER_MIN;
3575         req.ver_upd = DRV_VER_UPD;
3576
3577         if (BNXT_PF(bp)) {
3578                 u32 data[8];
3579                 int i;
3580
3581                 memset(data, 0, sizeof(data));
3582                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3583                         u16 cmd = bnxt_vf_req_snif[i];
3584                         unsigned int bit, idx;
3585
3586                         idx = cmd / 32;
3587                         bit = cmd % 32;
3588                         data[idx] |= 1 << bit;
3589                 }
3590
3591                 for (i = 0; i < 8; i++)
3592                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3593
3594                 req.enables |=
3595                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3596         }
3597
3598         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3599 }
3600
3601 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3602 {
3603         struct hwrm_func_drv_unrgtr_input req = {0};
3604
3605         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3606         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3607 }
3608
3609 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3610 {
3611         u32 rc = 0;
3612         struct hwrm_tunnel_dst_port_free_input req = {0};
3613
3614         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3615         req.tunnel_type = tunnel_type;
3616
3617         switch (tunnel_type) {
3618         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3619                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3620                 break;
3621         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3622                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3623                 break;
3624         default:
3625                 break;
3626         }
3627
3628         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3629         if (rc)
3630                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3631                            rc);
3632         return rc;
3633 }
3634
3635 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3636                                            u8 tunnel_type)
3637 {
3638         u32 rc = 0;
3639         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3640         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3641
3642         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3643
3644         req.tunnel_type = tunnel_type;
3645         req.tunnel_dst_port_val = port;
3646
3647         mutex_lock(&bp->hwrm_cmd_lock);
3648         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3649         if (rc) {
3650                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3651                            rc);
3652                 goto err_out;
3653         }
3654
3655         switch (tunnel_type) {
3656         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3657                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3658                 break;
3659         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3660                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3661                 break;
3662         default:
3663                 break;
3664         }
3665
3666 err_out:
3667         mutex_unlock(&bp->hwrm_cmd_lock);
3668         return rc;
3669 }
3670
3671 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3672 {
3673         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3674         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3675
3676         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3677         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3678
3679         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3680         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3681         req.mask = cpu_to_le32(vnic->rx_mask);
3682         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3683 }
3684
3685 #ifdef CONFIG_RFS_ACCEL
3686 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3687                                             struct bnxt_ntuple_filter *fltr)
3688 {
3689         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3690
3691         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3692         req.ntuple_filter_id = fltr->filter_id;
3693         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3694 }
3695
3696 #define BNXT_NTP_FLTR_FLAGS                                     \
3697         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3698          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3699          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3700          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3701          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3702          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3703          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3704          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3705          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3706          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3707          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3708          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3709          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3710          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3711
3712 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3713                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3714
3715 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3716                                              struct bnxt_ntuple_filter *fltr)
3717 {
3718         int rc = 0;
3719         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3720         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3721                 bp->hwrm_cmd_resp_addr;
3722         struct flow_keys *keys = &fltr->fkeys;
3723         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3724
3725         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3726         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3727
3728         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3729
3730         req.ethertype = htons(ETH_P_IP);
3731         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3732         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3733         req.ip_protocol = keys->basic.ip_proto;
3734
3735         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3736                 int i;
3737
3738                 req.ethertype = htons(ETH_P_IPV6);
3739                 req.ip_addr_type =
3740                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3741                 *(struct in6_addr *)&req.src_ipaddr[0] =
3742                         keys->addrs.v6addrs.src;
3743                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3744                         keys->addrs.v6addrs.dst;
3745                 for (i = 0; i < 4; i++) {
3746                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3747                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3748                 }
3749         } else {
3750                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3751                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3752                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3753                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3754         }
3755         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3756                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3757                 req.tunnel_type =
3758                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3759         }
3760
3761         req.src_port = keys->ports.src;
3762         req.src_port_mask = cpu_to_be16(0xffff);
3763         req.dst_port = keys->ports.dst;
3764         req.dst_port_mask = cpu_to_be16(0xffff);
3765
3766         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3767         mutex_lock(&bp->hwrm_cmd_lock);
3768         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3769         if (!rc)
3770                 fltr->filter_id = resp->ntuple_filter_id;
3771         mutex_unlock(&bp->hwrm_cmd_lock);
3772         return rc;
3773 }
3774 #endif
3775
3776 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3777                                      u8 *mac_addr)
3778 {
3779         u32 rc = 0;
3780         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3781         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3782
3783         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3784         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3785         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3786                 req.flags |=
3787                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3788         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3789         req.enables =
3790                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3791                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3792                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3793         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3794         req.l2_addr_mask[0] = 0xff;
3795         req.l2_addr_mask[1] = 0xff;
3796         req.l2_addr_mask[2] = 0xff;
3797         req.l2_addr_mask[3] = 0xff;
3798         req.l2_addr_mask[4] = 0xff;
3799         req.l2_addr_mask[5] = 0xff;
3800
3801         mutex_lock(&bp->hwrm_cmd_lock);
3802         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3803         if (!rc)
3804                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3805                                                         resp->l2_filter_id;
3806         mutex_unlock(&bp->hwrm_cmd_lock);
3807         return rc;
3808 }
3809
3810 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3811 {
3812         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3813         int rc = 0;
3814
3815         /* Any associated ntuple filters will also be cleared by firmware. */
3816         mutex_lock(&bp->hwrm_cmd_lock);
3817         for (i = 0; i < num_of_vnics; i++) {
3818                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3819
3820                 for (j = 0; j < vnic->uc_filter_count; j++) {
3821                         struct hwrm_cfa_l2_filter_free_input req = {0};
3822
3823                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3824                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3825
3826                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3827
3828                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3829                                                 HWRM_CMD_TIMEOUT);
3830                 }
3831                 vnic->uc_filter_count = 0;
3832         }
3833         mutex_unlock(&bp->hwrm_cmd_lock);
3834
3835         return rc;
3836 }
3837
3838 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3839 {
3840         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3841         struct hwrm_vnic_tpa_cfg_input req = {0};
3842
3843         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3844                 return 0;
3845
3846         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3847
3848         if (tpa_flags) {
3849                 u16 mss = bp->dev->mtu - 40;
3850                 u32 nsegs, n, segs = 0, flags;
3851
3852                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3853                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3854                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3855                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3856                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3857                 if (tpa_flags & BNXT_FLAG_GRO)
3858                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3859
3860                 req.flags = cpu_to_le32(flags);
3861
3862                 req.enables =
3863                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3864                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3865                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3866
3867                 /* Number of segs are log2 units, and first packet is not
3868                  * included as part of this units.
3869                  */
3870                 if (mss <= BNXT_RX_PAGE_SIZE) {
3871                         n = BNXT_RX_PAGE_SIZE / mss;
3872                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3873                 } else {
3874                         n = mss / BNXT_RX_PAGE_SIZE;
3875                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3876                                 n++;
3877                         nsegs = (MAX_SKB_FRAGS - n) / n;
3878                 }
3879
3880                 segs = ilog2(nsegs);
3881                 req.max_agg_segs = cpu_to_le16(segs);
3882                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3883
3884                 req.min_agg_len = cpu_to_le32(512);
3885         }
3886         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3887
3888         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3889 }
3890
3891 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3892 {
3893         u32 i, j, max_rings;
3894         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3895         struct hwrm_vnic_rss_cfg_input req = {0};
3896
3897         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3898                 return 0;
3899
3900         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3901         if (set_rss) {
3902                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3903                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3904                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3905                                 max_rings = bp->rx_nr_rings - 1;
3906                         else
3907                                 max_rings = bp->rx_nr_rings;
3908                 } else {
3909                         max_rings = 1;
3910                 }
3911
3912                 /* Fill the RSS indirection table with ring group ids */
3913                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3914                         if (j == max_rings)
3915                                 j = 0;
3916                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3917                 }
3918
3919                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3920                 req.hash_key_tbl_addr =
3921                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3922         }
3923         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3924         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3925 }
3926
3927 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3928 {
3929         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3930         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3931
3932         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3933         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3934                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3935                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3936         req.enables =
3937                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3938                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3939         /* thresholds not implemented in firmware yet */
3940         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3941         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3942         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3943         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3944 }
3945
3946 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3947                                         u16 ctx_idx)
3948 {
3949         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3950
3951         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3952         req.rss_cos_lb_ctx_id =
3953                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3954
3955         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3956         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3957 }
3958
3959 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3960 {
3961         int i, j;
3962
3963         for (i = 0; i < bp->nr_vnics; i++) {
3964                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3965
3966                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3967                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3968                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3969                 }
3970         }
3971         bp->rsscos_nr_ctxs = 0;
3972 }
3973
3974 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3975 {
3976         int rc;
3977         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3978         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3979                                                 bp->hwrm_cmd_resp_addr;
3980
3981         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3982                                -1);
3983
3984         mutex_lock(&bp->hwrm_cmd_lock);
3985         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3986         if (!rc)
3987                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3988                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3989         mutex_unlock(&bp->hwrm_cmd_lock);
3990
3991         return rc;
3992 }
3993
3994 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3995 {
3996         unsigned int ring = 0, grp_idx;
3997         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3998         struct hwrm_vnic_cfg_input req = {0};
3999         u16 def_vlan = 0;
4000
4001         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4002
4003         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4004         /* Only RSS support for now TBD: COS & LB */
4005         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4006                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4007                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4008                                            VNIC_CFG_REQ_ENABLES_MRU);
4009         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4010                 req.rss_rule =
4011                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4012                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4013                                            VNIC_CFG_REQ_ENABLES_MRU);
4014                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4015         } else {
4016                 req.rss_rule = cpu_to_le16(0xffff);
4017         }
4018
4019         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4020             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4021                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4022                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4023         } else {
4024                 req.cos_rule = cpu_to_le16(0xffff);
4025         }
4026
4027         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4028                 ring = 0;
4029         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4030                 ring = vnic_id - 1;
4031         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4032                 ring = bp->rx_nr_rings - 1;
4033
4034         grp_idx = bp->rx_ring[ring].bnapi->index;
4035         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4036         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4037
4038         req.lb_rule = cpu_to_le16(0xffff);
4039         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4040                               VLAN_HLEN);
4041
4042 #ifdef CONFIG_BNXT_SRIOV
4043         if (BNXT_VF(bp))
4044                 def_vlan = bp->vf.vlan;
4045 #endif
4046         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4047                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4048         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4049                 req.flags |=
4050                         cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
4051
4052         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4053 }
4054
4055 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4056 {
4057         u32 rc = 0;
4058
4059         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4060                 struct hwrm_vnic_free_input req = {0};
4061
4062                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4063                 req.vnic_id =
4064                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4065
4066                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4067                 if (rc)
4068                         return rc;
4069                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4070         }
4071         return rc;
4072 }
4073
4074 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4075 {
4076         u16 i;
4077
4078         for (i = 0; i < bp->nr_vnics; i++)
4079                 bnxt_hwrm_vnic_free_one(bp, i);
4080 }
4081
4082 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4083                                 unsigned int start_rx_ring_idx,
4084                                 unsigned int nr_rings)
4085 {
4086         int rc = 0;
4087         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4088         struct hwrm_vnic_alloc_input req = {0};
4089         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4090
4091         /* map ring groups to this vnic */
4092         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4093                 grp_idx = bp->rx_ring[i].bnapi->index;
4094                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4095                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4096                                    j, nr_rings);
4097                         break;
4098                 }
4099                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4100                                         bp->grp_info[grp_idx].fw_grp_id;
4101         }
4102
4103         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4104         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4105         if (vnic_id == 0)
4106                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4107
4108         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4109
4110         mutex_lock(&bp->hwrm_cmd_lock);
4111         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4112         if (!rc)
4113                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4114         mutex_unlock(&bp->hwrm_cmd_lock);
4115         return rc;
4116 }
4117
4118 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4119 {
4120         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4121         struct hwrm_vnic_qcaps_input req = {0};
4122         int rc;
4123
4124         if (bp->hwrm_spec_code < 0x10600)
4125                 return 0;
4126
4127         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4128         mutex_lock(&bp->hwrm_cmd_lock);
4129         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4130         if (!rc) {
4131                 if (resp->flags &
4132                     cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4133                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4134         }
4135         mutex_unlock(&bp->hwrm_cmd_lock);
4136         return rc;
4137 }
4138
4139 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4140 {
4141         u16 i;
4142         u32 rc = 0;
4143
4144         mutex_lock(&bp->hwrm_cmd_lock);
4145         for (i = 0; i < bp->rx_nr_rings; i++) {
4146                 struct hwrm_ring_grp_alloc_input req = {0};
4147                 struct hwrm_ring_grp_alloc_output *resp =
4148                                         bp->hwrm_cmd_resp_addr;
4149                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4150
4151                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4152
4153                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4154                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4155                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4156                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4157
4158                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4159                                         HWRM_CMD_TIMEOUT);
4160                 if (rc)
4161                         break;
4162
4163                 bp->grp_info[grp_idx].fw_grp_id =
4164                         le32_to_cpu(resp->ring_group_id);
4165         }
4166         mutex_unlock(&bp->hwrm_cmd_lock);
4167         return rc;
4168 }
4169
4170 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4171 {
4172         u16 i;
4173         u32 rc = 0;
4174         struct hwrm_ring_grp_free_input req = {0};
4175
4176         if (!bp->grp_info)
4177                 return 0;
4178
4179         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4180
4181         mutex_lock(&bp->hwrm_cmd_lock);
4182         for (i = 0; i < bp->cp_nr_rings; i++) {
4183                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4184                         continue;
4185                 req.ring_group_id =
4186                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4187
4188                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4189                                         HWRM_CMD_TIMEOUT);
4190                 if (rc)
4191                         break;
4192                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4193         }
4194         mutex_unlock(&bp->hwrm_cmd_lock);
4195         return rc;
4196 }
4197
4198 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4199                                     struct bnxt_ring_struct *ring,
4200                                     u32 ring_type, u32 map_index,
4201                                     u32 stats_ctx_id)
4202 {
4203         int rc = 0, err = 0;
4204         struct hwrm_ring_alloc_input req = {0};
4205         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4206         u16 ring_id;
4207
4208         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4209
4210         req.enables = 0;
4211         if (ring->nr_pages > 1) {
4212                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4213                 /* Page size is in log2 units */
4214                 req.page_size = BNXT_PAGE_SHIFT;
4215                 req.page_tbl_depth = 1;
4216         } else {
4217                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
4218         }
4219         req.fbo = 0;
4220         /* Association of ring index with doorbell index and MSIX number */
4221         req.logical_id = cpu_to_le16(map_index);
4222
4223         switch (ring_type) {
4224         case HWRM_RING_ALLOC_TX:
4225                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4226                 /* Association of transmit ring with completion ring */
4227                 req.cmpl_ring_id =
4228                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4229                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4230                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4231                 req.queue_id = cpu_to_le16(ring->queue_id);
4232                 break;
4233         case HWRM_RING_ALLOC_RX:
4234                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4235                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4236                 break;
4237         case HWRM_RING_ALLOC_AGG:
4238                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4239                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4240                 break;
4241         case HWRM_RING_ALLOC_CMPL:
4242                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4243                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4244                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4245                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4246                 break;
4247         default:
4248                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4249                            ring_type);
4250                 return -1;
4251         }
4252
4253         mutex_lock(&bp->hwrm_cmd_lock);
4254         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4255         err = le16_to_cpu(resp->error_code);
4256         ring_id = le16_to_cpu(resp->ring_id);
4257         mutex_unlock(&bp->hwrm_cmd_lock);
4258
4259         if (rc || err) {
4260                 switch (ring_type) {
4261                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4262                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4263                                    rc, err);
4264                         return -1;
4265
4266                 case RING_FREE_REQ_RING_TYPE_RX:
4267                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4268                                    rc, err);
4269                         return -1;
4270
4271                 case RING_FREE_REQ_RING_TYPE_TX:
4272                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4273                                    rc, err);
4274                         return -1;
4275
4276                 default:
4277                         netdev_err(bp->dev, "Invalid ring\n");
4278                         return -1;
4279                 }
4280         }
4281         ring->fw_ring_id = ring_id;
4282         return rc;
4283 }
4284
4285 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4286 {
4287         int rc;
4288
4289         if (BNXT_PF(bp)) {
4290                 struct hwrm_func_cfg_input req = {0};
4291
4292                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4293                 req.fid = cpu_to_le16(0xffff);
4294                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4295                 req.async_event_cr = cpu_to_le16(idx);
4296                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4297         } else {
4298                 struct hwrm_func_vf_cfg_input req = {0};
4299
4300                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4301                 req.enables =
4302                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4303                 req.async_event_cr = cpu_to_le16(idx);
4304                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4305         }
4306         return rc;
4307 }
4308
4309 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4310 {
4311         int i, rc = 0;
4312
4313         for (i = 0; i < bp->cp_nr_rings; i++) {
4314                 struct bnxt_napi *bnapi = bp->bnapi[i];
4315                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4316                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4317
4318                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4319                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4320                                               INVALID_STATS_CTX_ID);
4321                 if (rc)
4322                         goto err_out;
4323                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4324                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4325
4326                 if (!i) {
4327                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4328                         if (rc)
4329                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4330                 }
4331         }
4332
4333         for (i = 0; i < bp->tx_nr_rings; i++) {
4334                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4335                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4336                 u32 map_idx = txr->bnapi->index;
4337                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4338
4339                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4340                                               map_idx, fw_stats_ctx);
4341                 if (rc)
4342                         goto err_out;
4343                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4344         }
4345
4346         for (i = 0; i < bp->rx_nr_rings; i++) {
4347                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4348                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4349                 u32 map_idx = rxr->bnapi->index;
4350
4351                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4352                                               map_idx, INVALID_STATS_CTX_ID);
4353                 if (rc)
4354                         goto err_out;
4355                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4356                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4357                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4358         }
4359
4360         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4361                 for (i = 0; i < bp->rx_nr_rings; i++) {
4362                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4363                         struct bnxt_ring_struct *ring =
4364                                                 &rxr->rx_agg_ring_struct;
4365                         u32 grp_idx = rxr->bnapi->index;
4366                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4367
4368                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4369                                                       HWRM_RING_ALLOC_AGG,
4370                                                       map_idx,
4371                                                       INVALID_STATS_CTX_ID);
4372                         if (rc)
4373                                 goto err_out;
4374
4375                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4376                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4377                                rxr->rx_agg_doorbell);
4378                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4379                 }
4380         }
4381 err_out:
4382         return rc;
4383 }
4384
4385 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4386                                    struct bnxt_ring_struct *ring,
4387                                    u32 ring_type, int cmpl_ring_id)
4388 {
4389         int rc;
4390         struct hwrm_ring_free_input req = {0};
4391         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4392         u16 error_code;
4393
4394         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4395         req.ring_type = ring_type;
4396         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4397
4398         mutex_lock(&bp->hwrm_cmd_lock);
4399         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4400         error_code = le16_to_cpu(resp->error_code);
4401         mutex_unlock(&bp->hwrm_cmd_lock);
4402
4403         if (rc || error_code) {
4404                 switch (ring_type) {
4405                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4406                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4407                                    rc);
4408                         return rc;
4409                 case RING_FREE_REQ_RING_TYPE_RX:
4410                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4411                                    rc);
4412                         return rc;
4413                 case RING_FREE_REQ_RING_TYPE_TX:
4414                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4415                                    rc);
4416                         return rc;
4417                 default:
4418                         netdev_err(bp->dev, "Invalid ring\n");
4419                         return -1;
4420                 }
4421         }
4422         return 0;
4423 }
4424
4425 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4426 {
4427         int i;
4428
4429         if (!bp->bnapi)
4430                 return;
4431
4432         for (i = 0; i < bp->tx_nr_rings; i++) {
4433                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4434                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4435                 u32 grp_idx = txr->bnapi->index;
4436                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4437
4438                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4439                         hwrm_ring_free_send_msg(bp, ring,
4440                                                 RING_FREE_REQ_RING_TYPE_TX,
4441                                                 close_path ? cmpl_ring_id :
4442                                                 INVALID_HW_RING_ID);
4443                         ring->fw_ring_id = INVALID_HW_RING_ID;
4444                 }
4445         }
4446
4447         for (i = 0; i < bp->rx_nr_rings; i++) {
4448                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4449                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4450                 u32 grp_idx = rxr->bnapi->index;
4451                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4452
4453                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4454                         hwrm_ring_free_send_msg(bp, ring,
4455                                                 RING_FREE_REQ_RING_TYPE_RX,
4456                                                 close_path ? cmpl_ring_id :
4457                                                 INVALID_HW_RING_ID);
4458                         ring->fw_ring_id = INVALID_HW_RING_ID;
4459                         bp->grp_info[grp_idx].rx_fw_ring_id =
4460                                 INVALID_HW_RING_ID;
4461                 }
4462         }
4463
4464         for (i = 0; i < bp->rx_nr_rings; i++) {
4465                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4466                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4467                 u32 grp_idx = rxr->bnapi->index;
4468                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4469
4470                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4471                         hwrm_ring_free_send_msg(bp, ring,
4472                                                 RING_FREE_REQ_RING_TYPE_RX,
4473                                                 close_path ? cmpl_ring_id :
4474                                                 INVALID_HW_RING_ID);
4475                         ring->fw_ring_id = INVALID_HW_RING_ID;
4476                         bp->grp_info[grp_idx].agg_fw_ring_id =
4477                                 INVALID_HW_RING_ID;
4478                 }
4479         }
4480
4481         /* The completion rings are about to be freed.  After that the
4482          * IRQ doorbell will not work anymore.  So we need to disable
4483          * IRQ here.
4484          */
4485         bnxt_disable_int_sync(bp);
4486
4487         for (i = 0; i < bp->cp_nr_rings; i++) {
4488                 struct bnxt_napi *bnapi = bp->bnapi[i];
4489                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4490                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4491
4492                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4493                         hwrm_ring_free_send_msg(bp, ring,
4494                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4495                                                 INVALID_HW_RING_ID);
4496                         ring->fw_ring_id = INVALID_HW_RING_ID;
4497                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4498                 }
4499         }
4500 }
4501
4502 /* Caller must hold bp->hwrm_cmd_lock */
4503 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4504 {
4505         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4506         struct hwrm_func_qcfg_input req = {0};
4507         int rc;
4508
4509         if (bp->hwrm_spec_code < 0x10601)
4510                 return 0;
4511
4512         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4513         req.fid = cpu_to_le16(fid);
4514         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4515         if (!rc)
4516                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4517
4518         return rc;
4519 }
4520
4521 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4522 {
4523         struct hwrm_func_cfg_input req = {0};
4524         int rc;
4525
4526         if (bp->hwrm_spec_code < 0x10601)
4527                 return 0;
4528
4529         if (BNXT_VF(bp))
4530                 return 0;
4531
4532         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4533         req.fid = cpu_to_le16(0xffff);
4534         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4535         req.num_tx_rings = cpu_to_le16(*tx_rings);
4536         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4537         if (rc)
4538                 return rc;
4539
4540         mutex_lock(&bp->hwrm_cmd_lock);
4541         rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4542         mutex_unlock(&bp->hwrm_cmd_lock);
4543         if (!rc)
4544                 bp->tx_reserved_rings = *tx_rings;
4545         return rc;
4546 }
4547
4548 static int bnxt_hwrm_check_tx_rings(struct bnxt *bp, int tx_rings)
4549 {
4550         struct hwrm_func_cfg_input req = {0};
4551         int rc;
4552
4553         if (bp->hwrm_spec_code < 0x10801)
4554                 return 0;
4555
4556         if (BNXT_VF(bp))
4557                 return 0;
4558
4559         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4560         req.fid = cpu_to_le16(0xffff);
4561         req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST);
4562         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4563         req.num_tx_rings = cpu_to_le16(tx_rings);
4564         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4565         if (rc)
4566                 return -ENOMEM;
4567         return 0;
4568 }
4569
4570 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4571         u32 buf_tmrs, u16 flags,
4572         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4573 {
4574         req->flags = cpu_to_le16(flags);
4575         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4576         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4577         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4578         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4579         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4580         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4581         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4582         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4583 }
4584
4585 int bnxt_hwrm_set_coal(struct bnxt *bp)
4586 {
4587         int i, rc = 0;
4588         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4589                                                            req_tx = {0}, *req;
4590         u16 max_buf, max_buf_irq;
4591         u16 buf_tmr, buf_tmr_irq;
4592         u32 flags;
4593
4594         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4595                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4596         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4597                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4598
4599         /* Each rx completion (2 records) should be DMAed immediately.
4600          * DMA 1/4 of the completion buffers at a time.
4601          */
4602         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4603         /* max_buf must not be zero */
4604         max_buf = clamp_t(u16, max_buf, 1, 63);
4605         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4606         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4607         /* buf timer set to 1/4 of interrupt timer */
4608         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4609         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4610         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4611
4612         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4613
4614         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4615          * if coal_ticks is less than 25 us.
4616          */
4617         if (bp->rx_coal_ticks < 25)
4618                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4619
4620         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4621                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4622
4623         /* max_buf must not be zero */
4624         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4625         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4626         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4627         /* buf timer set to 1/4 of interrupt timer */
4628         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4629         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4630         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4631
4632         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4633         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4634                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4635
4636         mutex_lock(&bp->hwrm_cmd_lock);
4637         for (i = 0; i < bp->cp_nr_rings; i++) {
4638                 struct bnxt_napi *bnapi = bp->bnapi[i];
4639
4640                 req = &req_rx;
4641                 if (!bnapi->rx_ring)
4642                         req = &req_tx;
4643                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4644
4645                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4646                                         HWRM_CMD_TIMEOUT);
4647                 if (rc)
4648                         break;
4649         }
4650         mutex_unlock(&bp->hwrm_cmd_lock);
4651         return rc;
4652 }
4653
4654 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4655 {
4656         int rc = 0, i;
4657         struct hwrm_stat_ctx_free_input req = {0};
4658
4659         if (!bp->bnapi)
4660                 return 0;
4661
4662         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4663                 return 0;
4664
4665         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4666
4667         mutex_lock(&bp->hwrm_cmd_lock);
4668         for (i = 0; i < bp->cp_nr_rings; i++) {
4669                 struct bnxt_napi *bnapi = bp->bnapi[i];
4670                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4671
4672                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4673                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4674
4675                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4676                                                 HWRM_CMD_TIMEOUT);
4677                         if (rc)
4678                                 break;
4679
4680                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4681                 }
4682         }
4683         mutex_unlock(&bp->hwrm_cmd_lock);
4684         return rc;
4685 }
4686
4687 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4688 {
4689         int rc = 0, i;
4690         struct hwrm_stat_ctx_alloc_input req = {0};
4691         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4692
4693         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4694                 return 0;
4695
4696         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4697
4698         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4699
4700         mutex_lock(&bp->hwrm_cmd_lock);
4701         for (i = 0; i < bp->cp_nr_rings; i++) {
4702                 struct bnxt_napi *bnapi = bp->bnapi[i];
4703                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4704
4705                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4706
4707                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4708                                         HWRM_CMD_TIMEOUT);
4709                 if (rc)
4710                         break;
4711
4712                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4713
4714                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4715         }
4716         mutex_unlock(&bp->hwrm_cmd_lock);
4717         return rc;
4718 }
4719
4720 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4721 {
4722         struct hwrm_func_qcfg_input req = {0};
4723         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4724         u16 flags;
4725         int rc;
4726
4727         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4728         req.fid = cpu_to_le16(0xffff);
4729         mutex_lock(&bp->hwrm_cmd_lock);
4730         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4731         if (rc)
4732                 goto func_qcfg_exit;
4733
4734 #ifdef CONFIG_BNXT_SRIOV
4735         if (BNXT_VF(bp)) {
4736                 struct bnxt_vf_info *vf = &bp->vf;
4737
4738                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4739         }
4740 #endif
4741         flags = le16_to_cpu(resp->flags);
4742         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4743                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
4744                 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4745                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
4746                         bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
4747         }
4748         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
4749                 bp->flags |= BNXT_FLAG_MULTI_HOST;
4750
4751         switch (resp->port_partition_type) {
4752         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4753         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4754         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4755                 bp->port_partition_type = resp->port_partition_type;
4756                 break;
4757         }
4758         if (bp->hwrm_spec_code < 0x10707 ||
4759             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
4760                 bp->br_mode = BRIDGE_MODE_VEB;
4761         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
4762                 bp->br_mode = BRIDGE_MODE_VEPA;
4763         else
4764                 bp->br_mode = BRIDGE_MODE_UNDEF;
4765
4766 func_qcfg_exit:
4767         mutex_unlock(&bp->hwrm_cmd_lock);
4768         return rc;
4769 }
4770
4771 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4772 {
4773         int rc = 0;
4774         struct hwrm_func_qcaps_input req = {0};
4775         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4776
4777         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4778         req.fid = cpu_to_le16(0xffff);
4779
4780         mutex_lock(&bp->hwrm_cmd_lock);
4781         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4782         if (rc)
4783                 goto hwrm_func_qcaps_exit;
4784
4785         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4786                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4787         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4788                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4789
4790         bp->tx_push_thresh = 0;
4791         if (resp->flags &
4792             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4793                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4794
4795         if (BNXT_PF(bp)) {
4796                 struct bnxt_pf_info *pf = &bp->pf;
4797
4798                 pf->fw_fid = le16_to_cpu(resp->fid);
4799                 pf->port_id = le16_to_cpu(resp->port_id);
4800                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4801                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4802                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4803                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4804                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4805                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4806                 if (!pf->max_hw_ring_grps)
4807                         pf->max_hw_ring_grps = pf->max_tx_rings;
4808                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4809                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4810                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4811                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4812                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4813                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4814                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4815                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4816                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4817                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4818                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4819                 if (resp->flags &
4820                     cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4821                         bp->flags |= BNXT_FLAG_WOL_CAP;
4822         } else {
4823 #ifdef CONFIG_BNXT_SRIOV
4824                 struct bnxt_vf_info *vf = &bp->vf;
4825
4826                 vf->fw_fid = le16_to_cpu(resp->fid);
4827
4828                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4829                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4830                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4831                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4832                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4833                 if (!vf->max_hw_ring_grps)
4834                         vf->max_hw_ring_grps = vf->max_tx_rings;
4835                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4836                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4837                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4838
4839                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4840 #endif
4841         }
4842
4843 hwrm_func_qcaps_exit:
4844         mutex_unlock(&bp->hwrm_cmd_lock);
4845         return rc;
4846 }
4847
4848 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4849 {
4850         struct hwrm_func_reset_input req = {0};
4851
4852         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4853         req.enables = 0;
4854
4855         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4856 }
4857
4858 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4859 {
4860         int rc = 0;
4861         struct hwrm_queue_qportcfg_input req = {0};
4862         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4863         u8 i, *qptr;
4864
4865         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4866
4867         mutex_lock(&bp->hwrm_cmd_lock);
4868         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4869         if (rc)
4870                 goto qportcfg_exit;
4871
4872         if (!resp->max_configurable_queues) {
4873                 rc = -EINVAL;
4874                 goto qportcfg_exit;
4875         }
4876         bp->max_tc = resp->max_configurable_queues;
4877         bp->max_lltc = resp->max_configurable_lossless_queues;
4878         if (bp->max_tc > BNXT_MAX_QUEUE)
4879                 bp->max_tc = BNXT_MAX_QUEUE;
4880
4881         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4882                 bp->max_tc = 1;
4883
4884         if (bp->max_lltc > bp->max_tc)
4885                 bp->max_lltc = bp->max_tc;
4886
4887         qptr = &resp->queue_id0;
4888         for (i = 0; i < bp->max_tc; i++) {
4889                 bp->q_info[i].queue_id = *qptr++;
4890                 bp->q_info[i].queue_profile = *qptr++;
4891         }
4892
4893 qportcfg_exit:
4894         mutex_unlock(&bp->hwrm_cmd_lock);
4895         return rc;
4896 }
4897
4898 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4899 {
4900         int rc;
4901         struct hwrm_ver_get_input req = {0};
4902         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4903         u32 dev_caps_cfg;
4904
4905         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4906         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4907         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4908         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4909         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4910         mutex_lock(&bp->hwrm_cmd_lock);
4911         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4912         if (rc)
4913                 goto hwrm_ver_get_exit;
4914
4915         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4916
4917         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4918                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4919         if (resp->hwrm_intf_maj < 1) {
4920                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4921                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4922                             resp->hwrm_intf_upd);
4923                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4924         }
4925         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4926                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4927                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4928
4929         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4930         if (!bp->hwrm_cmd_timeout)
4931                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4932
4933         if (resp->hwrm_intf_maj >= 1)
4934                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4935
4936         bp->chip_num = le16_to_cpu(resp->chip_num);
4937         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4938             !resp->chip_metal)
4939                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4940
4941         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
4942         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
4943             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
4944                 bp->flags |= BNXT_FLAG_SHORT_CMD;
4945
4946 hwrm_ver_get_exit:
4947         mutex_unlock(&bp->hwrm_cmd_lock);
4948         return rc;
4949 }
4950
4951 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4952 {
4953 #if IS_ENABLED(CONFIG_RTC_LIB)
4954         struct hwrm_fw_set_time_input req = {0};
4955         struct rtc_time tm;
4956         struct timeval tv;
4957
4958         if (bp->hwrm_spec_code < 0x10400)
4959                 return -EOPNOTSUPP;
4960
4961         do_gettimeofday(&tv);
4962         rtc_time_to_tm(tv.tv_sec, &tm);
4963         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4964         req.year = cpu_to_le16(1900 + tm.tm_year);
4965         req.month = 1 + tm.tm_mon;
4966         req.day = tm.tm_mday;
4967         req.hour = tm.tm_hour;
4968         req.minute = tm.tm_min;
4969         req.second = tm.tm_sec;
4970         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4971 #else
4972         return -EOPNOTSUPP;
4973 #endif
4974 }
4975
4976 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4977 {
4978         int rc;
4979         struct bnxt_pf_info *pf = &bp->pf;
4980         struct hwrm_port_qstats_input req = {0};
4981
4982         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4983                 return 0;
4984
4985         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4986         req.port_id = cpu_to_le16(pf->port_id);
4987         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4988         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4989         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4990         return rc;
4991 }
4992
4993 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4994 {
4995         if (bp->vxlan_port_cnt) {
4996                 bnxt_hwrm_tunnel_dst_port_free(
4997                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4998         }
4999         bp->vxlan_port_cnt = 0;
5000         if (bp->nge_port_cnt) {
5001                 bnxt_hwrm_tunnel_dst_port_free(
5002                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5003         }
5004         bp->nge_port_cnt = 0;
5005 }
5006
5007 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5008 {
5009         int rc, i;
5010         u32 tpa_flags = 0;
5011
5012         if (set_tpa)
5013                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5014         for (i = 0; i < bp->nr_vnics; i++) {
5015                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5016                 if (rc) {
5017                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5018                                    i, rc);
5019                         return rc;
5020                 }
5021         }
5022         return 0;
5023 }
5024
5025 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5026 {
5027         int i;
5028
5029         for (i = 0; i < bp->nr_vnics; i++)
5030                 bnxt_hwrm_vnic_set_rss(bp, i, false);
5031 }
5032
5033 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5034                                     bool irq_re_init)
5035 {
5036         if (bp->vnic_info) {
5037                 bnxt_hwrm_clear_vnic_filter(bp);
5038                 /* clear all RSS setting before free vnic ctx */
5039                 bnxt_hwrm_clear_vnic_rss(bp);
5040                 bnxt_hwrm_vnic_ctx_free(bp);
5041                 /* before free the vnic, undo the vnic tpa settings */
5042                 if (bp->flags & BNXT_FLAG_TPA)
5043                         bnxt_set_tpa(bp, false);
5044                 bnxt_hwrm_vnic_free(bp);
5045         }
5046         bnxt_hwrm_ring_free(bp, close_path);
5047         bnxt_hwrm_ring_grp_free(bp);
5048         if (irq_re_init) {
5049                 bnxt_hwrm_stat_ctx_free(bp);
5050                 bnxt_hwrm_free_tunnel_ports(bp);
5051         }
5052 }
5053
5054 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5055 {
5056         struct hwrm_func_cfg_input req = {0};
5057         int rc;
5058
5059         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5060         req.fid = cpu_to_le16(0xffff);
5061         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5062         if (br_mode == BRIDGE_MODE_VEB)
5063                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5064         else if (br_mode == BRIDGE_MODE_VEPA)
5065                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5066         else
5067                 return -EINVAL;
5068         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5069         if (rc)
5070                 rc = -EIO;
5071         return rc;
5072 }
5073
5074 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5075 {
5076         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5077         int rc;
5078
5079         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5080                 goto skip_rss_ctx;
5081
5082         /* allocate context for vnic */
5083         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5084         if (rc) {
5085                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5086                            vnic_id, rc);
5087                 goto vnic_setup_err;
5088         }
5089         bp->rsscos_nr_ctxs++;
5090
5091         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5092                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5093                 if (rc) {
5094                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5095                                    vnic_id, rc);
5096                         goto vnic_setup_err;
5097                 }
5098                 bp->rsscos_nr_ctxs++;
5099         }
5100
5101 skip_rss_ctx:
5102         /* configure default vnic, ring grp */
5103         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5104         if (rc) {
5105                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5106                            vnic_id, rc);
5107                 goto vnic_setup_err;
5108         }
5109
5110         /* Enable RSS hashing on vnic */
5111         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5112         if (rc) {
5113                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5114                            vnic_id, rc);
5115                 goto vnic_setup_err;
5116         }
5117
5118         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5119                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5120                 if (rc) {
5121                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5122                                    vnic_id, rc);
5123                 }
5124         }
5125
5126 vnic_setup_err:
5127         return rc;
5128 }
5129
5130 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5131 {
5132 #ifdef CONFIG_RFS_ACCEL
5133         int i, rc = 0;
5134
5135         for (i = 0; i < bp->rx_nr_rings; i++) {
5136                 struct bnxt_vnic_info *vnic;
5137                 u16 vnic_id = i + 1;
5138                 u16 ring_id = i;
5139
5140                 if (vnic_id >= bp->nr_vnics)
5141                         break;
5142
5143                 vnic = &bp->vnic_info[vnic_id];
5144                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5145                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5146                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5147                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5148                 if (rc) {
5149                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5150                                    vnic_id, rc);
5151                         break;
5152                 }
5153                 rc = bnxt_setup_vnic(bp, vnic_id);
5154                 if (rc)
5155                         break;
5156         }
5157         return rc;
5158 #else
5159         return 0;
5160 #endif
5161 }
5162
5163 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5164 static bool bnxt_promisc_ok(struct bnxt *bp)
5165 {
5166 #ifdef CONFIG_BNXT_SRIOV
5167         if (BNXT_VF(bp) && !bp->vf.vlan)
5168                 return false;
5169 #endif
5170         return true;
5171 }
5172
5173 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5174 {
5175         unsigned int rc = 0;
5176
5177         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5178         if (rc) {
5179                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5180                            rc);
5181                 return rc;
5182         }
5183
5184         rc = bnxt_hwrm_vnic_cfg(bp, 1);
5185         if (rc) {
5186                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5187                            rc);
5188                 return rc;
5189         }
5190         return rc;
5191 }
5192
5193 static int bnxt_cfg_rx_mode(struct bnxt *);
5194 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5195
5196 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5197 {
5198         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5199         int rc = 0;
5200         unsigned int rx_nr_rings = bp->rx_nr_rings;
5201
5202         if (irq_re_init) {
5203                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5204                 if (rc) {
5205                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5206                                    rc);
5207                         goto err_out;
5208                 }
5209                 if (bp->tx_reserved_rings != bp->tx_nr_rings) {
5210                         int tx = bp->tx_nr_rings;
5211
5212                         if (bnxt_hwrm_reserve_tx_rings(bp, &tx) ||
5213                             tx < bp->tx_nr_rings) {
5214                                 rc = -ENOMEM;
5215                                 goto err_out;
5216                         }
5217                 }
5218         }
5219
5220         rc = bnxt_hwrm_ring_alloc(bp);
5221         if (rc) {
5222                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5223                 goto err_out;
5224         }
5225
5226         rc = bnxt_hwrm_ring_grp_alloc(bp);
5227         if (rc) {
5228                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5229                 goto err_out;
5230         }
5231
5232         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5233                 rx_nr_rings--;
5234
5235         /* default vnic 0 */
5236         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5237         if (rc) {
5238                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5239                 goto err_out;
5240         }
5241
5242         rc = bnxt_setup_vnic(bp, 0);
5243         if (rc)
5244                 goto err_out;
5245
5246         if (bp->flags & BNXT_FLAG_RFS) {
5247                 rc = bnxt_alloc_rfs_vnics(bp);
5248                 if (rc)
5249                         goto err_out;
5250         }
5251
5252         if (bp->flags & BNXT_FLAG_TPA) {
5253                 rc = bnxt_set_tpa(bp, true);
5254                 if (rc)
5255                         goto err_out;
5256         }
5257
5258         if (BNXT_VF(bp))
5259                 bnxt_update_vf_mac(bp);
5260
5261         /* Filter for default vnic 0 */
5262         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5263         if (rc) {
5264                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5265                 goto err_out;
5266         }
5267         vnic->uc_filter_count = 1;
5268
5269         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5270
5271         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5272                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5273
5274         if (bp->dev->flags & IFF_ALLMULTI) {
5275                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5276                 vnic->mc_list_count = 0;
5277         } else {
5278                 u32 mask = 0;
5279
5280                 bnxt_mc_list_updated(bp, &mask);
5281                 vnic->rx_mask |= mask;
5282         }
5283
5284         rc = bnxt_cfg_rx_mode(bp);
5285         if (rc)
5286                 goto err_out;
5287
5288         rc = bnxt_hwrm_set_coal(bp);
5289         if (rc)
5290                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5291                                 rc);
5292
5293         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5294                 rc = bnxt_setup_nitroa0_vnic(bp);
5295                 if (rc)
5296                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5297                                    rc);
5298         }
5299
5300         if (BNXT_VF(bp)) {
5301                 bnxt_hwrm_func_qcfg(bp);
5302                 netdev_update_features(bp->dev);
5303         }
5304
5305         return 0;
5306
5307 err_out:
5308         bnxt_hwrm_resource_free(bp, 0, true);
5309
5310         return rc;
5311 }
5312
5313 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5314 {
5315         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5316         return 0;
5317 }
5318
5319 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5320 {
5321         bnxt_init_cp_rings(bp);
5322         bnxt_init_rx_rings(bp);
5323         bnxt_init_tx_rings(bp);
5324         bnxt_init_ring_grps(bp, irq_re_init);
5325         bnxt_init_vnics(bp);
5326
5327         return bnxt_init_chip(bp, irq_re_init);
5328 }
5329
5330 static int bnxt_set_real_num_queues(struct bnxt *bp)
5331 {
5332         int rc;
5333         struct net_device *dev = bp->dev;
5334
5335         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5336                                           bp->tx_nr_rings_xdp);
5337         if (rc)
5338                 return rc;
5339
5340         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5341         if (rc)
5342                 return rc;
5343
5344 #ifdef CONFIG_RFS_ACCEL
5345         if (bp->flags & BNXT_FLAG_RFS)
5346                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5347 #endif
5348
5349         return rc;
5350 }
5351
5352 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5353                            bool shared)
5354 {
5355         int _rx = *rx, _tx = *tx;
5356
5357         if (shared) {
5358                 *rx = min_t(int, _rx, max);
5359                 *tx = min_t(int, _tx, max);
5360         } else {
5361                 if (max < 2)
5362                         return -ENOMEM;
5363
5364                 while (_rx + _tx > max) {
5365                         if (_rx > _tx && _rx > 1)
5366                                 _rx--;
5367                         else if (_tx > 1)
5368                                 _tx--;
5369                 }
5370                 *rx = _rx;
5371                 *tx = _tx;
5372         }
5373         return 0;
5374 }
5375
5376 static void bnxt_setup_msix(struct bnxt *bp)
5377 {
5378         const int len = sizeof(bp->irq_tbl[0].name);
5379         struct net_device *dev = bp->dev;
5380         int tcs, i;
5381
5382         tcs = netdev_get_num_tc(dev);
5383         if (tcs) {
5384                 int i, off, count;
5385
5386                 for (i = 0; i < tcs; i++) {
5387                         count = bp->tx_nr_rings_per_tc;
5388                         off = i * count;
5389                         netdev_set_tc_queue(dev, i, count, off);
5390                 }
5391         }
5392
5393         for (i = 0; i < bp->cp_nr_rings; i++) {
5394                 char *attr;
5395
5396                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5397                         attr = "TxRx";
5398                 else if (i < bp->rx_nr_rings)
5399                         attr = "rx";
5400                 else
5401                         attr = "tx";
5402
5403                 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5404                          i);
5405                 bp->irq_tbl[i].handler = bnxt_msix;
5406         }
5407 }
5408
5409 static void bnxt_setup_inta(struct bnxt *bp)
5410 {
5411         const int len = sizeof(bp->irq_tbl[0].name);
5412
5413         if (netdev_get_num_tc(bp->dev))
5414                 netdev_reset_tc(bp->dev);
5415
5416         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5417                  0);
5418         bp->irq_tbl[0].handler = bnxt_inta;
5419 }
5420
5421 static int bnxt_setup_int_mode(struct bnxt *bp)
5422 {
5423         int rc;
5424
5425         if (bp->flags & BNXT_FLAG_USING_MSIX)
5426                 bnxt_setup_msix(bp);
5427         else
5428                 bnxt_setup_inta(bp);
5429
5430         rc = bnxt_set_real_num_queues(bp);
5431         return rc;
5432 }
5433
5434 #ifdef CONFIG_RFS_ACCEL
5435 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5436 {
5437 #if defined(CONFIG_BNXT_SRIOV)
5438         if (BNXT_VF(bp))
5439                 return bp->vf.max_rsscos_ctxs;
5440 #endif
5441         return bp->pf.max_rsscos_ctxs;
5442 }
5443
5444 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5445 {
5446 #if defined(CONFIG_BNXT_SRIOV)
5447         if (BNXT_VF(bp))
5448                 return bp->vf.max_vnics;
5449 #endif
5450         return bp->pf.max_vnics;
5451 }
5452 #endif
5453
5454 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5455 {
5456 #if defined(CONFIG_BNXT_SRIOV)
5457         if (BNXT_VF(bp))
5458                 return bp->vf.max_stat_ctxs;
5459 #endif
5460         return bp->pf.max_stat_ctxs;
5461 }
5462
5463 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5464 {
5465 #if defined(CONFIG_BNXT_SRIOV)
5466         if (BNXT_VF(bp))
5467                 bp->vf.max_stat_ctxs = max;
5468         else
5469 #endif
5470                 bp->pf.max_stat_ctxs = max;
5471 }
5472
5473 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5474 {
5475 #if defined(CONFIG_BNXT_SRIOV)
5476         if (BNXT_VF(bp))
5477                 return bp->vf.max_cp_rings;
5478 #endif
5479         return bp->pf.max_cp_rings;
5480 }
5481
5482 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5483 {
5484 #if defined(CONFIG_BNXT_SRIOV)
5485         if (BNXT_VF(bp))
5486                 bp->vf.max_cp_rings = max;
5487         else
5488 #endif
5489                 bp->pf.max_cp_rings = max;
5490 }
5491
5492 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5493 {
5494 #if defined(CONFIG_BNXT_SRIOV)
5495         if (BNXT_VF(bp))
5496                 return min_t(unsigned int, bp->vf.max_irqs,
5497                              bp->vf.max_cp_rings);
5498 #endif
5499         return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5500 }
5501
5502 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5503 {
5504 #if defined(CONFIG_BNXT_SRIOV)
5505         if (BNXT_VF(bp))
5506                 bp->vf.max_irqs = max_irqs;
5507         else
5508 #endif
5509                 bp->pf.max_irqs = max_irqs;
5510 }
5511
5512 static int bnxt_init_msix(struct bnxt *bp)
5513 {
5514         int i, total_vecs, rc = 0, min = 1;
5515         struct msix_entry *msix_ent;
5516
5517         total_vecs = bnxt_get_max_func_irqs(bp);
5518         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5519         if (!msix_ent)
5520                 return -ENOMEM;
5521
5522         for (i = 0; i < total_vecs; i++) {
5523                 msix_ent[i].entry = i;
5524                 msix_ent[i].vector = 0;
5525         }
5526
5527         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5528                 min = 2;
5529
5530         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5531         if (total_vecs < 0) {
5532                 rc = -ENODEV;
5533                 goto msix_setup_exit;
5534         }
5535
5536         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5537         if (bp->irq_tbl) {
5538                 for (i = 0; i < total_vecs; i++)
5539                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5540
5541                 bp->total_irqs = total_vecs;
5542                 /* Trim rings based upon num of vectors allocated */
5543                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5544                                      total_vecs, min == 1);
5545                 if (rc)
5546                         goto msix_setup_exit;
5547
5548                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5549                 bp->cp_nr_rings = (min == 1) ?
5550                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5551                                   bp->tx_nr_rings + bp->rx_nr_rings;
5552
5553         } else {
5554                 rc = -ENOMEM;
5555                 goto msix_setup_exit;
5556         }
5557         bp->flags |= BNXT_FLAG_USING_MSIX;
5558         kfree(msix_ent);
5559         return 0;
5560
5561 msix_setup_exit:
5562         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5563         kfree(bp->irq_tbl);
5564         bp->irq_tbl = NULL;
5565         pci_disable_msix(bp->pdev);
5566         kfree(msix_ent);
5567         return rc;
5568 }
5569
5570 static int bnxt_init_inta(struct bnxt *bp)
5571 {
5572         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5573         if (!bp->irq_tbl)
5574                 return -ENOMEM;
5575
5576         bp->total_irqs = 1;
5577         bp->rx_nr_rings = 1;
5578         bp->tx_nr_rings = 1;
5579         bp->cp_nr_rings = 1;
5580         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5581         bp->flags |= BNXT_FLAG_SHARED_RINGS;
5582         bp->irq_tbl[0].vector = bp->pdev->irq;
5583         return 0;
5584 }
5585
5586 static int bnxt_init_int_mode(struct bnxt *bp)
5587 {
5588         int rc = 0;
5589
5590         if (bp->flags & BNXT_FLAG_MSIX_CAP)
5591                 rc = bnxt_init_msix(bp);
5592
5593         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5594                 /* fallback to INTA */
5595                 rc = bnxt_init_inta(bp);
5596         }
5597         return rc;
5598 }
5599
5600 static void bnxt_clear_int_mode(struct bnxt *bp)
5601 {
5602         if (bp->flags & BNXT_FLAG_USING_MSIX)
5603                 pci_disable_msix(bp->pdev);
5604
5605         kfree(bp->irq_tbl);
5606         bp->irq_tbl = NULL;
5607         bp->flags &= ~BNXT_FLAG_USING_MSIX;
5608 }
5609
5610 static void bnxt_free_irq(struct bnxt *bp)
5611 {
5612         struct bnxt_irq *irq;
5613         int i;
5614
5615 #ifdef CONFIG_RFS_ACCEL
5616         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5617         bp->dev->rx_cpu_rmap = NULL;
5618 #endif
5619         if (!bp->irq_tbl)
5620                 return;
5621
5622         for (i = 0; i < bp->cp_nr_rings; i++) {
5623                 irq = &bp->irq_tbl[i];
5624                 if (irq->requested) {
5625                         if (irq->have_cpumask) {
5626                                 irq_set_affinity_hint(irq->vector, NULL);
5627                                 free_cpumask_var(irq->cpu_mask);
5628                                 irq->have_cpumask = 0;
5629                         }
5630                         free_irq(irq->vector, bp->bnapi[i]);
5631                 }
5632
5633                 irq->requested = 0;
5634         }
5635 }
5636
5637 static int bnxt_request_irq(struct bnxt *bp)
5638 {
5639         int i, j, rc = 0;
5640         unsigned long flags = 0;
5641 #ifdef CONFIG_RFS_ACCEL
5642         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5643 #endif
5644
5645         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5646                 flags = IRQF_SHARED;
5647
5648         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5649                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5650 #ifdef CONFIG_RFS_ACCEL
5651                 if (rmap && bp->bnapi[i]->rx_ring) {
5652                         rc = irq_cpu_rmap_add(rmap, irq->vector);
5653                         if (rc)
5654                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5655                                             j);
5656                         j++;
5657                 }
5658 #endif
5659                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5660                                  bp->bnapi[i]);
5661                 if (rc)
5662                         break;
5663
5664                 irq->requested = 1;
5665
5666                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
5667                         int numa_node = dev_to_node(&bp->pdev->dev);
5668
5669                         irq->have_cpumask = 1;
5670                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
5671                                         irq->cpu_mask);
5672                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
5673                         if (rc) {
5674                                 netdev_warn(bp->dev,
5675                                             "Set affinity failed, IRQ = %d\n",
5676                                             irq->vector);
5677                                 break;
5678                         }
5679                 }
5680         }
5681         return rc;
5682 }
5683
5684 static void bnxt_del_napi(struct bnxt *bp)
5685 {
5686         int i;
5687
5688         if (!bp->bnapi)
5689                 return;
5690
5691         for (i = 0; i < bp->cp_nr_rings; i++) {
5692                 struct bnxt_napi *bnapi = bp->bnapi[i];
5693
5694                 napi_hash_del(&bnapi->napi);
5695                 netif_napi_del(&bnapi->napi);
5696         }
5697         /* We called napi_hash_del() before netif_napi_del(), we need
5698          * to respect an RCU grace period before freeing napi structures.
5699          */
5700         synchronize_net();
5701 }
5702
5703 static void bnxt_init_napi(struct bnxt *bp)
5704 {
5705         int i;
5706         unsigned int cp_nr_rings = bp->cp_nr_rings;
5707         struct bnxt_napi *bnapi;
5708
5709         if (bp->flags & BNXT_FLAG_USING_MSIX) {
5710                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5711                         cp_nr_rings--;
5712                 for (i = 0; i < cp_nr_rings; i++) {
5713                         bnapi = bp->bnapi[i];
5714                         netif_napi_add(bp->dev, &bnapi->napi,
5715                                        bnxt_poll, 64);
5716                 }
5717                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5718                         bnapi = bp->bnapi[cp_nr_rings];
5719                         netif_napi_add(bp->dev, &bnapi->napi,
5720                                        bnxt_poll_nitroa0, 64);
5721                 }
5722         } else {
5723                 bnapi = bp->bnapi[0];
5724                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5725         }
5726 }
5727
5728 static void bnxt_disable_napi(struct bnxt *bp)
5729 {
5730         int i;
5731
5732         if (!bp->bnapi)
5733                 return;
5734
5735         for (i = 0; i < bp->cp_nr_rings; i++)
5736                 napi_disable(&bp->bnapi[i]->napi);
5737 }
5738
5739 static void bnxt_enable_napi(struct bnxt *bp)
5740 {
5741         int i;
5742
5743         for (i = 0; i < bp->cp_nr_rings; i++) {
5744                 bp->bnapi[i]->in_reset = false;
5745                 napi_enable(&bp->bnapi[i]->napi);
5746         }
5747 }
5748
5749 void bnxt_tx_disable(struct bnxt *bp)
5750 {
5751         int i;
5752         struct bnxt_tx_ring_info *txr;
5753
5754         if (bp->tx_ring) {
5755                 for (i = 0; i < bp->tx_nr_rings; i++) {
5756                         txr = &bp->tx_ring[i];
5757                         WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
5758                 }
5759         }
5760         /* Make sure napi polls see @dev_state change */
5761         synchronize_net();
5762         /* Drop carrier first to prevent TX timeout */
5763         netif_carrier_off(bp->dev);
5764         /* Stop all TX queues */
5765         netif_tx_disable(bp->dev);
5766 }
5767
5768 void bnxt_tx_enable(struct bnxt *bp)
5769 {
5770         int i;
5771         struct bnxt_tx_ring_info *txr;
5772
5773         for (i = 0; i < bp->tx_nr_rings; i++) {
5774                 txr = &bp->tx_ring[i];
5775                 WRITE_ONCE(txr->dev_state, 0);
5776         }
5777         /* Make sure napi polls see @dev_state change */
5778         synchronize_net();
5779         netif_tx_wake_all_queues(bp->dev);
5780         if (bp->link_info.link_up)
5781                 netif_carrier_on(bp->dev);
5782 }
5783
5784 static void bnxt_report_link(struct bnxt *bp)
5785 {
5786         if (bp->link_info.link_up) {
5787                 const char *duplex;
5788                 const char *flow_ctrl;
5789                 u32 speed;
5790                 u16 fec;
5791
5792                 netif_carrier_on(bp->dev);
5793                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5794                 if (speed == SPEED_UNKNOWN) {
5795                         netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
5796                         return;
5797                 }
5798                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5799                         duplex = "full";
5800                 else
5801                         duplex = "half";
5802                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5803                         flow_ctrl = "ON - receive & transmit";
5804                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5805                         flow_ctrl = "ON - transmit";
5806                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5807                         flow_ctrl = "ON - receive";
5808                 else
5809                         flow_ctrl = "none";
5810                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5811                             speed, duplex, flow_ctrl);
5812                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5813                         netdev_info(bp->dev, "EEE is %s\n",
5814                                     bp->eee.eee_active ? "active" :
5815                                                          "not active");
5816                 fec = bp->link_info.fec_cfg;
5817                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5818                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5819                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5820                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5821                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5822         } else {
5823                 netif_carrier_off(bp->dev);
5824                 netdev_err(bp->dev, "NIC Link is Down\n");
5825         }
5826 }
5827
5828 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5829 {
5830         int rc = 0;
5831         struct hwrm_port_phy_qcaps_input req = {0};
5832         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5833         struct bnxt_link_info *link_info = &bp->link_info;
5834
5835         if (bp->hwrm_spec_code < 0x10201)
5836                 return 0;
5837
5838         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5839
5840         mutex_lock(&bp->hwrm_cmd_lock);
5841         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5842         if (rc)
5843                 goto hwrm_phy_qcaps_exit;
5844
5845         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
5846                 struct ethtool_eee *eee = &bp->eee;
5847                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5848
5849                 bp->flags |= BNXT_FLAG_EEE_CAP;
5850                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5851                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5852                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5853                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5854                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5855         }
5856         if (resp->supported_speeds_auto_mode)
5857                 link_info->support_auto_speeds =
5858                         le16_to_cpu(resp->supported_speeds_auto_mode);
5859
5860         bp->port_count = resp->port_cnt;
5861
5862 hwrm_phy_qcaps_exit:
5863         mutex_unlock(&bp->hwrm_cmd_lock);
5864         return rc;
5865 }
5866
5867 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5868 {
5869         int rc = 0;
5870         struct bnxt_link_info *link_info = &bp->link_info;
5871         struct hwrm_port_phy_qcfg_input req = {0};
5872         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5873         u8 link_up = link_info->link_up;
5874         u16 diff;
5875
5876         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5877
5878         mutex_lock(&bp->hwrm_cmd_lock);
5879         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5880         if (rc) {
5881                 mutex_unlock(&bp->hwrm_cmd_lock);
5882                 return rc;
5883         }
5884
5885         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5886         link_info->phy_link_status = resp->link;
5887         link_info->duplex = resp->duplex_cfg;
5888         if (bp->hwrm_spec_code >= 0x10800)
5889                 link_info->duplex = resp->duplex_state;
5890         link_info->pause = resp->pause;
5891         link_info->auto_mode = resp->auto_mode;
5892         link_info->auto_pause_setting = resp->auto_pause;
5893         link_info->lp_pause = resp->link_partner_adv_pause;
5894         link_info->force_pause_setting = resp->force_pause;
5895         link_info->duplex_setting = resp->duplex_cfg;
5896         if (link_info->phy_link_status == BNXT_LINK_LINK)
5897                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5898         else
5899                 link_info->link_speed = 0;
5900         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5901         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5902         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5903         link_info->lp_auto_link_speeds =
5904                 le16_to_cpu(resp->link_partner_adv_speeds);
5905         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5906         link_info->phy_ver[0] = resp->phy_maj;
5907         link_info->phy_ver[1] = resp->phy_min;
5908         link_info->phy_ver[2] = resp->phy_bld;
5909         link_info->media_type = resp->media_type;
5910         link_info->phy_type = resp->phy_type;
5911         link_info->transceiver = resp->xcvr_pkg_type;
5912         link_info->phy_addr = resp->eee_config_phy_addr &
5913                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5914         link_info->module_status = resp->module_status;
5915
5916         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5917                 struct ethtool_eee *eee = &bp->eee;
5918                 u16 fw_speeds;
5919
5920                 eee->eee_active = 0;
5921                 if (resp->eee_config_phy_addr &
5922                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5923                         eee->eee_active = 1;
5924                         fw_speeds = le16_to_cpu(
5925                                 resp->link_partner_adv_eee_link_speed_mask);
5926                         eee->lp_advertised =
5927                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5928                 }
5929
5930                 /* Pull initial EEE config */
5931                 if (!chng_link_state) {
5932                         if (resp->eee_config_phy_addr &
5933                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5934                                 eee->eee_enabled = 1;
5935
5936                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5937                         eee->advertised =
5938                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5939
5940                         if (resp->eee_config_phy_addr &
5941                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5942                                 __le32 tmr;
5943
5944                                 eee->tx_lpi_enabled = 1;
5945                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5946                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5947                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5948                         }
5949                 }
5950         }
5951
5952         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5953         if (bp->hwrm_spec_code >= 0x10504)
5954                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5955
5956         /* TODO: need to add more logic to report VF link */
5957         if (chng_link_state) {
5958                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5959                         link_info->link_up = 1;
5960                 else
5961                         link_info->link_up = 0;
5962                 if (link_up != link_info->link_up)
5963                         bnxt_report_link(bp);
5964         } else {
5965                 /* alwasy link down if not require to update link state */
5966                 link_info->link_up = 0;
5967         }
5968         mutex_unlock(&bp->hwrm_cmd_lock);
5969
5970         if (!BNXT_SINGLE_PF(bp))
5971                 return 0;
5972
5973         diff = link_info->support_auto_speeds ^ link_info->advertising;
5974         if ((link_info->support_auto_speeds | diff) !=
5975             link_info->support_auto_speeds) {
5976                 /* An advertised speed is no longer supported, so we need to
5977                  * update the advertisement settings.  Caller holds RTNL
5978                  * so we can modify link settings.
5979                  */
5980                 link_info->advertising = link_info->support_auto_speeds;
5981                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5982                         bnxt_hwrm_set_link_setting(bp, true, false);
5983         }
5984         return 0;
5985 }
5986
5987 static void bnxt_get_port_module_status(struct bnxt *bp)
5988 {
5989         struct bnxt_link_info *link_info = &bp->link_info;
5990         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5991         u8 module_status;
5992
5993         if (bnxt_update_link(bp, true))
5994                 return;
5995
5996         module_status = link_info->module_status;
5997         switch (module_status) {
5998         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5999         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6000         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6001                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6002                             bp->pf.port_id);
6003                 if (bp->hwrm_spec_code >= 0x10201) {
6004                         netdev_warn(bp->dev, "Module part number %s\n",
6005                                     resp->phy_vendor_partnumber);
6006                 }
6007                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6008                         netdev_warn(bp->dev, "TX is disabled\n");
6009                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6010                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6011         }
6012 }
6013
6014 static void
6015 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6016 {
6017         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6018                 if (bp->hwrm_spec_code >= 0x10201)
6019                         req->auto_pause =
6020                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6021                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6022                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6023                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6024                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6025                 req->enables |=
6026                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6027         } else {
6028                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6029                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6030                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6031                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6032                 req->enables |=
6033                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6034                 if (bp->hwrm_spec_code >= 0x10201) {
6035                         req->auto_pause = req->force_pause;
6036                         req->enables |= cpu_to_le32(
6037                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6038                 }
6039         }
6040 }
6041
6042 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6043                                       struct hwrm_port_phy_cfg_input *req)
6044 {
6045         u8 autoneg = bp->link_info.autoneg;
6046         u16 fw_link_speed = bp->link_info.req_link_speed;
6047         u16 advertising = bp->link_info.advertising;
6048
6049         if (autoneg & BNXT_AUTONEG_SPEED) {
6050                 req->auto_mode |=
6051                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6052
6053                 req->enables |= cpu_to_le32(
6054                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6055                 req->auto_link_speed_mask = cpu_to_le16(advertising);
6056
6057                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6058                 req->flags |=
6059                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6060         } else {
6061                 req->force_link_speed = cpu_to_le16(fw_link_speed);
6062                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6063         }
6064
6065         /* tell chimp that the setting takes effect immediately */
6066         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6067 }
6068
6069 int bnxt_hwrm_set_pause(struct bnxt *bp)
6070 {
6071         struct hwrm_port_phy_cfg_input req = {0};
6072         int rc;
6073
6074         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6075         bnxt_hwrm_set_pause_common(bp, &req);
6076
6077         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6078             bp->link_info.force_link_chng)
6079                 bnxt_hwrm_set_link_common(bp, &req);
6080
6081         mutex_lock(&bp->hwrm_cmd_lock);
6082         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6083         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6084                 /* since changing of pause setting doesn't trigger any link
6085                  * change event, the driver needs to update the current pause
6086                  * result upon successfully return of the phy_cfg command
6087                  */
6088                 bp->link_info.pause =
6089                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6090                 bp->link_info.auto_pause_setting = 0;
6091                 if (!bp->link_info.force_link_chng)
6092                         bnxt_report_link(bp);
6093         }
6094         bp->link_info.force_link_chng = false;
6095         mutex_unlock(&bp->hwrm_cmd_lock);
6096         return rc;
6097 }
6098
6099 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6100                               struct hwrm_port_phy_cfg_input *req)
6101 {
6102         struct ethtool_eee *eee = &bp->eee;
6103
6104         if (eee->eee_enabled) {
6105                 u16 eee_speeds;
6106                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6107
6108                 if (eee->tx_lpi_enabled)
6109                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6110                 else
6111                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6112
6113                 req->flags |= cpu_to_le32(flags);
6114                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6115                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6116                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6117         } else {
6118                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6119         }
6120 }
6121
6122 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6123 {
6124         struct hwrm_port_phy_cfg_input req = {0};
6125
6126         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6127         if (set_pause)
6128                 bnxt_hwrm_set_pause_common(bp, &req);
6129
6130         bnxt_hwrm_set_link_common(bp, &req);
6131
6132         if (set_eee)
6133                 bnxt_hwrm_set_eee(bp, &req);
6134         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6135 }
6136
6137 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6138 {
6139         struct hwrm_port_phy_cfg_input req = {0};
6140
6141         if (!BNXT_SINGLE_PF(bp))
6142                 return 0;
6143
6144         if (pci_num_vf(bp->pdev))
6145                 return 0;
6146
6147         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6148         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6149         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6150 }
6151
6152 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6153 {
6154         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6155         struct hwrm_port_led_qcaps_input req = {0};
6156         struct bnxt_pf_info *pf = &bp->pf;
6157         int rc;
6158
6159         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6160                 return 0;
6161
6162         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6163         req.port_id = cpu_to_le16(pf->port_id);
6164         mutex_lock(&bp->hwrm_cmd_lock);
6165         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6166         if (rc) {
6167                 mutex_unlock(&bp->hwrm_cmd_lock);
6168                 return rc;
6169         }
6170         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6171                 int i;
6172
6173                 bp->num_leds = resp->num_leds;
6174                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6175                                                  bp->num_leds);
6176                 for (i = 0; i < bp->num_leds; i++) {
6177                         struct bnxt_led_info *led = &bp->leds[i];
6178                         __le16 caps = led->led_state_caps;
6179
6180                         if (!led->led_group_id ||
6181                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
6182                                 bp->num_leds = 0;
6183                                 break;
6184                         }
6185                 }
6186         }
6187         mutex_unlock(&bp->hwrm_cmd_lock);
6188         return 0;
6189 }
6190
6191 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6192 {
6193         struct hwrm_wol_filter_alloc_input req = {0};
6194         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6195         int rc;
6196
6197         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6198         req.port_id = cpu_to_le16(bp->pf.port_id);
6199         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6200         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6201         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6202         mutex_lock(&bp->hwrm_cmd_lock);
6203         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6204         if (!rc)
6205                 bp->wol_filter_id = resp->wol_filter_id;
6206         mutex_unlock(&bp->hwrm_cmd_lock);
6207         return rc;
6208 }
6209
6210 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6211 {
6212         struct hwrm_wol_filter_free_input req = {0};
6213         int rc;
6214
6215         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6216         req.port_id = cpu_to_le16(bp->pf.port_id);
6217         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6218         req.wol_filter_id = bp->wol_filter_id;
6219         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6220         return rc;
6221 }
6222
6223 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6224 {
6225         struct hwrm_wol_filter_qcfg_input req = {0};
6226         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6227         u16 next_handle = 0;
6228         int rc;
6229
6230         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6231         req.port_id = cpu_to_le16(bp->pf.port_id);
6232         req.handle = cpu_to_le16(handle);
6233         mutex_lock(&bp->hwrm_cmd_lock);
6234         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6235         if (!rc) {
6236                 next_handle = le16_to_cpu(resp->next_handle);
6237                 if (next_handle != 0) {
6238                         if (resp->wol_type ==
6239                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6240                                 bp->wol = 1;
6241                                 bp->wol_filter_id = resp->wol_filter_id;
6242                         }
6243                 }
6244         }
6245         mutex_unlock(&bp->hwrm_cmd_lock);
6246         return next_handle;
6247 }
6248
6249 static void bnxt_get_wol_settings(struct bnxt *bp)
6250 {
6251         u16 handle = 0;
6252
6253         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6254                 return;
6255
6256         do {
6257                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6258         } while (handle && handle != 0xffff);
6259 }
6260
6261 static bool bnxt_eee_config_ok(struct bnxt *bp)
6262 {
6263         struct ethtool_eee *eee = &bp->eee;
6264         struct bnxt_link_info *link_info = &bp->link_info;
6265
6266         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6267                 return true;
6268
6269         if (eee->eee_enabled) {
6270                 u32 advertising =
6271                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6272
6273                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6274                         eee->eee_enabled = 0;
6275                         return false;
6276                 }
6277                 if (eee->advertised & ~advertising) {
6278                         eee->advertised = advertising & eee->supported;
6279                         return false;
6280                 }
6281         }
6282         return true;
6283 }
6284
6285 static int bnxt_update_phy_setting(struct bnxt *bp)
6286 {
6287         int rc;
6288         bool update_link = false;
6289         bool update_pause = false;
6290         bool update_eee = false;
6291         struct bnxt_link_info *link_info = &bp->link_info;
6292
6293         rc = bnxt_update_link(bp, true);
6294         if (rc) {
6295                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6296                            rc);
6297                 return rc;
6298         }
6299         if (!BNXT_SINGLE_PF(bp))
6300                 return 0;
6301
6302         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6303             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6304             link_info->req_flow_ctrl)
6305                 update_pause = true;
6306         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6307             link_info->force_pause_setting != link_info->req_flow_ctrl)
6308                 update_pause = true;
6309         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6310                 if (BNXT_AUTO_MODE(link_info->auto_mode))
6311                         update_link = true;
6312                 if (link_info->req_link_speed != link_info->force_link_speed)
6313                         update_link = true;
6314                 if (link_info->req_duplex != link_info->duplex_setting)
6315                         update_link = true;
6316         } else {
6317                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6318                         update_link = true;
6319                 if (link_info->advertising != link_info->auto_link_speeds)
6320                         update_link = true;
6321         }
6322
6323         /* The last close may have shutdown the link, so need to call
6324          * PHY_CFG to bring it back up.
6325          */
6326         if (!netif_carrier_ok(bp->dev))
6327                 update_link = true;
6328
6329         if (!bnxt_eee_config_ok(bp))
6330                 update_eee = true;
6331
6332         if (update_link)
6333                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6334         else if (update_pause)
6335                 rc = bnxt_hwrm_set_pause(bp);
6336         if (rc) {
6337                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6338                            rc);
6339                 return rc;
6340         }
6341
6342         return rc;
6343 }
6344
6345 /* Common routine to pre-map certain register block to different GRC window.
6346  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6347  * in PF and 3 windows in VF that can be customized to map in different
6348  * register blocks.
6349  */
6350 static void bnxt_preset_reg_win(struct bnxt *bp)
6351 {
6352         if (BNXT_PF(bp)) {
6353                 /* CAG registers map to GRC window #4 */
6354                 writel(BNXT_CAG_REG_BASE,
6355                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6356         }
6357 }
6358
6359 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6360 {
6361         int rc = 0;
6362
6363         bnxt_preset_reg_win(bp);
6364         netif_carrier_off(bp->dev);
6365         if (irq_re_init) {
6366                 rc = bnxt_setup_int_mode(bp);
6367                 if (rc) {
6368                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6369                                    rc);
6370                         return rc;
6371                 }
6372         }
6373         if ((bp->flags & BNXT_FLAG_RFS) &&
6374             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6375                 /* disable RFS if falling back to INTA */
6376                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6377                 bp->flags &= ~BNXT_FLAG_RFS;
6378         }
6379
6380         rc = bnxt_alloc_mem(bp, irq_re_init);
6381         if (rc) {
6382                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6383                 goto open_err_free_mem;
6384         }
6385
6386         if (irq_re_init) {
6387                 bnxt_init_napi(bp);
6388                 rc = bnxt_request_irq(bp);
6389                 if (rc) {
6390                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6391                         goto open_err_irq;
6392                 }
6393         }
6394
6395         rc = bnxt_init_nic(bp, irq_re_init);
6396         if (rc) {
6397                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6398                 goto open_err_irq;
6399         }
6400
6401         bnxt_enable_napi(bp);
6402
6403         if (link_re_init) {
6404                 mutex_lock(&bp->link_lock);
6405                 rc = bnxt_update_phy_setting(bp);
6406                 mutex_unlock(&bp->link_lock);
6407                 if (rc)
6408                         netdev_warn(bp->dev, "failed to update phy settings\n");
6409         }
6410
6411         if (irq_re_init)
6412                 udp_tunnel_get_rx_info(bp->dev);
6413
6414         set_bit(BNXT_STATE_OPEN, &bp->state);
6415         bnxt_enable_int(bp);
6416         /* Enable TX queues */
6417         bnxt_tx_enable(bp);
6418         mod_timer(&bp->timer, jiffies + bp->current_interval);
6419         /* Poll link status and check for SFP+ module status */
6420         bnxt_get_port_module_status(bp);
6421
6422         /* VF-reps may need to be re-opened after the PF is re-opened */
6423         if (BNXT_PF(bp))
6424                 bnxt_vf_reps_open(bp);
6425         return 0;
6426
6427 open_err_irq:
6428         bnxt_del_napi(bp);
6429
6430 open_err_free_mem:
6431         bnxt_free_skbs(bp);
6432         bnxt_free_irq(bp);
6433         bnxt_free_mem(bp, true);
6434         return rc;
6435 }
6436
6437 /* rtnl_lock held */
6438 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6439 {
6440         int rc = 0;
6441
6442         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6443         if (rc) {
6444                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6445                 dev_close(bp->dev);
6446         }
6447         return rc;
6448 }
6449
6450 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6451  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
6452  * self tests.
6453  */
6454 int bnxt_half_open_nic(struct bnxt *bp)
6455 {
6456         int rc = 0;
6457
6458         rc = bnxt_alloc_mem(bp, false);
6459         if (rc) {
6460                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6461                 goto half_open_err;
6462         }
6463         rc = bnxt_init_nic(bp, false);
6464         if (rc) {
6465                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6466                 goto half_open_err;
6467         }
6468         return 0;
6469
6470 half_open_err:
6471         bnxt_free_skbs(bp);
6472         bnxt_free_mem(bp, false);
6473         dev_close(bp->dev);
6474         return rc;
6475 }
6476
6477 /* rtnl_lock held, this call can only be made after a previous successful
6478  * call to bnxt_half_open_nic().
6479  */
6480 void bnxt_half_close_nic(struct bnxt *bp)
6481 {
6482         bnxt_hwrm_resource_free(bp, false, false);
6483         bnxt_free_skbs(bp);
6484         bnxt_free_mem(bp, false);
6485 }
6486
6487 static int bnxt_open(struct net_device *dev)
6488 {
6489         struct bnxt *bp = netdev_priv(dev);
6490
6491         return __bnxt_open_nic(bp, true, true);
6492 }
6493
6494 static bool bnxt_drv_busy(struct bnxt *bp)
6495 {
6496         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6497                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6498 }
6499
6500 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6501 {
6502         int rc = 0;
6503
6504 #ifdef CONFIG_BNXT_SRIOV
6505         if (bp->sriov_cfg) {
6506                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6507                                                       !bp->sriov_cfg,
6508                                                       BNXT_SRIOV_CFG_WAIT_TMO);
6509                 if (rc)
6510                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6511         }
6512
6513         /* Close the VF-reps before closing PF */
6514         if (BNXT_PF(bp))
6515                 bnxt_vf_reps_close(bp);
6516 #endif
6517         /* Change device state to avoid TX queue wake up's */
6518         bnxt_tx_disable(bp);
6519
6520         clear_bit(BNXT_STATE_OPEN, &bp->state);
6521         smp_mb__after_atomic();
6522         while (bnxt_drv_busy(bp))
6523                 msleep(20);
6524
6525         /* Flush rings and and disable interrupts */
6526         bnxt_shutdown_nic(bp, irq_re_init);
6527
6528         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6529
6530         bnxt_disable_napi(bp);
6531         del_timer_sync(&bp->timer);
6532         bnxt_free_skbs(bp);
6533
6534         if (irq_re_init) {
6535                 bnxt_free_irq(bp);
6536                 bnxt_del_napi(bp);
6537         }
6538         bnxt_free_mem(bp, irq_re_init);
6539         return rc;
6540 }
6541
6542 static int bnxt_close(struct net_device *dev)
6543 {
6544         struct bnxt *bp = netdev_priv(dev);
6545
6546         bnxt_close_nic(bp, true, true);
6547         bnxt_hwrm_shutdown_link(bp);
6548         return 0;
6549 }
6550
6551 /* rtnl_lock held */
6552 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6553 {
6554         switch (cmd) {
6555         case SIOCGMIIPHY:
6556                 /* fallthru */
6557         case SIOCGMIIREG: {
6558                 if (!netif_running(dev))
6559                         return -EAGAIN;
6560
6561                 return 0;
6562         }
6563
6564         case SIOCSMIIREG:
6565                 if (!netif_running(dev))
6566                         return -EAGAIN;
6567
6568                 return 0;
6569
6570         default:
6571                 /* do nothing */
6572                 break;
6573         }
6574         return -EOPNOTSUPP;
6575 }
6576
6577 static void
6578 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6579 {
6580         u32 i;
6581         struct bnxt *bp = netdev_priv(dev);
6582
6583         set_bit(BNXT_STATE_READ_STATS, &bp->state);
6584         /* Make sure bnxt_close_nic() sees that we are reading stats before
6585          * we check the BNXT_STATE_OPEN flag.
6586          */
6587         smp_mb__after_atomic();
6588         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6589                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6590                 return;
6591         }
6592
6593         /* TODO check if we need to synchronize with bnxt_close path */
6594         for (i = 0; i < bp->cp_nr_rings; i++) {
6595                 struct bnxt_napi *bnapi = bp->bnapi[i];
6596                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6597                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6598
6599                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6600                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6601                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6602
6603                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6604                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6605                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6606
6607                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6608                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6609                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6610
6611                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6612                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6613                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6614
6615                 stats->rx_missed_errors +=
6616                         le64_to_cpu(hw_stats->rx_discard_pkts);
6617
6618                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6619
6620                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6621         }
6622
6623         if (bp->flags & BNXT_FLAG_PORT_STATS) {
6624                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6625                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6626
6627                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6628                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6629                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6630                                           le64_to_cpu(rx->rx_ovrsz_frames) +
6631                                           le64_to_cpu(rx->rx_runt_frames);
6632                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6633                                    le64_to_cpu(rx->rx_jbr_frames);
6634                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6635                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6636                 stats->tx_errors = le64_to_cpu(tx->tx_err);
6637         }
6638         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6639 }
6640
6641 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6642 {
6643         struct net_device *dev = bp->dev;
6644         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6645         struct netdev_hw_addr *ha;
6646         u8 *haddr;
6647         int mc_count = 0;
6648         bool update = false;
6649         int off = 0;
6650
6651         netdev_for_each_mc_addr(ha, dev) {
6652                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6653                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6654                         vnic->mc_list_count = 0;
6655                         return false;
6656                 }
6657                 haddr = ha->addr;
6658                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6659                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6660                         update = true;
6661                 }
6662                 off += ETH_ALEN;
6663                 mc_count++;
6664         }
6665         if (mc_count)
6666                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6667
6668         if (mc_count != vnic->mc_list_count) {
6669                 vnic->mc_list_count = mc_count;
6670                 update = true;
6671         }
6672         return update;
6673 }
6674
6675 static bool bnxt_uc_list_updated(struct bnxt *bp)
6676 {
6677         struct net_device *dev = bp->dev;
6678         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6679         struct netdev_hw_addr *ha;
6680         int off = 0;
6681
6682         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6683                 return true;
6684
6685         netdev_for_each_uc_addr(ha, dev) {
6686                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6687                         return true;
6688
6689                 off += ETH_ALEN;
6690         }
6691         return false;
6692 }
6693
6694 static void bnxt_set_rx_mode(struct net_device *dev)
6695 {
6696         struct bnxt *bp = netdev_priv(dev);
6697         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6698         u32 mask = vnic->rx_mask;
6699         bool mc_update = false;
6700         bool uc_update;
6701
6702         if (!netif_running(dev))
6703                 return;
6704
6705         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6706                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6707                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6708
6709         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6710                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6711
6712         uc_update = bnxt_uc_list_updated(bp);
6713
6714         if (dev->flags & IFF_ALLMULTI) {
6715                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6716                 vnic->mc_list_count = 0;
6717         } else {
6718                 mc_update = bnxt_mc_list_updated(bp, &mask);
6719         }
6720
6721         if (mask != vnic->rx_mask || uc_update || mc_update) {
6722                 vnic->rx_mask = mask;
6723
6724                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6725                 bnxt_queue_sp_work(bp);
6726         }
6727 }
6728
6729 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6730 {
6731         struct net_device *dev = bp->dev;
6732         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6733         struct netdev_hw_addr *ha;
6734         int i, off = 0, rc;
6735         bool uc_update;
6736
6737         netif_addr_lock_bh(dev);
6738         uc_update = bnxt_uc_list_updated(bp);
6739         netif_addr_unlock_bh(dev);
6740
6741         if (!uc_update)
6742                 goto skip_uc;
6743
6744         mutex_lock(&bp->hwrm_cmd_lock);
6745         for (i = 1; i < vnic->uc_filter_count; i++) {
6746                 struct hwrm_cfa_l2_filter_free_input req = {0};
6747
6748                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6749                                        -1);
6750
6751                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6752
6753                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6754                                         HWRM_CMD_TIMEOUT);
6755         }
6756         mutex_unlock(&bp->hwrm_cmd_lock);
6757
6758         vnic->uc_filter_count = 1;
6759
6760         netif_addr_lock_bh(dev);
6761         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6762                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6763         } else {
6764                 netdev_for_each_uc_addr(ha, dev) {
6765                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6766                         off += ETH_ALEN;
6767                         vnic->uc_filter_count++;
6768                 }
6769         }
6770         netif_addr_unlock_bh(dev);
6771
6772         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6773                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6774                 if (rc) {
6775                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6776                                    rc);
6777                         vnic->uc_filter_count = i;
6778                         return rc;
6779                 }
6780         }
6781
6782 skip_uc:
6783         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6784         if (rc && vnic->mc_list_count) {
6785                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
6786                             rc);
6787                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6788                 vnic->mc_list_count = 0;
6789                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6790         }
6791         if (rc)
6792                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
6793                            rc);
6794
6795         return rc;
6796 }
6797
6798 /* If the chip and firmware supports RFS */
6799 static bool bnxt_rfs_supported(struct bnxt *bp)
6800 {
6801         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6802                 return true;
6803         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6804                 return true;
6805         return false;
6806 }
6807
6808 /* If runtime conditions support RFS */
6809 static bool bnxt_rfs_capable(struct bnxt *bp)
6810 {
6811 #ifdef CONFIG_RFS_ACCEL
6812         int vnics, max_vnics, max_rss_ctxs;
6813
6814         if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6815                 return false;
6816
6817         vnics = 1 + bp->rx_nr_rings;
6818         max_vnics = bnxt_get_max_func_vnics(bp);
6819         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6820
6821         /* RSS contexts not a limiting factor */
6822         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6823                 max_rss_ctxs = max_vnics;
6824         if (vnics > max_vnics || vnics > max_rss_ctxs) {
6825                 netdev_warn(bp->dev,
6826                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6827                             min(max_rss_ctxs - 1, max_vnics - 1));
6828                 return false;
6829         }
6830
6831         return true;
6832 #else
6833         return false;
6834 #endif
6835 }
6836
6837 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6838                                            netdev_features_t features)
6839 {
6840         struct bnxt *bp = netdev_priv(dev);
6841         netdev_features_t vlan_features;
6842
6843         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6844                 features &= ~NETIF_F_NTUPLE;
6845
6846         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6847          * turned on or off together.
6848          */
6849         vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX |
6850                                     NETIF_F_HW_VLAN_STAG_RX);
6851         if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX |
6852                               NETIF_F_HW_VLAN_STAG_RX)) {
6853                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6854                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6855                                       NETIF_F_HW_VLAN_STAG_RX);
6856                 else if (vlan_features)
6857                         features |= NETIF_F_HW_VLAN_CTAG_RX |
6858                                     NETIF_F_HW_VLAN_STAG_RX;
6859         }
6860 #ifdef CONFIG_BNXT_SRIOV
6861         if (BNXT_VF(bp)) {
6862                 if (bp->vf.vlan) {
6863                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6864                                       NETIF_F_HW_VLAN_STAG_RX);
6865                 }
6866         }
6867 #endif
6868         return features;
6869 }
6870
6871 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6872 {
6873         struct bnxt *bp = netdev_priv(dev);
6874         u32 flags = bp->flags;
6875         u32 changes;
6876         int rc = 0;
6877         bool re_init = false;
6878         bool update_tpa = false;
6879
6880         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6881         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6882                 flags |= BNXT_FLAG_GRO;
6883         if (features & NETIF_F_LRO)
6884                 flags |= BNXT_FLAG_LRO;
6885
6886         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6887                 flags &= ~BNXT_FLAG_TPA;
6888
6889         if (features & NETIF_F_HW_VLAN_CTAG_RX)
6890                 flags |= BNXT_FLAG_STRIP_VLAN;
6891
6892         if (features & NETIF_F_NTUPLE)
6893                 flags |= BNXT_FLAG_RFS;
6894
6895         changes = flags ^ bp->flags;
6896         if (changes & BNXT_FLAG_TPA) {
6897                 update_tpa = true;
6898                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6899                     (flags & BNXT_FLAG_TPA) == 0)
6900                         re_init = true;
6901         }
6902
6903         if (changes & ~BNXT_FLAG_TPA)
6904                 re_init = true;
6905
6906         if (flags != bp->flags) {
6907                 u32 old_flags = bp->flags;
6908
6909                 bp->flags = flags;
6910
6911                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6912                         if (update_tpa)
6913                                 bnxt_set_ring_params(bp);
6914                         return rc;
6915                 }
6916
6917                 if (re_init) {
6918                         bnxt_close_nic(bp, false, false);
6919                         if (update_tpa)
6920                                 bnxt_set_ring_params(bp);
6921
6922                         return bnxt_open_nic(bp, false, false);
6923                 }
6924                 if (update_tpa) {
6925                         rc = bnxt_set_tpa(bp,
6926                                           (flags & BNXT_FLAG_TPA) ?
6927                                           true : false);
6928                         if (rc)
6929                                 bp->flags = old_flags;
6930                 }
6931         }
6932         return rc;
6933 }
6934
6935 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6936 {
6937         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6938         int i = bnapi->index;
6939
6940         if (!txr)
6941                 return;
6942
6943         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6944                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6945                     txr->tx_cons);
6946 }
6947
6948 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6949 {
6950         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6951         int i = bnapi->index;
6952
6953         if (!rxr)
6954                 return;
6955
6956         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6957                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6958                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6959                     rxr->rx_sw_agg_prod);
6960 }
6961
6962 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6963 {
6964         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6965         int i = bnapi->index;
6966
6967         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6968                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6969 }
6970
6971 static void bnxt_dbg_dump_states(struct bnxt *bp)
6972 {
6973         int i;
6974         struct bnxt_napi *bnapi;
6975
6976         for (i = 0; i < bp->cp_nr_rings; i++) {
6977                 bnapi = bp->bnapi[i];
6978                 if (netif_msg_drv(bp)) {
6979                         bnxt_dump_tx_sw_state(bnapi);
6980                         bnxt_dump_rx_sw_state(bnapi);
6981                         bnxt_dump_cp_sw_state(bnapi);
6982                 }
6983         }
6984 }
6985
6986 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6987 {
6988         if (!silent)
6989                 bnxt_dbg_dump_states(bp);
6990         if (netif_running(bp->dev)) {
6991                 int rc;
6992
6993                 if (!silent)
6994                         bnxt_ulp_stop(bp);
6995                 bnxt_close_nic(bp, false, false);
6996                 rc = bnxt_open_nic(bp, false, false);
6997                 if (!silent && !rc)
6998                         bnxt_ulp_start(bp);
6999         }
7000 }
7001
7002 static void bnxt_tx_timeout(struct net_device *dev)
7003 {
7004         struct bnxt *bp = netdev_priv(dev);
7005
7006         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
7007         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7008         bnxt_queue_sp_work(bp);
7009 }
7010
7011 #ifdef CONFIG_NET_POLL_CONTROLLER
7012 static void bnxt_poll_controller(struct net_device *dev)
7013 {
7014         struct bnxt *bp = netdev_priv(dev);
7015         int i;
7016
7017         /* Only process tx rings/combined rings in netpoll mode. */
7018         for (i = 0; i < bp->tx_nr_rings; i++) {
7019                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
7020
7021                 napi_schedule(&txr->bnapi->napi);
7022         }
7023 }
7024 #endif
7025
7026 static void bnxt_timer(unsigned long data)
7027 {
7028         struct bnxt *bp = (struct bnxt *)data;
7029         struct net_device *dev = bp->dev;
7030
7031         if (!netif_running(dev))
7032                 return;
7033
7034         if (atomic_read(&bp->intr_sem) != 0)
7035                 goto bnxt_restart_timer;
7036
7037         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7038             bp->stats_coal_ticks) {
7039                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7040                 bnxt_queue_sp_work(bp);
7041         }
7042 bnxt_restart_timer:
7043         mod_timer(&bp->timer, jiffies + bp->current_interval);
7044 }
7045
7046 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7047 {
7048         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7049          * set.  If the device is being closed, bnxt_close() may be holding
7050          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
7051          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7052          */
7053         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7054         rtnl_lock();
7055 }
7056
7057 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7058 {
7059         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7060         rtnl_unlock();
7061 }
7062
7063 /* Only called from bnxt_sp_task() */
7064 static void bnxt_reset(struct bnxt *bp, bool silent)
7065 {
7066         bnxt_rtnl_lock_sp(bp);
7067         if (test_bit(BNXT_STATE_OPEN, &bp->state))
7068                 bnxt_reset_task(bp, silent);
7069         bnxt_rtnl_unlock_sp(bp);
7070 }
7071
7072 static void bnxt_cfg_ntp_filters(struct bnxt *);
7073
7074 static void bnxt_sp_task(struct work_struct *work)
7075 {
7076         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7077
7078         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7079         smp_mb__after_atomic();
7080         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7081                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7082                 return;
7083         }
7084
7085         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7086                 bnxt_cfg_rx_mode(bp);
7087
7088         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7089                 bnxt_cfg_ntp_filters(bp);
7090         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7091                 bnxt_hwrm_exec_fwd_req(bp);
7092         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7093                 bnxt_hwrm_tunnel_dst_port_alloc(
7094                         bp, bp->vxlan_port,
7095                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7096         }
7097         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7098                 bnxt_hwrm_tunnel_dst_port_free(
7099                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7100         }
7101         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7102                 bnxt_hwrm_tunnel_dst_port_alloc(
7103                         bp, bp->nge_port,
7104                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7105         }
7106         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7107                 bnxt_hwrm_tunnel_dst_port_free(
7108                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7109         }
7110         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7111                 bnxt_hwrm_port_qstats(bp);
7112
7113         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7114                 int rc;
7115
7116                 mutex_lock(&bp->link_lock);
7117                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7118                                        &bp->sp_event))
7119                         bnxt_hwrm_phy_qcaps(bp);
7120
7121                 rc = bnxt_update_link(bp, true);
7122                 mutex_unlock(&bp->link_lock);
7123                 if (rc)
7124                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7125                                    rc);
7126         }
7127         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7128                 mutex_lock(&bp->link_lock);
7129                 bnxt_get_port_module_status(bp);
7130                 mutex_unlock(&bp->link_lock);
7131         }
7132         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
7133          * must be the last functions to be called before exiting.
7134          */
7135         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7136                 bnxt_reset(bp, false);
7137
7138         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7139                 bnxt_reset(bp, true);
7140
7141         smp_mb__before_atomic();
7142         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7143 }
7144
7145 /* Under rtnl_lock */
7146 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7147                      int tx_xdp)
7148 {
7149         int max_rx, max_tx, tx_sets = 1;
7150         int tx_rings_needed;
7151         int rc;
7152
7153         if (tcs)
7154                 tx_sets = tcs;
7155
7156         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7157         if (rc)
7158                 return rc;
7159
7160         if (max_rx < rx)
7161                 return -ENOMEM;
7162
7163         tx_rings_needed = tx * tx_sets + tx_xdp;
7164         if (max_tx < tx_rings_needed)
7165                 return -ENOMEM;
7166
7167         return bnxt_hwrm_check_tx_rings(bp, tx_rings_needed);
7168 }
7169
7170 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7171 {
7172         if (bp->bar2) {
7173                 pci_iounmap(pdev, bp->bar2);
7174                 bp->bar2 = NULL;
7175         }
7176
7177         if (bp->bar1) {
7178                 pci_iounmap(pdev, bp->bar1);
7179                 bp->bar1 = NULL;
7180         }
7181
7182         if (bp->bar0) {
7183                 pci_iounmap(pdev, bp->bar0);
7184                 bp->bar0 = NULL;
7185         }
7186 }
7187
7188 static void bnxt_cleanup_pci(struct bnxt *bp)
7189 {
7190         bnxt_unmap_bars(bp, bp->pdev);
7191         pci_release_regions(bp->pdev);
7192         pci_disable_device(bp->pdev);
7193 }
7194
7195 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7196 {
7197         int rc;
7198         struct bnxt *bp = netdev_priv(dev);
7199
7200         SET_NETDEV_DEV(dev, &pdev->dev);
7201
7202         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7203         rc = pci_enable_device(pdev);
7204         if (rc) {
7205                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7206                 goto init_err;
7207         }
7208
7209         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7210                 dev_err(&pdev->dev,
7211                         "Cannot find PCI device base address, aborting\n");
7212                 rc = -ENODEV;
7213                 goto init_err_disable;
7214         }
7215
7216         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7217         if (rc) {
7218                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7219                 goto init_err_disable;
7220         }
7221
7222         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7223             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7224                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7225                 rc = -EIO;
7226                 goto init_err_release;
7227         }
7228
7229         pci_set_master(pdev);
7230
7231         bp->dev = dev;
7232         bp->pdev = pdev;
7233
7234         bp->bar0 = pci_ioremap_bar(pdev, 0);
7235         if (!bp->bar0) {
7236                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7237                 rc = -ENOMEM;
7238                 goto init_err_release;
7239         }
7240
7241         bp->bar1 = pci_ioremap_bar(pdev, 2);
7242         if (!bp->bar1) {
7243                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7244                 rc = -ENOMEM;
7245                 goto init_err_release;
7246         }
7247
7248         bp->bar2 = pci_ioremap_bar(pdev, 4);
7249         if (!bp->bar2) {
7250                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7251                 rc = -ENOMEM;
7252                 goto init_err_release;
7253         }
7254
7255         pci_enable_pcie_error_reporting(pdev);
7256
7257         INIT_WORK(&bp->sp_task, bnxt_sp_task);
7258
7259         spin_lock_init(&bp->ntp_fltr_lock);
7260
7261         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7262         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7263
7264         /* tick values in micro seconds */
7265         bp->rx_coal_ticks = 12;
7266         bp->rx_coal_bufs = 30;
7267         bp->rx_coal_ticks_irq = 1;
7268         bp->rx_coal_bufs_irq = 2;
7269
7270         bp->tx_coal_ticks = 25;
7271         bp->tx_coal_bufs = 30;
7272         bp->tx_coal_ticks_irq = 2;
7273         bp->tx_coal_bufs_irq = 2;
7274
7275         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7276
7277         init_timer(&bp->timer);
7278         bp->timer.data = (unsigned long)bp;
7279         bp->timer.function = bnxt_timer;
7280         bp->current_interval = BNXT_TIMER_INTERVAL;
7281
7282         clear_bit(BNXT_STATE_OPEN, &bp->state);
7283         return 0;
7284
7285 init_err_release:
7286         bnxt_unmap_bars(bp, pdev);
7287         pci_release_regions(pdev);
7288
7289 init_err_disable:
7290         pci_disable_device(pdev);
7291
7292 init_err:
7293         return rc;
7294 }
7295
7296 /* rtnl_lock held */
7297 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7298 {
7299         struct sockaddr *addr = p;
7300         struct bnxt *bp = netdev_priv(dev);
7301         int rc = 0;
7302
7303         if (!is_valid_ether_addr(addr->sa_data))
7304                 return -EADDRNOTAVAIL;
7305
7306         rc = bnxt_approve_mac(bp, addr->sa_data);
7307         if (rc)
7308                 return rc;
7309
7310         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7311                 return 0;
7312
7313         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7314         if (netif_running(dev)) {
7315                 bnxt_close_nic(bp, false, false);
7316                 rc = bnxt_open_nic(bp, false, false);
7317         }
7318
7319         return rc;
7320 }
7321
7322 /* rtnl_lock held */
7323 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7324 {
7325         struct bnxt *bp = netdev_priv(dev);
7326
7327         if (netif_running(dev))
7328                 bnxt_close_nic(bp, true, false);
7329
7330         dev->mtu = new_mtu;
7331         bnxt_set_ring_params(bp);
7332
7333         if (netif_running(dev))
7334                 return bnxt_open_nic(bp, true, false);
7335
7336         return 0;
7337 }
7338
7339 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7340 {
7341         struct bnxt *bp = netdev_priv(dev);
7342         bool sh = false;
7343         int rc;
7344
7345         if (tc > bp->max_tc) {
7346                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7347                            tc, bp->max_tc);
7348                 return -EINVAL;
7349         }
7350
7351         if (netdev_get_num_tc(dev) == tc)
7352                 return 0;
7353
7354         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7355                 sh = true;
7356
7357         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7358                               sh, tc, bp->tx_nr_rings_xdp);
7359         if (rc)
7360                 return rc;
7361
7362         /* Needs to close the device and do hw resource re-allocations */
7363         if (netif_running(bp->dev))
7364                 bnxt_close_nic(bp, true, false);
7365
7366         if (tc) {
7367                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7368                 netdev_set_num_tc(dev, tc);
7369         } else {
7370                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7371                 netdev_reset_tc(dev);
7372         }
7373         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
7374         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7375                                bp->tx_nr_rings + bp->rx_nr_rings;
7376         bp->num_stat_ctxs = bp->cp_nr_rings;
7377
7378         if (netif_running(bp->dev))
7379                 return bnxt_open_nic(bp, true, false);
7380
7381         return 0;
7382 }
7383
7384 static int bnxt_setup_flower(struct net_device *dev,
7385                              struct tc_cls_flower_offload *cls_flower)
7386 {
7387         struct bnxt *bp = netdev_priv(dev);
7388
7389         if (BNXT_VF(bp))
7390                 return -EOPNOTSUPP;
7391
7392         return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, cls_flower);
7393 }
7394
7395 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7396                          void *type_data)
7397 {
7398         switch (type) {
7399         case TC_SETUP_CLSFLOWER:
7400                 return bnxt_setup_flower(dev, type_data);
7401         case TC_SETUP_MQPRIO: {
7402                 struct tc_mqprio_qopt *mqprio = type_data;
7403
7404                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7405
7406                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7407         }
7408         default:
7409                 return -EOPNOTSUPP;
7410         }
7411 }
7412
7413 #ifdef CONFIG_RFS_ACCEL
7414 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7415                             struct bnxt_ntuple_filter *f2)
7416 {
7417         struct flow_keys *keys1 = &f1->fkeys;
7418         struct flow_keys *keys2 = &f2->fkeys;
7419
7420         if (keys1->basic.n_proto != keys2->basic.n_proto ||
7421             keys1->basic.ip_proto != keys2->basic.ip_proto)
7422                 return false;
7423
7424         if (keys1->basic.n_proto == htons(ETH_P_IP)) {
7425                 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
7426                     keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
7427                         return false;
7428         } else {
7429                 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
7430                            sizeof(keys1->addrs.v6addrs.src)) ||
7431                     memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
7432                            sizeof(keys1->addrs.v6addrs.dst)))
7433                         return false;
7434         }
7435
7436         if (keys1->ports.ports == keys2->ports.ports &&
7437             keys1->control.flags == keys2->control.flags &&
7438             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7439             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7440                 return true;
7441
7442         return false;
7443 }
7444
7445 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7446                               u16 rxq_index, u32 flow_id)
7447 {
7448         struct bnxt *bp = netdev_priv(dev);
7449         struct bnxt_ntuple_filter *fltr, *new_fltr;
7450         struct flow_keys *fkeys;
7451         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7452         int rc = 0, idx, bit_id, l2_idx = 0;
7453         struct hlist_head *head;
7454
7455         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7456                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7457                 int off = 0, j;
7458
7459                 netif_addr_lock_bh(dev);
7460                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7461                         if (ether_addr_equal(eth->h_dest,
7462                                              vnic->uc_list + off)) {
7463                                 l2_idx = j + 1;
7464                                 break;
7465                         }
7466                 }
7467                 netif_addr_unlock_bh(dev);
7468                 if (!l2_idx)
7469                         return -EINVAL;
7470         }
7471         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7472         if (!new_fltr)
7473                 return -ENOMEM;
7474
7475         fkeys = &new_fltr->fkeys;
7476         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7477                 rc = -EPROTONOSUPPORT;
7478                 goto err_free;
7479         }
7480
7481         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7482              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7483             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7484              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7485                 rc = -EPROTONOSUPPORT;
7486                 goto err_free;
7487         }
7488         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7489             bp->hwrm_spec_code < 0x10601) {
7490                 rc = -EPROTONOSUPPORT;
7491                 goto err_free;
7492         }
7493         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7494             bp->hwrm_spec_code < 0x10601) {
7495                 rc = -EPROTONOSUPPORT;
7496                 goto err_free;
7497         }
7498
7499         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7500         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7501
7502         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7503         head = &bp->ntp_fltr_hash_tbl[idx];
7504         rcu_read_lock();
7505         hlist_for_each_entry_rcu(fltr, head, hash) {
7506                 if (bnxt_fltr_match(fltr, new_fltr)) {
7507                         rc = fltr->sw_id;
7508                         rcu_read_unlock();
7509                         goto err_free;
7510                 }
7511         }
7512         rcu_read_unlock();
7513
7514         spin_lock_bh(&bp->ntp_fltr_lock);
7515         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7516                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
7517         if (bit_id < 0) {
7518                 spin_unlock_bh(&bp->ntp_fltr_lock);
7519                 rc = -ENOMEM;
7520                 goto err_free;
7521         }
7522
7523         new_fltr->sw_id = (u16)bit_id;
7524         new_fltr->flow_id = flow_id;
7525         new_fltr->l2_fltr_idx = l2_idx;
7526         new_fltr->rxq = rxq_index;
7527         hlist_add_head_rcu(&new_fltr->hash, head);
7528         bp->ntp_fltr_count++;
7529         spin_unlock_bh(&bp->ntp_fltr_lock);
7530
7531         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7532         bnxt_queue_sp_work(bp);
7533
7534         return new_fltr->sw_id;
7535
7536 err_free:
7537         kfree(new_fltr);
7538         return rc;
7539 }
7540
7541 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7542 {
7543         int i;
7544
7545         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7546                 struct hlist_head *head;
7547                 struct hlist_node *tmp;
7548                 struct bnxt_ntuple_filter *fltr;
7549                 int rc;
7550
7551                 head = &bp->ntp_fltr_hash_tbl[i];
7552                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7553                         bool del = false;
7554
7555                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7556                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7557                                                         fltr->flow_id,
7558                                                         fltr->sw_id)) {
7559                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
7560                                                                          fltr);
7561                                         del = true;
7562                                 }
7563                         } else {
7564                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7565                                                                        fltr);
7566                                 if (rc)
7567                                         del = true;
7568                                 else
7569                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
7570                         }
7571
7572                         if (del) {
7573                                 spin_lock_bh(&bp->ntp_fltr_lock);
7574                                 hlist_del_rcu(&fltr->hash);
7575                                 bp->ntp_fltr_count--;
7576                                 spin_unlock_bh(&bp->ntp_fltr_lock);
7577                                 synchronize_rcu();
7578                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7579                                 kfree(fltr);
7580                         }
7581                 }
7582         }
7583         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7584                 netdev_info(bp->dev, "Receive PF driver unload event!");
7585 }
7586
7587 #else
7588
7589 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7590 {
7591 }
7592
7593 #endif /* CONFIG_RFS_ACCEL */
7594
7595 static void bnxt_udp_tunnel_add(struct net_device *dev,
7596                                 struct udp_tunnel_info *ti)
7597 {
7598         struct bnxt *bp = netdev_priv(dev);
7599
7600         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7601                 return;
7602
7603         if (!netif_running(dev))
7604                 return;
7605
7606         switch (ti->type) {
7607         case UDP_TUNNEL_TYPE_VXLAN:
7608                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7609                         return;
7610
7611                 bp->vxlan_port_cnt++;
7612                 if (bp->vxlan_port_cnt == 1) {
7613                         bp->vxlan_port = ti->port;
7614                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7615                         bnxt_queue_sp_work(bp);
7616                 }
7617                 break;
7618         case UDP_TUNNEL_TYPE_GENEVE:
7619                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7620                         return;
7621
7622                 bp->nge_port_cnt++;
7623                 if (bp->nge_port_cnt == 1) {
7624                         bp->nge_port = ti->port;
7625                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7626                 }
7627                 break;
7628         default:
7629                 return;
7630         }
7631
7632         bnxt_queue_sp_work(bp);
7633 }
7634
7635 static void bnxt_udp_tunnel_del(struct net_device *dev,
7636                                 struct udp_tunnel_info *ti)
7637 {
7638         struct bnxt *bp = netdev_priv(dev);
7639
7640         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7641                 return;
7642
7643         if (!netif_running(dev))
7644                 return;
7645
7646         switch (ti->type) {
7647         case UDP_TUNNEL_TYPE_VXLAN:
7648                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7649                         return;
7650                 bp->vxlan_port_cnt--;
7651
7652                 if (bp->vxlan_port_cnt != 0)
7653                         return;
7654
7655                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7656                 break;
7657         case UDP_TUNNEL_TYPE_GENEVE:
7658                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7659                         return;
7660                 bp->nge_port_cnt--;
7661
7662                 if (bp->nge_port_cnt != 0)
7663                         return;
7664
7665                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7666                 break;
7667         default:
7668                 return;
7669         }
7670
7671         bnxt_queue_sp_work(bp);
7672 }
7673
7674 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7675                                struct net_device *dev, u32 filter_mask,
7676                                int nlflags)
7677 {
7678         struct bnxt *bp = netdev_priv(dev);
7679
7680         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
7681                                        nlflags, filter_mask, NULL);
7682 }
7683
7684 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
7685                                u16 flags)
7686 {
7687         struct bnxt *bp = netdev_priv(dev);
7688         struct nlattr *attr, *br_spec;
7689         int rem, rc = 0;
7690
7691         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
7692                 return -EOPNOTSUPP;
7693
7694         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7695         if (!br_spec)
7696                 return -EINVAL;
7697
7698         nla_for_each_nested(attr, br_spec, rem) {
7699                 u16 mode;
7700
7701                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7702                         continue;
7703
7704                 if (nla_len(attr) < sizeof(mode))
7705                         return -EINVAL;
7706
7707                 mode = nla_get_u16(attr);
7708                 if (mode == bp->br_mode)
7709                         break;
7710
7711                 rc = bnxt_hwrm_set_br_mode(bp, mode);
7712                 if (!rc)
7713                         bp->br_mode = mode;
7714                 break;
7715         }
7716         return rc;
7717 }
7718
7719 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
7720                                    size_t len)
7721 {
7722         struct bnxt *bp = netdev_priv(dev);
7723         int rc;
7724
7725         /* The PF and it's VF-reps only support the switchdev framework */
7726         if (!BNXT_PF(bp))
7727                 return -EOPNOTSUPP;
7728
7729         rc = snprintf(buf, len, "p%d", bp->pf.port_id);
7730
7731         if (rc >= len)
7732                 return -EOPNOTSUPP;
7733         return 0;
7734 }
7735
7736 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
7737 {
7738         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
7739                 return -EOPNOTSUPP;
7740
7741         /* The PF and it's VF-reps only support the switchdev framework */
7742         if (!BNXT_PF(bp))
7743                 return -EOPNOTSUPP;
7744
7745         switch (attr->id) {
7746         case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
7747                 /* In SRIOV each PF-pool (PF + child VFs) serves as a
7748                  * switching domain, the PF's perm mac-addr can be used
7749                  * as the unique parent-id
7750                  */
7751                 attr->u.ppid.id_len = ETH_ALEN;
7752                 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr);
7753                 break;
7754         default:
7755                 return -EOPNOTSUPP;
7756         }
7757         return 0;
7758 }
7759
7760 static int bnxt_swdev_port_attr_get(struct net_device *dev,
7761                                     struct switchdev_attr *attr)
7762 {
7763         return bnxt_port_attr_get(netdev_priv(dev), attr);
7764 }
7765
7766 static const struct switchdev_ops bnxt_switchdev_ops = {
7767         .switchdev_port_attr_get        = bnxt_swdev_port_attr_get
7768 };
7769
7770 static const struct net_device_ops bnxt_netdev_ops = {
7771         .ndo_open               = bnxt_open,
7772         .ndo_start_xmit         = bnxt_start_xmit,
7773         .ndo_stop               = bnxt_close,
7774         .ndo_get_stats64        = bnxt_get_stats64,
7775         .ndo_set_rx_mode        = bnxt_set_rx_mode,
7776         .ndo_do_ioctl           = bnxt_ioctl,
7777         .ndo_validate_addr      = eth_validate_addr,
7778         .ndo_set_mac_address    = bnxt_change_mac_addr,
7779         .ndo_change_mtu         = bnxt_change_mtu,
7780         .ndo_fix_features       = bnxt_fix_features,
7781         .ndo_set_features       = bnxt_set_features,
7782         .ndo_tx_timeout         = bnxt_tx_timeout,
7783 #ifdef CONFIG_BNXT_SRIOV
7784         .ndo_get_vf_config      = bnxt_get_vf_config,
7785         .ndo_set_vf_mac         = bnxt_set_vf_mac,
7786         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
7787         .ndo_set_vf_rate        = bnxt_set_vf_bw,
7788         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
7789         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
7790 #endif
7791 #ifdef CONFIG_NET_POLL_CONTROLLER
7792         .ndo_poll_controller    = bnxt_poll_controller,
7793 #endif
7794         .ndo_setup_tc           = bnxt_setup_tc,
7795 #ifdef CONFIG_RFS_ACCEL
7796         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
7797 #endif
7798         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
7799         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
7800         .ndo_xdp                = bnxt_xdp,
7801         .ndo_bridge_getlink     = bnxt_bridge_getlink,
7802         .ndo_bridge_setlink     = bnxt_bridge_setlink,
7803         .ndo_get_phys_port_name = bnxt_get_phys_port_name
7804 };
7805
7806 static void bnxt_remove_one(struct pci_dev *pdev)
7807 {
7808         struct net_device *dev = pci_get_drvdata(pdev);
7809         struct bnxt *bp = netdev_priv(dev);
7810
7811         if (BNXT_PF(bp)) {
7812                 bnxt_sriov_disable(bp);
7813                 bnxt_dl_unregister(bp);
7814         }
7815
7816         pci_disable_pcie_error_reporting(pdev);
7817         unregister_netdev(dev);
7818         bnxt_shutdown_tc(bp);
7819         bnxt_cancel_sp_work(bp);
7820         bp->sp_event = 0;
7821
7822         bnxt_clear_int_mode(bp);
7823         bnxt_hwrm_func_drv_unrgtr(bp);
7824         bnxt_free_hwrm_resources(bp);
7825         bnxt_free_hwrm_short_cmd_req(bp);
7826         bnxt_ethtool_free(bp);
7827         bnxt_dcb_free(bp);
7828         kfree(bp->edev);
7829         bp->edev = NULL;
7830         if (bp->xdp_prog)
7831                 bpf_prog_put(bp->xdp_prog);
7832         bnxt_cleanup_pci(bp);
7833         free_netdev(dev);
7834 }
7835
7836 static int bnxt_probe_phy(struct bnxt *bp)
7837 {
7838         int rc = 0;
7839         struct bnxt_link_info *link_info = &bp->link_info;
7840
7841         rc = bnxt_hwrm_phy_qcaps(bp);
7842         if (rc) {
7843                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7844                            rc);
7845                 return rc;
7846         }
7847         mutex_init(&bp->link_lock);
7848
7849         rc = bnxt_update_link(bp, false);
7850         if (rc) {
7851                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7852                            rc);
7853                 return rc;
7854         }
7855
7856         /* Older firmware does not have supported_auto_speeds, so assume
7857          * that all supported speeds can be autonegotiated.
7858          */
7859         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7860                 link_info->support_auto_speeds = link_info->support_speeds;
7861
7862         /*initialize the ethool setting copy with NVM settings */
7863         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7864                 link_info->autoneg = BNXT_AUTONEG_SPEED;
7865                 if (bp->hwrm_spec_code >= 0x10201) {
7866                         if (link_info->auto_pause_setting &
7867                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7868                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7869                 } else {
7870                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7871                 }
7872                 link_info->advertising = link_info->auto_link_speeds;
7873         } else {
7874                 link_info->req_link_speed = link_info->force_link_speed;
7875                 link_info->req_duplex = link_info->duplex_setting;
7876         }
7877         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7878                 link_info->req_flow_ctrl =
7879                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7880         else
7881                 link_info->req_flow_ctrl = link_info->force_pause_setting;
7882         return rc;
7883 }
7884
7885 static int bnxt_get_max_irq(struct pci_dev *pdev)
7886 {
7887         u16 ctrl;
7888
7889         if (!pdev->msix_cap)
7890                 return 1;
7891
7892         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7893         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7894 }
7895
7896 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7897                                 int *max_cp)
7898 {
7899         int max_ring_grps = 0;
7900
7901 #ifdef CONFIG_BNXT_SRIOV
7902         if (!BNXT_PF(bp)) {
7903                 *max_tx = bp->vf.max_tx_rings;
7904                 *max_rx = bp->vf.max_rx_rings;
7905                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7906                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7907                 max_ring_grps = bp->vf.max_hw_ring_grps;
7908         } else
7909 #endif
7910         {
7911                 *max_tx = bp->pf.max_tx_rings;
7912                 *max_rx = bp->pf.max_rx_rings;
7913                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7914                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7915                 max_ring_grps = bp->pf.max_hw_ring_grps;
7916         }
7917         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7918                 *max_cp -= 1;
7919                 *max_rx -= 2;
7920         }
7921         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7922                 *max_rx >>= 1;
7923         *max_rx = min_t(int, *max_rx, max_ring_grps);
7924 }
7925
7926 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7927 {
7928         int rx, tx, cp;
7929
7930         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7931         *max_rx = rx;
7932         *max_tx = tx;
7933         if (!rx || !tx || !cp)
7934                 return -ENOMEM;
7935
7936         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7937 }
7938
7939 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7940                                bool shared)
7941 {
7942         int rc;
7943
7944         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7945         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7946                 /* Not enough rings, try disabling agg rings. */
7947                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7948                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7949                 if (rc) {
7950                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
7951                         bp->flags |= BNXT_FLAG_AGG_RINGS;
7952                         return rc;
7953                 }
7954                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7955                 bp->dev->hw_features &= ~NETIF_F_LRO;
7956                 bp->dev->features &= ~NETIF_F_LRO;
7957                 bnxt_set_ring_params(bp);
7958         }
7959
7960         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7961                 int max_cp, max_stat, max_irq;
7962
7963                 /* Reserve minimum resources for RoCE */
7964                 max_cp = bnxt_get_max_func_cp_rings(bp);
7965                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7966                 max_irq = bnxt_get_max_func_irqs(bp);
7967                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7968                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7969                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7970                         return 0;
7971
7972                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7973                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7974                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7975                 max_cp = min_t(int, max_cp, max_irq);
7976                 max_cp = min_t(int, max_cp, max_stat);
7977                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7978                 if (rc)
7979                         rc = 0;
7980         }
7981         return rc;
7982 }
7983
7984 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
7985 {
7986         int dflt_rings, max_rx_rings, max_tx_rings, rc;
7987
7988         if (sh)
7989                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7990         dflt_rings = netif_get_num_default_rss_queues();
7991         /* Reduce default rings to reduce memory usage on multi-port cards */
7992         if (bp->port_count > 1)
7993                 dflt_rings = min_t(int, dflt_rings, 4);
7994         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7995         if (rc)
7996                 return rc;
7997         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7998         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7999
8000         rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
8001         if (rc)
8002                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8003
8004         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8005         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8006                                bp->tx_nr_rings + bp->rx_nr_rings;
8007         bp->num_stat_ctxs = bp->cp_nr_rings;
8008         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8009                 bp->rx_nr_rings++;
8010                 bp->cp_nr_rings++;
8011         }
8012         return rc;
8013 }
8014
8015 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
8016 {
8017         ASSERT_RTNL();
8018         bnxt_hwrm_func_qcaps(bp);
8019         bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
8020 }
8021
8022 static int bnxt_init_mac_addr(struct bnxt *bp)
8023 {
8024         int rc = 0;
8025
8026         if (BNXT_PF(bp)) {
8027                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8028         } else {
8029 #ifdef CONFIG_BNXT_SRIOV
8030                 struct bnxt_vf_info *vf = &bp->vf;
8031
8032                 if (is_valid_ether_addr(vf->mac_addr)) {
8033                         /* overwrite netdev dev_adr with admin VF MAC */
8034                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8035                 } else {
8036                         eth_hw_addr_random(bp->dev);
8037                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8038                 }
8039 #endif
8040         }
8041         return rc;
8042 }
8043
8044 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8045 {
8046         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8047         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8048
8049         if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
8050             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8051                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8052         else
8053                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8054                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8055                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8056                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8057                             "Unknown", width);
8058 }
8059
8060 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8061 {
8062         static int version_printed;
8063         struct net_device *dev;
8064         struct bnxt *bp;
8065         int rc, max_irqs;
8066
8067         if (pci_is_bridge(pdev))
8068                 return -ENODEV;
8069
8070         if (version_printed++ == 0)
8071                 pr_info("%s", version);
8072
8073         max_irqs = bnxt_get_max_irq(pdev);
8074         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8075         if (!dev)
8076                 return -ENOMEM;
8077
8078         bp = netdev_priv(dev);
8079
8080         if (bnxt_vf_pciid(ent->driver_data))
8081                 bp->flags |= BNXT_FLAG_VF;
8082
8083         if (pdev->msix_cap)
8084                 bp->flags |= BNXT_FLAG_MSIX_CAP;
8085
8086         rc = bnxt_init_board(pdev, dev);
8087         if (rc < 0)
8088                 goto init_err_free;
8089
8090         dev->netdev_ops = &bnxt_netdev_ops;
8091         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8092         dev->ethtool_ops = &bnxt_ethtool_ops;
8093         SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8094         pci_set_drvdata(pdev, dev);
8095
8096         rc = bnxt_alloc_hwrm_resources(bp);
8097         if (rc)
8098                 goto init_err_pci_clean;
8099
8100         mutex_init(&bp->hwrm_cmd_lock);
8101         rc = bnxt_hwrm_ver_get(bp);
8102         if (rc)
8103                 goto init_err_pci_clean;
8104
8105         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8106                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8107                 if (rc)
8108                         goto init_err_pci_clean;
8109         }
8110
8111         rc = bnxt_hwrm_func_reset(bp);
8112         if (rc)
8113                 goto init_err_pci_clean;
8114
8115         bnxt_hwrm_fw_set_time(bp);
8116
8117         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8118                            NETIF_F_TSO | NETIF_F_TSO6 |
8119                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8120                            NETIF_F_GSO_IPXIP4 |
8121                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8122                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8123                            NETIF_F_RXCSUM | NETIF_F_GRO;
8124
8125         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8126                 dev->hw_features |= NETIF_F_LRO;
8127
8128         dev->hw_enc_features =
8129                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8130                         NETIF_F_TSO | NETIF_F_TSO6 |
8131                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8132                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8133                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8134         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8135                                     NETIF_F_GSO_GRE_CSUM;
8136         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8137         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8138                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8139         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8140         dev->priv_flags |= IFF_UNICAST_FLT;
8141
8142         /* MTU range: 60 - 9500 */
8143         dev->min_mtu = ETH_ZLEN;
8144         dev->max_mtu = BNXT_MAX_MTU;
8145
8146 #ifdef CONFIG_BNXT_SRIOV
8147         init_waitqueue_head(&bp->sriov_cfg_wait);
8148         mutex_init(&bp->sriov_lock);
8149 #endif
8150         bp->gro_func = bnxt_gro_func_5730x;
8151         if (BNXT_CHIP_P4_PLUS(bp))
8152                 bp->gro_func = bnxt_gro_func_5731x;
8153         else
8154                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8155
8156         rc = bnxt_hwrm_func_drv_rgtr(bp);
8157         if (rc)
8158                 goto init_err_pci_clean;
8159
8160         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8161         if (rc)
8162                 goto init_err_pci_clean;
8163
8164         bp->ulp_probe = bnxt_ulp_probe;
8165
8166         /* Get the MAX capabilities for this function */
8167         rc = bnxt_hwrm_func_qcaps(bp);
8168         if (rc) {
8169                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8170                            rc);
8171                 rc = -1;
8172                 goto init_err_pci_clean;
8173         }
8174         rc = bnxt_init_mac_addr(bp);
8175         if (rc) {
8176                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8177                 rc = -EADDRNOTAVAIL;
8178                 goto init_err_pci_clean;
8179         }
8180         rc = bnxt_hwrm_queue_qportcfg(bp);
8181         if (rc) {
8182                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8183                            rc);
8184                 rc = -1;
8185                 goto init_err_pci_clean;
8186         }
8187
8188         bnxt_hwrm_func_qcfg(bp);
8189         bnxt_hwrm_port_led_qcaps(bp);
8190         bnxt_ethtool_init(bp);
8191         bnxt_dcb_init(bp);
8192
8193         rc = bnxt_probe_phy(bp);
8194         if (rc)
8195                 goto init_err_pci_clean;
8196
8197         bnxt_set_rx_skb_mode(bp, false);
8198         bnxt_set_tpa_flags(bp);
8199         bnxt_set_ring_params(bp);
8200         bnxt_set_max_func_irqs(bp, max_irqs);
8201         rc = bnxt_set_dflt_rings(bp, true);
8202         if (rc) {
8203                 netdev_err(bp->dev, "Not enough rings available.\n");
8204                 rc = -ENOMEM;
8205                 goto init_err_pci_clean;
8206         }
8207
8208         /* Default RSS hash cfg. */
8209         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8210                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8211                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8212                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8213         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8214                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8215                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8216                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8217         }
8218
8219         bnxt_hwrm_vnic_qcaps(bp);
8220         if (bnxt_rfs_supported(bp)) {
8221                 dev->hw_features |= NETIF_F_NTUPLE;
8222                 if (bnxt_rfs_capable(bp)) {
8223                         bp->flags |= BNXT_FLAG_RFS;
8224                         dev->features |= NETIF_F_NTUPLE;
8225                 }
8226         }
8227
8228         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8229                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8230
8231         rc = bnxt_init_int_mode(bp);
8232         if (rc)
8233                 goto init_err_pci_clean;
8234
8235         bnxt_get_wol_settings(bp);
8236         if (bp->flags & BNXT_FLAG_WOL_CAP)
8237                 device_set_wakeup_enable(&pdev->dev, bp->wol);
8238         else
8239                 device_set_wakeup_capable(&pdev->dev, false);
8240
8241         if (BNXT_PF(bp)) {
8242                 if (!bnxt_pf_wq) {
8243                         bnxt_pf_wq =
8244                                 create_singlethread_workqueue("bnxt_pf_wq");
8245                         if (!bnxt_pf_wq) {
8246                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8247                                 rc = -ENOMEM;
8248                                 goto init_err_pci_clean;
8249                         }
8250                 }
8251                 bnxt_init_tc(bp);
8252         }
8253
8254         rc = register_netdev(dev);
8255         if (rc)
8256                 goto init_err_cleanup_tc;
8257
8258         if (BNXT_PF(bp))
8259                 bnxt_dl_register(bp);
8260
8261         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8262                     board_info[ent->driver_data].name,
8263                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
8264
8265         bnxt_parse_log_pcie_link(bp);
8266
8267         pci_save_state(pdev);
8268         return 0;
8269
8270 init_err_cleanup_tc:
8271         bnxt_shutdown_tc(bp);
8272         bnxt_clear_int_mode(bp);
8273
8274 init_err_pci_clean:
8275         bnxt_free_hwrm_short_cmd_req(bp);
8276         bnxt_free_hwrm_resources(bp);
8277         bnxt_cleanup_pci(bp);
8278
8279 init_err_free:
8280         free_netdev(dev);
8281         return rc;
8282 }
8283
8284 static void bnxt_shutdown(struct pci_dev *pdev)
8285 {
8286         struct net_device *dev = pci_get_drvdata(pdev);
8287         struct bnxt *bp;
8288
8289         if (!dev)
8290                 return;
8291
8292         rtnl_lock();
8293         bp = netdev_priv(dev);
8294         if (!bp)
8295                 goto shutdown_exit;
8296
8297         if (netif_running(dev))
8298                 dev_close(dev);
8299
8300         bnxt_ulp_shutdown(bp);
8301
8302         if (system_state == SYSTEM_POWER_OFF) {
8303                 bnxt_clear_int_mode(bp);
8304                 pci_wake_from_d3(pdev, bp->wol);
8305                 pci_set_power_state(pdev, PCI_D3hot);
8306         }
8307
8308 shutdown_exit:
8309         rtnl_unlock();
8310 }
8311
8312 #ifdef CONFIG_PM_SLEEP
8313 static int bnxt_suspend(struct device *device)
8314 {
8315         struct pci_dev *pdev = to_pci_dev(device);
8316         struct net_device *dev = pci_get_drvdata(pdev);
8317         struct bnxt *bp = netdev_priv(dev);
8318         int rc = 0;
8319
8320         rtnl_lock();
8321         if (netif_running(dev)) {
8322                 netif_device_detach(dev);
8323                 rc = bnxt_close(dev);
8324         }
8325         bnxt_hwrm_func_drv_unrgtr(bp);
8326         rtnl_unlock();
8327         return rc;
8328 }
8329
8330 static int bnxt_resume(struct device *device)
8331 {
8332         struct pci_dev *pdev = to_pci_dev(device);
8333         struct net_device *dev = pci_get_drvdata(pdev);
8334         struct bnxt *bp = netdev_priv(dev);
8335         int rc = 0;
8336
8337         rtnl_lock();
8338         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8339                 rc = -ENODEV;
8340                 goto resume_exit;
8341         }
8342         rc = bnxt_hwrm_func_reset(bp);
8343         if (rc) {
8344                 rc = -EBUSY;
8345                 goto resume_exit;
8346         }
8347         bnxt_get_wol_settings(bp);
8348         if (netif_running(dev)) {
8349                 rc = bnxt_open(dev);
8350                 if (!rc)
8351                         netif_device_attach(dev);
8352         }
8353
8354 resume_exit:
8355         rtnl_unlock();
8356         return rc;
8357 }
8358
8359 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8360 #define BNXT_PM_OPS (&bnxt_pm_ops)
8361
8362 #else
8363
8364 #define BNXT_PM_OPS NULL
8365
8366 #endif /* CONFIG_PM_SLEEP */
8367
8368 /**
8369  * bnxt_io_error_detected - called when PCI error is detected
8370  * @pdev: Pointer to PCI device
8371  * @state: The current pci connection state
8372  *
8373  * This function is called after a PCI bus error affecting
8374  * this device has been detected.
8375  */
8376 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8377                                                pci_channel_state_t state)
8378 {
8379         struct net_device *netdev = pci_get_drvdata(pdev);
8380         struct bnxt *bp = netdev_priv(netdev);
8381
8382         netdev_info(netdev, "PCI I/O error detected\n");
8383
8384         rtnl_lock();
8385         netif_device_detach(netdev);
8386
8387         bnxt_ulp_stop(bp);
8388
8389         if (state == pci_channel_io_perm_failure) {
8390                 rtnl_unlock();
8391                 return PCI_ERS_RESULT_DISCONNECT;
8392         }
8393
8394         if (netif_running(netdev))
8395                 bnxt_close(netdev);
8396
8397         pci_disable_device(pdev);
8398         rtnl_unlock();
8399
8400         /* Request a slot slot reset. */
8401         return PCI_ERS_RESULT_NEED_RESET;
8402 }
8403
8404 /**
8405  * bnxt_io_slot_reset - called after the pci bus has been reset.
8406  * @pdev: Pointer to PCI device
8407  *
8408  * Restart the card from scratch, as if from a cold-boot.
8409  * At this point, the card has exprienced a hard reset,
8410  * followed by fixups by BIOS, and has its config space
8411  * set up identically to what it was at cold boot.
8412  */
8413 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8414 {
8415         struct net_device *netdev = pci_get_drvdata(pdev);
8416         struct bnxt *bp = netdev_priv(netdev);
8417         int err = 0;
8418         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8419
8420         netdev_info(bp->dev, "PCI Slot Reset\n");
8421
8422         rtnl_lock();
8423
8424         if (pci_enable_device(pdev)) {
8425                 dev_err(&pdev->dev,
8426                         "Cannot re-enable PCI device after reset.\n");
8427         } else {
8428                 pci_set_master(pdev);
8429                 pci_restore_state(pdev);
8430                 pci_save_state(pdev);
8431
8432                 err = bnxt_hwrm_func_reset(bp);
8433                 if (!err && netif_running(netdev))
8434                         err = bnxt_open(netdev);
8435
8436                 if (!err) {
8437                         result = PCI_ERS_RESULT_RECOVERED;
8438                         bnxt_ulp_start(bp);
8439                 }
8440         }
8441
8442         if (result != PCI_ERS_RESULT_RECOVERED) {
8443                 if (netif_running(netdev))
8444                         dev_close(netdev);
8445                 pci_disable_device(pdev);
8446         }
8447
8448         rtnl_unlock();
8449
8450         err = pci_cleanup_aer_uncorrect_error_status(pdev);
8451         if (err) {
8452                 dev_err(&pdev->dev,
8453                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8454                          err); /* non-fatal, continue */
8455         }
8456
8457         return result;
8458 }
8459
8460 /**
8461  * bnxt_io_resume - called when traffic can start flowing again.
8462  * @pdev: Pointer to PCI device
8463  *
8464  * This callback is called when the error recovery driver tells
8465  * us that its OK to resume normal operation.
8466  */
8467 static void bnxt_io_resume(struct pci_dev *pdev)
8468 {
8469         struct net_device *netdev = pci_get_drvdata(pdev);
8470
8471         rtnl_lock();
8472
8473         netif_device_attach(netdev);
8474
8475         rtnl_unlock();
8476 }
8477
8478 static const struct pci_error_handlers bnxt_err_handler = {
8479         .error_detected = bnxt_io_error_detected,
8480         .slot_reset     = bnxt_io_slot_reset,
8481         .resume         = bnxt_io_resume
8482 };
8483
8484 static struct pci_driver bnxt_pci_driver = {
8485         .name           = DRV_MODULE_NAME,
8486         .id_table       = bnxt_pci_tbl,
8487         .probe          = bnxt_init_one,
8488         .remove         = bnxt_remove_one,
8489         .shutdown       = bnxt_shutdown,
8490         .driver.pm      = BNXT_PM_OPS,
8491         .err_handler    = &bnxt_err_handler,
8492 #if defined(CONFIG_BNXT_SRIOV)
8493         .sriov_configure = bnxt_sriov_configure,
8494 #endif
8495 };
8496
8497 static int __init bnxt_init(void)
8498 {
8499         return pci_register_driver(&bnxt_pci_driver);
8500 }
8501
8502 static void __exit bnxt_exit(void)
8503 {
8504         pci_unregister_driver(&bnxt_pci_driver);
8505         if (bnxt_pf_wq)
8506                 destroy_workqueue(bnxt_pf_wq);
8507 }
8508
8509 module_init(bnxt_init);
8510 module_exit(bnxt_exit);