1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/netdevice.h>
8 #define IDLE_CHK_E1 0x01
9 #define IDLE_CHK_E1H 0x02
10 #define IDLE_CHK_E2 0x04
11 #define IDLE_CHK_E3A0 0x08
12 #define IDLE_CHK_E3B0 0x10
14 #define IDLE_CHK_ERROR 1
15 #define IDLE_CHK_ERROR_NO_TRAFFIC 2
16 #define IDLE_CHK_WARNING 3
18 #define MAX_FAIL_MSG 256
20 /* statistics and error reporting */
21 static int idle_chk_errors, idle_chk_warnings;
23 /* masks for all chip types */
24 static int is_e1, is_e1h, is_e2, is_e3a0, is_e3b0;
26 /* struct for the argument list for a predicate in the self test databasei */
28 u32 val1; /* value read from first register */
29 u32 val2; /* value read from second register, if applicable */
30 u32 imm1; /* 1st value in predicate condition, left-to-right */
31 u32 imm2; /* 2nd value in predicate condition, left-to-right */
32 u32 imm3; /* 3rd value in predicate condition, left-to-right */
33 u32 imm4; /* 4th value in predicate condition, left-to-right */
36 /* struct representing self test record - a single test */
44 int (*bnx2x_predicate)(struct st_pred_args *pred_args);
48 struct st_pred_args pred_args;
51 /* predicates for self test */
52 static int peq(struct st_pred_args *args)
54 return (args->val1 == args->imm1);
57 static int pneq(struct st_pred_args *args)
59 return (args->val1 != args->imm1);
62 static int pand_neq(struct st_pred_args *args)
64 return ((args->val1 & args->imm1) != args->imm2);
67 static int pand_neq_x2(struct st_pred_args *args)
69 return (((args->val1 & args->imm1) != args->imm2) &&
70 ((args->val1 & args->imm3) != args->imm4));
73 static int pneq_err(struct st_pred_args *args)
75 return ((args->val1 != args->imm1) && (idle_chk_errors > args->imm2));
78 static int pgt(struct st_pred_args *args)
80 return (args->val1 > args->imm1);
83 static int pneq_r2(struct st_pred_args *args)
85 return (args->val1 != args->val2);
88 static int plt_sub_r2(struct st_pred_args *args)
90 return (args->val1 < (args->val2 - args->imm1));
93 static int pne_sub_r2(struct st_pred_args *args)
95 return (args->val1 != (args->val2 - args->imm1));
98 static int prsh_and_neq(struct st_pred_args *args)
100 return (((args->val1 >> args->imm1) & args->imm2) != args->imm3);
103 static int peq_neq_r2(struct st_pred_args *args)
105 return ((args->val1 == args->imm1) && (args->val2 != args->imm2));
108 static int peq_neq_neq_r2(struct st_pred_args *args)
110 return ((args->val1 == args->imm1) && (args->val2 != args->imm2) &&
111 (args->val2 != args->imm3));
114 /* struct holding the database of self test checks (registers and predicates) */
115 /* lines start from 2 since line 1 is heading in csv */
116 #define ST_DB_LINES 468
117 static struct st_record st_database[ST_DB_LINES] = {
118 /*line 2*/{(0x3), 1, 0x2114,
121 "PCIE: ucorr_err_status is not 0",
122 {NA, NA, 0x0FF010, 0, NA, NA} },
124 /*line 3*/{(0x3), 1, 0x2114,
126 NA, IDLE_CHK_WARNING,
127 "PCIE: ucorr_err_status - Unsupported request error",
128 {NA, NA, 0x100000, 0, NA, NA} },
130 /*line 4*/{(0x3), 1, 0x2120,
131 NA, 1, 0, pand_neq_x2,
132 NA, IDLE_CHK_WARNING,
133 "PCIE: corr_err_status is not 0x2000",
134 {NA, NA, 0x31C1, 0x2000, 0x31C1, 0} },
136 /*line 5*/{(0x3), 1, 0x2814,
139 "PCIE: attentions register is not 0x40100",
140 {NA, NA, ~0x40100, 0, NA, NA} },
142 /*line 6*/{(0x2), 1, 0x281c,
145 "PCIE: attentions register is not 0x40040100",
146 {NA, NA, ~0x40040100, 0, NA, NA} },
148 /*line 7*/{(0x2), 1, 0x2820,
151 "PCIE: attentions register is not 0x40040100",
152 {NA, NA, ~0x40040100, 0, NA, NA} },
154 /*line 8*/{(0x3), 1, PXP2_REG_PGL_EXP_ROM2,
156 NA, IDLE_CHK_WARNING,
157 "PXP2: There are outstanding read requests. Not all completios have arrived for read requests on tags that are marked with 0",
158 {NA, NA, 0xffffffff, NA, NA, NA} },
160 /*line 9*/{(0x3), 2, 0x212c,
162 NA, IDLE_CHK_WARNING,
163 "PCIE: error packet header is not 0",
164 {NA, NA, 0, NA, NA, NA} },
166 /*line 10*/{(0x1C), 1, 0x2104,
169 "PCIE: ucorr_err_status is not 0",
170 {NA, NA, 0x0FD010, 0, NA, NA} },
172 /*line 11*/{(0x1C), 1, 0x2104,
174 NA, IDLE_CHK_WARNING,
175 "PCIE: ucorr_err_status - Unsupported request error",
176 {NA, NA, 0x100000, 0, NA, NA} },
178 /*line 12*/{(0x1C), 1, 0x2104,
180 NA, IDLE_CHK_WARNING,
181 "PCIE: ucorr_err_status - Flow Control Protocol Error",
182 {NA, NA, 0x2000, 0, NA, NA} },
184 /*line 13*/{(0x1C), 1, 0x2110,
185 NA, 1, 0, pand_neq_x2,
186 NA, IDLE_CHK_WARNING,
187 "PCIE: corr_err_status is not 0x2000",
188 {NA, NA, 0x31C1, 0x2000, 0x31C1, 0} },
190 /*line 14*/{(0x1C), 1, 0x2814,
192 NA, IDLE_CHK_WARNING,
193 "PCIE: TTX_BRIDGE_FORWARD_ERR - Received master request while BME was 0",
194 {NA, NA, 0x2000000, 0, NA, NA} },
196 /*line 15*/{(0x1C), 1, 0x2814,
199 "PCIE: Func 0 1: attentions register is not 0x2040902",
200 {NA, NA, ~0x2040902, 0, NA, NA} },
202 /*line 16*/{(0x1C), 1, 0x2854,
205 "PCIE: Func 2 3 4: attentions register is not 0x10240902",
206 {NA, NA, ~0x10240902, 0, NA, NA} },
208 /*line 17*/{(0x1C), 1, 0x285c,
211 "PCIE: Func 5 6 7: attentions register is not 0x10240902",
212 {NA, NA, ~0x10240902, 0, NA, NA} },
214 /*line 18*/{(0x18), 1, 0x3040,
217 "PCIE: Overflow in DLP2TLP buffer",
218 {NA, NA, 0x2, 0, NA, NA} },
220 /*line 19*/{(0x1C), 1, PXP2_REG_PGL_EXP_ROM2,
222 NA, IDLE_CHK_WARNING,
223 "PXP2: There are outstanding read requests for tags 0-31. Not all completios have arrived for read requests on tags that are marked with 0",
224 {NA, NA, 0xffffffff, NA, NA, NA} },
226 /*line 20*/{(0x1C), 2, 0x211c,
228 NA, IDLE_CHK_WARNING,
229 "PCIE: error packet header is not 0",
230 {NA, NA, 0, NA, NA, NA} },
232 /*line 21*/{(0x1C), 1, PGLUE_B_REG_INCORRECT_RCV_DETAILS,
235 "PGLUE_B: Packet received from PCIe not according to the rules",
236 {NA, NA, 0, NA, NA, NA} },
238 /*line 22*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_31_0,
240 NA, IDLE_CHK_WARNING,
241 "PGLUE_B: was_error for VFs 0-31 is not 0",
242 {NA, NA, 0, NA, NA, NA} },
244 /*line 23*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_63_32,
246 NA, IDLE_CHK_WARNING,
247 "PGLUE_B: was_error for VFs 32-63 is not 0",
248 {NA, NA, 0, NA, NA, NA} },
250 /*line 24*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_95_64,
252 NA, IDLE_CHK_WARNING,
253 "PGLUE_B: was_error for VFs 64-95 is not 0",
254 {NA, NA, 0, NA, NA, NA} },
256 /*line 25*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_127_96,
258 NA, IDLE_CHK_WARNING,
259 "PGLUE_B: was_error for VFs 96-127 is not 0",
260 {NA, NA, 0, NA, NA, NA} },
262 /*line 26*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_PF_7_0,
264 NA, IDLE_CHK_WARNING,
265 "PGLUE_B: was_error for PFs 0-7 is not 0",
266 {NA, NA, 0, NA, NA, NA} },
268 /*line 27*/{(0x1C), 1, PGLUE_B_REG_RX_ERR_DETAILS,
270 NA, IDLE_CHK_WARNING,
271 "PGLUE_B: Completion received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout; 1 - Unsupported Request; 2 - Completer Abort. (12) - valid bit",
272 {NA, NA, 0, NA, NA, NA} },
274 /*line 28*/{(0x1C), 1, PGLUE_B_REG_RX_TCPL_ERR_DETAILS,
276 NA, IDLE_CHK_WARNING,
277 "PGLUE_B: ATS TCPL received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (16:12) - OTB Entry ID. (17) - valid bit",
278 {NA, NA, 0, NA, NA, NA} },
280 /*line 29*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_31_0,
282 NA, IDLE_CHK_WARNING,
283 "PGLUE_B: Error in master write. Address(31:0) is not 0",
284 {NA, NA, 0, NA, NA, NA} },
286 /*line 30*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_63_32,
288 NA, IDLE_CHK_WARNING,
289 "PGLUE_B: Error in master write. Address(63:32) is not 0",
290 {NA, NA, 0, NA, NA, NA} },
292 /*line 31*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS,
294 NA, IDLE_CHK_WARNING,
295 "PGLUE_B: Error in master write. Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID",
296 {NA, NA, 0, NA, NA, NA} },
298 /*line 32*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS2,
300 NA, IDLE_CHK_WARNING,
301 "PGLUE_B: Error in master write. Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request",
302 {NA, NA, 0, NA, NA, NA} },
304 /*line 33*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_31_0,
306 NA, IDLE_CHK_WARNING,
307 "PGLUE: Error in master read address(31:0) is not 0",
308 {NA, NA, 0, NA, NA, NA} },
310 /*line 34*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_63_32,
312 NA, IDLE_CHK_WARNING,
313 "PGLUE_B: Error in master read address(63:32) is not 0",
314 {NA, NA, 0, NA, NA, NA} },
316 /*line 35*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS,
318 NA, IDLE_CHK_WARNING,
319 "PGLUE_B: Error in master read Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID",
320 {NA, NA, 0, NA, NA, NA} },
322 /*line 36*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS2,
324 NA, IDLE_CHK_WARNING,
325 "PGLUE_B: Error in master read Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request",
326 {NA, NA, 0, NA, NA, NA} },
328 /*line 37*/{(0x1C), 1, PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS,
330 NA, IDLE_CHK_WARNING,
331 "PGLUE_B: Target VF length violation access",
332 {NA, NA, 0, NA, NA, NA} },
334 /*line 38*/{(0x1C), 1, PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS,
336 NA, IDLE_CHK_WARNING,
337 "PGLUE_B: Target VF GRC space access failed permission check",
338 {NA, NA, 0, NA, NA, NA} },
340 /*line 39*/{(0x1C), 1, PGLUE_B_REG_TAGS_63_32,
342 NA, IDLE_CHK_WARNING,
343 "PGLUE_B: There are outstanding read requests for tags 32-63. Not all completios have arrived for read requests on tags that are marked with 0",
344 {NA, NA, 0xffffffff, NA, NA, NA} },
346 /*line 40*/{(0x1C), 3, PXP_REG_HST_VF_DISABLED_ERROR_VALID,
347 PXP_REG_HST_VF_DISABLED_ERROR_DATA, 1, 0, pneq,
348 NA, IDLE_CHK_WARNING,
349 "PXP: Access to disabled VF took place",
350 {NA, NA, 0, NA, NA, NA} },
352 /*line 41*/{(0x1C), 1, PXP_REG_HST_PER_VIOLATION_VALID,
354 NA, IDLE_CHK_WARNING,
355 "PXP: Zone A permission violation occurred",
356 {NA, NA, 0, NA, NA, NA} },
358 /*line 42*/{(0x1C), 1, PXP_REG_HST_INCORRECT_ACCESS_VALID,
360 NA, IDLE_CHK_WARNING,
361 "PXP: Incorrect transaction took place",
362 {NA, NA, 0, NA, NA, NA} },
364 /*line 43*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS,
366 NA, IDLE_CHK_WARNING,
367 "PXP2: Completion received with error. Error details register is not 0. (15:0) - ECHO. (28:16) - Sub Request length plus start_offset_2_0 minus 1",
368 {NA, NA, 0, NA, NA, NA} },
370 /*line 44*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS2,
372 NA, IDLE_CHK_WARNING,
373 "PXP2: Completion received with error. Error details 2nd register is not 0. (4:0) - VQ ID. (8:5) - client ID. (9) - valid bit",
374 {NA, NA, 0, NA, NA, NA} },
376 /*line 45*/{(0x1F), 1, PXP2_REG_RQ_VQ0_ENTRY_CNT,
378 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
379 "PXP2: VQ0 is not empty",
380 {NA, NA, 0, NA, NA, NA} },
382 /*line 46*/{(0x1F), 1, PXP2_REG_RQ_VQ1_ENTRY_CNT,
384 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
385 "PXP2: VQ1 is not empty",
386 {NA, NA, 0, NA, NA, NA} },
388 /*line 47*/{(0x1F), 1, PXP2_REG_RQ_VQ2_ENTRY_CNT,
390 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
391 "PXP2: VQ2 is not empty",
392 {NA, NA, 0, NA, NA, NA} },
394 /*line 48*/{(0x1F), 1, PXP2_REG_RQ_VQ3_ENTRY_CNT,
396 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
397 "PXP2: VQ3 is not empty",
398 {NA, NA, 2, NA, NA, NA} },
400 /*line 49*/{(0x1F), 1, PXP2_REG_RQ_VQ4_ENTRY_CNT,
402 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
403 "PXP2: VQ4 is not empty",
404 {NA, NA, 0, NA, NA, NA} },
406 /*line 50*/{(0x1F), 1, PXP2_REG_RQ_VQ5_ENTRY_CNT,
408 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
409 "PXP2: VQ5 is not empty",
410 {NA, NA, 0, NA, NA, NA} },
412 /*line 51*/{(0x1F), 1, PXP2_REG_RQ_VQ6_ENTRY_CNT,
414 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
415 "PXP2: VQ6 is not empty",
416 {NA, NA, 0, NA, NA, NA} },
418 /*line 52*/{(0x1F), 1, PXP2_REG_RQ_VQ7_ENTRY_CNT,
420 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
421 "PXP2: VQ7 is not empty",
422 {NA, NA, 0, NA, NA, NA} },
424 /*line 53*/{(0x1F), 1, PXP2_REG_RQ_VQ8_ENTRY_CNT,
426 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
427 "PXP2: VQ8 is not empty",
428 {NA, NA, 0, NA, NA, NA} },
430 /*line 54*/{(0x1F), 1, PXP2_REG_RQ_VQ9_ENTRY_CNT,
432 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
433 "PXP2: VQ9 is not empty",
434 {NA, NA, 0, NA, NA, NA} },
436 /*line 55*/{(0x1F), 1, PXP2_REG_RQ_VQ10_ENTRY_CNT,
438 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
439 "PXP2: VQ10 is not empty",
440 {NA, NA, 0, NA, NA, NA} },
442 /*line 56*/{(0x1F), 1, PXP2_REG_RQ_VQ11_ENTRY_CNT,
444 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
445 "PXP2: VQ11 is not empty",
446 {NA, NA, 0, NA, NA, NA} },
448 /*line 57*/{(0x1F), 1, PXP2_REG_RQ_VQ12_ENTRY_CNT,
450 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
451 "PXP2: VQ12 is not empty",
452 {NA, NA, 0, NA, NA, NA} },
454 /*line 58*/{(0x1F), 1, PXP2_REG_RQ_VQ13_ENTRY_CNT,
456 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
457 "PXP2: VQ13 is not empty",
458 {NA, NA, 0, NA, NA, NA} },
460 /*line 59*/{(0x1F), 1, PXP2_REG_RQ_VQ14_ENTRY_CNT,
462 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
463 "PXP2: VQ14 is not empty",
464 {NA, NA, 0, NA, NA, NA} },
466 /*line 60*/{(0x1F), 1, PXP2_REG_RQ_VQ15_ENTRY_CNT,
468 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
469 "PXP2: VQ15 is not empty",
470 {NA, NA, 0, NA, NA, NA} },
472 /*line 61*/{(0x1F), 1, PXP2_REG_RQ_VQ16_ENTRY_CNT,
474 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
475 "PXP2: VQ16 is not empty",
476 {NA, NA, 0, NA, NA, NA} },
478 /*line 62*/{(0x1F), 1, PXP2_REG_RQ_VQ17_ENTRY_CNT,
480 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
481 "PXP2: VQ17 is not empty",
482 {NA, NA, 0, NA, NA, NA} },
484 /*line 63*/{(0x1F), 1, PXP2_REG_RQ_VQ18_ENTRY_CNT,
486 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
487 "PXP2: VQ18 is not empty",
488 {NA, NA, 0, NA, NA, NA} },
490 /*line 64*/{(0x1F), 1, PXP2_REG_RQ_VQ19_ENTRY_CNT,
492 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
493 "PXP2: VQ19 is not empty",
494 {NA, NA, 0, NA, NA, NA} },
496 /*line 65*/{(0x1F), 1, PXP2_REG_RQ_VQ20_ENTRY_CNT,
498 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
499 "PXP2: VQ20 is not empty",
500 {NA, NA, 0, NA, NA, NA} },
502 /*line 66*/{(0x1F), 1, PXP2_REG_RQ_VQ21_ENTRY_CNT,
504 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
505 "PXP2: VQ21 is not empty",
506 {NA, NA, 0, NA, NA, NA} },
508 /*line 67*/{(0x1F), 1, PXP2_REG_RQ_VQ22_ENTRY_CNT,
510 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
511 "PXP2: VQ22 is not empty",
512 {NA, NA, 0, NA, NA, NA} },
514 /*line 68*/{(0x1F), 1, PXP2_REG_RQ_VQ23_ENTRY_CNT,
516 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
517 "PXP2: VQ23 is not empty",
518 {NA, NA, 0, NA, NA, NA} },
520 /*line 69*/{(0x1F), 1, PXP2_REG_RQ_VQ24_ENTRY_CNT,
522 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
523 "PXP2: VQ24 is not empty",
524 {NA, NA, 0, NA, NA, NA} },
526 /*line 70*/{(0x1F), 1, PXP2_REG_RQ_VQ25_ENTRY_CNT,
528 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
529 "PXP2: VQ25 is not empty",
530 {NA, NA, 0, NA, NA, NA} },
532 /*line 71*/{(0x1F), 1, PXP2_REG_RQ_VQ26_ENTRY_CNT,
534 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
535 "PXP2: VQ26 is not empty",
536 {NA, NA, 0, NA, NA, NA} },
538 /*line 72*/{(0x1F), 1, PXP2_REG_RQ_VQ27_ENTRY_CNT,
540 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
541 "PXP2: VQ27 is not empty",
542 {NA, NA, 0, NA, NA, NA} },
544 /*line 73*/{(0x1F), 1, PXP2_REG_RQ_VQ28_ENTRY_CNT,
546 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
547 "PXP2: VQ28 is not empty",
548 {NA, NA, 0, NA, NA, NA} },
550 /*line 74*/{(0x1F), 1, PXP2_REG_RQ_VQ29_ENTRY_CNT,
552 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
553 "PXP2: VQ29 is not empty",
554 {NA, NA, 0, NA, NA, NA} },
556 /*line 75*/{(0x1F), 1, PXP2_REG_RQ_VQ30_ENTRY_CNT,
558 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
559 "PXP2: VQ30 is not empty",
560 {NA, NA, 0, NA, NA, NA} },
562 /*line 76*/{(0x1F), 1, PXP2_REG_RQ_VQ31_ENTRY_CNT,
564 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
565 "PXP2: VQ31 is not empty",
566 {NA, NA, 0, NA, NA, NA} },
568 /*line 77*/{(0x1F), 1, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY,
570 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
571 "PXP2: rq_ufifo_num_of_entry is not 0",
572 {NA, NA, 0, NA, NA, NA} },
574 /*line 78*/{(0x1F), 1, PXP2_REG_RQ_RBC_DONE,
577 "PXP2: rq_rbc_done is not 1",
578 {NA, NA, 1, NA, NA, NA} },
580 /*line 79*/{(0x1F), 1, PXP2_REG_RQ_CFG_DONE,
583 "PXP2: rq_cfg_done is not 1",
584 {NA, NA, 1, NA, NA, NA} },
586 /*line 80*/{(0x3), 1, PXP2_REG_PSWRQ_BW_CREDIT,
588 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
589 "PXP2: rq_read_credit and rq_write_credit are not 3",
590 {NA, NA, 0x1B, NA, NA, NA} },
592 /*line 81*/{(0x1F), 1, PXP2_REG_RD_START_INIT,
595 "PXP2: rd_start_init is not 1",
596 {NA, NA, 1, NA, NA, NA} },
598 /*line 82*/{(0x1F), 1, PXP2_REG_RD_INIT_DONE,
601 "PXP2: rd_init_done is not 1",
602 {NA, NA, 1, NA, NA, NA} },
604 /*line 83*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
605 PXP2_REG_RD_SR_NUM_CFG, 1, 0, pne_sub_r2,
606 NA, IDLE_CHK_WARNING,
607 "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg",
608 {NA, NA, 1, NA, NA, NA} },
610 /*line 84*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
611 PXP2_REG_RD_BLK_NUM_CFG, 1, 0, pneq_r2,
612 NA, IDLE_CHK_WARNING,
613 "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg",
614 {NA, NA, NA, NA, NA, NA} },
616 /*line 85*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
617 PXP2_REG_RD_SR_NUM_CFG, 1, 0, plt_sub_r2,
618 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
619 "PXP2: There are more than two unused SRs",
620 {NA, NA, 3, NA, NA, NA} },
622 /*line 86*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
623 PXP2_REG_RD_BLK_NUM_CFG, 1, 0, plt_sub_r2,
624 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
625 "PXP2: There are more than two unused blocks",
626 {NA, NA, 2, NA, NA, NA} },
628 /*line 87*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_0,
630 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
631 "PXP2: P0 All delivery ports are not idle",
632 {NA, NA, 1, NA, NA, NA} },
634 /*line 88*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_1,
636 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
637 "PXP2: P1 All delivery ports are not idle",
638 {NA, NA, 1, NA, NA, NA} },
640 /*line 89*/{(0x1F), 2, PXP2_REG_RD_ALMOST_FULL_0,
642 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
643 "PXP2: rd_almost_full is not 0",
644 {NA, NA, 0, NA, NA, NA} },
646 /*line 90*/{(0x1F), 1, PXP2_REG_RD_DISABLE_INPUTS,
649 "PXP2: PSWRD inputs are disabled",
650 {NA, NA, 0, NA, NA, NA} },
652 /*line 91*/{(0x1F), 1, PXP2_REG_HST_HEADER_FIFO_STATUS,
654 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
655 "PXP2: HST header FIFO status is not 0",
656 {NA, NA, 0, NA, NA, NA} },
658 /*line 92*/{(0x1F), 1, PXP2_REG_HST_DATA_FIFO_STATUS,
660 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
661 "PXP2: HST data FIFO status is not 0",
662 {NA, NA, 0, NA, NA, NA} },
664 /*line 93*/{(0x3), 1, PXP2_REG_PGL_WRITE_BLOCKED,
667 "PXP2: pgl_write_blocked is not 0",
668 {NA, NA, 0, NA, NA, NA} },
670 /*line 94*/{(0x3), 1, PXP2_REG_PGL_READ_BLOCKED,
673 "PXP2: pgl_read_blocked is not 0",
674 {NA, NA, 0, NA, NA, NA} },
676 /*line 95*/{(0x1C), 1, PXP2_REG_PGL_WRITE_BLOCKED,
678 NA, IDLE_CHK_WARNING,
679 "PXP2: pgl_write_blocked is not 0",
680 {NA, NA, 0, NA, NA, NA} },
682 /*line 96*/{(0x1C), 1, PXP2_REG_PGL_READ_BLOCKED,
684 NA, IDLE_CHK_WARNING,
685 "PXP2: pgl_read_blocked is not 0",
686 {NA, NA, 0, NA, NA, NA} },
688 /*line 97*/{(0x1F), 1, PXP2_REG_PGL_TXW_CDTS,
689 NA, 1, 0, prsh_and_neq,
690 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
691 "PXP2: There is data which is ready",
692 {NA, NA, 17, 1, 0, NA} },
694 /*line 98*/{(0x1F), 1, PXP_REG_HST_ARB_IS_IDLE,
696 NA, IDLE_CHK_WARNING,
697 "PXP: HST arbiter is not idle",
698 {NA, NA, 1, NA, NA, NA} },
700 /*line 99*/{(0x1F), 1, PXP_REG_HST_CLIENTS_WAITING_TO_ARB,
702 NA, IDLE_CHK_WARNING,
703 "PXP: HST one of the clients is waiting for delivery",
704 {NA, NA, 0, NA, NA, NA} },
706 /*line 100*/{(0x1E), 1, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
708 NA, IDLE_CHK_WARNING,
709 "PXP: HST Close the gates: Discarding internal writes",
710 {NA, NA, 0, NA, NA, NA} },
712 /*line 101*/{(0x1E), 1, PXP_REG_HST_DISCARD_DOORBELLS_STATUS,
714 NA, IDLE_CHK_WARNING,
715 "PXP: HST Close the gates: Discarding doorbells",
716 {NA, NA, 0, NA, NA, NA} },
718 /*line 102*/{(0x1C), 1, PXP2_REG_RQ_GARB,
720 NA, IDLE_CHK_WARNING,
721 "PXP2: PSWRQ Close the gates is asserted. Check AEU AFTER_INVERT registers for parity errors",
722 {NA, NA, 0x1000, 0, NA, NA} },
724 /*line 103*/{(0x1F), 1, DMAE_REG_GO_C0,
726 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
727 "DMAE: command 0 go is not 0",
728 {NA, NA, 0, NA, NA, NA} },
730 /*line 104*/{(0x1F), 1, DMAE_REG_GO_C1,
732 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
733 "DMAE: command 1 go is not 0",
734 {NA, NA, 0, NA, NA, NA} },
736 /*line 105*/{(0x1F), 1, DMAE_REG_GO_C2,
738 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
739 "DMAE: command 2 go is not 0",
740 {NA, NA, 0, NA, NA, NA} },
742 /*line 106*/{(0x1F), 1, DMAE_REG_GO_C3,
744 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
745 "DMAE: command 3 go is not 0",
746 {NA, NA, 0, NA, NA, NA} },
748 /*line 107*/{(0x1F), 1, DMAE_REG_GO_C4,
750 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
751 "DMAE: command 4 go is not 0",
752 {NA, NA, 0, NA, NA, NA} },
754 /*line 108*/{(0x1F), 1, DMAE_REG_GO_C5,
756 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
757 "DMAE: command 5 go is not 0",
758 {NA, NA, 0, NA, NA, NA} },
760 /*line 109*/{(0x1F), 1, DMAE_REG_GO_C6,
762 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
763 "DMAE: command 6 go is not 0",
764 {NA, NA, 0, NA, NA, NA} },
766 /*line 110*/{(0x1F), 1, DMAE_REG_GO_C7,
768 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
769 "DMAE: command 7 go is not 0",
770 {NA, NA, 0, NA, NA, NA} },
772 /*line 111*/{(0x1F), 1, DMAE_REG_GO_C8,
774 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
775 "DMAE: command 8 go is not 0",
776 {NA, NA, 0, NA, NA, NA} },
778 /*line 112*/{(0x1F), 1, DMAE_REG_GO_C9,
780 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
781 "DMAE: command 9 go is not 0",
782 {NA, NA, 0, NA, NA, NA} },
784 /*line 113*/{(0x1F), 1, DMAE_REG_GO_C10,
786 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
787 "DMAE: command 10 go is not 0",
788 {NA, NA, 0, NA, NA, NA} },
790 /*line 114*/{(0x1F), 1, DMAE_REG_GO_C11,
792 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
793 "DMAE: command 11 go is not 0",
794 {NA, NA, 0, NA, NA, NA} },
796 /*line 115*/{(0x1F), 1, DMAE_REG_GO_C12,
798 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
799 "DMAE: command 12 go is not 0",
800 {NA, NA, 0, NA, NA, NA} },
802 /*line 116*/{(0x1F), 1, DMAE_REG_GO_C13,
804 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
805 "DMAE: command 13 go is not 0",
806 {NA, NA, 0, NA, NA, NA} },
808 /*line 117*/{(0x1F), 1, DMAE_REG_GO_C14,
810 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
811 "DMAE: command 14 go is not 0",
812 {NA, NA, 0, NA, NA, NA} },
814 /*line 118*/{(0x1F), 1, DMAE_REG_GO_C15,
816 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
817 "DMAE: command 15 go is not 0",
818 {NA, NA, 0, NA, NA, NA} },
820 /*line 119*/{(0x1F), 1, CFC_REG_ERROR_VECTOR,
823 "CFC: error vector is not 0",
824 {NA, NA, 0, NA, NA, NA} },
826 /*line 120*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ARRIVING,
829 "CFC: number of arriving LCIDs is not 0",
830 {NA, NA, 0, NA, NA, NA} },
832 /*line 121*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ALLOC,
835 "CFC: number of alloc LCIDs is not 0",
836 {NA, NA, 0, NA, NA, NA} },
838 /*line 122*/{(0x1F), 1, CFC_REG_NUM_LCIDS_LEAVING,
841 "CFC: number of leaving LCIDs is not 0",
842 {NA, NA, 0, NA, NA, NA} },
844 /*line 123*/{(0x1F), 7, CFC_REG_INFO_RAM,
845 CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_neq_r2,
846 CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
847 "CFC: AC is neither 0 nor 2 on connType 0 (ETH)",
848 {NA, NA, 0, 0, 2, NA} },
850 /*line 124*/{(0x1F), 7, CFC_REG_INFO_RAM,
851 CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2,
852 CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
853 "CFC: AC is not 0 on connType 1 (TOE)",
854 {NA, NA, 1, 0, NA, NA} },
856 /*line 125*/{(0x1F), 7, CFC_REG_INFO_RAM,
857 CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2,
858 CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
859 "CFC: AC is not 0 on connType 3 (iSCSI)",
860 {NA, NA, 3, 0, NA, NA} },
862 /*line 126*/{(0x1F), 7, CFC_REG_INFO_RAM,
863 CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2,
864 CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
865 "CFC: AC is not 0 on connType 4 (FCoE)",
866 {NA, NA, 4, 0, NA, NA} },
868 /*line 127*/{(0x1F), 2, QM_REG_QTASKCTR_0,
870 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
871 "QM: Queue is not empty",
872 {NA, NA, 0, NA, NA, NA} },
874 /*line 128*/{(0xF), 3, QM_REG_VOQCREDIT_0,
875 QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2,
876 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
877 "QM: VOQ_0, VOQ credit is not equal to initial credit",
878 {NA, NA, NA, NA, NA, NA} },
880 /*line 129*/{(0xF), 3, QM_REG_VOQCREDIT_1,
881 QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2,
882 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
883 "QM: VOQ_1, VOQ credit is not equal to initial credit",
884 {NA, NA, NA, NA, NA, NA} },
886 /*line 130*/{(0xF), 3, QM_REG_VOQCREDIT_4,
887 QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2,
888 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
889 "QM: VOQ_4, VOQ credit is not equal to initial credit",
890 {NA, NA, NA, NA, NA, NA} },
892 /*line 131*/{(0x3), 3, QM_REG_PORT0BYTECRD,
893 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
894 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
895 "QM: P0 Byte credit is not equal to initial credit",
896 {NA, NA, NA, NA, NA, NA} },
898 /*line 132*/{(0x3), 3, QM_REG_PORT1BYTECRD,
899 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
900 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
901 "QM: P1 Byte credit is not equal to initial credit",
902 {NA, NA, NA, NA, NA, NA} },
904 /*line 133*/{(0x1F), 1, CCM_REG_CAM_OCCUP,
906 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
907 "CCM: XX protection CAM is not empty",
908 {NA, NA, 0, NA, NA, NA} },
910 /*line 134*/{(0x1F), 1, TCM_REG_CAM_OCCUP,
912 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
913 "TCM: XX protection CAM is not empty",
914 {NA, NA, 0, NA, NA, NA} },
916 /*line 135*/{(0x1F), 1, UCM_REG_CAM_OCCUP,
918 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
919 "UCM: XX protection CAM is not empty",
920 {NA, NA, 0, NA, NA, NA} },
922 /*line 136*/{(0x1F), 1, XCM_REG_CAM_OCCUP,
924 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
925 "XCM: XX protection CAM is not empty",
926 {NA, NA, 0, NA, NA, NA} },
928 /*line 137*/{(0x1F), 1, BRB1_REG_NUM_OF_FULL_BLOCKS,
930 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
931 "BRB1: BRB is not empty",
932 {NA, NA, 0, NA, NA, NA} },
934 /*line 138*/{(0x1F), 1, CSEM_REG_SLEEP_THREADS_VALID,
936 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
937 "CSEM: There are sleeping threads",
938 {NA, NA, 0, NA, NA, NA} },
940 /*line 139*/{(0x1F), 1, TSEM_REG_SLEEP_THREADS_VALID,
942 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
943 "TSEM: There are sleeping threads",
944 {NA, NA, 0, NA, NA, NA} },
946 /*line 140*/{(0x1F), 1, USEM_REG_SLEEP_THREADS_VALID,
948 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
949 "USEM: There are sleeping threads",
950 {NA, NA, 0, NA, NA, NA} },
952 /*line 141*/{(0x1F), 1, XSEM_REG_SLEEP_THREADS_VALID,
954 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
955 "XSEM: There are sleeping threads",
956 {NA, NA, 0, NA, NA, NA} },
958 /*line 142*/{(0x1F), 1, CSEM_REG_SLOW_EXT_STORE_EMPTY,
960 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
961 "CSEM: External store FIFO is not empty",
962 {NA, NA, 1, NA, NA, NA} },
964 /*line 143*/{(0x1F), 1, TSEM_REG_SLOW_EXT_STORE_EMPTY,
966 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
967 "TSEM: External store FIFO is not empty",
968 {NA, NA, 1, NA, NA, NA} },
970 /*line 144*/{(0x1F), 1, USEM_REG_SLOW_EXT_STORE_EMPTY,
972 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
973 "USEM: External store FIFO is not empty",
974 {NA, NA, 1, NA, NA, NA} },
976 /*line 145*/{(0x1F), 1, XSEM_REG_SLOW_EXT_STORE_EMPTY,
978 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
979 "XSEM: External store FIFO is not empty",
980 {NA, NA, 1, NA, NA, NA} },
982 /*line 146*/{(0x1F), 1, CSDM_REG_SYNC_PARSER_EMPTY,
984 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
985 "CSDM: Parser serial FIFO is not empty",
986 {NA, NA, 1, NA, NA, NA} },
988 /*line 147*/{(0x1F), 1, TSDM_REG_SYNC_PARSER_EMPTY,
990 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
991 "TSDM: Parser serial FIFO is not empty",
992 {NA, NA, 1, NA, NA, NA} },
994 /*line 148*/{(0x1F), 1, USDM_REG_SYNC_PARSER_EMPTY,
996 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
997 "USDM: Parser serial FIFO is not empty",
998 {NA, NA, 1, NA, NA, NA} },
1000 /*line 149*/{(0x1F), 1, XSDM_REG_SYNC_PARSER_EMPTY,
1002 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1003 "XSDM: Parser serial FIFO is not empty",
1004 {NA, NA, 1, NA, NA, NA} },
1006 /*line 150*/{(0x1F), 1, CSDM_REG_SYNC_SYNC_EMPTY,
1008 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1009 "CSDM: Parser SYNC serial FIFO is not empty",
1010 {NA, NA, 1, NA, NA, NA} },
1012 /*line 151*/{(0x1F), 1, TSDM_REG_SYNC_SYNC_EMPTY,
1014 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1015 "TSDM: Parser SYNC serial FIFO is not empty",
1016 {NA, NA, 1, NA, NA, NA} },
1018 /*line 152*/{(0x1F), 1, USDM_REG_SYNC_SYNC_EMPTY,
1020 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1021 "USDM: Parser SYNC serial FIFO is not empty",
1022 {NA, NA, 1, NA, NA, NA} },
1024 /*line 153*/{(0x1F), 1, XSDM_REG_SYNC_SYNC_EMPTY,
1026 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1027 "XSDM: Parser SYNC serial FIFO is not empty",
1028 {NA, NA, 1, NA, NA, NA} },
1030 /*line 154*/{(0x1F), 1, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1032 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1033 "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1034 {NA, NA, 1, NA, NA, NA} },
1036 /*line 155*/{(0x1F), 1, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1038 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1039 "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1040 {NA, NA, 1, NA, NA, NA} },
1042 /*line 156*/{(0x1F), 1, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1044 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1045 "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1046 {NA, NA, 1, NA, NA, NA} },
1048 /*line 157*/{(0x1F), 1, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1050 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1051 "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1052 {NA, NA, 1, NA, NA, NA} },
1054 /*line 158*/{(0x1F), 1, DORQ_REG_DQ_FILL_LVLF,
1056 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1057 "DORQ: DORQ queue is not empty",
1058 {NA, NA, 0, NA, NA, NA} },
1060 /*line 159*/{(0x1F), 1, CFC_REG_CFC_INT_STS,
1063 "CFC: Interrupt status is not 0",
1064 {NA, NA, 0, NA, NA, NA} },
1066 /*line 160*/{(0x1F), 1, CDU_REG_CDU_INT_STS,
1069 "CDU: Interrupt status is not 0",
1070 {NA, NA, 0, NA, NA, NA} },
1072 /*line 161*/{(0x1F), 1, CCM_REG_CCM_INT_STS,
1075 "CCM: Interrupt status is not 0",
1076 {NA, NA, 0, NA, NA, NA} },
1078 /*line 162*/{(0x1F), 1, TCM_REG_TCM_INT_STS,
1081 "TCM: Interrupt status is not 0",
1082 {NA, NA, 0, NA, NA, NA} },
1084 /*line 163*/{(0x1F), 1, UCM_REG_UCM_INT_STS,
1087 "UCM: Interrupt status is not 0",
1088 {NA, NA, 0, NA, NA, NA} },
1090 /*line 164*/{(0x1F), 1, XCM_REG_XCM_INT_STS,
1093 "XCM: Interrupt status is not 0",
1094 {NA, NA, 0, NA, NA, NA} },
1096 /*line 165*/{(0xF), 1, PBF_REG_PBF_INT_STS,
1099 "PBF: Interrupt status is not 0",
1100 {NA, NA, 0, NA, NA, NA} },
1102 /*line 166*/{(0x1F), 1, TM_REG_TM_INT_STS,
1105 "TIMERS: Interrupt status is not 0",
1106 {NA, NA, 0, NA, NA, NA} },
1108 /*line 167*/{(0x1F), 1, DORQ_REG_DORQ_INT_STS,
1111 "DORQ: Interrupt status is not 0",
1112 {NA, NA, 0, NA, NA, NA} },
1114 /*line 168*/{(0x1F), 1, SRC_REG_SRC_INT_STS,
1117 "SRCH: Interrupt status is not 0",
1118 {NA, NA, 0, NA, NA, NA} },
1120 /*line 169*/{(0x1F), 1, PRS_REG_PRS_INT_STS,
1123 "PRS: Interrupt status is not 0",
1124 {NA, NA, 0, NA, NA, NA} },
1126 /*line 170*/{(0x1F), 1, BRB1_REG_BRB1_INT_STS,
1129 "BRB1: Interrupt status is not 0",
1130 {NA, NA, ~0xFC00, 0, NA, NA} },
1132 /*line 171*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_INT_STS,
1135 "XPB: Interrupt status is not 0",
1136 {NA, NA, 0, NA, NA, NA} },
1138 /*line 172*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_INT_STS,
1141 "UPB: Interrupt status is not 0",
1142 {NA, NA, 0, NA, NA, NA} },
1144 /*line 173*/{(0x1), 1, PXP2_REG_PXP2_INT_STS,
1146 NA, IDLE_CHK_WARNING,
1147 "PXP2: Interrupt status 0 is not 0",
1148 {NA, NA, 0, NA, NA, NA} },
1150 /*line 174*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_0,
1152 NA, IDLE_CHK_WARNING,
1153 "PXP2: Interrupt status 0 is not 0",
1154 {NA, NA, 0, NA, NA, NA} },
1156 /*line 175*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_1,
1158 NA, IDLE_CHK_WARNING,
1159 "PXP2: Interrupt status 1 is not 0",
1160 {NA, NA, 0, NA, NA, NA} },
1162 /*line 176*/{(0x1F), 1, QM_REG_QM_INT_STS,
1165 "QM: Interrupt status is not 0",
1166 {NA, NA, 0, NA, NA, NA} },
1168 /*line 177*/{(0x1F), 1, PXP_REG_PXP_INT_STS_0,
1170 NA, IDLE_CHK_WARNING,
1171 "PXP: P0 Interrupt status is not 0",
1172 {NA, NA, 0, NA, NA, NA} },
1174 /*line 178*/{(0x1F), 1, PXP_REG_PXP_INT_STS_1,
1176 NA, IDLE_CHK_WARNING,
1177 "PXP: P1 Interrupt status is not 0",
1178 {NA, NA, 0, NA, NA, NA} },
1180 /*line 179*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_INT_STS,
1182 NA, IDLE_CHK_WARNING,
1183 "PGLUE_B: Interrupt status is not 0",
1184 {NA, NA, 0, NA, NA, NA} },
1186 /*line 180*/{(0x1F), 1, DORQ_REG_RSPA_CRD_CNT,
1188 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1189 "DORQ: Credit to XCM is not full",
1190 {NA, NA, 2, NA, NA, NA} },
1192 /*line 181*/{(0x1F), 1, DORQ_REG_RSPB_CRD_CNT,
1194 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1195 "DORQ: Credit to UCM is not full",
1196 {NA, NA, 2, NA, NA, NA} },
1198 /*line 182*/{(0x3), 1, QM_REG_VOQCRDERRREG,
1201 "QM: Credit error register is not 0 (byte or credit overflow/underflow)",
1202 {NA, NA, 0, NA, NA, NA} },
1204 /*line 183*/{(0x1F), 1, DORQ_REG_DQ_FULL_ST,
1207 "DORQ: DORQ queue is full",
1208 {NA, NA, 0, NA, NA, NA} },
1210 /*line 184*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
1212 NA, IDLE_CHK_WARNING,
1213 "AEU: P0 AFTER_INVERT_1 is not 0",
1214 {NA, NA, ~0xCFFC, 0, NA, NA} },
1216 /*line 185*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0,
1219 "AEU: P0 AFTER_INVERT_2 is not 0",
1220 {NA, NA, 0, NA, NA, NA} },
1222 /*line 186*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
1225 "AEU: P0 AFTER_INVERT_3 is not 0",
1226 {NA, NA, ~0xFFFF0000, 0, NA, NA} },
1228 /*line 187*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
1231 "AEU: P0 AFTER_INVERT_4 is not 0",
1232 {NA, NA, ~0x801FFFFF, 0, NA, NA} },
1234 /*line 188*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
1236 NA, IDLE_CHK_WARNING,
1237 "AEU: P1 AFTER_INVERT_1 is not 0",
1238 {NA, NA, ~0xCFFC, 0, NA, NA} },
1240 /*line 189*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1,
1243 "AEU: P1 AFTER_INVERT_2 is not 0",
1244 {NA, NA, 0, NA, NA, NA} },
1246 /*line 190*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
1249 "AEU: P1 AFTER_INVERT_3 is not 0",
1250 {NA, NA, ~0xFFFF0000, 0, NA, NA} },
1252 /*line 191*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
1255 "AEU: P1 AFTER_INVERT_4 is not 0",
1256 {NA, NA, ~0x801FFFFF, 0, NA, NA} },
1258 /*line 192*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_MCP,
1260 NA, IDLE_CHK_WARNING,
1261 "AEU: MCP AFTER_INVERT_1 is not 0",
1262 {NA, NA, ~0xCFFC, 0, NA, NA} },
1264 /*line 193*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_MCP,
1267 "AEU: MCP AFTER_INVERT_2 is not 0",
1268 {NA, NA, 0, NA, NA, NA} },
1270 /*line 194*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_MCP,
1273 "AEU: MCP AFTER_INVERT_3 is not 0",
1274 {NA, NA, ~0xFFFF0000, 0, NA, NA} },
1276 /*line 195*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_MCP,
1279 "AEU: MCP AFTER_INVERT_4 is not 0",
1280 {NA, NA, ~0x801FFFFF, 0, NA, NA} },
1282 /*line 196*/{(0xF), 5, PBF_REG_P0_CREDIT,
1283 PBF_REG_P0_INIT_CRD, 1, 0, pneq_r2,
1284 PBF_REG_DISABLE_NEW_TASK_PROC_P0, IDLE_CHK_ERROR_NO_TRAFFIC,
1285 "PBF: P0 credit is not equal to init_crd",
1286 {NA, NA, NA, NA, NA, NA} },
1288 /*line 197*/{(0xF), 5, PBF_REG_P1_CREDIT,
1289 PBF_REG_P1_INIT_CRD, 1, 0, pneq_r2,
1290 PBF_REG_DISABLE_NEW_TASK_PROC_P1, IDLE_CHK_ERROR_NO_TRAFFIC,
1291 "PBF: P1 credit is not equal to init_crd",
1292 {NA, NA, NA, NA, NA, NA} },
1294 /*line 198*/{(0xF), 3, PBF_REG_P4_CREDIT,
1295 PBF_REG_P4_INIT_CRD, 1, 0, pneq_r2,
1296 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1297 "PBF: P4 credit is not equal to init_crd",
1298 {NA, NA, NA, NA, NA, NA} },
1300 /*line 199*/{(0x10), 5, PBF_REG_CREDIT_Q0,
1301 PBF_REG_INIT_CRD_Q0, 1, 0, pneq_r2,
1302 PBF_REG_DISABLE_NEW_TASK_PROC_Q0, IDLE_CHK_ERROR_NO_TRAFFIC,
1303 "PBF: Q0 credit is not equal to init_crd",
1304 {NA, NA, NA, NA, NA, NA} },
1306 /*line 200*/{(0x10), 5, PBF_REG_CREDIT_Q1,
1307 PBF_REG_INIT_CRD_Q1, 1, 0, pneq_r2,
1308 PBF_REG_DISABLE_NEW_TASK_PROC_Q1, IDLE_CHK_ERROR_NO_TRAFFIC,
1309 "PBF: Q1 credit is not equal to init_crd",
1310 {NA, NA, NA, NA, NA, NA} },
1312 /*line 201*/{(0x10), 5, PBF_REG_CREDIT_Q2,
1313 PBF_REG_INIT_CRD_Q2, 1, 0, pneq_r2,
1314 PBF_REG_DISABLE_NEW_TASK_PROC_Q2, IDLE_CHK_ERROR_NO_TRAFFIC,
1315 "PBF: Q2 credit is not equal to init_crd",
1316 {NA, NA, NA, NA, NA, NA} },
1318 /*line 202*/{(0x10), 5, PBF_REG_CREDIT_Q3,
1319 PBF_REG_INIT_CRD_Q3, 1, 0, pneq_r2,
1320 PBF_REG_DISABLE_NEW_TASK_PROC_Q3, IDLE_CHK_ERROR_NO_TRAFFIC,
1321 "PBF: Q3 credit is not equal to init_crd",
1322 {NA, NA, NA, NA, NA, NA} },
1324 /*line 203*/{(0x10), 5, PBF_REG_CREDIT_Q4,
1325 PBF_REG_INIT_CRD_Q4, 1, 0, pneq_r2,
1326 PBF_REG_DISABLE_NEW_TASK_PROC_Q4, IDLE_CHK_ERROR_NO_TRAFFIC,
1327 "PBF: Q4 credit is not equal to init_crd",
1328 {NA, NA, NA, NA, NA, NA} },
1330 /*line 204*/{(0x10), 5, PBF_REG_CREDIT_Q5,
1331 PBF_REG_INIT_CRD_Q5, 1, 0, pneq_r2,
1332 PBF_REG_DISABLE_NEW_TASK_PROC_Q5, IDLE_CHK_ERROR_NO_TRAFFIC,
1333 "PBF: Q5 credit is not equal to init_crd",
1334 {NA, NA, NA, NA, NA, NA} },
1336 /*line 205*/{(0x10), 3, PBF_REG_CREDIT_LB_Q,
1337 PBF_REG_INIT_CRD_LB_Q, 1, 0, pneq_r2,
1338 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1339 "PBF: LB Q credit is not equal to init_crd",
1340 {NA, NA, NA, NA, NA, NA} },
1342 /*line 206*/{(0xF), 1, PBF_REG_P0_TASK_CNT,
1344 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1345 "PBF: P0 task_cnt is not 0",
1346 {NA, NA, 0, NA, NA, NA} },
1348 /*line 207*/{(0xF), 1, PBF_REG_P1_TASK_CNT,
1350 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1351 "PBF: P1 task_cnt is not 0",
1352 {NA, NA, 0, NA, NA, NA} },
1354 /*line 208*/{(0xF), 1, PBF_REG_P4_TASK_CNT,
1356 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1357 "PBF: P4 task_cnt is not 0",
1358 {NA, NA, 0, NA, NA, NA} },
1360 /*line 209*/{(0x10), 1, PBF_REG_TASK_CNT_Q0,
1362 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1363 "PBF: Q0 task_cnt is not 0",
1364 {NA, NA, 0, NA, NA, NA} },
1366 /*line 210*/{(0x10), 1, PBF_REG_TASK_CNT_Q1,
1368 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1369 "PBF: Q1 task_cnt is not 0",
1370 {NA, NA, 0, NA, NA, NA} },
1372 /*line 211*/{(0x10), 1, PBF_REG_TASK_CNT_Q2,
1374 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1375 "PBF: Q2 task_cnt is not 0",
1376 {NA, NA, 0, NA, NA, NA} },
1378 /*line 212*/{(0x10), 1, PBF_REG_TASK_CNT_Q3,
1380 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1381 "PBF: Q3 task_cnt is not 0",
1382 {NA, NA, 0, NA, NA, NA} },
1384 /*line 213*/{(0x10), 1, PBF_REG_TASK_CNT_Q4,
1386 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1387 "PBF: Q4 task_cnt is not 0",
1388 {NA, NA, 0, NA, NA, NA} },
1390 /*line 214*/{(0x10), 1, PBF_REG_TASK_CNT_Q5,
1392 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1393 "PBF: Q5 task_cnt is not 0",
1394 {NA, NA, 0, NA, NA, NA} },
1396 /*line 215*/{(0x10), 1, PBF_REG_TASK_CNT_LB_Q,
1398 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1399 "PBF: LB Q task_cnt is not 0",
1400 {NA, NA, 0, NA, NA, NA} },
1402 /*line 216*/{(0x1F), 1, XCM_REG_CFC_INIT_CRD,
1404 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1405 "XCM: CFC_INIT_CRD is not 1",
1406 {NA, NA, 1, NA, NA, NA} },
1408 /*line 217*/{(0x1F), 1, UCM_REG_CFC_INIT_CRD,
1410 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1411 "UCM: CFC_INIT_CRD is not 1",
1412 {NA, NA, 1, NA, NA, NA} },
1414 /*line 218*/{(0x1F), 1, TCM_REG_CFC_INIT_CRD,
1416 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1417 "TCM: CFC_INIT_CRD is not 1",
1418 {NA, NA, 1, NA, NA, NA} },
1420 /*line 219*/{(0x1F), 1, CCM_REG_CFC_INIT_CRD,
1422 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1423 "CCM: CFC_INIT_CRD is not 1",
1424 {NA, NA, 1, NA, NA, NA} },
1426 /*line 220*/{(0x1F), 1, XCM_REG_XQM_INIT_CRD,
1428 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1429 "XCM: XQM_INIT_CRD is not 32",
1430 {NA, NA, 32, NA, NA, NA} },
1432 /*line 221*/{(0x1F), 1, UCM_REG_UQM_INIT_CRD,
1434 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1435 "UCM: UQM_INIT_CRD is not 32",
1436 {NA, NA, 32, NA, NA, NA} },
1438 /*line 222*/{(0x1F), 1, TCM_REG_TQM_INIT_CRD,
1440 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1441 "TCM: TQM_INIT_CRD is not 32",
1442 {NA, NA, 32, NA, NA, NA} },
1444 /*line 223*/{(0x1F), 1, CCM_REG_CQM_INIT_CRD,
1446 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1447 "CCM: CQM_INIT_CRD is not 32",
1448 {NA, NA, 32, NA, NA, NA} },
1450 /*line 224*/{(0x1F), 1, XCM_REG_TM_INIT_CRD,
1452 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1453 "XCM: TM_INIT_CRD is not 4",
1454 {NA, NA, 4, NA, NA, NA} },
1456 /*line 225*/{(0x1F), 1, UCM_REG_TM_INIT_CRD,
1458 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1459 "UCM: TM_INIT_CRD is not 4",
1460 {NA, NA, 4, NA, NA, NA} },
1462 /*line 226*/{(0x1F), 1, XCM_REG_FIC0_INIT_CRD,
1464 NA, IDLE_CHK_WARNING,
1465 "XCM: FIC0_INIT_CRD is not 64",
1466 {NA, NA, 64, NA, NA, NA} },
1468 /*line 227*/{(0x1F), 1, UCM_REG_FIC0_INIT_CRD,
1470 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1471 "UCM: FIC0_INIT_CRD is not 64",
1472 {NA, NA, 64, NA, NA, NA} },
1474 /*line 228*/{(0x1F), 1, TCM_REG_FIC0_INIT_CRD,
1476 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1477 "TCM: FIC0_INIT_CRD is not 64",
1478 {NA, NA, 64, NA, NA, NA} },
1480 /*line 229*/{(0x1F), 1, CCM_REG_FIC0_INIT_CRD,
1482 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1483 "CCM: FIC0_INIT_CRD is not 64",
1484 {NA, NA, 64, NA, NA, NA} },
1486 /*line 230*/{(0x1F), 1, XCM_REG_FIC1_INIT_CRD,
1488 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1489 "XCM: FIC1_INIT_CRD is not 64",
1490 {NA, NA, 64, NA, NA, NA} },
1492 /*line 231*/{(0x1F), 1, UCM_REG_FIC1_INIT_CRD,
1494 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1495 "UCM: FIC1_INIT_CRD is not 64",
1496 {NA, NA, 64, NA, NA, NA} },
1498 /*line 232*/{(0x1F), 1, TCM_REG_FIC1_INIT_CRD,
1500 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1501 "TCM: FIC1_INIT_CRD is not 64",
1502 {NA, NA, 64, NA, NA, NA} },
1504 /*line 233*/{(0x1F), 1, CCM_REG_FIC1_INIT_CRD,
1506 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1507 "CCM: FIC1_INIT_CRD is not 64",
1508 {NA, NA, 64, NA, NA, NA} },
1510 /*line 234*/{(0x1), 1, XCM_REG_XX_FREE,
1512 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1513 "XCM: XX_FREE differs from expected 31",
1514 {NA, NA, 31, NA, NA, NA} },
1516 /*line 235*/{(0x1E), 1, XCM_REG_XX_FREE,
1518 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1519 "XCM: XX_FREE differs from expected 32",
1520 {NA, NA, 32, NA, NA, NA} },
1522 /*line 236*/{(0x1F), 1, UCM_REG_XX_FREE,
1524 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1525 "UCM: XX_FREE differs from expected 27",
1526 {NA, NA, 27, NA, NA, NA} },
1528 /*line 237*/{(0x7), 1, TCM_REG_XX_FREE,
1530 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1531 "TCM: XX_FREE differs from expected 32",
1532 {NA, NA, 32, NA, NA, NA} },
1534 /*line 238*/{(0x18), 1, TCM_REG_XX_FREE,
1536 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1537 "TCM: XX_FREE differs from expected 29",
1538 {NA, NA, 29, NA, NA, NA} },
1540 /*line 239*/{(0x1F), 1, CCM_REG_XX_FREE,
1542 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1543 "CCM: XX_FREE differs from expected 24",
1544 {NA, NA, 24, NA, NA, NA} },
1546 /*line 240*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18000,
1548 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1549 "XSEM: FOC0 credit less than initial credit",
1550 {NA, NA, 0, NA, NA, NA} },
1552 /*line 241*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18040,
1554 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1555 "XSEM: FOC1 credit less than initial credit",
1556 {NA, NA, 24, NA, NA, NA} },
1558 /*line 242*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18080,
1560 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1561 "XSEM: FOC2 credit less than initial credit",
1562 {NA, NA, 12, NA, NA, NA} },
1564 /*line 243*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18000,
1566 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1567 "USEM: FOC0 credit less than initial credit",
1568 {NA, NA, 26, NA, NA, NA} },
1570 /*line 244*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18040,
1572 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1573 "USEM: FOC1 credit less than initial credit",
1574 {NA, NA, 78, NA, NA, NA} },
1576 /*line 245*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18080,
1578 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1579 "USEM: FOC2 credit less than initial credit",
1580 {NA, NA, 16, NA, NA, NA} },
1582 /*line 246*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x180C0,
1584 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1585 "USEM: FOC3 credit less than initial credit",
1586 {NA, NA, 32, NA, NA, NA} },
1588 /*line 247*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18000,
1590 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1591 "TSEM: FOC0 credit less than initial credit",
1592 {NA, NA, 52, NA, NA, NA} },
1594 /*line 248*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18040,
1596 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1597 "TSEM: FOC1 credit less than initial credit",
1598 {NA, NA, 24, NA, NA, NA} },
1600 /*line 249*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18080,
1602 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1603 "TSEM: FOC2 credit less than initial credit",
1604 {NA, NA, 12, NA, NA, NA} },
1606 /*line 250*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x180C0,
1608 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1609 "TSEM: FOC3 credit less than initial credit",
1610 {NA, NA, 32, NA, NA, NA} },
1612 /*line 251*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18000,
1614 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1615 "CSEM: FOC0 credit less than initial credit",
1616 {NA, NA, 16, NA, NA, NA} },
1618 /*line 252*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18040,
1620 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1621 "CSEM: FOC1 credit less than initial credit",
1622 {NA, NA, 18, NA, NA, NA} },
1624 /*line 253*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18080,
1626 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1627 "CSEM: FOC2 credit less than initial credit",
1628 {NA, NA, 48, NA, NA, NA} },
1630 /*line 254*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x180C0,
1632 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1633 "CSEM: FOC3 credit less than initial credit",
1634 {NA, NA, 14, NA, NA, NA} },
1636 /*line 255*/{(0x1F), 1, PRS_REG_TSDM_CURRENT_CREDIT,
1638 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1639 "PRS: TSDM current credit is not 0",
1640 {NA, NA, 0, NA, NA, NA} },
1642 /*line 256*/{(0x1F), 1, PRS_REG_TCM_CURRENT_CREDIT,
1644 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1645 "PRS: TCM current credit is not 0",
1646 {NA, NA, 0, NA, NA, NA} },
1648 /*line 257*/{(0x1F), 1, PRS_REG_CFC_LD_CURRENT_CREDIT,
1650 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1651 "PRS: CFC_LD current credit is not 0",
1652 {NA, NA, 0, NA, NA, NA} },
1654 /*line 258*/{(0x1F), 1, PRS_REG_CFC_SEARCH_CURRENT_CREDIT,
1656 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1657 "PRS: CFC_SEARCH current credit is not 0",
1658 {NA, NA, 0, NA, NA, NA} },
1660 /*line 259*/{(0x1F), 1, PRS_REG_SRC_CURRENT_CREDIT,
1662 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1663 "PRS: SRCH current credit is not 0",
1664 {NA, NA, 0, NA, NA, NA} },
1666 /*line 260*/{(0x1F), 1, PRS_REG_PENDING_BRB_PRS_RQ,
1668 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1669 "PRS: PENDING_BRB_PRS_RQ is not 0",
1670 {NA, NA, 0, NA, NA, NA} },
1672 /*line 261*/{(0x1F), 2, PRS_REG_PENDING_BRB_CAC0_RQ,
1674 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1675 "PRS: PENDING_BRB_CAC_RQ is not 0",
1676 {NA, NA, 0, NA, NA, NA} },
1678 /*line 262*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_LSB,
1680 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1681 "PRS: SERIAL_NUM_STATUS_LSB is not 0",
1682 {NA, NA, 0, NA, NA, NA} },
1684 /*line 263*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_MSB,
1686 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1687 "PRS: SERIAL_NUM_STATUS_MSB is not 0",
1688 {NA, NA, 0, NA, NA, NA} },
1690 /*line 264*/{(0x1F), 1, CDU_REG_ERROR_DATA,
1693 "CDU: ERROR_DATA is not 0",
1694 {NA, NA, 0, NA, NA, NA} },
1696 /*line 265*/{(0x1F), 1, CCM_REG_STORM_LENGTH_MIS,
1699 "CCM: STORM declared message length unequal to actual",
1700 {NA, NA, 0, NA, NA, NA} },
1702 /*line 266*/{(0x1F), 1, CCM_REG_CSDM_LENGTH_MIS,
1705 "CCM: CSDM declared message length unequal to actual",
1706 {NA, NA, 0, NA, NA, NA} },
1708 /*line 267*/{(0x1F), 1, CCM_REG_TSEM_LENGTH_MIS,
1711 "CCM: TSEM declared message length unequal to actual",
1712 {NA, NA, 0, NA, NA, NA} },
1714 /*line 268*/{(0x1F), 1, CCM_REG_XSEM_LENGTH_MIS,
1717 "CCM: XSEM declared message length unequal to actual",
1718 {NA, NA, 0, NA, NA, NA} },
1720 /*line 269*/{(0x1F), 1, CCM_REG_USEM_LENGTH_MIS,
1723 "CCM: USEM declared message length unequal to actual",
1724 {NA, NA, 0, NA, NA, NA} },
1726 /*line 270*/{(0x1F), 1, CCM_REG_PBF_LENGTH_MIS,
1729 "CCM: PBF declared message length unequal to actual",
1730 {NA, NA, 0, NA, NA, NA} },
1732 /*line 271*/{(0x1F), 1, TCM_REG_STORM_LENGTH_MIS,
1735 "TCM: STORM declared message length unequal to actual",
1736 {NA, NA, 0, NA, NA, NA} },
1738 /*line 272*/{(0x1F), 1, TCM_REG_TSDM_LENGTH_MIS,
1741 "TCM: TSDM declared message length unequal to actual",
1742 {NA, NA, 0, NA, NA, NA} },
1744 /*line 273*/{(0x1F), 1, TCM_REG_PRS_LENGTH_MIS,
1747 "TCM: PRS declared message length unequal to actual",
1748 {NA, NA, 0, NA, NA, NA} },
1750 /*line 274*/{(0x1F), 1, TCM_REG_PBF_LENGTH_MIS,
1753 "TCM: PBF declared message length unequal to actual",
1754 {NA, NA, 0, NA, NA, NA} },
1756 /*line 275*/{(0x1F), 1, TCM_REG_USEM_LENGTH_MIS,
1759 "TCM: USEM declared message length unequal to actual",
1760 {NA, NA, 0, NA, NA, NA} },
1762 /*line 276*/{(0x1F), 1, TCM_REG_CSEM_LENGTH_MIS,
1765 "TCM: CSEM declared message length unequal to actual",
1766 {NA, NA, 0, NA, NA, NA} },
1768 /*line 277*/{(0x1F), 1, UCM_REG_STORM_LENGTH_MIS,
1771 "UCM: STORM declared message length unequal to actual",
1772 {NA, NA, 0, NA, NA, NA} },
1774 /*line 278*/{(0x1F), 1, UCM_REG_USDM_LENGTH_MIS,
1777 "UCM: USDM declared message length unequal to actual",
1778 {NA, NA, 0, NA, NA, NA} },
1780 /*line 279*/{(0x1F), 1, UCM_REG_TSEM_LENGTH_MIS,
1783 "UCM: TSEM declared message length unequal to actual",
1784 {NA, NA, 0, NA, NA, NA} },
1786 /*line 280*/{(0x1F), 1, UCM_REG_CSEM_LENGTH_MIS,
1789 "UCM: CSEM declared message length unequal to actual",
1790 {NA, NA, 0, NA, NA, NA} },
1792 /*line 281*/{(0x1F), 1, UCM_REG_XSEM_LENGTH_MIS,
1795 "UCM: XSEM declared message length unequal to actual",
1796 {NA, NA, 0, NA, NA, NA} },
1798 /*line 282*/{(0x1F), 1, UCM_REG_DORQ_LENGTH_MIS,
1801 "UCM: DORQ declared message length unequal to actual",
1802 {NA, NA, 0, NA, NA, NA} },
1804 /*line 283*/{(0x1F), 1, XCM_REG_STORM_LENGTH_MIS,
1807 "XCM: STORM declared message length unequal to actual",
1808 {NA, NA, 0, NA, NA, NA} },
1810 /*line 284*/{(0x1F), 1, XCM_REG_XSDM_LENGTH_MIS,
1813 "XCM: XSDM declared message length unequal to actual",
1814 {NA, NA, 0, NA, NA, NA} },
1816 /*line 285*/{(0x1F), 1, XCM_REG_TSEM_LENGTH_MIS,
1819 "XCM: TSEM declared message length unequal to actual",
1820 {NA, NA, 0, NA, NA, NA} },
1822 /*line 286*/{(0x1F), 1, XCM_REG_CSEM_LENGTH_MIS,
1825 "XCM: CSEM declared message length unequal to actual",
1826 {NA, NA, 0, NA, NA, NA} },
1828 /*line 287*/{(0x1F), 1, XCM_REG_USEM_LENGTH_MIS,
1831 "XCM: USEM declared message length unequal to actual",
1832 {NA, NA, 0, NA, NA, NA} },
1834 /*line 288*/{(0x1F), 1, XCM_REG_DORQ_LENGTH_MIS,
1837 "XCM: DORQ declared message length unequal to actual",
1838 {NA, NA, 0, NA, NA, NA} },
1840 /*line 289*/{(0x1F), 1, XCM_REG_PBF_LENGTH_MIS,
1843 "XCM: PBF declared message length unequal to actual",
1844 {NA, NA, 0, NA, NA, NA} },
1846 /*line 290*/{(0x1F), 1, XCM_REG_NIG0_LENGTH_MIS,
1849 "XCM: NIG0 declared message length unequal to actual",
1850 {NA, NA, 0, NA, NA, NA} },
1852 /*line 291*/{(0x1F), 1, XCM_REG_NIG1_LENGTH_MIS,
1855 "XCM: NIG1 declared message length unequal to actual",
1856 {NA, NA, 0, NA, NA, NA} },
1858 /*line 292*/{(0x1F), 1, QM_REG_XQM_WRC_FIFOLVL,
1860 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1861 "QM: XQM wrc_fifolvl is not 0",
1862 {NA, NA, 0, NA, NA, NA} },
1864 /*line 293*/{(0x1F), 1, QM_REG_UQM_WRC_FIFOLVL,
1866 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1867 "QM: UQM wrc_fifolvl is not 0",
1868 {NA, NA, 0, NA, NA, NA} },
1870 /*line 294*/{(0x1F), 1, QM_REG_TQM_WRC_FIFOLVL,
1872 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1873 "QM: TQM wrc_fifolvl is not 0",
1874 {NA, NA, 0, NA, NA, NA} },
1876 /*line 295*/{(0x1F), 1, QM_REG_CQM_WRC_FIFOLVL,
1878 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1879 "QM: CQM wrc_fifolvl is not 0",
1880 {NA, NA, 0, NA, NA, NA} },
1882 /*line 296*/{(0x1F), 1, QM_REG_QSTATUS_LOW,
1884 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1885 "QM: QSTATUS_LOW is not 0",
1886 {NA, NA, 0, NA, NA, NA} },
1888 /*line 297*/{(0x1F), 1, QM_REG_QSTATUS_HIGH,
1890 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1891 "QM: QSTATUS_HIGH is not 0",
1892 {NA, NA, 0, NA, NA, NA} },
1894 /*line 298*/{(0x1F), 1, QM_REG_PAUSESTATE0,
1896 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1897 "QM: PAUSESTATE0 is not 0",
1898 {NA, NA, 0, NA, NA, NA} },
1900 /*line 299*/{(0x1F), 1, QM_REG_PAUSESTATE1,
1902 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1903 "QM: PAUSESTATE1 is not 0",
1904 {NA, NA, 0, NA, NA, NA} },
1906 /*line 300*/{(0x1F), 1, QM_REG_OVFQNUM,
1909 "QM: OVFQNUM is not 0",
1910 {NA, NA, 0, NA, NA, NA} },
1912 /*line 301*/{(0x1F), 1, QM_REG_OVFERROR,
1915 "QM: OVFERROR is not 0",
1916 {NA, NA, 0, NA, NA, NA} },
1918 /*line 302*/{(0x1F), 6, QM_REG_PTRTBL,
1920 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1921 "QM: read and write variables not equal",
1922 {NA, NA, NA, NA, NA, NA} },
1924 /*line 303*/{(0x1F), 1, BRB1_REG_BRB1_PRTY_STS,
1926 NA, IDLE_CHK_WARNING,
1927 "BRB1: parity status is not 0",
1928 {NA, NA, ~0x8, 0, NA, NA} },
1930 /*line 304*/{(0x1F), 1, CDU_REG_CDU_PRTY_STS,
1932 NA, IDLE_CHK_WARNING,
1933 "CDU: parity status is not 0",
1934 {NA, NA, 0, NA, NA, NA} },
1936 /*line 305*/{(0x1F), 1, CFC_REG_CFC_PRTY_STS,
1938 NA, IDLE_CHK_WARNING,
1939 "CFC: parity status is not 0",
1940 {NA, NA, ~0x2, 0, NA, NA} },
1942 /*line 306*/{(0x1F), 1, CSDM_REG_CSDM_PRTY_STS,
1944 NA, IDLE_CHK_WARNING,
1945 "CSDM: parity status is not 0",
1946 {NA, NA, 0, NA, NA, NA} },
1948 /*line 307*/{(0x3), 1, DBG_REG_DBG_PRTY_STS,
1950 NA, IDLE_CHK_WARNING,
1951 "DBG: parity status is not 0",
1952 {NA, NA, 0, NA, NA, NA} },
1954 /*line 308*/{(0x1F), 1, DMAE_REG_DMAE_PRTY_STS,
1956 NA, IDLE_CHK_WARNING,
1957 "DMAE: parity status is not 0",
1958 {NA, NA, 0, NA, NA, NA} },
1960 /*line 309*/{(0x1F), 1, DORQ_REG_DORQ_PRTY_STS,
1962 NA, IDLE_CHK_WARNING,
1963 "DORQ: parity status is not 0",
1964 {NA, NA, 0, NA, NA, NA} },
1966 /*line 310*/{(0x1), 1, TCM_REG_TCM_PRTY_STS,
1968 NA, IDLE_CHK_WARNING,
1969 "TCM: parity status is not 0",
1970 {NA, NA, ~0x3ffc0, 0, NA, NA} },
1972 /*line 311*/{(0x1E), 1, TCM_REG_TCM_PRTY_STS,
1974 NA, IDLE_CHK_WARNING,
1975 "TCM: parity status is not 0",
1976 {NA, NA, 0, NA, NA, NA} },
1978 /*line 312*/{(0x1), 1, CCM_REG_CCM_PRTY_STS,
1980 NA, IDLE_CHK_WARNING,
1981 "CCM: parity status is not 0",
1982 {NA, NA, ~0x3ffc0, 0, NA, NA} },
1984 /*line 313*/{(0x1E), 1, CCM_REG_CCM_PRTY_STS,
1986 NA, IDLE_CHK_WARNING,
1987 "CCM: parity status is not 0",
1988 {NA, NA, 0, NA, NA, NA} },
1990 /*line 314*/{(0x1), 1, UCM_REG_UCM_PRTY_STS,
1992 NA, IDLE_CHK_WARNING,
1993 "UCM: parity status is not 0",
1994 {NA, NA, ~0x3ffc0, 0, NA, NA} },
1996 /*line 315*/{(0x1E), 1, UCM_REG_UCM_PRTY_STS,
1998 NA, IDLE_CHK_WARNING,
1999 "UCM: parity status is not 0",
2000 {NA, NA, 0, NA, NA, NA} },
2002 /*line 316*/{(0x1), 1, XCM_REG_XCM_PRTY_STS,
2004 NA, IDLE_CHK_WARNING,
2005 "XCM: parity status is not 0",
2006 {NA, NA, ~0x3ffc0, 0, NA, NA} },
2008 /*line 317*/{(0x1E), 1, XCM_REG_XCM_PRTY_STS,
2010 NA, IDLE_CHK_WARNING,
2011 "XCM: parity status is not 0",
2012 {NA, NA, 0, NA, NA, NA} },
2014 /*line 318*/{(0x1), 1, HC_REG_HC_PRTY_STS,
2016 NA, IDLE_CHK_WARNING,
2017 "HC: parity status is not 0",
2018 {NA, NA, ~0x1, 0, NA, NA} },
2020 /*line 319*/{(0x1), 1, MISC_REG_MISC_PRTY_STS,
2022 NA, IDLE_CHK_WARNING,
2023 "MISC: parity status is not 0",
2024 {NA, NA, ~0x1, 0, NA, NA} },
2026 /*line 320*/{(0x1F), 1, PRS_REG_PRS_PRTY_STS,
2028 NA, IDLE_CHK_WARNING,
2029 "PRS: parity status is not 0",
2030 {NA, NA, 0, NA, NA, NA} },
2032 /*line 321*/{(0x1F), 1, PXP_REG_PXP_PRTY_STS,
2034 NA, IDLE_CHK_WARNING,
2035 "PXP: parity status is not 0",
2036 {NA, NA, 0, NA, NA, NA} },
2038 /*line 322*/{(0x1F), 1, QM_REG_QM_PRTY_STS,
2040 NA, IDLE_CHK_WARNING,
2041 "QM: parity status is not 0",
2042 {NA, NA, 0, NA, NA, NA} },
2044 /*line 323*/{(0x1), 1, SRC_REG_SRC_PRTY_STS,
2046 NA, IDLE_CHK_WARNING,
2047 "SRCH: parity status is not 0",
2048 {NA, NA, ~0x4, 0, NA, NA} },
2050 /*line 324*/{(0x1F), 1, TSDM_REG_TSDM_PRTY_STS,
2052 NA, IDLE_CHK_WARNING,
2053 "TSDM: parity status is not 0",
2054 {NA, NA, 0, NA, NA, NA} },
2056 /*line 325*/{(0x1F), 1, USDM_REG_USDM_PRTY_STS,
2058 NA, IDLE_CHK_WARNING,
2059 "USDM: parity status is not 0",
2060 {NA, NA, ~0x20, 0, NA, NA} },
2062 /*line 326*/{(0x1F), 1, XSDM_REG_XSDM_PRTY_STS,
2064 NA, IDLE_CHK_WARNING,
2065 "XSDM: parity status is not 0",
2066 {NA, NA, 0, NA, NA, NA} },
2068 /*line 327*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_PRTY_STS,
2070 NA, IDLE_CHK_WARNING,
2071 "XPB: parity status is not 0",
2072 {NA, NA, 0, NA, NA, NA} },
2074 /*line 328*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_PRTY_STS,
2076 NA, IDLE_CHK_WARNING,
2077 "UPB: parity status is not 0",
2078 {NA, NA, 0, NA, NA, NA} },
2080 /*line 329*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_0,
2082 NA, IDLE_CHK_WARNING,
2083 "CSEM: parity status 0 is not 0",
2084 {NA, NA, 0, NA, NA, NA} },
2086 /*line 330*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_0,
2088 NA, IDLE_CHK_WARNING,
2089 "PXP2: parity status 0 is not 0",
2090 {NA, NA, ~0xfff40020, 0, NA, NA} },
2092 /*line 331*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_0,
2094 NA, IDLE_CHK_WARNING,
2095 "PXP2: parity status 0 is not 0",
2096 {NA, NA, ~0x20, 0, NA, NA} },
2098 /*line 332*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_0,
2100 NA, IDLE_CHK_WARNING,
2101 "TSEM: parity status 0 is not 0",
2102 {NA, NA, 0, NA, NA, NA} },
2104 /*line 333*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_0,
2106 NA, IDLE_CHK_WARNING,
2107 "USEM: parity status 0 is not 0",
2108 {NA, NA, 0, NA, NA, NA} },
2110 /*line 334*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_0,
2112 NA, IDLE_CHK_WARNING,
2113 "XSEM: parity status 0 is not 0",
2114 {NA, NA, 0, NA, NA, NA} },
2116 /*line 335*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_1,
2118 NA, IDLE_CHK_WARNING,
2119 "CSEM: parity status 1 is not 0",
2120 {NA, NA, 0, NA, NA, NA} },
2122 /*line 336*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_1,
2124 NA, IDLE_CHK_WARNING,
2125 "PXP2: parity status 1 is not 0",
2126 {NA, NA, ~0x20, 0, NA, NA} },
2128 /*line 337*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_1,
2130 NA, IDLE_CHK_WARNING,
2131 "PXP2: parity status 1 is not 0",
2132 {NA, NA, 0, NA, NA, NA} },
2134 /*line 338*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_1,
2136 NA, IDLE_CHK_WARNING,
2137 "TSEM: parity status 1 is not 0",
2138 {NA, NA, 0, NA, NA, NA} },
2140 /*line 339*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_1,
2142 NA, IDLE_CHK_WARNING,
2143 "USEM: parity status 1 is not 0",
2144 {NA, NA, 0, NA, NA, NA} },
2146 /*line 340*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_1,
2148 NA, IDLE_CHK_WARNING,
2149 "XSEM: parity status 1 is not 0",
2150 {NA, NA, 0, NA, NA, NA} },
2152 /*line 341*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_PRTY_STS,
2154 NA, IDLE_CHK_WARNING,
2155 "PGLUE_B: parity status is not 0",
2156 {NA, NA, 0, NA, NA, NA} },
2158 /*line 342*/{(0x2), 2, QM_REG_QTASKCTR_EXT_A_0,
2160 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2161 "QM: Q_EXT_A (upper 64 queues), Queue is not empty",
2162 {NA, NA, 0, NA, NA, NA} },
2164 /*line 343*/{(0x2), 1, QM_REG_QSTATUS_LOW_EXT_A,
2167 "QM: QSTATUS_LOW_EXT_A is not 0",
2168 {NA, NA, 0, NA, NA, NA} },
2170 /*line 344*/{(0x2), 1, QM_REG_QSTATUS_HIGH_EXT_A,
2173 "QM: QSTATUS_HIGH_EXT_A is not 0",
2174 {NA, NA, 0, NA, NA, NA} },
2176 /*line 345*/{(0x1E), 1, QM_REG_PAUSESTATE2,
2178 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2179 "QM: PAUSESTATE2 is not 0",
2180 {NA, NA, 0, NA, NA, NA} },
2182 /*line 346*/{(0x1E), 1, QM_REG_PAUSESTATE3,
2184 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2185 "QM: PAUSESTATE3 is not 0",
2186 {NA, NA, 0, NA, NA, NA} },
2188 /*line 347*/{(0x2), 1, QM_REG_PAUSESTATE4,
2191 "QM: PAUSESTATE4 is not 0",
2192 {NA, NA, 0, NA, NA, NA} },
2194 /*line 348*/{(0x2), 1, QM_REG_PAUSESTATE5,
2197 "QM: PAUSESTATE5 is not 0",
2198 {NA, NA, 0, NA, NA, NA} },
2200 /*line 349*/{(0x2), 1, QM_REG_PAUSESTATE6,
2203 "QM: PAUSESTATE6 is not 0",
2204 {NA, NA, 0, NA, NA, NA} },
2206 /*line 350*/{(0x2), 1, QM_REG_PAUSESTATE7,
2209 "QM: PAUSESTATE7 is not 0",
2210 {NA, NA, 0, NA, NA, NA} },
2212 /*line 351*/{(0x2), 6, QM_REG_PTRTBL_EXT_A,
2214 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2215 "QM: read and write variables not equal in ext table",
2216 {NA, NA, NA, NA, NA, NA} },
2218 /*line 352*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_OCCURRED,
2221 "MISC: system kill occurred;",
2222 {NA, NA, 0, NA, NA, NA} },
2224 /*line 353*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_0,
2227 "MISC: system kill occurred; status_0 register",
2228 {NA, NA, 0, NA, NA, NA} },
2230 /*line 354*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_1,
2233 "MISC: system kill occurred; status_1 register",
2234 {NA, NA, 0, NA, NA, NA} },
2236 /*line 355*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_2,
2239 "MISC: system kill occurred; status_2 register",
2240 {NA, NA, 0, NA, NA, NA} },
2242 /*line 356*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_3,
2245 "MISC: system kill occurred; status_3 register",
2246 {NA, NA, 0, NA, NA, NA} },
2248 /*line 357*/{(0x1E), 1, MISC_REG_PCIE_HOT_RESET,
2250 NA, IDLE_CHK_WARNING,
2251 "MISC: pcie_rst_b was asserted without perst assertion",
2252 {NA, NA, 0, NA, NA, NA} },
2254 /*line 358*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2255 NA, NA, NA, pand_neq,
2257 "NIG: interrupt 0 is active",
2258 {NA, NA, ~0x300, 0, NA, NA} },
2260 /*line 359*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2262 NA, IDLE_CHK_WARNING,
2263 "NIG: Access to BMAC while not active. If tested on FPGA, ignore this warning",
2264 {NA, NA, 0x300, NA, NA, NA} },
2266 /*line 360*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2267 NA, NA, NA, pand_neq,
2269 "NIG: interrupt 1 is active",
2270 {NA, NA, 0x783FF03, 0, NA, NA} },
2272 /*line 361*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2273 NA, NA, NA, pand_neq,
2274 NA, IDLE_CHK_WARNING,
2275 "NIG: port cos was paused too long",
2276 {NA, NA, ~0x783FF0F, 0, NA, NA} },
2278 /*line 362*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2279 NA, NA, NA, pand_neq,
2280 NA, IDLE_CHK_WARNING,
2281 "NIG: Got packets w/o Outer-VLAN in MF mode",
2282 {NA, NA, 0xC, 0, NA, NA} },
2284 /*line 363*/{(0x2), 1, NIG_REG_NIG_PRTY_STS,
2285 NA, NA, NA, pand_neq,
2287 "NIG: parity interrupt is active",
2288 {NA, NA, ~0xFFC00000, 0, NA, NA} },
2290 /*line 364*/{(0x1C), 1, NIG_REG_NIG_PRTY_STS_0,
2291 NA, NA, NA, pand_neq,
2293 "NIG: parity 0 interrupt is active",
2294 {NA, NA, ~0xFFC00000, 0, NA, NA} },
2296 /*line 365*/{(0x4), 1, NIG_REG_NIG_PRTY_STS_1,
2297 NA, NA, NA, pand_neq,
2299 "NIG: parity 1 interrupt is active",
2300 {NA, NA, 0xff, 0, NA, NA} },
2302 /*line 366*/{(0x18), 1, NIG_REG_NIG_PRTY_STS_1,
2305 "NIG: parity 1 interrupt is active",
2306 {NA, NA, 0, NA, NA, NA} },
2308 /*line 367*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2309 NA, NA, NA, pand_neq,
2310 NA, IDLE_CHK_WARNING,
2311 "TSEM: interrupt 0 is active",
2312 {NA, NA, ~0x10000000, 0, NA, NA} },
2314 /*line 368*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2316 NA, IDLE_CHK_WARNING,
2317 "TSEM: interrupt 0 is active",
2318 {NA, NA, 0x10000000, NA, NA, NA} },
2320 /*line 369*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_1,
2323 "TSEM: interrupt 1 is active",
2324 {NA, NA, 0, NA, NA, NA} },
2326 /*line 370*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2327 NA, NA, NA, pand_neq,
2328 NA, IDLE_CHK_WARNING,
2329 "CSEM: interrupt 0 is active",
2330 {NA, NA, ~0x10000000, 0, NA, NA} },
2332 /*line 371*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2334 NA, IDLE_CHK_WARNING,
2335 "CSEM: interrupt 0 is active",
2336 {NA, NA, 0x10000000, NA, NA, NA} },
2338 /*line 372*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_1,
2341 "CSEM: interrupt 1 is active",
2342 {NA, NA, 0, NA, NA, NA} },
2344 /*line 373*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2345 NA, NA, NA, pand_neq,
2346 NA, IDLE_CHK_WARNING,
2347 "USEM: interrupt 0 is active",
2348 {NA, NA, ~0x10000000, 0, NA, NA} },
2350 /*line 374*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2352 NA, IDLE_CHK_WARNING,
2353 "USEM: interrupt 0 is active",
2354 {NA, NA, 0x10000000, NA, NA, NA} },
2356 /*line 375*/{(0x1F), 1, USEM_REG_USEM_INT_STS_1,
2359 "USEM: interrupt 1 is active",
2360 {NA, NA, 0, NA, NA, NA} },
2362 /*line 376*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2363 NA, NA, NA, pand_neq,
2364 NA, IDLE_CHK_WARNING,
2365 "XSEM: interrupt 0 is active",
2366 {NA, NA, ~0x10000000, 0, NA, NA} },
2368 /*line 377*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2370 NA, IDLE_CHK_WARNING,
2371 "XSEM: interrupt 0 is active",
2372 {NA, NA, 0x10000000, NA, NA, NA} },
2374 /*line 378*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_1,
2377 "XSEM: interrupt 1 is active",
2378 {NA, NA, 0, NA, NA, NA} },
2380 /*line 379*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_0,
2383 "TSDM: interrupt 0 is active",
2384 {NA, NA, 0, NA, NA, NA} },
2386 /*line 380*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_1,
2389 "TSDM: interrupt 0 is active",
2390 {NA, NA, 0, NA, NA, NA} },
2392 /*line 381*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_0,
2395 "CSDM: interrupt 0 is active",
2396 {NA, NA, 0, NA, NA, NA} },
2398 /*line 382*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_1,
2401 "CSDM: interrupt 0 is active",
2402 {NA, NA, 0, NA, NA, NA} },
2404 /*line 383*/{(0x1F), 1, USDM_REG_USDM_INT_STS_0,
2407 "USDM: interrupt 0 is active",
2408 {NA, NA, 0, NA, NA, NA} },
2410 /*line 384*/{(0x1F), 1, USDM_REG_USDM_INT_STS_1,
2413 "USDM: interrupt 0 is active",
2414 {NA, NA, 0, NA, NA, NA} },
2416 /*line 385*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_0,
2419 "XSDM: interrupt 0 is active",
2420 {NA, NA, 0, NA, NA, NA} },
2422 /*line 386*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_1,
2425 "XSDM: interrupt 0 is active",
2426 {NA, NA, 0, NA, NA, NA} },
2428 /*line 387*/{(0x2), 1, HC_REG_HC_PRTY_STS,
2430 NA, IDLE_CHK_WARNING,
2431 "HC: parity status is not 0",
2432 {NA, NA, 0, NA, NA, NA} },
2434 /*line 388*/{(0x1E), 1, MISC_REG_MISC_PRTY_STS,
2436 NA, IDLE_CHK_WARNING,
2437 "MISC: parity status is not 0",
2438 {NA, NA, 0, NA, NA, NA} },
2440 /*line 389*/{(0x1E), 1, SRC_REG_SRC_PRTY_STS,
2442 NA, IDLE_CHK_WARNING,
2443 "SRCH: parity status is not 0",
2444 {NA, NA, 0, NA, NA, NA} },
2446 /*line 390*/{(0xC), 3, QM_REG_BYTECRD0,
2447 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2448 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2449 "QM: Byte credit 0 is not equal to initial credit",
2450 {NA, NA, NA, NA, NA, NA} },
2452 /*line 391*/{(0xC), 3, QM_REG_BYTECRD1,
2453 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2454 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2455 "QM: Byte credit 1 is not equal to initial credit",
2456 {NA, NA, NA, NA, NA, NA} },
2458 /*line 392*/{(0xC), 3, QM_REG_BYTECRD2,
2459 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2460 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2461 "QM: Byte credit 2 is not equal to initial credit",
2462 {NA, NA, NA, NA, NA, NA} },
2464 /*line 393*/{(0x1C), 1, QM_REG_VOQCRDERRREG,
2467 "QM: VOQ credit error register is not 0 (VOQ credit overflow/underflow)",
2468 {NA, NA, 0xFFFF, 0, NA, NA} },
2470 /*line 394*/{(0x1C), 1, QM_REG_BYTECRDERRREG,
2473 "QM: Byte credit error register is not 0 (Byte credit overflow/underflow)",
2474 {NA, NA, 0xFFF, 0, NA, NA} },
2476 /*line 395*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_31_0,
2478 NA, IDLE_CHK_WARNING,
2479 "PGL: FLR request is set for VF addresses 31-0",
2480 {NA, NA, 0, NA, NA, NA} },
2482 /*line 396*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_63_32,
2484 NA, IDLE_CHK_WARNING,
2485 "PGL: FLR request is set for VF addresses 63-32",
2486 {NA, NA, 0, NA, NA, NA} },
2488 /*line 397*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_95_64,
2490 NA, IDLE_CHK_WARNING,
2491 "PGL: FLR request is set for VF addresses 95-64",
2492 {NA, NA, 0, NA, NA, NA} },
2494 /*line 398*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_127_96,
2496 NA, IDLE_CHK_WARNING,
2497 "PGL: FLR request is set for VF addresses 127-96",
2498 {NA, NA, 0, NA, NA, NA} },
2500 /*line 399*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_PF_7_0,
2502 NA, IDLE_CHK_WARNING,
2503 "PGL: FLR request is set for PF addresses 7-0",
2504 {NA, NA, 0, NA, NA, NA} },
2506 /*line 400*/{(0x1C), 1, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST,
2508 NA, IDLE_CHK_WARNING,
2509 "PGL: SR-IOV disable request is set",
2510 {NA, NA, 0, NA, NA, NA} },
2512 /*line 401*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_A_REQUEST,
2514 NA, IDLE_CHK_WARNING,
2515 "PGL: Cfg-Space A request is set",
2516 {NA, NA, 0, NA, NA, NA} },
2518 /*line 402*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_B_REQUEST,
2520 NA, IDLE_CHK_WARNING,
2521 "PGL: Cfg-Space B request is set",
2522 {NA, NA, 0, NA, NA, NA} },
2524 /*line 403*/{(0x1C), 1, IGU_REG_ERROR_HANDLING_DATA_VALID,
2526 NA, IDLE_CHK_WARNING,
2527 "IGU: some unauthorized commands arrived to the IGU. Use igu_dump_fifo utility for more details",
2528 {NA, NA, 0, NA, NA, NA} },
2530 /*line 404*/{(0x1C), 1, IGU_REG_ATTN_WRITE_DONE_PENDING,
2532 NA, IDLE_CHK_WARNING,
2533 "IGU attention message write done pending is not empty",
2534 {NA, NA, 0, NA, NA, NA} },
2536 /*line 405*/{(0x1C), 1, IGU_REG_WRITE_DONE_PENDING,
2538 NA, IDLE_CHK_WARNING,
2539 "IGU MSI/MSIX message write done pending is not empty",
2540 {NA, NA, 0, NA, NA, NA} },
2542 /*line 406*/{(0x1C), 1, IGU_REG_IGU_PRTY_STS,
2544 NA, IDLE_CHK_WARNING,
2545 "IGU: parity status is not 0",
2546 {NA, NA, 0, NA, NA, NA} },
2548 /*line 407*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2549 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, 1, 0, pand_neq,
2551 "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_0)",
2552 {NA, NA, 0x4000000, 0, NA, NA} },
2554 /*line 408*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2555 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, 1, 0, pand_neq,
2557 "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_0)",
2558 {NA, NA, 0x4000000, 0, NA, NA} },
2560 /*line 409*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2561 MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, 1, 0, pand_neq,
2563 "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_1)",
2564 {NA, NA, 0x4000000, 0, NA, NA} },
2566 /*line 410*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2567 MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, 1, 0, pand_neq,
2569 "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_1)",
2570 {NA, NA, 0x4000000, 0, NA, NA} },
2572 /*line 411*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2573 MISC_REG_AEU_AFTER_INVERT_4_MCP, 1, 0, pand_neq,
2575 "MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (MCP)",
2576 {NA, NA, 0x4000000, 0, NA, NA} },
2578 /*line 412*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2579 MISC_REG_AEU_AFTER_INVERT_4_MCP, 1, 0, pand_neq,
2581 "MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (MCP)",
2582 {NA, NA, 0x4000000, 0, NA, NA} },
2584 /*line 413*/{(0x1C), 1, IGU_REG_SILENT_DROP,
2587 "Some messages were not executed in the IGU",
2588 {NA, NA, 0, NA, NA, NA} },
2590 /*line 414*/{(0x1C), 1, PXP2_REG_PSWRQ_BW_CREDIT,
2593 "PXP2: rq_read_credit and rq_write_credit are not 5",
2594 {NA, NA, 0x2D, NA, NA, NA} },
2596 /*line 415*/{(0x1C), 1, IGU_REG_SB_CTRL_FSM,
2598 NA, IDLE_CHK_WARNING,
2599 "IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state",
2600 {NA, NA, 0, NA, NA, NA} },
2602 /*line 416*/{(0x1C), 1, IGU_REG_INT_HANDLE_FSM,
2604 NA, IDLE_CHK_WARNING,
2605 "IGU: block is not in idle. INT_HANDLE_FSM should be zero in idle state",
2606 {NA, NA, 0, NA, NA, NA} },
2608 /*line 417*/{(0x1C), 1, IGU_REG_ATTN_FSM,
2610 NA, IDLE_CHK_WARNING,
2611 "IGU: block is not in idle. SB_ATTN_FSMshould be zeroor two in idle state",
2612 {NA, NA, ~0x2, 0, NA, NA} },
2614 /*line 418*/{(0x1C), 1, IGU_REG_CTRL_FSM,
2616 NA, IDLE_CHK_WARNING,
2617 "IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state",
2618 {NA, NA, ~0x1, 0, NA, NA} },
2620 /*line 419*/{(0x1C), 1, IGU_REG_PXP_ARB_FSM,
2622 NA, IDLE_CHK_WARNING,
2623 "IGU: block is not in idle. SB_ARB_FSM should be zero in idle state",
2624 {NA, NA, ~0x1, 0, NA, NA} },
2626 /*line 420*/{(0x1C), 1, IGU_REG_PENDING_BITS_STATUS,
2628 NA, IDLE_CHK_WARNING,
2629 "IGU: block is not in idle. There are pending write done",
2630 {NA, NA, 0, NA, NA, NA} },
2632 /*line 421*/{(0x10), 3, QM_REG_VOQCREDIT_0,
2633 QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2,
2634 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2635 "QM: VOQ_0, VOQ credit is not equal to initial credit",
2636 {NA, NA, NA, NA, NA, NA} },
2638 /*line 422*/{(0x10), 3, QM_REG_VOQCREDIT_1,
2639 QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2,
2640 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2641 "QM: VOQ_1, VOQ credit is not equal to initial credit",
2642 {NA, NA, NA, NA, NA, NA} },
2644 /*line 423*/{(0x10), 3, QM_REG_VOQCREDIT_2,
2645 QM_REG_VOQINITCREDIT_2, 1, 0, pneq_r2,
2646 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2647 "QM: VOQ_2, VOQ credit is not equal to initial credit",
2648 {NA, NA, NA, NA, NA, NA} },
2650 /*line 424*/{(0x10), 3, QM_REG_VOQCREDIT_3,
2651 QM_REG_VOQINITCREDIT_3, 1, 0, pneq_r2,
2652 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2653 "QM: VOQ_3, VOQ credit is not equal to initial credit",
2654 {NA, NA, NA, NA, NA, NA} },
2656 /*line 425*/{(0x10), 3, QM_REG_VOQCREDIT_4,
2657 QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2,
2658 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2659 "QM: VOQ_4, VOQ credit is not equal to initial credit",
2660 {NA, NA, NA, NA, NA, NA} },
2662 /*line 426*/{(0x10), 3, QM_REG_VOQCREDIT_5,
2663 QM_REG_VOQINITCREDIT_5, 1, 0, pneq_r2,
2664 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2665 "QM: VOQ_5, VOQ credit is not equal to initial credit",
2666 {NA, NA, NA, NA, NA, NA} },
2668 /*line 427*/{(0x10), 3, QM_REG_VOQCREDIT_6,
2669 QM_REG_VOQINITCREDIT_6, 1, 0, pneq_r2,
2670 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2671 "QM: VOQ_6 (LB VOQ), VOQ credit is not equal to initial credit",
2672 {NA, NA, NA, NA, NA, NA} },
2674 /*line 428*/{(0x10), 3, QM_REG_BYTECRD0,
2675 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2676 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2677 "QM: Byte credit 0 is not equal to initial credit",
2678 {NA, NA, NA, NA, NA, NA} },
2680 /*line 429*/{(0x10), 3, QM_REG_BYTECRD1,
2681 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2682 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2683 "QM: Byte credit 1 is not equal to initial credit",
2684 {NA, NA, NA, NA, NA, NA} },
2686 /*line 430*/{(0x10), 3, QM_REG_BYTECRD2,
2687 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2688 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2689 "QM: Byte credit 2 is not equal to initial credit",
2690 {NA, NA, NA, NA, NA, NA} },
2692 /*line 431*/{(0x10), 3, QM_REG_BYTECRD3,
2693 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2694 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2695 "QM: Byte credit 3 is not equal to initial credit",
2696 {NA, NA, NA, NA, NA, NA} },
2698 /*line 432*/{(0x10), 3, QM_REG_BYTECRD4,
2699 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2700 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2701 "QM: Byte credit 4 is not equal to initial credit",
2702 {NA, NA, NA, NA, NA, NA} },
2704 /*line 433*/{(0x10), 3, QM_REG_BYTECRD5,
2705 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2706 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2707 "QM: Byte credit 5 is not equal to initial credit",
2708 {NA, NA, NA, NA, NA, NA} },
2710 /*line 434*/{(0x10), 3, QM_REG_BYTECRD6,
2711 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2712 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2713 "QM: Byte credit 6 is not equal to initial credit",
2714 {NA, NA, NA, NA, NA, NA} },
2716 /*line 435*/{(0x10), 1, QM_REG_FWVOQ0TOHWVOQ,
2719 "QM: FwVoq0 is mapped to HwVoq7 (non-TX HwVoq)",
2720 {NA, NA, 0x7, NA, NA, NA} },
2722 /*line 436*/{(0x10), 1, QM_REG_FWVOQ1TOHWVOQ,
2725 "QM: FwVoq1 is mapped to HwVoq7 (non-TX HwVoq)",
2726 {NA, NA, 0x7, NA, NA, NA} },
2728 /*line 437*/{(0x10), 1, QM_REG_FWVOQ2TOHWVOQ,
2731 "QM: FwVoq2 is mapped to HwVoq7 (non-TX HwVoq)",
2732 {NA, NA, 0x7, NA, NA, NA} },
2734 /*line 438*/{(0x10), 1, QM_REG_FWVOQ3TOHWVOQ,
2737 "QM: FwVoq3 is mapped to HwVoq7 (non-TX HwVoq)",
2738 {NA, NA, 0x7, NA, NA, NA} },
2740 /*line 439*/{(0x10), 1, QM_REG_FWVOQ4TOHWVOQ,
2743 "QM: FwVoq4 is mapped to HwVoq7 (non-TX HwVoq)",
2744 {NA, NA, 0x7, NA, NA, NA} },
2746 /*line 440*/{(0x10), 1, QM_REG_FWVOQ5TOHWVOQ,
2749 "QM: FwVoq5 is mapped to HwVoq7 (non-TX HwVoq)",
2750 {NA, NA, 0x7, NA, NA, NA} },
2752 /*line 441*/{(0x10), 1, QM_REG_FWVOQ6TOHWVOQ,
2755 "QM: FwVoq6 is mapped to HwVoq7 (non-TX HwVoq)",
2756 {NA, NA, 0x7, NA, NA, NA} },
2758 /*line 442*/{(0x10), 1, QM_REG_FWVOQ7TOHWVOQ,
2761 "QM: FwVoq7 is mapped to HwVoq7 (non-TX HwVoq)",
2762 {NA, NA, 0x7, NA, NA, NA} },
2764 /*line 443*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT0_EMPTY,
2766 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2767 "NIG: Port 0 EOP FIFO is not empty",
2768 {NA, NA, 1, NA, NA, NA} },
2770 /*line 444*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT1_EMPTY,
2772 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2773 "NIG: Port 1 EOP FIFO is not empty",
2774 {NA, NA, 1, NA, NA, NA} },
2776 /*line 445*/{(0x1F), 1, NIG_REG_INGRESS_EOP_LB_EMPTY,
2778 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2779 "NIG: LB EOP FIFO is not empty",
2780 {NA, NA, 1, NA, NA, NA} },
2782 /*line 446*/{(0x1F), 1, NIG_REG_INGRESS_RMP0_DSCR_EMPTY,
2784 NA, IDLE_CHK_WARNING,
2785 "NIG: Port 0 RX MCP descriptor FIFO is not empty",
2786 {NA, NA, 1, NA, NA, NA} },
2788 /*line 447*/{(0x1F), 1, NIG_REG_INGRESS_RMP1_DSCR_EMPTY,
2790 NA, IDLE_CHK_WARNING,
2791 "NIG: Port 1 RX MCP descriptor FIFO is not empty",
2792 {NA, NA, 1, NA, NA, NA} },
2794 /*line 448*/{(0x1F), 1, NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY,
2796 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2797 "NIG: PBF LB FIFO is not empty",
2798 {NA, NA, 1, NA, NA, NA} },
2800 /*line 449*/{(0x1F), 1, NIG_REG_EGRESS_MNG0_FIFO_EMPTY,
2802 NA, IDLE_CHK_WARNING,
2803 "NIG: Port 0 TX MCP FIFO is not empty",
2804 {NA, NA, 1, NA, NA, NA} },
2806 /*line 450*/{(0x1F), 1, NIG_REG_EGRESS_MNG1_FIFO_EMPTY,
2808 NA, IDLE_CHK_WARNING,
2809 "NIG: Port 1 TX MCP FIFO is not empty",
2810 {NA, NA, 1, NA, NA, NA} },
2812 /*line 451*/{(0x1F), 1, NIG_REG_EGRESS_DEBUG_FIFO_EMPTY,
2814 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2815 "NIG: Debug FIFO is not empty",
2816 {NA, NA, 1, NA, NA, NA} },
2818 /*line 452*/{(0x1F), 1, NIG_REG_EGRESS_DELAY0_EMPTY,
2820 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2821 "NIG: PBF IF0 FIFO is not empty",
2822 {NA, NA, 1, NA, NA, NA} },
2824 /*line 453*/{(0x1F), 1, NIG_REG_EGRESS_DELAY1_EMPTY,
2826 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2827 "NIG: PBF IF1 FIFO is not empty",
2828 {NA, NA, 1, NA, NA, NA} },
2830 /*line 454*/{(0x1F), 1, NIG_REG_LLH0_FIFO_EMPTY,
2832 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2833 "NIG: Port 0 RX LLH FIFO is not empty",
2834 {NA, NA, 1, NA, NA, NA} },
2836 /*line 455*/{(0x1F), 1, NIG_REG_LLH1_FIFO_EMPTY,
2838 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2839 "NIG: Port 1 RX LLH FIFO is not empty",
2840 {NA, NA, 1, NA, NA, NA} },
2842 /*line 456*/{(0x1C), 1, NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY,
2844 NA, IDLE_CHK_WARNING,
2845 "NIG: Port 0 TX MCP FIFO for traffic going to the host is not empty",
2846 {NA, NA, 1, NA, NA, NA} },
2848 /*line 457*/{(0x1C), 1, NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY,
2850 NA, IDLE_CHK_WARNING,
2851 "NIG: Port 1 TX MCP FIFO for traffic going to the host is not empty",
2852 {NA, NA, 1, NA, NA, NA} },
2854 /*line 458*/{(0x1C), 1, NIG_REG_P0_TLLH_FIFO_EMPTY,
2856 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2857 "NIG: Port 0 TX LLH FIFO is not empty",
2858 {NA, NA, 1, NA, NA, NA} },
2860 /*line 459*/{(0x1C), 1, NIG_REG_P1_TLLH_FIFO_EMPTY,
2862 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2863 "NIG: Port 1 TX LLH FIFO is not empty",
2864 {NA, NA, 1, NA, NA, NA} },
2866 /*line 460*/{(0x1C), 1, NIG_REG_P0_HBUF_DSCR_EMPTY,
2868 NA, IDLE_CHK_WARNING,
2869 "NIG: Port 0 RX MCP descriptor FIFO for traffic from the host is not empty",
2870 {NA, NA, 1, NA, NA, NA} },
2872 /*line 461*/{(0x1C), 1, NIG_REG_P1_HBUF_DSCR_EMPTY,
2874 NA, IDLE_CHK_WARNING,
2875 "NIG: Port 1 RX MCP descriptor FIFO for traffic from the host is not empty",
2876 {NA, NA, 1, NA, NA, NA} },
2878 /*line 462*/{(0x18), 1, NIG_REG_P0_RX_MACFIFO_EMPTY,
2880 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2881 "NIG: Port 0 RX MAC interface FIFO is not empty",
2882 {NA, NA, 1, NA, NA, NA} },
2884 /*line 463*/{(0x18), 1, NIG_REG_P1_RX_MACFIFO_EMPTY,
2886 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2887 "NIG: Port 1 RX MAC interface FIFO is not empty",
2888 {NA, NA, 1, NA, NA, NA} },
2890 /*line 464*/{(0x18), 1, NIG_REG_P0_TX_MACFIFO_EMPTY,
2892 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2893 "NIG: Port 0 TX MAC interface FIFO is not empty",
2894 {NA, NA, 1, NA, NA, NA} },
2896 /*line 465*/{(0x18), 1, NIG_REG_P1_TX_MACFIFO_EMPTY,
2898 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2899 "NIG: Port 1 TX MAC interface FIFO is not empty",
2900 {NA, NA, 1, NA, NA, NA} },
2902 /*line 466*/{(0x10), 1, NIG_REG_EGRESS_DELAY2_EMPTY,
2904 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2905 "NIG: PBF IF2 FIFO is not empty",
2906 {NA, NA, 1, NA, NA, NA} },
2908 /*line 467*/{(0x10), 1, NIG_REG_EGRESS_DELAY3_EMPTY,
2910 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2911 "NIG: PBF IF3 FIFO is not empty",
2912 {NA, NA, 1, NA, NA, NA} },
2914 /*line 468*/{(0x10), 1, NIG_REG_EGRESS_DELAY4_EMPTY,
2916 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2917 "NIG: PBF IF4 FIFO is not empty",
2918 {NA, NA, 1, NA, NA, NA} },
2920 /*line 469*/{(0x10), 1, NIG_REG_EGRESS_DELAY5_EMPTY,
2922 NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2923 "NIG: PBF IF5 FIFO is not empty",
2924 {NA, NA, 1, NA, NA, NA} },
2927 /* handle self test fails according to severity and type */
2928 static void bnx2x_self_test_log(struct bnx2x *bp, u8 severity, char *message)
2931 case IDLE_CHK_ERROR:
2932 BNX2X_ERR("ERROR %s", message);
2935 case IDLE_CHK_ERROR_NO_TRAFFIC:
2936 DP(NETIF_MSG_HW, "INFO %s", message);
2938 case IDLE_CHK_WARNING:
2939 DP(NETIF_MSG_HW, "WARNING %s", message);
2940 idle_chk_warnings++;
2945 /* specific test for QM rd/wr pointers and rd/wr banks */
2946 static void bnx2x_idle_chk6(struct bnx2x *bp,
2947 struct st_record *rec, char *message)
2949 u32 rd_ptr, wr_ptr, rd_bank, wr_bank;
2952 for (i = 0; i < rec->loop; i++) {
2954 rec->pred_args.val1 =
2955 REG_RD(bp, rec->reg1 + i * rec->incr);
2956 rec->pred_args.val2 =
2957 REG_RD(bp, rec->reg1 + i * rec->incr + 4);
2959 /* calc read and write pointers */
2960 rd_ptr = ((rec->pred_args.val1 & 0x3FFFFFC0) >> 6);
2961 wr_ptr = ((((rec->pred_args.val1 & 0xC0000000) >> 30) & 0x3) |
2962 ((rec->pred_args.val2 & 0x3FFFFF) << 2));
2964 /* perfrom pointer test */
2965 if (rd_ptr != wr_ptr) {
2966 snprintf(message, MAX_FAIL_MSG,
2967 "QM: PTRTBL entry %d- rd_ptr is not equal to wr_ptr. Values are 0x%x and 0x%x\n",
2969 bnx2x_self_test_log(bp, rec->severity, message);
2972 /* calculate read and write banks */
2973 rd_bank = ((rec->pred_args.val1 & 0x30) >> 4);
2974 wr_bank = (rec->pred_args.val1 & 0x03);
2976 /* perform bank test */
2977 if (rd_bank != wr_bank) {
2978 snprintf(message, MAX_FAIL_MSG,
2979 "QM: PTRTBL entry %d - rd_bank is not equal to wr_bank. Values are 0x%x 0x%x\n",
2980 i, rd_bank, wr_bank);
2981 bnx2x_self_test_log(bp, rec->severity, message);
2986 /* specific test for cfc info ram and cid cam */
2987 static void bnx2x_idle_chk7(struct bnx2x *bp,
2988 struct st_record *rec, char *message)
2992 /* iterate through lcids */
2993 for (i = 0; i < rec->loop; i++) {
2994 /* make sure cam entry is valid (bit 0) */
2995 if ((REG_RD(bp, (rec->reg2 + i * 4)) & 0x1) != 0x1)
2998 /* get connection type (multiple reads due to widebus) */
2999 REG_RD(bp, (rec->reg1 + i * rec->incr));
3000 REG_RD(bp, (rec->reg1 + i * rec->incr + 4));
3001 rec->pred_args.val1 =
3002 REG_RD(bp, (rec->reg1 + i * rec->incr + 8));
3003 REG_RD(bp, (rec->reg1 + i * rec->incr + 12));
3005 /* obtain connection type */
3006 if (is_e1 || is_e1h) {
3007 /* E1 E1H (bits 4..7) */
3008 rec->pred_args.val1 &= 0x78;
3009 rec->pred_args.val1 >>= 3;
3011 /* E2 E3A0 E3B0 (bits 26..29) */
3012 rec->pred_args.val1 &= 0x1E000000;
3013 rec->pred_args.val1 >>= 25;
3016 /* get activity counter value */
3017 rec->pred_args.val2 = REG_RD(bp, rec->reg3 + i * 4);
3019 /* validate ac value is legal for con_type at idle state */
3020 if (rec->bnx2x_predicate(&rec->pred_args)) {
3021 snprintf(message, MAX_FAIL_MSG,
3022 "%s. Values are 0x%x 0x%x\n", rec->fail_msg,
3023 rec->pred_args.val1, rec->pred_args.val2);
3024 bnx2x_self_test_log(bp, rec->severity, message);
3029 /* self test procedure
3030 * scan auto-generated database
3032 * 1. compare chip mask
3033 * 2. determine type (according to maro number)
3036 * 5. collate results and statistics
3038 int bnx2x_idle_chk(struct bnx2x *bp)
3040 u16 i; /* loop counter */
3041 u16 st_ind; /* self test database access index */
3042 struct st_record rec; /* current record variable */
3043 char message[MAX_FAIL_MSG]; /* message to log */
3046 idle_chk_errors = 0;
3047 idle_chk_warnings = 0;
3049 /*create masks for all chip types*/
3050 is_e1 = CHIP_IS_E1(bp);
3051 is_e1h = CHIP_IS_E1H(bp);
3052 is_e2 = CHIP_IS_E2(bp);
3053 is_e3a0 = CHIP_IS_E3A0(bp);
3054 is_e3b0 = CHIP_IS_E3B0(bp);
3056 /*database main loop*/
3057 for (st_ind = 0; st_ind < ST_DB_LINES; st_ind++) {
3058 rec = st_database[st_ind];
3060 /*check if test applies to chip*/
3061 if (!((rec.chip_mask & IDLE_CHK_E1) && is_e1) &&
3062 !((rec.chip_mask & IDLE_CHK_E1H) && is_e1h) &&
3063 !((rec.chip_mask & IDLE_CHK_E2) && is_e2) &&
3064 !((rec.chip_mask & IDLE_CHK_E3A0) && is_e3a0) &&
3065 !((rec.chip_mask & IDLE_CHK_E3B0) && is_e3b0))
3068 /* identify macro */
3069 switch (rec.macro) {
3071 /* read single reg and call predicate */
3072 rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3073 DP(BNX2X_MSG_IDLE, "mac1 add %x\n", rec.reg1);
3074 if (rec.bnx2x_predicate(&rec.pred_args)) {
3075 snprintf(message, sizeof(message),
3076 "%s.Value is 0x%x\n", rec.fail_msg,
3077 rec.pred_args.val1);
3078 bnx2x_self_test_log(bp, rec.severity, message);
3082 /* read repeatedly starting from reg1 and call
3083 * predicate after each read
3085 for (i = 0; i < rec.loop; i++) {
3086 rec.pred_args.val1 =
3087 REG_RD(bp, rec.reg1 + i * rec.incr);
3088 DP(BNX2X_MSG_IDLE, "mac2 add %x\n", rec.reg1);
3089 if (rec.bnx2x_predicate(&rec.pred_args)) {
3090 snprintf(message, sizeof(message),
3091 "%s. Value is 0x%x in loop %d\n",
3093 rec.pred_args.val1, i);
3094 bnx2x_self_test_log(bp, rec.severity,
3100 /* read two regs and call predicate */
3101 rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3102 rec.pred_args.val2 = REG_RD(bp, rec.reg2);
3103 DP(BNX2X_MSG_IDLE, "mac3 add1 %x add2 %x\n",
3104 rec.reg1, rec.reg2);
3105 if (rec.bnx2x_predicate(&rec.pred_args)) {
3106 snprintf(message, sizeof(message),
3107 "%s. Values are 0x%x 0x%x\n",
3108 rec.fail_msg, rec.pred_args.val1,
3109 rec.pred_args.val2);
3110 bnx2x_self_test_log(bp, rec.severity, message);
3115 for (i = 0; i < rec.loop; i++) {
3116 rec.pred_args.val1 =
3117 REG_RD(bp, rec.reg1 + i * rec.incr);
3118 rec.pred_args.val2 =
3120 rec.reg2 + i * rec.incr)) >> 1;
3121 if (rec.bnx2x_predicate(&rec.pred_args)) {
3122 snprintf(message, sizeof(message),
3123 "%s. Values are 0x%x 0x%x in loop %d\n",
3126 rec.pred_args.val2, i);
3127 bnx2x_self_test_log(bp, rec.severity,
3133 /* compare two regs, pending
3134 * the value of a condition reg
3136 rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3137 rec.pred_args.val2 = REG_RD(bp, rec.reg2);
3138 DP(BNX2X_MSG_IDLE, "mac3 add1 %x add2 %x add3 %x\n",
3139 rec.reg1, rec.reg2, rec.reg3);
3140 if (REG_RD(bp, rec.reg3) != 0) {
3141 if (rec.bnx2x_predicate(&rec.pred_args)) {
3142 snprintf(message, sizeof(message),
3143 "%s. Values are 0x%x 0x%x\n",
3146 rec.pred_args.val2);
3147 bnx2x_self_test_log(bp, rec.severity,
3153 /* compare read and write pointers
3154 * and read and write banks in QM
3156 bnx2x_idle_chk6(bp, &rec, message);
3159 /* compare cfc info cam with cid cam */
3160 bnx2x_idle_chk7(bp, &rec, message);
3164 "unknown macro in self test data base. macro %d line %d",
3169 /* abort if interface is not running */
3170 if (!netif_running(bp->dev))
3171 return idle_chk_errors;
3173 /* return value accorindg to statistics */
3174 if (idle_chk_errors == 0) {
3176 "completed successfully (logged %d warnings)\n",
3179 BNX2X_ERR("failed (with %d errors, %d warnings)\n",
3180 idle_chk_errors, idle_chk_warnings);
3182 return idle_chk_errors;