drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62
  63 #include "bnx2x.h"
  64 #include "bnx2x_init.h"
  65 #include "bnx2x_init_ops.h"
  66 #include "bnx2x_cmn.h"
  67 #include "bnx2x_vfpf.h"
  68 #include "bnx2x_dcb.h"
  69 #include "bnx2x_sp.h"
  70 #include <linux/firmware.h>
  71 #include "bnx2x_fw_file_hdr.h"
  72 /* FW files */
  73 /*(DEBLOBBED)*/
  74 #define FW_FILE_NAME_E1         "/*(DEBLOBBED)*/"
  75 #define FW_FILE_NAME_E1H        "/*(DEBLOBBED)*/"
  76 #define FW_FILE_NAME_E2         "/*(DEBLOBBED)*/"
  77 #define bnx2x_init_block(bp, start, end) \
  78   return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
  79           -EINVAL)
  80
  81 /* Time in jiffies before concluding the transmitter is hung */
  82 #define TX_TIMEOUT              (5*HZ)
  83
  84 static char version[] =
  85         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  87
  88 MODULE_AUTHOR("Eliezer Tamir");
  89 MODULE_DESCRIPTION("QLogic "
  90                    "BCM57710/57711/57711E/"
  91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  92                    "57840/57840_MF Driver");
  93 MODULE_LICENSE("GPL");
  94 MODULE_VERSION(DRV_MODULE_VERSION);
  95 /*(DEBLOBBED)*/
  96
  97 int bnx2x_num_queues;
  98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, S_IRUGO);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 static int int_mode;
 107 module_param(int_mode, int, S_IRUGO);
 108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 109                                 "(1 INT#x; 2 MSI)");
 110
 111 static int dropless_fc;
 112 module_param(dropless_fc, int, S_IRUGO);
 113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, S_IRUGO);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, S_IRUGO);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 static struct workqueue_struct *bnx2x_wq;
 124 struct workqueue_struct *bnx2x_iov_wq;
 125
 126 struct bnx2x_mac_vals {
 127         u32 xmac_addr;
 128         u32 xmac_val;
 129         u32 emac_addr;
 130         u32 emac_val;
 131         u32 umac_addr[2];
 132         u32 umac_val[2];
 133         u32 bmac_addr;
 134         u32 bmac_val[2];
 135 };
 136
 137 enum bnx2x_board_type {
 138         BCM57710 = 0,
 139         BCM57711,
 140         BCM57711E,
 141         BCM57712,
 142         BCM57712_MF,
 143         BCM57712_VF,
 144         BCM57800,
 145         BCM57800_MF,
 146         BCM57800_VF,
 147         BCM57810,
 148         BCM57810_MF,
 149         BCM57810_VF,
 150         BCM57840_4_10,
 151         BCM57840_2_20,
 152         BCM57840_MF,
 153         BCM57840_VF,
 154         BCM57811,
 155         BCM57811_MF,
 156         BCM57840_O,
 157         BCM57840_MFO,
 158         BCM57811_VF
 159 };
 160
 161 /* indexed by board_type, above */
 162 static struct {
 163         char *name;
 164 } board_info[] = {
 165         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 166         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 167         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 168         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 169         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 170         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 171         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 172         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 173         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 175         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 176         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 178         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 179         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 181         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 182         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 183         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 184         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 185         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 186 };
 187
 188 #ifndef PCI_DEVICE_ID_NX2_57710
 189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 190 #endif
 191 #ifndef PCI_DEVICE_ID_NX2_57711
 192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711E
 195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57712
 198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57800
 207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57810
 216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57840_O
 222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57811
 243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 250 #endif
 251
 252 static const struct pci_device_id bnx2x_pci_tbl[] = {
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 266         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 273         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286
 287 /* Forward declaration */
 288 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 289 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 290 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 291
 292 /****************************************************************************
 293 * General service functions
 294 ****************************************************************************/
 295
 296 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 297
 298 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 299                                        u32 addr, dma_addr_t mapping)
 300 {
 301         REG_WR(bp,  addr, U64_LO(mapping));
 302         REG_WR(bp,  addr + 4, U64_HI(mapping));
 303 }
 304
 305 static void storm_memset_spq_addr(struct bnx2x *bp,
 306                                   dma_addr_t mapping, u16 abs_fid)
 307 {
 308         u32 addr = XSEM_REG_FAST_MEMORY +
 309                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 310
 311         __storm_memset_dma_mapping(bp, addr, mapping);
 312 }
 313
 314 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 315                                   u16 pf_id)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 324                 pf_id);
 325 }
 326
 327 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 328                                  u8 enable)
 329 {
 330         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 337                 enable);
 338 }
 339
 340 static void storm_memset_eq_data(struct bnx2x *bp,
 341                                  struct event_ring_data *eq_data,
 342                                 u16 pfid)
 343 {
 344         size_t size = sizeof(struct event_ring_data);
 345
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 347
 348         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 349 }
 350
 351 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 352                                  u16 pfid)
 353 {
 354         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 355         REG_WR16(bp, addr, eq_prod);
 356 }
 357
 358 /* used only at init
 359  * locking is done by mcp
 360  */
 361 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 362 {
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 364         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 366                                PCICFG_VENDOR_ID_OFFSET);
 367 }
 368
 369 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 370 {
 371         u32 val;
 372
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 374         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 376                                PCICFG_VENDOR_ID_OFFSET);
 377
 378         return val;
 379 }
 380
 381 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 382 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 383 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 384 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 385 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 386
 387 static void bnx2x_dp_dmae(struct bnx2x *bp,
 388                           struct dmae_command *dmae, int msglvl)
 389 {
 390         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 391         int i;
 392
 393         switch (dmae->opcode & DMAE_COMMAND_DST) {
 394         case DMAE_CMD_DST_PCI:
 395                 if (src_type == DMAE_CMD_SRC_PCI)
 396                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 397                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 398                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 399                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 400                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 401                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 402                            dmae->comp_val);
 403                 else
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_lo >> 2,
 408                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 break;
 412         case DMAE_CMD_DST_GRC:
 413                 if (src_type == DMAE_CMD_SRC_PCI)
 414                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 415                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 416                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 417                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 418                            dmae->len, dmae->dst_addr_lo >> 2,
 419                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 420                            dmae->comp_val);
 421                 else
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src [%08x], len [%d*4], dst [%08x]\n"
 424                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_lo >> 2,
 426                            dmae->len, dmae->dst_addr_lo >> 2,
 427                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 428                            dmae->comp_val);
 429                 break;
 430         default:
 431                 if (src_type == DMAE_CMD_SRC_PCI)
 432                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 433                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 434                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 435                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 436                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 437                            dmae->comp_val);
 438                 else
 439                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 440                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 441                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 442                            dmae->opcode, dmae->src_addr_lo >> 2,
 443                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 444                            dmae->comp_val);
 445                 break;
 446         }
 447
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 449                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 450                    i, *(((u32 *)dmae) + i));
 451 }
 452
 453 /* copy command into DMAE command memory and set DMAE command go */
 454 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 455 {
 456         u32 cmd_offset;
 457         int i;
 458
 459         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 460         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 461                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 462         }
 463         REG_WR(bp, dmae_reg_go_c[idx], 1);
 464 }
 465
 466 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 467 {
 468         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 469                            DMAE_CMD_C_ENABLE);
 470 }
 471
 472 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 473 {
 474         return opcode & ~DMAE_CMD_SRC_RESET;
 475 }
 476
 477 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 478                              bool with_comp, u8 comp_type)
 479 {
 480         u32 opcode = 0;
 481
 482         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 483                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 484
 485         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 486
 487         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 488         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 489                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 490         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 491
 492 #ifdef __BIG_ENDIAN
 493         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 494 #else
 495         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 496 #endif
 497         if (with_comp)
 498                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 499         return opcode;
 500 }
 501
 502 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 503                                       struct dmae_command *dmae,
 504                                       u8 src_type, u8 dst_type)
 505 {
 506         memset(dmae, 0, sizeof(struct dmae_command));
 507
 508         /* set the opcode */
 509         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 510                                          true, DMAE_COMP_PCI);
 511
 512         /* fill in the completion parameters */
 513         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 514         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 515         dmae->comp_val = DMAE_COMP_VAL;
 516 }
 517
 518 /* issue a dmae command over the init-channel and wait for completion */
 519 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 520                                u32 *comp)
 521 {
 522         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 523         int rc = 0;
 524
 525         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 526
 527         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 528          * as long as this code is called both from syscall context and
 529          * from ndo_set_rx_mode() flow that may be called from BH.
 530          */
 531
 532         spin_lock_bh(&bp->dmae_lock);
 533
 534         /* reset completion */
 535         *comp = 0;
 536
 537         /* post the command on the channel used for initializations */
 538         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 539
 540         /* wait for completion */
 541         udelay(5);
 542         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 543
 544                 if (!cnt ||
 545                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 546                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 547                         BNX2X_ERR("DMAE timeout!\n");
 548                         rc = DMAE_TIMEOUT;
 549                         goto unlock;
 550                 }
 551                 cnt--;
 552                 udelay(50);
 553         }
 554         if (*comp & DMAE_PCI_ERR_FLAG) {
 555                 BNX2X_ERR("DMAE PCI error!\n");
 556                 rc = DMAE_PCI_ERROR;
 557         }
 558
 559 unlock:
 560
 561         spin_unlock_bh(&bp->dmae_lock);
 562
 563         return rc;
 564 }
 565
 566 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 567                       u32 len32)
 568 {
 569         int rc;
 570         struct dmae_command dmae;
 571
 572         if (!bp->dmae_ready) {
 573                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 574
 575                 if (CHIP_IS_E1(bp))
 576                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 577                 else
 578                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 579                 return;
 580         }
 581
 582         /* set opcode and fixed command fields */
 583         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 584
 585         /* fill in addresses and len */
 586         dmae.src_addr_lo = U64_LO(dma_addr);
 587         dmae.src_addr_hi = U64_HI(dma_addr);
 588         dmae.dst_addr_lo = dst_addr >> 2;
 589         dmae.dst_addr_hi = 0;
 590         dmae.len = len32;
 591
 592         /* issue the command and wait for completion */
 593         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 594         if (rc) {
 595                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 596 #ifdef BNX2X_STOP_ON_ERROR
 597                 bnx2x_panic();
 598 #endif
 599         }
 600 }
 601
 602 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 603 {
 604         int rc;
 605         struct dmae_command dmae;
 606
 607         if (!bp->dmae_ready) {
 608                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 609                 int i;
 610
 611                 if (CHIP_IS_E1(bp))
 612                         for (i = 0; i < len32; i++)
 613                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 614                 else
 615                         for (i = 0; i < len32; i++)
 616                                 data[i] = REG_RD(bp, src_addr + i*4);
 617
 618                 return;
 619         }
 620
 621         /* set opcode and fixed command fields */
 622         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 623
 624         /* fill in addresses and len */
 625         dmae.src_addr_lo = src_addr >> 2;
 626         dmae.src_addr_hi = 0;
 627         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 628         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 629         dmae.len = len32;
 630
 631         /* issue the command and wait for completion */
 632         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 633         if (rc) {
 634                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 635 #ifdef BNX2X_STOP_ON_ERROR
 636                 bnx2x_panic();
 637 #endif
 638         }
 639 }
 640
 641 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 642                                       u32 addr, u32 len)
 643 {
 644         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 645         int offset = 0;
 646
 647         while (len > dmae_wr_max) {
 648                 bnx2x_write_dmae(bp, phys_addr + offset,
 649                                  addr + offset, dmae_wr_max);
 650                 offset += dmae_wr_max * 4;
 651                 len -= dmae_wr_max;
 652         }
 653
 654         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 655 }
 656
 657 enum storms {
 658            XSTORM,
 659            TSTORM,
 660            CSTORM,
 661            USTORM,
 662            MAX_STORMS
 663 };
 664
 665 #define STORMS_NUM 4
 666 #define REGS_IN_ENTRY 4
 667
 668 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 669                                               enum storms storm,
 670                                               int entry)
 671 {
 672         switch (storm) {
 673         case XSTORM:
 674                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 675         case TSTORM:
 676                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 677         case CSTORM:
 678                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 679         case USTORM:
 680                 return USTORM_ASSERT_LIST_OFFSET(entry);
 681         case MAX_STORMS:
 682         default:
 683                 BNX2X_ERR("unknown storm\n");
 684         }
 685         return -EINVAL;
 686 }
 687
 688 static int bnx2x_mc_assert(struct bnx2x *bp)
 689 {
 690         char last_idx;
 691         int i, j, rc = 0;
 692         enum storms storm;
 693         u32 regs[REGS_IN_ENTRY];
 694         u32 bar_storm_intmem[STORMS_NUM] = {
 695                 BAR_XSTRORM_INTMEM,
 696                 BAR_TSTRORM_INTMEM,
 697                 BAR_CSTRORM_INTMEM,
 698                 BAR_USTRORM_INTMEM
 699         };
 700         u32 storm_assert_list_index[STORMS_NUM] = {
 701                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 703                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 704                 USTORM_ASSERT_LIST_INDEX_OFFSET
 705         };
 706         char *storms_string[STORMS_NUM] = {
 707                 "XSTORM",
 708                 "TSTORM",
 709                 "CSTORM",
 710                 "USTORM"
 711         };
 712
 713         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 714                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 715                                    storm_assert_list_index[storm]);
 716                 if (last_idx)
 717                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 718                                   storms_string[storm], last_idx);
 719
 720                 /* print the asserts */
 721                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 722                         /* read a single assert entry */
 723                         for (j = 0; j < REGS_IN_ENTRY; j++)
 724                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 725                                           bnx2x_get_assert_list_entry(bp,
 726                                                                       storm,
 727                                                                       i) +
 728                                           sizeof(u32) * j);
 729
 730                         /* log entry if it contains a valid assert */
 731                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 732                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 733                                           storms_string[storm], i, regs[3],
 734                                           regs[2], regs[1], regs[0]);
 735                                 rc++;
 736                         } else {
 737                                 break;
 738                         }
 739                 }
 740         }
 741
 742         BNX2X_ERR("Chip Revision: %s, /*(DEBLOBBED)*/\n",
 743                   CHIP_IS_E1(bp) ? "everest1" :
 744                   CHIP_IS_E1H(bp) ? "everest1h" :
 745                   CHIP_IS_E2(bp) ? "everest2" : "everest3"/*(DEBLOBBED)*/);
 746
 747         return rc;
 748 }
 749
 750 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 751 #define SCRATCH_BUFFER_SIZE(bp) \
 752         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 753
 754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 755 {
 756         u32 addr, val;
 757         u32 mark, offset;
 758         __be32 data[9];
 759         int word;
 760         u32 trace_shmem_base;
 761         if (BP_NOMCP(bp)) {
 762                 BNX2X_ERR("NO MCP - can not dump\n");
 763                 return;
 764         }
 765         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 766                 (bp->common.bc_ver & 0xff0000) >> 16,
 767                 (bp->common.bc_ver & 0xff00) >> 8,
 768                 (bp->common.bc_ver & 0xff));
 769
 770         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 771         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 772                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 773
 774         if (BP_PATH(bp) == 0)
 775                 trace_shmem_base = bp->common.shmem_base;
 776         else
 777                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 778
 779         /* sanity */
 780         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 781             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 782                                 SCRATCH_BUFFER_SIZE(bp)) {
 783                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 784                           trace_shmem_base);
 785                 return;
 786         }
 787
 788         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 789
 790         /* validate TRCB signature */
 791         mark = REG_RD(bp, addr);
 792         if (mark != MFW_TRACE_SIGNATURE) {
 793                 BNX2X_ERR("Trace buffer signature is missing.");
 794                 return ;
 795         }
 796
 797         /* read cyclic buffer pointer */
 798         addr += 4;
 799         mark = REG_RD(bp, addr);
 800         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 801         if (mark >= trace_shmem_base || mark < addr + 4) {
 802                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 803                 return;
 804         }
 805         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 806
 807         printk("%s", lvl);
 808
 809         /* dump buffer after the mark */
 810         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 811                 for (word = 0; word < 8; word++)
 812                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 813                 data[8] = 0x0;
 814                 pr_cont("%s", (char *)data);
 815         }
 816
 817         /* dump buffer before the mark */
 818         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 819                 for (word = 0; word < 8; word++)
 820                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 821                 data[8] = 0x0;
 822                 pr_cont("%s", (char *)data);
 823         }
 824         printk("%s" "end of fw dump\n", lvl);
 825 }
 826
 827 static void bnx2x_fw_dump(struct bnx2x *bp)
 828 {
 829         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 830 }
 831
 832 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 833 {
 834         int port = BP_PORT(bp);
 835         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 836         u32 val = REG_RD(bp, addr);
 837
 838         /* in E1 we must use only PCI configuration space to disable
 839          * MSI/MSIX capability
 840          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 841          */
 842         if (CHIP_IS_E1(bp)) {
 843                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 844                  * Use mask register to prevent from HC sending interrupts
 845                  * after we exit the function
 846                  */
 847                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 848
 849                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 850                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 851                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 852         } else
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 855                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 856                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 857
 858         DP(NETIF_MSG_IFDOWN,
 859            "write %x to HC %d (addr 0x%x)\n",
 860            val, port, addr);
 861
 862         /* flush all outstanding writes */
 863         mmiowb();
 864
 865         REG_WR(bp, addr, val);
 866         if (REG_RD(bp, addr) != val)
 867                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 868 }
 869
 870 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 871 {
 872         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 873
 874         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 875                  IGU_PF_CONF_INT_LINE_EN |
 876                  IGU_PF_CONF_ATTN_BIT_EN);
 877
 878         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 879
 880         /* flush all outstanding writes */
 881         mmiowb();
 882
 883         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 884         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 885                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 886 }
 887
 888 static void bnx2x_int_disable(struct bnx2x *bp)
 889 {
 890         if (bp->common.int_block == INT_BLOCK_HC)
 891                 bnx2x_hc_int_disable(bp);
 892         else
 893                 bnx2x_igu_int_disable(bp);
 894 }
 895
 896 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 897 {
 898         int i;
 899         u16 j;
 900         struct hc_sp_status_block_data sp_sb_data;
 901         int func = BP_FUNC(bp);
 902 #ifdef BNX2X_STOP_ON_ERROR
 903         u16 start = 0, end = 0;
 904         u8 cos;
 905 #endif
 906         if (IS_PF(bp) && disable_int)
 907                 bnx2x_int_disable(bp);
 908
 909         bp->stats_state = STATS_STATE_DISABLED;
 910         bp->eth_stats.unrecoverable_error++;
 911         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 912
 913         BNX2X_ERR("begin crash dump -----------------\n");
 914
 915         /* Indices */
 916         /* Common */
 917         if (IS_PF(bp)) {
 918                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 919                 int data_size, cstorm_offset;
 920
 921                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 922                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 923                           bp->spq_prod_idx, bp->stats_counter);
 924                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 925                           def_sb->atten_status_block.attn_bits,
 926                           def_sb->atten_status_block.attn_bits_ack,
 927                           def_sb->atten_status_block.status_block_id,
 928                           def_sb->atten_status_block.attn_bits_index);
 929                 BNX2X_ERR("     def (");
 930                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 931                         pr_cont("0x%x%s",
 932                                 def_sb->sp_sb.index_values[i],
 933                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 934
 935                 data_size = sizeof(struct hc_sp_status_block_data) /
 936                             sizeof(u32);
 937                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 938                 for (i = 0; i < data_size; i++)
 939                         *((u32 *)&sp_sb_data + i) =
 940                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 941                                            i * sizeof(u32));
 942
 943                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 944                         sp_sb_data.igu_sb_id,
 945                         sp_sb_data.igu_seg_id,
 946                         sp_sb_data.p_func.pf_id,
 947                         sp_sb_data.p_func.vnic_id,
 948                         sp_sb_data.p_func.vf_id,
 949                         sp_sb_data.p_func.vf_valid,
 950                         sp_sb_data.state);
 951         }
 952
 953         for_each_eth_queue(bp, i) {
 954                 struct bnx2x_fastpath *fp = &bp->fp[i];
 955                 int loop;
 956                 struct hc_status_block_data_e2 sb_data_e2;
 957                 struct hc_status_block_data_e1x sb_data_e1x;
 958                 struct hc_status_block_sm  *hc_sm_p =
 959                         CHIP_IS_E1x(bp) ?
 960                         sb_data_e1x.common.state_machine :
 961                         sb_data_e2.common.state_machine;
 962                 struct hc_index_data *hc_index_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.index_data :
 965                         sb_data_e2.index_data;
 966                 u8 data_size, cos;
 967                 u32 *sb_data_p;
 968                 struct bnx2x_fp_txdata txdata;
 969
 970                 if (!bp->fp)
 971                         break;
 972
 973                 if (!fp->rx_cons_sb)
 974                         continue;
 975
 976                 /* Rx */
 977                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 978                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 979                           fp->rx_comp_prod,
 980                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 981                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 982                           fp->rx_sge_prod, fp->last_max_sge,
 983                           le16_to_cpu(fp->fp_hc_idx));
 984
 985                 /* Tx */
 986                 for_each_cos_in_tx_queue(fp, cos)
 987                 {
 988                         if (!fp->txdata_ptr[cos])
 989                                 break;
 990
 991                         txdata = *fp->txdata_ptr[cos];
 992
 993                         if (!txdata.tx_cons_sb)
 994                                 continue;
 995
 996                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 997                                   i, txdata.tx_pkt_prod,
 998                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 999                                   txdata.tx_bd_cons,
1000                                   le16_to_cpu(*txdata.tx_cons_sb));
1001                 }
1002
1003                 loop = CHIP_IS_E1x(bp) ?
1004                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1005
1006                 /* host sb data */
1007
1008                 if (IS_FCOE_FP(fp))
1009                         continue;
1010
1011                 BNX2X_ERR("     run indexes (");
1012                 for (j = 0; j < HC_SB_MAX_SM; j++)
1013                         pr_cont("0x%x%s",
1014                                fp->sb_running_index[j],
1015                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016
1017                 BNX2X_ERR("     indexes (");
1018                 for (j = 0; j < loop; j++)
1019                         pr_cont("0x%x%s",
1020                                fp->sb_index_values[j],
1021                                (j == loop - 1) ? ")" : " ");
1022
1023                 /* VF cannot access FW refelection for status block */
1024                 if (IS_VF(bp))
1025                         continue;
1026
1027                 /* fw sb data */
1028                 data_size = CHIP_IS_E1x(bp) ?
1029                         sizeof(struct hc_status_block_data_e1x) :
1030                         sizeof(struct hc_status_block_data_e2);
1031                 data_size /= sizeof(u32);
1032                 sb_data_p = CHIP_IS_E1x(bp) ?
1033                         (u32 *)&sb_data_e1x :
1034                         (u32 *)&sb_data_e2;
1035                 /* copy sb data in here */
1036                 for (j = 0; j < data_size; j++)
1037                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039                                 j * sizeof(u32));
1040
1041                 if (!CHIP_IS_E1x(bp)) {
1042                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1043                                 sb_data_e2.common.p_func.pf_id,
1044                                 sb_data_e2.common.p_func.vf_id,
1045                                 sb_data_e2.common.p_func.vf_valid,
1046                                 sb_data_e2.common.p_func.vnic_id,
1047                                 sb_data_e2.common.same_igu_sb_1b,
1048                                 sb_data_e2.common.state);
1049                 } else {
1050                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1051                                 sb_data_e1x.common.p_func.pf_id,
1052                                 sb_data_e1x.common.p_func.vf_id,
1053                                 sb_data_e1x.common.p_func.vf_valid,
1054                                 sb_data_e1x.common.p_func.vnic_id,
1055                                 sb_data_e1x.common.same_igu_sb_1b,
1056                                 sb_data_e1x.common.state);
1057                 }
1058
1059                 /* SB_SMs data */
1060                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1061                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062                                 j, hc_sm_p[j].__flags,
1063                                 hc_sm_p[j].igu_sb_id,
1064                                 hc_sm_p[j].igu_seg_id,
1065                                 hc_sm_p[j].time_to_expire,
1066                                 hc_sm_p[j].timer_value);
1067                 }
1068
1069                 /* Indices data */
1070                 for (j = 0; j < loop; j++) {
1071                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1072                                hc_index_p[j].flags,
1073                                hc_index_p[j].timeout);
1074                 }
1075         }
1076
1077 #ifdef BNX2X_STOP_ON_ERROR
1078         if (IS_PF(bp)) {
1079                 /* event queue */
1080                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081                 for (i = 0; i < NUM_EQ_DESC; i++) {
1082                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083
1084                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085                                   i, bp->eq_ring[i].message.opcode,
1086                                   bp->eq_ring[i].message.error);
1087                         BNX2X_ERR("data: %x %x %x\n",
1088                                   data[0], data[1], data[2]);
1089                 }
1090         }
1091
1092         /* Rings */
1093         /* Rx */
1094         for_each_valid_rx_queue(bp, i) {
1095                 struct bnx2x_fastpath *fp = &bp->fp[i];
1096
1097                 if (!bp->fp)
1098                         break;
1099
1100                 if (!fp->rx_cons_sb)
1101                         continue;
1102
1103                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1105                 for (j = start; j != end; j = RX_BD(j + 1)) {
1106                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108
1109                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1110                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1111                 }
1112
1113                 start = RX_SGE(fp->rx_sge_prod);
1114                 end = RX_SGE(fp->last_max_sge);
1115                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1116                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118
1119                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1120                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1121                 }
1122
1123                 start = RCQ_BD(fp->rx_comp_cons - 10);
1124                 end = RCQ_BD(fp->rx_comp_cons + 503);
1125                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1126                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127
1128                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1130                 }
1131         }
1132
1133         /* Tx */
1134         for_each_valid_tx_queue(bp, i) {
1135                 struct bnx2x_fastpath *fp = &bp->fp[i];
1136
1137                 if (!bp->fp)
1138                         break;
1139
1140                 for_each_cos_in_tx_queue(fp, cos) {
1141                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1142
1143                         if (!fp->txdata_ptr[cos])
1144                                 break;
1145
1146                         if (!txdata->tx_cons_sb)
1147                                 continue;
1148
1149                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151                         for (j = start; j != end; j = TX_BD(j + 1)) {
1152                                 struct sw_tx_bd *sw_bd =
1153                                         &txdata->tx_buf_ring[j];
1154
1155                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1156                                           i, cos, j, sw_bd->skb,
1157                                           sw_bd->first_bd);
1158                         }
1159
1160                         start = TX_BD(txdata->tx_bd_cons - 10);
1161                         end = TX_BD(txdata->tx_bd_cons + 254);
1162                         for (j = start; j != end; j = TX_BD(j + 1)) {
1163                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1164
1165                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1166                                           i, cos, j, tx_bd[0], tx_bd[1],
1167                                           tx_bd[2], tx_bd[3]);
1168                         }
1169                 }
1170         }
1171 #endif
1172         if (IS_PF(bp)) {
1173                 bnx2x_fw_dump(bp);
1174                 bnx2x_mc_assert(bp);
1175         }
1176         BNX2X_ERR("end crash dump -----------------\n");
1177 }
1178
1179 /*
1180  * FLR Support for E2
1181  *
1182  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183  * initialization.
1184  */
1185 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1186 #define FLR_WAIT_INTERVAL       50      /* usec */
1187 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1188
1189 struct pbf_pN_buf_regs {
1190         int pN;
1191         u32 init_crd;
1192         u32 crd;
1193         u32 crd_freed;
1194 };
1195
1196 struct pbf_pN_cmd_regs {
1197         int pN;
1198         u32 lines_occup;
1199         u32 lines_freed;
1200 };
1201
1202 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203                                      struct pbf_pN_buf_regs *regs,
1204                                      u32 poll_count)
1205 {
1206         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207         u32 cur_cnt = poll_count;
1208
1209         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210         crd = crd_start = REG_RD(bp, regs->crd);
1211         init_crd = REG_RD(bp, regs->init_crd);
1212
1213         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1215         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216
1217         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218                (init_crd - crd_start))) {
1219                 if (cur_cnt--) {
1220                         udelay(FLR_WAIT_INTERVAL);
1221                         crd = REG_RD(bp, regs->crd);
1222                         crd_freed = REG_RD(bp, regs->crd_freed);
1223                 } else {
1224                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225                            regs->pN);
1226                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1227                            regs->pN, crd);
1228                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229                            regs->pN, crd_freed);
1230                         break;
1231                 }
1232         }
1233         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1234            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1235 }
1236
1237 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238                                      struct pbf_pN_cmd_regs *regs,
1239                                      u32 poll_count)
1240 {
1241         u32 occup, to_free, freed, freed_start;
1242         u32 cur_cnt = poll_count;
1243
1244         occup = to_free = REG_RD(bp, regs->lines_occup);
1245         freed = freed_start = REG_RD(bp, regs->lines_freed);
1246
1247         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1248         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249
1250         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251                 if (cur_cnt--) {
1252                         udelay(FLR_WAIT_INTERVAL);
1253                         occup = REG_RD(bp, regs->lines_occup);
1254                         freed = REG_RD(bp, regs->lines_freed);
1255                 } else {
1256                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257                            regs->pN);
1258                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1259                            regs->pN, occup);
1260                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261                            regs->pN, freed);
1262                         break;
1263                 }
1264         }
1265         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1266            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1267 }
1268
1269 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270                                     u32 expected, u32 poll_count)
1271 {
1272         u32 cur_cnt = poll_count;
1273         u32 val;
1274
1275         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1276                 udelay(FLR_WAIT_INTERVAL);
1277
1278         return val;
1279 }
1280
1281 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282                                     char *msg, u32 poll_cnt)
1283 {
1284         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285         if (val != 0) {
1286                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287                 return 1;
1288         }
1289         return 0;
1290 }
1291
1292 /* Common routines with VF FLR cleanup */
1293 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1294 {
1295         /* adjust polling timeout */
1296         if (CHIP_REV_IS_EMUL(bp))
1297                 return FLR_POLL_CNT * 2000;
1298
1299         if (CHIP_REV_IS_FPGA(bp))
1300                 return FLR_POLL_CNT * 120;
1301
1302         return FLR_POLL_CNT;
1303 }
1304
1305 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1306 {
1307         struct pbf_pN_cmd_regs cmd_regs[] = {
1308                 {0, (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_TQ_OCCUPANCY_Q0 :
1310                         PBF_REG_P0_TQ_OCCUPANCY,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1314                 {1, (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_OCCUPANCY_Q1 :
1316                         PBF_REG_P1_TQ_OCCUPANCY,
1317                     (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1320                 {4, (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1322                         PBF_REG_P4_TQ_OCCUPANCY,
1323                     (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1326         };
1327
1328         struct pbf_pN_buf_regs buf_regs[] = {
1329                 {0, (CHIP_IS_E3B0(bp)) ?
1330                         PBF_REG_INIT_CRD_Q0 :
1331                         PBF_REG_P0_INIT_CRD ,
1332                     (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_CREDIT_Q0 :
1334                         PBF_REG_P0_CREDIT,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338                 {1, (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INIT_CRD_Q1 :
1340                         PBF_REG_P1_INIT_CRD,
1341                     (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_CREDIT_Q1 :
1343                         PBF_REG_P1_CREDIT,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347                 {4, (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INIT_CRD_LB_Q :
1349                         PBF_REG_P4_INIT_CRD,
1350                     (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_CREDIT_LB_Q :
1352                         PBF_REG_P4_CREDIT,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356         };
1357
1358         int i;
1359
1360         /* Verify the command queues are flushed P0, P1, P4 */
1361         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363
1364         /* Verify the transmission buffers are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367 }
1368
1369 #define OP_GEN_PARAM(param) \
1370         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371
1372 #define OP_GEN_TYPE(type) \
1373         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374
1375 #define OP_GEN_AGG_VECT(index) \
1376         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377
1378 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1379 {
1380         u32 op_gen_command = 0;
1381         u32 comp_addr = BAR_CSTRORM_INTMEM +
1382                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383         int ret = 0;
1384
1385         if (REG_RD(bp, comp_addr)) {
1386                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1387                 return 1;
1388         }
1389
1390         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1394
1395         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1396         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1397
1398         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399                 BNX2X_ERR("FW final cleanup did not succeed\n");
1400                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401                    (REG_RD(bp, comp_addr)));
1402                 bnx2x_panic();
1403                 return 1;
1404         }
1405         /* Zero completion for next FLR */
1406         REG_WR(bp, comp_addr, 0);
1407
1408         return ret;
1409 }
1410
1411 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1412 {
1413         u16 status;
1414
1415         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1416         return status & PCI_EXP_DEVSTA_TRPND;
1417 }
1418
1419 /* PF FLR specific routines
1420 */
1421 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422 {
1423         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1426                         "CFC PF usage counter timed out",
1427                         poll_cnt))
1428                 return 1;
1429
1430         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432                         DORQ_REG_PF_USAGE_CNT,
1433                         "DQ PF usage counter timed out",
1434                         poll_cnt))
1435                 return 1;
1436
1437         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440                         "QM PF usage counter timed out",
1441                         poll_cnt))
1442                 return 1;
1443
1444         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447                         "Timers VNIC usage counter timed out",
1448                         poll_cnt))
1449                 return 1;
1450         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452                         "Timers NUM_SCANS usage counter timed out",
1453                         poll_cnt))
1454                 return 1;
1455
1456         /* Wait DMAE PF usage counter to zero */
1457         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1459                         "DMAE command register timed out",
1460                         poll_cnt))
1461                 return 1;
1462
1463         return 0;
1464 }
1465
1466 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467 {
1468         u32 val;
1469
1470         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472
1473         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475
1476         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484
1485         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487
1488         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490
1491         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493            val);
1494 }
1495
1496 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497 {
1498         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499
1500         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501
1502         /* Re-enable PF target read access */
1503         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504
1505         /* Poll HW usage counters */
1506         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1507         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508                 return -EBUSY;
1509
1510         /* Zero the igu 'trailing edge' and 'leading edge' */
1511
1512         /* Send the FW cleanup command */
1513         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514                 return -EBUSY;
1515
1516         /* ATC cleanup */
1517
1518         /* Verify TX hw is flushed */
1519         bnx2x_tx_hw_flushed(bp, poll_cnt);
1520
1521         /* Wait 100ms (not adjusted according to platform) */
1522         msleep(100);
1523
1524         /* Verify no pending pci transactions */
1525         if (bnx2x_is_pcie_pending(bp->pdev))
1526                 BNX2X_ERR("PCIE Transactions still pending\n");
1527
1528         /* Debug */
1529         bnx2x_hw_enable_status(bp);
1530
1531         /*
1532          * Master enable - Due to WB DMAE writes performed before this
1533          * register is re-initialized as part of the regular function init
1534          */
1535         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536
1537         return 0;
1538 }
1539
1540 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1541 {
1542         int port = BP_PORT(bp);
1543         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544         u32 val = REG_RD(bp, addr);
1545         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1548
1549         if (msix) {
1550                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1552                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1554                 if (single_msix)
1555                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1556         } else if (msi) {
1557                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561         } else {
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566
1567                 if (!CHIP_IS_E1(bp)) {
1568                         DP(NETIF_MSG_IFUP,
1569                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1570
1571                         REG_WR(bp, addr, val);
1572
1573                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574                 }
1575         }
1576
1577         if (CHIP_IS_E1(bp))
1578                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579
1580         DP(NETIF_MSG_IFUP,
1581            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1583
1584         REG_WR(bp, addr, val);
1585         /*
1586          * Ensure that HC_CONFIG is written before leading/trailing edge config
1587          */
1588         mmiowb();
1589         barrier();
1590
1591         if (!CHIP_IS_E1(bp)) {
1592                 /* init leading/trailing edge */
1593                 if (IS_MF(bp)) {
1594                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595                         if (bp->port.pmf)
1596                                 /* enable nig and gpio3 attention */
1597                                 val |= 0x1100;
1598                 } else
1599                         val = 0xffff;
1600
1601                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603         }
1604
1605         /* Make sure that interrupts are indeed enabled from here on */
1606         mmiowb();
1607 }
1608
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611         u32 val;
1612         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615
1616         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618         if (msix) {
1619                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620                          IGU_PF_CONF_SINGLE_ISR_EN);
1621                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622                         IGU_PF_CONF_ATTN_BIT_EN);
1623
1624                 if (single_msix)
1625                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626         } else if (msi) {
1627                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         } else {
1632                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633                 val |= (IGU_PF_CONF_INT_LINE_EN |
1634                         IGU_PF_CONF_ATTN_BIT_EN |
1635                         IGU_PF_CONF_SINGLE_ISR_EN);
1636         }
1637
1638         /* Clean previous status - need to configure igu prior to ack*/
1639         if ((!msix) || single_msix) {
1640                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641                 bnx2x_ack_int(bp);
1642         }
1643
1644         val |= IGU_PF_CONF_FUNC_EN;
1645
1646         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1647            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
1651         if (val & IGU_PF_CONF_INT_LINE_EN)
1652                 pci_intx(bp->pdev, true);
1653
1654         barrier();
1655
1656         /* init leading/trailing edge */
1657         if (IS_MF(bp)) {
1658                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659                 if (bp->port.pmf)
1660                         /* enable nig and gpio3 attention */
1661                         val |= 0x1100;
1662         } else
1663                 val = 0xffff;
1664
1665         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667
1668         /* Make sure that interrupts are indeed enabled from here on */
1669         mmiowb();
1670 }
1671
1672 void bnx2x_int_enable(struct bnx2x *bp)
1673 {
1674         if (bp->common.int_block == INT_BLOCK_HC)
1675                 bnx2x_hc_int_enable(bp);
1676         else
1677                 bnx2x_igu_int_enable(bp);
1678 }
1679
1680 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1681 {
1682         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1683         int i, offset;
1684
1685         if (disable_hw)
1686                 /* prevent the HW from sending interrupts */
1687                 bnx2x_int_disable(bp);
1688
1689         /* make sure all ISRs are done */
1690         if (msix) {
1691                 synchronize_irq(bp->msix_table[0].vector);
1692                 offset = 1;
1693                 if (CNIC_SUPPORT(bp))
1694                         offset++;
1695                 for_each_eth_queue(bp, i)
1696                         synchronize_irq(bp->msix_table[offset++].vector);
1697         } else
1698                 synchronize_irq(bp->pdev->irq);
1699
1700         /* make sure sp_task is not running */
1701         cancel_delayed_work(&bp->sp_task);
1702         cancel_delayed_work(&bp->period_task);
1703         flush_workqueue(bnx2x_wq);
1704 }
1705
1706 /* fast path */
1707
1708 /*
1709  * General service functions
1710  */
1711
1712 /* Return true if succeeded to acquire the lock */
1713 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714 {
1715         u32 lock_status;
1716         u32 resource_bit = (1 << resource);
1717         int func = BP_FUNC(bp);
1718         u32 hw_lock_control_reg;
1719
1720         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721            "Trying to take a lock on resource %d\n", resource);
1722
1723         /* Validating that the resource is within range */
1724         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1725                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1726                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1728                 return false;
1729         }
1730
1731         if (func <= 5)
1732                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733         else
1734                 hw_lock_control_reg =
1735                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736
1737         /* Try to acquire the lock */
1738         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739         lock_status = REG_RD(bp, hw_lock_control_reg);
1740         if (lock_status & resource_bit)
1741                 return true;
1742
1743         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744            "Failed to get a lock on resource %d\n", resource);
1745         return false;
1746 }
1747
1748 /**
1749  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750  *
1751  * @bp: driver handle
1752  *
1753  * Returns the recovery leader resource id according to the engine this function
1754  * belongs to. Currently only only 2 engines is supported.
1755  */
1756 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1757 {
1758         if (BP_PATH(bp))
1759                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760         else
1761                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762 }
1763
1764 /**
1765  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1766  *
1767  * @bp: driver handle
1768  *
1769  * Tries to acquire a leader lock for current engine.
1770  */
1771 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1772 {
1773         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774 }
1775
1776 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1777
1778 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780 {
1781         /* Set the interrupt occurred bit for the sp-task to recognize it
1782          * must ack the interrupt and transition according to the IGU
1783          * state machine.
1784          */
1785         atomic_set(&bp->interrupt_occurred, 1);
1786
1787         /* The sp_task must execute only after this bit
1788          * is set, otherwise we will get out of sync and miss all
1789          * further interrupts. Hence, the barrier.
1790          */
1791         smp_wmb();
1792
1793         /* schedule sp_task to workqueue */
1794         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 }
1796
1797 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1798 {
1799         struct bnx2x *bp = fp->bp;
1800         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1803         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1804
1805         DP(BNX2X_MSG_SP,
1806            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1807            fp->index, cid, command, bp->state,
1808            rr_cqe->ramrod_cqe.ramrod_type);
1809
1810         /* If cid is within VF range, replace the slowpath object with the
1811          * one corresponding to this VF
1812          */
1813         if (cid >= BNX2X_FIRST_VF_CID  &&
1814             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816
1817         switch (command) {
1818         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1819                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1820                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821                 break;
1822
1823         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1824                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1825                 drv_cmd = BNX2X_Q_CMD_SETUP;
1826                 break;
1827
1828         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1829                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831                 break;
1832
1833         case (RAMROD_CMD_ID_ETH_HALT):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_HALT;
1836                 break;
1837
1838         case (RAMROD_CMD_ID_ETH_TERMINATE):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1841                 break;
1842
1843         case (RAMROD_CMD_ID_ETH_EMPTY):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1846                 break;
1847
1848         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851                 break;
1852
1853         default:
1854                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855                           command, fp->index);
1856                 return;
1857         }
1858
1859         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861                 /* q_obj->complete_cmd() failure means that this was
1862                  * an unexpected completion.
1863                  *
1864                  * In this case we don't want to increase the bp->spq_left
1865                  * because apparently we haven't sent this command the first
1866                  * place.
1867                  */
1868 #ifdef BNX2X_STOP_ON_ERROR
1869                 bnx2x_panic();
1870 #else
1871                 return;
1872 #endif
1873
1874         smp_mb__before_atomic();
1875         atomic_inc(&bp->cq_spq_left);
1876         /* push the change in bp->spq_left and towards the memory */
1877         smp_mb__after_atomic();
1878
1879         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880
1881         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883                 /* if Q update ramrod is completed for last Q in AFEX vif set
1884                  * flow, then ACK MCP at the end
1885                  *
1886                  * mark pending ACK to MCP bit.
1887                  * prevent case that both bits are cleared.
1888                  * At the end of load/unload driver checks that
1889                  * sp_state is cleared, and this order prevents
1890                  * races
1891                  */
1892                 smp_mb__before_atomic();
1893                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894                 wmb();
1895                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1896                 smp_mb__after_atomic();
1897
1898                 /* schedule the sp task as mcp ack is required */
1899                 bnx2x_schedule_sp_task(bp);
1900         }
1901
1902         return;
1903 }
1904
1905 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1906 {
1907         struct bnx2x *bp = netdev_priv(dev_instance);
1908         u16 status = bnx2x_ack_int(bp);
1909         u16 mask;
1910         int i;
1911         u8 cos;
1912
1913         /* Return here if interrupt is shared and it's not for us */
1914         if (unlikely(status == 0)) {
1915                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916                 return IRQ_NONE;
1917         }
1918         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1919
1920 #ifdef BNX2X_STOP_ON_ERROR
1921         if (unlikely(bp->panic))
1922                 return IRQ_HANDLED;
1923 #endif
1924
1925         for_each_eth_queue(bp, i) {
1926                 struct bnx2x_fastpath *fp = &bp->fp[i];
1927
1928                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1929                 if (status & mask) {
1930                         /* Handle Rx or Tx according to SB id */
1931                         for_each_cos_in_tx_queue(fp, cos)
1932                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1933                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1934                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1935                         status &= ~mask;
1936                 }
1937         }
1938
1939         if (CNIC_SUPPORT(bp)) {
1940                 mask = 0x2;
1941                 if (status & (mask | 0x1)) {
1942                         struct cnic_ops *c_ops = NULL;
1943
1944                         rcu_read_lock();
1945                         c_ops = rcu_dereference(bp->cnic_ops);
1946                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1947                                       CNIC_DRV_STATE_HANDLES_IRQ))
1948                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1949                         rcu_read_unlock();
1950
1951                         status &= ~mask;
1952                 }
1953         }
1954
1955         if (unlikely(status & 0x1)) {
1956
1957                 /* schedule sp task to perform default status block work, ack
1958                  * attentions and enable interrupts.
1959                  */
1960                 bnx2x_schedule_sp_task(bp);
1961
1962                 status &= ~0x1;
1963                 if (!status)
1964                         return IRQ_HANDLED;
1965         }
1966
1967         if (unlikely(status))
1968                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1969                    status);
1970
1971         return IRQ_HANDLED;
1972 }
1973
1974 /* Link */
1975
1976 /*
1977  * General service functions
1978  */
1979
1980 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1981 {
1982         u32 lock_status;
1983         u32 resource_bit = (1 << resource);
1984         int func = BP_FUNC(bp);
1985         u32 hw_lock_control_reg;
1986         int cnt;
1987
1988         /* Validating that the resource is within range */
1989         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992                 return -EINVAL;
1993         }
1994
1995         if (func <= 5) {
1996                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997         } else {
1998                 hw_lock_control_reg =
1999                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000         }
2001
2002         /* Validating that the resource is not already taken */
2003         lock_status = REG_RD(bp, hw_lock_control_reg);
2004         if (lock_status & resource_bit) {
2005                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2006                    lock_status, resource_bit);
2007                 return -EEXIST;
2008         }
2009
2010         /* Try for 5 second every 5ms */
2011         for (cnt = 0; cnt < 1000; cnt++) {
2012                 /* Try to acquire the lock */
2013                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014                 lock_status = REG_RD(bp, hw_lock_control_reg);
2015                 if (lock_status & resource_bit)
2016                         return 0;
2017
2018                 usleep_range(5000, 10000);
2019         }
2020         BNX2X_ERR("Timeout\n");
2021         return -EAGAIN;
2022 }
2023
2024 int bnx2x_release_leader_lock(struct bnx2x *bp)
2025 {
2026         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027 }
2028
2029 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2030 {
2031         u32 lock_status;
2032         u32 resource_bit = (1 << resource);
2033         int func = BP_FUNC(bp);
2034         u32 hw_lock_control_reg;
2035
2036         /* Validating that the resource is within range */
2037         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2038                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2039                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040                 return -EINVAL;
2041         }
2042
2043         if (func <= 5) {
2044                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045         } else {
2046                 hw_lock_control_reg =
2047                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048         }
2049
2050         /* Validating that the resource is currently taken */
2051         lock_status = REG_RD(bp, hw_lock_control_reg);
2052         if (!(lock_status & resource_bit)) {
2053                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054                           lock_status, resource_bit);
2055                 return -EFAULT;
2056         }
2057
2058         REG_WR(bp, hw_lock_control_reg, resource_bit);
2059         return 0;
2060 }
2061
2062 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063 {
2064         /* The GPIO should be swapped if swap register is set and active */
2065         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067         int gpio_shift = gpio_num +
2068                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069         u32 gpio_mask = (1 << gpio_shift);
2070         u32 gpio_reg;
2071         int value;
2072
2073         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075                 return -EINVAL;
2076         }
2077
2078         /* read GPIO value */
2079         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080
2081         /* get the requested pin value */
2082         if ((gpio_reg & gpio_mask) == gpio_mask)
2083                 value = 1;
2084         else
2085                 value = 0;
2086
2087         return value;
2088 }
2089
2090 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2091 {
2092         /* The GPIO should be swapped if swap register is set and active */
2093         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2094                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2095         int gpio_shift = gpio_num +
2096                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097         u32 gpio_mask = (1 << gpio_shift);
2098         u32 gpio_reg;
2099
2100         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102                 return -EINVAL;
2103         }
2104
2105         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2106         /* read GPIO and mask except the float bits */
2107         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2108
2109         switch (mode) {
2110         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2111                 DP(NETIF_MSG_LINK,
2112                    "Set GPIO %d (shift %d) -> output low\n",
2113                    gpio_num, gpio_shift);
2114                 /* clear FLOAT and set CLR */
2115                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117                 break;
2118
2119         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2120                 DP(NETIF_MSG_LINK,
2121                    "Set GPIO %d (shift %d) -> output high\n",
2122                    gpio_num, gpio_shift);
2123                 /* clear FLOAT and set SET */
2124                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126                 break;
2127
2128         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2129                 DP(NETIF_MSG_LINK,
2130                    "Set GPIO %d (shift %d) -> input\n",
2131                    gpio_num, gpio_shift);
2132                 /* set FLOAT */
2133                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135
2136         default:
2137                 break;
2138         }
2139
2140         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2142
2143         return 0;
2144 }
2145
2146 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147 {
2148         u32 gpio_reg = 0;
2149         int rc = 0;
2150
2151         /* Any port swapping should be handled by caller. */
2152
2153         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154         /* read GPIO and mask except the float bits */
2155         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159
2160         switch (mode) {
2161         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163                 /* set CLR */
2164                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165                 break;
2166
2167         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169                 /* set SET */
2170                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171                 break;
2172
2173         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175                 /* set FLOAT */
2176                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177                 break;
2178
2179         default:
2180                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181                 rc = -EINVAL;
2182                 break;
2183         }
2184
2185         if (rc == 0)
2186                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187
2188         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189
2190         return rc;
2191 }
2192
2193 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194 {
2195         /* The GPIO should be swapped if swap register is set and active */
2196         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198         int gpio_shift = gpio_num +
2199                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200         u32 gpio_mask = (1 << gpio_shift);
2201         u32 gpio_reg;
2202
2203         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205                 return -EINVAL;
2206         }
2207
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209         /* read GPIO int */
2210         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211
2212         switch (mode) {
2213         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2214                 DP(NETIF_MSG_LINK,
2215                    "Clear GPIO INT %d (shift %d) -> output low\n",
2216                    gpio_num, gpio_shift);
2217                 /* clear SET and set CLR */
2218                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220                 break;
2221
2222         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2223                 DP(NETIF_MSG_LINK,
2224                    "Set GPIO INT %d (shift %d) -> output high\n",
2225                    gpio_num, gpio_shift);
2226                 /* clear CLR and set SET */
2227                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 break;
2230
2231         default:
2232                 break;
2233         }
2234
2235         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237
2238         return 0;
2239 }
2240
2241 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2242 {
2243         u32 spio_reg;
2244
2245         /* Only 2 SPIOs are configurable */
2246         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2248                 return -EINVAL;
2249         }
2250
2251         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2252         /* read SPIO and mask except the float bits */
2253         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2254
2255         switch (mode) {
2256         case MISC_SPIO_OUTPUT_LOW:
2257                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2258                 /* clear FLOAT and set CLR */
2259                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2261                 break;
2262
2263         case MISC_SPIO_OUTPUT_HIGH:
2264                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2265                 /* clear FLOAT and set SET */
2266                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2268                 break;
2269
2270         case MISC_SPIO_INPUT_HI_Z:
2271                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2272                 /* set FLOAT */
2273                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2274                 break;
2275
2276         default:
2277                 break;
2278         }
2279
2280         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2281         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2282
2283         return 0;
2284 }
2285
2286 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2287 {
2288         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2289
2290         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2291                                            ADVERTISED_Pause);
2292         switch (bp->link_vars.ieee_fc &
2293                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2294         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2295                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2296                                                   ADVERTISED_Pause);
2297                 break;
2298
2299         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2300                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2301                 break;
2302
2303         default:
2304                 break;
2305         }
2306 }
2307
2308 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2309 {
2310         /* Initialize link parameters structure variables
2311          * It is recommended to turn off RX FC for jumbo frames
2312          *  for better performance
2313          */
2314         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2315                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2316         else
2317                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2318 }
2319
2320 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2321 {
2322         u32 pause_enabled = 0;
2323
2324         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2325                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2326                         pause_enabled = 1;
2327
2328                 REG_WR(bp, BAR_USTRORM_INTMEM +
2329                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2330                        pause_enabled);
2331         }
2332
2333         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2334            pause_enabled ? "enabled" : "disabled");
2335 }
2336
2337 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2338 {
2339         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2340         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2341
2342         if (!BP_NOMCP(bp)) {
2343                 bnx2x_set_requested_fc(bp);
2344                 bnx2x_acquire_phy_lock(bp);
2345
2346                 if (load_mode == LOAD_DIAG) {
2347                         struct link_params *lp = &bp->link_params;
2348                         lp->loopback_mode = LOOPBACK_XGXS;
2349                         /* Prefer doing PHY loopback at highest speed */
2350                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2351                                 if (lp->speed_cap_mask[cfx_idx] &
2352                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2353                                         lp->req_line_speed[cfx_idx] =
2354                                         SPEED_20000;
2355                                 else if (lp->speed_cap_mask[cfx_idx] &
2356                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357                                                 lp->req_line_speed[cfx_idx] =
2358                                                 SPEED_10000;
2359                                 else
2360                                         lp->req_line_speed[cfx_idx] =
2361                                         SPEED_1000;
2362                         }
2363                 }
2364
2365                 if (load_mode == LOAD_LOOPBACK_EXT) {
2366                         struct link_params *lp = &bp->link_params;
2367                         lp->loopback_mode = LOOPBACK_EXT;
2368                 }
2369
2370                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2371
2372                 bnx2x_release_phy_lock(bp);
2373
2374                 bnx2x_init_dropless_fc(bp);
2375
2376                 bnx2x_calc_fc_adv(bp);
2377
2378                 if (bp->link_vars.link_up) {
2379                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2380                         bnx2x_link_report(bp);
2381                 }
2382                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2383                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2384                 return rc;
2385         }
2386         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387         return -EINVAL;
2388 }
2389
2390 void bnx2x_link_set(struct bnx2x *bp)
2391 {
2392         if (!BP_NOMCP(bp)) {
2393                 bnx2x_acquire_phy_lock(bp);
2394                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2395                 bnx2x_release_phy_lock(bp);
2396
2397                 bnx2x_init_dropless_fc(bp);
2398
2399                 bnx2x_calc_fc_adv(bp);
2400         } else
2401                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2402 }
2403
2404 static void bnx2x__link_reset(struct bnx2x *bp)
2405 {
2406         if (!BP_NOMCP(bp)) {
2407                 bnx2x_acquire_phy_lock(bp);
2408                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2409                 bnx2x_release_phy_lock(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2412 }
2413
2414 void bnx2x_force_link_reset(struct bnx2x *bp)
2415 {
2416         bnx2x_acquire_phy_lock(bp);
2417         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418         bnx2x_release_phy_lock(bp);
2419 }
2420
2421 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 {
2423         u8 rc = 0;
2424
2425         if (!BP_NOMCP(bp)) {
2426                 bnx2x_acquire_phy_lock(bp);
2427                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428                                      is_serdes);
2429                 bnx2x_release_phy_lock(bp);
2430         } else
2431                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2432
2433         return rc;
2434 }
2435
2436 /* Calculates the sum of vn_min_rates.
2437    It's needed for further normalizing of the min_rates.
2438    Returns:
2439      sum of vn_min_rates.
2440        or
2441      0 - if all the min_rates are 0.
2442      In the later case fairness algorithm should be deactivated.
2443      If not all min_rates are zero then those that are zeroes will be set to 1.
2444  */
2445 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446                                       struct cmng_init_input *input)
2447 {
2448         int all_zero = 1;
2449         int vn;
2450
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 u32 vn_cfg = bp->mf_config[vn];
2453                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455
2456                 /* Skip hidden vns */
2457                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2458                         vn_min_rate = 0;
2459                 /* If min rate is zero - set it to 1 */
2460                 else if (!vn_min_rate)
2461                         vn_min_rate = DEF_MIN_RATE;
2462                 else
2463                         all_zero = 0;
2464
2465                 input->vnic_min_rate[vn] = vn_min_rate;
2466         }
2467
2468         /* if ETS or all min rates are zeros - disable fairness */
2469         if (BNX2X_IS_ETS_ENABLED(bp)) {
2470                 input->flags.cmng_enables &=
2471                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473         } else if (all_zero) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP,
2477                    "All MIN values are zeroes fairness will be disabled\n");
2478         } else
2479                 input->flags.cmng_enables |=
2480                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 }
2482
2483 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484                                     struct cmng_init_input *input)
2485 {
2486         u16 vn_max_rate;
2487         u32 vn_cfg = bp->mf_config[vn];
2488
2489         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2490                 vn_max_rate = 0;
2491         else {
2492                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493
2494                 if (IS_MF_PERCENT_BW(bp)) {
2495                         /* maxCfg in percents of linkspeed */
2496                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2497                 } else /* SD modes */
2498                         /* maxCfg is absolute in 100Mb units */
2499                         vn_max_rate = maxCfg * 100;
2500         }
2501
2502         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2503
2504         input->vnic_max_rate[vn] = vn_max_rate;
2505 }
2506
2507 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508 {
2509         if (CHIP_REV_IS_SLOW(bp))
2510                 return CMNG_FNS_NONE;
2511         if (IS_MF(bp))
2512                 return CMNG_FNS_MINMAX;
2513
2514         return CMNG_FNS_NONE;
2515 }
2516
2517 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2518 {
2519         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2520
2521         if (BP_NOMCP(bp))
2522                 return; /* what should be the default value in this case */
2523
2524         /* For 2 port configuration the absolute function number formula
2525          * is:
2526          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2527          *
2528          *      and there are 4 functions per port
2529          *
2530          * For 4 port configuration it is
2531          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532          *
2533          *      and there are 2 functions per port
2534          */
2535         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2536                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537
2538                 if (func >= E1H_FUNC_MAX)
2539                         break;
2540
2541                 bp->mf_config[vn] =
2542                         MF_CFG_RD(bp, func_mf_config[func].config);
2543         }
2544         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546                 bp->flags |= MF_FUNC_DIS;
2547         } else {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549                 bp->flags &= ~MF_FUNC_DIS;
2550         }
2551 }
2552
2553 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554 {
2555         struct cmng_init_input input;
2556         memset(&input, 0, sizeof(struct cmng_init_input));
2557
2558         input.port_rate = bp->link_vars.line_speed;
2559
2560         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2561                 int vn;
2562
2563                 /* read mf conf from shmem */
2564                 if (read_cfg)
2565                         bnx2x_read_mf_cfg(bp);
2566
2567                 /* vn_weight_sum and enable fairness if not 0 */
2568                 bnx2x_calc_vn_min(bp, &input);
2569
2570                 /* calculate and set min-max rate for each vn */
2571                 if (bp->port.pmf)
2572                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2573                                 bnx2x_calc_vn_max(bp, vn, &input);
2574
2575                 /* always enable rate shaping and fairness */
2576                 input.flags.cmng_enables |=
2577                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2578
2579                 bnx2x_init_cmng(&input, &bp->cmng);
2580                 return;
2581         }
2582
2583         /* rate shaping and fairness are disabled */
2584         DP(NETIF_MSG_IFUP,
2585            "rate shaping and fairness are disabled\n");
2586 }
2587
2588 static void storm_memset_cmng(struct bnx2x *bp,
2589                               struct cmng_init *cmng,
2590                               u8 port)
2591 {
2592         int vn;
2593         size_t size = sizeof(struct cmng_struct_per_port);
2594
2595         u32 addr = BAR_XSTRORM_INTMEM +
2596                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597
2598         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599
2600         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601                 int func = func_by_vn(bp, vn);
2602
2603                 addr = BAR_XSTRORM_INTMEM +
2604                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605                 size = sizeof(struct rate_shaping_vars_per_vn);
2606                 __storm_memset_struct(bp, addr, size,
2607                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608
2609                 addr = BAR_XSTRORM_INTMEM +
2610                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611                 size = sizeof(struct fairness_vars_per_vn);
2612                 __storm_memset_struct(bp, addr, size,
2613                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614         }
2615 }
2616
2617 /* init cmng mode in HW according to local configuration */
2618 void bnx2x_set_local_cmng(struct bnx2x *bp)
2619 {
2620         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621
2622         if (cmng_fns != CMNG_FNS_NONE) {
2623                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625         } else {
2626                 /* rate shaping and fairness are disabled */
2627                 DP(NETIF_MSG_IFUP,
2628                    "single function mode without fairness\n");
2629         }
2630 }
2631
2632 /* This function is called upon link interrupt */
2633 static void bnx2x_link_attn(struct bnx2x *bp)
2634 {
2635         /* Make sure that we are synced with the current statistics */
2636         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637
2638         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2639
2640         bnx2x_init_dropless_fc(bp);
2641
2642         if (bp->link_vars.link_up) {
2643
2644                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2645                         struct host_port_stats *pstats;
2646
2647                         pstats = bnx2x_sp(bp, port_stats);
2648                         /* reset old mac stats */
2649                         memset(&(pstats->mac_stx[0]), 0,
2650                                sizeof(struct mac_stx));
2651                 }
2652                 if (bp->state == BNX2X_STATE_OPEN)
2653                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654         }
2655
2656         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657                 bnx2x_set_local_cmng(bp);
2658
2659         __bnx2x_link_report(bp);
2660
2661         if (IS_MF(bp))
2662                 bnx2x_link_sync_notify(bp);
2663 }
2664
2665 void bnx2x__link_status_update(struct bnx2x *bp)
2666 {
2667         if (bp->state != BNX2X_STATE_OPEN)
2668                 return;
2669
2670         /* read updated dcb configuration */
2671         if (IS_PF(bp)) {
2672                 bnx2x_dcbx_pmf_update(bp);
2673                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674                 if (bp->link_vars.link_up)
2675                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676                 else
2677                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678                         /* indicate link status */
2679                 bnx2x_link_report(bp);
2680
2681         } else { /* VF */
2682                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683                                           SUPPORTED_10baseT_Full |
2684                                           SUPPORTED_100baseT_Half |
2685                                           SUPPORTED_100baseT_Full |
2686                                           SUPPORTED_1000baseT_Full |
2687                                           SUPPORTED_2500baseX_Full |
2688                                           SUPPORTED_10000baseT_Full |
2689                                           SUPPORTED_TP |
2690                                           SUPPORTED_FIBRE |
2691                                           SUPPORTED_Autoneg |
2692                                           SUPPORTED_Pause |
2693                                           SUPPORTED_Asym_Pause);
2694                 bp->port.advertising[0] = bp->port.supported[0];
2695
2696                 bp->link_params.bp = bp;
2697                 bp->link_params.port = BP_PORT(bp);
2698                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700                 bp->link_params.req_line_speed[0] = SPEED_10000;
2701                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704                 bp->link_vars.line_speed = SPEED_10000;
2705                 bp->link_vars.link_status =
2706                         (LINK_STATUS_LINK_UP |
2707                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708                 bp->link_vars.link_up = 1;
2709                 bp->link_vars.duplex = DUPLEX_FULL;
2710                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711                 __bnx2x_link_report(bp);
2712
2713                 bnx2x_sample_bulletin(bp);
2714
2715                 /* if bulletin board did not have an update for link status
2716                  * __bnx2x_link_report will report current status
2717                  * but it will NOT duplicate report in case of already reported
2718                  * during sampling bulletin board.
2719                  */
2720                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721         }
2722 }
2723
2724 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725                                   u16 vlan_val, u8 allowed_prio)
2726 {
2727         struct bnx2x_func_state_params func_params = {NULL};
2728         struct bnx2x_func_afex_update_params *f_update_params =
2729                 &func_params.params.afex_update;
2730
2731         func_params.f_obj = &bp->func_obj;
2732         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733
2734         /* no need to wait for RAMROD completion, so don't
2735          * set RAMROD_COMP_WAIT flag
2736          */
2737
2738         f_update_params->vif_id = vifid;
2739         f_update_params->afex_default_vlan = vlan_val;
2740         f_update_params->allowed_priorities = allowed_prio;
2741
2742         /* if ramrod can not be sent, response to MCP immediately */
2743         if (bnx2x_func_state_change(bp, &func_params) < 0)
2744                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745
2746         return 0;
2747 }
2748
2749 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750                                           u16 vif_index, u8 func_bit_map)
2751 {
2752         struct bnx2x_func_state_params func_params = {NULL};
2753         struct bnx2x_func_afex_viflists_params *update_params =
2754                 &func_params.params.afex_viflists;
2755         int rc;
2756         u32 drv_msg_code;
2757
2758         /* validate only LIST_SET and LIST_GET are received from switch */
2759         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761                           cmd_type);
2762
2763         func_params.f_obj = &bp->func_obj;
2764         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765
2766         /* set parameters according to cmd_type */
2767         update_params->afex_vif_list_command = cmd_type;
2768         update_params->vif_list_index = vif_index;
2769         update_params->func_bit_map =
2770                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771         update_params->func_to_clear = 0;
2772         drv_msg_code =
2773                 (cmd_type == VIF_LIST_RULE_GET) ?
2774                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776
2777         /* if ramrod can not be sent, respond to MCP immediately for
2778          * SET and GET requests (other are not triggered from MCP)
2779          */
2780         rc = bnx2x_func_state_change(bp, &func_params);
2781         if (rc < 0)
2782                 bnx2x_fw_command(bp, drv_msg_code, 0);
2783
2784         return 0;
2785 }
2786
2787 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788 {
2789         struct afex_stats afex_stats;
2790         u32 func = BP_ABS_FUNC(bp);
2791         u32 mf_config;
2792         u16 vlan_val;
2793         u32 vlan_prio;
2794         u16 vif_id;
2795         u8 allowed_prio;
2796         u8 vlan_mode;
2797         u32 addr_to_write, vifid, addrs, stats_type, i;
2798
2799         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801                 DP(BNX2X_MSG_MCP,
2802                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804         }
2805
2806         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809                 DP(BNX2X_MSG_MCP,
2810                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811                    vifid, addrs);
2812                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813                                                addrs);
2814         }
2815
2816         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817                 addr_to_write = SHMEM2_RD(bp,
2818                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819                 stats_type = SHMEM2_RD(bp,
2820                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821
2822                 DP(BNX2X_MSG_MCP,
2823                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824                    addr_to_write);
2825
2826                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827
2828                 /* write response to scratchpad, for MCP */
2829                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2831                                *(((u32 *)(&afex_stats))+i));
2832
2833                 /* send ack message to MCP */
2834                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835         }
2836
2837         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839                 bp->mf_config[BP_VN(bp)] = mf_config;
2840                 DP(BNX2X_MSG_MCP,
2841                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842                    mf_config);
2843
2844                 /* if VIF_SET is "enabled" */
2845                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846                         /* set rate limit directly to internal RAM */
2847                         struct cmng_init_input cmng_input;
2848                         struct rate_shaping_vars_per_vn m_rs_vn;
2849                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850                         u32 addr = BAR_XSTRORM_INTMEM +
2851                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852
2853                         bp->mf_config[BP_VN(bp)] = mf_config;
2854
2855                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856                         m_rs_vn.vn_counter.rate =
2857                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2858                         m_rs_vn.vn_counter.quota =
2859                                 (m_rs_vn.vn_counter.rate *
2860                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2861
2862                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863
2864                         /* read relevant values from mf_cfg struct in shmem */
2865                         vif_id =
2866                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869                         vlan_val =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873                         vlan_prio = (mf_config &
2874                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877                         vlan_mode =
2878                                 (MF_CFG_RD(bp,
2879                                            func_mf_config[func].afex_config) &
2880                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882                         allowed_prio =
2883                                 (MF_CFG_RD(bp,
2884                                            func_mf_config[func].afex_config) &
2885                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887
2888                         /* send ramrod to FW, return in case of failure */
2889                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890                                                    allowed_prio))
2891                                 return;
2892
2893                         bp->afex_def_vlan_tag = vlan_val;
2894                         bp->afex_vlan_mode = vlan_mode;
2895                 } else {
2896                         /* notify link down because BP->flags is disabled */
2897                         bnx2x_link_report(bp);
2898
2899                         /* send INVALID VIF ramrod to FW */
2900                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901
2902                         /* Reset the default afex VLAN */
2903                         bp->afex_def_vlan_tag = -1;
2904                 }
2905         }
2906 }
2907
2908 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2909 {
2910         struct bnx2x_func_switch_update_params *switch_update_params;
2911         struct bnx2x_func_state_params func_params;
2912
2913         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2914         switch_update_params = &func_params.params.switch_update;
2915         func_params.f_obj = &bp->func_obj;
2916         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2917
2918         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2919                 int func = BP_ABS_FUNC(bp);
2920                 u32 val;
2921
2922                 /* Re-learn the S-tag from shmem */
2923                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2924                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2925                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2926                         bp->mf_ov = val;
2927                 } else {
2928                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2929                         goto fail;
2930                 }
2931
2932                 /* Configure new S-tag in LLH */
2933                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2934                        bp->mf_ov);
2935
2936                 /* Send Ramrod to update FW of change */
2937                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2938                           &switch_update_params->changes);
2939                 switch_update_params->vlan = bp->mf_ov;
2940
2941                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2942                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2943                                   bp->mf_ov);
2944                         goto fail;
2945                 } else {
2946                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2947                            bp->mf_ov);
2948                 }
2949         } else {
2950                 goto fail;
2951         }
2952
2953         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2954         return;
2955 fail:
2956         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2957 }
2958
2959 static void bnx2x_pmf_update(struct bnx2x *bp)
2960 {
2961         int port = BP_PORT(bp);
2962         u32 val;
2963
2964         bp->port.pmf = 1;
2965         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2966
2967         /*
2968          * We need the mb() to ensure the ordering between the writing to
2969          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2970          */
2971         smp_mb();
2972
2973         /* queue a periodic task */
2974         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2975
2976         bnx2x_dcbx_pmf_update(bp);
2977
2978         /* enable nig attention */
2979         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2980         if (bp->common.int_block == INT_BLOCK_HC) {
2981                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2982                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2983         } else if (!CHIP_IS_E1x(bp)) {
2984                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2985                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2986         }
2987
2988         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2989 }
2990
2991 /* end of Link */
2992
2993 /* slow path */
2994
2995 /*
2996  * General service functions
2997  */
2998
2999 /* send the MCP a request, block until there is a reply */
3000 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3001 {
3002         int mb_idx = BP_FW_MB_IDX(bp);
3003         u32 seq;
3004         u32 rc = 0;
3005         u32 cnt = 1;
3006         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3007
3008         mutex_lock(&bp->fw_mb_mutex);
3009         seq = ++bp->fw_seq;
3010         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3012
3013         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3014                         (command | seq), param);
3015
3016         do {
3017                 /* let the FW do it's magic ... */
3018                 msleep(delay);
3019
3020                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3021
3022                 /* Give the FW up to 5 second (500*10ms) */
3023         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3024
3025         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3026            cnt*delay, rc, seq);
3027
3028         /* is this a reply to our command? */
3029         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3030                 rc &= FW_MSG_CODE_MASK;
3031         else {
3032                 /* FW BUG! */
3033                 BNX2X_ERR("FW failed to respond!\n");
3034                 bnx2x_fw_dump(bp);
3035                 rc = 0;
3036         }
3037         mutex_unlock(&bp->fw_mb_mutex);
3038
3039         return rc;
3040 }
3041
3042 static void storm_memset_func_cfg(struct bnx2x *bp,
3043                                  struct tstorm_eth_function_common_config *tcfg,
3044                                  u16 abs_fid)
3045 {
3046         size_t size = sizeof(struct tstorm_eth_function_common_config);
3047
3048         u32 addr = BAR_TSTRORM_INTMEM +
3049                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3050
3051         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3052 }
3053
3054 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3055 {
3056         if (CHIP_IS_E1x(bp)) {
3057                 struct tstorm_eth_function_common_config tcfg = {0};
3058
3059                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3060         }
3061
3062         /* Enable the function in the FW */
3063         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3064         storm_memset_func_en(bp, p->func_id, 1);
3065
3066         /* spq */
3067         if (p->spq_active) {
3068                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3069                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3070                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3071         }
3072 }
3073
3074 /**
3075  * bnx2x_get_common_flags - Return common flags
3076  *
3077  * @bp          device handle
3078  * @fp          queue handle
3079  * @zero_stats  TRUE if statistics zeroing is needed
3080  *
3081  * Return the flags that are common for the Tx-only and not normal connections.
3082  */
3083 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3084                                             struct bnx2x_fastpath *fp,
3085                                             bool zero_stats)
3086 {
3087         unsigned long flags = 0;
3088
3089         /* PF driver will always initialize the Queue to an ACTIVE state */
3090         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3091
3092         /* tx only connections collect statistics (on the same index as the
3093          * parent connection). The statistics are zeroed when the parent
3094          * connection is initialized.
3095          */
3096
3097         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3098         if (zero_stats)
3099                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3100
3101         if (bp->flags & TX_SWITCHING)
3102                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3103
3104         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3105         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3106
3107 #ifdef BNX2X_STOP_ON_ERROR
3108         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3109 #endif
3110
3111         return flags;
3112 }
3113
3114 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3115                                        struct bnx2x_fastpath *fp,
3116                                        bool leading)
3117 {
3118         unsigned long flags = 0;
3119
3120         /* calculate other queue flags */
3121         if (IS_MF_SD(bp))
3122                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3123
3124         if (IS_FCOE_FP(fp)) {
3125                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3126                 /* For FCoE - force usage of default priority (for afex) */
3127                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3128         }
3129
3130         if (fp->mode != TPA_MODE_DISABLED) {
3131                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3132                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3133                 if (fp->mode == TPA_MODE_GRO)
3134                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3135         }
3136
3137         if (leading) {
3138                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3139                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3140         }
3141
3142         /* Always set HW VLAN stripping */
3143         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3144
3145         /* configure silent vlan removal */
3146         if (IS_MF_AFEX(bp))
3147                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3148
3149         return flags | bnx2x_get_common_flags(bp, fp, true);
3150 }
3151
3152 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3153         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3154         u8 cos)
3155 {
3156         gen_init->stat_id = bnx2x_stats_id(fp);
3157         gen_init->spcl_id = fp->cl_id;
3158
3159         /* Always use mini-jumbo MTU for FCoE L2 ring */
3160         if (IS_FCOE_FP(fp))
3161                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3162         else
3163                 gen_init->mtu = bp->dev->mtu;
3164
3165         gen_init->cos = cos;
3166
3167         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3168 }
3169
3170 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3171         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3172         struct bnx2x_rxq_setup_params *rxq_init)
3173 {
3174         u8 max_sge = 0;
3175         u16 sge_sz = 0;
3176         u16 tpa_agg_size = 0;
3177
3178         if (fp->mode != TPA_MODE_DISABLED) {
3179                 pause->sge_th_lo = SGE_TH_LO(bp);
3180                 pause->sge_th_hi = SGE_TH_HI(bp);
3181
3182                 /* validate SGE ring has enough to cross high threshold */
3183                 WARN_ON(bp->dropless_fc &&
3184                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3185                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3186
3187                 tpa_agg_size = TPA_AGG_SIZE;
3188                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3189                         SGE_PAGE_SHIFT;
3190                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3191                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3192                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3193         }
3194
3195         /* pause - not for e1 */
3196         if (!CHIP_IS_E1(bp)) {
3197                 pause->bd_th_lo = BD_TH_LO(bp);
3198                 pause->bd_th_hi = BD_TH_HI(bp);
3199
3200                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3201                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3202                 /*
3203                  * validate that rings have enough entries to cross
3204                  * high thresholds
3205                  */
3206                 WARN_ON(bp->dropless_fc &&
3207                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3208                                 bp->rx_ring_size);
3209                 WARN_ON(bp->dropless_fc &&
3210                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3211                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3212
3213                 pause->pri_map = 1;
3214         }
3215
3216         /* rxq setup */
3217         rxq_init->dscr_map = fp->rx_desc_mapping;
3218         rxq_init->sge_map = fp->rx_sge_mapping;
3219         rxq_init->rcq_map = fp->rx_comp_mapping;
3220         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3221
3222         /* This should be a maximum number of data bytes that may be
3223          * placed on the BD (not including paddings).
3224          */
3225         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3226                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3227
3228         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3229         rxq_init->tpa_agg_sz = tpa_agg_size;
3230         rxq_init->sge_buf_sz = sge_sz;
3231         rxq_init->max_sges_pkt = max_sge;
3232         rxq_init->rss_engine_id = BP_FUNC(bp);
3233         rxq_init->mcast_engine_id = BP_FUNC(bp);
3234
3235         /* Maximum number or simultaneous TPA aggregation for this Queue.
3236          *
3237          * For PF Clients it should be the maximum available number.
3238          * VF driver(s) may want to define it to a smaller value.
3239          */
3240         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3241
3242         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3243         rxq_init->fw_sb_id = fp->fw_sb_id;
3244
3245         if (IS_FCOE_FP(fp))
3246                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3247         else
3248                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3249         /* configure silent vlan removal
3250          * if multi function mode is afex, then mask default vlan
3251          */
3252         if (IS_MF_AFEX(bp)) {
3253                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3254                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3255         }
3256 }
3257
3258 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3259         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3260         u8 cos)
3261 {
3262         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3263         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3264         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3265         txq_init->fw_sb_id = fp->fw_sb_id;
3266
3267         /*
3268          * set the tss leading client id for TX classification ==
3269          * leading RSS client id
3270          */
3271         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3272
3273         if (IS_FCOE_FP(fp)) {
3274                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3275                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3276         }
3277 }
3278
3279 static void bnx2x_pf_init(struct bnx2x *bp)
3280 {
3281         struct bnx2x_func_init_params func_init = {0};
3282         struct event_ring_data eq_data = { {0} };
3283
3284         if (!CHIP_IS_E1x(bp)) {
3285                 /* reset IGU PF statistics: MSIX + ATTN */
3286                 /* PF */
3287                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3288                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3289                            (CHIP_MODE_IS_4_PORT(bp) ?
3290                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3291                 /* ATTN */
3292                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3293                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3294                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3295                            (CHIP_MODE_IS_4_PORT(bp) ?
3296                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297         }
3298
3299         func_init.spq_active = true;
3300         func_init.pf_id = BP_FUNC(bp);
3301         func_init.func_id = BP_FUNC(bp);
3302         func_init.spq_map = bp->spq_mapping;
3303         func_init.spq_prod = bp->spq_prod_idx;
3304
3305         bnx2x_func_init(bp, &func_init);
3306
3307         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3308
3309         /*
3310          * Congestion management values depend on the link rate
3311          * There is no active link so initial link rate is set to 10 Gbps.
3312          * When the link comes up The congestion management values are
3313          * re-calculated according to the actual link rate.
3314          */
3315         bp->link_vars.line_speed = SPEED_10000;
3316         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3317
3318         /* Only the PMF sets the HW */
3319         if (bp->port.pmf)
3320                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3321
3322         /* init Event Queue - PCI bus guarantees correct endianity*/
3323         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3324         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3325         eq_data.producer = bp->eq_prod;
3326         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3327         eq_data.sb_id = DEF_SB_ID;
3328         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3329 }
3330
3331 static void bnx2x_e1h_disable(struct bnx2x *bp)
3332 {
3333         int port = BP_PORT(bp);
3334
3335         bnx2x_tx_disable(bp);
3336
3337         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3338 }
3339
3340 static void bnx2x_e1h_enable(struct bnx2x *bp)
3341 {
3342         int port = BP_PORT(bp);
3343
3344         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3345                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3346
3347         /* Tx queue should be only re-enabled */
3348         netif_tx_wake_all_queues(bp->dev);
3349
3350         /*
3351          * Should not call netif_carrier_on since it will be called if the link
3352          * is up when checking for link state
3353          */
3354 }
3355
3356 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3357
3358 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3359 {
3360         struct eth_stats_info *ether_stat =
3361                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3362         struct bnx2x_vlan_mac_obj *mac_obj =
3363                 &bp->sp_objs->mac_obj;
3364         int i;
3365
3366         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3367                 ETH_STAT_INFO_VERSION_LEN);
3368
3369         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3370          * mac_local field in ether_stat struct. The base address is offset by 2
3371          * bytes to account for the field being 8 bytes but a mac address is
3372          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3373          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3374          * allocated by the ether_stat struct, so the macs will land in their
3375          * proper positions.
3376          */
3377         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3378                 memset(ether_stat->mac_local + i, 0,
3379                        sizeof(ether_stat->mac_local[0]));
3380         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3381                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3382                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3383                                 ETH_ALEN);
3384         ether_stat->mtu_size = bp->dev->mtu;
3385         if (bp->dev->features & NETIF_F_RXCSUM)
3386                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3387         if (bp->dev->features & NETIF_F_TSO)
3388                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3389         ether_stat->feature_flags |= bp->common.boot_mode;
3390
3391         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3392
3393         ether_stat->txq_size = bp->tx_ring_size;
3394         ether_stat->rxq_size = bp->rx_ring_size;
3395
3396 #ifdef CONFIG_BNX2X_SRIOV
3397         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3398 #endif
3399 }
3400
3401 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3402 {
3403         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3404         struct fcoe_stats_info *fcoe_stat =
3405                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3406
3407         if (!CNIC_LOADED(bp))
3408                 return;
3409
3410         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3411
3412         fcoe_stat->qos_priority =
3413                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3414
3415         /* insert FCoE stats from ramrod response */
3416         if (!NO_FCOE(bp)) {
3417                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3418                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3419                         tstorm_queue_statistics;
3420
3421                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3422                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3423                         xstorm_queue_statistics;
3424
3425                 struct fcoe_statistics_params *fw_fcoe_stat =
3426                         &bp->fw_stats_data->fcoe;
3427
3428                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3429                           fcoe_stat->rx_bytes_lo,
3430                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3431
3432                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3433                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3434                           fcoe_stat->rx_bytes_lo,
3435                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3436
3437                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3438                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3441
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3446
3447                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3448                           fcoe_stat->rx_frames_lo,
3449                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3450
3451                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3452                           fcoe_stat->rx_frames_lo,
3453                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3454
3455                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456                           fcoe_stat->rx_frames_lo,
3457                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3462
3463                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3464                           fcoe_stat->tx_bytes_lo,
3465                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3466
3467                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3468                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3469                           fcoe_stat->tx_bytes_lo,
3470                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3471
3472                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3473                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3476
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3481
3482                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3483                           fcoe_stat->tx_frames_lo,
3484                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3485
3486                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3487                           fcoe_stat->tx_frames_lo,
3488                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3489
3490                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491                           fcoe_stat->tx_frames_lo,
3492                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3497         }
3498
3499         /* ask L5 driver to add data to the struct */
3500         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3501 }
3502
3503 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3504 {
3505         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3506         struct iscsi_stats_info *iscsi_stat =
3507                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3508
3509         if (!CNIC_LOADED(bp))
3510                 return;
3511
3512         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3513                ETH_ALEN);
3514
3515         iscsi_stat->qos_priority =
3516                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3517
3518         /* ask L5 driver to add data to the struct */
3519         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3520 }
3521
3522 /* called due to MCP event (on pmf):
3523  *      reread new bandwidth configuration
3524  *      configure FW
3525  *      notify others function about the change
3526  */
3527 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3528 {
3529         if (bp->link_vars.link_up) {
3530                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3531                 bnx2x_link_sync_notify(bp);
3532         }
3533         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3534 }
3535
3536 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3537 {
3538         bnx2x_config_mf_bw(bp);
3539         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3540 }
3541
3542 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3543 {
3544         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3545         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3546 }
3547
3548 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3549 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3550
3551 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3552 {
3553         enum drv_info_opcode op_code;
3554         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3555         bool release = false;
3556         int wait;
3557
3558         /* if drv_info version supported by MFW doesn't match - send NACK */
3559         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3560                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3561                 return;
3562         }
3563
3564         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3565                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3566
3567         /* Must prevent other flows from accessing drv_info_to_mcp */
3568         mutex_lock(&bp->drv_info_mutex);
3569
3570         memset(&bp->slowpath->drv_info_to_mcp, 0,
3571                sizeof(union drv_info_to_mcp));
3572
3573         switch (op_code) {
3574         case ETH_STATS_OPCODE:
3575                 bnx2x_drv_info_ether_stat(bp);
3576                 break;
3577         case FCOE_STATS_OPCODE:
3578                 bnx2x_drv_info_fcoe_stat(bp);
3579                 break;
3580         case ISCSI_STATS_OPCODE:
3581                 bnx2x_drv_info_iscsi_stat(bp);
3582                 break;
3583         default:
3584                 /* if op code isn't supported - send NACK */
3585                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3586                 goto out;
3587         }
3588
3589         /* if we got drv_info attn from MFW then these fields are defined in
3590          * shmem2 for sure
3591          */
3592         SHMEM2_WR(bp, drv_info_host_addr_lo,
3593                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3594         SHMEM2_WR(bp, drv_info_host_addr_hi,
3595                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3596
3597         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3598
3599         /* Since possible management wants both this and get_driver_version
3600          * need to wait until management notifies us it finished utilizing
3601          * the buffer.
3602          */
3603         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3604                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3605         } else if (!bp->drv_info_mng_owner) {
3606                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3607
3608                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3609                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3610
3611                         /* Management is done; need to clear indication */
3612                         if (indication & bit) {
3613                                 SHMEM2_WR(bp, mfw_drv_indication,
3614                                           indication & ~bit);
3615                                 release = true;
3616                                 break;
3617                         }
3618
3619                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3620                 }
3621         }
3622         if (!release) {
3623                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3624                 bp->drv_info_mng_owner = true;
3625         }
3626
3627 out:
3628         mutex_unlock(&bp->drv_info_mutex);
3629 }
3630
3631 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3632 {
3633         u8 vals[4];
3634         int i = 0;
3635
3636         if (bnx2x_format) {
3637                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3638                            &vals[0], &vals[1], &vals[2], &vals[3]);
3639                 if (i > 0)
3640                         vals[0] -= '0';
3641         } else {
3642                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3643                            &vals[0], &vals[1], &vals[2], &vals[3]);
3644         }
3645
3646         while (i < 4)
3647                 vals[i++] = 0;
3648
3649         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3650 }
3651
3652 void bnx2x_update_mng_version(struct bnx2x *bp)
3653 {
3654         u32 iscsiver = DRV_VER_NOT_LOADED;
3655         u32 fcoever = DRV_VER_NOT_LOADED;
3656         u32 ethver = DRV_VER_NOT_LOADED;
3657         int idx = BP_FW_MB_IDX(bp);
3658         u8 *version;
3659
3660         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3661                 return;
3662
3663         mutex_lock(&bp->drv_info_mutex);
3664         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3665         if (bp->drv_info_mng_owner)
3666                 goto out;
3667
3668         if (bp->state != BNX2X_STATE_OPEN)
3669                 goto out;
3670
3671         /* Parse ethernet driver version */
3672         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3673         if (!CNIC_LOADED(bp))
3674                 goto out;
3675
3676         /* Try getting storage driver version via cnic */
3677         memset(&bp->slowpath->drv_info_to_mcp, 0,
3678                sizeof(union drv_info_to_mcp));
3679         bnx2x_drv_info_iscsi_stat(bp);
3680         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3681         iscsiver = bnx2x_update_mng_version_utility(version, false);
3682
3683         memset(&bp->slowpath->drv_info_to_mcp, 0,
3684                sizeof(union drv_info_to_mcp));
3685         bnx2x_drv_info_fcoe_stat(bp);
3686         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3687         fcoever = bnx2x_update_mng_version_utility(version, false);
3688
3689 out:
3690         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3691         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3692         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3693
3694         mutex_unlock(&bp->drv_info_mutex);
3695
3696         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3697            ethver, iscsiver, fcoever);
3698 }
3699
3700 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3701 {
3702         u32 drv_ver;
3703         u32 valid_dump;
3704
3705         if (!SHMEM2_HAS(bp, drv_info))
3706                 return;
3707
3708         /* Update Driver load time, possibly broken in y2038 */
3709         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3710
3711         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3712         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3713
3714         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3715
3716         /* Check & notify On-Chip dump. */
3717         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3718
3719         if (valid_dump & FIRST_DUMP_VALID)
3720                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3721
3722         if (valid_dump & SECOND_DUMP_VALID)
3723                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3724 }
3725
3726 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3727 {
3728         u32 cmd_ok, cmd_fail;
3729
3730         /* sanity */
3731         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3732             event & DRV_STATUS_OEM_EVENT_MASK) {
3733                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3734                 return;
3735         }
3736
3737         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3738                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3739                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3740         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3741                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3742                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3743         }
3744
3745         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3746
3747         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3748                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3749                 /* This is the only place besides the function initialization
3750                  * where the bp->flags can change so it is done without any
3751                  * locks
3752                  */
3753                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3754                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3755                         bp->flags |= MF_FUNC_DIS;
3756
3757                         bnx2x_e1h_disable(bp);
3758                 } else {
3759                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3760                         bp->flags &= ~MF_FUNC_DIS;
3761
3762                         bnx2x_e1h_enable(bp);
3763                 }
3764                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3765                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3766         }
3767
3768         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3769                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3770                 bnx2x_config_mf_bw(bp);
3771                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3772                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3773         }
3774
3775         /* Report results to MCP */
3776         if (event)
3777                 bnx2x_fw_command(bp, cmd_fail, 0);
3778         else
3779                 bnx2x_fw_command(bp, cmd_ok, 0);
3780 }
3781
3782 /* must be called under the spq lock */
3783 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3784 {
3785         struct eth_spe *next_spe = bp->spq_prod_bd;
3786
3787         if (bp->spq_prod_bd == bp->spq_last_bd) {
3788                 bp->spq_prod_bd = bp->spq;
3789                 bp->spq_prod_idx = 0;
3790                 DP(BNX2X_MSG_SP, "end of spq\n");
3791         } else {
3792                 bp->spq_prod_bd++;
3793                 bp->spq_prod_idx++;
3794         }
3795         return next_spe;
3796 }
3797
3798 /* must be called under the spq lock */
3799 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3800 {
3801         int func = BP_FUNC(bp);
3802
3803         /*
3804          * Make sure that BD data is updated before writing the producer:
3805          * BD data is written to the memory, the producer is read from the
3806          * memory, thus we need a full memory barrier to ensure the ordering.
3807          */
3808         mb();
3809
3810         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3811                  bp->spq_prod_idx);
3812         mmiowb();
3813 }
3814
3815 /**
3816  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3817  *
3818  * @cmd:        command to check
3819  * @cmd_type:   command type
3820  */
3821 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3822 {
3823         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3824             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3825             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3826             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3827             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3828             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3829             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3830                 return true;
3831         else
3832                 return false;
3833 }
3834
3835 /**
3836  * bnx2x_sp_post - place a single command on an SP ring
3837  *
3838  * @bp:         driver handle
3839  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3840  * @cid:        SW CID the command is related to
3841  * @data_hi:    command private data address (high 32 bits)
3842  * @data_lo:    command private data address (low 32 bits)
3843  * @cmd_type:   command type (e.g. NONE, ETH)
3844  *
3845  * SP data is handled as if it's always an address pair, thus data fields are
3846  * not swapped to little endian in upper functions. Instead this function swaps
3847  * data as if it's two u32 fields.
3848  */
3849 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3850                   u32 data_hi, u32 data_lo, int cmd_type)
3851 {
3852         struct eth_spe *spe;
3853         u16 type;
3854         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3855
3856 #ifdef BNX2X_STOP_ON_ERROR
3857         if (unlikely(bp->panic)) {
3858                 BNX2X_ERR("Can't post SP when there is panic\n");
3859                 return -EIO;
3860         }
3861 #endif
3862
3863         spin_lock_bh(&bp->spq_lock);
3864
3865         if (common) {
3866                 if (!atomic_read(&bp->eq_spq_left)) {
3867                         BNX2X_ERR("BUG! EQ ring full!\n");
3868                         spin_unlock_bh(&bp->spq_lock);
3869                         bnx2x_panic();
3870                         return -EBUSY;
3871                 }
3872         } else if (!atomic_read(&bp->cq_spq_left)) {
3873                         BNX2X_ERR("BUG! SPQ ring full!\n");
3874                         spin_unlock_bh(&bp->spq_lock);
3875                         bnx2x_panic();
3876                         return -EBUSY;
3877         }
3878
3879         spe = bnx2x_sp_get_next(bp);
3880
3881         /* CID needs port number to be encoded int it */
3882         spe->hdr.conn_and_cmd_data =
3883                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3884                                     HW_CID(bp, cid));
3885
3886         /* In some cases, type may already contain the func-id
3887          * mainly in SRIOV related use cases, so we add it here only
3888          * if it's not already set.
3889          */
3890         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3891                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3892                         SPE_HDR_CONN_TYPE;
3893                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3894                          SPE_HDR_FUNCTION_ID);
3895         } else {
3896                 type = cmd_type;
3897         }
3898
3899         spe->hdr.type = cpu_to_le16(type);
3900
3901         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3902         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3903
3904         /*
3905          * It's ok if the actual decrement is issued towards the memory
3906          * somewhere between the spin_lock and spin_unlock. Thus no
3907          * more explicit memory barrier is needed.
3908          */
3909         if (common)
3910                 atomic_dec(&bp->eq_spq_left);
3911         else
3912                 atomic_dec(&bp->cq_spq_left);
3913
3914         DP(BNX2X_MSG_SP,
3915            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3916            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3917            (u32)(U64_LO(bp->spq_mapping) +
3918            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3919            HW_CID(bp, cid), data_hi, data_lo, type,
3920            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3921
3922         bnx2x_sp_prod_update(bp);
3923         spin_unlock_bh(&bp->spq_lock);
3924         return 0;
3925 }
3926
3927 /* acquire split MCP access lock register */
3928 static int bnx2x_acquire_alr(struct bnx2x *bp)
3929 {
3930         u32 j, val;
3931         int rc = 0;
3932
3933         might_sleep();
3934         for (j = 0; j < 1000; j++) {
3935                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3936                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3937                 if (val & MCPR_ACCESS_LOCK_LOCK)
3938                         break;
3939
3940                 usleep_range(5000, 10000);
3941         }
3942         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3943                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3944                 rc = -EBUSY;
3945         }
3946
3947         return rc;
3948 }
3949
3950 /* release split MCP access lock register */
3951 static void bnx2x_release_alr(struct bnx2x *bp)
3952 {
3953         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3954 }
3955
3956 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3957 #define BNX2X_DEF_SB_IDX        0x0002
3958
3959 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3960 {
3961         struct host_sp_status_block *def_sb = bp->def_status_blk;
3962         u16 rc = 0;
3963
3964         barrier(); /* status block is written to by the chip */
3965         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3966                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3967                 rc |= BNX2X_DEF_SB_ATT_IDX;
3968         }
3969
3970         if (bp->def_idx != def_sb->sp_sb.running_index) {
3971                 bp->def_idx = def_sb->sp_sb.running_index;
3972                 rc |= BNX2X_DEF_SB_IDX;
3973         }
3974
3975         /* Do not reorder: indices reading should complete before handling */
3976         barrier();
3977         return rc;
3978 }
3979
3980 /*
3981  * slow path service functions
3982  */
3983
3984 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3985 {
3986         int port = BP_PORT(bp);
3987         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3988                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3989         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3990                                        NIG_REG_MASK_INTERRUPT_PORT0;
3991         u32 aeu_mask;
3992         u32 nig_mask = 0;
3993         u32 reg_addr;
3994
3995         if (bp->attn_state & asserted)
3996                 BNX2X_ERR("IGU ERROR\n");
3997
3998         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3999         aeu_mask = REG_RD(bp, aeu_addr);
4000
4001         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4002            aeu_mask, asserted);
4003         aeu_mask &= ~(asserted & 0x3ff);
4004         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4005
4006         REG_WR(bp, aeu_addr, aeu_mask);
4007         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4008
4009         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4010         bp->attn_state |= asserted;
4011         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4012
4013         if (asserted & ATTN_HARD_WIRED_MASK) {
4014                 if (asserted & ATTN_NIG_FOR_FUNC) {
4015
4016                         bnx2x_acquire_phy_lock(bp);
4017
4018                         /* save nig interrupt mask */
4019                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4020
4021                         /* If nig_mask is not set, no need to call the update
4022                          * function.
4023                          */
4024                         if (nig_mask) {
4025                                 REG_WR(bp, nig_int_mask_addr, 0);
4026
4027                                 bnx2x_link_attn(bp);
4028                         }
4029
4030                         /* handle unicore attn? */
4031                 }
4032                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4033                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4034
4035                 if (asserted & GPIO_2_FUNC)
4036                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4037
4038                 if (asserted & GPIO_3_FUNC)
4039                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4040
4041                 if (asserted & GPIO_4_FUNC)
4042                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4043
4044                 if (port == 0) {
4045                         if (asserted & ATTN_GENERAL_ATTN_1) {
4046                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4047                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4048                         }
4049                         if (asserted & ATTN_GENERAL_ATTN_2) {
4050                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4051                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4052                         }
4053                         if (asserted & ATTN_GENERAL_ATTN_3) {
4054                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4055                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4056                         }
4057                 } else {
4058                         if (asserted & ATTN_GENERAL_ATTN_4) {
4059                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4060                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4061                         }
4062                         if (asserted & ATTN_GENERAL_ATTN_5) {
4063                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4064                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4065                         }
4066                         if (asserted & ATTN_GENERAL_ATTN_6) {
4067                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4068                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4069                         }
4070                 }
4071
4072         } /* if hardwired */
4073
4074         if (bp->common.int_block == INT_BLOCK_HC)
4075                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4076                             COMMAND_REG_ATTN_BITS_SET);
4077         else
4078                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4079
4080         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4081            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4082         REG_WR(bp, reg_addr, asserted);
4083
4084         /* now set back the mask */
4085         if (asserted & ATTN_NIG_FOR_FUNC) {
4086                 /* Verify that IGU ack through BAR was written before restoring
4087                  * NIG mask. This loop should exit after 2-3 iterations max.
4088                  */
4089                 if (bp->common.int_block != INT_BLOCK_HC) {
4090                         u32 cnt = 0, igu_acked;
4091                         do {
4092                                 igu_acked = REG_RD(bp,
4093                                                    IGU_REG_ATTENTION_ACK_BITS);
4094                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4095                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4096                         if (!igu_acked)
4097                                 DP(NETIF_MSG_HW,
4098                                    "Failed to verify IGU ack on time\n");
4099                         barrier();
4100                 }
4101                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4102                 bnx2x_release_phy_lock(bp);
4103         }
4104 }
4105
4106 static void bnx2x_fan_failure(struct bnx2x *bp)
4107 {
4108         int port = BP_PORT(bp);
4109         u32 ext_phy_config;
4110         /* mark the failure */
4111         ext_phy_config =
4112                 SHMEM_RD(bp,
4113                          dev_info.port_hw_config[port].external_phy_config);
4114
4115         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4116         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4117         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4118                  ext_phy_config);
4119
4120         /* log the failure */
4121         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4122                             "Please contact OEM Support for assistance\n");
4123
4124         /* Schedule device reset (unload)
4125          * This is due to some boards consuming sufficient power when driver is
4126          * up to overheat if fan fails.
4127          */
4128         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4129 }
4130
4131 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4132 {
4133         int port = BP_PORT(bp);
4134         int reg_offset;
4135         u32 val;
4136
4137         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4138                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4139
4140         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4141
4142                 val = REG_RD(bp, reg_offset);
4143                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4144                 REG_WR(bp, reg_offset, val);
4145
4146                 BNX2X_ERR("SPIO5 hw attention\n");
4147
4148                 /* Fan failure attention */
4149                 bnx2x_hw_reset_phy(&bp->link_params);
4150                 bnx2x_fan_failure(bp);
4151         }
4152
4153         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4154                 bnx2x_acquire_phy_lock(bp);
4155                 bnx2x_handle_module_detect_int(&bp->link_params);
4156                 bnx2x_release_phy_lock(bp);
4157         }
4158
4159         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4160
4161                 val = REG_RD(bp, reg_offset);
4162                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4163                 REG_WR(bp, reg_offset, val);
4164
4165                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4166                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4167                 bnx2x_panic();
4168         }
4169 }
4170
4171 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4172 {
4173         u32 val;
4174
4175         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4176
4177                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4178                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4179                 /* DORQ discard attention */
4180                 if (val & 0x2)
4181                         BNX2X_ERR("FATAL error from DORQ\n");
4182         }
4183
4184         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4185
4186                 int port = BP_PORT(bp);
4187                 int reg_offset;
4188
4189                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4190                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4191
4192                 val = REG_RD(bp, reg_offset);
4193                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4194                 REG_WR(bp, reg_offset, val);
4195
4196                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4197                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4198                 bnx2x_panic();
4199         }
4200 }
4201
4202 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4203 {
4204         u32 val;
4205
4206         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4207
4208                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4209                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4210                 /* CFC error attention */
4211                 if (val & 0x2)
4212                         BNX2X_ERR("FATAL error from CFC\n");
4213         }
4214
4215         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4216                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4217                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4218                 /* RQ_USDMDP_FIFO_OVERFLOW */
4219                 if (val & 0x18000)
4220                         BNX2X_ERR("FATAL error from PXP\n");
4221
4222                 if (!CHIP_IS_E1x(bp)) {
4223                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4224                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4225                 }
4226         }
4227
4228         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4229
4230                 int port = BP_PORT(bp);
4231                 int reg_offset;
4232
4233                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4234                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4235
4236                 val = REG_RD(bp, reg_offset);
4237                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4238                 REG_WR(bp, reg_offset, val);
4239
4240                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4241                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4242                 bnx2x_panic();
4243         }
4244 }
4245
4246 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4247 {
4248         u32 val;
4249
4250         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4251
4252                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4253                         int func = BP_FUNC(bp);
4254
4255                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4256                         bnx2x_read_mf_cfg(bp);
4257                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4258                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4259                         val = SHMEM_RD(bp,
4260                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4261
4262                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4263                                    DRV_STATUS_OEM_EVENT_MASK))
4264                                 bnx2x_oem_event(bp,
4265                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4266                                                 DRV_STATUS_OEM_EVENT_MASK)));
4267
4268                         if (val & DRV_STATUS_SET_MF_BW)
4269                                 bnx2x_set_mf_bw(bp);
4270
4271                         if (val & DRV_STATUS_DRV_INFO_REQ)
4272                                 bnx2x_handle_drv_info_req(bp);
4273
4274                         if (val & DRV_STATUS_VF_DISABLED)
4275                                 bnx2x_schedule_iov_task(bp,
4276                                                         BNX2X_IOV_HANDLE_FLR);
4277
4278                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4279                                 bnx2x_pmf_update(bp);
4280
4281                         if (bp->port.pmf &&
4282                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4283                                 bp->dcbx_enabled > 0)
4284                                 /* start dcbx state machine */
4285                                 bnx2x_dcbx_set_params(bp,
4286                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4287                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4288                                 bnx2x_handle_afex_cmd(bp,
4289                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4290                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4291                                 bnx2x_handle_eee_event(bp);
4292
4293                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4294                                 bnx2x_handle_update_svid_cmd(bp);
4295
4296                         if (bp->link_vars.periodic_flags &
4297                             PERIODIC_FLAGS_LINK_EVENT) {
4298                                 /*  sync with link */
4299                                 bnx2x_acquire_phy_lock(bp);
4300                                 bp->link_vars.periodic_flags &=
4301                                         ~PERIODIC_FLAGS_LINK_EVENT;
4302                                 bnx2x_release_phy_lock(bp);
4303                                 if (IS_MF(bp))
4304                                         bnx2x_link_sync_notify(bp);
4305                                 bnx2x_link_report(bp);
4306                         }
4307                         /* Always call it here: bnx2x_link_report() will
4308                          * prevent the link indication duplication.
4309                          */
4310                         bnx2x__link_status_update(bp);
4311                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4312
4313                         BNX2X_ERR("MC assert!\n");
4314                         bnx2x_mc_assert(bp);
4315                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4316                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4317                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4318                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4319                         bnx2x_panic();
4320
4321                 } else if (attn & BNX2X_MCP_ASSERT) {
4322
4323                         BNX2X_ERR("MCP assert!\n");
4324                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4325                         bnx2x_fw_dump(bp);
4326
4327                 } else
4328                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4329         }
4330
4331         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4332                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4333                 if (attn & BNX2X_GRC_TIMEOUT) {
4334                         val = CHIP_IS_E1(bp) ? 0 :
4335                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4336                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4337                 }
4338                 if (attn & BNX2X_GRC_RSV) {
4339                         val = CHIP_IS_E1(bp) ? 0 :
4340                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4341                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4342                 }
4343                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4344         }
4345 }
4346
4347 /*
4348  * Bits map:
4349  * 0-7   - Engine0 load counter.
4350  * 8-15  - Engine1 load counter.
4351  * 16    - Engine0 RESET_IN_PROGRESS bit.
4352  * 17    - Engine1 RESET_IN_PROGRESS bit.
4353  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4354  *         on the engine
4355  * 19    - Engine1 ONE_IS_LOADED.
4356  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4357  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4358  *         just the one belonging to its engine).
4359  *
4360  */
4361 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4362
4363 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4364 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4365 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4366 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4367 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4368 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4369 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4370
4371 /*
4372  * Set the GLOBAL_RESET bit.
4373  *
4374  * Should be run under rtnl lock
4375  */
4376 void bnx2x_set_reset_global(struct bnx2x *bp)
4377 {
4378         u32 val;
4379         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4381         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4382         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4383 }
4384
4385 /*
4386  * Clear the GLOBAL_RESET bit.
4387  *
4388  * Should be run under rtnl lock
4389  */
4390 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4391 {
4392         u32 val;
4393         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4394         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4395         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4396         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4397 }
4398
4399 /*
4400  * Checks the GLOBAL_RESET bit.
4401  *
4402  * should be run under rtnl lock
4403  */
4404 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4405 {
4406         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4407
4408         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4409         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4410 }
4411
4412 /*
4413  * Clear RESET_IN_PROGRESS bit for the current engine.
4414  *
4415  * Should be run under rtnl lock
4416  */
4417 static void bnx2x_set_reset_done(struct bnx2x *bp)
4418 {
4419         u32 val;
4420         u32 bit = BP_PATH(bp) ?
4421                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4422         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4423         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4424
4425         /* Clear the bit */
4426         val &= ~bit;
4427         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4428
4429         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4430 }
4431
4432 /*
4433  * Set RESET_IN_PROGRESS for the current engine.
4434  *
4435  * should be run under rtnl lock
4436  */
4437 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4438 {
4439         u32 val;
4440         u32 bit = BP_PATH(bp) ?
4441                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4442         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4443         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4444
4445         /* Set the bit */
4446         val |= bit;
4447         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4448         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4449 }
4450
4451 /*
4452  * Checks the RESET_IN_PROGRESS bit for the given engine.
4453  * should be run under rtnl lock
4454  */
4455 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4456 {
4457         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4458         u32 bit = engine ?
4459                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4460
4461         /* return false if bit is set */
4462         return (val & bit) ? false : true;
4463 }
4464
4465 /*
4466  * set pf load for the current pf.
4467  *
4468  * should be run under rtnl lock
4469  */
4470 void bnx2x_set_pf_load(struct bnx2x *bp)
4471 {
4472         u32 val1, val;
4473         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4474                              BNX2X_PATH0_LOAD_CNT_MASK;
4475         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4476                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4477
4478         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4479         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4480
4481         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4482
4483         /* get the current counter value */
4484         val1 = (val & mask) >> shift;
4485
4486         /* set bit of that PF */
4487         val1 |= (1 << bp->pf_num);
4488
4489         /* clear the old value */
4490         val &= ~mask;
4491
4492         /* set the new one */
4493         val |= ((val1 << shift) & mask);
4494
4495         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4496         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4497 }
4498
4499 /**
4500  * bnx2x_clear_pf_load - clear pf load mark
4501  *
4502  * @bp:         driver handle
4503  *
4504  * Should be run under rtnl lock.
4505  * Decrements the load counter for the current engine. Returns
4506  * whether other functions are still loaded
4507  */
4508 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4509 {
4510         u32 val1, val;
4511         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4512                              BNX2X_PATH0_LOAD_CNT_MASK;
4513         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4514                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4515
4516         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4517         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4518         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4519
4520         /* get the current counter value */
4521         val1 = (val & mask) >> shift;
4522
4523         /* clear bit of that PF */
4524         val1 &= ~(1 << bp->pf_num);
4525
4526         /* clear the old value */
4527         val &= ~mask;
4528
4529         /* set the new one */
4530         val |= ((val1 << shift) & mask);
4531
4532         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4533         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4534         return val1 != 0;
4535 }
4536
4537 /*
4538  * Read the load status for the current engine.
4539  *
4540  * should be run under rtnl lock
4541  */
4542 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4543 {
4544         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4545                              BNX2X_PATH0_LOAD_CNT_MASK);
4546         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4547                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4548         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4549
4550         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4551
4552         val = (val & mask) >> shift;
4553
4554         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4555            engine, val);
4556
4557         return val != 0;
4558 }
4559
4560 static void _print_parity(struct bnx2x *bp, u32 reg)
4561 {
4562         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4563 }
4564
4565 static void _print_next_block(int idx, const char *blk)
4566 {
4567         pr_cont("%s%s", idx ? ", " : "", blk);
4568 }
4569
4570 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4571                                             int *par_num, bool print)
4572 {
4573         u32 cur_bit;
4574         bool res;
4575         int i;
4576
4577         res = false;
4578
4579         for (i = 0; sig; i++) {
4580                 cur_bit = (0x1UL << i);
4581                 if (sig & cur_bit) {
4582                         res |= true; /* Each bit is real error! */
4583
4584                         if (print) {
4585                                 switch (cur_bit) {
4586                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4587                                         _print_next_block((*par_num)++, "BRB");
4588                                         _print_parity(bp,
4589                                                       BRB1_REG_BRB1_PRTY_STS);
4590                                         break;
4591                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4592                                         _print_next_block((*par_num)++,
4593                                                           "PARSER");
4594                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4595                                         break;
4596                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4597                                         _print_next_block((*par_num)++, "TSDM");
4598                                         _print_parity(bp,
4599                                                       TSDM_REG_TSDM_PRTY_STS);
4600                                         break;
4601                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4602                                         _print_next_block((*par_num)++,
4603                                                           "SEARCHER");
4604                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4605                                         break;
4606                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4607                                         _print_next_block((*par_num)++, "TCM");
4608                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4609                                         break;
4610                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4611                                         _print_next_block((*par_num)++,
4612                                                           "TSEMI");
4613                                         _print_parity(bp,
4614                                                       TSEM_REG_TSEM_PRTY_STS_0);
4615                                         _print_parity(bp,
4616                                                       TSEM_REG_TSEM_PRTY_STS_1);
4617                                         break;
4618                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4619                                         _print_next_block((*par_num)++, "XPB");
4620                                         _print_parity(bp, GRCBASE_XPB +
4621                                                           PB_REG_PB_PRTY_STS);
4622                                         break;
4623                                 }
4624                         }
4625
4626                         /* Clear the bit */
4627                         sig &= ~cur_bit;
4628                 }
4629         }
4630
4631         return res;
4632 }
4633
4634 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4635                                             int *par_num, bool *global,
4636                                             bool print)
4637 {
4638         u32 cur_bit;
4639         bool res;
4640         int i;
4641
4642         res = false;
4643
4644         for (i = 0; sig; i++) {
4645                 cur_bit = (0x1UL << i);
4646                 if (sig & cur_bit) {
4647                         res |= true; /* Each bit is real error! */
4648                         switch (cur_bit) {
4649                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4650                                 if (print) {
4651                                         _print_next_block((*par_num)++, "PBF");
4652                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4653                                 }
4654                                 break;
4655                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4656                                 if (print) {
4657                                         _print_next_block((*par_num)++, "QM");
4658                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4659                                 }
4660                                 break;
4661                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4662                                 if (print) {
4663                                         _print_next_block((*par_num)++, "TM");
4664                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4665                                 }
4666                                 break;
4667                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4668                                 if (print) {
4669                                         _print_next_block((*par_num)++, "XSDM");
4670                                         _print_parity(bp,
4671                                                       XSDM_REG_XSDM_PRTY_STS);
4672                                 }
4673                                 break;
4674                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4675                                 if (print) {
4676                                         _print_next_block((*par_num)++, "XCM");
4677                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4678                                 }
4679                                 break;
4680                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4681                                 if (print) {
4682                                         _print_next_block((*par_num)++,
4683                                                           "XSEMI");
4684                                         _print_parity(bp,
4685                                                       XSEM_REG_XSEM_PRTY_STS_0);
4686                                         _print_parity(bp,
4687                                                       XSEM_REG_XSEM_PRTY_STS_1);
4688                                 }
4689                                 break;
4690                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4691                                 if (print) {
4692                                         _print_next_block((*par_num)++,
4693                                                           "DOORBELLQ");
4694                                         _print_parity(bp,
4695                                                       DORQ_REG_DORQ_PRTY_STS);
4696                                 }
4697                                 break;
4698                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4699                                 if (print) {
4700                                         _print_next_block((*par_num)++, "NIG");
4701                                         if (CHIP_IS_E1x(bp)) {
4702                                                 _print_parity(bp,
4703                                                         NIG_REG_NIG_PRTY_STS);
4704                                         } else {
4705                                                 _print_parity(bp,
4706                                                         NIG_REG_NIG_PRTY_STS_0);
4707                                                 _print_parity(bp,
4708                                                         NIG_REG_NIG_PRTY_STS_1);
4709                                         }
4710                                 }
4711                                 break;
4712                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4713                                 if (print)
4714                                         _print_next_block((*par_num)++,
4715                                                           "VAUX PCI CORE");
4716                                 *global = true;
4717                                 break;
4718                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4719                                 if (print) {
4720                                         _print_next_block((*par_num)++,
4721                                                           "DEBUG");
4722                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4723                                 }
4724                                 break;
4725                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4726                                 if (print) {
4727                                         _print_next_block((*par_num)++, "USDM");
4728                                         _print_parity(bp,
4729                                                       USDM_REG_USDM_PRTY_STS);
4730                                 }
4731                                 break;
4732                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4733                                 if (print) {
4734                                         _print_next_block((*par_num)++, "UCM");
4735                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4736                                 }
4737                                 break;
4738                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4739                                 if (print) {
4740                                         _print_next_block((*par_num)++,
4741                                                           "USEMI");
4742                                         _print_parity(bp,
4743                                                       USEM_REG_USEM_PRTY_STS_0);
4744                                         _print_parity(bp,
4745                                                       USEM_REG_USEM_PRTY_STS_1);
4746                                 }
4747                                 break;
4748                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4749                                 if (print) {
4750                                         _print_next_block((*par_num)++, "UPB");
4751                                         _print_parity(bp, GRCBASE_UPB +
4752                                                           PB_REG_PB_PRTY_STS);
4753                                 }
4754                                 break;
4755                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4756                                 if (print) {
4757                                         _print_next_block((*par_num)++, "CSDM");
4758                                         _print_parity(bp,
4759                                                       CSDM_REG_CSDM_PRTY_STS);
4760                                 }
4761                                 break;
4762                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4763                                 if (print) {
4764                                         _print_next_block((*par_num)++, "CCM");
4765                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4766                                 }
4767                                 break;
4768                         }
4769
4770                         /* Clear the bit */
4771                         sig &= ~cur_bit;
4772                 }
4773         }
4774
4775         return res;
4776 }
4777
4778 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4779                                             int *par_num, bool print)
4780 {
4781         u32 cur_bit;
4782         bool res;
4783         int i;
4784
4785         res = false;
4786
4787         for (i = 0; sig; i++) {
4788                 cur_bit = (0x1UL << i);
4789                 if (sig & cur_bit) {
4790                         res = true; /* Each bit is real error! */
4791                         if (print) {
4792                                 switch (cur_bit) {
4793                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4794                                         _print_next_block((*par_num)++,
4795                                                           "CSEMI");
4796                                         _print_parity(bp,
4797                                                       CSEM_REG_CSEM_PRTY_STS_0);
4798                                         _print_parity(bp,
4799                                                       CSEM_REG_CSEM_PRTY_STS_1);
4800                                         break;
4801                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4802                                         _print_next_block((*par_num)++, "PXP");
4803                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4804                                         _print_parity(bp,
4805                                                       PXP2_REG_PXP2_PRTY_STS_0);
4806                                         _print_parity(bp,
4807                                                       PXP2_REG_PXP2_PRTY_STS_1);
4808                                         break;
4809                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4810                                         _print_next_block((*par_num)++,
4811                                                           "PXPPCICLOCKCLIENT");
4812                                         break;
4813                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4814                                         _print_next_block((*par_num)++, "CFC");
4815                                         _print_parity(bp,
4816                                                       CFC_REG_CFC_PRTY_STS);
4817                                         break;
4818                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4819                                         _print_next_block((*par_num)++, "CDU");
4820                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4821                                         break;
4822                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4823                                         _print_next_block((*par_num)++, "DMAE");
4824                                         _print_parity(bp,
4825                                                       DMAE_REG_DMAE_PRTY_STS);
4826                                         break;
4827                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4828                                         _print_next_block((*par_num)++, "IGU");
4829                                         if (CHIP_IS_E1x(bp))
4830                                                 _print_parity(bp,
4831                                                         HC_REG_HC_PRTY_STS);
4832                                         else
4833                                                 _print_parity(bp,
4834                                                         IGU_REG_IGU_PRTY_STS);
4835                                         break;
4836                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4837                                         _print_next_block((*par_num)++, "MISC");
4838                                         _print_parity(bp,
4839                                                       MISC_REG_MISC_PRTY_STS);
4840                                         break;
4841                                 }
4842                         }
4843
4844                         /* Clear the bit */
4845                         sig &= ~cur_bit;
4846                 }
4847         }
4848
4849         return res;
4850 }
4851
4852 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4853                                             int *par_num, bool *global,
4854                                             bool print)
4855 {
4856         bool res = false;
4857         u32 cur_bit;
4858         int i;
4859
4860         for (i = 0; sig; i++) {
4861                 cur_bit = (0x1UL << i);
4862                 if (sig & cur_bit) {
4863                         switch (cur_bit) {
4864                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4865                                 if (print)
4866                                         _print_next_block((*par_num)++,
4867                                                           "MCP ROM");
4868                                 *global = true;
4869                                 res = true;
4870                                 break;
4871                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4872                                 if (print)
4873                                         _print_next_block((*par_num)++,
4874                                                           "MCP UMP RX");
4875                                 *global = true;
4876                                 res = true;
4877                                 break;
4878                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4879                                 if (print)
4880                                         _print_next_block((*par_num)++,
4881                                                           "MCP UMP TX");
4882                                 *global = true;
4883                                 res = true;
4884                                 break;
4885                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4886                                 (*par_num)++;
4887                                 /* clear latched SCPAD PATIRY from MCP */
4888                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4889                                        1UL << 10);
4890                                 break;
4891                         }
4892
4893                         /* Clear the bit */
4894                         sig &= ~cur_bit;
4895                 }
4896         }
4897
4898         return res;
4899 }
4900
4901 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4902                                             int *par_num, bool print)
4903 {
4904         u32 cur_bit;
4905         bool res;
4906         int i;
4907
4908         res = false;
4909
4910         for (i = 0; sig; i++) {
4911                 cur_bit = (0x1UL << i);
4912                 if (sig & cur_bit) {
4913                         res = true; /* Each bit is real error! */
4914                         if (print) {
4915                                 switch (cur_bit) {
4916                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4917                                         _print_next_block((*par_num)++,
4918                                                           "PGLUE_B");
4919                                         _print_parity(bp,
4920                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4921                                         break;
4922                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4923                                         _print_next_block((*par_num)++, "ATC");
4924                                         _print_parity(bp,
4925                                                       ATC_REG_ATC_PRTY_STS);
4926                                         break;
4927                                 }
4928                         }
4929                         /* Clear the bit */
4930                         sig &= ~cur_bit;
4931                 }
4932         }
4933
4934         return res;
4935 }
4936
4937 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4938                               u32 *sig)
4939 {
4940         bool res = false;
4941
4942         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4943             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4944             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4945             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4946             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4947                 int par_num = 0;
4948
4949                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4950                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4951                           sig[0] & HW_PRTY_ASSERT_SET_0,
4952                           sig[1] & HW_PRTY_ASSERT_SET_1,
4953                           sig[2] & HW_PRTY_ASSERT_SET_2,
4954                           sig[3] & HW_PRTY_ASSERT_SET_3,
4955                           sig[4] & HW_PRTY_ASSERT_SET_4);
4956                 if (print) {
4957                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4958                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4959                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4960                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4961                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4962                                 netdev_err(bp->dev,
4963                                            "Parity errors detected in blocks: ");
4964                         } else {
4965                                 print = false;
4966                         }
4967                 }
4968                 res |= bnx2x_check_blocks_with_parity0(bp,
4969                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4970                 res |= bnx2x_check_blocks_with_parity1(bp,
4971                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4972                 res |= bnx2x_check_blocks_with_parity2(bp,
4973                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4974                 res |= bnx2x_check_blocks_with_parity3(bp,
4975                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4976                 res |= bnx2x_check_blocks_with_parity4(bp,
4977                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4978
4979                 if (print)
4980                         pr_cont("\n");
4981         }
4982
4983         return res;
4984 }
4985
4986 /**
4987  * bnx2x_chk_parity_attn - checks for parity attentions.
4988  *
4989  * @bp:         driver handle
4990  * @global:     true if there was a global attention
4991  * @print:      show parity attention in syslog
4992  */
4993 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4994 {
4995         struct attn_route attn = { {0} };
4996         int port = BP_PORT(bp);
4997
4998         attn.sig[0] = REG_RD(bp,
4999                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5000                              port*4);
5001         attn.sig[1] = REG_RD(bp,
5002                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5003                              port*4);
5004         attn.sig[2] = REG_RD(bp,
5005                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5006                              port*4);
5007         attn.sig[3] = REG_RD(bp,
5008                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5009                              port*4);
5010         /* Since MCP attentions can't be disabled inside the block, we need to
5011          * read AEU registers to see whether they're currently disabled
5012          */
5013         attn.sig[3] &= ((REG_RD(bp,
5014                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5015                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5016                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5017                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5018
5019         if (!CHIP_IS_E1x(bp))
5020                 attn.sig[4] = REG_RD(bp,
5021                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5022                                      port*4);
5023
5024         return bnx2x_parity_attn(bp, global, print, attn.sig);
5025 }
5026
5027 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5028 {
5029         u32 val;
5030         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5031
5032                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5033                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5034                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5035                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5036                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5037                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5038                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5039                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5040                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5041                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5042                 if (val &
5043                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5044                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5045                 if (val &
5046                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5047                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5048                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5049                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5050                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5051                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5052                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5053                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5054         }
5055         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5056                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5057                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5058                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5059                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5060                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5061                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5062                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5063                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5064                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5065                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5066                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5067                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5068                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5069                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5070         }
5071
5072         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5073                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5074                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5075                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5076                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5077         }
5078 }
5079
5080 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5081 {
5082         struct attn_route attn, *group_mask;
5083         int port = BP_PORT(bp);
5084         int index;
5085         u32 reg_addr;
5086         u32 val;
5087         u32 aeu_mask;
5088         bool global = false;
5089
5090         /* need to take HW lock because MCP or other port might also
5091            try to handle this event */
5092         bnx2x_acquire_alr(bp);
5093
5094         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5095 #ifndef BNX2X_STOP_ON_ERROR
5096                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5097                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5098                 /* Disable HW interrupts */
5099                 bnx2x_int_disable(bp);
5100                 /* In case of parity errors don't handle attentions so that
5101                  * other function would "see" parity errors.
5102                  */
5103 #else
5104                 bnx2x_panic();
5105 #endif
5106                 bnx2x_release_alr(bp);
5107                 return;
5108         }
5109
5110         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5111         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5112         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5113         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5114         if (!CHIP_IS_E1x(bp))
5115                 attn.sig[4] =
5116                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5117         else
5118                 attn.sig[4] = 0;
5119
5120         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5121            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5122
5123         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5124                 if (deasserted & (1 << index)) {
5125                         group_mask = &bp->attn_group[index];
5126
5127                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5128                            index,
5129                            group_mask->sig[0], group_mask->sig[1],
5130                            group_mask->sig[2], group_mask->sig[3],
5131                            group_mask->sig[4]);
5132
5133                         bnx2x_attn_int_deasserted4(bp,
5134                                         attn.sig[4] & group_mask->sig[4]);
5135                         bnx2x_attn_int_deasserted3(bp,
5136                                         attn.sig[3] & group_mask->sig[3]);
5137                         bnx2x_attn_int_deasserted1(bp,
5138                                         attn.sig[1] & group_mask->sig[1]);
5139                         bnx2x_attn_int_deasserted2(bp,
5140                                         attn.sig[2] & group_mask->sig[2]);
5141                         bnx2x_attn_int_deasserted0(bp,
5142                                         attn.sig[0] & group_mask->sig[0]);
5143                 }
5144         }
5145
5146         bnx2x_release_alr(bp);
5147
5148         if (bp->common.int_block == INT_BLOCK_HC)
5149                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5150                             COMMAND_REG_ATTN_BITS_CLR);
5151         else
5152                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5153
5154         val = ~deasserted;
5155         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5156            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5157         REG_WR(bp, reg_addr, val);
5158
5159         if (~bp->attn_state & deasserted)
5160                 BNX2X_ERR("IGU ERROR\n");
5161
5162         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5163                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5164
5165         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5166         aeu_mask = REG_RD(bp, reg_addr);
5167
5168         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5169            aeu_mask, deasserted);
5170         aeu_mask |= (deasserted & 0x3ff);
5171         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5172
5173         REG_WR(bp, reg_addr, aeu_mask);
5174         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5175
5176         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5177         bp->attn_state &= ~deasserted;
5178         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5179 }
5180
5181 static void bnx2x_attn_int(struct bnx2x *bp)
5182 {
5183         /* read local copy of bits */
5184         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5185                                                                 attn_bits);
5186         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5187                                                                 attn_bits_ack);
5188         u32 attn_state = bp->attn_state;
5189
5190         /* look for changed bits */
5191         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5192         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5193
5194         DP(NETIF_MSG_HW,
5195            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5196            attn_bits, attn_ack, asserted, deasserted);
5197
5198         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5199                 BNX2X_ERR("BAD attention state\n");
5200
5201         /* handle bits that were raised */
5202         if (asserted)
5203                 bnx2x_attn_int_asserted(bp, asserted);
5204
5205         if (deasserted)
5206                 bnx2x_attn_int_deasserted(bp, deasserted);
5207 }
5208
5209 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5210                       u16 index, u8 op, u8 update)
5211 {
5212         u32 igu_addr = bp->igu_base_addr;
5213         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5214         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5215                              igu_addr);
5216 }
5217
5218 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5219 {
5220         /* No memory barriers */
5221         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5222         mmiowb(); /* keep prod updates ordered */
5223 }
5224
5225 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5226                                       union event_ring_elem *elem)
5227 {
5228         u8 err = elem->message.error;
5229
5230         if (!bp->cnic_eth_dev.starting_cid  ||
5231             (cid < bp->cnic_eth_dev.starting_cid &&
5232             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5233                 return 1;
5234
5235         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5236
5237         if (unlikely(err)) {
5238
5239                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5240                           cid);
5241                 bnx2x_panic_dump(bp, false);
5242         }
5243         bnx2x_cnic_cfc_comp(bp, cid, err);
5244         return 0;
5245 }
5246
5247 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5248 {
5249         struct bnx2x_mcast_ramrod_params rparam;
5250         int rc;
5251
5252         memset(&rparam, 0, sizeof(rparam));
5253
5254         rparam.mcast_obj = &bp->mcast_obj;
5255
5256         netif_addr_lock_bh(bp->dev);
5257
5258         /* Clear pending state for the last command */
5259         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5260
5261         /* If there are pending mcast commands - send them */
5262         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5263                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5264                 if (rc < 0)
5265                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5266                                   rc);
5267         }
5268
5269         netif_addr_unlock_bh(bp->dev);
5270 }
5271
5272 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5273                                             union event_ring_elem *elem)
5274 {
5275         unsigned long ramrod_flags = 0;
5276         int rc = 0;
5277         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5278         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5279
5280         /* Always push next commands out, don't wait here */
5281         __set_bit(RAMROD_CONT, &ramrod_flags);
5282
5283         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5284                             >> BNX2X_SWCID_SHIFT) {
5285         case BNX2X_FILTER_MAC_PENDING:
5286                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5287                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5288                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5289                 else
5290                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5291
5292                 break;
5293         case BNX2X_FILTER_VLAN_PENDING:
5294                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5295                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5296                 break;
5297         case BNX2X_FILTER_MCAST_PENDING:
5298                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5299                 /* This is only relevant for 57710 where multicast MACs are
5300                  * configured as unicast MACs using the same ramrod.
5301                  */
5302                 bnx2x_handle_mcast_eqe(bp);
5303                 return;
5304         default:
5305                 BNX2X_ERR("Unsupported classification command: %d\n",
5306                           elem->message.data.eth_event.echo);
5307                 return;
5308         }
5309
5310         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5311
5312         if (rc < 0)
5313                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5314         else if (rc > 0)
5315                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5316 }
5317
5318 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5319
5320 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5321 {
5322         netif_addr_lock_bh(bp->dev);
5323
5324         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5325
5326         /* Send rx_mode command again if was requested */
5327         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5328                 bnx2x_set_storm_rx_mode(bp);
5329         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5330                                     &bp->sp_state))
5331                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5332         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5333                                     &bp->sp_state))
5334                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5335
5336         netif_addr_unlock_bh(bp->dev);
5337 }
5338
5339 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5340                                               union event_ring_elem *elem)
5341 {
5342         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5343                 DP(BNX2X_MSG_SP,
5344                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5345                    elem->message.data.vif_list_event.func_bit_map);
5346                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5347                         elem->message.data.vif_list_event.func_bit_map);
5348         } else if (elem->message.data.vif_list_event.echo ==
5349                    VIF_LIST_RULE_SET) {
5350                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5351                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5352         }
5353 }
5354
5355 /* called with rtnl_lock */
5356 static void bnx2x_after_function_update(struct bnx2x *bp)
5357 {
5358         int q, rc;
5359         struct bnx2x_fastpath *fp;
5360         struct bnx2x_queue_state_params queue_params = {NULL};
5361         struct bnx2x_queue_update_params *q_update_params =
5362                 &queue_params.params.update;
5363
5364         /* Send Q update command with afex vlan removal values for all Qs */
5365         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5366
5367         /* set silent vlan removal values according to vlan mode */
5368         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5369                   &q_update_params->update_flags);
5370         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5371                   &q_update_params->update_flags);
5372         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5373
5374         /* in access mode mark mask and value are 0 to strip all vlans */
5375         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5376                 q_update_params->silent_removal_value = 0;
5377                 q_update_params->silent_removal_mask = 0;
5378         } else {
5379                 q_update_params->silent_removal_value =
5380                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5381                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5382         }
5383
5384         for_each_eth_queue(bp, q) {
5385                 /* Set the appropriate Queue object */
5386                 fp = &bp->fp[q];
5387                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5388
5389                 /* send the ramrod */
5390                 rc = bnx2x_queue_state_change(bp, &queue_params);
5391                 if (rc < 0)
5392                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5393                                   q);
5394         }
5395
5396         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5397                 fp = &bp->fp[FCOE_IDX(bp)];
5398                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5399
5400                 /* clear pending completion bit */
5401                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5402
5403                 /* mark latest Q bit */
5404                 smp_mb__before_atomic();
5405                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5406                 smp_mb__after_atomic();
5407
5408                 /* send Q update ramrod for FCoE Q */
5409                 rc = bnx2x_queue_state_change(bp, &queue_params);
5410                 if (rc < 0)
5411                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5412                                   q);
5413         } else {
5414                 /* If no FCoE ring - ACK MCP now */
5415                 bnx2x_link_report(bp);
5416                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5417         }
5418 }
5419
5420 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5421         struct bnx2x *bp, u32 cid)
5422 {
5423         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5424
5425         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5426                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5427         else
5428                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5429 }
5430
5431 static void bnx2x_eq_int(struct bnx2x *bp)
5432 {
5433         u16 hw_cons, sw_cons, sw_prod;
5434         union event_ring_elem *elem;
5435         u8 echo;
5436         u32 cid;
5437         u8 opcode;
5438         int rc, spqe_cnt = 0;
5439         struct bnx2x_queue_sp_obj *q_obj;
5440         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5441         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5442
5443         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5444
5445         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5446          * when we get the next-page we need to adjust so the loop
5447          * condition below will be met. The next element is the size of a
5448          * regular element and hence incrementing by 1
5449          */
5450         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5451                 hw_cons++;
5452
5453         /* This function may never run in parallel with itself for a
5454          * specific bp, thus there is no need in "paired" read memory
5455          * barrier here.
5456          */
5457         sw_cons = bp->eq_cons;
5458         sw_prod = bp->eq_prod;
5459
5460         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5461                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5462
5463         for (; sw_cons != hw_cons;
5464               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5465
5466                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5467
5468                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5469                 if (!rc) {
5470                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5471                            rc);
5472                         goto next_spqe;
5473                 }
5474
5475                 /* elem CID originates from FW; actually LE */
5476                 cid = SW_CID((__force __le32)
5477                              elem->message.data.cfc_del_event.cid);
5478                 opcode = elem->message.opcode;
5479
5480                 /* handle eq element */
5481                 switch (opcode) {
5482                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5483                         bnx2x_vf_mbx_schedule(bp,
5484                                               &elem->message.data.vf_pf_event);
5485                         continue;
5486
5487                 case EVENT_RING_OPCODE_STAT_QUERY:
5488                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5489                                "got statistics comp event %d\n",
5490                                bp->stats_comp++);
5491                         /* nothing to do with stats comp */
5492                         goto next_spqe;
5493
5494                 case EVENT_RING_OPCODE_CFC_DEL:
5495                         /* handle according to cid range */
5496                         /*
5497                          * we may want to verify here that the bp state is
5498                          * HALTING
5499                          */
5500                         DP(BNX2X_MSG_SP,
5501                            "got delete ramrod for MULTI[%d]\n", cid);
5502
5503                         if (CNIC_LOADED(bp) &&
5504                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5505                                 goto next_spqe;
5506
5507                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5508
5509                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5510                                 break;
5511
5512                         goto next_spqe;
5513
5514                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5515                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5516                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5517                         if (f_obj->complete_cmd(bp, f_obj,
5518                                                 BNX2X_F_CMD_TX_STOP))
5519                                 break;
5520                         goto next_spqe;
5521
5522                 case EVENT_RING_OPCODE_START_TRAFFIC:
5523                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5524                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5525                         if (f_obj->complete_cmd(bp, f_obj,
5526                                                 BNX2X_F_CMD_TX_START))
5527                                 break;
5528                         goto next_spqe;
5529
5530                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5531                         echo = elem->message.data.function_update_event.echo;
5532                         if (echo == SWITCH_UPDATE) {
5533                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5534                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5535                                 if (f_obj->complete_cmd(
5536                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5537                                         break;
5538
5539                         } else {
5540                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5541
5542                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5543                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5544                                 f_obj->complete_cmd(bp, f_obj,
5545                                                     BNX2X_F_CMD_AFEX_UPDATE);
5546
5547                                 /* We will perform the Queues update from
5548                                  * sp_rtnl task as all Queue SP operations
5549                                  * should run under rtnl_lock.
5550                                  */
5551                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5552                         }
5553
5554                         goto next_spqe;
5555
5556                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5557                         f_obj->complete_cmd(bp, f_obj,
5558                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5559                         bnx2x_after_afex_vif_lists(bp, elem);
5560                         goto next_spqe;
5561                 case EVENT_RING_OPCODE_FUNCTION_START:
5562                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5563                            "got FUNC_START ramrod\n");
5564                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5565                                 break;
5566
5567                         goto next_spqe;
5568
5569                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5570                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5571                            "got FUNC_STOP ramrod\n");
5572                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5573                                 break;
5574
5575                         goto next_spqe;
5576
5577                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5578                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5579                            "got set_timesync ramrod completion\n");
5580                         if (f_obj->complete_cmd(bp, f_obj,
5581                                                 BNX2X_F_CMD_SET_TIMESYNC))
5582                                 break;
5583                         goto next_spqe;
5584                 }
5585
5586                 switch (opcode | bp->state) {
5587                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5588                       BNX2X_STATE_OPEN):
5589                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5590                       BNX2X_STATE_OPENING_WAIT4_PORT):
5591                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5592                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5593                         cid = elem->message.data.eth_event.echo &
5594                                 BNX2X_SWCID_MASK;
5595                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5596                            cid);
5597                         rss_raw->clear_pending(rss_raw);
5598                         break;
5599
5600                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5601                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5602                 case (EVENT_RING_OPCODE_SET_MAC |
5603                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5604                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5605                       BNX2X_STATE_OPEN):
5606                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5607                       BNX2X_STATE_DIAG):
5608                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5609                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5610                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5611                         bnx2x_handle_classification_eqe(bp, elem);
5612                         break;
5613
5614                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5615                       BNX2X_STATE_OPEN):
5616                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5617                       BNX2X_STATE_DIAG):
5618                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5619                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5620                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5621                         bnx2x_handle_mcast_eqe(bp);
5622                         break;
5623
5624                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5625                       BNX2X_STATE_OPEN):
5626                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5627                       BNX2X_STATE_DIAG):
5628                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5629                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5630                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5631                         bnx2x_handle_rx_mode_eqe(bp);
5632                         break;
5633                 default:
5634                         /* unknown event log error and continue */
5635                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5636                                   elem->message.opcode, bp->state);
5637                 }
5638 next_spqe:
5639                 spqe_cnt++;
5640         } /* for */
5641
5642         smp_mb__before_atomic();
5643         atomic_add(spqe_cnt, &bp->eq_spq_left);
5644
5645         bp->eq_cons = sw_cons;
5646         bp->eq_prod = sw_prod;
5647         /* Make sure that above mem writes were issued towards the memory */
5648         smp_wmb();
5649
5650         /* update producer */
5651         bnx2x_update_eq_prod(bp, bp->eq_prod);
5652 }
5653
5654 static void bnx2x_sp_task(struct work_struct *work)
5655 {
5656         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5657
5658         DP(BNX2X_MSG_SP, "sp task invoked\n");
5659
5660         /* make sure the atomic interrupt_occurred has been written */
5661         smp_rmb();
5662         if (atomic_read(&bp->interrupt_occurred)) {
5663
5664                 /* what work needs to be performed? */
5665                 u16 status = bnx2x_update_dsb_idx(bp);
5666
5667                 DP(BNX2X_MSG_SP, "status %x\n", status);
5668                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5669                 atomic_set(&bp->interrupt_occurred, 0);
5670
5671                 /* HW attentions */
5672                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5673                         bnx2x_attn_int(bp);
5674                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5675                 }
5676
5677                 /* SP events: STAT_QUERY and others */
5678                 if (status & BNX2X_DEF_SB_IDX) {
5679                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5680
5681                 if (FCOE_INIT(bp) &&
5682                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5683                                 /* Prevent local bottom-halves from running as
5684                                  * we are going to change the local NAPI list.
5685                                  */
5686                                 local_bh_disable();
5687                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5688                                 local_bh_enable();
5689                         }
5690
5691                         /* Handle EQ completions */
5692                         bnx2x_eq_int(bp);
5693                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5694                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5695
5696                         status &= ~BNX2X_DEF_SB_IDX;
5697                 }
5698
5699                 /* if status is non zero then perhaps something went wrong */
5700                 if (unlikely(status))
5701                         DP(BNX2X_MSG_SP,
5702                            "got an unknown interrupt! (status 0x%x)\n", status);
5703
5704                 /* ack status block only if something was actually handled */
5705                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5706                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5707         }
5708
5709         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5710         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5711                                &bp->sp_state)) {
5712                 bnx2x_link_report(bp);
5713                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5714         }
5715 }
5716
5717 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5718 {
5719         struct net_device *dev = dev_instance;
5720         struct bnx2x *bp = netdev_priv(dev);
5721
5722         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5723                      IGU_INT_DISABLE, 0);
5724
5725 #ifdef BNX2X_STOP_ON_ERROR
5726         if (unlikely(bp->panic))
5727                 return IRQ_HANDLED;
5728 #endif
5729
5730         if (CNIC_LOADED(bp)) {
5731                 struct cnic_ops *c_ops;
5732
5733                 rcu_read_lock();
5734                 c_ops = rcu_dereference(bp->cnic_ops);
5735                 if (c_ops)
5736                         c_ops->cnic_handler(bp->cnic_data, NULL);
5737                 rcu_read_unlock();
5738         }
5739
5740         /* schedule sp task to perform default status block work, ack
5741          * attentions and enable interrupts.
5742          */
5743         bnx2x_schedule_sp_task(bp);
5744
5745         return IRQ_HANDLED;
5746 }
5747
5748 /* end of slow path */
5749
5750 void bnx2x_drv_pulse(struct bnx2x *bp)
5751 {
5752         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5753                  bp->fw_drv_pulse_wr_seq);
5754 }
5755
5756 static void bnx2x_timer(unsigned long data)
5757 {
5758         struct bnx2x *bp = (struct bnx2x *) data;
5759
5760         if (!netif_running(bp->dev))
5761                 return;
5762
5763         if (IS_PF(bp) &&
5764             !BP_NOMCP(bp)) {
5765                 int mb_idx = BP_FW_MB_IDX(bp);
5766                 u16 drv_pulse;
5767                 u16 mcp_pulse;
5768
5769                 ++bp->fw_drv_pulse_wr_seq;
5770                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5771                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5772                 bnx2x_drv_pulse(bp);
5773
5774                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5775                              MCP_PULSE_SEQ_MASK);
5776                 /* The delta between driver pulse and mcp response
5777                  * should not get too big. If the MFW is more than 5 pulses
5778                  * behind, we should worry about it enough to generate an error
5779                  * log.
5780                  */
5781                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5782                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5783                                   drv_pulse, mcp_pulse);
5784         }
5785
5786         if (bp->state == BNX2X_STATE_OPEN)
5787                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5788
5789         /* sample pf vf bulletin board for new posts from pf */
5790         if (IS_VF(bp))
5791                 bnx2x_timer_sriov(bp);
5792
5793         mod_timer(&bp->timer, jiffies + bp->current_interval);
5794 }
5795
5796 /* end of Statistics */
5797
5798 /* nic init */
5799
5800 /*
5801  * nic init service functions
5802  */
5803
5804 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5805 {
5806         u32 i;
5807         if (!(len%4) && !(addr%4))
5808                 for (i = 0; i < len; i += 4)
5809                         REG_WR(bp, addr + i, fill);
5810         else
5811                 for (i = 0; i < len; i++)
5812                         REG_WR8(bp, addr + i, fill);
5813 }
5814
5815 /* helper: writes FP SP data to FW - data_size in dwords */
5816 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5817                                 int fw_sb_id,
5818                                 u32 *sb_data_p,
5819                                 u32 data_size)
5820 {
5821         int index;
5822         for (index = 0; index < data_size; index++)
5823                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5824                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5825                         sizeof(u32)*index,
5826                         *(sb_data_p + index));
5827 }
5828
5829 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5830 {
5831         u32 *sb_data_p;
5832         u32 data_size = 0;
5833         struct hc_status_block_data_e2 sb_data_e2;
5834         struct hc_status_block_data_e1x sb_data_e1x;
5835
5836         /* disable the function first */
5837         if (!CHIP_IS_E1x(bp)) {
5838                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5839                 sb_data_e2.common.state = SB_DISABLED;
5840                 sb_data_e2.common.p_func.vf_valid = false;
5841                 sb_data_p = (u32 *)&sb_data_e2;
5842                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5843         } else {
5844                 memset(&sb_data_e1x, 0,
5845                        sizeof(struct hc_status_block_data_e1x));
5846                 sb_data_e1x.common.state = SB_DISABLED;
5847                 sb_data_e1x.common.p_func.vf_valid = false;
5848                 sb_data_p = (u32 *)&sb_data_e1x;
5849                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5850         }
5851         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5852
5853         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5854                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5855                         CSTORM_STATUS_BLOCK_SIZE);
5856         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5857                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5858                         CSTORM_SYNC_BLOCK_SIZE);
5859 }
5860
5861 /* helper:  writes SP SB data to FW */
5862 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5863                 struct hc_sp_status_block_data *sp_sb_data)
5864 {
5865         int func = BP_FUNC(bp);
5866         int i;
5867         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5868                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5869                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5870                         i*sizeof(u32),
5871                         *((u32 *)sp_sb_data + i));
5872 }
5873
5874 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5875 {
5876         int func = BP_FUNC(bp);
5877         struct hc_sp_status_block_data sp_sb_data;
5878         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5879
5880         sp_sb_data.state = SB_DISABLED;
5881         sp_sb_data.p_func.vf_valid = false;
5882
5883         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5884
5885         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5886                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5887                         CSTORM_SP_STATUS_BLOCK_SIZE);
5888         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5889                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5890                         CSTORM_SP_SYNC_BLOCK_SIZE);
5891 }
5892
5893 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5894                                            int igu_sb_id, int igu_seg_id)
5895 {
5896         hc_sm->igu_sb_id = igu_sb_id;
5897         hc_sm->igu_seg_id = igu_seg_id;
5898         hc_sm->timer_value = 0xFF;
5899         hc_sm->time_to_expire = 0xFFFFFFFF;
5900 }
5901
5902 /* allocates state machine ids. */
5903 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5904 {
5905         /* zero out state machine indices */
5906         /* rx indices */
5907         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5908
5909         /* tx indices */
5910         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5911         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5912         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5913         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5914
5915         /* map indices */
5916         /* rx indices */
5917         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5918                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5919
5920         /* tx indices */
5921         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5922                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5923         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5924                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5925         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5926                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5927         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5928                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929 }
5930
5931 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5932                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5933 {
5934         int igu_seg_id;
5935
5936         struct hc_status_block_data_e2 sb_data_e2;
5937         struct hc_status_block_data_e1x sb_data_e1x;
5938         struct hc_status_block_sm  *hc_sm_p;
5939         int data_size;
5940         u32 *sb_data_p;
5941
5942         if (CHIP_INT_MODE_IS_BC(bp))
5943                 igu_seg_id = HC_SEG_ACCESS_NORM;
5944         else
5945                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5946
5947         bnx2x_zero_fp_sb(bp, fw_sb_id);
5948
5949         if (!CHIP_IS_E1x(bp)) {
5950                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5951                 sb_data_e2.common.state = SB_ENABLED;
5952                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5953                 sb_data_e2.common.p_func.vf_id = vfid;
5954                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5955                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5956                 sb_data_e2.common.same_igu_sb_1b = true;
5957                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5958                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5959                 hc_sm_p = sb_data_e2.common.state_machine;
5960                 sb_data_p = (u32 *)&sb_data_e2;
5961                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5962                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5963         } else {
5964                 memset(&sb_data_e1x, 0,
5965                        sizeof(struct hc_status_block_data_e1x));
5966                 sb_data_e1x.common.state = SB_ENABLED;
5967                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5968                 sb_data_e1x.common.p_func.vf_id = 0xff;
5969                 sb_data_e1x.common.p_func.vf_valid = false;
5970                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5971                 sb_data_e1x.common.same_igu_sb_1b = true;
5972                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5973                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5974                 hc_sm_p = sb_data_e1x.common.state_machine;
5975                 sb_data_p = (u32 *)&sb_data_e1x;
5976                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5977                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5978         }
5979
5980         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5981                                        igu_sb_id, igu_seg_id);
5982         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5983                                        igu_sb_id, igu_seg_id);
5984
5985         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5986
5987         /* write indices to HW - PCI guarantees endianity of regpairs */
5988         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5989 }
5990
5991 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5992                                      u16 tx_usec, u16 rx_usec)
5993 {
5994         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5995                                     false, rx_usec);
5996         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5997                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5998                                        tx_usec);
5999         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6000                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6001                                        tx_usec);
6002         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6003                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6004                                        tx_usec);
6005 }
6006
6007 static void bnx2x_init_def_sb(struct bnx2x *bp)
6008 {
6009         struct host_sp_status_block *def_sb = bp->def_status_blk;
6010         dma_addr_t mapping = bp->def_status_blk_mapping;
6011         int igu_sp_sb_index;
6012         int igu_seg_id;
6013         int port = BP_PORT(bp);
6014         int func = BP_FUNC(bp);
6015         int reg_offset, reg_offset_en5;
6016         u64 section;
6017         int index;
6018         struct hc_sp_status_block_data sp_sb_data;
6019         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6020
6021         if (CHIP_INT_MODE_IS_BC(bp)) {
6022                 igu_sp_sb_index = DEF_SB_IGU_ID;
6023                 igu_seg_id = HC_SEG_ACCESS_DEF;
6024         } else {
6025                 igu_sp_sb_index = bp->igu_dsb_id;
6026                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6027         }
6028
6029         /* ATTN */
6030         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6031                                             atten_status_block);
6032         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6033
6034         bp->attn_state = 0;
6035
6036         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6037                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6038         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6039                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6040         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6041                 int sindex;
6042                 /* take care of sig[0]..sig[4] */
6043                 for (sindex = 0; sindex < 4; sindex++)
6044                         bp->attn_group[index].sig[sindex] =
6045                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6046
6047                 if (!CHIP_IS_E1x(bp))
6048                         /*
6049                          * enable5 is separate from the rest of the registers,
6050                          * and therefore the address skip is 4
6051                          * and not 16 between the different groups
6052                          */
6053                         bp->attn_group[index].sig[4] = REG_RD(bp,
6054                                         reg_offset_en5 + 0x4*index);
6055                 else
6056                         bp->attn_group[index].sig[4] = 0;
6057         }
6058
6059         if (bp->common.int_block == INT_BLOCK_HC) {
6060                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6061                                      HC_REG_ATTN_MSG0_ADDR_L);
6062
6063                 REG_WR(bp, reg_offset, U64_LO(section));
6064                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6065         } else if (!CHIP_IS_E1x(bp)) {
6066                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6067                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6068         }
6069
6070         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6071                                             sp_sb);
6072
6073         bnx2x_zero_sp_sb(bp);
6074
6075         /* PCI guarantees endianity of regpairs */
6076         sp_sb_data.state                = SB_ENABLED;
6077         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6078         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6079         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6080         sp_sb_data.igu_seg_id           = igu_seg_id;
6081         sp_sb_data.p_func.pf_id         = func;
6082         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6083         sp_sb_data.p_func.vf_id         = 0xff;
6084
6085         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6086
6087         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6088 }
6089
6090 void bnx2x_update_coalesce(struct bnx2x *bp)
6091 {
6092         int i;
6093
6094         for_each_eth_queue(bp, i)
6095                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6096                                          bp->tx_ticks, bp->rx_ticks);
6097 }
6098
6099 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6100 {
6101         spin_lock_init(&bp->spq_lock);
6102         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6103
6104         bp->spq_prod_idx = 0;
6105         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6106         bp->spq_prod_bd = bp->spq;
6107         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6108 }
6109
6110 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6111 {
6112         int i;
6113         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6114                 union event_ring_elem *elem =
6115                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6116
6117                 elem->next_page.addr.hi =
6118                         cpu_to_le32(U64_HI(bp->eq_mapping +
6119                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6120                 elem->next_page.addr.lo =
6121                         cpu_to_le32(U64_LO(bp->eq_mapping +
6122                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6123         }
6124         bp->eq_cons = 0;
6125         bp->eq_prod = NUM_EQ_DESC;
6126         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6127         /* we want a warning message before it gets wrought... */
6128         atomic_set(&bp->eq_spq_left,
6129                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6130 }
6131
6132 /* called with netif_addr_lock_bh() */
6133 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6134                                unsigned long rx_mode_flags,
6135                                unsigned long rx_accept_flags,
6136                                unsigned long tx_accept_flags,
6137                                unsigned long ramrod_flags)
6138 {
6139         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6140         int rc;
6141
6142         memset(&ramrod_param, 0, sizeof(ramrod_param));
6143
6144         /* Prepare ramrod parameters */
6145         ramrod_param.cid = 0;
6146         ramrod_param.cl_id = cl_id;
6147         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6148         ramrod_param.func_id = BP_FUNC(bp);
6149
6150         ramrod_param.pstate = &bp->sp_state;
6151         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6152
6153         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6154         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6155
6156         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6157
6158         ramrod_param.ramrod_flags = ramrod_flags;
6159         ramrod_param.rx_mode_flags = rx_mode_flags;
6160
6161         ramrod_param.rx_accept_flags = rx_accept_flags;
6162         ramrod_param.tx_accept_flags = tx_accept_flags;
6163
6164         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6165         if (rc < 0) {
6166                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6167                 return rc;
6168         }
6169
6170         return 0;
6171 }
6172
6173 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6174                                    unsigned long *rx_accept_flags,
6175                                    unsigned long *tx_accept_flags)
6176 {
6177         /* Clear the flags first */
6178         *rx_accept_flags = 0;
6179         *tx_accept_flags = 0;
6180
6181         switch (rx_mode) {
6182         case BNX2X_RX_MODE_NONE:
6183                 /*
6184                  * 'drop all' supersedes any accept flags that may have been
6185                  * passed to the function.
6186                  */
6187                 break;
6188         case BNX2X_RX_MODE_NORMAL:
6189                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6190                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6191                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6192
6193                 /* internal switching mode */
6194                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6195                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6196                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6197
6198                 if (bp->accept_any_vlan) {
6199                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6200                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6201                 }
6202
6203                 break;
6204         case BNX2X_RX_MODE_ALLMULTI:
6205                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6206                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6207                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6208
6209                 /* internal switching mode */
6210                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6211                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6212                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6213
6214                 if (bp->accept_any_vlan) {
6215                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6216                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6217                 }
6218
6219                 break;
6220         case BNX2X_RX_MODE_PROMISC:
6221                 /* According to definition of SI mode, iface in promisc mode
6222                  * should receive matched and unmatched (in resolution of port)
6223                  * unicast packets.
6224                  */
6225                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6226                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6227                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6228                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6229
6230                 /* internal switching mode */
6231                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6232                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6233
6234                 if (IS_MF_SI(bp))
6235                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6236                 else
6237                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6238
6239                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6240                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6241
6242                 break;
6243         default:
6244                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6245                 return -EINVAL;
6246         }
6247
6248         return 0;
6249 }
6250
6251 /* called with netif_addr_lock_bh() */
6252 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6253 {
6254         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6255         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6256         int rc;
6257
6258         if (!NO_FCOE(bp))
6259                 /* Configure rx_mode of FCoE Queue */
6260                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6261
6262         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6263                                      &tx_accept_flags);
6264         if (rc)
6265                 return rc;
6266
6267         __set_bit(RAMROD_RX, &ramrod_flags);
6268         __set_bit(RAMROD_TX, &ramrod_flags);
6269
6270         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6271                                    rx_accept_flags, tx_accept_flags,
6272                                    ramrod_flags);
6273 }
6274
6275 static void bnx2x_init_internal_common(struct bnx2x *bp)
6276 {
6277         int i;
6278
6279         /* Zero this manually as its initialization is
6280            currently missing in the initTool */
6281         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6282                 REG_WR(bp, BAR_USTRORM_INTMEM +
6283                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6284         if (!CHIP_IS_E1x(bp)) {
6285                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6286                         CHIP_INT_MODE_IS_BC(bp) ?
6287                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6288         }
6289 }
6290
6291 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6292 {
6293         switch (load_code) {
6294         case FW_MSG_CODE_DRV_LOAD_COMMON:
6295         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6296                 bnx2x_init_internal_common(bp);
6297                 /* no break */
6298
6299         case FW_MSG_CODE_DRV_LOAD_PORT:
6300                 /* nothing to do */
6301                 /* no break */
6302
6303         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6304                 /* internal memory per function is
6305                    initialized inside bnx2x_pf_init */
6306                 break;
6307
6308         default:
6309                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6310                 break;
6311         }
6312 }
6313
6314 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6315 {
6316         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6317 }
6318
6319 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6320 {
6321         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6322 }
6323
6324 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6325 {
6326         if (CHIP_IS_E1x(fp->bp))
6327                 return BP_L_ID(fp->bp) + fp->index;
6328         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6329                 return bnx2x_fp_igu_sb_id(fp);
6330 }
6331
6332 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6333 {
6334         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6335         u8 cos;
6336         unsigned long q_type = 0;
6337         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6338         fp->rx_queue = fp_idx;
6339         fp->cid = fp_idx;
6340         fp->cl_id = bnx2x_fp_cl_id(fp);
6341         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6342         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6343         /* qZone id equals to FW (per path) client id */
6344         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6345
6346         /* init shortcut */
6347         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6348
6349         /* Setup SB indices */
6350         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6351
6352         /* Configure Queue State object */
6353         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6354         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6355
6356         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6357
6358         /* init tx data */
6359         for_each_cos_in_tx_queue(fp, cos) {
6360                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6361                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6362                                   FP_COS_TO_TXQ(fp, cos, bp),
6363                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6364                 cids[cos] = fp->txdata_ptr[cos]->cid;
6365         }
6366
6367         /* nothing more for vf to do here */
6368         if (IS_VF(bp))
6369                 return;
6370
6371         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6372                       fp->fw_sb_id, fp->igu_sb_id);
6373         bnx2x_update_fpsb_idx(fp);
6374         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6375                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6376                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6377
6378         /**
6379          * Configure classification DBs: Always enable Tx switching
6380          */
6381         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6382
6383         DP(NETIF_MSG_IFUP,
6384            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6385            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6386            fp->igu_sb_id);
6387 }
6388
6389 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6390 {
6391         int i;
6392
6393         for (i = 1; i <= NUM_TX_RINGS; i++) {
6394                 struct eth_tx_next_bd *tx_next_bd =
6395                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6396
6397                 tx_next_bd->addr_hi =
6398                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6399                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6400                 tx_next_bd->addr_lo =
6401                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6402                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6403         }
6404
6405         *txdata->tx_cons_sb = cpu_to_le16(0);
6406
6407         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6408         txdata->tx_db.data.zero_fill1 = 0;
6409         txdata->tx_db.data.prod = 0;
6410
6411         txdata->tx_pkt_prod = 0;
6412         txdata->tx_pkt_cons = 0;
6413         txdata->tx_bd_prod = 0;
6414         txdata->tx_bd_cons = 0;
6415         txdata->tx_pkt = 0;
6416 }
6417
6418 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6419 {
6420         int i;
6421
6422         for_each_tx_queue_cnic(bp, i)
6423                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6424 }
6425
6426 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6427 {
6428         int i;
6429         u8 cos;
6430
6431         for_each_eth_queue(bp, i)
6432                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6433                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6434 }
6435
6436 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6437 {
6438         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6439         unsigned long q_type = 0;
6440
6441         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6442         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6443                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6444         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6445         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6446         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6447         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6448         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6449                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6450                           fp);
6451
6452         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6453
6454         /* qZone id equals to FW (per path) client id */
6455         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6456         /* init shortcut */
6457         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6458                 bnx2x_rx_ustorm_prods_offset(fp);
6459
6460         /* Configure Queue State object */
6461         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6462         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6463
6464         /* No multi-CoS for FCoE L2 client */
6465         BUG_ON(fp->max_cos != 1);
6466
6467         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6468                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6469                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6470
6471         DP(NETIF_MSG_IFUP,
6472            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6473            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6474            fp->igu_sb_id);
6475 }
6476
6477 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6478 {
6479         if (!NO_FCOE(bp))
6480                 bnx2x_init_fcoe_fp(bp);
6481
6482         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6483                       BNX2X_VF_ID_INVALID, false,
6484                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6485
6486         /* ensure status block indices were read */
6487         rmb();
6488         bnx2x_init_rx_rings_cnic(bp);
6489         bnx2x_init_tx_rings_cnic(bp);
6490
6491         /* flush all */
6492         mb();
6493         mmiowb();
6494 }
6495
6496 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6497 {
6498         int i;
6499
6500         /* Setup NIC internals and enable interrupts */
6501         for_each_eth_queue(bp, i)
6502                 bnx2x_init_eth_fp(bp, i);
6503
6504         /* ensure status block indices were read */
6505         rmb();
6506         bnx2x_init_rx_rings(bp);
6507         bnx2x_init_tx_rings(bp);
6508
6509         if (IS_PF(bp)) {
6510                 /* Initialize MOD_ABS interrupts */
6511                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6512                                        bp->common.shmem_base,
6513                                        bp->common.shmem2_base, BP_PORT(bp));
6514
6515                 /* initialize the default status block and sp ring */
6516                 bnx2x_init_def_sb(bp);
6517                 bnx2x_update_dsb_idx(bp);
6518                 bnx2x_init_sp_ring(bp);
6519         } else {
6520                 bnx2x_memset_stats(bp);
6521         }
6522 }
6523
6524 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6525 {
6526         bnx2x_init_eq_ring(bp);
6527         bnx2x_init_internal(bp, load_code);
6528         bnx2x_pf_init(bp);
6529         bnx2x_stats_init(bp);
6530
6531         /* flush all before enabling interrupts */
6532         mb();
6533         mmiowb();
6534
6535         bnx2x_int_enable(bp);
6536
6537         /* Check for SPIO5 */
6538         bnx2x_attn_int_deasserted0(bp,
6539                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6540                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6541 }
6542
6543 /* gzip service functions */
6544 static int bnx2x_gunzip_init(struct bnx2x *bp)
6545 {
6546         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6547                                             &bp->gunzip_mapping, GFP_KERNEL);
6548         if (bp->gunzip_buf  == NULL)
6549                 goto gunzip_nomem1;
6550
6551         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6552         if (bp->strm  == NULL)
6553                 goto gunzip_nomem2;
6554
6555         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6556         if (bp->strm->workspace == NULL)
6557                 goto gunzip_nomem3;
6558
6559         return 0;
6560
6561 gunzip_nomem3:
6562         kfree(bp->strm);
6563         bp->strm = NULL;
6564
6565 gunzip_nomem2:
6566         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6567                           bp->gunzip_mapping);
6568         bp->gunzip_buf = NULL;
6569
6570 gunzip_nomem1:
6571         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6572         return -ENOMEM;
6573 }
6574
6575 static void bnx2x_gunzip_end(struct bnx2x *bp)
6576 {
6577         if (bp->strm) {
6578                 vfree(bp->strm->workspace);
6579                 kfree(bp->strm);
6580                 bp->strm = NULL;
6581         }
6582
6583         if (bp->gunzip_buf) {
6584                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6585                                   bp->gunzip_mapping);
6586                 bp->gunzip_buf = NULL;
6587         }
6588 }
6589
6590 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6591 {
6592         int n, rc;
6593
6594         /* check gzip header */
6595         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6596                 BNX2X_ERR("Bad gzip header\n");
6597                 return -EINVAL;
6598         }
6599
6600         n = 10;
6601
6602 #define FNAME                           0x8
6603
6604         if (zbuf[3] & FNAME)
6605                 while ((zbuf[n++] != 0) && (n < len));
6606
6607         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6608         bp->strm->avail_in = len - n;
6609         bp->strm->next_out = bp->gunzip_buf;
6610         bp->strm->avail_out = FW_BUF_SIZE;
6611
6612         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6613         if (rc != Z_OK)
6614                 return rc;
6615
6616         rc = zlib_inflate(bp->strm, Z_FINISH);
6617         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6618                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6619                            bp->strm->msg);
6620
6621         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6622         if (bp->gunzip_outlen & 0x3)
6623                 netdev_err(bp->dev,
6624                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6625                                 bp->gunzip_outlen);
6626         bp->gunzip_outlen >>= 2;
6627
6628         zlib_inflateEnd(bp->strm);
6629
6630         if (rc == Z_STREAM_END)
6631                 return 0;
6632
6633         return rc;
6634 }
6635
6636 /* nic load/unload */
6637
6638 /*
6639  * General service functions
6640  */
6641
6642 /* send a NIG loopback debug packet */
6643 static void bnx2x_lb_pckt(struct bnx2x *bp)
6644 {
6645         u32 wb_write[3];
6646
6647         /* Ethernet source and destination addresses */
6648         wb_write[0] = 0x55555555;
6649         wb_write[1] = 0x55555555;
6650         wb_write[2] = 0x20;             /* SOP */
6651         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6652
6653         /* NON-IP protocol */
6654         wb_write[0] = 0x09000000;
6655         wb_write[1] = 0x55555555;
6656         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6657         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6658 }
6659
6660 /* some of the internal memories
6661  * are not directly readable from the driver
6662  * to test them we send debug packets
6663  */
6664 static int bnx2x_int_mem_test(struct bnx2x *bp)
6665 {
6666         int factor;
6667         int count, i;
6668         u32 val = 0;
6669
6670         if (CHIP_REV_IS_FPGA(bp))
6671                 factor = 120;
6672         else if (CHIP_REV_IS_EMUL(bp))
6673                 factor = 200;
6674         else
6675                 factor = 1;
6676
6677         /* Disable inputs of parser neighbor blocks */
6678         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6679         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6680         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6681         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6682
6683         /*  Write 0 to parser credits for CFC search request */
6684         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6685
6686         /* send Ethernet packet */
6687         bnx2x_lb_pckt(bp);
6688
6689         /* TODO do i reset NIG statistic? */
6690         /* Wait until NIG register shows 1 packet of size 0x10 */
6691         count = 1000 * factor;
6692         while (count) {
6693
6694                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6695                 val = *bnx2x_sp(bp, wb_data[0]);
6696                 if (val == 0x10)
6697                         break;
6698
6699                 usleep_range(10000, 20000);
6700                 count--;
6701         }
6702         if (val != 0x10) {
6703                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6704                 return -1;
6705         }
6706
6707         /* Wait until PRS register shows 1 packet */
6708         count = 1000 * factor;
6709         while (count) {
6710                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6711                 if (val == 1)
6712                         break;
6713
6714                 usleep_range(10000, 20000);
6715                 count--;
6716         }
6717         if (val != 0x1) {
6718                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6719                 return -2;
6720         }
6721
6722         /* Reset and init BRB, PRS */
6723         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6724         msleep(50);
6725         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6726         msleep(50);
6727         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6728         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6729
6730         DP(NETIF_MSG_HW, "part2\n");
6731
6732         /* Disable inputs of parser neighbor blocks */
6733         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6734         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6735         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6736         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6737
6738         /* Write 0 to parser credits for CFC search request */
6739         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6740
6741         /* send 10 Ethernet packets */
6742         for (i = 0; i < 10; i++)
6743                 bnx2x_lb_pckt(bp);
6744
6745         /* Wait until NIG register shows 10 + 1
6746            packets of size 11*0x10 = 0xb0 */
6747         count = 1000 * factor;
6748         while (count) {
6749
6750                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6751                 val = *bnx2x_sp(bp, wb_data[0]);
6752                 if (val == 0xb0)
6753                         break;
6754
6755                 usleep_range(10000, 20000);
6756                 count--;
6757         }
6758         if (val != 0xb0) {
6759                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6760                 return -3;
6761         }
6762
6763         /* Wait until PRS register shows 2 packets */
6764         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6765         if (val != 2)
6766                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6767
6768         /* Write 1 to parser credits for CFC search request */
6769         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6770
6771         /* Wait until PRS register shows 3 packets */
6772         msleep(10 * factor);
6773         /* Wait until NIG register shows 1 packet of size 0x10 */
6774         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6775         if (val != 3)
6776                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6777
6778         /* clear NIG EOP FIFO */
6779         for (i = 0; i < 11; i++)
6780                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6781         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6782         if (val != 1) {
6783                 BNX2X_ERR("clear of NIG failed\n");
6784                 return -4;
6785         }
6786
6787         /* Reset and init BRB, PRS, NIG */
6788         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6789         msleep(50);
6790         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6791         msleep(50);
6792         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6793         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6794         if (!CNIC_SUPPORT(bp))
6795                 /* set NIC mode */
6796                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6797
6798         /* Enable inputs of parser neighbor blocks */
6799         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6800         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6801         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6802         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6803
6804         DP(NETIF_MSG_HW, "done\n");
6805
6806         return 0; /* OK */
6807 }
6808
6809 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6810 {
6811         u32 val;
6812
6813         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6814         if (!CHIP_IS_E1x(bp))
6815                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6816         else
6817                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6818         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6819         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6820         /*
6821          * mask read length error interrupts in brb for parser
6822          * (parsing unit and 'checksum and crc' unit)
6823          * these errors are legal (PU reads fixed length and CAC can cause
6824          * read length error on truncated packets)
6825          */
6826         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6827         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6828         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6829         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6830         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6831         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6832 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6833 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6834         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6835         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6836         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6837 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6838 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6839         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6840         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6841         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6842         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6843 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6844 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6845
6846         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6847                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6848                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6849         if (!CHIP_IS_E1x(bp))
6850                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6851                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6852         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6853
6854         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6855         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6856         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6857 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6858
6859         if (!CHIP_IS_E1x(bp))
6860                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6861                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6862
6863         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6864         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6865 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6866         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6867 }
6868
6869 static void bnx2x_reset_common(struct bnx2x *bp)
6870 {
6871         u32 val = 0x1400;
6872
6873         /* reset_common */
6874         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6875                0xd3ffff7f);
6876
6877         if (CHIP_IS_E3(bp)) {
6878                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6879                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6880         }
6881
6882         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6883 }
6884
6885 static void bnx2x_setup_dmae(struct bnx2x *bp)
6886 {
6887         bp->dmae_ready = 0;
6888         spin_lock_init(&bp->dmae_lock);
6889 }
6890
6891 static void bnx2x_init_pxp(struct bnx2x *bp)
6892 {
6893         u16 devctl;
6894         int r_order, w_order;
6895
6896         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6897         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6898         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6899         if (bp->mrrs == -1)
6900                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6901         else {
6902                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6903                 r_order = bp->mrrs;
6904         }
6905
6906         bnx2x_init_pxp_arb(bp, r_order, w_order);
6907 }
6908
6909 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6910 {
6911         int is_required;
6912         u32 val;
6913         int port;
6914
6915         if (BP_NOMCP(bp))
6916                 return;
6917
6918         is_required = 0;
6919         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6920               SHARED_HW_CFG_FAN_FAILURE_MASK;
6921
6922         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6923                 is_required = 1;
6924
6925         /*
6926          * The fan failure mechanism is usually related to the PHY type since
6927          * the power consumption of the board is affected by the PHY. Currently,
6928          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6929          */
6930         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6931                 for (port = PORT_0; port < PORT_MAX; port++) {
6932                         is_required |=
6933                                 bnx2x_fan_failure_det_req(
6934                                         bp,
6935                                         bp->common.shmem_base,
6936                                         bp->common.shmem2_base,
6937                                         port);
6938                 }
6939
6940         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6941
6942         if (is_required == 0)
6943                 return;
6944
6945         /* Fan failure is indicated by SPIO 5 */
6946         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6947
6948         /* set to active low mode */
6949         val = REG_RD(bp, MISC_REG_SPIO_INT);
6950         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6951         REG_WR(bp, MISC_REG_SPIO_INT, val);
6952
6953         /* enable interrupt to signal the IGU */
6954         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6955         val |= MISC_SPIO_SPIO5;
6956         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6957 }
6958
6959 void bnx2x_pf_disable(struct bnx2x *bp)
6960 {
6961         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6962         val &= ~IGU_PF_CONF_FUNC_EN;
6963
6964         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6965         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6966         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6967 }
6968
6969 static void bnx2x__common_init_phy(struct bnx2x *bp)
6970 {
6971         u32 shmem_base[2], shmem2_base[2];
6972         /* Avoid common init in case MFW supports LFA */
6973         if (SHMEM2_RD(bp, size) >
6974             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6975                 return;
6976         shmem_base[0] =  bp->common.shmem_base;
6977         shmem2_base[0] = bp->common.shmem2_base;
6978         if (!CHIP_IS_E1x(bp)) {
6979                 shmem_base[1] =
6980                         SHMEM2_RD(bp, other_shmem_base_addr);
6981                 shmem2_base[1] =
6982                         SHMEM2_RD(bp, other_shmem2_base_addr);
6983         }
6984         bnx2x_acquire_phy_lock(bp);
6985         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6986                               bp->common.chip_id);
6987         bnx2x_release_phy_lock(bp);
6988 }
6989
6990 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6991 {
6992         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6993         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6994         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6995         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6996         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6997
6998         /* make sure this value is 0 */
6999         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7000
7001         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7002         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7003         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7004         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7005 }
7006
7007 static void bnx2x_set_endianity(struct bnx2x *bp)
7008 {
7009 #ifdef __BIG_ENDIAN
7010         bnx2x_config_endianity(bp, 1);
7011 #else
7012         bnx2x_config_endianity(bp, 0);
7013 #endif
7014 }
7015
7016 static void bnx2x_reset_endianity(struct bnx2x *bp)
7017 {
7018         bnx2x_config_endianity(bp, 0);
7019 }
7020
7021 /**
7022  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7023  *
7024  * @bp:         driver handle
7025  */
7026 static int bnx2x_init_hw_common(struct bnx2x *bp)
7027 {
7028         u32 val;
7029
7030         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7031
7032         /*
7033          * take the RESET lock to protect undi_unload flow from accessing
7034          * registers while we're resetting the chip
7035          */
7036         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7037
7038         bnx2x_reset_common(bp);
7039         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7040
7041         val = 0xfffc;
7042         if (CHIP_IS_E3(bp)) {
7043                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7044                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7045         }
7046         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7047
7048         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7049
7050         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7051
7052         if (!CHIP_IS_E1x(bp)) {
7053                 u8 abs_func_id;
7054
7055                 /**
7056                  * 4-port mode or 2-port mode we need to turn of master-enable
7057                  * for everyone, after that, turn it back on for self.
7058                  * so, we disregard multi-function or not, and always disable
7059                  * for all functions on the given path, this means 0,2,4,6 for
7060                  * path 0 and 1,3,5,7 for path 1
7061                  */
7062                 for (abs_func_id = BP_PATH(bp);
7063                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7064                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7065                                 REG_WR(bp,
7066                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7067                                     1);
7068                                 continue;
7069                         }
7070
7071                         bnx2x_pretend_func(bp, abs_func_id);
7072                         /* clear pf enable */
7073                         bnx2x_pf_disable(bp);
7074                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7075                 }
7076         }
7077
7078         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7079         if (CHIP_IS_E1(bp)) {
7080                 /* enable HW interrupt from PXP on USDM overflow
7081                    bit 16 on INT_MASK_0 */
7082                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7083         }
7084
7085         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7086         bnx2x_init_pxp(bp);
7087         bnx2x_set_endianity(bp);
7088         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7089
7090         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7091                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7092
7093         /* let the HW do it's magic ... */
7094         msleep(100);
7095         /* finish PXP init */
7096         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7097         if (val != 1) {
7098                 BNX2X_ERR("PXP2 CFG failed\n");
7099                 return -EBUSY;
7100         }
7101         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7102         if (val != 1) {
7103                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7104                 return -EBUSY;
7105         }
7106
7107         /* Timers bug workaround E2 only. We need to set the entire ILT to
7108          * have entries with value "0" and valid bit on.
7109          * This needs to be done by the first PF that is loaded in a path
7110          * (i.e. common phase)
7111          */
7112         if (!CHIP_IS_E1x(bp)) {
7113 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7114  * (i.e. vnic3) to start even if it is marked as "scan-off".
7115  * This occurs when a different function (func2,3) is being marked
7116  * as "scan-off". Real-life scenario for example: if a driver is being
7117  * load-unloaded while func6,7 are down. This will cause the timer to access
7118  * the ilt, translate to a logical address and send a request to read/write.
7119  * Since the ilt for the function that is down is not valid, this will cause
7120  * a translation error which is unrecoverable.
7121  * The Workaround is intended to make sure that when this happens nothing fatal
7122  * will occur. The workaround:
7123  *      1.  First PF driver which loads on a path will:
7124  *              a.  After taking the chip out of reset, by using pretend,
7125  *                  it will write "0" to the following registers of
7126  *                  the other vnics.
7127  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7128  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7129  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7130  *                  And for itself it will write '1' to
7131  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7132  *                  dmae-operations (writing to pram for example.)
7133  *                  note: can be done for only function 6,7 but cleaner this
7134  *                        way.
7135  *              b.  Write zero+valid to the entire ILT.
7136  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7137  *                  VNIC3 (of that port). The range allocated will be the
7138  *                  entire ILT. This is needed to prevent  ILT range error.
7139  *      2.  Any PF driver load flow:
7140  *              a.  ILT update with the physical addresses of the allocated
7141  *                  logical pages.
7142  *              b.  Wait 20msec. - note that this timeout is needed to make
7143  *                  sure there are no requests in one of the PXP internal
7144  *                  queues with "old" ILT addresses.
7145  *              c.  PF enable in the PGLC.
7146  *              d.  Clear the was_error of the PF in the PGLC. (could have
7147  *                  occurred while driver was down)
7148  *              e.  PF enable in the CFC (WEAK + STRONG)
7149  *              f.  Timers scan enable
7150  *      3.  PF driver unload flow:
7151  *              a.  Clear the Timers scan_en.
7152  *              b.  Polling for scan_on=0 for that PF.
7153  *              c.  Clear the PF enable bit in the PXP.
7154  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7155  *              e.  Write zero+valid to all ILT entries (The valid bit must
7156  *                  stay set)
7157  *              f.  If this is VNIC 3 of a port then also init
7158  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7159  *                  to the last entry in the ILT.
7160  *
7161  *      Notes:
7162  *      Currently the PF error in the PGLC is non recoverable.
7163  *      In the future the there will be a recovery routine for this error.
7164  *      Currently attention is masked.
7165  *      Having an MCP lock on the load/unload process does not guarantee that
7166  *      there is no Timer disable during Func6/7 enable. This is because the
7167  *      Timers scan is currently being cleared by the MCP on FLR.
7168  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7169  *      there is error before clearing it. But the flow above is simpler and
7170  *      more general.
7171  *      All ILT entries are written by zero+valid and not just PF6/7
7172  *      ILT entries since in the future the ILT entries allocation for
7173  *      PF-s might be dynamic.
7174  */
7175                 struct ilt_client_info ilt_cli;
7176                 struct bnx2x_ilt ilt;
7177                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7178                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7179
7180                 /* initialize dummy TM client */
7181                 ilt_cli.start = 0;
7182                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7183                 ilt_cli.client_num = ILT_CLIENT_TM;
7184
7185                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7186                  * Step 2: set the timers first/last ilt entry to point
7187                  * to the entire range to prevent ILT range error for 3rd/4th
7188                  * vnic (this code assumes existence of the vnic)
7189                  *
7190                  * both steps performed by call to bnx2x_ilt_client_init_op()
7191                  * with dummy TM client
7192                  *
7193                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7194                  * and his brother are split registers
7195                  */
7196                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7197                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7198                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7199
7200                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7201                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7202                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7203         }
7204
7205         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7206         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7207
7208         if (!CHIP_IS_E1x(bp)) {
7209                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7210                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7211                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7212
7213                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7214
7215                 /* let the HW do it's magic ... */
7216                 do {
7217                         msleep(200);
7218                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7219                 } while (factor-- && (val != 1));
7220
7221                 if (val != 1) {
7222                         BNX2X_ERR("ATC_INIT failed\n");
7223                         return -EBUSY;
7224                 }
7225         }
7226
7227         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7228
7229         bnx2x_iov_init_dmae(bp);
7230
7231         /* clean the DMAE memory */
7232         bp->dmae_ready = 1;
7233         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7234
7235         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7236
7237         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7238
7239         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7240
7241         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7242
7243         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7244         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7245         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7246         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7247
7248         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7249
7250         /* QM queues pointers table */
7251         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7252
7253         /* soft reset pulse */
7254         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7255         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7256
7257         if (CNIC_SUPPORT(bp))
7258                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7259
7260         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7261
7262         if (!CHIP_REV_IS_SLOW(bp))
7263                 /* enable hw interrupt from doorbell Q */
7264                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7265
7266         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7267
7268         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7269         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7270
7271         if (!CHIP_IS_E1(bp))
7272                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7273
7274         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7275                 if (IS_MF_AFEX(bp)) {
7276                         /* configure that VNTag and VLAN headers must be
7277                          * received in afex mode
7278                          */
7279                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7280                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7281                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7282                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7283                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7284                 } else {
7285                         /* Bit-map indicating which L2 hdrs may appear
7286                          * after the basic Ethernet header
7287                          */
7288                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7289                                bp->path_has_ovlan ? 7 : 6);
7290                 }
7291         }
7292
7293         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7294         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7295         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7296         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7297
7298         if (!CHIP_IS_E1x(bp)) {
7299                 /* reset VFC memories */
7300                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7301                            VFC_MEMORIES_RST_REG_CAM_RST |
7302                            VFC_MEMORIES_RST_REG_RAM_RST);
7303                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7304                            VFC_MEMORIES_RST_REG_CAM_RST |
7305                            VFC_MEMORIES_RST_REG_RAM_RST);
7306
7307                 msleep(20);
7308         }
7309
7310         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7311         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7312         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7313         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7314
7315         /* sync semi rtc */
7316         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7317                0x80000000);
7318         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7319                0x80000000);
7320
7321         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7322         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7323         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7324
7325         if (!CHIP_IS_E1x(bp)) {
7326                 if (IS_MF_AFEX(bp)) {
7327                         /* configure that VNTag and VLAN headers must be
7328                          * sent in afex mode
7329                          */
7330                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7331                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7332                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7333                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7334                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7335                 } else {
7336                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7337                                bp->path_has_ovlan ? 7 : 6);
7338                 }
7339         }
7340
7341         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7342
7343         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7344
7345         if (CNIC_SUPPORT(bp)) {
7346                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7347                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7348                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7349                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7350                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7351                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7352                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7353                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7354                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7355                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7356         }
7357         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7358
7359         if (sizeof(union cdu_context) != 1024)
7360                 /* we currently assume that a context is 1024 bytes */
7361                 dev_alert(&bp->pdev->dev,
7362                           "please adjust the size of cdu_context(%ld)\n",
7363                           (long)sizeof(union cdu_context));
7364
7365         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7366         val = (4 << 24) + (0 << 12) + 1024;
7367         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7368
7369         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7370         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7371         /* enable context validation interrupt from CFC */
7372         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7373
7374         /* set the thresholds to prevent CFC/CDU race */
7375         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7376
7377         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7378
7379         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7380                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7381
7382         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7383         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7384
7385         /* Reset PCIE errors for debug */
7386         REG_WR(bp, 0x2814, 0xffffffff);
7387         REG_WR(bp, 0x3820, 0xffffffff);
7388
7389         if (!CHIP_IS_E1x(bp)) {
7390                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7391                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7392                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7393                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7394                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7395                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7396                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7397                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7398                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7399                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7400                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7401         }
7402
7403         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7404         if (!CHIP_IS_E1(bp)) {
7405                 /* in E3 this done in per-port section */
7406                 if (!CHIP_IS_E3(bp))
7407                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7408         }
7409         if (CHIP_IS_E1H(bp))
7410                 /* not applicable for E2 (and above ...) */
7411                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7412
7413         if (CHIP_REV_IS_SLOW(bp))
7414                 msleep(200);
7415
7416         /* finish CFC init */
7417         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7418         if (val != 1) {
7419                 BNX2X_ERR("CFC LL_INIT failed\n");
7420                 return -EBUSY;
7421         }
7422         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7423         if (val != 1) {
7424                 BNX2X_ERR("CFC AC_INIT failed\n");
7425                 return -EBUSY;
7426         }
7427         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7428         if (val != 1) {
7429                 BNX2X_ERR("CFC CAM_INIT failed\n");
7430                 return -EBUSY;
7431         }
7432         REG_WR(bp, CFC_REG_DEBUG0, 0);
7433
7434         if (CHIP_IS_E1(bp)) {
7435                 /* read NIG statistic
7436                    to see if this is our first up since powerup */
7437                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7438                 val = *bnx2x_sp(bp, wb_data[0]);
7439
7440                 /* do internal memory self test */
7441                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7442                         BNX2X_ERR("internal mem self test failed\n");
7443                         return -EBUSY;
7444                 }
7445         }
7446
7447         bnx2x_setup_fan_failure_detection(bp);
7448
7449         /* clear PXP2 attentions */
7450         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7451
7452         bnx2x_enable_blocks_attention(bp);
7453         bnx2x_enable_blocks_parity(bp);
7454
7455         if (!BP_NOMCP(bp)) {
7456                 if (CHIP_IS_E1x(bp))
7457                         bnx2x__common_init_phy(bp);
7458         } else
7459                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7460
7461         if (SHMEM2_HAS(bp, netproc_fw_ver))
7462                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7463
7464         return 0;
7465 }
7466
7467 /**
7468  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7469  *
7470  * @bp:         driver handle
7471  */
7472 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7473 {
7474         int rc = bnx2x_init_hw_common(bp);
7475
7476         if (rc)
7477                 return rc;
7478
7479         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7480         if (!BP_NOMCP(bp))
7481                 bnx2x__common_init_phy(bp);
7482
7483         return 0;
7484 }
7485
7486 static int bnx2x_init_hw_port(struct bnx2x *bp)
7487 {
7488         int port = BP_PORT(bp);
7489         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7490         u32 low, high;
7491         u32 val, reg;
7492
7493         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7494
7495         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7496
7497         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7498         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7499         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7500
7501         /* Timers bug workaround: disables the pf_master bit in pglue at
7502          * common phase, we need to enable it here before any dmae access are
7503          * attempted. Therefore we manually added the enable-master to the
7504          * port phase (it also happens in the function phase)
7505          */
7506         if (!CHIP_IS_E1x(bp))
7507                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7508
7509         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7510         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7511         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7512         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7513
7514         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7515         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7516         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7517         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7518
7519         /* QM cid (connection) count */
7520         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7521
7522         if (CNIC_SUPPORT(bp)) {
7523                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7524                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7525                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7526         }
7527
7528         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7529
7530         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7531
7532         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7533
7534                 if (IS_MF(bp))
7535                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7536                 else if (bp->dev->mtu > 4096) {
7537                         if (bp->flags & ONE_PORT_FLAG)
7538                                 low = 160;
7539                         else {
7540                                 val = bp->dev->mtu;
7541                                 /* (24*1024 + val*4)/256 */
7542                                 low = 96 + (val/64) +
7543                                                 ((val % 64) ? 1 : 0);
7544                         }
7545                 } else
7546                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7547                 high = low + 56;        /* 14*1024/256 */
7548                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7549                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7550         }
7551
7552         if (CHIP_MODE_IS_4_PORT(bp))
7553                 REG_WR(bp, (BP_PORT(bp) ?
7554                             BRB1_REG_MAC_GUARANTIED_1 :
7555                             BRB1_REG_MAC_GUARANTIED_0), 40);
7556
7557         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7558         if (CHIP_IS_E3B0(bp)) {
7559                 if (IS_MF_AFEX(bp)) {
7560                         /* configure headers for AFEX mode */
7561                         REG_WR(bp, BP_PORT(bp) ?
7562                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7563                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7564                         REG_WR(bp, BP_PORT(bp) ?
7565                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7566                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7567                         REG_WR(bp, BP_PORT(bp) ?
7568                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7569                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7570                 } else {
7571                         /* Ovlan exists only if we are in multi-function +
7572                          * switch-dependent mode, in switch-independent there
7573                          * is no ovlan headers
7574                          */
7575                         REG_WR(bp, BP_PORT(bp) ?
7576                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7577                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7578                                (bp->path_has_ovlan ? 7 : 6));
7579                 }
7580         }
7581
7582         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7583         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7584         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7585         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7586
7587         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7588         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7589         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7590         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7591
7592         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7593         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7594
7595         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7596
7597         if (CHIP_IS_E1x(bp)) {
7598                 /* configure PBF to work without PAUSE mtu 9000 */
7599                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7600
7601                 /* update threshold */
7602                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7603                 /* update init credit */
7604                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7605
7606                 /* probe changes */
7607                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7608                 udelay(50);
7609                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7610         }
7611
7612         if (CNIC_SUPPORT(bp))
7613                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7614
7615         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7616         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7617
7618         if (CHIP_IS_E1(bp)) {
7619                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7620                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7621         }
7622         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7623
7624         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7625
7626         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7627         /* init aeu_mask_attn_func_0/1:
7628          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7629          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7630          *             bits 4-7 are used for "per vn group attention" */
7631         val = IS_MF(bp) ? 0xF7 : 0x7;
7632         /* Enable DCBX attention for all but E1 */
7633         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7634         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7635
7636         /* SCPAD_PARITY should NOT trigger close the gates */
7637         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7638         REG_WR(bp, reg,
7639                REG_RD(bp, reg) &
7640                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7641
7642         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7643         REG_WR(bp, reg,
7644                REG_RD(bp, reg) &
7645                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7646
7647         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7648
7649         if (!CHIP_IS_E1x(bp)) {
7650                 /* Bit-map indicating which L2 hdrs may appear after the
7651                  * basic Ethernet header
7652                  */
7653                 if (IS_MF_AFEX(bp))
7654                         REG_WR(bp, BP_PORT(bp) ?
7655                                NIG_REG_P1_HDRS_AFTER_BASIC :
7656                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7657                 else
7658                         REG_WR(bp, BP_PORT(bp) ?
7659                                NIG_REG_P1_HDRS_AFTER_BASIC :
7660                                NIG_REG_P0_HDRS_AFTER_BASIC,
7661                                IS_MF_SD(bp) ? 7 : 6);
7662
7663                 if (CHIP_IS_E3(bp))
7664                         REG_WR(bp, BP_PORT(bp) ?
7665                                    NIG_REG_LLH1_MF_MODE :
7666                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7667         }
7668         if (!CHIP_IS_E3(bp))
7669                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7670
7671         if (!CHIP_IS_E1(bp)) {
7672                 /* 0x2 disable mf_ov, 0x1 enable */
7673                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7674                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7675
7676                 if (!CHIP_IS_E1x(bp)) {
7677                         val = 0;
7678                         switch (bp->mf_mode) {
7679                         case MULTI_FUNCTION_SD:
7680                                 val = 1;
7681                                 break;
7682                         case MULTI_FUNCTION_SI:
7683                         case MULTI_FUNCTION_AFEX:
7684                                 val = 2;
7685                                 break;
7686                         }
7687
7688                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7689                                                   NIG_REG_LLH0_CLS_TYPE), val);
7690                 }
7691                 {
7692                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7693                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7694                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7695                 }
7696         }
7697
7698         /* If SPIO5 is set to generate interrupts, enable it for this port */
7699         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7700         if (val & MISC_SPIO_SPIO5) {
7701                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7702                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7703                 val = REG_RD(bp, reg_addr);
7704                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7705                 REG_WR(bp, reg_addr, val);
7706         }
7707
7708         return 0;
7709 }
7710
7711 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7712 {
7713         int reg;
7714         u32 wb_write[2];
7715
7716         if (CHIP_IS_E1(bp))
7717                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7718         else
7719                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7720
7721         wb_write[0] = ONCHIP_ADDR1(addr);
7722         wb_write[1] = ONCHIP_ADDR2(addr);
7723         REG_WR_DMAE(bp, reg, wb_write, 2);
7724 }
7725
7726 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7727 {
7728         u32 data, ctl, cnt = 100;
7729         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7730         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7731         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7732         u32 sb_bit =  1 << (idu_sb_id%32);
7733         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7734         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7735
7736         /* Not supported in BC mode */
7737         if (CHIP_INT_MODE_IS_BC(bp))
7738                 return;
7739
7740         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7741                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7742                 IGU_REGULAR_CLEANUP_SET                         |
7743                 IGU_REGULAR_BCLEANUP;
7744
7745         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7746               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7747               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7748
7749         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7750                          data, igu_addr_data);
7751         REG_WR(bp, igu_addr_data, data);
7752         mmiowb();
7753         barrier();
7754         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7755                           ctl, igu_addr_ctl);
7756         REG_WR(bp, igu_addr_ctl, ctl);
7757         mmiowb();
7758         barrier();
7759
7760         /* wait for clean up to finish */
7761         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7762                 msleep(20);
7763
7764         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7765                 DP(NETIF_MSG_HW,
7766                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7767                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7768         }
7769 }
7770
7771 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7772 {
7773         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7774 }
7775
7776 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7777 {
7778         u32 i, base = FUNC_ILT_BASE(func);
7779         for (i = base; i < base + ILT_PER_FUNC; i++)
7780                 bnx2x_ilt_wr(bp, i, 0);
7781 }
7782
7783 static void bnx2x_init_searcher(struct bnx2x *bp)
7784 {
7785         int port = BP_PORT(bp);
7786         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7787         /* T1 hash bits value determines the T1 number of entries */
7788         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7789 }
7790
7791 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7792 {
7793         int rc;
7794         struct bnx2x_func_state_params func_params = {NULL};
7795         struct bnx2x_func_switch_update_params *switch_update_params =
7796                 &func_params.params.switch_update;
7797
7798         /* Prepare parameters for function state transitions */
7799         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7800         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7801
7802         func_params.f_obj = &bp->func_obj;
7803         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7804
7805         /* Function parameters */
7806         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7807                   &switch_update_params->changes);
7808         if (suspend)
7809                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7810                           &switch_update_params->changes);
7811
7812         rc = bnx2x_func_state_change(bp, &func_params);
7813
7814         return rc;
7815 }
7816
7817 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7818 {
7819         int rc, i, port = BP_PORT(bp);
7820         int vlan_en = 0, mac_en[NUM_MACS];
7821
7822         /* Close input from network */
7823         if (bp->mf_mode == SINGLE_FUNCTION) {
7824                 bnx2x_set_rx_filter(&bp->link_params, 0);
7825         } else {
7826                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7827                                    NIG_REG_LLH0_FUNC_EN);
7828                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7829                           NIG_REG_LLH0_FUNC_EN, 0);
7830                 for (i = 0; i < NUM_MACS; i++) {
7831                         mac_en[i] = REG_RD(bp, port ?
7832                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7833                                               4 * i) :
7834                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7835                                               4 * i));
7836                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7837                                               4 * i) :
7838                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7839                 }
7840         }
7841
7842         /* Close BMC to host */
7843         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7844                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7845
7846         /* Suspend Tx switching to the PF. Completion of this ramrod
7847          * further guarantees that all the packets of that PF / child
7848          * VFs in BRB were processed by the Parser, so it is safe to
7849          * change the NIC_MODE register.
7850          */
7851         rc = bnx2x_func_switch_update(bp, 1);
7852         if (rc) {
7853                 BNX2X_ERR("Can't suspend tx-switching!\n");
7854                 return rc;
7855         }
7856
7857         /* Change NIC_MODE register */
7858         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7859
7860         /* Open input from network */
7861         if (bp->mf_mode == SINGLE_FUNCTION) {
7862                 bnx2x_set_rx_filter(&bp->link_params, 1);
7863         } else {
7864                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7865                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7866                 for (i = 0; i < NUM_MACS; i++) {
7867                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7868                                               4 * i) :
7869                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7870                                   mac_en[i]);
7871                 }
7872         }
7873
7874         /* Enable BMC to host */
7875         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7876                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7877
7878         /* Resume Tx switching to the PF */
7879         rc = bnx2x_func_switch_update(bp, 0);
7880         if (rc) {
7881                 BNX2X_ERR("Can't resume tx-switching!\n");
7882                 return rc;
7883         }
7884
7885         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7886         return 0;
7887 }
7888
7889 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7890 {
7891         int rc;
7892
7893         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7894
7895         if (CONFIGURE_NIC_MODE(bp)) {
7896                 /* Configure searcher as part of function hw init */
7897                 bnx2x_init_searcher(bp);
7898
7899                 /* Reset NIC mode */
7900                 rc = bnx2x_reset_nic_mode(bp);
7901                 if (rc)
7902                         BNX2X_ERR("Can't change NIC mode!\n");
7903                 return rc;
7904         }
7905
7906         return 0;
7907 }
7908
7909 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7910  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7911  * the addresses of the transaction, resulting in was-error bit set in the pci
7912  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7913  * to clear the interrupt which detected this from the pglueb and the was done
7914  * bit
7915  */
7916 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7917 {
7918         if (!CHIP_IS_E1x(bp))
7919                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7920                        1 << BP_ABS_FUNC(bp));
7921 }
7922
7923 static int bnx2x_init_hw_func(struct bnx2x *bp)
7924 {
7925         int port = BP_PORT(bp);
7926         int func = BP_FUNC(bp);
7927         int init_phase = PHASE_PF0 + func;
7928         struct bnx2x_ilt *ilt = BP_ILT(bp);
7929         u16 cdu_ilt_start;
7930         u32 addr, val;
7931         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7932         int i, main_mem_width, rc;
7933
7934         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7935
7936         /* FLR cleanup - hmmm */
7937         if (!CHIP_IS_E1x(bp)) {
7938                 rc = bnx2x_pf_flr_clnup(bp);
7939                 if (rc) {
7940                         bnx2x_fw_dump(bp);
7941                         return rc;
7942                 }
7943         }
7944
7945         /* set MSI reconfigure capability */
7946         if (bp->common.int_block == INT_BLOCK_HC) {
7947                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7948                 val = REG_RD(bp, addr);
7949                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7950                 REG_WR(bp, addr, val);
7951         }
7952
7953         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7954         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7955
7956         ilt = BP_ILT(bp);
7957         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7958
7959         if (IS_SRIOV(bp))
7960                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7961         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7962
7963         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7964          * those of the VFs, so start line should be reset
7965          */
7966         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7967         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7968                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7969                 ilt->lines[cdu_ilt_start + i].page_mapping =
7970                         bp->context[i].cxt_mapping;
7971                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7972         }
7973
7974         bnx2x_ilt_init_op(bp, INITOP_SET);
7975
7976         if (!CONFIGURE_NIC_MODE(bp)) {
7977                 bnx2x_init_searcher(bp);
7978                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7979                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7980         } else {
7981                 /* Set NIC mode */
7982                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7983                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7984         }
7985
7986         if (!CHIP_IS_E1x(bp)) {
7987                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7988
7989                 /* Turn on a single ISR mode in IGU if driver is going to use
7990                  * INT#x or MSI
7991                  */
7992                 if (!(bp->flags & USING_MSIX_FLAG))
7993                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7994                 /*
7995                  * Timers workaround bug: function init part.
7996                  * Need to wait 20msec after initializing ILT,
7997                  * needed to make sure there are no requests in
7998                  * one of the PXP internal queues with "old" ILT addresses
7999                  */
8000                 msleep(20);
8001                 /*
8002                  * Master enable - Due to WB DMAE writes performed before this
8003                  * register is re-initialized as part of the regular function
8004                  * init
8005                  */
8006                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8007                 /* Enable the function in IGU */
8008                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8009         }
8010
8011         bp->dmae_ready = 1;
8012
8013         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8014
8015         bnx2x_clean_pglue_errors(bp);
8016
8017         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8018         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8019         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8020         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8021         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8022         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8023         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8024         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8025         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8026         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8027         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8028         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8029         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8030
8031         if (!CHIP_IS_E1x(bp))
8032                 REG_WR(bp, QM_REG_PF_EN, 1);
8033
8034         if (!CHIP_IS_E1x(bp)) {
8035                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8036                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8037                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8038                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8039         }
8040         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8041
8042         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8043         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8044         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8045
8046         bnx2x_iov_init_dq(bp);
8047
8048         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8049         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8050         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8051         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8052         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8053         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8054         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8055         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8056         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8057         if (!CHIP_IS_E1x(bp))
8058                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8059
8060         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8061
8062         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8063
8064         if (!CHIP_IS_E1x(bp))
8065                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8066
8067         if (IS_MF(bp)) {
8068                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8069                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8070                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8071                                bp->mf_ov);
8072                 }
8073         }
8074
8075         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8076
8077         /* HC init per function */
8078         if (bp->common.int_block == INT_BLOCK_HC) {
8079                 if (CHIP_IS_E1H(bp)) {
8080                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8081
8082                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8083                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8084                 }
8085                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8086
8087         } else {
8088                 int num_segs, sb_idx, prod_offset;
8089
8090                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8091
8092                 if (!CHIP_IS_E1x(bp)) {
8093                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8094                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8095                 }
8096
8097                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8098
8099                 if (!CHIP_IS_E1x(bp)) {
8100                         int dsb_idx = 0;
8101                         /**
8102                          * Producer memory:
8103                          * E2 mode: address 0-135 match to the mapping memory;
8104                          * 136 - PF0 default prod; 137 - PF1 default prod;
8105                          * 138 - PF2 default prod; 139 - PF3 default prod;
8106                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8107                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8108                          * 144-147 reserved.
8109                          *
8110                          * E1.5 mode - In backward compatible mode;
8111                          * for non default SB; each even line in the memory
8112                          * holds the U producer and each odd line hold
8113                          * the C producer. The first 128 producers are for
8114                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8115                          * producers are for the DSB for each PF.
8116                          * Each PF has five segments: (the order inside each
8117                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8118                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8119                          * 144-147 attn prods;
8120                          */
8121                         /* non-default-status-blocks */
8122                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8123                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8124                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8125                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8126                                         num_segs;
8127
8128                                 for (i = 0; i < num_segs; i++) {
8129                                         addr = IGU_REG_PROD_CONS_MEMORY +
8130                                                         (prod_offset + i) * 4;
8131                                         REG_WR(bp, addr, 0);
8132                                 }
8133                                 /* send consumer update with value 0 */
8134                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8135                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8136                                 bnx2x_igu_clear_sb(bp,
8137                                                    bp->igu_base_sb + sb_idx);
8138                         }
8139
8140                         /* default-status-blocks */
8141                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8142                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8143
8144                         if (CHIP_MODE_IS_4_PORT(bp))
8145                                 dsb_idx = BP_FUNC(bp);
8146                         else
8147                                 dsb_idx = BP_VN(bp);
8148
8149                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8150                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8151                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8152
8153                         /*
8154                          * igu prods come in chunks of E1HVN_MAX (4) -
8155                          * does not matters what is the current chip mode
8156                          */
8157                         for (i = 0; i < (num_segs * E1HVN_MAX);
8158                              i += E1HVN_MAX) {
8159                                 addr = IGU_REG_PROD_CONS_MEMORY +
8160                                                         (prod_offset + i)*4;
8161                                 REG_WR(bp, addr, 0);
8162                         }
8163                         /* send consumer update with 0 */
8164                         if (CHIP_INT_MODE_IS_BC(bp)) {
8165                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8166                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8167                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8168                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8169                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8170                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8171                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8172                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8173                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8175                         } else {
8176                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8177                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8178                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8179                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8180                         }
8181                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8182
8183                         /* !!! These should become driver const once
8184                            rf-tool supports split-68 const */
8185                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8186                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8187                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8188                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8189                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8190                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8191                 }
8192         }
8193
8194         /* Reset PCIE errors for debug */
8195         REG_WR(bp, 0x2114, 0xffffffff);
8196         REG_WR(bp, 0x2120, 0xffffffff);
8197
8198         if (CHIP_IS_E1x(bp)) {
8199                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8200                 main_mem_base = HC_REG_MAIN_MEMORY +
8201                                 BP_PORT(bp) * (main_mem_size * 4);
8202                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8203                 main_mem_width = 8;
8204
8205                 val = REG_RD(bp, main_mem_prty_clr);
8206                 if (val)
8207                         DP(NETIF_MSG_HW,
8208                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8209                            val);
8210
8211                 /* Clear "false" parity errors in MSI-X table */
8212                 for (i = main_mem_base;
8213                      i < main_mem_base + main_mem_size * 4;
8214                      i += main_mem_width) {
8215                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8216                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8217                                          i, main_mem_width / 4);
8218                 }
8219                 /* Clear HC parity attention */
8220                 REG_RD(bp, main_mem_prty_clr);
8221         }
8222
8223 #ifdef BNX2X_STOP_ON_ERROR
8224         /* Enable STORMs SP logging */
8225         REG_WR8(bp, BAR_USTRORM_INTMEM +
8226                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8227         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8228                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8229         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8230                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8231         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8232                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8233 #endif
8234
8235         bnx2x_phy_probe(&bp->link_params);
8236
8237         return 0;
8238 }
8239
8240 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8241 {
8242         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8243
8244         if (!CHIP_IS_E1x(bp))
8245                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8246                                sizeof(struct host_hc_status_block_e2));
8247         else
8248                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8249                                sizeof(struct host_hc_status_block_e1x));
8250
8251         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8252 }
8253
8254 void bnx2x_free_mem(struct bnx2x *bp)
8255 {
8256         int i;
8257
8258         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8259                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8260
8261         if (IS_VF(bp))
8262                 return;
8263
8264         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8265                        sizeof(struct host_sp_status_block));
8266
8267         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8268                        sizeof(struct bnx2x_slowpath));
8269
8270         for (i = 0; i < L2_ILT_LINES(bp); i++)
8271                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8272                                bp->context[i].size);
8273         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8274
8275         BNX2X_FREE(bp->ilt->lines);
8276
8277         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8278
8279         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8280                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8281
8282         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8283
8284         bnx2x_iov_free_mem(bp);
8285 }
8286
8287 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8288 {
8289         if (!CHIP_IS_E1x(bp)) {
8290                 /* size = the status block + ramrod buffers */
8291                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8292                                                     sizeof(struct host_hc_status_block_e2));
8293                 if (!bp->cnic_sb.e2_sb)
8294                         goto alloc_mem_err;
8295         } else {
8296                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8297                                                      sizeof(struct host_hc_status_block_e1x));
8298                 if (!bp->cnic_sb.e1x_sb)
8299                         goto alloc_mem_err;
8300         }
8301
8302         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8303                 /* allocate searcher T2 table, as it wasn't allocated before */
8304                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8305                 if (!bp->t2)
8306                         goto alloc_mem_err;
8307         }
8308
8309         /* write address to which L5 should insert its values */
8310         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8311                 &bp->slowpath->drv_info_to_mcp;
8312
8313         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8314                 goto alloc_mem_err;
8315
8316         return 0;
8317
8318 alloc_mem_err:
8319         bnx2x_free_mem_cnic(bp);
8320         BNX2X_ERR("Can't allocate memory\n");
8321         return -ENOMEM;
8322 }
8323
8324 int bnx2x_alloc_mem(struct bnx2x *bp)
8325 {
8326         int i, allocated, context_size;
8327
8328         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8329                 /* allocate searcher T2 table */
8330                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8331                 if (!bp->t2)
8332                         goto alloc_mem_err;
8333         }
8334
8335         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8336                                              sizeof(struct host_sp_status_block));
8337         if (!bp->def_status_blk)
8338                 goto alloc_mem_err;
8339
8340         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8341                                        sizeof(struct bnx2x_slowpath));
8342         if (!bp->slowpath)
8343                 goto alloc_mem_err;
8344
8345         /* Allocate memory for CDU context:
8346          * This memory is allocated separately and not in the generic ILT
8347          * functions because CDU differs in few aspects:
8348          * 1. There are multiple entities allocating memory for context -
8349          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8350          * its own ILT lines.
8351          * 2. Since CDU page-size is not a single 4KB page (which is the case
8352          * for the other ILT clients), to be efficient we want to support
8353          * allocation of sub-page-size in the last entry.
8354          * 3. Context pointers are used by the driver to pass to FW / update
8355          * the context (for the other ILT clients the pointers are used just to
8356          * free the memory during unload).
8357          */
8358         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8359
8360         for (i = 0, allocated = 0; allocated < context_size; i++) {
8361                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8362                                           (context_size - allocated));
8363                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8364                                                       bp->context[i].size);
8365                 if (!bp->context[i].vcxt)
8366                         goto alloc_mem_err;
8367                 allocated += bp->context[i].size;
8368         }
8369         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8370                                  GFP_KERNEL);
8371         if (!bp->ilt->lines)
8372                 goto alloc_mem_err;
8373
8374         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8375                 goto alloc_mem_err;
8376
8377         if (bnx2x_iov_alloc_mem(bp))
8378                 goto alloc_mem_err;
8379
8380         /* Slow path ring */
8381         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8382         if (!bp->spq)
8383                 goto alloc_mem_err;
8384
8385         /* EQ */
8386         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8387                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8388         if (!bp->eq_ring)
8389                 goto alloc_mem_err;
8390
8391         return 0;
8392
8393 alloc_mem_err:
8394         bnx2x_free_mem(bp);
8395         BNX2X_ERR("Can't allocate memory\n");
8396         return -ENOMEM;
8397 }
8398
8399 /*
8400  * Init service functions
8401  */
8402
8403 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8404                       struct bnx2x_vlan_mac_obj *obj, bool set,
8405                       int mac_type, unsigned long *ramrod_flags)
8406 {
8407         int rc;
8408         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8409
8410         memset(&ramrod_param, 0, sizeof(ramrod_param));
8411
8412         /* Fill general parameters */
8413         ramrod_param.vlan_mac_obj = obj;
8414         ramrod_param.ramrod_flags = *ramrod_flags;
8415
8416         /* Fill a user request section if needed */
8417         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8418                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8419
8420                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8421
8422                 /* Set the command: ADD or DEL */
8423                 if (set)
8424                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8425                 else
8426                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8427         }
8428
8429         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8430
8431         if (rc == -EEXIST) {
8432                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8433                 /* do not treat adding same MAC as error */
8434                 rc = 0;
8435         } else if (rc < 0)
8436                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8437
8438         return rc;
8439 }
8440
8441 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8442                        struct bnx2x_vlan_mac_obj *obj, bool set,
8443                        unsigned long *ramrod_flags)
8444 {
8445         int rc;
8446         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8447
8448         memset(&ramrod_param, 0, sizeof(ramrod_param));
8449
8450         /* Fill general parameters */
8451         ramrod_param.vlan_mac_obj = obj;
8452         ramrod_param.ramrod_flags = *ramrod_flags;
8453
8454         /* Fill a user request section if needed */
8455         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8456                 ramrod_param.user_req.u.vlan.vlan = vlan;
8457                 /* Set the command: ADD or DEL */
8458                 if (set)
8459                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8460                 else
8461                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8462         }
8463
8464         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8465
8466         if (rc == -EEXIST) {
8467                 /* Do not treat adding same vlan as error. */
8468                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8469                 rc = 0;
8470         } else if (rc < 0) {
8471                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8472         }
8473
8474         return rc;
8475 }
8476
8477 int bnx2x_del_all_macs(struct bnx2x *bp,
8478                        struct bnx2x_vlan_mac_obj *mac_obj,
8479                        int mac_type, bool wait_for_comp)
8480 {
8481         int rc;
8482         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8483
8484         /* Wait for completion of requested */
8485         if (wait_for_comp)
8486                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8487
8488         /* Set the mac type of addresses we want to clear */
8489         __set_bit(mac_type, &vlan_mac_flags);
8490
8491         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8492         if (rc < 0)
8493                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8494
8495         return rc;
8496 }
8497
8498 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8499 {
8500         if (IS_PF(bp)) {
8501                 unsigned long ramrod_flags = 0;
8502
8503                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8504                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8505                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8506                                          &bp->sp_objs->mac_obj, set,
8507                                          BNX2X_ETH_MAC, &ramrod_flags);
8508         } else { /* vf */
8509                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8510                                              bp->fp->index, set);
8511         }
8512 }
8513
8514 int bnx2x_setup_leading(struct bnx2x *bp)
8515 {
8516         if (IS_PF(bp))
8517                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8518         else /* VF */
8519                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8520 }
8521
8522 /**
8523  * bnx2x_set_int_mode - configure interrupt mode
8524  *
8525  * @bp:         driver handle
8526  *
8527  * In case of MSI-X it will also try to enable MSI-X.
8528  */
8529 int bnx2x_set_int_mode(struct bnx2x *bp)
8530 {
8531         int rc = 0;
8532
8533         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8534                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8535                 return -EINVAL;
8536         }
8537
8538         switch (int_mode) {
8539         case BNX2X_INT_MODE_MSIX:
8540                 /* attempt to enable msix */
8541                 rc = bnx2x_enable_msix(bp);
8542
8543                 /* msix attained */
8544                 if (!rc)
8545                         return 0;
8546
8547                 /* vfs use only msix */
8548                 if (rc && IS_VF(bp))
8549                         return rc;
8550
8551                 /* failed to enable multiple MSI-X */
8552                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8553                                bp->num_queues,
8554                                1 + bp->num_cnic_queues);
8555
8556                 /* falling through... */
8557         case BNX2X_INT_MODE_MSI:
8558                 bnx2x_enable_msi(bp);
8559
8560                 /* falling through... */
8561         case BNX2X_INT_MODE_INTX:
8562                 bp->num_ethernet_queues = 1;
8563                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8564                 BNX2X_DEV_INFO("set number of queues to 1\n");
8565                 break;
8566         default:
8567                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8568                 return -EINVAL;
8569         }
8570         return 0;
8571 }
8572
8573 /* must be called prior to any HW initializations */
8574 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8575 {
8576         if (IS_SRIOV(bp))
8577                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8578         return L2_ILT_LINES(bp);
8579 }
8580
8581 void bnx2x_ilt_set_info(struct bnx2x *bp)
8582 {
8583         struct ilt_client_info *ilt_client;
8584         struct bnx2x_ilt *ilt = BP_ILT(bp);
8585         u16 line = 0;
8586
8587         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8588         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8589
8590         /* CDU */
8591         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8592         ilt_client->client_num = ILT_CLIENT_CDU;
8593         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8594         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8595         ilt_client->start = line;
8596         line += bnx2x_cid_ilt_lines(bp);
8597
8598         if (CNIC_SUPPORT(bp))
8599                 line += CNIC_ILT_LINES;
8600         ilt_client->end = line - 1;
8601
8602         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8603            ilt_client->start,
8604            ilt_client->end,
8605            ilt_client->page_size,
8606            ilt_client->flags,
8607            ilog2(ilt_client->page_size >> 12));
8608
8609         /* QM */
8610         if (QM_INIT(bp->qm_cid_count)) {
8611                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8612                 ilt_client->client_num = ILT_CLIENT_QM;
8613                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8614                 ilt_client->flags = 0;
8615                 ilt_client->start = line;
8616
8617                 /* 4 bytes for each cid */
8618                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8619                                                          QM_ILT_PAGE_SZ);
8620
8621                 ilt_client->end = line - 1;
8622
8623                 DP(NETIF_MSG_IFUP,
8624                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8625                    ilt_client->start,
8626                    ilt_client->end,
8627                    ilt_client->page_size,
8628                    ilt_client->flags,
8629                    ilog2(ilt_client->page_size >> 12));
8630         }
8631
8632         if (CNIC_SUPPORT(bp)) {
8633                 /* SRC */
8634                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8635                 ilt_client->client_num = ILT_CLIENT_SRC;
8636                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8637                 ilt_client->flags = 0;
8638                 ilt_client->start = line;
8639                 line += SRC_ILT_LINES;
8640                 ilt_client->end = line - 1;
8641
8642                 DP(NETIF_MSG_IFUP,
8643                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8644                    ilt_client->start,
8645                    ilt_client->end,
8646                    ilt_client->page_size,
8647                    ilt_client->flags,
8648                    ilog2(ilt_client->page_size >> 12));
8649
8650                 /* TM */
8651                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8652                 ilt_client->client_num = ILT_CLIENT_TM;
8653                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8654                 ilt_client->flags = 0;
8655                 ilt_client->start = line;
8656                 line += TM_ILT_LINES;
8657                 ilt_client->end = line - 1;
8658
8659                 DP(NETIF_MSG_IFUP,
8660                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8661                    ilt_client->start,
8662                    ilt_client->end,
8663                    ilt_client->page_size,
8664                    ilt_client->flags,
8665                    ilog2(ilt_client->page_size >> 12));
8666         }
8667
8668         BUG_ON(line > ILT_MAX_LINES);
8669 }
8670
8671 /**
8672  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8673  *
8674  * @bp:                 driver handle
8675  * @fp:                 pointer to fastpath
8676  * @init_params:        pointer to parameters structure
8677  *
8678  * parameters configured:
8679  *      - HC configuration
8680  *      - Queue's CDU context
8681  */
8682 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8683         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8684 {
8685         u8 cos;
8686         int cxt_index, cxt_offset;
8687
8688         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8689         if (!IS_FCOE_FP(fp)) {
8690                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8691                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8692
8693                 /* If HC is supported, enable host coalescing in the transition
8694                  * to INIT state.
8695                  */
8696                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8697                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8698
8699                 /* HC rate */
8700                 init_params->rx.hc_rate = bp->rx_ticks ?
8701                         (1000000 / bp->rx_ticks) : 0;
8702                 init_params->tx.hc_rate = bp->tx_ticks ?
8703                         (1000000 / bp->tx_ticks) : 0;
8704
8705                 /* FW SB ID */
8706                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8707                         fp->fw_sb_id;
8708
8709                 /*
8710                  * CQ index among the SB indices: FCoE clients uses the default
8711                  * SB, therefore it's different.
8712                  */
8713                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8714                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8715         }
8716
8717         /* set maximum number of COSs supported by this queue */
8718         init_params->max_cos = fp->max_cos;
8719
8720         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8721             fp->index, init_params->max_cos);
8722
8723         /* set the context pointers queue object */
8724         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8725                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8726                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8727                                 ILT_PAGE_CIDS);
8728                 init_params->cxts[cos] =
8729                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8730         }
8731 }
8732
8733 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8734                         struct bnx2x_queue_state_params *q_params,
8735                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8736                         int tx_index, bool leading)
8737 {
8738         memset(tx_only_params, 0, sizeof(*tx_only_params));
8739
8740         /* Set the command */
8741         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8742
8743         /* Set tx-only QUEUE flags: don't zero statistics */
8744         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8745
8746         /* choose the index of the cid to send the slow path on */
8747         tx_only_params->cid_index = tx_index;
8748
8749         /* Set general TX_ONLY_SETUP parameters */
8750         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8751
8752         /* Set Tx TX_ONLY_SETUP parameters */
8753         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8754
8755         DP(NETIF_MSG_IFUP,
8756            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8757            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8758            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8759            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8760
8761         /* send the ramrod */
8762         return bnx2x_queue_state_change(bp, q_params);
8763 }
8764
8765 /**
8766  * bnx2x_setup_queue - setup queue
8767  *
8768  * @bp:         driver handle
8769  * @fp:         pointer to fastpath
8770  * @leading:    is leading
8771  *
8772  * This function performs 2 steps in a Queue state machine
8773  *      actually: 1) RESET->INIT 2) INIT->SETUP
8774  */
8775
8776 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8777                        bool leading)
8778 {
8779         struct bnx2x_queue_state_params q_params = {NULL};
8780         struct bnx2x_queue_setup_params *setup_params =
8781                                                 &q_params.params.setup;
8782         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8783                                                 &q_params.params.tx_only;
8784         int rc;
8785         u8 tx_index;
8786
8787         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8788
8789         /* reset IGU state skip FCoE L2 queue */
8790         if (!IS_FCOE_FP(fp))
8791                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8792                              IGU_INT_ENABLE, 0);
8793
8794         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8795         /* We want to wait for completion in this context */
8796         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8797
8798         /* Prepare the INIT parameters */
8799         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8800
8801         /* Set the command */
8802         q_params.cmd = BNX2X_Q_CMD_INIT;
8803
8804         /* Change the state to INIT */
8805         rc = bnx2x_queue_state_change(bp, &q_params);
8806         if (rc) {
8807                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8808                 return rc;
8809         }
8810
8811         DP(NETIF_MSG_IFUP, "init complete\n");
8812
8813         /* Now move the Queue to the SETUP state... */
8814         memset(setup_params, 0, sizeof(*setup_params));
8815
8816         /* Set QUEUE flags */
8817         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8818
8819         /* Set general SETUP parameters */
8820         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8821                                 FIRST_TX_COS_INDEX);
8822
8823         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8824                             &setup_params->rxq_params);
8825
8826         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8827                            FIRST_TX_COS_INDEX);
8828
8829         /* Set the command */
8830         q_params.cmd = BNX2X_Q_CMD_SETUP;
8831
8832         if (IS_FCOE_FP(fp))
8833                 bp->fcoe_init = true;
8834
8835         /* Change the state to SETUP */
8836         rc = bnx2x_queue_state_change(bp, &q_params);
8837         if (rc) {
8838                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8839                 return rc;
8840         }
8841
8842         /* loop through the relevant tx-only indices */
8843         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8844               tx_index < fp->max_cos;
8845               tx_index++) {
8846
8847                 /* prepare and send tx-only ramrod*/
8848                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8849                                           tx_only_params, tx_index, leading);
8850                 if (rc) {
8851                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8852                                   fp->index, tx_index);
8853                         return rc;
8854                 }
8855         }
8856
8857         return rc;
8858 }
8859
8860 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8861 {
8862         struct bnx2x_fastpath *fp = &bp->fp[index];
8863         struct bnx2x_fp_txdata *txdata;
8864         struct bnx2x_queue_state_params q_params = {NULL};
8865         int rc, tx_index;
8866
8867         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8868
8869         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8870         /* We want to wait for completion in this context */
8871         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8872
8873         /* close tx-only connections */
8874         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8875              tx_index < fp->max_cos;
8876              tx_index++){
8877
8878                 /* ascertain this is a normal queue*/
8879                 txdata = fp->txdata_ptr[tx_index];
8880
8881                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8882                                                         txdata->txq_index);
8883
8884                 /* send halt terminate on tx-only connection */
8885                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8886                 memset(&q_params.params.terminate, 0,
8887                        sizeof(q_params.params.terminate));
8888                 q_params.params.terminate.cid_index = tx_index;
8889
8890                 rc = bnx2x_queue_state_change(bp, &q_params);
8891                 if (rc)
8892                         return rc;
8893
8894                 /* send halt terminate on tx-only connection */
8895                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8896                 memset(&q_params.params.cfc_del, 0,
8897                        sizeof(q_params.params.cfc_del));
8898                 q_params.params.cfc_del.cid_index = tx_index;
8899                 rc = bnx2x_queue_state_change(bp, &q_params);
8900                 if (rc)
8901                         return rc;
8902         }
8903         /* Stop the primary connection: */
8904         /* ...halt the connection */
8905         q_params.cmd = BNX2X_Q_CMD_HALT;
8906         rc = bnx2x_queue_state_change(bp, &q_params);
8907         if (rc)
8908                 return rc;
8909
8910         /* ...terminate the connection */
8911         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8912         memset(&q_params.params.terminate, 0,
8913                sizeof(q_params.params.terminate));
8914         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8915         rc = bnx2x_queue_state_change(bp, &q_params);
8916         if (rc)
8917                 return rc;
8918         /* ...delete cfc entry */
8919         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8920         memset(&q_params.params.cfc_del, 0,
8921                sizeof(q_params.params.cfc_del));
8922         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8923         return bnx2x_queue_state_change(bp, &q_params);
8924 }
8925
8926 static void bnx2x_reset_func(struct bnx2x *bp)
8927 {
8928         int port = BP_PORT(bp);
8929         int func = BP_FUNC(bp);
8930         int i;
8931
8932         /* Disable the function in the FW */
8933         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8934         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8935         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8936         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8937
8938         /* FP SBs */
8939         for_each_eth_queue(bp, i) {
8940                 struct bnx2x_fastpath *fp = &bp->fp[i];
8941                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8942                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8943                            SB_DISABLED);
8944         }
8945
8946         if (CNIC_LOADED(bp))
8947                 /* CNIC SB */
8948                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8949                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8950                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8951
8952         /* SP SB */
8953         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8954                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8955                 SB_DISABLED);
8956
8957         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8958                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8959                        0);
8960
8961         /* Configure IGU */
8962         if (bp->common.int_block == INT_BLOCK_HC) {
8963                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8964                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8965         } else {
8966                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8967                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8968         }
8969
8970         if (CNIC_LOADED(bp)) {
8971                 /* Disable Timer scan */
8972                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8973                 /*
8974                  * Wait for at least 10ms and up to 2 second for the timers
8975                  * scan to complete
8976                  */
8977                 for (i = 0; i < 200; i++) {
8978                         usleep_range(10000, 20000);
8979                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8980                                 break;
8981                 }
8982         }
8983         /* Clear ILT */
8984         bnx2x_clear_func_ilt(bp, func);
8985
8986         /* Timers workaround bug for E2: if this is vnic-3,
8987          * we need to set the entire ilt range for this timers.
8988          */
8989         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8990                 struct ilt_client_info ilt_cli;
8991                 /* use dummy TM client */
8992                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8993                 ilt_cli.start = 0;
8994                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8995                 ilt_cli.client_num = ILT_CLIENT_TM;
8996
8997                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8998         }
8999
9000         /* this assumes that reset_port() called before reset_func()*/
9001         if (!CHIP_IS_E1x(bp))
9002                 bnx2x_pf_disable(bp);
9003
9004         bp->dmae_ready = 0;
9005 }
9006
9007 static void bnx2x_reset_port(struct bnx2x *bp)
9008 {
9009         int port = BP_PORT(bp);
9010         u32 val;
9011
9012         /* Reset physical Link */
9013         bnx2x__link_reset(bp);
9014
9015         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9016
9017         /* Do not rcv packets to BRB */
9018         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9019         /* Do not direct rcv packets that are not for MCP to the BRB */
9020         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9021                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9022
9023         /* Configure AEU */
9024         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9025
9026         msleep(100);
9027         /* Check for BRB port occupancy */
9028         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9029         if (val)
9030                 DP(NETIF_MSG_IFDOWN,
9031                    "BRB1 is not empty  %d blocks are occupied\n", val);
9032
9033         /* TODO: Close Doorbell port? */
9034 }
9035
9036 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9037 {
9038         struct bnx2x_func_state_params func_params = {NULL};
9039
9040         /* Prepare parameters for function state transitions */
9041         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9042
9043         func_params.f_obj = &bp->func_obj;
9044         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9045
9046         func_params.params.hw_init.load_phase = load_code;
9047
9048         return bnx2x_func_state_change(bp, &func_params);
9049 }
9050
9051 static int bnx2x_func_stop(struct bnx2x *bp)
9052 {
9053         struct bnx2x_func_state_params func_params = {NULL};
9054         int rc;
9055
9056         /* Prepare parameters for function state transitions */
9057         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9058         func_params.f_obj = &bp->func_obj;
9059         func_params.cmd = BNX2X_F_CMD_STOP;
9060
9061         /*
9062          * Try to stop the function the 'good way'. If fails (in case
9063          * of a parity error during bnx2x_chip_cleanup()) and we are
9064          * not in a debug mode, perform a state transaction in order to
9065          * enable further HW_RESET transaction.
9066          */
9067         rc = bnx2x_func_state_change(bp, &func_params);
9068         if (rc) {
9069 #ifdef BNX2X_STOP_ON_ERROR
9070                 return rc;
9071 #else
9072                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9073                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9074                 return bnx2x_func_state_change(bp, &func_params);
9075 #endif
9076         }
9077
9078         return 0;
9079 }
9080
9081 /**
9082  * bnx2x_send_unload_req - request unload mode from the MCP.
9083  *
9084  * @bp:                 driver handle
9085  * @unload_mode:        requested function's unload mode
9086  *
9087  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9088  */
9089 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9090 {
9091         u32 reset_code = 0;
9092         int port = BP_PORT(bp);
9093
9094         /* Select the UNLOAD request mode */
9095         if (unload_mode == UNLOAD_NORMAL)
9096                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9097
9098         else if (bp->flags & NO_WOL_FLAG)
9099                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9100
9101         else if (bp->wol) {
9102                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9103                 u8 *mac_addr = bp->dev->dev_addr;
9104                 struct pci_dev *pdev = bp->pdev;
9105                 u32 val;
9106                 u16 pmc;
9107
9108                 /* The mac address is written to entries 1-4 to
9109                  * preserve entry 0 which is used by the PMF
9110                  */
9111                 u8 entry = (BP_VN(bp) + 1)*8;
9112
9113                 val = (mac_addr[0] << 8) | mac_addr[1];
9114                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9115
9116                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9117                       (mac_addr[4] << 8) | mac_addr[5];
9118                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9119
9120                 /* Enable the PME and clear the status */
9121                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9122                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9123                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9124
9125                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9126
9127         } else
9128                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9129
9130         /* Send the request to the MCP */
9131         if (!BP_NOMCP(bp))
9132                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9133         else {
9134                 int path = BP_PATH(bp);
9135
9136                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9137                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9138                    bnx2x_load_count[path][2]);
9139                 bnx2x_load_count[path][0]--;
9140                 bnx2x_load_count[path][1 + port]--;
9141                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9142                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9143                    bnx2x_load_count[path][2]);
9144                 if (bnx2x_load_count[path][0] == 0)
9145                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9146                 else if (bnx2x_load_count[path][1 + port] == 0)
9147                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9148                 else
9149                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9150         }
9151
9152         return reset_code;
9153 }
9154
9155 /**
9156  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9157  *
9158  * @bp:         driver handle
9159  * @keep_link:          true iff link should be kept up
9160  */
9161 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9162 {
9163         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9164
9165         /* Report UNLOAD_DONE to MCP */
9166         if (!BP_NOMCP(bp))
9167                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9168 }
9169
9170 static int bnx2x_func_wait_started(struct bnx2x *bp)
9171 {
9172         int tout = 50;
9173         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9174
9175         if (!bp->port.pmf)
9176                 return 0;
9177
9178         /*
9179          * (assumption: No Attention from MCP at this stage)
9180          * PMF probably in the middle of TX disable/enable transaction
9181          * 1. Sync IRS for default SB
9182          * 2. Sync SP queue - this guarantees us that attention handling started
9183          * 3. Wait, that TX disable/enable transaction completes
9184          *
9185          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9186          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9187          * received completion for the transaction the state is TX_STOPPED.
9188          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9189          * transaction.
9190          */
9191
9192         /* make sure default SB ISR is done */
9193         if (msix)
9194                 synchronize_irq(bp->msix_table[0].vector);
9195         else
9196                 synchronize_irq(bp->pdev->irq);
9197
9198         flush_workqueue(bnx2x_wq);
9199         flush_workqueue(bnx2x_iov_wq);
9200
9201         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9202                                 BNX2X_F_STATE_STARTED && tout--)
9203                 msleep(20);
9204
9205         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9206                                                 BNX2X_F_STATE_STARTED) {
9207 #ifdef BNX2X_STOP_ON_ERROR
9208                 BNX2X_ERR("Wrong function state\n");
9209                 return -EBUSY;
9210 #else
9211                 /*
9212                  * Failed to complete the transaction in a "good way"
9213                  * Force both transactions with CLR bit
9214                  */
9215                 struct bnx2x_func_state_params func_params = {NULL};
9216
9217                 DP(NETIF_MSG_IFDOWN,
9218                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9219
9220                 func_params.f_obj = &bp->func_obj;
9221                 __set_bit(RAMROD_DRV_CLR_ONLY,
9222                                         &func_params.ramrod_flags);
9223
9224                 /* STARTED-->TX_ST0PPED */
9225                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9226                 bnx2x_func_state_change(bp, &func_params);
9227
9228                 /* TX_ST0PPED-->STARTED */
9229                 func_params.cmd = BNX2X_F_CMD_TX_START;
9230                 return bnx2x_func_state_change(bp, &func_params);
9231 #endif
9232         }
9233
9234         return 0;
9235 }
9236
9237 static void bnx2x_disable_ptp(struct bnx2x *bp)
9238 {
9239         int port = BP_PORT(bp);
9240
9241         /* Disable sending PTP packets to host */
9242         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9243                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9244
9245         /* Reset PTP event detection rules */
9246         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9247                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9248         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9249                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9250         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9251                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9252         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9253                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9254
9255         /* Disable the PTP feature */
9256         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9257                NIG_REG_P0_PTP_EN, 0x0);
9258 }
9259
9260 /* Called during unload, to stop PTP-related stuff */
9261 static void bnx2x_stop_ptp(struct bnx2x *bp)
9262 {
9263         /* Cancel PTP work queue. Should be done after the Tx queues are
9264          * drained to prevent additional scheduling.
9265          */
9266         cancel_work_sync(&bp->ptp_task);
9267
9268         if (bp->ptp_tx_skb) {
9269                 dev_kfree_skb_any(bp->ptp_tx_skb);
9270                 bp->ptp_tx_skb = NULL;
9271         }
9272
9273         /* Disable PTP in HW */
9274         bnx2x_disable_ptp(bp);
9275
9276         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9277 }
9278
9279 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9280 {
9281         int port = BP_PORT(bp);
9282         int i, rc = 0;
9283         u8 cos;
9284         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9285         u32 reset_code;
9286
9287         /* Wait until tx fastpath tasks complete */
9288         for_each_tx_queue(bp, i) {
9289                 struct bnx2x_fastpath *fp = &bp->fp[i];
9290
9291                 for_each_cos_in_tx_queue(fp, cos)
9292                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9293 #ifdef BNX2X_STOP_ON_ERROR
9294                 if (rc)
9295                         return;
9296 #endif
9297         }
9298
9299         /* Give HW time to discard old tx messages */
9300         usleep_range(1000, 2000);
9301
9302         /* Clean all ETH MACs */
9303         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9304                                 false);
9305         if (rc < 0)
9306                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9307
9308         /* Clean up UC list  */
9309         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9310                                 true);
9311         if (rc < 0)
9312                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9313                           rc);
9314
9315         /* Disable LLH */
9316         if (!CHIP_IS_E1(bp))
9317                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9318
9319         /* Set "drop all" (stop Rx).
9320          * We need to take a netif_addr_lock() here in order to prevent
9321          * a race between the completion code and this code.
9322          */
9323         netif_addr_lock_bh(bp->dev);
9324         /* Schedule the rx_mode command */
9325         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9326                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9327         else
9328                 bnx2x_set_storm_rx_mode(bp);
9329
9330         /* Cleanup multicast configuration */
9331         rparam.mcast_obj = &bp->mcast_obj;
9332         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9333         if (rc < 0)
9334                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9335
9336         netif_addr_unlock_bh(bp->dev);
9337
9338         bnx2x_iov_chip_cleanup(bp);
9339
9340         /*
9341          * Send the UNLOAD_REQUEST to the MCP. This will return if
9342          * this function should perform FUNC, PORT or COMMON HW
9343          * reset.
9344          */
9345         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9346
9347         /*
9348          * (assumption: No Attention from MCP at this stage)
9349          * PMF probably in the middle of TX disable/enable transaction
9350          */
9351         rc = bnx2x_func_wait_started(bp);
9352         if (rc) {
9353                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9354 #ifdef BNX2X_STOP_ON_ERROR
9355                 return;
9356 #endif
9357         }
9358
9359         /* Close multi and leading connections
9360          * Completions for ramrods are collected in a synchronous way
9361          */
9362         for_each_eth_queue(bp, i)
9363                 if (bnx2x_stop_queue(bp, i))
9364 #ifdef BNX2X_STOP_ON_ERROR
9365                         return;
9366 #else
9367                         goto unload_error;
9368 #endif
9369
9370         if (CNIC_LOADED(bp)) {
9371                 for_each_cnic_queue(bp, i)
9372                         if (bnx2x_stop_queue(bp, i))
9373 #ifdef BNX2X_STOP_ON_ERROR
9374                                 return;
9375 #else
9376                                 goto unload_error;
9377 #endif
9378         }
9379
9380         /* If SP settings didn't get completed so far - something
9381          * very wrong has happen.
9382          */
9383         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9384                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9385
9386 #ifndef BNX2X_STOP_ON_ERROR
9387 unload_error:
9388 #endif
9389         rc = bnx2x_func_stop(bp);
9390         if (rc) {
9391                 BNX2X_ERR("Function stop failed!\n");
9392 #ifdef BNX2X_STOP_ON_ERROR
9393                 return;
9394 #endif
9395         }
9396
9397         /* stop_ptp should be after the Tx queues are drained to prevent
9398          * scheduling to the cancelled PTP work queue. It should also be after
9399          * function stop ramrod is sent, since as part of this ramrod FW access
9400          * PTP registers.
9401          */
9402         if (bp->flags & PTP_SUPPORTED)
9403                 bnx2x_stop_ptp(bp);
9404
9405         /* Disable HW interrupts, NAPI */
9406         bnx2x_netif_stop(bp, 1);
9407         /* Delete all NAPI objects */
9408         bnx2x_del_all_napi(bp);
9409         if (CNIC_LOADED(bp))
9410                 bnx2x_del_all_napi_cnic(bp);
9411
9412         /* Release IRQs */
9413         bnx2x_free_irq(bp);
9414
9415         /* Reset the chip */
9416         rc = bnx2x_reset_hw(bp, reset_code);
9417         if (rc)
9418                 BNX2X_ERR("HW_RESET failed\n");
9419
9420         /* Report UNLOAD_DONE to MCP */
9421         bnx2x_send_unload_done(bp, keep_link);
9422 }
9423
9424 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9425 {
9426         u32 val;
9427
9428         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9429
9430         if (CHIP_IS_E1(bp)) {
9431                 int port = BP_PORT(bp);
9432                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9433                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9434
9435                 val = REG_RD(bp, addr);
9436                 val &= ~(0x300);
9437                 REG_WR(bp, addr, val);
9438         } else {
9439                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9440                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9441                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9442                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9443         }
9444 }
9445
9446 /* Close gates #2, #3 and #4: */
9447 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9448 {
9449         u32 val;
9450
9451         /* Gates #2 and #4a are closed/opened for "not E1" only */
9452         if (!CHIP_IS_E1(bp)) {
9453                 /* #4 */
9454                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9455                 /* #2 */
9456                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9457         }
9458
9459         /* #3 */
9460         if (CHIP_IS_E1x(bp)) {
9461                 /* Prevent interrupts from HC on both ports */
9462                 val = REG_RD(bp, HC_REG_CONFIG_1);
9463                 REG_WR(bp, HC_REG_CONFIG_1,
9464                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9465                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9466
9467                 val = REG_RD(bp, HC_REG_CONFIG_0);
9468                 REG_WR(bp, HC_REG_CONFIG_0,
9469                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9470                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9471         } else {
9472                 /* Prevent incoming interrupts in IGU */
9473                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9474
9475                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9476                        (!close) ?
9477                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9478                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9479         }
9480
9481         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9482                 close ? "closing" : "opening");
9483         mmiowb();
9484 }
9485
9486 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9487
9488 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9489 {
9490         /* Do some magic... */
9491         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9492         *magic_val = val & SHARED_MF_CLP_MAGIC;
9493         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9494 }
9495
9496 /**
9497  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9498  *
9499  * @bp:         driver handle
9500  * @magic_val:  old value of the `magic' bit.
9501  */
9502 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9503 {
9504         /* Restore the `magic' bit value... */
9505         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9506         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9507                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9508 }
9509
9510 /**
9511  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9512  *
9513  * @bp:         driver handle
9514  * @magic_val:  old value of 'magic' bit.
9515  *
9516  * Takes care of CLP configurations.
9517  */
9518 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9519 {
9520         u32 shmem;
9521         u32 validity_offset;
9522
9523         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9524
9525         /* Set `magic' bit in order to save MF config */
9526         if (!CHIP_IS_E1(bp))
9527                 bnx2x_clp_reset_prep(bp, magic_val);
9528
9529         /* Get shmem offset */
9530         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9531         validity_offset =
9532                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9533
9534         /* Clear validity map flags */
9535         if (shmem > 0)
9536                 REG_WR(bp, shmem + validity_offset, 0);
9537 }
9538
9539 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9540 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9541
9542 /**
9543  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9544  *
9545  * @bp: driver handle
9546  */
9547 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9548 {
9549         /* special handling for emulation and FPGA,
9550            wait 10 times longer */
9551         if (CHIP_REV_IS_SLOW(bp))
9552                 msleep(MCP_ONE_TIMEOUT*10);
9553         else
9554                 msleep(MCP_ONE_TIMEOUT);
9555 }
9556
9557 /*
9558  * initializes bp->common.shmem_base and waits for validity signature to appear
9559  */
9560 static int bnx2x_init_shmem(struct bnx2x *bp)
9561 {
9562         int cnt = 0;
9563         u32 val = 0;
9564
9565         do {
9566                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9567                 if (bp->common.shmem_base) {
9568                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9569                         if (val & SHR_MEM_VALIDITY_MB)
9570                                 return 0;
9571                 }
9572
9573                 bnx2x_mcp_wait_one(bp);
9574
9575         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9576
9577         BNX2X_ERR("BAD MCP validity signature\n");
9578
9579         return -ENODEV;
9580 }
9581
9582 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9583 {
9584         int rc = bnx2x_init_shmem(bp);
9585
9586         /* Restore the `magic' bit value */
9587         if (!CHIP_IS_E1(bp))
9588                 bnx2x_clp_reset_done(bp, magic_val);
9589
9590         return rc;
9591 }
9592
9593 static void bnx2x_pxp_prep(struct bnx2x *bp)
9594 {
9595         if (!CHIP_IS_E1(bp)) {
9596                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9597                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9598                 mmiowb();
9599         }
9600 }
9601
9602 /*
9603  * Reset the whole chip except for:
9604  *      - PCIE core
9605  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9606  *              one reset bit)
9607  *      - IGU
9608  *      - MISC (including AEU)
9609  *      - GRC
9610  *      - RBCN, RBCP
9611  */
9612 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9613 {
9614         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9615         u32 global_bits2, stay_reset2;
9616
9617         /*
9618          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9619          * (per chip) blocks.
9620          */
9621         global_bits2 =
9622                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9623                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9624
9625         /* Don't reset the following blocks.
9626          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9627          *            reset, as in 4 port device they might still be owned
9628          *            by the MCP (there is only one leader per path).
9629          */
9630         not_reset_mask1 =
9631                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9632                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9633                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9634
9635         not_reset_mask2 =
9636                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9637                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9638                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9639                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9640                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9641                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9642                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9643                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9644                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9645                 MISC_REGISTERS_RESET_REG_2_PGLC |
9646                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9647                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9648                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9649                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9650                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9651                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9652
9653         /*
9654          * Keep the following blocks in reset:
9655          *  - all xxMACs are handled by the bnx2x_link code.
9656          */
9657         stay_reset2 =
9658                 MISC_REGISTERS_RESET_REG_2_XMAC |
9659                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9660
9661         /* Full reset masks according to the chip */
9662         reset_mask1 = 0xffffffff;
9663
9664         if (CHIP_IS_E1(bp))
9665                 reset_mask2 = 0xffff;
9666         else if (CHIP_IS_E1H(bp))
9667                 reset_mask2 = 0x1ffff;
9668         else if (CHIP_IS_E2(bp))
9669                 reset_mask2 = 0xfffff;
9670         else /* CHIP_IS_E3 */
9671                 reset_mask2 = 0x3ffffff;
9672
9673         /* Don't reset global blocks unless we need to */
9674         if (!global)
9675                 reset_mask2 &= ~global_bits2;
9676
9677         /*
9678          * In case of attention in the QM, we need to reset PXP
9679          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9680          * because otherwise QM reset would release 'close the gates' shortly
9681          * before resetting the PXP, then the PSWRQ would send a write
9682          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9683          * read the payload data from PSWWR, but PSWWR would not
9684          * respond. The write queue in PGLUE would stuck, dmae commands
9685          * would not return. Therefore it's important to reset the second
9686          * reset register (containing the
9687          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9688          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9689          * bit).
9690          */
9691         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9692                reset_mask2 & (~not_reset_mask2));
9693
9694         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9695                reset_mask1 & (~not_reset_mask1));
9696
9697         barrier();
9698         mmiowb();
9699
9700         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9701                reset_mask2 & (~stay_reset2));
9702
9703         barrier();
9704         mmiowb();
9705
9706         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9707         mmiowb();
9708 }
9709
9710 /**
9711  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9712  * It should get cleared in no more than 1s.
9713  *
9714  * @bp: driver handle
9715  *
9716  * It should get cleared in no more than 1s. Returns 0 if
9717  * pending writes bit gets cleared.
9718  */
9719 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9720 {
9721         u32 cnt = 1000;
9722         u32 pend_bits = 0;
9723
9724         do {
9725                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9726
9727                 if (pend_bits == 0)
9728                         break;
9729
9730                 usleep_range(1000, 2000);
9731         } while (cnt-- > 0);
9732
9733         if (cnt <= 0) {
9734                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9735                           pend_bits);
9736                 return -EBUSY;
9737         }
9738
9739         return 0;
9740 }
9741
9742 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9743 {
9744         int cnt = 1000;
9745         u32 val = 0;
9746         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9747         u32 tags_63_32 = 0;
9748
9749         /* Empty the Tetris buffer, wait for 1s */
9750         do {
9751                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9752                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9753                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9754                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9755                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9756                 if (CHIP_IS_E3(bp))
9757                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9758
9759                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9760                     ((port_is_idle_0 & 0x1) == 0x1) &&
9761                     ((port_is_idle_1 & 0x1) == 0x1) &&
9762                     (pgl_exp_rom2 == 0xffffffff) &&
9763                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9764                         break;
9765                 usleep_range(1000, 2000);
9766         } while (cnt-- > 0);
9767
9768         if (cnt <= 0) {
9769                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9770                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9771                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9772                           pgl_exp_rom2);
9773                 return -EAGAIN;
9774         }
9775
9776         barrier();
9777
9778         /* Close gates #2, #3 and #4 */
9779         bnx2x_set_234_gates(bp, true);
9780
9781         /* Poll for IGU VQs for 57712 and newer chips */
9782         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9783                 return -EAGAIN;
9784
9785         /* TBD: Indicate that "process kill" is in progress to MCP */
9786
9787         /* Clear "unprepared" bit */
9788         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9789         barrier();
9790
9791         /* Make sure all is written to the chip before the reset */
9792         mmiowb();
9793
9794         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9795          * PSWHST, GRC and PSWRD Tetris buffer.
9796          */
9797         usleep_range(1000, 2000);
9798
9799         /* Prepare to chip reset: */
9800         /* MCP */
9801         if (global)
9802                 bnx2x_reset_mcp_prep(bp, &val);
9803
9804         /* PXP */
9805         bnx2x_pxp_prep(bp);
9806         barrier();
9807
9808         /* reset the chip */
9809         bnx2x_process_kill_chip_reset(bp, global);
9810         barrier();
9811
9812         /* clear errors in PGB */
9813         if (!CHIP_IS_E1x(bp))
9814                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9815
9816         /* Recover after reset: */
9817         /* MCP */
9818         if (global && bnx2x_reset_mcp_comp(bp, val))
9819                 return -EAGAIN;
9820
9821         /* TBD: Add resetting the NO_MCP mode DB here */
9822
9823         /* Open the gates #2, #3 and #4 */
9824         bnx2x_set_234_gates(bp, false);
9825
9826         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9827          * reset state, re-enable attentions. */
9828
9829         return 0;
9830 }
9831
9832 static int bnx2x_leader_reset(struct bnx2x *bp)
9833 {
9834         int rc = 0;
9835         bool global = bnx2x_reset_is_global(bp);
9836         u32 load_code;
9837
9838         /* if not going to reset MCP - load "fake" driver to reset HW while
9839          * driver is owner of the HW
9840          */
9841         if (!global && !BP_NOMCP(bp)) {
9842                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9843                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9844                 if (!load_code) {
9845                         BNX2X_ERR("MCP response failure, aborting\n");
9846                         rc = -EAGAIN;
9847                         goto exit_leader_reset;
9848                 }
9849                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9850                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9851                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9852                         rc = -EAGAIN;
9853                         goto exit_leader_reset2;
9854                 }
9855                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9856                 if (!load_code) {
9857                         BNX2X_ERR("MCP response failure, aborting\n");
9858                         rc = -EAGAIN;
9859                         goto exit_leader_reset2;
9860                 }
9861         }
9862
9863         /* Try to recover after the failure */
9864         if (bnx2x_process_kill(bp, global)) {
9865                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9866                           BP_PATH(bp));
9867                 rc = -EAGAIN;
9868                 goto exit_leader_reset2;
9869         }
9870
9871         /*
9872          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9873          * state.
9874          */
9875         bnx2x_set_reset_done(bp);
9876         if (global)
9877                 bnx2x_clear_reset_global(bp);
9878
9879 exit_leader_reset2:
9880         /* unload "fake driver" if it was loaded */
9881         if (!global && !BP_NOMCP(bp)) {
9882                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9883                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9884         }
9885 exit_leader_reset:
9886         bp->is_leader = 0;
9887         bnx2x_release_leader_lock(bp);
9888         smp_mb();
9889         return rc;
9890 }
9891
9892 static void bnx2x_recovery_failed(struct bnx2x *bp)
9893 {
9894         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9895
9896         /* Disconnect this device */
9897         netif_device_detach(bp->dev);
9898
9899         /*
9900          * Block ifup for all function on this engine until "process kill"
9901          * or power cycle.
9902          */
9903         bnx2x_set_reset_in_progress(bp);
9904
9905         /* Shut down the power */
9906         bnx2x_set_power_state(bp, PCI_D3hot);
9907
9908         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9909
9910         smp_mb();
9911 }
9912
9913 /*
9914  * Assumption: runs under rtnl lock. This together with the fact
9915  * that it's called only from bnx2x_sp_rtnl() ensure that it
9916  * will never be called when netif_running(bp->dev) is false.
9917  */
9918 static void bnx2x_parity_recover(struct bnx2x *bp)
9919 {
9920         bool global = false;
9921         u32 error_recovered, error_unrecovered;
9922         bool is_parity;
9923
9924         DP(NETIF_MSG_HW, "Handling parity\n");
9925         while (1) {
9926                 switch (bp->recovery_state) {
9927                 case BNX2X_RECOVERY_INIT:
9928                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9929                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9930                         WARN_ON(!is_parity);
9931
9932                         /* Try to get a LEADER_LOCK HW lock */
9933                         if (bnx2x_trylock_leader_lock(bp)) {
9934                                 bnx2x_set_reset_in_progress(bp);
9935                                 /*
9936                                  * Check if there is a global attention and if
9937                                  * there was a global attention, set the global
9938                                  * reset bit.
9939                                  */
9940
9941                                 if (global)
9942                                         bnx2x_set_reset_global(bp);
9943
9944                                 bp->is_leader = 1;
9945                         }
9946
9947                         /* Stop the driver */
9948                         /* If interface has been removed - break */
9949                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9950                                 return;
9951
9952                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9953
9954                         /* Ensure "is_leader", MCP command sequence and
9955                          * "recovery_state" update values are seen on other
9956                          * CPUs.
9957                          */
9958                         smp_mb();
9959                         break;
9960
9961                 case BNX2X_RECOVERY_WAIT:
9962                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9963                         if (bp->is_leader) {
9964                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9965                                 bool other_load_status =
9966                                         bnx2x_get_load_status(bp, other_engine);
9967                                 bool load_status =
9968                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9969                                 global = bnx2x_reset_is_global(bp);
9970
9971                                 /*
9972                                  * In case of a parity in a global block, let
9973                                  * the first leader that performs a
9974                                  * leader_reset() reset the global blocks in
9975                                  * order to clear global attentions. Otherwise
9976                                  * the gates will remain closed for that
9977                                  * engine.
9978                                  */
9979                                 if (load_status ||
9980                                     (global && other_load_status)) {
9981                                         /* Wait until all other functions get
9982                                          * down.
9983                                          */
9984                                         schedule_delayed_work(&bp->sp_rtnl_task,
9985                                                                 HZ/10);
9986                                         return;
9987                                 } else {
9988                                         /* If all other functions got down -
9989                                          * try to bring the chip back to
9990                                          * normal. In any case it's an exit
9991                                          * point for a leader.
9992                                          */
9993                                         if (bnx2x_leader_reset(bp)) {
9994                                                 bnx2x_recovery_failed(bp);
9995                                                 return;
9996                                         }
9997
9998                                         /* If we are here, means that the
9999                                          * leader has succeeded and doesn't
10000                                          * want to be a leader any more. Try
10001                                          * to continue as a none-leader.
10002                                          */
10003                                         break;
10004                                 }
10005                         } else { /* non-leader */
10006                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10007                                         /* Try to get a LEADER_LOCK HW lock as
10008                                          * long as a former leader may have
10009                                          * been unloaded by the user or
10010                                          * released a leadership by another
10011                                          * reason.
10012                                          */
10013                                         if (bnx2x_trylock_leader_lock(bp)) {
10014                                                 /* I'm a leader now! Restart a
10015                                                  * switch case.
10016                                                  */
10017                                                 bp->is_leader = 1;
10018                                                 break;
10019                                         }
10020
10021                                         schedule_delayed_work(&bp->sp_rtnl_task,
10022                                                                 HZ/10);
10023                                         return;
10024
10025                                 } else {
10026                                         /*
10027                                          * If there was a global attention, wait
10028                                          * for it to be cleared.
10029                                          */
10030                                         if (bnx2x_reset_is_global(bp)) {
10031                                                 schedule_delayed_work(
10032                                                         &bp->sp_rtnl_task,
10033                                                         HZ/10);
10034                                                 return;
10035                                         }
10036
10037                                         error_recovered =
10038                                           bp->eth_stats.recoverable_error;
10039                                         error_unrecovered =
10040                                           bp->eth_stats.unrecoverable_error;
10041                                         bp->recovery_state =
10042                                                 BNX2X_RECOVERY_NIC_LOADING;
10043                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10044                                                 error_unrecovered++;
10045                                                 netdev_err(bp->dev,
10046                                                            "Recovery failed. Power cycle needed\n");
10047                                                 /* Disconnect this device */
10048                                                 netif_device_detach(bp->dev);
10049                                                 /* Shut down the power */
10050                                                 bnx2x_set_power_state(
10051                                                         bp, PCI_D3hot);
10052                                                 smp_mb();
10053                                         } else {
10054                                                 bp->recovery_state =
10055                                                         BNX2X_RECOVERY_DONE;
10056                                                 error_recovered++;
10057                                                 smp_mb();
10058                                         }
10059                                         bp->eth_stats.recoverable_error =
10060                                                 error_recovered;
10061                                         bp->eth_stats.unrecoverable_error =
10062                                                 error_unrecovered;
10063
10064                                         return;
10065                                 }
10066                         }
10067                 default:
10068                         return;
10069                 }
10070         }
10071 }
10072
10073 #ifdef CONFIG_BNX2X_VXLAN
10074 static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port)
10075 {
10076         struct bnx2x_func_switch_update_params *switch_update_params;
10077         struct bnx2x_func_state_params func_params = {NULL};
10078         int rc;
10079
10080         switch_update_params = &func_params.params.switch_update;
10081
10082         /* Prepare parameters for function state transitions */
10083         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10084         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10085
10086         func_params.f_obj = &bp->func_obj;
10087         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10088
10089         /* Function parameters */
10090         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10091                   &switch_update_params->changes);
10092         switch_update_params->vxlan_dst_port = port;
10093         rc = bnx2x_func_state_change(bp, &func_params);
10094         if (rc)
10095                 BNX2X_ERR("failed to change vxlan dst port to %d (rc = 0x%x)\n",
10096                           port, rc);
10097         return rc;
10098 }
10099
10100 static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port)
10101 {
10102         if (!netif_running(bp->dev))
10103                 return;
10104
10105         if (bp->vxlan_dst_port_count && bp->vxlan_dst_port == port) {
10106                 bp->vxlan_dst_port_count++;
10107                 return;
10108         }
10109
10110         if (bp->vxlan_dst_port_count || !IS_PF(bp)) {
10111                 DP(BNX2X_MSG_SP, "Vxlan destination port limit reached\n");
10112                 return;
10113         }
10114
10115         bp->vxlan_dst_port = port;
10116         bp->vxlan_dst_port_count = 1;
10117         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0);
10118 }
10119
10120 static void bnx2x_add_vxlan_port(struct net_device *netdev,
10121                                  sa_family_t sa_family, __be16 port)
10122 {
10123         struct bnx2x *bp = netdev_priv(netdev);
10124         u16 t_port = ntohs(port);
10125
10126         __bnx2x_add_vxlan_port(bp, t_port);
10127 }
10128
10129 static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port)
10130 {
10131         if (!bp->vxlan_dst_port_count || bp->vxlan_dst_port != port ||
10132             !IS_PF(bp)) {
10133                 DP(BNX2X_MSG_SP, "Invalid vxlan port\n");
10134                 return;
10135         }
10136         bp->vxlan_dst_port_count--;
10137         if (bp->vxlan_dst_port_count)
10138                 return;
10139
10140         if (netif_running(bp->dev)) {
10141                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0);
10142         } else {
10143                 bp->vxlan_dst_port = 0;
10144                 netdev_info(bp->dev, "Deleted vxlan dest port %d", port);
10145         }
10146 }
10147
10148 static void bnx2x_del_vxlan_port(struct net_device *netdev,
10149                                  sa_family_t sa_family, __be16 port)
10150 {
10151         struct bnx2x *bp = netdev_priv(netdev);
10152         u16 t_port = ntohs(port);
10153
10154         __bnx2x_del_vxlan_port(bp, t_port);
10155 }
10156 #endif
10157
10158 static int bnx2x_close(struct net_device *dev);
10159
10160 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10161  * scheduled on a general queue in order to prevent a dead lock.
10162  */
10163 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10164 {
10165         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10166 #ifdef CONFIG_BNX2X_VXLAN
10167         u16 port;
10168 #endif
10169
10170         rtnl_lock();
10171
10172         if (!netif_running(bp->dev)) {
10173                 rtnl_unlock();
10174                 return;
10175         }
10176
10177         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10178 #ifdef BNX2X_STOP_ON_ERROR
10179                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10180                           "you will need to reboot when done\n");
10181                 goto sp_rtnl_not_reset;
10182 #endif
10183                 /*
10184                  * Clear all pending SP commands as we are going to reset the
10185                  * function anyway.
10186                  */
10187                 bp->sp_rtnl_state = 0;
10188                 smp_mb();
10189
10190                 bnx2x_parity_recover(bp);
10191
10192                 rtnl_unlock();
10193                 return;
10194         }
10195
10196         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10197 #ifdef BNX2X_STOP_ON_ERROR
10198                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10199                           "you will need to reboot when done\n");
10200                 goto sp_rtnl_not_reset;
10201 #endif
10202
10203                 /*
10204                  * Clear all pending SP commands as we are going to reset the
10205                  * function anyway.
10206                  */
10207                 bp->sp_rtnl_state = 0;
10208                 smp_mb();
10209
10210                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10211                 bnx2x_nic_load(bp, LOAD_NORMAL);
10212
10213                 rtnl_unlock();
10214                 return;
10215         }
10216 #ifdef BNX2X_STOP_ON_ERROR
10217 sp_rtnl_not_reset:
10218 #endif
10219         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10220                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10221         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10222                 bnx2x_after_function_update(bp);
10223         /*
10224          * in case of fan failure we need to reset id if the "stop on error"
10225          * debug flag is set, since we trying to prevent permanent overheating
10226          * damage
10227          */
10228         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10229                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10230                 netif_device_detach(bp->dev);
10231                 bnx2x_close(bp->dev);
10232                 rtnl_unlock();
10233                 return;
10234         }
10235
10236         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10237                 DP(BNX2X_MSG_SP,
10238                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10239                 bnx2x_vfpf_set_mcast(bp->dev);
10240         }
10241         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10242                                &bp->sp_rtnl_state)){
10243                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10244                         bnx2x_tx_disable(bp);
10245                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10246                 }
10247         }
10248
10249         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10250                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10251                 bnx2x_set_rx_mode_inner(bp);
10252         }
10253
10254         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10255                                &bp->sp_rtnl_state))
10256                 bnx2x_pf_set_vfs_vlan(bp);
10257
10258         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10259                 bnx2x_dcbx_stop_hw_tx(bp);
10260                 bnx2x_dcbx_resume_hw_tx(bp);
10261         }
10262
10263         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10264                                &bp->sp_rtnl_state))
10265                 bnx2x_update_mng_version(bp);
10266
10267 #ifdef CONFIG_BNX2X_VXLAN
10268         port = bp->vxlan_dst_port;
10269         if (test_and_clear_bit(BNX2X_SP_RTNL_ADD_VXLAN_PORT,
10270                                &bp->sp_rtnl_state)) {
10271                 if (!bnx2x_vxlan_port_update(bp, port))
10272                         netdev_info(bp->dev, "Added vxlan dest port %d", port);
10273                 else
10274                         bp->vxlan_dst_port = 0;
10275         }
10276
10277         if (test_and_clear_bit(BNX2X_SP_RTNL_DEL_VXLAN_PORT,
10278                                &bp->sp_rtnl_state)) {
10279                 if (!bnx2x_vxlan_port_update(bp, 0)) {
10280                         netdev_info(bp->dev,
10281                                     "Deleted vxlan dest port %d", port);
10282                         bp->vxlan_dst_port = 0;
10283                         vxlan_get_rx_port(bp->dev);
10284                 }
10285         }
10286 #endif
10287
10288         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10289          * can be called from other contexts as well)
10290          */
10291         rtnl_unlock();
10292
10293         /* enable SR-IOV if applicable */
10294         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10295                                                &bp->sp_rtnl_state)) {
10296                 bnx2x_disable_sriov(bp);
10297                 bnx2x_enable_sriov(bp);
10298         }
10299 }
10300
10301 static void bnx2x_period_task(struct work_struct *work)
10302 {
10303         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10304
10305         if (!netif_running(bp->dev))
10306                 goto period_task_exit;
10307
10308         if (CHIP_REV_IS_SLOW(bp)) {
10309                 BNX2X_ERR("period task called on emulation, ignoring\n");
10310                 goto period_task_exit;
10311         }
10312
10313         bnx2x_acquire_phy_lock(bp);
10314         /*
10315          * The barrier is needed to ensure the ordering between the writing to
10316          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10317          * the reading here.
10318          */
10319         smp_mb();
10320         if (bp->port.pmf) {
10321                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10322
10323                 /* Re-queue task in 1 sec */
10324                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10325         }
10326
10327         bnx2x_release_phy_lock(bp);
10328 period_task_exit:
10329         return;
10330 }
10331
10332 /*
10333  * Init service functions
10334  */
10335
10336 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10337 {
10338         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10339         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10340         return base + (BP_ABS_FUNC(bp)) * stride;
10341 }
10342
10343 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10344                                          u8 port, u32 reset_reg,
10345                                          struct bnx2x_mac_vals *vals)
10346 {
10347         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10348         u32 base_addr;
10349
10350         if (!(mask & reset_reg))
10351                 return false;
10352
10353         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10354         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10355         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10356         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10357         REG_WR(bp, vals->umac_addr[port], 0);
10358
10359         return true;
10360 }
10361
10362 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10363                                         struct bnx2x_mac_vals *vals)
10364 {
10365         u32 val, base_addr, offset, mask, reset_reg;
10366         bool mac_stopped = false;
10367         u8 port = BP_PORT(bp);
10368
10369         /* reset addresses as they also mark which values were changed */
10370         memset(vals, 0, sizeof(*vals));
10371
10372         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10373
10374         if (!CHIP_IS_E3(bp)) {
10375                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10376                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10377                 if ((mask & reset_reg) && val) {
10378                         u32 wb_data[2];
10379                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10380                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10381                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10382                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10383                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10384
10385                         /*
10386                          * use rd/wr since we cannot use dmae. This is safe
10387                          * since MCP won't access the bus due to the request
10388                          * to unload, and no function on the path can be
10389                          * loaded at this time.
10390                          */
10391                         wb_data[0] = REG_RD(bp, base_addr + offset);
10392                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10393                         vals->bmac_addr = base_addr + offset;
10394                         vals->bmac_val[0] = wb_data[0];
10395                         vals->bmac_val[1] = wb_data[1];
10396                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10397                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10398                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10399                 }
10400                 BNX2X_DEV_INFO("Disable emac Rx\n");
10401                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10402                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10403                 REG_WR(bp, vals->emac_addr, 0);
10404                 mac_stopped = true;
10405         } else {
10406                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10407                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10408                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10409                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10410                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10411                                val & ~(1 << 1));
10412                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10413                                val | (1 << 1));
10414                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10415                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10416                         REG_WR(bp, vals->xmac_addr, 0);
10417                         mac_stopped = true;
10418                 }
10419
10420                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10421                                                             reset_reg, vals);
10422                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10423                                                             reset_reg, vals);
10424         }
10425
10426         if (mac_stopped)
10427                 msleep(20);
10428 }
10429
10430 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10431 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10432                                         0x1848 + ((f) << 4))
10433 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10434 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10435 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10436
10437 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10438 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10439 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10440
10441 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10442 {
10443         /* UNDI marks its presence in DORQ -
10444          * it initializes CID offset for normal bell to 0x7
10445          */
10446         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10447             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10448                 return false;
10449
10450         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10451                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10452                 return true;
10453         }
10454
10455         return false;
10456 }
10457
10458 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10459 {
10460         u16 rcq, bd;
10461         u32 addr, tmp_reg;
10462
10463         if (BP_FUNC(bp) < 2)
10464                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10465         else
10466                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10467
10468         tmp_reg = REG_RD(bp, addr);
10469         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10470         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10471
10472         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10473         REG_WR(bp, addr, tmp_reg);
10474
10475         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10476                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10477 }
10478
10479 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10480 {
10481         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10482                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10483         if (!rc) {
10484                 BNX2X_ERR("MCP response failure, aborting\n");
10485                 return -EBUSY;
10486         }
10487
10488         return 0;
10489 }
10490
10491 static struct bnx2x_prev_path_list *
10492                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10493 {
10494         struct bnx2x_prev_path_list *tmp_list;
10495
10496         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10497                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10498                     bp->pdev->bus->number == tmp_list->bus &&
10499                     BP_PATH(bp) == tmp_list->path)
10500                         return tmp_list;
10501
10502         return NULL;
10503 }
10504
10505 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10506 {
10507         struct bnx2x_prev_path_list *tmp_list;
10508         int rc;
10509
10510         rc = down_interruptible(&bnx2x_prev_sem);
10511         if (rc) {
10512                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10513                 return rc;
10514         }
10515
10516         tmp_list = bnx2x_prev_path_get_entry(bp);
10517         if (tmp_list) {
10518                 tmp_list->aer = 1;
10519                 rc = 0;
10520         } else {
10521                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10522                           BP_PATH(bp));
10523         }
10524
10525         up(&bnx2x_prev_sem);
10526
10527         return rc;
10528 }
10529
10530 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10531 {
10532         struct bnx2x_prev_path_list *tmp_list;
10533         bool rc = false;
10534
10535         if (down_trylock(&bnx2x_prev_sem))
10536                 return false;
10537
10538         tmp_list = bnx2x_prev_path_get_entry(bp);
10539         if (tmp_list) {
10540                 if (tmp_list->aer) {
10541                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10542                            BP_PATH(bp));
10543                 } else {
10544                         rc = true;
10545                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10546                                        BP_PATH(bp));
10547                 }
10548         }
10549
10550         up(&bnx2x_prev_sem);
10551
10552         return rc;
10553 }
10554
10555 bool bnx2x_port_after_undi(struct bnx2x *bp)
10556 {
10557         struct bnx2x_prev_path_list *entry;
10558         bool val;
10559
10560         down(&bnx2x_prev_sem);
10561
10562         entry = bnx2x_prev_path_get_entry(bp);
10563         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10564
10565         up(&bnx2x_prev_sem);
10566
10567         return val;
10568 }
10569
10570 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10571 {
10572         struct bnx2x_prev_path_list *tmp_list;
10573         int rc;
10574
10575         rc = down_interruptible(&bnx2x_prev_sem);
10576         if (rc) {
10577                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10578                 return rc;
10579         }
10580
10581         /* Check whether the entry for this path already exists */
10582         tmp_list = bnx2x_prev_path_get_entry(bp);
10583         if (tmp_list) {
10584                 if (!tmp_list->aer) {
10585                         BNX2X_ERR("Re-Marking the path.\n");
10586                 } else {
10587                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10588                            BP_PATH(bp));
10589                         tmp_list->aer = 0;
10590                 }
10591                 up(&bnx2x_prev_sem);
10592                 return 0;
10593         }
10594         up(&bnx2x_prev_sem);
10595
10596         /* Create an entry for this path and add it */
10597         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10598         if (!tmp_list) {
10599                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10600                 return -ENOMEM;
10601         }
10602
10603         tmp_list->bus = bp->pdev->bus->number;
10604         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10605         tmp_list->path = BP_PATH(bp);
10606         tmp_list->aer = 0;
10607         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10608
10609         rc = down_interruptible(&bnx2x_prev_sem);
10610         if (rc) {
10611                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10612                 kfree(tmp_list);
10613         } else {
10614                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10615                    BP_PATH(bp));
10616                 list_add(&tmp_list->list, &bnx2x_prev_list);
10617                 up(&bnx2x_prev_sem);
10618         }
10619
10620         return rc;
10621 }
10622
10623 static int bnx2x_do_flr(struct bnx2x *bp)
10624 {
10625         struct pci_dev *dev = bp->pdev;
10626
10627         if (CHIP_IS_E1x(bp)) {
10628                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10629                 return -EINVAL;
10630         }
10631
10632         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10633         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10634                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10635                           bp->common.bc_ver);
10636                 return -EINVAL;
10637         }
10638
10639         if (!pci_wait_for_pending_transaction(dev))
10640                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10641
10642         BNX2X_DEV_INFO("Initiating FLR\n");
10643         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10644
10645         return 0;
10646 }
10647
10648 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10649 {
10650         int rc;
10651
10652         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10653
10654         /* Test if previous unload process was already finished for this path */
10655         if (bnx2x_prev_is_path_marked(bp))
10656                 return bnx2x_prev_mcp_done(bp);
10657
10658         BNX2X_DEV_INFO("Path is unmarked\n");
10659
10660         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10661         if (bnx2x_prev_is_after_undi(bp))
10662                 goto out;
10663
10664         /* If function has FLR capabilities, and existing FW version matches
10665          * the one required, then FLR will be sufficient to clean any residue
10666          * left by previous driver
10667          */
10668         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10669
10670         if (!rc) {
10671                 /* fw version is good */
10672                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10673                 rc = bnx2x_do_flr(bp);
10674         }
10675
10676         if (!rc) {
10677                 /* FLR was performed */
10678                 BNX2X_DEV_INFO("FLR successful\n");
10679                 return 0;
10680         }
10681
10682         BNX2X_DEV_INFO("Could not FLR\n");
10683
10684 out:
10685         /* Close the MCP request, return failure*/
10686         rc = bnx2x_prev_mcp_done(bp);
10687         if (!rc)
10688                 rc = BNX2X_PREV_WAIT_NEEDED;
10689
10690         return rc;
10691 }
10692
10693 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10694 {
10695         u32 reset_reg, tmp_reg = 0, rc;
10696         bool prev_undi = false;
10697         struct bnx2x_mac_vals mac_vals;
10698
10699         /* It is possible a previous function received 'common' answer,
10700          * but hasn't loaded yet, therefore creating a scenario of
10701          * multiple functions receiving 'common' on the same path.
10702          */
10703         BNX2X_DEV_INFO("Common unload Flow\n");
10704
10705         memset(&mac_vals, 0, sizeof(mac_vals));
10706
10707         if (bnx2x_prev_is_path_marked(bp))
10708                 return bnx2x_prev_mcp_done(bp);
10709
10710         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10711
10712         /* Reset should be performed after BRB is emptied */
10713         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10714                 u32 timer_count = 1000;
10715
10716                 /* Close the MAC Rx to prevent BRB from filling up */
10717                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10718
10719                 /* close LLH filters for both ports towards the BRB */
10720                 bnx2x_set_rx_filter(&bp->link_params, 0);
10721                 bp->link_params.port ^= 1;
10722                 bnx2x_set_rx_filter(&bp->link_params, 0);
10723                 bp->link_params.port ^= 1;
10724
10725                 /* Check if the UNDI driver was previously loaded */
10726                 if (bnx2x_prev_is_after_undi(bp)) {
10727                         prev_undi = true;
10728                         /* clear the UNDI indication */
10729                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10730                         /* clear possible idle check errors */
10731                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10732                 }
10733                 if (!CHIP_IS_E1x(bp))
10734                         /* block FW from writing to host */
10735                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10736
10737                 /* wait until BRB is empty */
10738                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10739                 while (timer_count) {
10740                         u32 prev_brb = tmp_reg;
10741
10742                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10743                         if (!tmp_reg)
10744                                 break;
10745
10746                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10747
10748                         /* reset timer as long as BRB actually gets emptied */
10749                         if (prev_brb > tmp_reg)
10750                                 timer_count = 1000;
10751                         else
10752                                 timer_count--;
10753
10754                         /* If UNDI resides in memory, manually increment it */
10755                         if (prev_undi)
10756                                 bnx2x_prev_unload_undi_inc(bp, 1);
10757
10758                         udelay(10);
10759                 }
10760
10761                 if (!timer_count)
10762                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10763         }
10764
10765         /* No packets are in the pipeline, path is ready for reset */
10766         bnx2x_reset_common(bp);
10767
10768         if (mac_vals.xmac_addr)
10769                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10770         if (mac_vals.umac_addr[0])
10771                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10772         if (mac_vals.umac_addr[1])
10773                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10774         if (mac_vals.emac_addr)
10775                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10776         if (mac_vals.bmac_addr) {
10777                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10778                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10779         }
10780
10781         rc = bnx2x_prev_mark_path(bp, prev_undi);
10782         if (rc) {
10783                 bnx2x_prev_mcp_done(bp);
10784                 return rc;
10785         }
10786
10787         return bnx2x_prev_mcp_done(bp);
10788 }
10789
10790 static int bnx2x_prev_unload(struct bnx2x *bp)
10791 {
10792         int time_counter = 10;
10793         u32 rc, fw, hw_lock_reg, hw_lock_val;
10794         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10795
10796         /* clear hw from errors which may have resulted from an interrupted
10797          * dmae transaction.
10798          */
10799         bnx2x_clean_pglue_errors(bp);
10800
10801         /* Release previously held locks */
10802         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10803                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10804                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10805
10806         hw_lock_val = REG_RD(bp, hw_lock_reg);
10807         if (hw_lock_val) {
10808                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10809                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10810                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10811                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10812                 }
10813
10814                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10815                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10816         } else
10817                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10818
10819         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10820                 BNX2X_DEV_INFO("Release previously held alr\n");
10821                 bnx2x_release_alr(bp);
10822         }
10823
10824         do {
10825                 int aer = 0;
10826                 /* Lock MCP using an unload request */
10827                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10828                 if (!fw) {
10829                         BNX2X_ERR("MCP response failure, aborting\n");
10830                         rc = -EBUSY;
10831                         break;
10832                 }
10833
10834                 rc = down_interruptible(&bnx2x_prev_sem);
10835                 if (rc) {
10836                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10837                                   rc);
10838                 } else {
10839                         /* If Path is marked by EEH, ignore unload status */
10840                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10841                                  bnx2x_prev_path_get_entry(bp)->aer);
10842                         up(&bnx2x_prev_sem);
10843                 }
10844
10845                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10846                         rc = bnx2x_prev_unload_common(bp);
10847                         break;
10848                 }
10849
10850                 /* non-common reply from MCP might require looping */
10851                 rc = bnx2x_prev_unload_uncommon(bp);
10852                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10853                         break;
10854
10855                 msleep(20);
10856         } while (--time_counter);
10857
10858         if (!time_counter || rc) {
10859                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10860                 rc = -EPROBE_DEFER;
10861         }
10862
10863         /* Mark function if its port was used to boot from SAN */
10864         if (bnx2x_port_after_undi(bp))
10865                 bp->link_params.feature_config_flags |=
10866                         FEATURE_CONFIG_BOOT_FROM_SAN;
10867
10868         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10869
10870         return rc;
10871 }
10872
10873 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10874 {
10875         u32 val, val2, val3, val4, id, boot_mode;
10876         u16 pmc;
10877
10878         /* Get the chip revision id and number. */
10879         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10880         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10881         id = ((val & 0xffff) << 16);
10882         val = REG_RD(bp, MISC_REG_CHIP_REV);
10883         id |= ((val & 0xf) << 12);
10884
10885         /* Metal is read from PCI regs, but we can't access >=0x400 from
10886          * the configuration space (so we need to reg_rd)
10887          */
10888         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10889         id |= (((val >> 24) & 0xf) << 4);
10890         val = REG_RD(bp, MISC_REG_BOND_ID);
10891         id |= (val & 0xf);
10892         bp->common.chip_id = id;
10893
10894         /* force 57811 according to MISC register */
10895         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10896                 if (CHIP_IS_57810(bp))
10897                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10898                                 (bp->common.chip_id & 0x0000FFFF);
10899                 else if (CHIP_IS_57810_MF(bp))
10900                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10901                                 (bp->common.chip_id & 0x0000FFFF);
10902                 bp->common.chip_id |= 0x1;
10903         }
10904
10905         /* Set doorbell size */
10906         bp->db_size = (1 << BNX2X_DB_SHIFT);
10907
10908         if (!CHIP_IS_E1x(bp)) {
10909                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10910                 if ((val & 1) == 0)
10911                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10912                 else
10913                         val = (val >> 1) & 1;
10914                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10915                                                        "2_PORT_MODE");
10916                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10917                                                  CHIP_2_PORT_MODE;
10918
10919                 if (CHIP_MODE_IS_4_PORT(bp))
10920                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10921                 else
10922                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10923         } else {
10924                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10925                 bp->pfid = bp->pf_num;                  /* 0..7 */
10926         }
10927
10928         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10929
10930         bp->link_params.chip_id = bp->common.chip_id;
10931         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10932
10933         val = (REG_RD(bp, 0x2874) & 0x55);
10934         if ((bp->common.chip_id & 0x1) ||
10935             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10936                 bp->flags |= ONE_PORT_FLAG;
10937                 BNX2X_DEV_INFO("single port device\n");
10938         }
10939
10940         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10941         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10942                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10943         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10944                        bp->common.flash_size, bp->common.flash_size);
10945
10946         bnx2x_init_shmem(bp);
10947
10948         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10949                                         MISC_REG_GENERIC_CR_1 :
10950                                         MISC_REG_GENERIC_CR_0));
10951
10952         bp->link_params.shmem_base = bp->common.shmem_base;
10953         bp->link_params.shmem2_base = bp->common.shmem2_base;
10954         if (SHMEM2_RD(bp, size) >
10955             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10956                 bp->link_params.lfa_base =
10957                 REG_RD(bp, bp->common.shmem2_base +
10958                        (u32)offsetof(struct shmem2_region,
10959                                      lfa_host_addr[BP_PORT(bp)]));
10960         else
10961                 bp->link_params.lfa_base = 0;
10962         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10963                        bp->common.shmem_base, bp->common.shmem2_base);
10964
10965         if (!bp->common.shmem_base) {
10966                 BNX2X_DEV_INFO("MCP not active\n");
10967                 bp->flags |= NO_MCP_FLAG;
10968                 return;
10969         }
10970
10971         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10972         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10973
10974         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10975                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10976                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10977
10978         bp->link_params.feature_config_flags = 0;
10979         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10980         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10981                 bp->link_params.feature_config_flags |=
10982                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10983         else
10984                 bp->link_params.feature_config_flags &=
10985                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10986
10987         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10988         bp->common.bc_ver = val;
10989         BNX2X_DEV_INFO("bc_ver %X\n", val);
10990         if (val < BNX2X_BC_VER) {
10991                 /* for now only warn
10992                  * later we might need to enforce this */
10993                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10994                           BNX2X_BC_VER, val);
10995         }
10996         bp->link_params.feature_config_flags |=
10997                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10998                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10999
11000         bp->link_params.feature_config_flags |=
11001                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11002                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11003         bp->link_params.feature_config_flags |=
11004                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11005                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11006         bp->link_params.feature_config_flags |=
11007                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11008                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11009
11010         bp->link_params.feature_config_flags |=
11011                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11012                 FEATURE_CONFIG_MT_SUPPORT : 0;
11013
11014         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11015                         BC_SUPPORTS_PFC_STATS : 0;
11016
11017         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11018                         BC_SUPPORTS_FCOE_FEATURES : 0;
11019
11020         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11021                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11022
11023         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11024                         BC_SUPPORTS_RMMOD_CMD : 0;
11025
11026         boot_mode = SHMEM_RD(bp,
11027                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11028                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11029         switch (boot_mode) {
11030         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11031                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11032                 break;
11033         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11034                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11035                 break;
11036         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11037                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11038                 break;
11039         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11040                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11041                 break;
11042         }
11043
11044         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11045         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11046
11047         BNX2X_DEV_INFO("%sWoL capable\n",
11048                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11049
11050         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11051         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11052         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11053         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11054
11055         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11056                  val, val2, val3, val4);
11057 }
11058
11059 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11060 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11061
11062 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11063 {
11064         int pfid = BP_FUNC(bp);
11065         int igu_sb_id;
11066         u32 val;
11067         u8 fid, igu_sb_cnt = 0;
11068
11069         bp->igu_base_sb = 0xff;
11070         if (CHIP_INT_MODE_IS_BC(bp)) {
11071                 int vn = BP_VN(bp);
11072                 igu_sb_cnt = bp->igu_sb_cnt;
11073                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11074                         FP_SB_MAX_E1x;
11075
11076                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11077                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11078
11079                 return 0;
11080         }
11081
11082         /* IGU in normal mode - read CAM */
11083         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11084              igu_sb_id++) {
11085                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11086                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11087                         continue;
11088                 fid = IGU_FID(val);
11089                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11090                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11091                                 continue;
11092                         if (IGU_VEC(val) == 0)
11093                                 /* default status block */
11094                                 bp->igu_dsb_id = igu_sb_id;
11095                         else {
11096                                 if (bp->igu_base_sb == 0xff)
11097                                         bp->igu_base_sb = igu_sb_id;
11098                                 igu_sb_cnt++;
11099                         }
11100                 }
11101         }
11102
11103 #ifdef CONFIG_PCI_MSI
11104         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11105          * optional that number of CAM entries will not be equal to the value
11106          * advertised in PCI.
11107          * Driver should use the minimal value of both as the actual status
11108          * block count
11109          */
11110         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11111 #endif
11112
11113         if (igu_sb_cnt == 0) {
11114                 BNX2X_ERR("CAM configuration error\n");
11115                 return -EINVAL;
11116         }
11117
11118         return 0;
11119 }
11120
11121 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11122 {
11123         int cfg_size = 0, idx, port = BP_PORT(bp);
11124
11125         /* Aggregation of supported attributes of all external phys */
11126         bp->port.supported[0] = 0;
11127         bp->port.supported[1] = 0;
11128         switch (bp->link_params.num_phys) {
11129         case 1:
11130                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11131                 cfg_size = 1;
11132                 break;
11133         case 2:
11134                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11135                 cfg_size = 1;
11136                 break;
11137         case 3:
11138                 if (bp->link_params.multi_phy_config &
11139                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11140                         bp->port.supported[1] =
11141                                 bp->link_params.phy[EXT_PHY1].supported;
11142                         bp->port.supported[0] =
11143                                 bp->link_params.phy[EXT_PHY2].supported;
11144                 } else {
11145                         bp->port.supported[0] =
11146                                 bp->link_params.phy[EXT_PHY1].supported;
11147                         bp->port.supported[1] =
11148                                 bp->link_params.phy[EXT_PHY2].supported;
11149                 }
11150                 cfg_size = 2;
11151                 break;
11152         }
11153
11154         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11155                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11156                            SHMEM_RD(bp,
11157                            dev_info.port_hw_config[port].external_phy_config),
11158                            SHMEM_RD(bp,
11159                            dev_info.port_hw_config[port].external_phy_config2));
11160                         return;
11161         }
11162
11163         if (CHIP_IS_E3(bp))
11164                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11165         else {
11166                 switch (switch_cfg) {
11167                 case SWITCH_CFG_1G:
11168                         bp->port.phy_addr = REG_RD(
11169                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11170                         break;
11171                 case SWITCH_CFG_10G:
11172                         bp->port.phy_addr = REG_RD(
11173                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11174                         break;
11175                 default:
11176                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11177                                   bp->port.link_config[0]);
11178                         return;
11179                 }
11180         }
11181         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11182         /* mask what we support according to speed_cap_mask per configuration */
11183         for (idx = 0; idx < cfg_size; idx++) {
11184                 if (!(bp->link_params.speed_cap_mask[idx] &
11185                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11186                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11187
11188                 if (!(bp->link_params.speed_cap_mask[idx] &
11189                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11190                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11191
11192                 if (!(bp->link_params.speed_cap_mask[idx] &
11193                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11194                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11195
11196                 if (!(bp->link_params.speed_cap_mask[idx] &
11197                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11198                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11199
11200                 if (!(bp->link_params.speed_cap_mask[idx] &
11201                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11202                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11203                                                      SUPPORTED_1000baseT_Full);
11204
11205                 if (!(bp->link_params.speed_cap_mask[idx] &
11206                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11207                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11208
11209                 if (!(bp->link_params.speed_cap_mask[idx] &
11210                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11211                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11212
11213                 if (!(bp->link_params.speed_cap_mask[idx] &
11214                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11215                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11216         }
11217
11218         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11219                        bp->port.supported[1]);
11220 }
11221
11222 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11223 {
11224         u32 link_config, idx, cfg_size = 0;
11225         bp->port.advertising[0] = 0;
11226         bp->port.advertising[1] = 0;
11227         switch (bp->link_params.num_phys) {
11228         case 1:
11229         case 2:
11230                 cfg_size = 1;
11231                 break;
11232         case 3:
11233                 cfg_size = 2;
11234                 break;
11235         }
11236         for (idx = 0; idx < cfg_size; idx++) {
11237                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11238                 link_config = bp->port.link_config[idx];
11239                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11240                 case PORT_FEATURE_LINK_SPEED_AUTO:
11241                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11242                                 bp->link_params.req_line_speed[idx] =
11243                                         SPEED_AUTO_NEG;
11244                                 bp->port.advertising[idx] |=
11245                                         bp->port.supported[idx];
11246                                 if (bp->link_params.phy[EXT_PHY1].type ==
11247                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11248                                         bp->port.advertising[idx] |=
11249                                         (SUPPORTED_100baseT_Half |
11250                                          SUPPORTED_100baseT_Full);
11251                         } else {
11252                                 /* force 10G, no AN */
11253                                 bp->link_params.req_line_speed[idx] =
11254                                         SPEED_10000;
11255                                 bp->port.advertising[idx] |=
11256                                         (ADVERTISED_10000baseT_Full |
11257                                          ADVERTISED_FIBRE);
11258                                 continue;
11259                         }
11260                         break;
11261
11262                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11263                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11264                                 bp->link_params.req_line_speed[idx] =
11265                                         SPEED_10;
11266                                 bp->port.advertising[idx] |=
11267                                         (ADVERTISED_10baseT_Full |
11268                                          ADVERTISED_TP);
11269                         } else {
11270                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11271                                             link_config,
11272                                     bp->link_params.speed_cap_mask[idx]);
11273                                 return;
11274                         }
11275                         break;
11276
11277                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11278                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11279                                 bp->link_params.req_line_speed[idx] =
11280                                         SPEED_10;
11281                                 bp->link_params.req_duplex[idx] =
11282                                         DUPLEX_HALF;
11283                                 bp->port.advertising[idx] |=
11284                                         (ADVERTISED_10baseT_Half |
11285                                          ADVERTISED_TP);
11286                         } else {
11287                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11288                                             link_config,
11289                                           bp->link_params.speed_cap_mask[idx]);
11290                                 return;
11291                         }
11292                         break;
11293
11294                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11295                         if (bp->port.supported[idx] &
11296                             SUPPORTED_100baseT_Full) {
11297                                 bp->link_params.req_line_speed[idx] =
11298                                         SPEED_100;
11299                                 bp->port.advertising[idx] |=
11300                                         (ADVERTISED_100baseT_Full |
11301                                          ADVERTISED_TP);
11302                         } else {
11303                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11304                                             link_config,
11305                                           bp->link_params.speed_cap_mask[idx]);
11306                                 return;
11307                         }
11308                         break;
11309
11310                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11311                         if (bp->port.supported[idx] &
11312                             SUPPORTED_100baseT_Half) {
11313                                 bp->link_params.req_line_speed[idx] =
11314                                                                 SPEED_100;
11315                                 bp->link_params.req_duplex[idx] =
11316                                                                 DUPLEX_HALF;
11317                                 bp->port.advertising[idx] |=
11318                                         (ADVERTISED_100baseT_Half |
11319                                          ADVERTISED_TP);
11320                         } else {
11321                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11322                                     link_config,
11323                                     bp->link_params.speed_cap_mask[idx]);
11324                                 return;
11325                         }
11326                         break;
11327
11328                 case PORT_FEATURE_LINK_SPEED_1G:
11329                         if (bp->port.supported[idx] &
11330                             SUPPORTED_1000baseT_Full) {
11331                                 bp->link_params.req_line_speed[idx] =
11332                                         SPEED_1000;
11333                                 bp->port.advertising[idx] |=
11334                                         (ADVERTISED_1000baseT_Full |
11335                                          ADVERTISED_TP);
11336                         } else if (bp->port.supported[idx] &
11337                                    SUPPORTED_1000baseKX_Full) {
11338                                 bp->link_params.req_line_speed[idx] =
11339                                         SPEED_1000;
11340                                 bp->port.advertising[idx] |=
11341                                         ADVERTISED_1000baseKX_Full;
11342                         } else {
11343                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11344                                     link_config,
11345                                     bp->link_params.speed_cap_mask[idx]);
11346                                 return;
11347                         }
11348                         break;
11349
11350                 case PORT_FEATURE_LINK_SPEED_2_5G:
11351                         if (bp->port.supported[idx] &
11352                             SUPPORTED_2500baseX_Full) {
11353                                 bp->link_params.req_line_speed[idx] =
11354                                         SPEED_2500;
11355                                 bp->port.advertising[idx] |=
11356                                         (ADVERTISED_2500baseX_Full |
11357                                                 ADVERTISED_TP);
11358                         } else {
11359                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11360                                     link_config,
11361                                     bp->link_params.speed_cap_mask[idx]);
11362                                 return;
11363                         }
11364                         break;
11365
11366                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11367                         if (bp->port.supported[idx] &
11368                             SUPPORTED_10000baseT_Full) {
11369                                 bp->link_params.req_line_speed[idx] =
11370                                         SPEED_10000;
11371                                 bp->port.advertising[idx] |=
11372                                         (ADVERTISED_10000baseT_Full |
11373                                                 ADVERTISED_FIBRE);
11374                         } else if (bp->port.supported[idx] &
11375                                    SUPPORTED_10000baseKR_Full) {
11376                                 bp->link_params.req_line_speed[idx] =
11377                                         SPEED_10000;
11378                                 bp->port.advertising[idx] |=
11379                                         (ADVERTISED_10000baseKR_Full |
11380                                                 ADVERTISED_FIBRE);
11381                         } else {
11382                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11383                                     link_config,
11384                                     bp->link_params.speed_cap_mask[idx]);
11385                                 return;
11386                         }
11387                         break;
11388                 case PORT_FEATURE_LINK_SPEED_20G:
11389                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11390
11391                         break;
11392                 default:
11393                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11394                                   link_config);
11395                                 bp->link_params.req_line_speed[idx] =
11396                                                         SPEED_AUTO_NEG;
11397                                 bp->port.advertising[idx] =
11398                                                 bp->port.supported[idx];
11399                         break;
11400                 }
11401
11402                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11403                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11404                 if (bp->link_params.req_flow_ctrl[idx] ==
11405                     BNX2X_FLOW_CTRL_AUTO) {
11406                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11407                                 bp->link_params.req_flow_ctrl[idx] =
11408                                                         BNX2X_FLOW_CTRL_NONE;
11409                         else
11410                                 bnx2x_set_requested_fc(bp);
11411                 }
11412
11413                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11414                                bp->link_params.req_line_speed[idx],
11415                                bp->link_params.req_duplex[idx],
11416                                bp->link_params.req_flow_ctrl[idx],
11417                                bp->port.advertising[idx]);
11418         }
11419 }
11420
11421 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11422 {
11423         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11424         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11425         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11426         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11427 }
11428
11429 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11430 {
11431         int port = BP_PORT(bp);
11432         u32 config;
11433         u32 ext_phy_type, ext_phy_config, eee_mode;
11434
11435         bp->link_params.bp = bp;
11436         bp->link_params.port = port;
11437
11438         bp->link_params.lane_config =
11439                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11440
11441         bp->link_params.speed_cap_mask[0] =
11442                 SHMEM_RD(bp,
11443                          dev_info.port_hw_config[port].speed_capability_mask) &
11444                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11445         bp->link_params.speed_cap_mask[1] =
11446                 SHMEM_RD(bp,
11447                          dev_info.port_hw_config[port].speed_capability_mask2) &
11448                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11449         bp->port.link_config[0] =
11450                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11451
11452         bp->port.link_config[1] =
11453                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11454
11455         bp->link_params.multi_phy_config =
11456                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11457         /* If the device is capable of WoL, set the default state according
11458          * to the HW
11459          */
11460         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11461         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11462                    (config & PORT_FEATURE_WOL_ENABLED));
11463
11464         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11465             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11466                 bp->flags |= NO_ISCSI_FLAG;
11467         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11468             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11469                 bp->flags |= NO_FCOE_FLAG;
11470
11471         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11472                        bp->link_params.lane_config,
11473                        bp->link_params.speed_cap_mask[0],
11474                        bp->port.link_config[0]);
11475
11476         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11477                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11478         bnx2x_phy_probe(&bp->link_params);
11479         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11480
11481         bnx2x_link_settings_requested(bp);
11482
11483         /*
11484          * If connected directly, work with the internal PHY, otherwise, work
11485          * with the external PHY
11486          */
11487         ext_phy_config =
11488                 SHMEM_RD(bp,
11489                          dev_info.port_hw_config[port].external_phy_config);
11490         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11491         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11492                 bp->mdio.prtad = bp->port.phy_addr;
11493
11494         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11495                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11496                 bp->mdio.prtad =
11497                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11498
11499         /* Configure link feature according to nvram value */
11500         eee_mode = (((SHMEM_RD(bp, dev_info.
11501                       port_feature_config[port].eee_power_mode)) &
11502                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11503                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11504         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11505                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11506                                            EEE_MODE_ENABLE_LPI |
11507                                            EEE_MODE_OUTPUT_TIME;
11508         } else {
11509                 bp->link_params.eee_mode = 0;
11510         }
11511 }
11512
11513 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11514 {
11515         u32 no_flags = NO_ISCSI_FLAG;
11516         int port = BP_PORT(bp);
11517         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11518                                 drv_lic_key[port].max_iscsi_conn);
11519
11520         if (!CNIC_SUPPORT(bp)) {
11521                 bp->flags |= no_flags;
11522                 return;
11523         }
11524
11525         /* Get the number of maximum allowed iSCSI connections */
11526         bp->cnic_eth_dev.max_iscsi_conn =
11527                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11528                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11529
11530         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11531                        bp->cnic_eth_dev.max_iscsi_conn);
11532
11533         /*
11534          * If maximum allowed number of connections is zero -
11535          * disable the feature.
11536          */
11537         if (!bp->cnic_eth_dev.max_iscsi_conn)
11538                 bp->flags |= no_flags;
11539 }
11540
11541 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11542 {
11543         /* Port info */
11544         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11545                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11546         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11547                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11548
11549         /* Node info */
11550         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11551                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11552         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11553                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11554 }
11555
11556 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11557 {
11558         u8 count = 0;
11559
11560         if (IS_MF(bp)) {
11561                 u8 fid;
11562
11563                 /* iterate over absolute function ids for this path: */
11564                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11565                         if (IS_MF_SD(bp)) {
11566                                 u32 cfg = MF_CFG_RD(bp,
11567                                                     func_mf_config[fid].config);
11568
11569                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11570                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11571                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11572                                         count++;
11573                         } else {
11574                                 u32 cfg = MF_CFG_RD(bp,
11575                                                     func_ext_config[fid].
11576                                                                       func_cfg);
11577
11578                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11579                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11580                                         count++;
11581                         }
11582                 }
11583         } else { /* SF */
11584                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11585
11586                 for (port = 0; port < port_cnt; port++) {
11587                         u32 lic = SHMEM_RD(bp,
11588                                            drv_lic_key[port].max_fcoe_conn) ^
11589                                   FW_ENCODE_32BIT_PATTERN;
11590                         if (lic)
11591                                 count++;
11592                 }
11593         }
11594
11595         return count;
11596 }
11597
11598 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11599 {
11600         int port = BP_PORT(bp);
11601         int func = BP_ABS_FUNC(bp);
11602         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11603                                 drv_lic_key[port].max_fcoe_conn);
11604         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11605
11606         if (!CNIC_SUPPORT(bp)) {
11607                 bp->flags |= NO_FCOE_FLAG;
11608                 return;
11609         }
11610
11611         /* Get the number of maximum allowed FCoE connections */
11612         bp->cnic_eth_dev.max_fcoe_conn =
11613                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11614                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11615
11616         /* Calculate the number of maximum allowed FCoE tasks */
11617         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11618
11619         /* check if FCoE resources must be shared between different functions */
11620         if (num_fcoe_func)
11621                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11622
11623         /* Read the WWN: */
11624         if (!IS_MF(bp)) {
11625                 /* Port info */
11626                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11627                         SHMEM_RD(bp,
11628                                  dev_info.port_hw_config[port].
11629                                  fcoe_wwn_port_name_upper);
11630                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11631                         SHMEM_RD(bp,
11632                                  dev_info.port_hw_config[port].
11633                                  fcoe_wwn_port_name_lower);
11634
11635                 /* Node info */
11636                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11637                         SHMEM_RD(bp,
11638                                  dev_info.port_hw_config[port].
11639                                  fcoe_wwn_node_name_upper);
11640                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11641                         SHMEM_RD(bp,
11642                                  dev_info.port_hw_config[port].
11643                                  fcoe_wwn_node_name_lower);
11644         } else if (!IS_MF_SD(bp)) {
11645                 /* Read the WWN info only if the FCoE feature is enabled for
11646                  * this function.
11647                  */
11648                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11649                         bnx2x_get_ext_wwn_info(bp, func);
11650         } else {
11651                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11652                         bnx2x_get_ext_wwn_info(bp, func);
11653         }
11654
11655         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11656
11657         /*
11658          * If maximum allowed number of connections is zero -
11659          * disable the feature.
11660          */
11661         if (!bp->cnic_eth_dev.max_fcoe_conn)
11662                 bp->flags |= NO_FCOE_FLAG;
11663 }
11664
11665 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11666 {
11667         /*
11668          * iSCSI may be dynamically disabled but reading
11669          * info here we will decrease memory usage by driver
11670          * if the feature is disabled for good
11671          */
11672         bnx2x_get_iscsi_info(bp);
11673         bnx2x_get_fcoe_info(bp);
11674 }
11675
11676 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11677 {
11678         u32 val, val2;
11679         int func = BP_ABS_FUNC(bp);
11680         int port = BP_PORT(bp);
11681         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11682         u8 *fip_mac = bp->fip_mac;
11683
11684         if (IS_MF(bp)) {
11685                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11686                  * FCoE MAC then the appropriate feature should be disabled.
11687                  * In non SD mode features configuration comes from struct
11688                  * func_ext_config.
11689                  */
11690                 if (!IS_MF_SD(bp)) {
11691                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11692                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11693                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11694                                                  iscsi_mac_addr_upper);
11695                                 val = MF_CFG_RD(bp, func_ext_config[func].
11696                                                 iscsi_mac_addr_lower);
11697                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11698                                 BNX2X_DEV_INFO
11699                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11700                         } else {
11701                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11702                         }
11703
11704                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11705                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11706                                                  fcoe_mac_addr_upper);
11707                                 val = MF_CFG_RD(bp, func_ext_config[func].
11708                                                 fcoe_mac_addr_lower);
11709                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11710                                 BNX2X_DEV_INFO
11711                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11712                         } else {
11713                                 bp->flags |= NO_FCOE_FLAG;
11714                         }
11715
11716                         bp->mf_ext_config = cfg;
11717
11718                 } else { /* SD MODE */
11719                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11720                                 /* use primary mac as iscsi mac */
11721                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11722
11723                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11724                                 BNX2X_DEV_INFO
11725                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11726                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11727                                 /* use primary mac as fip mac */
11728                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11729                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11730                                 BNX2X_DEV_INFO
11731                                         ("Read FIP MAC: %pM\n", fip_mac);
11732                         }
11733                 }
11734
11735                 /* If this is a storage-only interface, use SAN mac as
11736                  * primary MAC. Notice that for SD this is already the case,
11737                  * as the SAN mac was copied from the primary MAC.
11738                  */
11739                 if (IS_MF_FCOE_AFEX(bp))
11740                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11741         } else {
11742                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11743                                 iscsi_mac_upper);
11744                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11745                                iscsi_mac_lower);
11746                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11747
11748                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11749                                 fcoe_fip_mac_upper);
11750                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11751                                fcoe_fip_mac_lower);
11752                 bnx2x_set_mac_buf(fip_mac, val, val2);
11753         }
11754
11755         /* Disable iSCSI OOO if MAC configuration is invalid. */
11756         if (!is_valid_ether_addr(iscsi_mac)) {
11757                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11758                 eth_zero_addr(iscsi_mac);
11759         }
11760
11761         /* Disable FCoE if MAC configuration is invalid. */
11762         if (!is_valid_ether_addr(fip_mac)) {
11763                 bp->flags |= NO_FCOE_FLAG;
11764                 eth_zero_addr(bp->fip_mac);
11765         }
11766 }
11767
11768 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11769 {
11770         u32 val, val2;
11771         int func = BP_ABS_FUNC(bp);
11772         int port = BP_PORT(bp);
11773
11774         /* Zero primary MAC configuration */
11775         eth_zero_addr(bp->dev->dev_addr);
11776
11777         if (BP_NOMCP(bp)) {
11778                 BNX2X_ERROR("warning: random MAC workaround active\n");
11779                 eth_hw_addr_random(bp->dev);
11780         } else if (IS_MF(bp)) {
11781                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11782                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11783                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11784                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11785                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11786
11787                 if (CNIC_SUPPORT(bp))
11788                         bnx2x_get_cnic_mac_hwinfo(bp);
11789         } else {
11790                 /* in SF read MACs from port configuration */
11791                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11792                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11793                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11794
11795                 if (CNIC_SUPPORT(bp))
11796                         bnx2x_get_cnic_mac_hwinfo(bp);
11797         }
11798
11799         if (!BP_NOMCP(bp)) {
11800                 /* Read physical port identifier from shmem */
11801                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11802                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11803                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11804                 bp->flags |= HAS_PHYS_PORT_ID;
11805         }
11806
11807         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11808
11809         if (!is_valid_ether_addr(bp->dev->dev_addr))
11810                 dev_err(&bp->pdev->dev,
11811                         "bad Ethernet MAC address configuration: %pM\n"
11812                         "change it manually before bringing up the appropriate network interface\n",
11813                         bp->dev->dev_addr);
11814 }
11815
11816 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11817 {
11818         int tmp;
11819         u32 cfg;
11820
11821         if (IS_VF(bp))
11822                 return false;
11823
11824         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11825                 /* Take function: tmp = func */
11826                 tmp = BP_ABS_FUNC(bp);
11827                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11828                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11829         } else {
11830                 /* Take port: tmp = port */
11831                 tmp = BP_PORT(bp);
11832                 cfg = SHMEM_RD(bp,
11833                                dev_info.port_hw_config[tmp].generic_features);
11834                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11835         }
11836         return cfg;
11837 }
11838
11839 static void validate_set_si_mode(struct bnx2x *bp)
11840 {
11841         u8 func = BP_ABS_FUNC(bp);
11842         u32 val;
11843
11844         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11845
11846         /* check for legal mac (upper bytes) */
11847         if (val != 0xffff) {
11848                 bp->mf_mode = MULTI_FUNCTION_SI;
11849                 bp->mf_config[BP_VN(bp)] =
11850                         MF_CFG_RD(bp, func_mf_config[func].config);
11851         } else
11852                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11853 }
11854
11855 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11856 {
11857         int /*abs*/func = BP_ABS_FUNC(bp);
11858         int vn, mfw_vn;
11859         u32 val = 0, val2 = 0;
11860         int rc = 0;
11861
11862         /* Validate that chip access is feasible */
11863         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11864                 dev_err(&bp->pdev->dev,
11865                         "Chip read returns all Fs. Preventing probe from continuing\n");
11866                 return -EINVAL;
11867         }
11868
11869         bnx2x_get_common_hwinfo(bp);
11870
11871         /*
11872          * initialize IGU parameters
11873          */
11874         if (CHIP_IS_E1x(bp)) {
11875                 bp->common.int_block = INT_BLOCK_HC;
11876
11877                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11878                 bp->igu_base_sb = 0;
11879         } else {
11880                 bp->common.int_block = INT_BLOCK_IGU;
11881
11882                 /* do not allow device reset during IGU info processing */
11883                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11884
11885                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11886
11887                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11888                         int tout = 5000;
11889
11890                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11891
11892                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11893                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11894                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11895
11896                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11897                                 tout--;
11898                                 usleep_range(1000, 2000);
11899                         }
11900
11901                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11902                                 dev_err(&bp->pdev->dev,
11903                                         "FORCING Normal Mode failed!!!\n");
11904                                 bnx2x_release_hw_lock(bp,
11905                                                       HW_LOCK_RESOURCE_RESET);
11906                                 return -EPERM;
11907                         }
11908                 }
11909
11910                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11911                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11912                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11913                 } else
11914                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11915
11916                 rc = bnx2x_get_igu_cam_info(bp);
11917                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11918                 if (rc)
11919                         return rc;
11920         }
11921
11922         /*
11923          * set base FW non-default (fast path) status block id, this value is
11924          * used to initialize the fw_sb_id saved on the fp/queue structure to
11925          * determine the id used by the FW.
11926          */
11927         if (CHIP_IS_E1x(bp))
11928                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11929         else /*
11930               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11931               * the same queue are indicated on the same IGU SB). So we prefer
11932               * FW and IGU SBs to be the same value.
11933               */
11934                 bp->base_fw_ndsb = bp->igu_base_sb;
11935
11936         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11937                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11938                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11939
11940         /*
11941          * Initialize MF configuration
11942          */
11943
11944         bp->mf_ov = 0;
11945         bp->mf_mode = 0;
11946         bp->mf_sub_mode = 0;
11947         vn = BP_VN(bp);
11948         mfw_vn = BP_FW_MB_IDX(bp);
11949
11950         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11951                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11952                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11953                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11954
11955                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11956                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11957                 else
11958                         bp->common.mf_cfg_base = bp->common.shmem_base +
11959                                 offsetof(struct shmem_region, func_mb) +
11960                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11961                 /*
11962                  * get mf configuration:
11963                  * 1. Existence of MF configuration
11964                  * 2. MAC address must be legal (check only upper bytes)
11965                  *    for  Switch-Independent mode;
11966                  *    OVLAN must be legal for Switch-Dependent mode
11967                  * 3. SF_MODE configures specific MF mode
11968                  */
11969                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11970                         /* get mf configuration */
11971                         val = SHMEM_RD(bp,
11972                                        dev_info.shared_feature_config.config);
11973                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11974
11975                         switch (val) {
11976                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11977                                 validate_set_si_mode(bp);
11978                                 break;
11979                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11980                                 if ((!CHIP_IS_E1x(bp)) &&
11981                                     (MF_CFG_RD(bp, func_mf_config[func].
11982                                                mac_upper) != 0xffff) &&
11983                                     (SHMEM2_HAS(bp,
11984                                                 afex_driver_support))) {
11985                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11986                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11987                                                 func_mf_config[func].config);
11988                                 } else {
11989                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11990                                 }
11991                                 break;
11992                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11993                                 /* get OV configuration */
11994                                 val = MF_CFG_RD(bp,
11995                                         func_mf_config[FUNC_0].e1hov_tag);
11996                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11997
11998                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11999                                         bp->mf_mode = MULTI_FUNCTION_SD;
12000                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12001                                                 func_mf_config[func].config);
12002                                 } else
12003                                         BNX2X_DEV_INFO("illegal OV for SD\n");
12004                                 break;
12005                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12006                                 bp->mf_mode = MULTI_FUNCTION_SD;
12007                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12008                                 bp->mf_config[vn] =
12009                                         MF_CFG_RD(bp,
12010                                                   func_mf_config[func].config);
12011
12012                                 if (SHMEM2_HAS(bp, mtu_size)) {
12013                                         int mtu_idx = BP_FW_MB_IDX(bp);
12014                                         u16 mtu_size;
12015                                         u32 mtu;
12016
12017                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12018                                         mtu_size = (u16)mtu;
12019                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12020                                            mtu_size, mtu);
12021
12022                                         /* if valid: update device mtu */
12023                                         if (((mtu_size + ETH_HLEN) >=
12024                                              ETH_MIN_PACKET_SIZE) &&
12025                                             (mtu_size <=
12026                                              ETH_MAX_JUMBO_PACKET_SIZE))
12027                                                 bp->dev->mtu = mtu_size;
12028                                 }
12029                                 break;
12030                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12031                                 bp->mf_mode = MULTI_FUNCTION_SD;
12032                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12033                                 bp->mf_config[vn] =
12034                                         MF_CFG_RD(bp,
12035                                                   func_mf_config[func].config);
12036                                 break;
12037                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12038                                 bp->mf_config[vn] = 0;
12039                                 break;
12040                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12041                                 val2 = SHMEM_RD(bp,
12042                                         dev_info.shared_hw_config.config_3);
12043                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12044                                 switch (val2) {
12045                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12046                                         validate_set_si_mode(bp);
12047                                         bp->mf_sub_mode =
12048                                                         SUB_MF_MODE_NPAR1_DOT_5;
12049                                         break;
12050                                 default:
12051                                         /* Unknown configuration */
12052                                         bp->mf_config[vn] = 0;
12053                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12054                                                        val);
12055                                 }
12056                                 break;
12057                         default:
12058                                 /* Unknown configuration: reset mf_config */
12059                                 bp->mf_config[vn] = 0;
12060                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12061                         }
12062                 }
12063
12064                 BNX2X_DEV_INFO("%s function mode\n",
12065                                IS_MF(bp) ? "multi" : "single");
12066
12067                 switch (bp->mf_mode) {
12068                 case MULTI_FUNCTION_SD:
12069                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12070                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12071                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12072                                 bp->mf_ov = val;
12073                                 bp->path_has_ovlan = true;
12074
12075                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12076                                                func, bp->mf_ov, bp->mf_ov);
12077                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12078                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12079                                 dev_err(&bp->pdev->dev,
12080                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12081                                         func);
12082                                 bp->path_has_ovlan = true;
12083                         } else {
12084                                 dev_err(&bp->pdev->dev,
12085                                         "No valid MF OV for func %d, aborting\n",
12086                                         func);
12087                                 return -EPERM;
12088                         }
12089                         break;
12090                 case MULTI_FUNCTION_AFEX:
12091                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12092                         break;
12093                 case MULTI_FUNCTION_SI:
12094                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12095                                        func);
12096                         break;
12097                 default:
12098                         if (vn) {
12099                                 dev_err(&bp->pdev->dev,
12100                                         "VN %d is in a single function mode, aborting\n",
12101                                         vn);
12102                                 return -EPERM;
12103                         }
12104                         break;
12105                 }
12106
12107                 /* check if other port on the path needs ovlan:
12108                  * Since MF configuration is shared between ports
12109                  * Possible mixed modes are only
12110                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12111                  */
12112                 if (CHIP_MODE_IS_4_PORT(bp) &&
12113                     !bp->path_has_ovlan &&
12114                     !IS_MF(bp) &&
12115                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12116                         u8 other_port = !BP_PORT(bp);
12117                         u8 other_func = BP_PATH(bp) + 2*other_port;
12118                         val = MF_CFG_RD(bp,
12119                                         func_mf_config[other_func].e1hov_tag);
12120                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12121                                 bp->path_has_ovlan = true;
12122                 }
12123         }
12124
12125         /* adjust igu_sb_cnt to MF for E1H */
12126         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12127                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12128
12129         /* port info */
12130         bnx2x_get_port_hwinfo(bp);
12131
12132         /* Get MAC addresses */
12133         bnx2x_get_mac_hwinfo(bp);
12134
12135         bnx2x_get_cnic_info(bp);
12136
12137         return rc;
12138 }
12139
12140 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12141 {
12142         int cnt, i, block_end, rodi;
12143         char vpd_start[BNX2X_VPD_LEN+1];
12144         char str_id_reg[VENDOR_ID_LEN+1];
12145         char str_id_cap[VENDOR_ID_LEN+1];
12146         char *vpd_data;
12147         char *vpd_extended_data = NULL;
12148         u8 len;
12149
12150         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12151         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12152
12153         if (cnt < BNX2X_VPD_LEN)
12154                 goto out_not_found;
12155
12156         /* VPD RO tag should be first tag after identifier string, hence
12157          * we should be able to find it in first BNX2X_VPD_LEN chars
12158          */
12159         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12160                              PCI_VPD_LRDT_RO_DATA);
12161         if (i < 0)
12162                 goto out_not_found;
12163
12164         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12165                     pci_vpd_lrdt_size(&vpd_start[i]);
12166
12167         i += PCI_VPD_LRDT_TAG_SIZE;
12168
12169         if (block_end > BNX2X_VPD_LEN) {
12170                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12171                 if (vpd_extended_data  == NULL)
12172                         goto out_not_found;
12173
12174                 /* read rest of vpd image into vpd_extended_data */
12175                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12176                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12177                                    block_end - BNX2X_VPD_LEN,
12178                                    vpd_extended_data + BNX2X_VPD_LEN);
12179                 if (cnt < (block_end - BNX2X_VPD_LEN))
12180                         goto out_not_found;
12181                 vpd_data = vpd_extended_data;
12182         } else
12183                 vpd_data = vpd_start;
12184
12185         /* now vpd_data holds full vpd content in both cases */
12186
12187         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12188                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12189         if (rodi < 0)
12190                 goto out_not_found;
12191
12192         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12193
12194         if (len != VENDOR_ID_LEN)
12195                 goto out_not_found;
12196
12197         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12198
12199         /* vendor specific info */
12200         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12201         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12202         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12203             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12204
12205                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12206                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12207                 if (rodi >= 0) {
12208                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12209
12210                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12211
12212                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12213                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12214                                 bp->fw_ver[len] = ' ';
12215                         }
12216                 }
12217                 kfree(vpd_extended_data);
12218                 return;
12219         }
12220 out_not_found:
12221         kfree(vpd_extended_data);
12222         return;
12223 }
12224
12225 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12226 {
12227         u32 flags = 0;
12228
12229         if (CHIP_REV_IS_FPGA(bp))
12230                 SET_FLAGS(flags, MODE_FPGA);
12231         else if (CHIP_REV_IS_EMUL(bp))
12232                 SET_FLAGS(flags, MODE_EMUL);
12233         else
12234                 SET_FLAGS(flags, MODE_ASIC);
12235
12236         if (CHIP_MODE_IS_4_PORT(bp))
12237                 SET_FLAGS(flags, MODE_PORT4);
12238         else
12239                 SET_FLAGS(flags, MODE_PORT2);
12240
12241         if (CHIP_IS_E2(bp))
12242                 SET_FLAGS(flags, MODE_E2);
12243         else if (CHIP_IS_E3(bp)) {
12244                 SET_FLAGS(flags, MODE_E3);
12245                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12246                         SET_FLAGS(flags, MODE_E3_A0);
12247                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12248                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12249         }
12250
12251         if (IS_MF(bp)) {
12252                 SET_FLAGS(flags, MODE_MF);
12253                 switch (bp->mf_mode) {
12254                 case MULTI_FUNCTION_SD:
12255                         SET_FLAGS(flags, MODE_MF_SD);
12256                         break;
12257                 case MULTI_FUNCTION_SI:
12258                         SET_FLAGS(flags, MODE_MF_SI);
12259                         break;
12260                 case MULTI_FUNCTION_AFEX:
12261                         SET_FLAGS(flags, MODE_MF_AFEX);
12262                         break;
12263                 }
12264         } else
12265                 SET_FLAGS(flags, MODE_SF);
12266
12267 #if defined(__LITTLE_ENDIAN)
12268         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12269 #else /*(__BIG_ENDIAN)*/
12270         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12271 #endif
12272         INIT_MODE_FLAGS(bp) = flags;
12273 }
12274
12275 static int bnx2x_init_bp(struct bnx2x *bp)
12276 {
12277         int func;
12278         int rc;
12279
12280         mutex_init(&bp->port.phy_mutex);
12281         mutex_init(&bp->fw_mb_mutex);
12282         mutex_init(&bp->drv_info_mutex);
12283         sema_init(&bp->stats_lock, 1);
12284         bp->drv_info_mng_owner = false;
12285         INIT_LIST_HEAD(&bp->vlan_reg);
12286
12287         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12288         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12289         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12290         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12291         if (IS_PF(bp)) {
12292                 rc = bnx2x_get_hwinfo(bp);
12293                 if (rc)
12294                         return rc;
12295         } else {
12296                 eth_zero_addr(bp->dev->dev_addr);
12297         }
12298
12299         bnx2x_set_modes_bitmap(bp);
12300
12301         rc = bnx2x_alloc_mem_bp(bp);
12302         if (rc)
12303                 return rc;
12304
12305         bnx2x_read_fwinfo(bp);
12306
12307         func = BP_FUNC(bp);
12308
12309         /* need to reset chip if undi was active */
12310         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12311                 /* init fw_seq */
12312                 bp->fw_seq =
12313                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12314                                                         DRV_MSG_SEQ_NUMBER_MASK;
12315                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12316
12317                 rc = bnx2x_prev_unload(bp);
12318                 if (rc) {
12319                         bnx2x_free_mem_bp(bp);
12320                         return rc;
12321                 }
12322         }
12323
12324         if (CHIP_REV_IS_FPGA(bp))
12325                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12326
12327         if (BP_NOMCP(bp) && (func == 0))
12328                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12329
12330         bp->disable_tpa = disable_tpa;
12331         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12332         /* Reduce memory usage in kdump environment by disabling TPA */
12333         bp->disable_tpa |= is_kdump_kernel();
12334
12335         /* Set TPA flags */
12336         if (bp->disable_tpa) {
12337                 bp->dev->hw_features &= ~NETIF_F_LRO;
12338                 bp->dev->features &= ~NETIF_F_LRO;
12339         }
12340
12341         if (CHIP_IS_E1(bp))
12342                 bp->dropless_fc = 0;
12343         else
12344                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12345
12346         bp->mrrs = mrrs;
12347
12348         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12349         if (IS_VF(bp))
12350                 bp->rx_ring_size = MAX_RX_AVAIL;
12351
12352         /* make sure that the numbers are in the right granularity */
12353         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12354         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12355
12356         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12357
12358         init_timer(&bp->timer);
12359         bp->timer.expires = jiffies + bp->current_interval;
12360         bp->timer.data = (unsigned long) bp;
12361         bp->timer.function = bnx2x_timer;
12362
12363         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12364             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12365             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12366             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12367                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12368                 bnx2x_dcbx_init_params(bp);
12369         } else {
12370                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12371         }
12372
12373         if (CHIP_IS_E1x(bp))
12374                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12375         else
12376                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12377
12378         /* multiple tx priority */
12379         if (IS_VF(bp))
12380                 bp->max_cos = 1;
12381         else if (CHIP_IS_E1x(bp))
12382                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12383         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12384                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12385         else if (CHIP_IS_E3B0(bp))
12386                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12387         else
12388                 BNX2X_ERR("unknown chip %x revision %x\n",
12389                           CHIP_NUM(bp), CHIP_REV(bp));
12390         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12391
12392         /* We need at least one default status block for slow-path events,
12393          * second status block for the L2 queue, and a third status block for
12394          * CNIC if supported.
12395          */
12396         if (IS_VF(bp))
12397                 bp->min_msix_vec_cnt = 1;
12398         else if (CNIC_SUPPORT(bp))
12399                 bp->min_msix_vec_cnt = 3;
12400         else /* PF w/o cnic */
12401                 bp->min_msix_vec_cnt = 2;
12402         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12403
12404         bp->dump_preset_idx = 1;
12405
12406         if (CHIP_IS_E3B0(bp))
12407                 bp->flags |= PTP_SUPPORTED;
12408
12409         return rc;
12410 }
12411
12412 /****************************************************************************
12413 * General service functions
12414 ****************************************************************************/
12415
12416 /*
12417  * net_device service functions
12418  */
12419
12420 /* called with rtnl_lock */
12421 static int bnx2x_open(struct net_device *dev)
12422 {
12423         struct bnx2x *bp = netdev_priv(dev);
12424         int rc;
12425
12426         bp->stats_init = true;
12427
12428         netif_carrier_off(dev);
12429
12430         bnx2x_set_power_state(bp, PCI_D0);
12431
12432         /* If parity had happen during the unload, then attentions
12433          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12434          * want the first function loaded on the current engine to
12435          * complete the recovery.
12436          * Parity recovery is only relevant for PF driver.
12437          */
12438         if (IS_PF(bp)) {
12439                 int other_engine = BP_PATH(bp) ? 0 : 1;
12440                 bool other_load_status, load_status;
12441                 bool global = false;
12442
12443                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12444                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12445                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12446                     bnx2x_chk_parity_attn(bp, &global, true)) {
12447                         do {
12448                                 /* If there are attentions and they are in a
12449                                  * global blocks, set the GLOBAL_RESET bit
12450                                  * regardless whether it will be this function
12451                                  * that will complete the recovery or not.
12452                                  */
12453                                 if (global)
12454                                         bnx2x_set_reset_global(bp);
12455
12456                                 /* Only the first function on the current
12457                                  * engine should try to recover in open. In case
12458                                  * of attentions in global blocks only the first
12459                                  * in the chip should try to recover.
12460                                  */
12461                                 if ((!load_status &&
12462                                      (!global || !other_load_status)) &&
12463                                       bnx2x_trylock_leader_lock(bp) &&
12464                                       !bnx2x_leader_reset(bp)) {
12465                                         netdev_info(bp->dev,
12466                                                     "Recovered in open\n");
12467                                         break;
12468                                 }
12469
12470                                 /* recovery has failed... */
12471                                 bnx2x_set_power_state(bp, PCI_D3hot);
12472                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12473
12474                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12475                                           "If you still see this message after a few retries then power cycle is required.\n");
12476
12477                                 return -EAGAIN;
12478                         } while (0);
12479                 }
12480         }
12481
12482         bp->recovery_state = BNX2X_RECOVERY_DONE;
12483         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12484         if (rc)
12485                 return rc;
12486
12487 #ifdef CONFIG_BNX2X_VXLAN
12488         if (IS_PF(bp))
12489                 vxlan_get_rx_port(dev);
12490 #endif
12491
12492         return 0;
12493 }
12494
12495 /* called with rtnl_lock */
12496 static int bnx2x_close(struct net_device *dev)
12497 {
12498         struct bnx2x *bp = netdev_priv(dev);
12499
12500         /* Unload the driver, release IRQs */
12501         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12502
12503         return 0;
12504 }
12505
12506 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12507                                       struct bnx2x_mcast_ramrod_params *p)
12508 {
12509         int mc_count = netdev_mc_count(bp->dev);
12510         struct bnx2x_mcast_list_elem *mc_mac =
12511                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12512         struct netdev_hw_addr *ha;
12513
12514         if (!mc_mac)
12515                 return -ENOMEM;
12516
12517         INIT_LIST_HEAD(&p->mcast_list);
12518
12519         netdev_for_each_mc_addr(ha, bp->dev) {
12520                 mc_mac->mac = bnx2x_mc_addr(ha);
12521                 list_add_tail(&mc_mac->link, &p->mcast_list);
12522                 mc_mac++;
12523         }
12524
12525         p->mcast_list_len = mc_count;
12526
12527         return 0;
12528 }
12529
12530 static void bnx2x_free_mcast_macs_list(
12531         struct bnx2x_mcast_ramrod_params *p)
12532 {
12533         struct bnx2x_mcast_list_elem *mc_mac =
12534                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12535                                  link);
12536
12537         WARN_ON(!mc_mac);
12538         kfree(mc_mac);
12539 }
12540
12541 /**
12542  * bnx2x_set_uc_list - configure a new unicast MACs list.
12543  *
12544  * @bp: driver handle
12545  *
12546  * We will use zero (0) as a MAC type for these MACs.
12547  */
12548 static int bnx2x_set_uc_list(struct bnx2x *bp)
12549 {
12550         int rc;
12551         struct net_device *dev = bp->dev;
12552         struct netdev_hw_addr *ha;
12553         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12554         unsigned long ramrod_flags = 0;
12555
12556         /* First schedule a cleanup up of old configuration */
12557         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12558         if (rc < 0) {
12559                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12560                 return rc;
12561         }
12562
12563         netdev_for_each_uc_addr(ha, dev) {
12564                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12565                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12566                 if (rc == -EEXIST) {
12567                         DP(BNX2X_MSG_SP,
12568                            "Failed to schedule ADD operations: %d\n", rc);
12569                         /* do not treat adding same MAC as error */
12570                         rc = 0;
12571
12572                 } else if (rc < 0) {
12573
12574                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12575                                   rc);
12576                         return rc;
12577                 }
12578         }
12579
12580         /* Execute the pending commands */
12581         __set_bit(RAMROD_CONT, &ramrod_flags);
12582         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12583                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12584 }
12585
12586 static int bnx2x_set_mc_list(struct bnx2x *bp)
12587 {
12588         struct net_device *dev = bp->dev;
12589         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12590         int rc = 0;
12591
12592         rparam.mcast_obj = &bp->mcast_obj;
12593
12594         /* first, clear all configured multicast MACs */
12595         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12596         if (rc < 0) {
12597                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12598                 return rc;
12599         }
12600
12601         /* then, configure a new MACs list */
12602         if (netdev_mc_count(dev)) {
12603                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12604                 if (rc) {
12605                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12606                                   rc);
12607                         return rc;
12608                 }
12609
12610                 /* Now add the new MACs */
12611                 rc = bnx2x_config_mcast(bp, &rparam,
12612                                         BNX2X_MCAST_CMD_ADD);
12613                 if (rc < 0)
12614                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12615                                   rc);
12616
12617                 bnx2x_free_mcast_macs_list(&rparam);
12618         }
12619
12620         return rc;
12621 }
12622
12623 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12624 static void bnx2x_set_rx_mode(struct net_device *dev)
12625 {
12626         struct bnx2x *bp = netdev_priv(dev);
12627
12628         if (bp->state != BNX2X_STATE_OPEN) {
12629                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12630                 return;
12631         } else {
12632                 /* Schedule an SP task to handle rest of change */
12633                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12634                                        NETIF_MSG_IFUP);
12635         }
12636 }
12637
12638 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12639 {
12640         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12641
12642         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12643
12644         netif_addr_lock_bh(bp->dev);
12645
12646         if (bp->dev->flags & IFF_PROMISC) {
12647                 rx_mode = BNX2X_RX_MODE_PROMISC;
12648         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12649                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12650                     CHIP_IS_E1(bp))) {
12651                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12652         } else {
12653                 if (IS_PF(bp)) {
12654                         /* some multicasts */
12655                         if (bnx2x_set_mc_list(bp) < 0)
12656                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12657
12658                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12659                         netif_addr_unlock_bh(bp->dev);
12660                         if (bnx2x_set_uc_list(bp) < 0)
12661                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12662                         netif_addr_lock_bh(bp->dev);
12663                 } else {
12664                         /* configuring mcast to a vf involves sleeping (when we
12665                          * wait for the pf's response).
12666                          */
12667                         bnx2x_schedule_sp_rtnl(bp,
12668                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12669                 }
12670         }
12671
12672         bp->rx_mode = rx_mode;
12673         /* handle ISCSI SD mode */
12674         if (IS_MF_ISCSI_ONLY(bp))
12675                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12676
12677         /* Schedule the rx_mode command */
12678         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12679                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12680                 netif_addr_unlock_bh(bp->dev);
12681                 return;
12682         }
12683
12684         if (IS_PF(bp)) {
12685                 bnx2x_set_storm_rx_mode(bp);
12686                 netif_addr_unlock_bh(bp->dev);
12687         } else {
12688                 /* VF will need to request the PF to make this change, and so
12689                  * the VF needs to release the bottom-half lock prior to the
12690                  * request (as it will likely require sleep on the VF side)
12691                  */
12692                 netif_addr_unlock_bh(bp->dev);
12693                 bnx2x_vfpf_storm_rx_mode(bp);
12694         }
12695 }
12696
12697 /* called with rtnl_lock */
12698 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12699                            int devad, u16 addr)
12700 {
12701         struct bnx2x *bp = netdev_priv(netdev);
12702         u16 value;
12703         int rc;
12704
12705         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12706            prtad, devad, addr);
12707
12708         /* The HW expects different devad if CL22 is used */
12709         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12710
12711         bnx2x_acquire_phy_lock(bp);
12712         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12713         bnx2x_release_phy_lock(bp);
12714         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12715
12716         if (!rc)
12717                 rc = value;
12718         return rc;
12719 }
12720
12721 /* called with rtnl_lock */
12722 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12723                             u16 addr, u16 value)
12724 {
12725         struct bnx2x *bp = netdev_priv(netdev);
12726         int rc;
12727
12728         DP(NETIF_MSG_LINK,
12729            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12730            prtad, devad, addr, value);
12731
12732         /* The HW expects different devad if CL22 is used */
12733         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12734
12735         bnx2x_acquire_phy_lock(bp);
12736         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12737         bnx2x_release_phy_lock(bp);
12738         return rc;
12739 }
12740
12741 /* called with rtnl_lock */
12742 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12743 {
12744         struct bnx2x *bp = netdev_priv(dev);
12745         struct mii_ioctl_data *mdio = if_mii(ifr);
12746
12747         if (!netif_running(dev))
12748                 return -EAGAIN;
12749
12750         switch (cmd) {
12751         case SIOCSHWTSTAMP:
12752                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12753         default:
12754                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12755                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12756                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12757         }
12758 }
12759
12760 #ifdef CONFIG_NET_POLL_CONTROLLER
12761 static void poll_bnx2x(struct net_device *dev)
12762 {
12763         struct bnx2x *bp = netdev_priv(dev);
12764         int i;
12765
12766         for_each_eth_queue(bp, i) {
12767                 struct bnx2x_fastpath *fp = &bp->fp[i];
12768                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12769         }
12770 }
12771 #endif
12772
12773 static int bnx2x_validate_addr(struct net_device *dev)
12774 {
12775         struct bnx2x *bp = netdev_priv(dev);
12776
12777         /* query the bulletin board for mac address configured by the PF */
12778         if (IS_VF(bp))
12779                 bnx2x_sample_bulletin(bp);
12780
12781         if (!is_valid_ether_addr(dev->dev_addr)) {
12782                 BNX2X_ERR("Non-valid Ethernet address\n");
12783                 return -EADDRNOTAVAIL;
12784         }
12785         return 0;
12786 }
12787
12788 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12789                                   struct netdev_phys_item_id *ppid)
12790 {
12791         struct bnx2x *bp = netdev_priv(netdev);
12792
12793         if (!(bp->flags & HAS_PHYS_PORT_ID))
12794                 return -EOPNOTSUPP;
12795
12796         ppid->id_len = sizeof(bp->phys_port_id);
12797         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12798
12799         return 0;
12800 }
12801
12802 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12803                                               struct net_device *dev,
12804                                               netdev_features_t features)
12805 {
12806         features = vlan_features_check(skb, features);
12807         return vxlan_features_check(skb, features);
12808 }
12809
12810 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12811 {
12812         int rc;
12813
12814         if (IS_PF(bp)) {
12815                 unsigned long ramrod_flags = 0;
12816
12817                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12818                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12819                                         add, &ramrod_flags);
12820         } else {
12821                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12822         }
12823
12824         return rc;
12825 }
12826
12827 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12828 {
12829         struct bnx2x_vlan_entry *vlan;
12830         int rc = 0;
12831
12832         if (!bp->vlan_cnt) {
12833                 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12834                 return 0;
12835         }
12836
12837         list_for_each_entry(vlan, &bp->vlan_reg, link) {
12838                 /* Prepare for cleanup in case of errors */
12839                 if (rc) {
12840                         vlan->hw = false;
12841                         continue;
12842                 }
12843
12844                 if (!vlan->hw)
12845                         continue;
12846
12847                 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12848
12849                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12850                 if (rc) {
12851                         BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12852                         vlan->hw = false;
12853                         rc = -EINVAL;
12854                         continue;
12855                 }
12856         }
12857
12858         return rc;
12859 }
12860
12861 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12862 {
12863         struct bnx2x *bp = netdev_priv(dev);
12864         struct bnx2x_vlan_entry *vlan;
12865         bool hw = false;
12866         int rc = 0;
12867
12868         if (!netif_running(bp->dev)) {
12869                 DP(NETIF_MSG_IFUP,
12870                    "Ignoring VLAN configuration the interface is down\n");
12871                 return -EFAULT;
12872         }
12873
12874         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12875
12876         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12877         if (!vlan)
12878                 return -ENOMEM;
12879
12880         bp->vlan_cnt++;
12881         if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12882                 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12883                 bp->accept_any_vlan = true;
12884                 if (IS_PF(bp))
12885                         bnx2x_set_rx_mode_inner(bp);
12886                 else
12887                         bnx2x_vfpf_storm_rx_mode(bp);
12888         } else if (bp->vlan_cnt <= bp->vlan_credit) {
12889                 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12890                 hw = true;
12891         }
12892
12893         vlan->vid = vid;
12894         vlan->hw = hw;
12895
12896         if (!rc) {
12897                 list_add(&vlan->link, &bp->vlan_reg);
12898         } else {
12899                 bp->vlan_cnt--;
12900                 kfree(vlan);
12901         }
12902
12903         DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12904
12905         return rc;
12906 }
12907
12908 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12909 {
12910         struct bnx2x *bp = netdev_priv(dev);
12911         struct bnx2x_vlan_entry *vlan;
12912         int rc = 0;
12913
12914         if (!netif_running(bp->dev)) {
12915                 DP(NETIF_MSG_IFUP,
12916                    "Ignoring VLAN configuration the interface is down\n");
12917                 return -EFAULT;
12918         }
12919
12920         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12921
12922         if (!bp->vlan_cnt) {
12923                 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12924                 return -EINVAL;
12925         }
12926
12927         list_for_each_entry(vlan, &bp->vlan_reg, link)
12928                 if (vlan->vid == vid)
12929                         break;
12930
12931         if (vlan->vid != vid) {
12932                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
12933                 return -EINVAL;
12934         }
12935
12936         if (vlan->hw)
12937                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
12938
12939         list_del(&vlan->link);
12940         kfree(vlan);
12941
12942         bp->vlan_cnt--;
12943
12944         if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
12945                 /* Configure all non-configured entries */
12946                 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12947                         if (vlan->hw)
12948                                 continue;
12949
12950                         rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12951                         if (rc) {
12952                                 BNX2X_ERR("Unable to config VLAN %d\n",
12953                                           vlan->vid);
12954                                 continue;
12955                         }
12956                         DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
12957                            vlan->vid);
12958                         vlan->hw = true;
12959                 }
12960                 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
12961                 bp->accept_any_vlan = false;
12962                 if (IS_PF(bp))
12963                         bnx2x_set_rx_mode_inner(bp);
12964                 else
12965                         bnx2x_vfpf_storm_rx_mode(bp);
12966         }
12967
12968         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
12969
12970         return rc;
12971 }
12972
12973 static const struct net_device_ops bnx2x_netdev_ops = {
12974         .ndo_open               = bnx2x_open,
12975         .ndo_stop               = bnx2x_close,
12976         .ndo_start_xmit         = bnx2x_start_xmit,
12977         .ndo_select_queue       = bnx2x_select_queue,
12978         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12979         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12980         .ndo_validate_addr      = bnx2x_validate_addr,
12981         .ndo_do_ioctl           = bnx2x_ioctl,
12982         .ndo_change_mtu         = bnx2x_change_mtu,
12983         .ndo_fix_features       = bnx2x_fix_features,
12984         .ndo_set_features       = bnx2x_set_features,
12985         .ndo_tx_timeout         = bnx2x_tx_timeout,
12986         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
12987         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
12988 #ifdef CONFIG_NET_POLL_CONTROLLER
12989         .ndo_poll_controller    = poll_bnx2x,
12990 #endif
12991         .ndo_setup_tc           = bnx2x_setup_tc,
12992 #ifdef CONFIG_BNX2X_SRIOV
12993         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12994         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12995         .ndo_get_vf_config      = bnx2x_get_vf_config,
12996 #endif
12997 #ifdef NETDEV_FCOE_WWNN
12998         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12999 #endif
13000
13001 #ifdef CONFIG_NET_RX_BUSY_POLL
13002         .ndo_busy_poll          = bnx2x_low_latency_recv,
13003 #endif
13004         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13005         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13006         .ndo_features_check     = bnx2x_features_check,
13007 #ifdef CONFIG_BNX2X_VXLAN
13008         .ndo_add_vxlan_port     = bnx2x_add_vxlan_port,
13009         .ndo_del_vxlan_port     = bnx2x_del_vxlan_port,
13010 #endif
13011 };
13012
13013 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13014 {
13015         struct device *dev = &bp->pdev->dev;
13016
13017         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13018             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13019                 dev_err(dev, "System does not support DMA, aborting\n");
13020                 return -EIO;
13021         }
13022
13023         return 0;
13024 }
13025
13026 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13027 {
13028         if (bp->flags & AER_ENABLED) {
13029                 pci_disable_pcie_error_reporting(bp->pdev);
13030                 bp->flags &= ~AER_ENABLED;
13031         }
13032 }
13033
13034 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13035                           struct net_device *dev, unsigned long board_type)
13036 {
13037         int rc;
13038         u32 pci_cfg_dword;
13039         bool chip_is_e1x = (board_type == BCM57710 ||
13040                             board_type == BCM57711 ||
13041                             board_type == BCM57711E);
13042
13043         SET_NETDEV_DEV(dev, &pdev->dev);
13044
13045         bp->dev = dev;
13046         bp->pdev = pdev;
13047
13048         rc = pci_enable_device(pdev);
13049         if (rc) {
13050                 dev_err(&bp->pdev->dev,
13051                         "Cannot enable PCI device, aborting\n");
13052                 goto err_out;
13053         }
13054
13055         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13056                 dev_err(&bp->pdev->dev,
13057                         "Cannot find PCI device base address, aborting\n");
13058                 rc = -ENODEV;
13059                 goto err_out_disable;
13060         }
13061
13062         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13063                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13064                 rc = -ENODEV;
13065                 goto err_out_disable;
13066         }
13067
13068         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13069         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13070             PCICFG_REVESION_ID_ERROR_VAL) {
13071                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13072                 rc = -ENODEV;
13073                 goto err_out_disable;
13074         }
13075
13076         if (atomic_read(&pdev->enable_cnt) == 1) {
13077                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13078                 if (rc) {
13079                         dev_err(&bp->pdev->dev,
13080                                 "Cannot obtain PCI resources, aborting\n");
13081                         goto err_out_disable;
13082                 }
13083
13084                 pci_set_master(pdev);
13085                 pci_save_state(pdev);
13086         }
13087
13088         if (IS_PF(bp)) {
13089                 if (!pdev->pm_cap) {
13090                         dev_err(&bp->pdev->dev,
13091                                 "Cannot find power management capability, aborting\n");
13092                         rc = -EIO;
13093                         goto err_out_release;
13094                 }
13095         }
13096
13097         if (!pci_is_pcie(pdev)) {
13098                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13099                 rc = -EIO;
13100                 goto err_out_release;
13101         }
13102
13103         rc = bnx2x_set_coherency_mask(bp);
13104         if (rc)
13105                 goto err_out_release;
13106
13107         dev->mem_start = pci_resource_start(pdev, 0);
13108         dev->base_addr = dev->mem_start;
13109         dev->mem_end = pci_resource_end(pdev, 0);
13110
13111         dev->irq = pdev->irq;
13112
13113         bp->regview = pci_ioremap_bar(pdev, 0);
13114         if (!bp->regview) {
13115                 dev_err(&bp->pdev->dev,
13116                         "Cannot map register space, aborting\n");
13117                 rc = -ENOMEM;
13118                 goto err_out_release;
13119         }
13120
13121         /* In E1/E1H use pci device function given by kernel.
13122          * In E2/E3 read physical function from ME register since these chips
13123          * support Physical Device Assignment where kernel BDF maybe arbitrary
13124          * (depending on hypervisor).
13125          */
13126         if (chip_is_e1x) {
13127                 bp->pf_num = PCI_FUNC(pdev->devfn);
13128         } else {
13129                 /* chip is E2/3*/
13130                 pci_read_config_dword(bp->pdev,
13131                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13132                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13133                                   ME_REG_ABS_PF_NUM_SHIFT);
13134         }
13135         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13136
13137         /* clean indirect addresses */
13138         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13139                                PCICFG_VENDOR_ID_OFFSET);
13140
13141         /* Set PCIe reset type to fundamental for EEH recovery */
13142         pdev->needs_freset = 1;
13143
13144         /* AER (Advanced Error reporting) configuration */
13145         rc = pci_enable_pcie_error_reporting(pdev);
13146         if (!rc)
13147                 bp->flags |= AER_ENABLED;
13148         else
13149                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13150
13151         /*
13152          * Clean the following indirect addresses for all functions since it
13153          * is not used by the driver.
13154          */
13155         if (IS_PF(bp)) {
13156                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13157                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13158                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13159                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13160
13161                 if (chip_is_e1x) {
13162                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13163                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13164                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13165                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13166                 }
13167
13168                 /* Enable internal target-read (in case we are probed after PF
13169                  * FLR). Must be done prior to any BAR read access. Only for
13170                  * 57712 and up
13171                  */
13172                 if (!chip_is_e1x)
13173                         REG_WR(bp,
13174                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13175         }
13176
13177         dev->watchdog_timeo = TX_TIMEOUT;
13178
13179         dev->netdev_ops = &bnx2x_netdev_ops;
13180         bnx2x_set_ethtool_ops(bp, dev);
13181
13182         dev->priv_flags |= IFF_UNICAST_FLT;
13183
13184         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13185                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13186                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13187                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13188         if (!chip_is_e1x) {
13189                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
13190                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
13191                 dev->hw_enc_features =
13192                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13193                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13194                         NETIF_F_GSO_IPIP |
13195                         NETIF_F_GSO_SIT |
13196                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
13197         }
13198
13199         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13200                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13201
13202         /* VF with OLD Hypervisor or old PF do not support filtering */
13203         if (IS_PF(bp)) {
13204                 if (chip_is_e1x)
13205                         bp->accept_any_vlan = true;
13206                 else
13207                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13208 #ifdef CONFIG_BNX2X_SRIOV
13209         } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13210                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13211 #endif
13212         }
13213
13214         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13215         dev->features |= NETIF_F_HIGHDMA;
13216
13217         /* Add Loopback capability to the device */
13218         dev->hw_features |= NETIF_F_LOOPBACK;
13219
13220 #ifdef BCM_DCBNL
13221         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13222 #endif
13223
13224         /* get_port_hwinfo() will set prtad and mmds properly */
13225         bp->mdio.prtad = MDIO_PRTAD_NONE;
13226         bp->mdio.mmds = 0;
13227         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13228         bp->mdio.dev = dev;
13229         bp->mdio.mdio_read = bnx2x_mdio_read;
13230         bp->mdio.mdio_write = bnx2x_mdio_write;
13231
13232         return 0;
13233
13234 err_out_release:
13235         if (atomic_read(&pdev->enable_cnt) == 1)
13236                 pci_release_regions(pdev);
13237
13238 err_out_disable:
13239         pci_disable_device(pdev);
13240
13241 err_out:
13242         return rc;
13243 }
13244
13245 /*(DEBLOBBED)*/
13246
13247 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13248 {
13249         const __be32 *source = (const __be32 *)_source;
13250         u32 *target = (u32 *)_target;
13251         u32 i;
13252
13253         for (i = 0; i < n/4; i++)
13254                 target[i] = be32_to_cpu(source[i]);
13255 }
13256
13257 /*
13258    Ops array is stored in the following format:
13259    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13260  */
13261 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13262 {
13263         const __be32 *source = (const __be32 *)_source;
13264         struct raw_op *target = (struct raw_op *)_target;
13265         u32 i, j, tmp;
13266
13267         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13268                 tmp = be32_to_cpu(source[j]);
13269                 target[i].op = (tmp >> 24) & 0xff;
13270                 target[i].offset = tmp & 0xffffff;
13271                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13272         }
13273 }
13274
13275 /* IRO array is stored in the following format:
13276  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13277  */
13278 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13279 {
13280         const __be32 *source = (const __be32 *)_source;
13281         struct iro *target = (struct iro *)_target;
13282         u32 i, j, tmp;
13283
13284         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13285                 target[i].base = be32_to_cpu(source[j]);
13286                 j++;
13287                 tmp = be32_to_cpu(source[j]);
13288                 target[i].m1 = (tmp >> 16) & 0xffff;
13289                 target[i].m2 = tmp & 0xffff;
13290                 j++;
13291                 tmp = be32_to_cpu(source[j]);
13292                 target[i].m3 = (tmp >> 16) & 0xffff;
13293                 target[i].size = tmp & 0xffff;
13294                 j++;
13295         }
13296 }
13297
13298 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13299 {
13300         const __be16 *source = (const __be16 *)_source;
13301         u16 *target = (u16 *)_target;
13302         u32 i;
13303
13304         for (i = 0; i < n/2; i++)
13305                 target[i] = be16_to_cpu(source[i]);
13306 }
13307
13308 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13309 do {                                                                    \
13310         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13311         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13312         if (!bp->arr)                                                   \
13313                 goto lbl;                                               \
13314         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13315              (u8 *)bp->arr, len);                                       \
13316 } while (0)
13317
13318 static int bnx2x_init_firmware(struct bnx2x *bp)
13319 {
13320         const char *fw_file_name;
13321         struct bnx2x_fw_file_hdr *fw_hdr;
13322         int rc;
13323
13324         if (bp->firmware)
13325                 return 0;
13326
13327         if (CHIP_IS_E1(bp))
13328                 fw_file_name = FW_FILE_NAME_E1;
13329         else if (CHIP_IS_E1H(bp))
13330                 fw_file_name = FW_FILE_NAME_E1H;
13331         else if (!CHIP_IS_E1x(bp))
13332                 fw_file_name = FW_FILE_NAME_E2;
13333         else {
13334                 BNX2X_ERR("Unsupported chip revision\n");
13335                 return -EINVAL;
13336         }
13337         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13338
13339         rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13340         if (rc) {
13341                 BNX2X_ERR("Can't load firmware file %s\n",
13342                           fw_file_name);
13343                 goto request_firmware_exit;
13344         }
13345
13346         /*(DEBLOBBED)*/
13347         if (rc) {
13348                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13349                 goto request_firmware_exit;
13350         }
13351
13352         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13353
13354         /* Initialize the pointers to the init arrays */
13355         /* Blob */
13356         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13357
13358         /* Opcodes */
13359         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13360
13361         /* Offsets */
13362         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13363                             be16_to_cpu_n);
13364
13365         /* STORMs firmware */
13366         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13367                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13368         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13369                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13370         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13371                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13372         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13373                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13374         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13375                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13376         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13377                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13378         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13379                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13380         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13381                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13382         /* IRO */
13383         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13384
13385         return 0;
13386
13387 iro_alloc_err:
13388         kfree(bp->init_ops_offsets);
13389 init_offsets_alloc_err:
13390         kfree(bp->init_ops);
13391 init_ops_alloc_err:
13392         kfree(bp->init_data);
13393 request_firmware_exit:
13394         release_firmware(bp->firmware);
13395         bp->firmware = NULL;
13396
13397         return rc;
13398 }
13399
13400 static void bnx2x_release_firmware(struct bnx2x *bp)
13401 {
13402         kfree(bp->init_ops_offsets);
13403         kfree(bp->init_ops);
13404         kfree(bp->init_data);
13405         release_firmware(bp->firmware);
13406         bp->firmware = NULL;
13407 }
13408
13409 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13410         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13411         .init_hw_cmn      = bnx2x_init_hw_common,
13412         .init_hw_port     = bnx2x_init_hw_port,
13413         .init_hw_func     = bnx2x_init_hw_func,
13414
13415         .reset_hw_cmn     = bnx2x_reset_common,
13416         .reset_hw_port    = bnx2x_reset_port,
13417         .reset_hw_func    = bnx2x_reset_func,
13418
13419         .gunzip_init      = bnx2x_gunzip_init,
13420         .gunzip_end       = bnx2x_gunzip_end,
13421
13422         .init_fw          = bnx2x_init_firmware,
13423         .release_fw       = bnx2x_release_firmware,
13424 };
13425
13426 void bnx2x__init_func_obj(struct bnx2x *bp)
13427 {
13428         /* Prepare DMAE related driver resources */
13429         bnx2x_setup_dmae(bp);
13430
13431         bnx2x_init_func_obj(bp, &bp->func_obj,
13432                             bnx2x_sp(bp, func_rdata),
13433                             bnx2x_sp_mapping(bp, func_rdata),
13434                             bnx2x_sp(bp, func_afex_rdata),
13435                             bnx2x_sp_mapping(bp, func_afex_rdata),
13436                             &bnx2x_func_sp_drv);
13437 }
13438
13439 /* must be called after sriov-enable */
13440 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13441 {
13442         int cid_count = BNX2X_L2_MAX_CID(bp);
13443
13444         if (IS_SRIOV(bp))
13445                 cid_count += BNX2X_VF_CIDS;
13446
13447         if (CNIC_SUPPORT(bp))
13448                 cid_count += CNIC_CID_MAX;
13449
13450         return roundup(cid_count, QM_CID_ROUND);
13451 }
13452
13453 /**
13454  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13455  *
13456  * @dev:        pci device
13457  *
13458  */
13459 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13460 {
13461         int index;
13462         u16 control = 0;
13463
13464         /*
13465          * If MSI-X is not supported - return number of SBs needed to support
13466          * one fast path queue: one FP queue + SB for CNIC
13467          */
13468         if (!pdev->msix_cap) {
13469                 dev_info(&pdev->dev, "no msix capability found\n");
13470                 return 1 + cnic_cnt;
13471         }
13472         dev_info(&pdev->dev, "msix capability found\n");
13473
13474         /*
13475          * The value in the PCI configuration space is the index of the last
13476          * entry, namely one less than the actual size of the table, which is
13477          * exactly what we want to return from this function: number of all SBs
13478          * without the default SB.
13479          * For VFs there is no default SB, then we return (index+1).
13480          */
13481         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13482
13483         index = control & PCI_MSIX_FLAGS_QSIZE;
13484
13485         return index;
13486 }
13487
13488 static int set_max_cos_est(int chip_id)
13489 {
13490         switch (chip_id) {
13491         case BCM57710:
13492         case BCM57711:
13493         case BCM57711E:
13494                 return BNX2X_MULTI_TX_COS_E1X;
13495         case BCM57712:
13496         case BCM57712_MF:
13497                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13498         case BCM57800:
13499         case BCM57800_MF:
13500         case BCM57810:
13501         case BCM57810_MF:
13502         case BCM57840_4_10:
13503         case BCM57840_2_20:
13504         case BCM57840_O:
13505         case BCM57840_MFO:
13506         case BCM57840_MF:
13507         case BCM57811:
13508         case BCM57811_MF:
13509                 return BNX2X_MULTI_TX_COS_E3B0;
13510         case BCM57712_VF:
13511         case BCM57800_VF:
13512         case BCM57810_VF:
13513         case BCM57840_VF:
13514         case BCM57811_VF:
13515                 return 1;
13516         default:
13517                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13518                 return -ENODEV;
13519         }
13520 }
13521
13522 static int set_is_vf(int chip_id)
13523 {
13524         switch (chip_id) {
13525         case BCM57712_VF:
13526         case BCM57800_VF:
13527         case BCM57810_VF:
13528         case BCM57840_VF:
13529         case BCM57811_VF:
13530                 return true;
13531         default:
13532                 return false;
13533         }
13534 }
13535
13536 /* nig_tsgen registers relative address */
13537 #define tsgen_ctrl 0x0
13538 #define tsgen_freecount 0x10
13539 #define tsgen_synctime_t0 0x20
13540 #define tsgen_offset_t0 0x28
13541 #define tsgen_drift_t0 0x30
13542 #define tsgen_synctime_t1 0x58
13543 #define tsgen_offset_t1 0x60
13544 #define tsgen_drift_t1 0x68
13545
13546 /* FW workaround for setting drift */
13547 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13548                                           int best_val, int best_period)
13549 {
13550         struct bnx2x_func_state_params func_params = {NULL};
13551         struct bnx2x_func_set_timesync_params *set_timesync_params =
13552                 &func_params.params.set_timesync;
13553
13554         /* Prepare parameters for function state transitions */
13555         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13556         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13557
13558         func_params.f_obj = &bp->func_obj;
13559         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13560
13561         /* Function parameters */
13562         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13563         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13564         set_timesync_params->add_sub_drift_adjust_value =
13565                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13566         set_timesync_params->drift_adjust_value = best_val;
13567         set_timesync_params->drift_adjust_period = best_period;
13568
13569         return bnx2x_func_state_change(bp, &func_params);
13570 }
13571
13572 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13573 {
13574         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13575         int rc;
13576         int drift_dir = 1;
13577         int val, period, period1, period2, dif, dif1, dif2;
13578         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13579
13580         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13581
13582         if (!netif_running(bp->dev)) {
13583                 DP(BNX2X_MSG_PTP,
13584                    "PTP adjfreq called while the interface is down\n");
13585                 return -EFAULT;
13586         }
13587
13588         if (ppb < 0) {
13589                 ppb = -ppb;
13590                 drift_dir = 0;
13591         }
13592
13593         if (ppb == 0) {
13594                 best_val = 1;
13595                 best_period = 0x1FFFFFF;
13596         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13597                 best_val = 31;
13598                 best_period = 1;
13599         } else {
13600                 /* Changed not to allow val = 8, 16, 24 as these values
13601                  * are not supported in workaround.
13602                  */
13603                 for (val = 0; val <= 31; val++) {
13604                         if ((val & 0x7) == 0)
13605                                 continue;
13606                         period1 = val * 1000000 / ppb;
13607                         period2 = period1 + 1;
13608                         if (period1 != 0)
13609                                 dif1 = ppb - (val * 1000000 / period1);
13610                         else
13611                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13612                         if (dif1 < 0)
13613                                 dif1 = -dif1;
13614                         dif2 = ppb - (val * 1000000 / period2);
13615                         if (dif2 < 0)
13616                                 dif2 = -dif2;
13617                         dif = (dif1 < dif2) ? dif1 : dif2;
13618                         period = (dif1 < dif2) ? period1 : period2;
13619                         if (dif < best_dif) {
13620                                 best_dif = dif;
13621                                 best_val = val;
13622                                 best_period = period;
13623                         }
13624                 }
13625         }
13626
13627         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13628                                             best_period);
13629         if (rc) {
13630                 BNX2X_ERR("Failed to set drift\n");
13631                 return -EFAULT;
13632         }
13633
13634         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13635            best_period);
13636
13637         return 0;
13638 }
13639
13640 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13641 {
13642         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13643
13644         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13645
13646         timecounter_adjtime(&bp->timecounter, delta);
13647
13648         return 0;
13649 }
13650
13651 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13652 {
13653         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13654         u64 ns;
13655
13656         ns = timecounter_read(&bp->timecounter);
13657
13658         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13659
13660         *ts = ns_to_timespec64(ns);
13661
13662         return 0;
13663 }
13664
13665 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13666                              const struct timespec64 *ts)
13667 {
13668         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13669         u64 ns;
13670
13671         ns = timespec64_to_ns(ts);
13672
13673         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13674
13675         /* Re-init the timecounter */
13676         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13677
13678         return 0;
13679 }
13680
13681 /* Enable (or disable) ancillary features of the phc subsystem */
13682 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13683                             struct ptp_clock_request *rq, int on)
13684 {
13685         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13686
13687         BNX2X_ERR("PHC ancillary features are not supported\n");
13688         return -ENOTSUPP;
13689 }
13690
13691 static void bnx2x_register_phc(struct bnx2x *bp)
13692 {
13693         /* Fill the ptp_clock_info struct and register PTP clock*/
13694         bp->ptp_clock_info.owner = THIS_MODULE;
13695         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13696         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13697         bp->ptp_clock_info.n_alarm = 0;
13698         bp->ptp_clock_info.n_ext_ts = 0;
13699         bp->ptp_clock_info.n_per_out = 0;
13700         bp->ptp_clock_info.pps = 0;
13701         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13702         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13703         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13704         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13705         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13706
13707         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13708         if (IS_ERR(bp->ptp_clock)) {
13709                 bp->ptp_clock = NULL;
13710                 BNX2X_ERR("PTP clock registeration failed\n");
13711         }
13712 }
13713
13714 static int bnx2x_init_one(struct pci_dev *pdev,
13715                                     const struct pci_device_id *ent)
13716 {
13717         struct net_device *dev = NULL;
13718         struct bnx2x *bp;
13719         enum pcie_link_width pcie_width;
13720         enum pci_bus_speed pcie_speed;
13721         int rc, max_non_def_sbs;
13722         int rx_count, tx_count, rss_count, doorbell_size;
13723         int max_cos_est;
13724         bool is_vf;
13725         int cnic_cnt;
13726
13727         /* Management FW 'remembers' living interfaces. Allow it some time
13728          * to forget previously living interfaces, allowing a proper re-load.
13729          */
13730         if (is_kdump_kernel()) {
13731                 ktime_t now = ktime_get_boottime();
13732                 ktime_t fw_ready_time = ktime_set(5, 0);
13733
13734                 if (ktime_before(now, fw_ready_time))
13735                         msleep(ktime_ms_delta(fw_ready_time, now));
13736         }
13737
13738         /* An estimated maximum supported CoS number according to the chip
13739          * version.
13740          * We will try to roughly estimate the maximum number of CoSes this chip
13741          * may support in order to minimize the memory allocated for Tx
13742          * netdev_queue's. This number will be accurately calculated during the
13743          * initialization of bp->max_cos based on the chip versions AND chip
13744          * revision in the bnx2x_init_bp().
13745          */
13746         max_cos_est = set_max_cos_est(ent->driver_data);
13747         if (max_cos_est < 0)
13748                 return max_cos_est;
13749         is_vf = set_is_vf(ent->driver_data);
13750         cnic_cnt = is_vf ? 0 : 1;
13751
13752         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13753
13754         /* add another SB for VF as it has no default SB */
13755         max_non_def_sbs += is_vf ? 1 : 0;
13756
13757         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13758         rss_count = max_non_def_sbs - cnic_cnt;
13759
13760         if (rss_count < 1)
13761                 return -EINVAL;
13762
13763         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13764         rx_count = rss_count + cnic_cnt;
13765
13766         /* Maximum number of netdev Tx queues:
13767          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13768          */
13769         tx_count = rss_count * max_cos_est + cnic_cnt;
13770
13771         /* dev zeroed in init_etherdev */
13772         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13773         if (!dev)
13774                 return -ENOMEM;
13775
13776         bp = netdev_priv(dev);
13777
13778         bp->flags = 0;
13779         if (is_vf)
13780                 bp->flags |= IS_VF_FLAG;
13781
13782         bp->igu_sb_cnt = max_non_def_sbs;
13783         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13784         bp->msg_enable = debug;
13785         bp->cnic_support = cnic_cnt;
13786         bp->cnic_probe = bnx2x_cnic_probe;
13787
13788         pci_set_drvdata(pdev, dev);
13789
13790         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13791         if (rc < 0) {
13792                 free_netdev(dev);
13793                 return rc;
13794         }
13795
13796         BNX2X_DEV_INFO("This is a %s function\n",
13797                        IS_PF(bp) ? "physical" : "virtual");
13798         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13799         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13800         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13801                        tx_count, rx_count);
13802
13803         rc = bnx2x_init_bp(bp);
13804         if (rc)
13805                 goto init_one_exit;
13806
13807         /* Map doorbells here as we need the real value of bp->max_cos which
13808          * is initialized in bnx2x_init_bp() to determine the number of
13809          * l2 connections.
13810          */
13811         if (IS_VF(bp)) {
13812                 bp->doorbells = bnx2x_vf_doorbells(bp);
13813                 rc = bnx2x_vf_pci_alloc(bp);
13814                 if (rc)
13815                         goto init_one_exit;
13816         } else {
13817                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13818                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13819                         dev_err(&bp->pdev->dev,
13820                                 "Cannot map doorbells, bar size too small, aborting\n");
13821                         rc = -ENOMEM;
13822                         goto init_one_exit;
13823                 }
13824                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13825                                                 doorbell_size);
13826         }
13827         if (!bp->doorbells) {
13828                 dev_err(&bp->pdev->dev,
13829                         "Cannot map doorbell space, aborting\n");
13830                 rc = -ENOMEM;
13831                 goto init_one_exit;
13832         }
13833
13834         if (IS_VF(bp)) {
13835                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13836                 if (rc)
13837                         goto init_one_exit;
13838         }
13839
13840         /* Enable SRIOV if capability found in configuration space */
13841         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13842         if (rc)
13843                 goto init_one_exit;
13844
13845         /* calc qm_cid_count */
13846         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13847         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13848
13849         /* disable FCOE L2 queue for E1x*/
13850         if (CHIP_IS_E1x(bp))
13851                 bp->flags |= NO_FCOE_FLAG;
13852
13853         /* Set bp->num_queues for MSI-X mode*/
13854         bnx2x_set_num_queues(bp);
13855
13856         /* Configure interrupt mode: try to enable MSI-X/MSI if
13857          * needed.
13858          */
13859         rc = bnx2x_set_int_mode(bp);
13860         if (rc) {
13861                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13862                 goto init_one_exit;
13863         }
13864         BNX2X_DEV_INFO("set interrupts successfully\n");
13865
13866         /* register the net device */
13867         rc = register_netdev(dev);
13868         if (rc) {
13869                 dev_err(&pdev->dev, "Cannot register net device\n");
13870                 goto init_one_exit;
13871         }
13872         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13873
13874         if (!NO_FCOE(bp)) {
13875                 /* Add storage MAC address */
13876                 rtnl_lock();
13877                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13878                 rtnl_unlock();
13879         }
13880         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13881             pcie_speed == PCI_SPEED_UNKNOWN ||
13882             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13883                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13884         else
13885                 BNX2X_DEV_INFO(
13886                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13887                        board_info[ent->driver_data].name,
13888                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13889                        pcie_width,
13890                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13891                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13892                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13893                        "Unknown",
13894                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13895
13896         bnx2x_register_phc(bp);
13897
13898         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13899                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13900
13901         return 0;
13902
13903 init_one_exit:
13904         bnx2x_disable_pcie_error_reporting(bp);
13905
13906         if (bp->regview)
13907                 iounmap(bp->regview);
13908
13909         if (IS_PF(bp) && bp->doorbells)
13910                 iounmap(bp->doorbells);
13911
13912         free_netdev(dev);
13913
13914         if (atomic_read(&pdev->enable_cnt) == 1)
13915                 pci_release_regions(pdev);
13916
13917         pci_disable_device(pdev);
13918
13919         return rc;
13920 }
13921
13922 static void __bnx2x_remove(struct pci_dev *pdev,
13923                            struct net_device *dev,
13924                            struct bnx2x *bp,
13925                            bool remove_netdev)
13926 {
13927         if (bp->ptp_clock) {
13928                 ptp_clock_unregister(bp->ptp_clock);
13929                 bp->ptp_clock = NULL;
13930         }
13931
13932         /* Delete storage MAC address */
13933         if (!NO_FCOE(bp)) {
13934                 rtnl_lock();
13935                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13936                 rtnl_unlock();
13937         }
13938
13939 #ifdef BCM_DCBNL
13940         /* Delete app tlvs from dcbnl */
13941         bnx2x_dcbnl_update_applist(bp, true);
13942 #endif
13943
13944         if (IS_PF(bp) &&
13945             !BP_NOMCP(bp) &&
13946             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13947                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13948
13949         /* Close the interface - either directly or implicitly */
13950         if (remove_netdev) {
13951                 unregister_netdev(dev);
13952         } else {
13953                 rtnl_lock();
13954                 dev_close(dev);
13955                 rtnl_unlock();
13956         }
13957
13958         bnx2x_iov_remove_one(bp);
13959
13960         /* Power on: we can't let PCI layer write to us while we are in D3 */
13961         if (IS_PF(bp)) {
13962                 bnx2x_set_power_state(bp, PCI_D0);
13963                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
13964
13965                 /* Set endianity registers to reset values in case next driver
13966                  * boots in different endianty environment.
13967                  */
13968                 bnx2x_reset_endianity(bp);
13969         }
13970
13971         /* Disable MSI/MSI-X */
13972         bnx2x_disable_msi(bp);
13973
13974         /* Power off */
13975         if (IS_PF(bp))
13976                 bnx2x_set_power_state(bp, PCI_D3hot);
13977
13978         /* Make sure RESET task is not scheduled before continuing */
13979         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13980
13981         /* send message via vfpf channel to release the resources of this vf */
13982         if (IS_VF(bp))
13983                 bnx2x_vfpf_release(bp);
13984
13985         /* Assumes no further PCIe PM changes will occur */
13986         if (system_state == SYSTEM_POWER_OFF) {
13987                 pci_wake_from_d3(pdev, bp->wol);
13988                 pci_set_power_state(pdev, PCI_D3hot);
13989         }
13990
13991         bnx2x_disable_pcie_error_reporting(bp);
13992         if (remove_netdev) {
13993                 if (bp->regview)
13994                         iounmap(bp->regview);
13995
13996                 /* For vfs, doorbells are part of the regview and were unmapped
13997                  * along with it. FW is only loaded by PF.
13998                  */
13999                 if (IS_PF(bp)) {
14000                         if (bp->doorbells)
14001                                 iounmap(bp->doorbells);
14002
14003                         bnx2x_release_firmware(bp);
14004                 } else {
14005                         bnx2x_vf_pci_dealloc(bp);
14006                 }
14007                 bnx2x_free_mem_bp(bp);
14008
14009                 free_netdev(dev);
14010
14011                 if (atomic_read(&pdev->enable_cnt) == 1)
14012                         pci_release_regions(pdev);
14013
14014                 pci_disable_device(pdev);
14015         }
14016 }
14017
14018 static void bnx2x_remove_one(struct pci_dev *pdev)
14019 {
14020         struct net_device *dev = pci_get_drvdata(pdev);
14021         struct bnx2x *bp;
14022
14023         if (!dev) {
14024                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14025                 return;
14026         }
14027         bp = netdev_priv(dev);
14028
14029         __bnx2x_remove(pdev, dev, bp, true);
14030 }
14031
14032 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14033 {
14034         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14035
14036         bp->rx_mode = BNX2X_RX_MODE_NONE;
14037
14038         if (CNIC_LOADED(bp))
14039                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14040
14041         /* Stop Tx */
14042         bnx2x_tx_disable(bp);
14043         /* Delete all NAPI objects */
14044         bnx2x_del_all_napi(bp);
14045         if (CNIC_LOADED(bp))
14046                 bnx2x_del_all_napi_cnic(bp);
14047         netdev_reset_tc(bp->dev);
14048
14049         del_timer_sync(&bp->timer);
14050         cancel_delayed_work_sync(&bp->sp_task);
14051         cancel_delayed_work_sync(&bp->period_task);
14052
14053         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14054                 bp->stats_state = STATS_STATE_DISABLED;
14055                 up(&bp->stats_lock);
14056         }
14057
14058         bnx2x_save_statistics(bp);
14059
14060         netif_carrier_off(bp->dev);
14061
14062         return 0;
14063 }
14064
14065 /**
14066  * bnx2x_io_error_detected - called when PCI error is detected
14067  * @pdev: Pointer to PCI device
14068  * @state: The current pci connection state
14069  *
14070  * This function is called after a PCI bus error affecting
14071  * this device has been detected.
14072  */
14073 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14074                                                 pci_channel_state_t state)
14075 {
14076         struct net_device *dev = pci_get_drvdata(pdev);
14077         struct bnx2x *bp = netdev_priv(dev);
14078
14079         rtnl_lock();
14080
14081         BNX2X_ERR("IO error detected\n");
14082
14083         netif_device_detach(dev);
14084
14085         if (state == pci_channel_io_perm_failure) {
14086                 rtnl_unlock();
14087                 return PCI_ERS_RESULT_DISCONNECT;
14088         }
14089
14090         if (netif_running(dev))
14091                 bnx2x_eeh_nic_unload(bp);
14092
14093         bnx2x_prev_path_mark_eeh(bp);
14094
14095         pci_disable_device(pdev);
14096
14097         rtnl_unlock();
14098
14099         /* Request a slot reset */
14100         return PCI_ERS_RESULT_NEED_RESET;
14101 }
14102
14103 /**
14104  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14105  * @pdev: Pointer to PCI device
14106  *
14107  * Restart the card from scratch, as if from a cold-boot.
14108  */
14109 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14110 {
14111         struct net_device *dev = pci_get_drvdata(pdev);
14112         struct bnx2x *bp = netdev_priv(dev);
14113         int i;
14114
14115         rtnl_lock();
14116         BNX2X_ERR("IO slot reset initializing...\n");
14117         if (pci_enable_device(pdev)) {
14118                 dev_err(&pdev->dev,
14119                         "Cannot re-enable PCI device after reset\n");
14120                 rtnl_unlock();
14121                 return PCI_ERS_RESULT_DISCONNECT;
14122         }
14123
14124         pci_set_master(pdev);
14125         pci_restore_state(pdev);
14126         pci_save_state(pdev);
14127
14128         if (netif_running(dev))
14129                 bnx2x_set_power_state(bp, PCI_D0);
14130
14131         if (netif_running(dev)) {
14132                 BNX2X_ERR("IO slot reset --> driver unload\n");
14133
14134                 /* MCP should have been reset; Need to wait for validity */
14135                 bnx2x_init_shmem(bp);
14136
14137                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14138                         u32 v;
14139
14140                         v = SHMEM2_RD(bp,
14141                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14142                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14143                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14144                 }
14145                 bnx2x_drain_tx_queues(bp);
14146                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14147                 bnx2x_netif_stop(bp, 1);
14148                 bnx2x_free_irq(bp);
14149
14150                 /* Report UNLOAD_DONE to MCP */
14151                 bnx2x_send_unload_done(bp, true);
14152
14153                 bp->sp_state = 0;
14154                 bp->port.pmf = 0;
14155
14156                 bnx2x_prev_unload(bp);
14157
14158                 /* We should have reseted the engine, so It's fair to
14159                  * assume the FW will no longer write to the bnx2x driver.
14160                  */
14161                 bnx2x_squeeze_objects(bp);
14162                 bnx2x_free_skbs(bp);
14163                 for_each_rx_queue(bp, i)
14164                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14165                 bnx2x_free_fp_mem(bp);
14166                 bnx2x_free_mem(bp);
14167
14168                 bp->state = BNX2X_STATE_CLOSED;
14169         }
14170
14171         rtnl_unlock();
14172
14173         /* If AER, perform cleanup of the PCIe registers */
14174         if (bp->flags & AER_ENABLED) {
14175                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14176                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14177                 else
14178                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14179         }
14180
14181         return PCI_ERS_RESULT_RECOVERED;
14182 }
14183
14184 /**
14185  * bnx2x_io_resume - called when traffic can start flowing again
14186  * @pdev: Pointer to PCI device
14187  *
14188  * This callback is called when the error recovery driver tells us that
14189  * its OK to resume normal operation.
14190  */
14191 static void bnx2x_io_resume(struct pci_dev *pdev)
14192 {
14193         struct net_device *dev = pci_get_drvdata(pdev);
14194         struct bnx2x *bp = netdev_priv(dev);
14195
14196         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14197                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14198                 return;
14199         }
14200
14201         rtnl_lock();
14202
14203         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14204                                                         DRV_MSG_SEQ_NUMBER_MASK;
14205
14206         if (netif_running(dev))
14207                 bnx2x_nic_load(bp, LOAD_NORMAL);
14208
14209         netif_device_attach(dev);
14210
14211         rtnl_unlock();
14212 }
14213
14214 static const struct pci_error_handlers bnx2x_err_handler = {
14215         .error_detected = bnx2x_io_error_detected,
14216         .slot_reset     = bnx2x_io_slot_reset,
14217         .resume         = bnx2x_io_resume,
14218 };
14219
14220 static void bnx2x_shutdown(struct pci_dev *pdev)
14221 {
14222         struct net_device *dev = pci_get_drvdata(pdev);
14223         struct bnx2x *bp;
14224
14225         if (!dev)
14226                 return;
14227
14228         bp = netdev_priv(dev);
14229         if (!bp)
14230                 return;
14231
14232         rtnl_lock();
14233         netif_device_detach(dev);
14234         rtnl_unlock();
14235
14236         /* Don't remove the netdevice, as there are scenarios which will cause
14237          * the kernel to hang, e.g., when trying to remove bnx2i while the
14238          * rootfs is mounted from SAN.
14239          */
14240         __bnx2x_remove(pdev, dev, bp, false);
14241 }
14242
14243 static struct pci_driver bnx2x_pci_driver = {
14244         .name        = DRV_MODULE_NAME,
14245         .id_table    = bnx2x_pci_tbl,
14246         .probe       = bnx2x_init_one,
14247         .remove      = bnx2x_remove_one,
14248         .suspend     = bnx2x_suspend,
14249         .resume      = bnx2x_resume,
14250         .err_handler = &bnx2x_err_handler,
14251 #ifdef CONFIG_BNX2X_SRIOV
14252         .sriov_configure = bnx2x_sriov_configure,
14253 #endif
14254         .shutdown    = bnx2x_shutdown,
14255 };
14256
14257 static int __init bnx2x_init(void)
14258 {
14259         int ret;
14260
14261         pr_info("%s", version);
14262
14263         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14264         if (bnx2x_wq == NULL) {
14265                 pr_err("Cannot create workqueue\n");
14266                 return -ENOMEM;
14267         }
14268         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14269         if (!bnx2x_iov_wq) {
14270                 pr_err("Cannot create iov workqueue\n");
14271                 destroy_workqueue(bnx2x_wq);
14272                 return -ENOMEM;
14273         }
14274
14275         ret = pci_register_driver(&bnx2x_pci_driver);
14276         if (ret) {
14277                 pr_err("Cannot register driver\n");
14278                 destroy_workqueue(bnx2x_wq);
14279                 destroy_workqueue(bnx2x_iov_wq);
14280         }
14281         return ret;
14282 }
14283
14284 static void __exit bnx2x_cleanup(void)
14285 {
14286         struct list_head *pos, *q;
14287
14288         pci_unregister_driver(&bnx2x_pci_driver);
14289
14290         destroy_workqueue(bnx2x_wq);
14291         destroy_workqueue(bnx2x_iov_wq);
14292
14293         /* Free globally allocated resources */
14294         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14295                 struct bnx2x_prev_path_list *tmp =
14296                         list_entry(pos, struct bnx2x_prev_path_list, list);
14297                 list_del(pos);
14298                 kfree(tmp);
14299         }
14300 }
14301
14302 void bnx2x_notify_link_changed(struct bnx2x *bp)
14303 {
14304         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14305 }
14306
14307 module_init(bnx2x_init);
14308 module_exit(bnx2x_cleanup);
14309
14310 /**
14311  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14312  *
14313  * @bp:         driver handle
14314  * @set:        set or clear the CAM entry
14315  *
14316  * This function will wait until the ramrod completion returns.
14317  * Return 0 if success, -ENODEV if ramrod doesn't return.
14318  */
14319 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14320 {
14321         unsigned long ramrod_flags = 0;
14322
14323         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14324         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14325                                  &bp->iscsi_l2_mac_obj, true,
14326                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14327 }
14328
14329 /* count denotes the number of new completions we have seen */
14330 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14331 {
14332         struct eth_spe *spe;
14333         int cxt_index, cxt_offset;
14334
14335 #ifdef BNX2X_STOP_ON_ERROR
14336         if (unlikely(bp->panic))
14337                 return;
14338 #endif
14339
14340         spin_lock_bh(&bp->spq_lock);
14341         BUG_ON(bp->cnic_spq_pending < count);
14342         bp->cnic_spq_pending -= count;
14343
14344         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14345                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14346                                 & SPE_HDR_CONN_TYPE) >>
14347                                 SPE_HDR_CONN_TYPE_SHIFT;
14348                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14349                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14350
14351                 /* Set validation for iSCSI L2 client before sending SETUP
14352                  *  ramrod
14353                  */
14354                 if (type == ETH_CONNECTION_TYPE) {
14355                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14356                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14357                                         ILT_PAGE_CIDS;
14358                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14359                                         (cxt_index * ILT_PAGE_CIDS);
14360                                 bnx2x_set_ctx_validation(bp,
14361                                         &bp->context[cxt_index].
14362                                                          vcxt[cxt_offset].eth,
14363                                         BNX2X_ISCSI_ETH_CID(bp));
14364                         }
14365                 }
14366
14367                 /*
14368                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14369                  * and in the air. We also check that number of outstanding
14370                  * COMMON ramrods is not more than the EQ and SPQ can
14371                  * accommodate.
14372                  */
14373                 if (type == ETH_CONNECTION_TYPE) {
14374                         if (!atomic_read(&bp->cq_spq_left))
14375                                 break;
14376                         else
14377                                 atomic_dec(&bp->cq_spq_left);
14378                 } else if (type == NONE_CONNECTION_TYPE) {
14379                         if (!atomic_read(&bp->eq_spq_left))
14380                                 break;
14381                         else
14382                                 atomic_dec(&bp->eq_spq_left);
14383                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14384                            (type == FCOE_CONNECTION_TYPE)) {
14385                         if (bp->cnic_spq_pending >=
14386                             bp->cnic_eth_dev.max_kwqe_pending)
14387                                 break;
14388                         else
14389                                 bp->cnic_spq_pending++;
14390                 } else {
14391                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14392                         bnx2x_panic();
14393                         break;
14394                 }
14395
14396                 spe = bnx2x_sp_get_next(bp);
14397                 *spe = *bp->cnic_kwq_cons;
14398
14399                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14400                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14401
14402                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14403                         bp->cnic_kwq_cons = bp->cnic_kwq;
14404                 else
14405                         bp->cnic_kwq_cons++;
14406         }
14407         bnx2x_sp_prod_update(bp);
14408         spin_unlock_bh(&bp->spq_lock);
14409 }
14410
14411 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14412                                struct kwqe_16 *kwqes[], u32 count)
14413 {
14414         struct bnx2x *bp = netdev_priv(dev);
14415         int i;
14416
14417 #ifdef BNX2X_STOP_ON_ERROR
14418         if (unlikely(bp->panic)) {
14419                 BNX2X_ERR("Can't post to SP queue while panic\n");
14420                 return -EIO;
14421         }
14422 #endif
14423
14424         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14425             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14426                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14427                 return -EAGAIN;
14428         }
14429
14430         spin_lock_bh(&bp->spq_lock);
14431
14432         for (i = 0; i < count; i++) {
14433                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14434
14435                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14436                         break;
14437
14438                 *bp->cnic_kwq_prod = *spe;
14439
14440                 bp->cnic_kwq_pending++;
14441
14442                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14443                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14444                    spe->data.update_data_addr.hi,
14445                    spe->data.update_data_addr.lo,
14446                    bp->cnic_kwq_pending);
14447
14448                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14449                         bp->cnic_kwq_prod = bp->cnic_kwq;
14450                 else
14451                         bp->cnic_kwq_prod++;
14452         }
14453
14454         spin_unlock_bh(&bp->spq_lock);
14455
14456         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14457                 bnx2x_cnic_sp_post(bp, 0);
14458
14459         return i;
14460 }
14461
14462 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14463 {
14464         struct cnic_ops *c_ops;
14465         int rc = 0;
14466
14467         mutex_lock(&bp->cnic_mutex);
14468         c_ops = rcu_dereference_protected(bp->cnic_ops,
14469                                           lockdep_is_held(&bp->cnic_mutex));
14470         if (c_ops)
14471                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14472         mutex_unlock(&bp->cnic_mutex);
14473
14474         return rc;
14475 }
14476
14477 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14478 {
14479         struct cnic_ops *c_ops;
14480         int rc = 0;
14481
14482         rcu_read_lock();
14483         c_ops = rcu_dereference(bp->cnic_ops);
14484         if (c_ops)
14485                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14486         rcu_read_unlock();
14487
14488         return rc;
14489 }
14490
14491 /*
14492  * for commands that have no data
14493  */
14494 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14495 {
14496         struct cnic_ctl_info ctl = {0};
14497
14498         ctl.cmd = cmd;
14499
14500         return bnx2x_cnic_ctl_send(bp, &ctl);
14501 }
14502
14503 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14504 {
14505         struct cnic_ctl_info ctl = {0};
14506
14507         /* first we tell CNIC and only then we count this as a completion */
14508         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14509         ctl.data.comp.cid = cid;
14510         ctl.data.comp.error = err;
14511
14512         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14513         bnx2x_cnic_sp_post(bp, 0);
14514 }
14515
14516 /* Called with netif_addr_lock_bh() taken.
14517  * Sets an rx_mode config for an iSCSI ETH client.
14518  * Doesn't block.
14519  * Completion should be checked outside.
14520  */
14521 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14522 {
14523         unsigned long accept_flags = 0, ramrod_flags = 0;
14524         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14525         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14526
14527         if (start) {
14528                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14529                  * because it's the only way for UIO Queue to accept
14530                  * multicasts (in non-promiscuous mode only one Queue per
14531                  * function will receive multicast packets (leading in our
14532                  * case).
14533                  */
14534                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14535                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14536                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14537                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14538
14539                 /* Clear STOP_PENDING bit if START is requested */
14540                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14541
14542                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14543         } else
14544                 /* Clear START_PENDING bit if STOP is requested */
14545                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14546
14547         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14548                 set_bit(sched_state, &bp->sp_state);
14549         else {
14550                 __set_bit(RAMROD_RX, &ramrod_flags);
14551                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14552                                     ramrod_flags);
14553         }
14554 }
14555
14556 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14557 {
14558         struct bnx2x *bp = netdev_priv(dev);
14559         int rc = 0;
14560
14561         switch (ctl->cmd) {
14562         case DRV_CTL_CTXTBL_WR_CMD: {
14563                 u32 index = ctl->data.io.offset;
14564                 dma_addr_t addr = ctl->data.io.dma_addr;
14565
14566                 bnx2x_ilt_wr(bp, index, addr);
14567                 break;
14568         }
14569
14570         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14571                 int count = ctl->data.credit.credit_count;
14572
14573                 bnx2x_cnic_sp_post(bp, count);
14574                 break;
14575         }
14576
14577         /* rtnl_lock is held.  */
14578         case DRV_CTL_START_L2_CMD: {
14579                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14580                 unsigned long sp_bits = 0;
14581
14582                 /* Configure the iSCSI classification object */
14583                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14584                                    cp->iscsi_l2_client_id,
14585                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14586                                    bnx2x_sp(bp, mac_rdata),
14587                                    bnx2x_sp_mapping(bp, mac_rdata),
14588                                    BNX2X_FILTER_MAC_PENDING,
14589                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14590                                    &bp->macs_pool);
14591
14592                 /* Set iSCSI MAC address */
14593                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14594                 if (rc)
14595                         break;
14596
14597                 mmiowb();
14598                 barrier();
14599
14600                 /* Start accepting on iSCSI L2 ring */
14601
14602                 netif_addr_lock_bh(dev);
14603                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14604                 netif_addr_unlock_bh(dev);
14605
14606                 /* bits to wait on */
14607                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14608                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14609
14610                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14611                         BNX2X_ERR("rx_mode completion timed out!\n");
14612
14613                 break;
14614         }
14615
14616         /* rtnl_lock is held.  */
14617         case DRV_CTL_STOP_L2_CMD: {
14618                 unsigned long sp_bits = 0;
14619
14620                 /* Stop accepting on iSCSI L2 ring */
14621                 netif_addr_lock_bh(dev);
14622                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14623                 netif_addr_unlock_bh(dev);
14624
14625                 /* bits to wait on */
14626                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14627                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14628
14629                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14630                         BNX2X_ERR("rx_mode completion timed out!\n");
14631
14632                 mmiowb();
14633                 barrier();
14634
14635                 /* Unset iSCSI L2 MAC */
14636                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14637                                         BNX2X_ISCSI_ETH_MAC, true);
14638                 break;
14639         }
14640         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14641                 int count = ctl->data.credit.credit_count;
14642
14643                 smp_mb__before_atomic();
14644                 atomic_add(count, &bp->cq_spq_left);
14645                 smp_mb__after_atomic();
14646                 break;
14647         }
14648         case DRV_CTL_ULP_REGISTER_CMD: {
14649                 int ulp_type = ctl->data.register_data.ulp_type;
14650
14651                 if (CHIP_IS_E3(bp)) {
14652                         int idx = BP_FW_MB_IDX(bp);
14653                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14654                         int path = BP_PATH(bp);
14655                         int port = BP_PORT(bp);
14656                         int i;
14657                         u32 scratch_offset;
14658                         u32 *host_addr;
14659
14660                         /* first write capability to shmem2 */
14661                         if (ulp_type == CNIC_ULP_ISCSI)
14662                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14663                         else if (ulp_type == CNIC_ULP_FCOE)
14664                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14665                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14666
14667                         if ((ulp_type != CNIC_ULP_FCOE) ||
14668                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14669                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14670                                 break;
14671
14672                         /* if reached here - should write fcoe capabilities */
14673                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14674                         if (!scratch_offset)
14675                                 break;
14676                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14677                                                    fcoe_features[path][port]);
14678                         host_addr = (u32 *) &(ctl->data.register_data.
14679                                               fcoe_features);
14680                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14681                              i += 4)
14682                                 REG_WR(bp, scratch_offset + i,
14683                                        *(host_addr + i/4));
14684                 }
14685                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14686                 break;
14687         }
14688
14689         case DRV_CTL_ULP_UNREGISTER_CMD: {
14690                 int ulp_type = ctl->data.ulp_type;
14691
14692                 if (CHIP_IS_E3(bp)) {
14693                         int idx = BP_FW_MB_IDX(bp);
14694                         u32 cap;
14695
14696                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14697                         if (ulp_type == CNIC_ULP_ISCSI)
14698                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14699                         else if (ulp_type == CNIC_ULP_FCOE)
14700                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14701                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14702                 }
14703                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14704                 break;
14705         }
14706
14707         default:
14708                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14709                 rc = -EINVAL;
14710         }
14711
14712         /* For storage-only interfaces, change driver state */
14713         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14714                 switch (ctl->drv_state) {
14715                 case DRV_NOP:
14716                         break;
14717                 case DRV_ACTIVE:
14718                         bnx2x_set_os_driver_state(bp,
14719                                                   OS_DRIVER_STATE_ACTIVE);
14720                         break;
14721                 case DRV_INACTIVE:
14722                         bnx2x_set_os_driver_state(bp,
14723                                                   OS_DRIVER_STATE_DISABLED);
14724                         break;
14725                 case DRV_UNLOADED:
14726                         bnx2x_set_os_driver_state(bp,
14727                                                   OS_DRIVER_STATE_NOT_LOADED);
14728                         break;
14729                 default:
14730                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14731                 }
14732         }
14733
14734         return rc;
14735 }
14736
14737 static int bnx2x_get_fc_npiv(struct net_device *dev,
14738                              struct cnic_fc_npiv_tbl *cnic_tbl)
14739 {
14740         struct bnx2x *bp = netdev_priv(dev);
14741         struct bdn_fc_npiv_tbl *tbl = NULL;
14742         u32 offset, entries;
14743         int rc = -EINVAL;
14744         int i;
14745
14746         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14747                 goto out;
14748
14749         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14750
14751         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14752         if (!tbl) {
14753                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14754                 goto out;
14755         }
14756
14757         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14758         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14759
14760         /* Read the table contents from nvram */
14761         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14762                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14763                 goto out;
14764         }
14765
14766         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14767          * the number of entries back to cpu endianness.
14768          */
14769         entries = tbl->fc_npiv_cfg.num_of_npiv;
14770         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14771         tbl->fc_npiv_cfg.num_of_npiv = entries;
14772
14773         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14774                 DP(BNX2X_MSG_MCP,
14775                    "No FC-NPIV table [valid, simply not present]\n");
14776                 goto out;
14777         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14778                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14779                           tbl->fc_npiv_cfg.num_of_npiv);
14780                 goto out;
14781         } else {
14782                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14783                    tbl->fc_npiv_cfg.num_of_npiv);
14784         }
14785
14786         /* Copy the data into cnic-provided struct */
14787         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14788         for (i = 0; i < cnic_tbl->count; i++) {
14789                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14790                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14791         }
14792
14793         rc = 0;
14794 out:
14795         kfree(tbl);
14796         return rc;
14797 }
14798
14799 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14800 {
14801         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14802
14803         if (bp->flags & USING_MSIX_FLAG) {
14804                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14805                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14806                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14807         } else {
14808                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14809                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14810         }
14811         if (!CHIP_IS_E1x(bp))
14812                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14813         else
14814                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14815
14816         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14817         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14818         cp->irq_arr[1].status_blk = bp->def_status_blk;
14819         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14820         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14821
14822         cp->num_irq = 2;
14823 }
14824
14825 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14826 {
14827         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14828
14829         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14830                              bnx2x_cid_ilt_lines(bp);
14831         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14832         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14833         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14834
14835         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14836            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14837            cp->iscsi_l2_cid);
14838
14839         if (NO_ISCSI_OOO(bp))
14840                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14841 }
14842
14843 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14844                                void *data)
14845 {
14846         struct bnx2x *bp = netdev_priv(dev);
14847         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14848         int rc;
14849
14850         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14851
14852         if (ops == NULL) {
14853                 BNX2X_ERR("NULL ops received\n");
14854                 return -EINVAL;
14855         }
14856
14857         if (!CNIC_SUPPORT(bp)) {
14858                 BNX2X_ERR("Can't register CNIC when not supported\n");
14859                 return -EOPNOTSUPP;
14860         }
14861
14862         if (!CNIC_LOADED(bp)) {
14863                 rc = bnx2x_load_cnic(bp);
14864                 if (rc) {
14865                         BNX2X_ERR("CNIC-related load failed\n");
14866                         return rc;
14867                 }
14868         }
14869
14870         bp->cnic_enabled = true;
14871
14872         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14873         if (!bp->cnic_kwq)
14874                 return -ENOMEM;
14875
14876         bp->cnic_kwq_cons = bp->cnic_kwq;
14877         bp->cnic_kwq_prod = bp->cnic_kwq;
14878         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14879
14880         bp->cnic_spq_pending = 0;
14881         bp->cnic_kwq_pending = 0;
14882
14883         bp->cnic_data = data;
14884
14885         cp->num_irq = 0;
14886         cp->drv_state |= CNIC_DRV_STATE_REGD;
14887         cp->iro_arr = bp->iro_arr;
14888
14889         bnx2x_setup_cnic_irq_info(bp);
14890
14891         rcu_assign_pointer(bp->cnic_ops, ops);
14892
14893         /* Schedule driver to read CNIC driver versions */
14894         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14895
14896         return 0;
14897 }
14898
14899 static int bnx2x_unregister_cnic(struct net_device *dev)
14900 {
14901         struct bnx2x *bp = netdev_priv(dev);
14902         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14903
14904         mutex_lock(&bp->cnic_mutex);
14905         cp->drv_state = 0;
14906         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14907         mutex_unlock(&bp->cnic_mutex);
14908         synchronize_rcu();
14909         bp->cnic_enabled = false;
14910         kfree(bp->cnic_kwq);
14911         bp->cnic_kwq = NULL;
14912
14913         return 0;
14914 }
14915
14916 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14917 {
14918         struct bnx2x *bp = netdev_priv(dev);
14919         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14920
14921         /* If both iSCSI and FCoE are disabled - return NULL in
14922          * order to indicate CNIC that it should not try to work
14923          * with this device.
14924          */
14925         if (NO_ISCSI(bp) && NO_FCOE(bp))
14926                 return NULL;
14927
14928         cp->drv_owner = THIS_MODULE;
14929         cp->chip_id = CHIP_ID(bp);
14930         cp->pdev = bp->pdev;
14931         cp->io_base = bp->regview;
14932         cp->io_base2 = bp->doorbells;
14933         cp->max_kwqe_pending = 8;
14934         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14935         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14936                              bnx2x_cid_ilt_lines(bp);
14937         cp->ctx_tbl_len = CNIC_ILT_LINES;
14938         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14939         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14940         cp->drv_ctl = bnx2x_drv_ctl;
14941         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
14942         cp->drv_register_cnic = bnx2x_register_cnic;
14943         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14944         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14945         cp->iscsi_l2_client_id =
14946                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14947         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14948
14949         if (NO_ISCSI_OOO(bp))
14950                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14951
14952         if (NO_ISCSI(bp))
14953                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14954
14955         if (NO_FCOE(bp))
14956                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14957
14958         BNX2X_DEV_INFO(
14959                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14960            cp->ctx_blk_size,
14961            cp->ctx_tbl_offset,
14962            cp->ctx_tbl_len,
14963            cp->starting_cid);
14964         return cp;
14965 }
14966
14967 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14968 {
14969         struct bnx2x *bp = fp->bp;
14970         u32 offset = BAR_USTRORM_INTMEM;
14971
14972         if (IS_VF(bp))
14973                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14974         else if (!CHIP_IS_E1x(bp))
14975                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14976         else
14977                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14978
14979         return offset;
14980 }
14981
14982 /* called only on E1H or E2.
14983  * When pretending to be PF, the pretend value is the function number 0...7
14984  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14985  * combination
14986  */
14987 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14988 {
14989         u32 pretend_reg;
14990
14991         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14992                 return -1;
14993
14994         /* get my own pretend register */
14995         pretend_reg = bnx2x_get_pretend_reg(bp);
14996         REG_WR(bp, pretend_reg, pretend_func_val);
14997         REG_RD(bp, pretend_reg);
14998         return 0;
14999 }
15000
15001 static void bnx2x_ptp_task(struct work_struct *work)
15002 {
15003         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15004         int port = BP_PORT(bp);
15005         u32 val_seq;
15006         u64 timestamp, ns;
15007         struct skb_shared_hwtstamps shhwtstamps;
15008
15009         /* Read Tx timestamp registers */
15010         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15011                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15012         if (val_seq & 0x10000) {
15013                 /* There is a valid timestamp value */
15014                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15015                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15016                 timestamp <<= 32;
15017                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15018                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15019                 /* Reset timestamp register to allow new timestamp */
15020                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15021                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15022                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15023
15024                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15025                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15026                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15027                 dev_kfree_skb_any(bp->ptp_tx_skb);
15028                 bp->ptp_tx_skb = NULL;
15029
15030                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15031                    timestamp, ns);
15032         } else {
15033                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15034                 /* Reschedule to keep checking for a valid timestamp value */
15035                 schedule_work(&bp->ptp_task);
15036         }
15037 }
15038
15039 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15040 {
15041         int port = BP_PORT(bp);
15042         u64 timestamp, ns;
15043
15044         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15045                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15046         timestamp <<= 32;
15047         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15048                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15049
15050         /* Reset timestamp register to allow new timestamp */
15051         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15052                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15053
15054         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15055
15056         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15057
15058         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15059            timestamp, ns);
15060 }
15061
15062 /* Read the PHC */
15063 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15064 {
15065         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15066         int port = BP_PORT(bp);
15067         u32 wb_data[2];
15068         u64 phc_cycles;
15069
15070         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15071                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15072         phc_cycles = wb_data[1];
15073         phc_cycles = (phc_cycles << 32) + wb_data[0];
15074
15075         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15076
15077         return phc_cycles;
15078 }
15079
15080 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15081 {
15082         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15083         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15084         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15085         bp->cyclecounter.shift = 1;
15086         bp->cyclecounter.mult = 1;
15087 }
15088
15089 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15090 {
15091         struct bnx2x_func_state_params func_params = {NULL};
15092         struct bnx2x_func_set_timesync_params *set_timesync_params =
15093                 &func_params.params.set_timesync;
15094
15095         /* Prepare parameters for function state transitions */
15096         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15097         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15098
15099         func_params.f_obj = &bp->func_obj;
15100         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15101
15102         /* Function parameters */
15103         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15104         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15105
15106         return bnx2x_func_state_change(bp, &func_params);
15107 }
15108
15109 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15110 {
15111         struct bnx2x_queue_state_params q_params;
15112         int rc, i;
15113
15114         /* send queue update ramrod to enable PTP packets */
15115         memset(&q_params, 0, sizeof(q_params));
15116         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15117         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15118         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15119                   &q_params.params.update.update_flags);
15120         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15121                   &q_params.params.update.update_flags);
15122
15123         /* send the ramrod on all the queues of the PF */
15124         for_each_eth_queue(bp, i) {
15125                 struct bnx2x_fastpath *fp = &bp->fp[i];
15126
15127                 /* Set the appropriate Queue object */
15128                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15129
15130                 /* Update the Queue state */
15131                 rc = bnx2x_queue_state_change(bp, &q_params);
15132                 if (rc) {
15133                         BNX2X_ERR("Failed to enable PTP packets\n");
15134                         return rc;
15135                 }
15136         }
15137
15138         return 0;
15139 }
15140
15141 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15142 {
15143         int port = BP_PORT(bp);
15144         int rc;
15145
15146         if (!bp->hwtstamp_ioctl_called)
15147                 return 0;
15148
15149         switch (bp->tx_type) {
15150         case HWTSTAMP_TX_ON:
15151                 bp->flags |= TX_TIMESTAMPING_EN;
15152                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15153                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15154                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15155                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15156                 break;
15157         case HWTSTAMP_TX_ONESTEP_SYNC:
15158                 BNX2X_ERR("One-step timestamping is not supported\n");
15159                 return -ERANGE;
15160         }
15161
15162         switch (bp->rx_filter) {
15163         case HWTSTAMP_FILTER_NONE:
15164                 break;
15165         case HWTSTAMP_FILTER_ALL:
15166         case HWTSTAMP_FILTER_SOME:
15167                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15168                 break;
15169         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15170         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15171         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15172                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15173                 /* Initialize PTP detection for UDP/IPv4 events */
15174                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15175                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15176                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15177                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15178                 break;
15179         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15180         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15181         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15182                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15183                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15184                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15185                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15186                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15187                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15188                 break;
15189         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15190         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15191         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15192                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15193                 /* Initialize PTP detection L2 events */
15194                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15195                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15196                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15197                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15198
15199                 break;
15200         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15201         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15202         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15203                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15204                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15205                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15206                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15207                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15208                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15209                 break;
15210         }
15211
15212         /* Indicate to FW that this PF expects recorded PTP packets */
15213         rc = bnx2x_enable_ptp_packets(bp);
15214         if (rc)
15215                 return rc;
15216
15217         /* Enable sending PTP packets to host */
15218         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15219                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15220
15221         return 0;
15222 }
15223
15224 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15225 {
15226         struct hwtstamp_config config;
15227         int rc;
15228
15229         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15230
15231         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15232                 return -EFAULT;
15233
15234         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15235            config.tx_type, config.rx_filter);
15236
15237         if (config.flags) {
15238                 BNX2X_ERR("config.flags is reserved for future use\n");
15239                 return -EINVAL;
15240         }
15241
15242         bp->hwtstamp_ioctl_called = 1;
15243         bp->tx_type = config.tx_type;
15244         bp->rx_filter = config.rx_filter;
15245
15246         rc = bnx2x_configure_ptp_filters(bp);
15247         if (rc)
15248                 return rc;
15249
15250         config.rx_filter = bp->rx_filter;
15251
15252         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15253                 -EFAULT : 0;
15254 }
15255
15256 /* Configures HW for PTP */
15257 static int bnx2x_configure_ptp(struct bnx2x *bp)
15258 {
15259         int rc, port = BP_PORT(bp);
15260         u32 wb_data[2];
15261
15262         /* Reset PTP event detection rules - will be configured in the IOCTL */
15263         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15264                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15265         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15266                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15267         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15268                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15269         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15270                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15271
15272         /* Disable PTP packets to host - will be configured in the IOCTL*/
15273         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15274                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15275
15276         /* Enable the PTP feature */
15277         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15278                NIG_REG_P0_PTP_EN, 0x3F);
15279
15280         /* Enable the free-running counter */
15281         wb_data[0] = 0;
15282         wb_data[1] = 0;
15283         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15284
15285         /* Reset drift register (offset register is not reset) */
15286         rc = bnx2x_send_reset_timesync_ramrod(bp);
15287         if (rc) {
15288                 BNX2X_ERR("Failed to reset PHC drift register\n");
15289                 return -EFAULT;
15290         }
15291
15292         /* Reset possibly old timestamps */
15293         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15294                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15295         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15296                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15297
15298         return 0;
15299 }
15300
15301 /* Called during load, to initialize PTP-related stuff */
15302 void bnx2x_init_ptp(struct bnx2x *bp)
15303 {
15304         int rc;
15305
15306         /* Configure PTP in HW */
15307         rc = bnx2x_configure_ptp(bp);
15308         if (rc) {
15309                 BNX2X_ERR("Stopping PTP initialization\n");
15310                 return;
15311         }
15312
15313         /* Init work queue for Tx timestamping */
15314         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15315
15316         /* Init cyclecounter and timecounter. This is done only in the first
15317          * load. If done in every load, PTP application will fail when doing
15318          * unload / load (e.g. MTU change) while it is running.
15319          */
15320         if (!bp->timecounter_init_done) {
15321                 bnx2x_init_cyclecounter(bp);
15322                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15323                                  ktime_to_ns(ktime_get_real()));
15324                 bp->timecounter_init_done = 1;
15325         }
15326
15327         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15328 }