1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
63 #include "bnx2x_init.h"
64 #include "bnx2x_init_ops.h"
65 #include "bnx2x_cmn.h"
66 #include "bnx2x_vfpf.h"
67 #include "bnx2x_dcb.h"
69 #include <linux/firmware.h>
70 #include "bnx2x_fw_file_hdr.h"
73 #define FW_FILE_NAME_E1 "/*(DEBLOBBED)*/"
74 #define FW_FILE_NAME_E1H "/*(DEBLOBBED)*/"
75 #define FW_FILE_NAME_E2 "/*(DEBLOBBED)*/"
76 #define bnx2x_init_block(bp, start, end) \
77 return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
80 /* Time in jiffies before concluding the transmitter is hung */
81 #define TX_TIMEOUT (5*HZ)
83 static char version[] =
84 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
85 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87 MODULE_AUTHOR("Eliezer Tamir");
88 MODULE_DESCRIPTION("QLogic "
89 "BCM57710/57711/57711E/"
90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
91 "57840/57840_MF Driver");
92 MODULE_LICENSE("GPL");
93 MODULE_VERSION(DRV_MODULE_VERSION);
97 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
98 MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, S_IRUGO);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 module_param(int_mode, int, S_IRUGO);
107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110 static int dropless_fc;
111 module_param(dropless_fc, int, S_IRUGO);
112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 static int mrrs = -1;
115 module_param(mrrs, int, S_IRUGO);
116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119 module_param(debug, int, S_IRUGO);
120 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 static struct workqueue_struct *bnx2x_wq;
123 struct workqueue_struct *bnx2x_iov_wq;
125 struct bnx2x_mac_vals {
136 enum bnx2x_board_type {
160 /* indexed by board_type, above */
164 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
165 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
166 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
167 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
168 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
169 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
170 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
171 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
172 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
173 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
174 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
175 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
176 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
177 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
178 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
179 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
180 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
181 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
182 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
183 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
184 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
187 #ifndef PCI_DEVICE_ID_NX2_57710
188 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
190 #ifndef PCI_DEVICE_ID_NX2_57711
191 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
193 #ifndef PCI_DEVICE_ID_NX2_57711E
194 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
196 #ifndef PCI_DEVICE_ID_NX2_57712
197 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
199 #ifndef PCI_DEVICE_ID_NX2_57712_MF
200 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
202 #ifndef PCI_DEVICE_ID_NX2_57712_VF
203 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
205 #ifndef PCI_DEVICE_ID_NX2_57800
206 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
208 #ifndef PCI_DEVICE_ID_NX2_57800_MF
209 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
211 #ifndef PCI_DEVICE_ID_NX2_57800_VF
212 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
214 #ifndef PCI_DEVICE_ID_NX2_57810
215 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
217 #ifndef PCI_DEVICE_ID_NX2_57810_MF
218 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
220 #ifndef PCI_DEVICE_ID_NX2_57840_O
221 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
223 #ifndef PCI_DEVICE_ID_NX2_57810_VF
224 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
226 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
227 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
229 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
230 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
232 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
233 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
235 #ifndef PCI_DEVICE_ID_NX2_57840_MF
236 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
238 #ifndef PCI_DEVICE_ID_NX2_57840_VF
239 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
241 #ifndef PCI_DEVICE_ID_NX2_57811
242 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
244 #ifndef PCI_DEVICE_ID_NX2_57811_MF
245 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
247 #ifndef PCI_DEVICE_ID_NX2_57811_VF
248 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
251 static const struct pci_device_id bnx2x_pci_tbl[] = {
252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
265 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
270 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
272 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
279 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
281 /* Global resources for unloading a previously loaded device */
282 #define BNX2X_PREV_WAIT_NEEDED 1
283 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
284 static LIST_HEAD(bnx2x_prev_list);
286 /* Forward declaration */
287 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
288 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
289 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
291 /****************************************************************************
292 * General service functions
293 ****************************************************************************/
295 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
297 static void __storm_memset_dma_mapping(struct bnx2x *bp,
298 u32 addr, dma_addr_t mapping)
300 REG_WR(bp, addr, U64_LO(mapping));
301 REG_WR(bp, addr + 4, U64_HI(mapping));
304 static void storm_memset_spq_addr(struct bnx2x *bp,
305 dma_addr_t mapping, u16 abs_fid)
307 u32 addr = XSEM_REG_FAST_MEMORY +
308 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
310 __storm_memset_dma_mapping(bp, addr, mapping);
313 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
316 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
318 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
320 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
322 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
326 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
329 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
331 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
333 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
335 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
339 static void storm_memset_eq_data(struct bnx2x *bp,
340 struct event_ring_data *eq_data,
343 size_t size = sizeof(struct event_ring_data);
345 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
347 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
350 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
353 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
354 REG_WR16(bp, addr, eq_prod);
358 * locking is done by mcp
360 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
363 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
364 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
365 PCICFG_VENDOR_ID_OFFSET);
368 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
372 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
373 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
374 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
375 PCICFG_VENDOR_ID_OFFSET);
380 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
381 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
382 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
383 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
384 #define DMAE_DP_DST_NONE "dst_addr [none]"
386 static void bnx2x_dp_dmae(struct bnx2x *bp,
387 struct dmae_command *dmae, int msglvl)
389 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
392 switch (dmae->opcode & DMAE_COMMAND_DST) {
393 case DMAE_CMD_DST_PCI:
394 if (src_type == DMAE_CMD_SRC_PCI)
395 DP(msglvl, "DMAE: opcode 0x%08x\n"
396 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
397 "comp_addr [%x:%08x], comp_val 0x%08x\n",
398 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
399 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
400 dmae->comp_addr_hi, dmae->comp_addr_lo,
403 DP(msglvl, "DMAE: opcode 0x%08x\n"
404 "src [%08x], len [%d*4], dst [%x:%08x]\n"
405 "comp_addr [%x:%08x], comp_val 0x%08x\n",
406 dmae->opcode, dmae->src_addr_lo >> 2,
407 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
408 dmae->comp_addr_hi, dmae->comp_addr_lo,
411 case DMAE_CMD_DST_GRC:
412 if (src_type == DMAE_CMD_SRC_PCI)
413 DP(msglvl, "DMAE: opcode 0x%08x\n"
414 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
415 "comp_addr [%x:%08x], comp_val 0x%08x\n",
416 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
417 dmae->len, dmae->dst_addr_lo >> 2,
418 dmae->comp_addr_hi, dmae->comp_addr_lo,
421 DP(msglvl, "DMAE: opcode 0x%08x\n"
422 "src [%08x], len [%d*4], dst [%08x]\n"
423 "comp_addr [%x:%08x], comp_val 0x%08x\n",
424 dmae->opcode, dmae->src_addr_lo >> 2,
425 dmae->len, dmae->dst_addr_lo >> 2,
426 dmae->comp_addr_hi, dmae->comp_addr_lo,
430 if (src_type == DMAE_CMD_SRC_PCI)
431 DP(msglvl, "DMAE: opcode 0x%08x\n"
432 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
433 "comp_addr [%x:%08x] comp_val 0x%08x\n",
434 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
435 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
440 "comp_addr [%x:%08x] comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_lo >> 2,
442 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
447 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
448 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
449 i, *(((u32 *)dmae) + i));
452 /* copy command into DMAE command memory and set DMAE command go */
453 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
458 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
459 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
460 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
462 REG_WR(bp, dmae_reg_go_c[idx], 1);
465 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
467 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
471 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
473 return opcode & ~DMAE_CMD_SRC_RESET;
476 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
477 bool with_comp, u8 comp_type)
481 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
482 (dst_type << DMAE_COMMAND_DST_SHIFT));
484 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
486 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
487 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
488 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
489 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
492 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
494 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
497 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
501 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
502 struct dmae_command *dmae,
503 u8 src_type, u8 dst_type)
505 memset(dmae, 0, sizeof(struct dmae_command));
508 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
509 true, DMAE_COMP_PCI);
511 /* fill in the completion parameters */
512 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
513 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
514 dmae->comp_val = DMAE_COMP_VAL;
517 /* issue a dmae command over the init-channel and wait for completion */
518 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
521 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
524 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
526 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
527 * as long as this code is called both from syscall context and
528 * from ndo_set_rx_mode() flow that may be called from BH.
531 spin_lock_bh(&bp->dmae_lock);
533 /* reset completion */
536 /* post the command on the channel used for initializations */
537 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
539 /* wait for completion */
541 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
544 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
545 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
546 BNX2X_ERR("DMAE timeout!\n");
553 if (*comp & DMAE_PCI_ERR_FLAG) {
554 BNX2X_ERR("DMAE PCI error!\n");
560 spin_unlock_bh(&bp->dmae_lock);
565 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
569 struct dmae_command dmae;
571 if (!bp->dmae_ready) {
572 u32 *data = bnx2x_sp(bp, wb_data[0]);
575 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
577 bnx2x_init_str_wr(bp, dst_addr, data, len32);
581 /* set opcode and fixed command fields */
582 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
584 /* fill in addresses and len */
585 dmae.src_addr_lo = U64_LO(dma_addr);
586 dmae.src_addr_hi = U64_HI(dma_addr);
587 dmae.dst_addr_lo = dst_addr >> 2;
588 dmae.dst_addr_hi = 0;
591 /* issue the command and wait for completion */
592 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
594 BNX2X_ERR("DMAE returned failure %d\n", rc);
595 #ifdef BNX2X_STOP_ON_ERROR
601 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
604 struct dmae_command dmae;
606 if (!bp->dmae_ready) {
607 u32 *data = bnx2x_sp(bp, wb_data[0]);
611 for (i = 0; i < len32; i++)
612 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
614 for (i = 0; i < len32; i++)
615 data[i] = REG_RD(bp, src_addr + i*4);
620 /* set opcode and fixed command fields */
621 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
623 /* fill in addresses and len */
624 dmae.src_addr_lo = src_addr >> 2;
625 dmae.src_addr_hi = 0;
626 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
627 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
630 /* issue the command and wait for completion */
631 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
633 BNX2X_ERR("DMAE returned failure %d\n", rc);
634 #ifdef BNX2X_STOP_ON_ERROR
640 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
643 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
646 while (len > dmae_wr_max) {
647 bnx2x_write_dmae(bp, phys_addr + offset,
648 addr + offset, dmae_wr_max);
649 offset += dmae_wr_max * 4;
653 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
665 #define REGS_IN_ENTRY 4
667 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
673 return XSTORM_ASSERT_LIST_OFFSET(entry);
675 return TSTORM_ASSERT_LIST_OFFSET(entry);
677 return CSTORM_ASSERT_LIST_OFFSET(entry);
679 return USTORM_ASSERT_LIST_OFFSET(entry);
682 BNX2X_ERR("unknown storm\n");
687 static int bnx2x_mc_assert(struct bnx2x *bp)
692 u32 regs[REGS_IN_ENTRY];
693 u32 bar_storm_intmem[STORMS_NUM] = {
699 u32 storm_assert_list_index[STORMS_NUM] = {
700 XSTORM_ASSERT_LIST_INDEX_OFFSET,
701 TSTORM_ASSERT_LIST_INDEX_OFFSET,
702 CSTORM_ASSERT_LIST_INDEX_OFFSET,
703 USTORM_ASSERT_LIST_INDEX_OFFSET
705 char *storms_string[STORMS_NUM] = {
712 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
713 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
714 storm_assert_list_index[storm]);
716 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
717 storms_string[storm], last_idx);
719 /* print the asserts */
720 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
721 /* read a single assert entry */
722 for (j = 0; j < REGS_IN_ENTRY; j++)
723 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
724 bnx2x_get_assert_list_entry(bp,
729 /* log entry if it contains a valid assert */
730 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
731 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
732 storms_string[storm], i, regs[3],
733 regs[2], regs[1], regs[0]);
741 BNX2X_ERR("Chip Revision: %s, /*(DEBLOBBED)*/\n",
742 CHIP_IS_E1(bp) ? "everest1" :
743 CHIP_IS_E1H(bp) ? "everest1h" :
744 CHIP_IS_E2(bp) ? "everest2" : "everest3"/*(DEBLOBBED)*/);
749 #define MCPR_TRACE_BUFFER_SIZE (0x800)
750 #define SCRATCH_BUFFER_SIZE(bp) \
751 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
753 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
759 u32 trace_shmem_base;
761 BNX2X_ERR("NO MCP - can not dump\n");
764 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
765 (bp->common.bc_ver & 0xff0000) >> 16,
766 (bp->common.bc_ver & 0xff00) >> 8,
767 (bp->common.bc_ver & 0xff));
769 if (pci_channel_offline(bp->pdev)) {
770 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
774 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
775 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
776 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
778 if (BP_PATH(bp) == 0)
779 trace_shmem_base = bp->common.shmem_base;
781 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
784 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
785 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
786 SCRATCH_BUFFER_SIZE(bp)) {
787 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
792 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
794 /* validate TRCB signature */
795 mark = REG_RD(bp, addr);
796 if (mark != MFW_TRACE_SIGNATURE) {
797 BNX2X_ERR("Trace buffer signature is missing.");
801 /* read cyclic buffer pointer */
803 mark = REG_RD(bp, addr);
804 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
805 if (mark >= trace_shmem_base || mark < addr + 4) {
806 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
809 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
813 /* dump buffer after the mark */
814 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
815 for (word = 0; word < 8; word++)
816 data[word] = htonl(REG_RD(bp, offset + 4*word));
818 pr_cont("%s", (char *)data);
821 /* dump buffer before the mark */
822 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
823 for (word = 0; word < 8; word++)
824 data[word] = htonl(REG_RD(bp, offset + 4*word));
826 pr_cont("%s", (char *)data);
828 printk("%s" "end of fw dump\n", lvl);
831 static void bnx2x_fw_dump(struct bnx2x *bp)
833 bnx2x_fw_dump_lvl(bp, KERN_ERR);
836 static void bnx2x_hc_int_disable(struct bnx2x *bp)
838 int port = BP_PORT(bp);
839 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
840 u32 val = REG_RD(bp, addr);
842 /* in E1 we must use only PCI configuration space to disable
843 * MSI/MSIX capability
844 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
846 if (CHIP_IS_E1(bp)) {
847 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
848 * Use mask register to prevent from HC sending interrupts
849 * after we exit the function
851 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
853 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
854 HC_CONFIG_0_REG_INT_LINE_EN_0 |
855 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
857 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
858 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
859 HC_CONFIG_0_REG_INT_LINE_EN_0 |
860 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
863 "write %x to HC %d (addr 0x%x)\n",
866 /* flush all outstanding writes */
869 REG_WR(bp, addr, val);
870 if (REG_RD(bp, addr) != val)
871 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
874 static void bnx2x_igu_int_disable(struct bnx2x *bp)
876 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
878 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
879 IGU_PF_CONF_INT_LINE_EN |
880 IGU_PF_CONF_ATTN_BIT_EN);
882 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
884 /* flush all outstanding writes */
887 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
888 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
889 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
892 static void bnx2x_int_disable(struct bnx2x *bp)
894 if (bp->common.int_block == INT_BLOCK_HC)
895 bnx2x_hc_int_disable(bp);
897 bnx2x_igu_int_disable(bp);
900 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
904 struct hc_sp_status_block_data sp_sb_data;
905 int func = BP_FUNC(bp);
906 #ifdef BNX2X_STOP_ON_ERROR
907 u16 start = 0, end = 0;
910 if (IS_PF(bp) && disable_int)
911 bnx2x_int_disable(bp);
913 bp->stats_state = STATS_STATE_DISABLED;
914 bp->eth_stats.unrecoverable_error++;
915 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
917 BNX2X_ERR("begin crash dump -----------------\n");
922 struct host_sp_status_block *def_sb = bp->def_status_blk;
923 int data_size, cstorm_offset;
925 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
926 bp->def_idx, bp->def_att_idx, bp->attn_state,
927 bp->spq_prod_idx, bp->stats_counter);
928 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
929 def_sb->atten_status_block.attn_bits,
930 def_sb->atten_status_block.attn_bits_ack,
931 def_sb->atten_status_block.status_block_id,
932 def_sb->atten_status_block.attn_bits_index);
934 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
936 def_sb->sp_sb.index_values[i],
937 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
939 data_size = sizeof(struct hc_sp_status_block_data) /
941 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
942 for (i = 0; i < data_size; i++)
943 *((u32 *)&sp_sb_data + i) =
944 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
947 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
948 sp_sb_data.igu_sb_id,
949 sp_sb_data.igu_seg_id,
950 sp_sb_data.p_func.pf_id,
951 sp_sb_data.p_func.vnic_id,
952 sp_sb_data.p_func.vf_id,
953 sp_sb_data.p_func.vf_valid,
957 for_each_eth_queue(bp, i) {
958 struct bnx2x_fastpath *fp = &bp->fp[i];
960 struct hc_status_block_data_e2 sb_data_e2;
961 struct hc_status_block_data_e1x sb_data_e1x;
962 struct hc_status_block_sm *hc_sm_p =
964 sb_data_e1x.common.state_machine :
965 sb_data_e2.common.state_machine;
966 struct hc_index_data *hc_index_p =
968 sb_data_e1x.index_data :
969 sb_data_e2.index_data;
972 struct bnx2x_fp_txdata txdata;
981 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
982 i, fp->rx_bd_prod, fp->rx_bd_cons,
984 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
985 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
986 fp->rx_sge_prod, fp->last_max_sge,
987 le16_to_cpu(fp->fp_hc_idx));
990 for_each_cos_in_tx_queue(fp, cos)
992 if (!fp->txdata_ptr[cos])
995 txdata = *fp->txdata_ptr[cos];
997 if (!txdata.tx_cons_sb)
1000 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1001 i, txdata.tx_pkt_prod,
1002 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1004 le16_to_cpu(*txdata.tx_cons_sb));
1007 loop = CHIP_IS_E1x(bp) ?
1008 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1015 BNX2X_ERR(" run indexes (");
1016 for (j = 0; j < HC_SB_MAX_SM; j++)
1018 fp->sb_running_index[j],
1019 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1021 BNX2X_ERR(" indexes (");
1022 for (j = 0; j < loop; j++)
1024 fp->sb_index_values[j],
1025 (j == loop - 1) ? ")" : " ");
1027 /* VF cannot access FW refelection for status block */
1032 data_size = CHIP_IS_E1x(bp) ?
1033 sizeof(struct hc_status_block_data_e1x) :
1034 sizeof(struct hc_status_block_data_e2);
1035 data_size /= sizeof(u32);
1036 sb_data_p = CHIP_IS_E1x(bp) ?
1037 (u32 *)&sb_data_e1x :
1039 /* copy sb data in here */
1040 for (j = 0; j < data_size; j++)
1041 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1042 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1045 if (!CHIP_IS_E1x(bp)) {
1046 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1047 sb_data_e2.common.p_func.pf_id,
1048 sb_data_e2.common.p_func.vf_id,
1049 sb_data_e2.common.p_func.vf_valid,
1050 sb_data_e2.common.p_func.vnic_id,
1051 sb_data_e2.common.same_igu_sb_1b,
1052 sb_data_e2.common.state);
1054 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1055 sb_data_e1x.common.p_func.pf_id,
1056 sb_data_e1x.common.p_func.vf_id,
1057 sb_data_e1x.common.p_func.vf_valid,
1058 sb_data_e1x.common.p_func.vnic_id,
1059 sb_data_e1x.common.same_igu_sb_1b,
1060 sb_data_e1x.common.state);
1064 for (j = 0; j < HC_SB_MAX_SM; j++) {
1065 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1066 j, hc_sm_p[j].__flags,
1067 hc_sm_p[j].igu_sb_id,
1068 hc_sm_p[j].igu_seg_id,
1069 hc_sm_p[j].time_to_expire,
1070 hc_sm_p[j].timer_value);
1074 for (j = 0; j < loop; j++) {
1075 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1076 hc_index_p[j].flags,
1077 hc_index_p[j].timeout);
1081 #ifdef BNX2X_STOP_ON_ERROR
1084 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1085 for (i = 0; i < NUM_EQ_DESC; i++) {
1086 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1088 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1089 i, bp->eq_ring[i].message.opcode,
1090 bp->eq_ring[i].message.error);
1091 BNX2X_ERR("data: %x %x %x\n",
1092 data[0], data[1], data[2]);
1098 for_each_valid_rx_queue(bp, i) {
1099 struct bnx2x_fastpath *fp = &bp->fp[i];
1104 if (!fp->rx_cons_sb)
1107 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1108 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1109 for (j = start; j != end; j = RX_BD(j + 1)) {
1110 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1111 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1113 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1114 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1117 start = RX_SGE(fp->rx_sge_prod);
1118 end = RX_SGE(fp->last_max_sge);
1119 for (j = start; j != end; j = RX_SGE(j + 1)) {
1120 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1121 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1123 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1124 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1127 start = RCQ_BD(fp->rx_comp_cons - 10);
1128 end = RCQ_BD(fp->rx_comp_cons + 503);
1129 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1130 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1132 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1133 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1138 for_each_valid_tx_queue(bp, i) {
1139 struct bnx2x_fastpath *fp = &bp->fp[i];
1144 for_each_cos_in_tx_queue(fp, cos) {
1145 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1147 if (!fp->txdata_ptr[cos])
1150 if (!txdata->tx_cons_sb)
1153 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1154 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1155 for (j = start; j != end; j = TX_BD(j + 1)) {
1156 struct sw_tx_bd *sw_bd =
1157 &txdata->tx_buf_ring[j];
1159 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1160 i, cos, j, sw_bd->skb,
1164 start = TX_BD(txdata->tx_bd_cons - 10);
1165 end = TX_BD(txdata->tx_bd_cons + 254);
1166 for (j = start; j != end; j = TX_BD(j + 1)) {
1167 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1169 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1170 i, cos, j, tx_bd[0], tx_bd[1],
1171 tx_bd[2], tx_bd[3]);
1178 bnx2x_mc_assert(bp);
1180 BNX2X_ERR("end crash dump -----------------\n");
1184 * FLR Support for E2
1186 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1189 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1190 #define FLR_WAIT_INTERVAL 50 /* usec */
1191 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1193 struct pbf_pN_buf_regs {
1200 struct pbf_pN_cmd_regs {
1206 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1207 struct pbf_pN_buf_regs *regs,
1210 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1211 u32 cur_cnt = poll_count;
1213 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1214 crd = crd_start = REG_RD(bp, regs->crd);
1215 init_crd = REG_RD(bp, regs->init_crd);
1217 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1218 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1219 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1221 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1222 (init_crd - crd_start))) {
1224 udelay(FLR_WAIT_INTERVAL);
1225 crd = REG_RD(bp, regs->crd);
1226 crd_freed = REG_RD(bp, regs->crd_freed);
1228 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1230 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1232 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1233 regs->pN, crd_freed);
1237 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1238 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1241 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1242 struct pbf_pN_cmd_regs *regs,
1245 u32 occup, to_free, freed, freed_start;
1246 u32 cur_cnt = poll_count;
1248 occup = to_free = REG_RD(bp, regs->lines_occup);
1249 freed = freed_start = REG_RD(bp, regs->lines_freed);
1251 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1252 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1254 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1256 udelay(FLR_WAIT_INTERVAL);
1257 occup = REG_RD(bp, regs->lines_occup);
1258 freed = REG_RD(bp, regs->lines_freed);
1260 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1262 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1264 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1269 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1270 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1273 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1274 u32 expected, u32 poll_count)
1276 u32 cur_cnt = poll_count;
1279 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1280 udelay(FLR_WAIT_INTERVAL);
1285 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1286 char *msg, u32 poll_cnt)
1288 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1290 BNX2X_ERR("%s usage count=%d\n", msg, val);
1296 /* Common routines with VF FLR cleanup */
1297 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1299 /* adjust polling timeout */
1300 if (CHIP_REV_IS_EMUL(bp))
1301 return FLR_POLL_CNT * 2000;
1303 if (CHIP_REV_IS_FPGA(bp))
1304 return FLR_POLL_CNT * 120;
1306 return FLR_POLL_CNT;
1309 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1311 struct pbf_pN_cmd_regs cmd_regs[] = {
1312 {0, (CHIP_IS_E3B0(bp)) ?
1313 PBF_REG_TQ_OCCUPANCY_Q0 :
1314 PBF_REG_P0_TQ_OCCUPANCY,
1315 (CHIP_IS_E3B0(bp)) ?
1316 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1317 PBF_REG_P0_TQ_LINES_FREED_CNT},
1318 {1, (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_TQ_OCCUPANCY_Q1 :
1320 PBF_REG_P1_TQ_OCCUPANCY,
1321 (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1323 PBF_REG_P1_TQ_LINES_FREED_CNT},
1324 {4, (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_TQ_OCCUPANCY_LB_Q :
1326 PBF_REG_P4_TQ_OCCUPANCY,
1327 (CHIP_IS_E3B0(bp)) ?
1328 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1329 PBF_REG_P4_TQ_LINES_FREED_CNT}
1332 struct pbf_pN_buf_regs buf_regs[] = {
1333 {0, (CHIP_IS_E3B0(bp)) ?
1334 PBF_REG_INIT_CRD_Q0 :
1335 PBF_REG_P0_INIT_CRD ,
1336 (CHIP_IS_E3B0(bp)) ?
1339 (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1341 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1342 {1, (CHIP_IS_E3B0(bp)) ?
1343 PBF_REG_INIT_CRD_Q1 :
1344 PBF_REG_P1_INIT_CRD,
1345 (CHIP_IS_E3B0(bp)) ?
1348 (CHIP_IS_E3B0(bp)) ?
1349 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1350 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1351 {4, (CHIP_IS_E3B0(bp)) ?
1352 PBF_REG_INIT_CRD_LB_Q :
1353 PBF_REG_P4_INIT_CRD,
1354 (CHIP_IS_E3B0(bp)) ?
1355 PBF_REG_CREDIT_LB_Q :
1357 (CHIP_IS_E3B0(bp)) ?
1358 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1359 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1364 /* Verify the command queues are flushed P0, P1, P4 */
1365 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1366 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1368 /* Verify the transmission buffers are flushed P0, P1, P4 */
1369 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1370 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1373 #define OP_GEN_PARAM(param) \
1374 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1376 #define OP_GEN_TYPE(type) \
1377 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1379 #define OP_GEN_AGG_VECT(index) \
1380 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1382 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1384 u32 op_gen_command = 0;
1385 u32 comp_addr = BAR_CSTRORM_INTMEM +
1386 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1389 if (REG_RD(bp, comp_addr)) {
1390 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1394 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1395 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1396 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1397 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1399 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1400 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1402 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1403 BNX2X_ERR("FW final cleanup did not succeed\n");
1404 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1405 (REG_RD(bp, comp_addr)));
1409 /* Zero completion for next FLR */
1410 REG_WR(bp, comp_addr, 0);
1415 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1419 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1420 return status & PCI_EXP_DEVSTA_TRPND;
1423 /* PF FLR specific routines
1425 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1427 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1428 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1429 CFC_REG_NUM_LCIDS_INSIDE_PF,
1430 "CFC PF usage counter timed out",
1434 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1435 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1436 DORQ_REG_PF_USAGE_CNT,
1437 "DQ PF usage counter timed out",
1441 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1442 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1443 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1444 "QM PF usage counter timed out",
1448 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1449 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1450 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1451 "Timers VNIC usage counter timed out",
1454 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1455 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1456 "Timers NUM_SCANS usage counter timed out",
1460 /* Wait DMAE PF usage counter to zero */
1461 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1462 dmae_reg_go_c[INIT_DMAE_C(bp)],
1463 "DMAE command register timed out",
1470 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1474 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1475 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1477 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1478 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1480 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1481 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1483 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1484 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1486 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1487 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1489 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1490 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1492 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1493 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1495 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1496 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1500 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1502 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1504 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1506 /* Re-enable PF target read access */
1507 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1509 /* Poll HW usage counters */
1510 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1511 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1514 /* Zero the igu 'trailing edge' and 'leading edge' */
1516 /* Send the FW cleanup command */
1517 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1522 /* Verify TX hw is flushed */
1523 bnx2x_tx_hw_flushed(bp, poll_cnt);
1525 /* Wait 100ms (not adjusted according to platform) */
1528 /* Verify no pending pci transactions */
1529 if (bnx2x_is_pcie_pending(bp->pdev))
1530 BNX2X_ERR("PCIE Transactions still pending\n");
1533 bnx2x_hw_enable_status(bp);
1536 * Master enable - Due to WB DMAE writes performed before this
1537 * register is re-initialized as part of the regular function init
1539 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1544 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1546 int port = BP_PORT(bp);
1547 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1548 u32 val = REG_RD(bp, addr);
1549 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1550 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1551 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1554 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1555 HC_CONFIG_0_REG_INT_LINE_EN_0);
1556 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1557 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1559 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1561 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1562 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1567 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1568 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1569 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1571 if (!CHIP_IS_E1(bp)) {
1573 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1575 REG_WR(bp, addr, val);
1577 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1582 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1585 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1586 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1588 REG_WR(bp, addr, val);
1590 * Ensure that HC_CONFIG is written before leading/trailing edge config
1595 if (!CHIP_IS_E1(bp)) {
1596 /* init leading/trailing edge */
1598 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1600 /* enable nig and gpio3 attention */
1605 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1606 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1609 /* Make sure that interrupts are indeed enabled from here on */
1613 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1616 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1617 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1618 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1620 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1623 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1624 IGU_PF_CONF_SINGLE_ISR_EN);
1625 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1626 IGU_PF_CONF_ATTN_BIT_EN);
1629 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1631 val &= ~IGU_PF_CONF_INT_LINE_EN;
1632 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1633 IGU_PF_CONF_ATTN_BIT_EN |
1634 IGU_PF_CONF_SINGLE_ISR_EN);
1636 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1637 val |= (IGU_PF_CONF_INT_LINE_EN |
1638 IGU_PF_CONF_ATTN_BIT_EN |
1639 IGU_PF_CONF_SINGLE_ISR_EN);
1642 /* Clean previous status - need to configure igu prior to ack*/
1643 if ((!msix) || single_msix) {
1644 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1648 val |= IGU_PF_CONF_FUNC_EN;
1650 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1651 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1653 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1655 if (val & IGU_PF_CONF_INT_LINE_EN)
1656 pci_intx(bp->pdev, true);
1660 /* init leading/trailing edge */
1662 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1664 /* enable nig and gpio3 attention */
1669 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1670 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1672 /* Make sure that interrupts are indeed enabled from here on */
1676 void bnx2x_int_enable(struct bnx2x *bp)
1678 if (bp->common.int_block == INT_BLOCK_HC)
1679 bnx2x_hc_int_enable(bp);
1681 bnx2x_igu_int_enable(bp);
1684 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1686 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1690 /* prevent the HW from sending interrupts */
1691 bnx2x_int_disable(bp);
1693 /* make sure all ISRs are done */
1695 synchronize_irq(bp->msix_table[0].vector);
1697 if (CNIC_SUPPORT(bp))
1699 for_each_eth_queue(bp, i)
1700 synchronize_irq(bp->msix_table[offset++].vector);
1702 synchronize_irq(bp->pdev->irq);
1704 /* make sure sp_task is not running */
1705 cancel_delayed_work(&bp->sp_task);
1706 cancel_delayed_work(&bp->period_task);
1707 flush_workqueue(bnx2x_wq);
1713 * General service functions
1716 /* Return true if succeeded to acquire the lock */
1717 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1720 u32 resource_bit = (1 << resource);
1721 int func = BP_FUNC(bp);
1722 u32 hw_lock_control_reg;
1724 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1725 "Trying to take a lock on resource %d\n", resource);
1727 /* Validating that the resource is within range */
1728 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1729 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1730 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1731 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1736 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1738 hw_lock_control_reg =
1739 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1741 /* Try to acquire the lock */
1742 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1743 lock_status = REG_RD(bp, hw_lock_control_reg);
1744 if (lock_status & resource_bit)
1747 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1748 "Failed to get a lock on resource %d\n", resource);
1753 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1755 * @bp: driver handle
1757 * Returns the recovery leader resource id according to the engine this function
1758 * belongs to. Currently only only 2 engines is supported.
1760 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1763 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1765 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1769 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1771 * @bp: driver handle
1773 * Tries to acquire a leader lock for current engine.
1775 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1777 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1780 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1782 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1783 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1785 /* Set the interrupt occurred bit for the sp-task to recognize it
1786 * must ack the interrupt and transition according to the IGU
1789 atomic_set(&bp->interrupt_occurred, 1);
1791 /* The sp_task must execute only after this bit
1792 * is set, otherwise we will get out of sync and miss all
1793 * further interrupts. Hence, the barrier.
1797 /* schedule sp_task to workqueue */
1798 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1801 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1803 struct bnx2x *bp = fp->bp;
1804 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1805 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1806 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1807 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1810 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1811 fp->index, cid, command, bp->state,
1812 rr_cqe->ramrod_cqe.ramrod_type);
1814 /* If cid is within VF range, replace the slowpath object with the
1815 * one corresponding to this VF
1817 if (cid >= BNX2X_FIRST_VF_CID &&
1818 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1819 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1822 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1823 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1824 drv_cmd = BNX2X_Q_CMD_UPDATE;
1827 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1828 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1829 drv_cmd = BNX2X_Q_CMD_SETUP;
1832 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1833 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1834 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1837 case (RAMROD_CMD_ID_ETH_HALT):
1838 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1839 drv_cmd = BNX2X_Q_CMD_HALT;
1842 case (RAMROD_CMD_ID_ETH_TERMINATE):
1843 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1844 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1847 case (RAMROD_CMD_ID_ETH_EMPTY):
1848 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1849 drv_cmd = BNX2X_Q_CMD_EMPTY;
1852 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1853 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1854 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1858 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1859 command, fp->index);
1863 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1864 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1865 /* q_obj->complete_cmd() failure means that this was
1866 * an unexpected completion.
1868 * In this case we don't want to increase the bp->spq_left
1869 * because apparently we haven't sent this command the first
1872 #ifdef BNX2X_STOP_ON_ERROR
1878 smp_mb__before_atomic();
1879 atomic_inc(&bp->cq_spq_left);
1880 /* push the change in bp->spq_left and towards the memory */
1881 smp_mb__after_atomic();
1883 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1885 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1886 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1887 /* if Q update ramrod is completed for last Q in AFEX vif set
1888 * flow, then ACK MCP at the end
1890 * mark pending ACK to MCP bit.
1891 * prevent case that both bits are cleared.
1892 * At the end of load/unload driver checks that
1893 * sp_state is cleared, and this order prevents
1896 smp_mb__before_atomic();
1897 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1899 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1900 smp_mb__after_atomic();
1902 /* schedule the sp task as mcp ack is required */
1903 bnx2x_schedule_sp_task(bp);
1909 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1911 struct bnx2x *bp = netdev_priv(dev_instance);
1912 u16 status = bnx2x_ack_int(bp);
1917 /* Return here if interrupt is shared and it's not for us */
1918 if (unlikely(status == 0)) {
1919 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1922 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1924 #ifdef BNX2X_STOP_ON_ERROR
1925 if (unlikely(bp->panic))
1929 for_each_eth_queue(bp, i) {
1930 struct bnx2x_fastpath *fp = &bp->fp[i];
1932 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1933 if (status & mask) {
1934 /* Handle Rx or Tx according to SB id */
1935 for_each_cos_in_tx_queue(fp, cos)
1936 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1937 prefetch(&fp->sb_running_index[SM_RX_ID]);
1938 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1943 if (CNIC_SUPPORT(bp)) {
1945 if (status & (mask | 0x1)) {
1946 struct cnic_ops *c_ops = NULL;
1949 c_ops = rcu_dereference(bp->cnic_ops);
1950 if (c_ops && (bp->cnic_eth_dev.drv_state &
1951 CNIC_DRV_STATE_HANDLES_IRQ))
1952 c_ops->cnic_handler(bp->cnic_data, NULL);
1959 if (unlikely(status & 0x1)) {
1961 /* schedule sp task to perform default status block work, ack
1962 * attentions and enable interrupts.
1964 bnx2x_schedule_sp_task(bp);
1971 if (unlikely(status))
1972 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1981 * General service functions
1984 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1987 u32 resource_bit = (1 << resource);
1988 int func = BP_FUNC(bp);
1989 u32 hw_lock_control_reg;
1992 /* Validating that the resource is within range */
1993 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1994 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1995 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2000 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2002 hw_lock_control_reg =
2003 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2006 /* Validating that the resource is not already taken */
2007 lock_status = REG_RD(bp, hw_lock_control_reg);
2008 if (lock_status & resource_bit) {
2009 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2010 lock_status, resource_bit);
2014 /* Try for 5 second every 5ms */
2015 for (cnt = 0; cnt < 1000; cnt++) {
2016 /* Try to acquire the lock */
2017 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2018 lock_status = REG_RD(bp, hw_lock_control_reg);
2019 if (lock_status & resource_bit)
2022 usleep_range(5000, 10000);
2024 BNX2X_ERR("Timeout\n");
2028 int bnx2x_release_leader_lock(struct bnx2x *bp)
2030 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2033 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2036 u32 resource_bit = (1 << resource);
2037 int func = BP_FUNC(bp);
2038 u32 hw_lock_control_reg;
2040 /* Validating that the resource is within range */
2041 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2042 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2043 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2048 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2050 hw_lock_control_reg =
2051 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2054 /* Validating that the resource is currently taken */
2055 lock_status = REG_RD(bp, hw_lock_control_reg);
2056 if (!(lock_status & resource_bit)) {
2057 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2058 lock_status, resource_bit);
2062 REG_WR(bp, hw_lock_control_reg, resource_bit);
2066 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2068 /* The GPIO should be swapped if swap register is set and active */
2069 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2070 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2071 int gpio_shift = gpio_num +
2072 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2073 u32 gpio_mask = (1 << gpio_shift);
2077 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2078 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2082 /* read GPIO value */
2083 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2085 /* get the requested pin value */
2086 if ((gpio_reg & gpio_mask) == gpio_mask)
2094 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2096 /* The GPIO should be swapped if swap register is set and active */
2097 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2098 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2099 int gpio_shift = gpio_num +
2100 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2101 u32 gpio_mask = (1 << gpio_shift);
2104 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2105 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2109 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2110 /* read GPIO and mask except the float bits */
2111 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2114 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2116 "Set GPIO %d (shift %d) -> output low\n",
2117 gpio_num, gpio_shift);
2118 /* clear FLOAT and set CLR */
2119 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2120 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2123 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2125 "Set GPIO %d (shift %d) -> output high\n",
2126 gpio_num, gpio_shift);
2127 /* clear FLOAT and set SET */
2128 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2129 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2132 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2134 "Set GPIO %d (shift %d) -> input\n",
2135 gpio_num, gpio_shift);
2137 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2144 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2145 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2150 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2155 /* Any port swapping should be handled by caller. */
2157 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2158 /* read GPIO and mask except the float bits */
2159 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2160 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2161 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2162 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2165 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2166 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2168 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2171 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2172 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2174 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2177 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2178 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2180 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2184 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2190 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2192 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2197 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2199 /* The GPIO should be swapped if swap register is set and active */
2200 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2201 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2202 int gpio_shift = gpio_num +
2203 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2204 u32 gpio_mask = (1 << gpio_shift);
2207 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2208 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2214 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2217 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2219 "Clear GPIO INT %d (shift %d) -> output low\n",
2220 gpio_num, gpio_shift);
2221 /* clear SET and set CLR */
2222 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2223 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2226 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2228 "Set GPIO INT %d (shift %d) -> output high\n",
2229 gpio_num, gpio_shift);
2230 /* clear CLR and set SET */
2231 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2232 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2239 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2240 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2245 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2249 /* Only 2 SPIOs are configurable */
2250 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2251 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2255 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2256 /* read SPIO and mask except the float bits */
2257 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2260 case MISC_SPIO_OUTPUT_LOW:
2261 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2262 /* clear FLOAT and set CLR */
2263 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2264 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2267 case MISC_SPIO_OUTPUT_HIGH:
2268 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2269 /* clear FLOAT and set SET */
2270 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2271 spio_reg |= (spio << MISC_SPIO_SET_POS);
2274 case MISC_SPIO_INPUT_HI_Z:
2275 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2277 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2284 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2285 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2290 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2292 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2294 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2296 switch (bp->link_vars.ieee_fc &
2297 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2298 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2299 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2303 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2304 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2314 /* Initialize link parameters structure variables
2315 * It is recommended to turn off RX FC for jumbo frames
2316 * for better performance
2318 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2326 u32 pause_enabled = 0;
2328 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2332 REG_WR(bp, BAR_USTRORM_INTMEM +
2333 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2337 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338 pause_enabled ? "enabled" : "disabled");
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2343 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2346 if (!BP_NOMCP(bp)) {
2347 bnx2x_set_requested_fc(bp);
2348 bnx2x_acquire_phy_lock(bp);
2350 if (load_mode == LOAD_DIAG) {
2351 struct link_params *lp = &bp->link_params;
2352 lp->loopback_mode = LOOPBACK_XGXS;
2353 /* Prefer doing PHY loopback at highest speed */
2354 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2355 if (lp->speed_cap_mask[cfx_idx] &
2356 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2357 lp->req_line_speed[cfx_idx] =
2359 else if (lp->speed_cap_mask[cfx_idx] &
2360 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2361 lp->req_line_speed[cfx_idx] =
2364 lp->req_line_speed[cfx_idx] =
2369 if (load_mode == LOAD_LOOPBACK_EXT) {
2370 struct link_params *lp = &bp->link_params;
2371 lp->loopback_mode = LOOPBACK_EXT;
2374 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2376 bnx2x_release_phy_lock(bp);
2378 bnx2x_init_dropless_fc(bp);
2380 bnx2x_calc_fc_adv(bp);
2382 if (bp->link_vars.link_up) {
2383 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2384 bnx2x_link_report(bp);
2386 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2387 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2390 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2394 void bnx2x_link_set(struct bnx2x *bp)
2396 if (!BP_NOMCP(bp)) {
2397 bnx2x_acquire_phy_lock(bp);
2398 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2399 bnx2x_release_phy_lock(bp);
2401 bnx2x_init_dropless_fc(bp);
2403 bnx2x_calc_fc_adv(bp);
2405 BNX2X_ERR("Bootcode is missing - can not set link\n");
2408 static void bnx2x__link_reset(struct bnx2x *bp)
2410 if (!BP_NOMCP(bp)) {
2411 bnx2x_acquire_phy_lock(bp);
2412 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2413 bnx2x_release_phy_lock(bp);
2415 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2418 void bnx2x_force_link_reset(struct bnx2x *bp)
2420 bnx2x_acquire_phy_lock(bp);
2421 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2422 bnx2x_release_phy_lock(bp);
2425 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2429 if (!BP_NOMCP(bp)) {
2430 bnx2x_acquire_phy_lock(bp);
2431 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2433 bnx2x_release_phy_lock(bp);
2435 BNX2X_ERR("Bootcode is missing - can not test link\n");
2440 /* Calculates the sum of vn_min_rates.
2441 It's needed for further normalizing of the min_rates.
2443 sum of vn_min_rates.
2445 0 - if all the min_rates are 0.
2446 In the later case fairness algorithm should be deactivated.
2447 If not all min_rates are zero then those that are zeroes will be set to 1.
2449 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2450 struct cmng_init_input *input)
2455 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2456 u32 vn_cfg = bp->mf_config[vn];
2457 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2458 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2460 /* Skip hidden vns */
2461 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2463 /* If min rate is zero - set it to 1 */
2464 else if (!vn_min_rate)
2465 vn_min_rate = DEF_MIN_RATE;
2469 input->vnic_min_rate[vn] = vn_min_rate;
2472 /* if ETS or all min rates are zeros - disable fairness */
2473 if (BNX2X_IS_ETS_ENABLED(bp)) {
2474 input->flags.cmng_enables &=
2475 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2477 } else if (all_zero) {
2478 input->flags.cmng_enables &=
2479 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 "All MIN values are zeroes fairness will be disabled\n");
2483 input->flags.cmng_enables |=
2484 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2487 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2488 struct cmng_init_input *input)
2491 u32 vn_cfg = bp->mf_config[vn];
2493 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2496 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2498 if (IS_MF_PERCENT_BW(bp)) {
2499 /* maxCfg in percents of linkspeed */
2500 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2501 } else /* SD modes */
2502 /* maxCfg is absolute in 100Mb units */
2503 vn_max_rate = maxCfg * 100;
2506 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2508 input->vnic_max_rate[vn] = vn_max_rate;
2511 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2513 if (CHIP_REV_IS_SLOW(bp))
2514 return CMNG_FNS_NONE;
2516 return CMNG_FNS_MINMAX;
2518 return CMNG_FNS_NONE;
2521 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2523 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2526 return; /* what should be the default value in this case */
2528 /* For 2 port configuration the absolute function number formula
2530 * abs_func = 2 * vn + BP_PORT + BP_PATH
2532 * and there are 4 functions per port
2534 * For 4 port configuration it is
2535 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2537 * and there are 2 functions per port
2539 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2540 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2542 if (func >= E1H_FUNC_MAX)
2546 MF_CFG_RD(bp, func_mf_config[func].config);
2548 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2549 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2550 bp->flags |= MF_FUNC_DIS;
2552 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2553 bp->flags &= ~MF_FUNC_DIS;
2557 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2559 struct cmng_init_input input;
2560 memset(&input, 0, sizeof(struct cmng_init_input));
2562 input.port_rate = bp->link_vars.line_speed;
2564 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2567 /* read mf conf from shmem */
2569 bnx2x_read_mf_cfg(bp);
2571 /* vn_weight_sum and enable fairness if not 0 */
2572 bnx2x_calc_vn_min(bp, &input);
2574 /* calculate and set min-max rate for each vn */
2576 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2577 bnx2x_calc_vn_max(bp, vn, &input);
2579 /* always enable rate shaping and fairness */
2580 input.flags.cmng_enables |=
2581 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2583 bnx2x_init_cmng(&input, &bp->cmng);
2587 /* rate shaping and fairness are disabled */
2589 "rate shaping and fairness are disabled\n");
2592 static void storm_memset_cmng(struct bnx2x *bp,
2593 struct cmng_init *cmng,
2597 size_t size = sizeof(struct cmng_struct_per_port);
2599 u32 addr = BAR_XSTRORM_INTMEM +
2600 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2602 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2604 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2605 int func = func_by_vn(bp, vn);
2607 addr = BAR_XSTRORM_INTMEM +
2608 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2609 size = sizeof(struct rate_shaping_vars_per_vn);
2610 __storm_memset_struct(bp, addr, size,
2611 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2613 addr = BAR_XSTRORM_INTMEM +
2614 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2615 size = sizeof(struct fairness_vars_per_vn);
2616 __storm_memset_struct(bp, addr, size,
2617 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2621 /* init cmng mode in HW according to local configuration */
2622 void bnx2x_set_local_cmng(struct bnx2x *bp)
2624 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2626 if (cmng_fns != CMNG_FNS_NONE) {
2627 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2628 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2630 /* rate shaping and fairness are disabled */
2632 "single function mode without fairness\n");
2636 /* This function is called upon link interrupt */
2637 static void bnx2x_link_attn(struct bnx2x *bp)
2639 /* Make sure that we are synced with the current statistics */
2640 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2642 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2644 bnx2x_init_dropless_fc(bp);
2646 if (bp->link_vars.link_up) {
2648 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2649 struct host_port_stats *pstats;
2651 pstats = bnx2x_sp(bp, port_stats);
2652 /* reset old mac stats */
2653 memset(&(pstats->mac_stx[0]), 0,
2654 sizeof(struct mac_stx));
2656 if (bp->state == BNX2X_STATE_OPEN)
2657 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2660 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2661 bnx2x_set_local_cmng(bp);
2663 __bnx2x_link_report(bp);
2666 bnx2x_link_sync_notify(bp);
2669 void bnx2x__link_status_update(struct bnx2x *bp)
2671 if (bp->state != BNX2X_STATE_OPEN)
2674 /* read updated dcb configuration */
2676 bnx2x_dcbx_pmf_update(bp);
2677 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2678 if (bp->link_vars.link_up)
2679 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2681 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2682 /* indicate link status */
2683 bnx2x_link_report(bp);
2686 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2687 SUPPORTED_10baseT_Full |
2688 SUPPORTED_100baseT_Half |
2689 SUPPORTED_100baseT_Full |
2690 SUPPORTED_1000baseT_Full |
2691 SUPPORTED_2500baseX_Full |
2692 SUPPORTED_10000baseT_Full |
2697 SUPPORTED_Asym_Pause);
2698 bp->port.advertising[0] = bp->port.supported[0];
2700 bp->link_params.bp = bp;
2701 bp->link_params.port = BP_PORT(bp);
2702 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2703 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2704 bp->link_params.req_line_speed[0] = SPEED_10000;
2705 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2706 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2707 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2708 bp->link_vars.line_speed = SPEED_10000;
2709 bp->link_vars.link_status =
2710 (LINK_STATUS_LINK_UP |
2711 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2712 bp->link_vars.link_up = 1;
2713 bp->link_vars.duplex = DUPLEX_FULL;
2714 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2715 __bnx2x_link_report(bp);
2717 bnx2x_sample_bulletin(bp);
2719 /* if bulletin board did not have an update for link status
2720 * __bnx2x_link_report will report current status
2721 * but it will NOT duplicate report in case of already reported
2722 * during sampling bulletin board.
2724 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2728 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2729 u16 vlan_val, u8 allowed_prio)
2731 struct bnx2x_func_state_params func_params = {NULL};
2732 struct bnx2x_func_afex_update_params *f_update_params =
2733 &func_params.params.afex_update;
2735 func_params.f_obj = &bp->func_obj;
2736 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2738 /* no need to wait for RAMROD completion, so don't
2739 * set RAMROD_COMP_WAIT flag
2742 f_update_params->vif_id = vifid;
2743 f_update_params->afex_default_vlan = vlan_val;
2744 f_update_params->allowed_priorities = allowed_prio;
2746 /* if ramrod can not be sent, response to MCP immediately */
2747 if (bnx2x_func_state_change(bp, &func_params) < 0)
2748 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2753 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2754 u16 vif_index, u8 func_bit_map)
2756 struct bnx2x_func_state_params func_params = {NULL};
2757 struct bnx2x_func_afex_viflists_params *update_params =
2758 &func_params.params.afex_viflists;
2762 /* validate only LIST_SET and LIST_GET are received from switch */
2763 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2764 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2767 func_params.f_obj = &bp->func_obj;
2768 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2770 /* set parameters according to cmd_type */
2771 update_params->afex_vif_list_command = cmd_type;
2772 update_params->vif_list_index = vif_index;
2773 update_params->func_bit_map =
2774 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2775 update_params->func_to_clear = 0;
2777 (cmd_type == VIF_LIST_RULE_GET) ?
2778 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2779 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2781 /* if ramrod can not be sent, respond to MCP immediately for
2782 * SET and GET requests (other are not triggered from MCP)
2784 rc = bnx2x_func_state_change(bp, &func_params);
2786 bnx2x_fw_command(bp, drv_msg_code, 0);
2791 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2793 struct afex_stats afex_stats;
2794 u32 func = BP_ABS_FUNC(bp);
2801 u32 addr_to_write, vifid, addrs, stats_type, i;
2803 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2804 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2806 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2807 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2810 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2811 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2812 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2814 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2816 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2820 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2821 addr_to_write = SHMEM2_RD(bp,
2822 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2823 stats_type = SHMEM2_RD(bp,
2824 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2827 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2830 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2832 /* write response to scratchpad, for MCP */
2833 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2834 REG_WR(bp, addr_to_write + i*sizeof(u32),
2835 *(((u32 *)(&afex_stats))+i));
2837 /* send ack message to MCP */
2838 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2841 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2842 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2843 bp->mf_config[BP_VN(bp)] = mf_config;
2845 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2848 /* if VIF_SET is "enabled" */
2849 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2850 /* set rate limit directly to internal RAM */
2851 struct cmng_init_input cmng_input;
2852 struct rate_shaping_vars_per_vn m_rs_vn;
2853 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2854 u32 addr = BAR_XSTRORM_INTMEM +
2855 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2857 bp->mf_config[BP_VN(bp)] = mf_config;
2859 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2860 m_rs_vn.vn_counter.rate =
2861 cmng_input.vnic_max_rate[BP_VN(bp)];
2862 m_rs_vn.vn_counter.quota =
2863 (m_rs_vn.vn_counter.rate *
2864 RS_PERIODIC_TIMEOUT_USEC) / 8;
2866 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2868 /* read relevant values from mf_cfg struct in shmem */
2870 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2872 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2874 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2875 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2876 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2877 vlan_prio = (mf_config &
2878 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2879 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2880 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2883 func_mf_config[func].afex_config) &
2884 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2885 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2888 func_mf_config[func].afex_config) &
2889 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2890 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2892 /* send ramrod to FW, return in case of failure */
2893 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2897 bp->afex_def_vlan_tag = vlan_val;
2898 bp->afex_vlan_mode = vlan_mode;
2900 /* notify link down because BP->flags is disabled */
2901 bnx2x_link_report(bp);
2903 /* send INVALID VIF ramrod to FW */
2904 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2906 /* Reset the default afex VLAN */
2907 bp->afex_def_vlan_tag = -1;
2912 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2914 struct bnx2x_func_switch_update_params *switch_update_params;
2915 struct bnx2x_func_state_params func_params;
2917 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2918 switch_update_params = &func_params.params.switch_update;
2919 func_params.f_obj = &bp->func_obj;
2920 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2922 /* Prepare parameters for function state transitions */
2923 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2924 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
2926 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2927 int func = BP_ABS_FUNC(bp);
2930 /* Re-learn the S-tag from shmem */
2931 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2932 FUNC_MF_CFG_E1HOV_TAG_MASK;
2933 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2936 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2940 /* Configure new S-tag in LLH */
2941 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2944 /* Send Ramrod to update FW of change */
2945 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2946 &switch_update_params->changes);
2947 switch_update_params->vlan = bp->mf_ov;
2949 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2950 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2954 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2961 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2964 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2967 static void bnx2x_pmf_update(struct bnx2x *bp)
2969 int port = BP_PORT(bp);
2973 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2976 * We need the mb() to ensure the ordering between the writing to
2977 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2981 /* queue a periodic task */
2982 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2984 bnx2x_dcbx_pmf_update(bp);
2986 /* enable nig attention */
2987 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2988 if (bp->common.int_block == INT_BLOCK_HC) {
2989 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2990 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2991 } else if (!CHIP_IS_E1x(bp)) {
2992 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2993 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2996 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3004 * General service functions
3007 /* send the MCP a request, block until there is a reply */
3008 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3010 int mb_idx = BP_FW_MB_IDX(bp);
3014 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3016 mutex_lock(&bp->fw_mb_mutex);
3018 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3019 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3021 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3022 (command | seq), param);
3025 /* let the FW do it's magic ... */
3028 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3030 /* Give the FW up to 5 second (500*10ms) */
3031 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3033 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3034 cnt*delay, rc, seq);
3036 /* is this a reply to our command? */
3037 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3038 rc &= FW_MSG_CODE_MASK;
3041 BNX2X_ERR("FW failed to respond!\n");
3045 mutex_unlock(&bp->fw_mb_mutex);
3050 static void storm_memset_func_cfg(struct bnx2x *bp,
3051 struct tstorm_eth_function_common_config *tcfg,
3054 size_t size = sizeof(struct tstorm_eth_function_common_config);
3056 u32 addr = BAR_TSTRORM_INTMEM +
3057 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3059 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3062 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3064 if (CHIP_IS_E1x(bp)) {
3065 struct tstorm_eth_function_common_config tcfg = {0};
3067 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3070 /* Enable the function in the FW */
3071 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3072 storm_memset_func_en(bp, p->func_id, 1);
3075 if (p->spq_active) {
3076 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3077 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3078 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3083 * bnx2x_get_common_flags - Return common flags
3087 * @zero_stats TRUE if statistics zeroing is needed
3089 * Return the flags that are common for the Tx-only and not normal connections.
3091 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3092 struct bnx2x_fastpath *fp,
3095 unsigned long flags = 0;
3097 /* PF driver will always initialize the Queue to an ACTIVE state */
3098 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3100 /* tx only connections collect statistics (on the same index as the
3101 * parent connection). The statistics are zeroed when the parent
3102 * connection is initialized.
3105 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3107 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3109 if (bp->flags & TX_SWITCHING)
3110 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3112 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3113 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3115 #ifdef BNX2X_STOP_ON_ERROR
3116 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3122 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3123 struct bnx2x_fastpath *fp,
3126 unsigned long flags = 0;
3128 /* calculate other queue flags */
3130 __set_bit(BNX2X_Q_FLG_OV, &flags);
3132 if (IS_FCOE_FP(fp)) {
3133 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3134 /* For FCoE - force usage of default priority (for afex) */
3135 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3138 if (fp->mode != TPA_MODE_DISABLED) {
3139 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3140 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3141 if (fp->mode == TPA_MODE_GRO)
3142 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3146 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3147 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3150 /* Always set HW VLAN stripping */
3151 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3153 /* configure silent vlan removal */
3155 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3157 return flags | bnx2x_get_common_flags(bp, fp, true);
3160 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3161 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3164 gen_init->stat_id = bnx2x_stats_id(fp);
3165 gen_init->spcl_id = fp->cl_id;
3167 /* Always use mini-jumbo MTU for FCoE L2 ring */
3169 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3171 gen_init->mtu = bp->dev->mtu;
3173 gen_init->cos = cos;
3175 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3178 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3179 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3180 struct bnx2x_rxq_setup_params *rxq_init)
3184 u16 tpa_agg_size = 0;
3186 if (fp->mode != TPA_MODE_DISABLED) {
3187 pause->sge_th_lo = SGE_TH_LO(bp);
3188 pause->sge_th_hi = SGE_TH_HI(bp);
3190 /* validate SGE ring has enough to cross high threshold */
3191 WARN_ON(bp->dropless_fc &&
3192 pause->sge_th_hi + FW_PREFETCH_CNT >
3193 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3195 tpa_agg_size = TPA_AGG_SIZE;
3196 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3198 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3199 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3200 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3203 /* pause - not for e1 */
3204 if (!CHIP_IS_E1(bp)) {
3205 pause->bd_th_lo = BD_TH_LO(bp);
3206 pause->bd_th_hi = BD_TH_HI(bp);
3208 pause->rcq_th_lo = RCQ_TH_LO(bp);
3209 pause->rcq_th_hi = RCQ_TH_HI(bp);
3211 * validate that rings have enough entries to cross
3214 WARN_ON(bp->dropless_fc &&
3215 pause->bd_th_hi + FW_PREFETCH_CNT >
3217 WARN_ON(bp->dropless_fc &&
3218 pause->rcq_th_hi + FW_PREFETCH_CNT >
3219 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3225 rxq_init->dscr_map = fp->rx_desc_mapping;
3226 rxq_init->sge_map = fp->rx_sge_mapping;
3227 rxq_init->rcq_map = fp->rx_comp_mapping;
3228 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3230 /* This should be a maximum number of data bytes that may be
3231 * placed on the BD (not including paddings).
3233 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3234 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3236 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3237 rxq_init->tpa_agg_sz = tpa_agg_size;
3238 rxq_init->sge_buf_sz = sge_sz;
3239 rxq_init->max_sges_pkt = max_sge;
3240 rxq_init->rss_engine_id = BP_FUNC(bp);
3241 rxq_init->mcast_engine_id = BP_FUNC(bp);
3243 /* Maximum number or simultaneous TPA aggregation for this Queue.
3245 * For PF Clients it should be the maximum available number.
3246 * VF driver(s) may want to define it to a smaller value.
3248 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3250 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3251 rxq_init->fw_sb_id = fp->fw_sb_id;
3254 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3256 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3257 /* configure silent vlan removal
3258 * if multi function mode is afex, then mask default vlan
3260 if (IS_MF_AFEX(bp)) {
3261 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3262 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3266 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3267 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3270 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3271 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3272 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3273 txq_init->fw_sb_id = fp->fw_sb_id;
3276 * set the tss leading client id for TX classification ==
3277 * leading RSS client id
3279 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3281 if (IS_FCOE_FP(fp)) {
3282 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3283 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3287 static void bnx2x_pf_init(struct bnx2x *bp)
3289 struct bnx2x_func_init_params func_init = {0};
3290 struct event_ring_data eq_data = { {0} };
3292 if (!CHIP_IS_E1x(bp)) {
3293 /* reset IGU PF statistics: MSIX + ATTN */
3295 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3296 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3297 (CHIP_MODE_IS_4_PORT(bp) ?
3298 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3300 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3301 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3302 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3303 (CHIP_MODE_IS_4_PORT(bp) ?
3304 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3307 func_init.spq_active = true;
3308 func_init.pf_id = BP_FUNC(bp);
3309 func_init.func_id = BP_FUNC(bp);
3310 func_init.spq_map = bp->spq_mapping;
3311 func_init.spq_prod = bp->spq_prod_idx;
3313 bnx2x_func_init(bp, &func_init);
3315 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318 * Congestion management values depend on the link rate
3319 * There is no active link so initial link rate is set to 10 Gbps.
3320 * When the link comes up The congestion management values are
3321 * re-calculated according to the actual link rate.
3323 bp->link_vars.line_speed = SPEED_10000;
3324 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3326 /* Only the PMF sets the HW */
3328 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3330 /* init Event Queue - PCI bus guarantees correct endianity*/
3331 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3332 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3333 eq_data.producer = bp->eq_prod;
3334 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3335 eq_data.sb_id = DEF_SB_ID;
3336 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339 static void bnx2x_e1h_disable(struct bnx2x *bp)
3341 int port = BP_PORT(bp);
3343 bnx2x_tx_disable(bp);
3345 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3348 static void bnx2x_e1h_enable(struct bnx2x *bp)
3350 int port = BP_PORT(bp);
3352 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3353 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3355 /* Tx queue should be only re-enabled */
3356 netif_tx_wake_all_queues(bp->dev);
3359 * Should not call netif_carrier_on since it will be called if the link
3360 * is up when checking for link state
3364 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3366 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3368 struct eth_stats_info *ether_stat =
3369 &bp->slowpath->drv_info_to_mcp.ether_stat;
3370 struct bnx2x_vlan_mac_obj *mac_obj =
3371 &bp->sp_objs->mac_obj;
3374 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3375 ETH_STAT_INFO_VERSION_LEN);
3377 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3378 * mac_local field in ether_stat struct. The base address is offset by 2
3379 * bytes to account for the field being 8 bytes but a mac address is
3380 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3381 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3382 * allocated by the ether_stat struct, so the macs will land in their
3385 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3386 memset(ether_stat->mac_local + i, 0,
3387 sizeof(ether_stat->mac_local[0]));
3388 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3389 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3390 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3392 ether_stat->mtu_size = bp->dev->mtu;
3393 if (bp->dev->features & NETIF_F_RXCSUM)
3394 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3395 if (bp->dev->features & NETIF_F_TSO)
3396 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3397 ether_stat->feature_flags |= bp->common.boot_mode;
3399 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3401 ether_stat->txq_size = bp->tx_ring_size;
3402 ether_stat->rxq_size = bp->rx_ring_size;
3404 #ifdef CONFIG_BNX2X_SRIOV
3405 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3409 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3411 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3412 struct fcoe_stats_info *fcoe_stat =
3413 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3415 if (!CNIC_LOADED(bp))
3418 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3420 fcoe_stat->qos_priority =
3421 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3423 /* insert FCoE stats from ramrod response */
3425 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3426 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3427 tstorm_queue_statistics;
3429 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3430 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3431 xstorm_queue_statistics;
3433 struct fcoe_statistics_params *fw_fcoe_stat =
3434 &bp->fw_stats_data->fcoe;
3436 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3437 fcoe_stat->rx_bytes_lo,
3438 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3440 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3441 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3442 fcoe_stat->rx_bytes_lo,
3443 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3445 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3446 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3447 fcoe_stat->rx_bytes_lo,
3448 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3450 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3451 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3452 fcoe_stat->rx_bytes_lo,
3453 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3455 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456 fcoe_stat->rx_frames_lo,
3457 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3459 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460 fcoe_stat->rx_frames_lo,
3461 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3463 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464 fcoe_stat->rx_frames_lo,
3465 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3467 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3468 fcoe_stat->rx_frames_lo,
3469 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3471 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3472 fcoe_stat->tx_bytes_lo,
3473 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3475 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3476 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3477 fcoe_stat->tx_bytes_lo,
3478 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3480 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3481 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3482 fcoe_stat->tx_bytes_lo,
3483 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3485 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3486 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3487 fcoe_stat->tx_bytes_lo,
3488 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3490 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491 fcoe_stat->tx_frames_lo,
3492 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3494 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495 fcoe_stat->tx_frames_lo,
3496 fcoe_q_xstorm_stats->ucast_pkts_sent);
3498 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499 fcoe_stat->tx_frames_lo,
3500 fcoe_q_xstorm_stats->bcast_pkts_sent);
3502 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3503 fcoe_stat->tx_frames_lo,
3504 fcoe_q_xstorm_stats->mcast_pkts_sent);
3507 /* ask L5 driver to add data to the struct */
3508 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3511 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3513 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3514 struct iscsi_stats_info *iscsi_stat =
3515 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3517 if (!CNIC_LOADED(bp))
3520 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523 iscsi_stat->qos_priority =
3524 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3526 /* ask L5 driver to add data to the struct */
3527 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3530 /* called due to MCP event (on pmf):
3531 * reread new bandwidth configuration
3533 * notify others function about the change
3535 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3537 /* Workaround for MFW bug.
3538 * MFW is not supposed to generate BW attention in
3539 * single function mode.
3543 "Ignoring MF BW config in single function mode\n");
3547 if (bp->link_vars.link_up) {
3548 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3549 bnx2x_link_sync_notify(bp);
3551 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3554 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3556 bnx2x_config_mf_bw(bp);
3557 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3560 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3562 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3563 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3566 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3567 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3569 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3571 enum drv_info_opcode op_code;
3572 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3573 bool release = false;
3576 /* if drv_info version supported by MFW doesn't match - send NACK */
3577 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3578 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3582 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3583 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3585 /* Must prevent other flows from accessing drv_info_to_mcp */
3586 mutex_lock(&bp->drv_info_mutex);
3588 memset(&bp->slowpath->drv_info_to_mcp, 0,
3589 sizeof(union drv_info_to_mcp));
3592 case ETH_STATS_OPCODE:
3593 bnx2x_drv_info_ether_stat(bp);
3595 case FCOE_STATS_OPCODE:
3596 bnx2x_drv_info_fcoe_stat(bp);
3598 case ISCSI_STATS_OPCODE:
3599 bnx2x_drv_info_iscsi_stat(bp);
3602 /* if op code isn't supported - send NACK */
3603 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3607 /* if we got drv_info attn from MFW then these fields are defined in
3610 SHMEM2_WR(bp, drv_info_host_addr_lo,
3611 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3612 SHMEM2_WR(bp, drv_info_host_addr_hi,
3613 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3615 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3617 /* Since possible management wants both this and get_driver_version
3618 * need to wait until management notifies us it finished utilizing
3621 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3622 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3623 } else if (!bp->drv_info_mng_owner) {
3624 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3626 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3627 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3629 /* Management is done; need to clear indication */
3630 if (indication & bit) {
3631 SHMEM2_WR(bp, mfw_drv_indication,
3637 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3641 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3642 bp->drv_info_mng_owner = true;
3646 mutex_unlock(&bp->drv_info_mutex);
3649 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3655 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3656 &vals[0], &vals[1], &vals[2], &vals[3]);
3660 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3661 &vals[0], &vals[1], &vals[2], &vals[3]);
3667 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3670 void bnx2x_update_mng_version(struct bnx2x *bp)
3672 u32 iscsiver = DRV_VER_NOT_LOADED;
3673 u32 fcoever = DRV_VER_NOT_LOADED;
3674 u32 ethver = DRV_VER_NOT_LOADED;
3675 int idx = BP_FW_MB_IDX(bp);
3678 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3681 mutex_lock(&bp->drv_info_mutex);
3682 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3683 if (bp->drv_info_mng_owner)
3686 if (bp->state != BNX2X_STATE_OPEN)
3689 /* Parse ethernet driver version */
3690 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3691 if (!CNIC_LOADED(bp))
3694 /* Try getting storage driver version via cnic */
3695 memset(&bp->slowpath->drv_info_to_mcp, 0,
3696 sizeof(union drv_info_to_mcp));
3697 bnx2x_drv_info_iscsi_stat(bp);
3698 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3699 iscsiver = bnx2x_update_mng_version_utility(version, false);
3701 memset(&bp->slowpath->drv_info_to_mcp, 0,
3702 sizeof(union drv_info_to_mcp));
3703 bnx2x_drv_info_fcoe_stat(bp);
3704 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3705 fcoever = bnx2x_update_mng_version_utility(version, false);
3708 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3709 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3710 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3712 mutex_unlock(&bp->drv_info_mutex);
3714 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3715 ethver, iscsiver, fcoever);
3718 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3723 if (!SHMEM2_HAS(bp, drv_info))
3726 /* Update Driver load time, possibly broken in y2038 */
3727 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3729 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3730 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3732 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3734 /* Check & notify On-Chip dump. */
3735 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3737 if (valid_dump & FIRST_DUMP_VALID)
3738 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3740 if (valid_dump & SECOND_DUMP_VALID)
3741 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3744 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3746 u32 cmd_ok, cmd_fail;
3749 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3750 event & DRV_STATUS_OEM_EVENT_MASK) {
3751 BNX2X_ERR("Received simultaneous events %08x\n", event);
3755 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3756 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3757 cmd_ok = DRV_MSG_CODE_DCC_OK;
3758 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3759 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3760 cmd_ok = DRV_MSG_CODE_OEM_OK;
3763 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3765 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3766 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3767 /* This is the only place besides the function initialization
3768 * where the bp->flags can change so it is done without any
3771 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3772 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3773 bp->flags |= MF_FUNC_DIS;
3775 bnx2x_e1h_disable(bp);
3777 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3778 bp->flags &= ~MF_FUNC_DIS;
3780 bnx2x_e1h_enable(bp);
3782 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3783 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3786 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3787 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3788 bnx2x_config_mf_bw(bp);
3789 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3790 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3793 /* Report results to MCP */
3795 bnx2x_fw_command(bp, cmd_fail, 0);
3797 bnx2x_fw_command(bp, cmd_ok, 0);
3800 /* must be called under the spq lock */
3801 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3803 struct eth_spe *next_spe = bp->spq_prod_bd;
3805 if (bp->spq_prod_bd == bp->spq_last_bd) {
3806 bp->spq_prod_bd = bp->spq;
3807 bp->spq_prod_idx = 0;
3808 DP(BNX2X_MSG_SP, "end of spq\n");
3816 /* must be called under the spq lock */
3817 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3819 int func = BP_FUNC(bp);
3822 * Make sure that BD data is updated before writing the producer:
3823 * BD data is written to the memory, the producer is read from the
3824 * memory, thus we need a full memory barrier to ensure the ordering.
3828 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3834 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3836 * @cmd: command to check
3837 * @cmd_type: command type
3839 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3841 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3842 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3843 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3844 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3845 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3846 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3847 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3854 * bnx2x_sp_post - place a single command on an SP ring
3856 * @bp: driver handle
3857 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3858 * @cid: SW CID the command is related to
3859 * @data_hi: command private data address (high 32 bits)
3860 * @data_lo: command private data address (low 32 bits)
3861 * @cmd_type: command type (e.g. NONE, ETH)
3863 * SP data is handled as if it's always an address pair, thus data fields are
3864 * not swapped to little endian in upper functions. Instead this function swaps
3865 * data as if it's two u32 fields.
3867 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3868 u32 data_hi, u32 data_lo, int cmd_type)
3870 struct eth_spe *spe;
3872 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3874 #ifdef BNX2X_STOP_ON_ERROR
3875 if (unlikely(bp->panic)) {
3876 BNX2X_ERR("Can't post SP when there is panic\n");
3881 spin_lock_bh(&bp->spq_lock);
3884 if (!atomic_read(&bp->eq_spq_left)) {
3885 BNX2X_ERR("BUG! EQ ring full!\n");
3886 spin_unlock_bh(&bp->spq_lock);
3890 } else if (!atomic_read(&bp->cq_spq_left)) {
3891 BNX2X_ERR("BUG! SPQ ring full!\n");
3892 spin_unlock_bh(&bp->spq_lock);
3897 spe = bnx2x_sp_get_next(bp);
3899 /* CID needs port number to be encoded int it */
3900 spe->hdr.conn_and_cmd_data =
3901 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3904 /* In some cases, type may already contain the func-id
3905 * mainly in SRIOV related use cases, so we add it here only
3906 * if it's not already set.
3908 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3909 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3911 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3912 SPE_HDR_FUNCTION_ID);
3917 spe->hdr.type = cpu_to_le16(type);
3919 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3920 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3923 * It's ok if the actual decrement is issued towards the memory
3924 * somewhere between the spin_lock and spin_unlock. Thus no
3925 * more explicit memory barrier is needed.
3928 atomic_dec(&bp->eq_spq_left);
3930 atomic_dec(&bp->cq_spq_left);
3933 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3934 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3935 (u32)(U64_LO(bp->spq_mapping) +
3936 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3937 HW_CID(bp, cid), data_hi, data_lo, type,
3938 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3940 bnx2x_sp_prod_update(bp);
3941 spin_unlock_bh(&bp->spq_lock);
3945 /* acquire split MCP access lock register */
3946 static int bnx2x_acquire_alr(struct bnx2x *bp)
3952 for (j = 0; j < 1000; j++) {
3953 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3954 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3955 if (val & MCPR_ACCESS_LOCK_LOCK)
3958 usleep_range(5000, 10000);
3960 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3961 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3968 /* release split MCP access lock register */
3969 static void bnx2x_release_alr(struct bnx2x *bp)
3971 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3974 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3975 #define BNX2X_DEF_SB_IDX 0x0002
3977 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3979 struct host_sp_status_block *def_sb = bp->def_status_blk;
3982 barrier(); /* status block is written to by the chip */
3983 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3984 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3985 rc |= BNX2X_DEF_SB_ATT_IDX;
3988 if (bp->def_idx != def_sb->sp_sb.running_index) {
3989 bp->def_idx = def_sb->sp_sb.running_index;
3990 rc |= BNX2X_DEF_SB_IDX;
3993 /* Do not reorder: indices reading should complete before handling */
3999 * slow path service functions
4002 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4004 int port = BP_PORT(bp);
4005 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4006 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4007 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4008 NIG_REG_MASK_INTERRUPT_PORT0;
4013 if (bp->attn_state & asserted)
4014 BNX2X_ERR("IGU ERROR\n");
4016 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4017 aeu_mask = REG_RD(bp, aeu_addr);
4019 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
4020 aeu_mask, asserted);
4021 aeu_mask &= ~(asserted & 0x3ff);
4022 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4024 REG_WR(bp, aeu_addr, aeu_mask);
4025 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4027 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4028 bp->attn_state |= asserted;
4029 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4031 if (asserted & ATTN_HARD_WIRED_MASK) {
4032 if (asserted & ATTN_NIG_FOR_FUNC) {
4034 bnx2x_acquire_phy_lock(bp);
4036 /* save nig interrupt mask */
4037 nig_mask = REG_RD(bp, nig_int_mask_addr);
4039 /* If nig_mask is not set, no need to call the update
4043 REG_WR(bp, nig_int_mask_addr, 0);
4045 bnx2x_link_attn(bp);
4048 /* handle unicore attn? */
4050 if (asserted & ATTN_SW_TIMER_4_FUNC)
4051 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4053 if (asserted & GPIO_2_FUNC)
4054 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4056 if (asserted & GPIO_3_FUNC)
4057 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4059 if (asserted & GPIO_4_FUNC)
4060 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4063 if (asserted & ATTN_GENERAL_ATTN_1) {
4064 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4065 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4067 if (asserted & ATTN_GENERAL_ATTN_2) {
4068 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4069 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4071 if (asserted & ATTN_GENERAL_ATTN_3) {
4072 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4073 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4076 if (asserted & ATTN_GENERAL_ATTN_4) {
4077 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4078 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4080 if (asserted & ATTN_GENERAL_ATTN_5) {
4081 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4082 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4084 if (asserted & ATTN_GENERAL_ATTN_6) {
4085 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4090 } /* if hardwired */
4092 if (bp->common.int_block == INT_BLOCK_HC)
4093 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4094 COMMAND_REG_ATTN_BITS_SET);
4096 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4098 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4099 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4100 REG_WR(bp, reg_addr, asserted);
4102 /* now set back the mask */
4103 if (asserted & ATTN_NIG_FOR_FUNC) {
4104 /* Verify that IGU ack through BAR was written before restoring
4105 * NIG mask. This loop should exit after 2-3 iterations max.
4107 if (bp->common.int_block != INT_BLOCK_HC) {
4108 u32 cnt = 0, igu_acked;
4110 igu_acked = REG_RD(bp,
4111 IGU_REG_ATTENTION_ACK_BITS);
4112 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4113 (++cnt < MAX_IGU_ATTN_ACK_TO));
4116 "Failed to verify IGU ack on time\n");
4119 REG_WR(bp, nig_int_mask_addr, nig_mask);
4120 bnx2x_release_phy_lock(bp);
4124 static void bnx2x_fan_failure(struct bnx2x *bp)
4126 int port = BP_PORT(bp);
4128 /* mark the failure */
4131 dev_info.port_hw_config[port].external_phy_config);
4133 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4134 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4135 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4138 /* log the failure */
4139 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4140 "Please contact OEM Support for assistance\n");
4142 /* Schedule device reset (unload)
4143 * This is due to some boards consuming sufficient power when driver is
4144 * up to overheat if fan fails.
4146 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4149 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4151 int port = BP_PORT(bp);
4155 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4156 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4158 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4160 val = REG_RD(bp, reg_offset);
4161 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4162 REG_WR(bp, reg_offset, val);
4164 BNX2X_ERR("SPIO5 hw attention\n");
4166 /* Fan failure attention */
4167 bnx2x_hw_reset_phy(&bp->link_params);
4168 bnx2x_fan_failure(bp);
4171 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4172 bnx2x_acquire_phy_lock(bp);
4173 bnx2x_handle_module_detect_int(&bp->link_params);
4174 bnx2x_release_phy_lock(bp);
4177 if (attn & HW_INTERRUPT_ASSERT_SET_0) {
4179 val = REG_RD(bp, reg_offset);
4180 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0);
4181 REG_WR(bp, reg_offset, val);
4183 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4184 (u32)(attn & HW_INTERRUPT_ASSERT_SET_0));
4189 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4193 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4195 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4196 BNX2X_ERR("DB hw attention 0x%x\n", val);
4197 /* DORQ discard attention */
4199 BNX2X_ERR("FATAL error from DORQ\n");
4202 if (attn & HW_INTERRUPT_ASSERT_SET_1) {
4204 int port = BP_PORT(bp);
4207 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4208 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4210 val = REG_RD(bp, reg_offset);
4211 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1);
4212 REG_WR(bp, reg_offset, val);
4214 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4215 (u32)(attn & HW_INTERRUPT_ASSERT_SET_1));
4220 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4224 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4226 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4227 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4228 /* CFC error attention */
4230 BNX2X_ERR("FATAL error from CFC\n");
4233 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4234 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4235 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4236 /* RQ_USDMDP_FIFO_OVERFLOW */
4238 BNX2X_ERR("FATAL error from PXP\n");
4240 if (!CHIP_IS_E1x(bp)) {
4241 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4242 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4246 if (attn & HW_INTERRUPT_ASSERT_SET_2) {
4248 int port = BP_PORT(bp);
4251 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4252 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4254 val = REG_RD(bp, reg_offset);
4255 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2);
4256 REG_WR(bp, reg_offset, val);
4258 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4259 (u32)(attn & HW_INTERRUPT_ASSERT_SET_2));
4264 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4268 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4270 if (attn & BNX2X_PMF_LINK_ASSERT) {
4271 int func = BP_FUNC(bp);
4273 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4274 bnx2x_read_mf_cfg(bp);
4275 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4276 func_mf_config[BP_ABS_FUNC(bp)].config);
4278 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4280 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4281 DRV_STATUS_OEM_EVENT_MASK))
4283 (val & (DRV_STATUS_DCC_EVENT_MASK |
4284 DRV_STATUS_OEM_EVENT_MASK)));
4286 if (val & DRV_STATUS_SET_MF_BW)
4287 bnx2x_set_mf_bw(bp);
4289 if (val & DRV_STATUS_DRV_INFO_REQ)
4290 bnx2x_handle_drv_info_req(bp);
4292 if (val & DRV_STATUS_VF_DISABLED)
4293 bnx2x_schedule_iov_task(bp,
4294 BNX2X_IOV_HANDLE_FLR);
4296 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4297 bnx2x_pmf_update(bp);
4300 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4301 bp->dcbx_enabled > 0)
4302 /* start dcbx state machine */
4303 bnx2x_dcbx_set_params(bp,
4304 BNX2X_DCBX_STATE_NEG_RECEIVED);
4305 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4306 bnx2x_handle_afex_cmd(bp,
4307 val & DRV_STATUS_AFEX_EVENT_MASK);
4308 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4309 bnx2x_handle_eee_event(bp);
4311 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4312 bnx2x_schedule_sp_rtnl(bp,
4313 BNX2X_SP_RTNL_UPDATE_SVID, 0);
4315 if (bp->link_vars.periodic_flags &
4316 PERIODIC_FLAGS_LINK_EVENT) {
4317 /* sync with link */
4318 bnx2x_acquire_phy_lock(bp);
4319 bp->link_vars.periodic_flags &=
4320 ~PERIODIC_FLAGS_LINK_EVENT;
4321 bnx2x_release_phy_lock(bp);
4323 bnx2x_link_sync_notify(bp);
4324 bnx2x_link_report(bp);
4326 /* Always call it here: bnx2x_link_report() will
4327 * prevent the link indication duplication.
4329 bnx2x__link_status_update(bp);
4330 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4332 BNX2X_ERR("MC assert!\n");
4333 bnx2x_mc_assert(bp);
4334 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4335 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4336 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4337 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4340 } else if (attn & BNX2X_MCP_ASSERT) {
4342 BNX2X_ERR("MCP assert!\n");
4343 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4347 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4350 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4351 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4352 if (attn & BNX2X_GRC_TIMEOUT) {
4353 val = CHIP_IS_E1(bp) ? 0 :
4354 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4355 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4357 if (attn & BNX2X_GRC_RSV) {
4358 val = CHIP_IS_E1(bp) ? 0 :
4359 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4360 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4362 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4368 * 0-7 - Engine0 load counter.
4369 * 8-15 - Engine1 load counter.
4370 * 16 - Engine0 RESET_IN_PROGRESS bit.
4371 * 17 - Engine1 RESET_IN_PROGRESS bit.
4372 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4374 * 19 - Engine1 ONE_IS_LOADED.
4375 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4376 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4377 * just the one belonging to its engine).
4380 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4382 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4383 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4384 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4385 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4386 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4387 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4388 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4391 * Set the GLOBAL_RESET bit.
4393 * Should be run under rtnl lock
4395 void bnx2x_set_reset_global(struct bnx2x *bp)
4398 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4399 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4400 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4401 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4405 * Clear the GLOBAL_RESET bit.
4407 * Should be run under rtnl lock
4409 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4412 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4413 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4414 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4415 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4419 * Checks the GLOBAL_RESET bit.
4421 * should be run under rtnl lock
4423 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4425 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4427 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4428 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4432 * Clear RESET_IN_PROGRESS bit for the current engine.
4434 * Should be run under rtnl lock
4436 static void bnx2x_set_reset_done(struct bnx2x *bp)
4439 u32 bit = BP_PATH(bp) ?
4440 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4441 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4442 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4446 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4448 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4452 * Set RESET_IN_PROGRESS for the current engine.
4454 * should be run under rtnl lock
4456 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4459 u32 bit = BP_PATH(bp) ?
4460 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4461 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4462 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4466 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4467 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4471 * Checks the RESET_IN_PROGRESS bit for the given engine.
4472 * should be run under rtnl lock
4474 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4476 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4478 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4480 /* return false if bit is set */
4481 return (val & bit) ? false : true;
4485 * set pf load for the current pf.
4487 * should be run under rtnl lock
4489 void bnx2x_set_pf_load(struct bnx2x *bp)
4492 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4493 BNX2X_PATH0_LOAD_CNT_MASK;
4494 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4495 BNX2X_PATH0_LOAD_CNT_SHIFT;
4497 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4498 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4500 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4502 /* get the current counter value */
4503 val1 = (val & mask) >> shift;
4505 /* set bit of that PF */
4506 val1 |= (1 << bp->pf_num);
4508 /* clear the old value */
4511 /* set the new one */
4512 val |= ((val1 << shift) & mask);
4514 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4515 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4519 * bnx2x_clear_pf_load - clear pf load mark
4521 * @bp: driver handle
4523 * Should be run under rtnl lock.
4524 * Decrements the load counter for the current engine. Returns
4525 * whether other functions are still loaded
4527 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4530 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4531 BNX2X_PATH0_LOAD_CNT_MASK;
4532 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4533 BNX2X_PATH0_LOAD_CNT_SHIFT;
4535 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4536 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4537 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4539 /* get the current counter value */
4540 val1 = (val & mask) >> shift;
4542 /* clear bit of that PF */
4543 val1 &= ~(1 << bp->pf_num);
4545 /* clear the old value */
4548 /* set the new one */
4549 val |= ((val1 << shift) & mask);
4551 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4552 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4557 * Read the load status for the current engine.
4559 * should be run under rtnl lock
4561 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4563 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4564 BNX2X_PATH0_LOAD_CNT_MASK);
4565 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4566 BNX2X_PATH0_LOAD_CNT_SHIFT);
4567 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4569 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4571 val = (val & mask) >> shift;
4573 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4579 static void _print_parity(struct bnx2x *bp, u32 reg)
4581 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4584 static void _print_next_block(int idx, const char *blk)
4586 pr_cont("%s%s", idx ? ", " : "", blk);
4589 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4590 int *par_num, bool print)
4598 for (i = 0; sig; i++) {
4599 cur_bit = (0x1UL << i);
4600 if (sig & cur_bit) {
4601 res |= true; /* Each bit is real error! */
4605 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4606 _print_next_block((*par_num)++, "BRB");
4608 BRB1_REG_BRB1_PRTY_STS);
4610 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4611 _print_next_block((*par_num)++,
4613 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4615 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4616 _print_next_block((*par_num)++, "TSDM");
4618 TSDM_REG_TSDM_PRTY_STS);
4620 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4621 _print_next_block((*par_num)++,
4623 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4625 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4626 _print_next_block((*par_num)++, "TCM");
4627 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4629 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4630 _print_next_block((*par_num)++,
4633 TSEM_REG_TSEM_PRTY_STS_0);
4635 TSEM_REG_TSEM_PRTY_STS_1);
4637 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4638 _print_next_block((*par_num)++, "XPB");
4639 _print_parity(bp, GRCBASE_XPB +
4640 PB_REG_PB_PRTY_STS);
4653 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4654 int *par_num, bool *global,
4663 for (i = 0; sig; i++) {
4664 cur_bit = (0x1UL << i);
4665 if (sig & cur_bit) {
4666 res |= true; /* Each bit is real error! */
4668 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4670 _print_next_block((*par_num)++, "PBF");
4671 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4674 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4676 _print_next_block((*par_num)++, "QM");
4677 _print_parity(bp, QM_REG_QM_PRTY_STS);
4680 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4682 _print_next_block((*par_num)++, "TM");
4683 _print_parity(bp, TM_REG_TM_PRTY_STS);
4686 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4688 _print_next_block((*par_num)++, "XSDM");
4690 XSDM_REG_XSDM_PRTY_STS);
4693 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4695 _print_next_block((*par_num)++, "XCM");
4696 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4699 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4701 _print_next_block((*par_num)++,
4704 XSEM_REG_XSEM_PRTY_STS_0);
4706 XSEM_REG_XSEM_PRTY_STS_1);
4709 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4711 _print_next_block((*par_num)++,
4714 DORQ_REG_DORQ_PRTY_STS);
4717 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4719 _print_next_block((*par_num)++, "NIG");
4720 if (CHIP_IS_E1x(bp)) {
4722 NIG_REG_NIG_PRTY_STS);
4725 NIG_REG_NIG_PRTY_STS_0);
4727 NIG_REG_NIG_PRTY_STS_1);
4731 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4733 _print_next_block((*par_num)++,
4737 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4739 _print_next_block((*par_num)++,
4741 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4744 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4746 _print_next_block((*par_num)++, "USDM");
4748 USDM_REG_USDM_PRTY_STS);
4751 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4753 _print_next_block((*par_num)++, "UCM");
4754 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4757 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4759 _print_next_block((*par_num)++,
4762 USEM_REG_USEM_PRTY_STS_0);
4764 USEM_REG_USEM_PRTY_STS_1);
4767 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4769 _print_next_block((*par_num)++, "UPB");
4770 _print_parity(bp, GRCBASE_UPB +
4771 PB_REG_PB_PRTY_STS);
4774 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4776 _print_next_block((*par_num)++, "CSDM");
4778 CSDM_REG_CSDM_PRTY_STS);
4781 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4783 _print_next_block((*par_num)++, "CCM");
4784 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4797 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4798 int *par_num, bool print)
4806 for (i = 0; sig; i++) {
4807 cur_bit = (0x1UL << i);
4808 if (sig & cur_bit) {
4809 res = true; /* Each bit is real error! */
4812 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4813 _print_next_block((*par_num)++,
4816 CSEM_REG_CSEM_PRTY_STS_0);
4818 CSEM_REG_CSEM_PRTY_STS_1);
4820 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4821 _print_next_block((*par_num)++, "PXP");
4822 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4824 PXP2_REG_PXP2_PRTY_STS_0);
4826 PXP2_REG_PXP2_PRTY_STS_1);
4828 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4829 _print_next_block((*par_num)++,
4830 "PXPPCICLOCKCLIENT");
4832 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4833 _print_next_block((*par_num)++, "CFC");
4835 CFC_REG_CFC_PRTY_STS);
4837 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4838 _print_next_block((*par_num)++, "CDU");
4839 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4841 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4842 _print_next_block((*par_num)++, "DMAE");
4844 DMAE_REG_DMAE_PRTY_STS);
4846 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4847 _print_next_block((*par_num)++, "IGU");
4848 if (CHIP_IS_E1x(bp))
4850 HC_REG_HC_PRTY_STS);
4853 IGU_REG_IGU_PRTY_STS);
4855 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4856 _print_next_block((*par_num)++, "MISC");
4858 MISC_REG_MISC_PRTY_STS);
4871 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4872 int *par_num, bool *global,
4879 for (i = 0; sig; i++) {
4880 cur_bit = (0x1UL << i);
4881 if (sig & cur_bit) {
4883 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4885 _print_next_block((*par_num)++,
4890 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4892 _print_next_block((*par_num)++,
4897 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4899 _print_next_block((*par_num)++,
4904 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4906 /* clear latched SCPAD PATIRY from MCP */
4907 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4920 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4921 int *par_num, bool print)
4929 for (i = 0; sig; i++) {
4930 cur_bit = (0x1UL << i);
4931 if (sig & cur_bit) {
4932 res = true; /* Each bit is real error! */
4935 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4936 _print_next_block((*par_num)++,
4939 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4941 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4942 _print_next_block((*par_num)++, "ATC");
4944 ATC_REG_ATC_PRTY_STS);
4956 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4961 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4962 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4963 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4964 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4965 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4968 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4969 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4970 sig[0] & HW_PRTY_ASSERT_SET_0,
4971 sig[1] & HW_PRTY_ASSERT_SET_1,
4972 sig[2] & HW_PRTY_ASSERT_SET_2,
4973 sig[3] & HW_PRTY_ASSERT_SET_3,
4974 sig[4] & HW_PRTY_ASSERT_SET_4);
4976 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4977 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4978 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4979 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4980 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4982 "Parity errors detected in blocks: ");
4987 res |= bnx2x_check_blocks_with_parity0(bp,
4988 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4989 res |= bnx2x_check_blocks_with_parity1(bp,
4990 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4991 res |= bnx2x_check_blocks_with_parity2(bp,
4992 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4993 res |= bnx2x_check_blocks_with_parity3(bp,
4994 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4995 res |= bnx2x_check_blocks_with_parity4(bp,
4996 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
5006 * bnx2x_chk_parity_attn - checks for parity attentions.
5008 * @bp: driver handle
5009 * @global: true if there was a global attention
5010 * @print: show parity attention in syslog
5012 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5014 struct attn_route attn = { {0} };
5015 int port = BP_PORT(bp);
5017 attn.sig[0] = REG_RD(bp,
5018 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5020 attn.sig[1] = REG_RD(bp,
5021 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5023 attn.sig[2] = REG_RD(bp,
5024 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5026 attn.sig[3] = REG_RD(bp,
5027 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5029 /* Since MCP attentions can't be disabled inside the block, we need to
5030 * read AEU registers to see whether they're currently disabled
5032 attn.sig[3] &= ((REG_RD(bp,
5033 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5034 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5035 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5036 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5038 if (!CHIP_IS_E1x(bp))
5039 attn.sig[4] = REG_RD(bp,
5040 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5043 return bnx2x_parity_attn(bp, global, print, attn.sig);
5046 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5049 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5051 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5052 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5053 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5054 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5055 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5056 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5057 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5058 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5059 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5060 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5062 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5063 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5065 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5066 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5067 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5068 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5069 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5070 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5071 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5072 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5074 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5075 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5076 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5077 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5078 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5079 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5080 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5081 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5082 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5083 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5084 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5085 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5086 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5087 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5088 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5091 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5092 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5093 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5094 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5095 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5099 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5101 struct attn_route attn, *group_mask;
5102 int port = BP_PORT(bp);
5107 bool global = false;
5109 /* need to take HW lock because MCP or other port might also
5110 try to handle this event */
5111 bnx2x_acquire_alr(bp);
5113 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5114 #ifndef BNX2X_STOP_ON_ERROR
5115 bp->recovery_state = BNX2X_RECOVERY_INIT;
5116 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5117 /* Disable HW interrupts */
5118 bnx2x_int_disable(bp);
5119 /* In case of parity errors don't handle attentions so that
5120 * other function would "see" parity errors.
5125 bnx2x_release_alr(bp);
5129 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5130 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5131 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5132 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5133 if (!CHIP_IS_E1x(bp))
5135 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5139 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5140 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5142 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5143 if (deasserted & (1 << index)) {
5144 group_mask = &bp->attn_group[index];
5146 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5148 group_mask->sig[0], group_mask->sig[1],
5149 group_mask->sig[2], group_mask->sig[3],
5150 group_mask->sig[4]);
5152 bnx2x_attn_int_deasserted4(bp,
5153 attn.sig[4] & group_mask->sig[4]);
5154 bnx2x_attn_int_deasserted3(bp,
5155 attn.sig[3] & group_mask->sig[3]);
5156 bnx2x_attn_int_deasserted1(bp,
5157 attn.sig[1] & group_mask->sig[1]);
5158 bnx2x_attn_int_deasserted2(bp,
5159 attn.sig[2] & group_mask->sig[2]);
5160 bnx2x_attn_int_deasserted0(bp,
5161 attn.sig[0] & group_mask->sig[0]);
5165 bnx2x_release_alr(bp);
5167 if (bp->common.int_block == INT_BLOCK_HC)
5168 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5169 COMMAND_REG_ATTN_BITS_CLR);
5171 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5174 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5175 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5176 REG_WR(bp, reg_addr, val);
5178 if (~bp->attn_state & deasserted)
5179 BNX2X_ERR("IGU ERROR\n");
5181 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5182 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5184 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5185 aeu_mask = REG_RD(bp, reg_addr);
5187 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5188 aeu_mask, deasserted);
5189 aeu_mask |= (deasserted & 0x3ff);
5190 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5192 REG_WR(bp, reg_addr, aeu_mask);
5193 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5195 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5196 bp->attn_state &= ~deasserted;
5197 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5200 static void bnx2x_attn_int(struct bnx2x *bp)
5202 /* read local copy of bits */
5203 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5205 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5207 u32 attn_state = bp->attn_state;
5209 /* look for changed bits */
5210 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5211 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5214 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5215 attn_bits, attn_ack, asserted, deasserted);
5217 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5218 BNX2X_ERR("BAD attention state\n");
5220 /* handle bits that were raised */
5222 bnx2x_attn_int_asserted(bp, asserted);
5225 bnx2x_attn_int_deasserted(bp, deasserted);
5228 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5229 u16 index, u8 op, u8 update)
5231 u32 igu_addr = bp->igu_base_addr;
5232 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5233 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5237 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5239 /* No memory barriers */
5240 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5241 mmiowb(); /* keep prod updates ordered */
5244 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5245 union event_ring_elem *elem)
5247 u8 err = elem->message.error;
5249 if (!bp->cnic_eth_dev.starting_cid ||
5250 (cid < bp->cnic_eth_dev.starting_cid &&
5251 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5254 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5256 if (unlikely(err)) {
5258 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5260 bnx2x_panic_dump(bp, false);
5262 bnx2x_cnic_cfc_comp(bp, cid, err);
5266 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5268 struct bnx2x_mcast_ramrod_params rparam;
5271 memset(&rparam, 0, sizeof(rparam));
5273 rparam.mcast_obj = &bp->mcast_obj;
5275 netif_addr_lock_bh(bp->dev);
5277 /* Clear pending state for the last command */
5278 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5280 /* If there are pending mcast commands - send them */
5281 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5282 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5284 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5288 netif_addr_unlock_bh(bp->dev);
5291 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5292 union event_ring_elem *elem)
5294 unsigned long ramrod_flags = 0;
5296 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5297 u32 cid = echo & BNX2X_SWCID_MASK;
5298 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5300 /* Always push next commands out, don't wait here */
5301 __set_bit(RAMROD_CONT, &ramrod_flags);
5303 switch (echo >> BNX2X_SWCID_SHIFT) {
5304 case BNX2X_FILTER_MAC_PENDING:
5305 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5306 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5307 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5309 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5312 case BNX2X_FILTER_VLAN_PENDING:
5313 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5314 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5316 case BNX2X_FILTER_MCAST_PENDING:
5317 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5318 /* This is only relevant for 57710 where multicast MACs are
5319 * configured as unicast MACs using the same ramrod.
5321 bnx2x_handle_mcast_eqe(bp);
5324 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5328 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5331 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5333 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5336 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5338 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5340 netif_addr_lock_bh(bp->dev);
5342 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5344 /* Send rx_mode command again if was requested */
5345 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5346 bnx2x_set_storm_rx_mode(bp);
5347 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5349 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5350 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5352 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5354 netif_addr_unlock_bh(bp->dev);
5357 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5358 union event_ring_elem *elem)
5360 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5362 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5363 elem->message.data.vif_list_event.func_bit_map);
5364 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5365 elem->message.data.vif_list_event.func_bit_map);
5366 } else if (elem->message.data.vif_list_event.echo ==
5367 VIF_LIST_RULE_SET) {
5368 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5369 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5373 /* called with rtnl_lock */
5374 static void bnx2x_after_function_update(struct bnx2x *bp)
5377 struct bnx2x_fastpath *fp;
5378 struct bnx2x_queue_state_params queue_params = {NULL};
5379 struct bnx2x_queue_update_params *q_update_params =
5380 &queue_params.params.update;
5382 /* Send Q update command with afex vlan removal values for all Qs */
5383 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5385 /* set silent vlan removal values according to vlan mode */
5386 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5387 &q_update_params->update_flags);
5388 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5389 &q_update_params->update_flags);
5390 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5392 /* in access mode mark mask and value are 0 to strip all vlans */
5393 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5394 q_update_params->silent_removal_value = 0;
5395 q_update_params->silent_removal_mask = 0;
5397 q_update_params->silent_removal_value =
5398 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5399 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5402 for_each_eth_queue(bp, q) {
5403 /* Set the appropriate Queue object */
5405 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5407 /* send the ramrod */
5408 rc = bnx2x_queue_state_change(bp, &queue_params);
5410 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5414 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5415 fp = &bp->fp[FCOE_IDX(bp)];
5416 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5418 /* clear pending completion bit */
5419 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5421 /* mark latest Q bit */
5422 smp_mb__before_atomic();
5423 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5424 smp_mb__after_atomic();
5426 /* send Q update ramrod for FCoE Q */
5427 rc = bnx2x_queue_state_change(bp, &queue_params);
5429 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5432 /* If no FCoE ring - ACK MCP now */
5433 bnx2x_link_report(bp);
5434 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5438 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5439 struct bnx2x *bp, u32 cid)
5441 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5443 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5444 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5446 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5449 static void bnx2x_eq_int(struct bnx2x *bp)
5451 u16 hw_cons, sw_cons, sw_prod;
5452 union event_ring_elem *elem;
5456 int rc, spqe_cnt = 0;
5457 struct bnx2x_queue_sp_obj *q_obj;
5458 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5459 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5461 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5463 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5464 * when we get the next-page we need to adjust so the loop
5465 * condition below will be met. The next element is the size of a
5466 * regular element and hence incrementing by 1
5468 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5471 /* This function may never run in parallel with itself for a
5472 * specific bp, thus there is no need in "paired" read memory
5475 sw_cons = bp->eq_cons;
5476 sw_prod = bp->eq_prod;
5478 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5479 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5481 for (; sw_cons != hw_cons;
5482 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5484 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5486 rc = bnx2x_iov_eq_sp_event(bp, elem);
5488 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5493 opcode = elem->message.opcode;
5495 /* handle eq element */
5497 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5498 bnx2x_vf_mbx_schedule(bp,
5499 &elem->message.data.vf_pf_event);
5502 case EVENT_RING_OPCODE_STAT_QUERY:
5503 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5504 "got statistics comp event %d\n",
5506 /* nothing to do with stats comp */
5509 case EVENT_RING_OPCODE_CFC_DEL:
5510 /* handle according to cid range */
5512 * we may want to verify here that the bp state is
5516 /* elem CID originates from FW; actually LE */
5517 cid = SW_CID(elem->message.data.cfc_del_event.cid);
5520 "got delete ramrod for MULTI[%d]\n", cid);
5522 if (CNIC_LOADED(bp) &&
5523 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5526 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5528 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5533 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5534 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5535 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5536 if (f_obj->complete_cmd(bp, f_obj,
5537 BNX2X_F_CMD_TX_STOP))
5541 case EVENT_RING_OPCODE_START_TRAFFIC:
5542 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5543 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5544 if (f_obj->complete_cmd(bp, f_obj,
5545 BNX2X_F_CMD_TX_START))
5549 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5550 echo = elem->message.data.function_update_event.echo;
5551 if (echo == SWITCH_UPDATE) {
5552 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5553 "got FUNC_SWITCH_UPDATE ramrod\n");
5554 if (f_obj->complete_cmd(
5555 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5559 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5561 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5562 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5563 f_obj->complete_cmd(bp, f_obj,
5564 BNX2X_F_CMD_AFEX_UPDATE);
5566 /* We will perform the Queues update from
5567 * sp_rtnl task as all Queue SP operations
5568 * should run under rtnl_lock.
5570 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5575 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5576 f_obj->complete_cmd(bp, f_obj,
5577 BNX2X_F_CMD_AFEX_VIFLISTS);
5578 bnx2x_after_afex_vif_lists(bp, elem);
5580 case EVENT_RING_OPCODE_FUNCTION_START:
5581 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5582 "got FUNC_START ramrod\n");
5583 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5588 case EVENT_RING_OPCODE_FUNCTION_STOP:
5589 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5590 "got FUNC_STOP ramrod\n");
5591 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5596 case EVENT_RING_OPCODE_SET_TIMESYNC:
5597 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5598 "got set_timesync ramrod completion\n");
5599 if (f_obj->complete_cmd(bp, f_obj,
5600 BNX2X_F_CMD_SET_TIMESYNC))
5605 switch (opcode | bp->state) {
5606 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5608 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5609 BNX2X_STATE_OPENING_WAIT4_PORT):
5610 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5611 BNX2X_STATE_CLOSING_WAIT4_HALT):
5612 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5613 SW_CID(elem->message.data.eth_event.echo));
5614 rss_raw->clear_pending(rss_raw);
5617 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5618 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5619 case (EVENT_RING_OPCODE_SET_MAC |
5620 BNX2X_STATE_CLOSING_WAIT4_HALT):
5621 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5623 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5625 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5626 BNX2X_STATE_CLOSING_WAIT4_HALT):
5627 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5628 bnx2x_handle_classification_eqe(bp, elem);
5631 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5633 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5635 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5636 BNX2X_STATE_CLOSING_WAIT4_HALT):
5637 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5638 bnx2x_handle_mcast_eqe(bp);
5641 case (EVENT_RING_OPCODE_FILTERS_RULES |
5643 case (EVENT_RING_OPCODE_FILTERS_RULES |
5645 case (EVENT_RING_OPCODE_FILTERS_RULES |
5646 BNX2X_STATE_CLOSING_WAIT4_HALT):
5647 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5648 bnx2x_handle_rx_mode_eqe(bp);
5651 /* unknown event log error and continue */
5652 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5653 elem->message.opcode, bp->state);
5659 smp_mb__before_atomic();
5660 atomic_add(spqe_cnt, &bp->eq_spq_left);
5662 bp->eq_cons = sw_cons;
5663 bp->eq_prod = sw_prod;
5664 /* Make sure that above mem writes were issued towards the memory */
5667 /* update producer */
5668 bnx2x_update_eq_prod(bp, bp->eq_prod);
5671 static void bnx2x_sp_task(struct work_struct *work)
5673 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5675 DP(BNX2X_MSG_SP, "sp task invoked\n");
5677 /* make sure the atomic interrupt_occurred has been written */
5679 if (atomic_read(&bp->interrupt_occurred)) {
5681 /* what work needs to be performed? */
5682 u16 status = bnx2x_update_dsb_idx(bp);
5684 DP(BNX2X_MSG_SP, "status %x\n", status);
5685 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5686 atomic_set(&bp->interrupt_occurred, 0);
5689 if (status & BNX2X_DEF_SB_ATT_IDX) {
5691 status &= ~BNX2X_DEF_SB_ATT_IDX;
5694 /* SP events: STAT_QUERY and others */
5695 if (status & BNX2X_DEF_SB_IDX) {
5696 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5698 if (FCOE_INIT(bp) &&
5699 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5700 /* Prevent local bottom-halves from running as
5701 * we are going to change the local NAPI list.
5704 napi_schedule(&bnx2x_fcoe(bp, napi));
5708 /* Handle EQ completions */
5710 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5711 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5713 status &= ~BNX2X_DEF_SB_IDX;
5716 /* if status is non zero then perhaps something went wrong */
5717 if (unlikely(status))
5719 "got an unknown interrupt! (status 0x%x)\n", status);
5721 /* ack status block only if something was actually handled */
5722 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5723 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5726 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5727 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5729 bnx2x_link_report(bp);
5730 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5734 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5736 struct net_device *dev = dev_instance;
5737 struct bnx2x *bp = netdev_priv(dev);
5739 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5740 IGU_INT_DISABLE, 0);
5742 #ifdef BNX2X_STOP_ON_ERROR
5743 if (unlikely(bp->panic))
5747 if (CNIC_LOADED(bp)) {
5748 struct cnic_ops *c_ops;
5751 c_ops = rcu_dereference(bp->cnic_ops);
5753 c_ops->cnic_handler(bp->cnic_data, NULL);
5757 /* schedule sp task to perform default status block work, ack
5758 * attentions and enable interrupts.
5760 bnx2x_schedule_sp_task(bp);
5765 /* end of slow path */
5767 void bnx2x_drv_pulse(struct bnx2x *bp)
5769 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5770 bp->fw_drv_pulse_wr_seq);
5773 static void bnx2x_timer(unsigned long data)
5775 struct bnx2x *bp = (struct bnx2x *) data;
5777 if (!netif_running(bp->dev))
5782 int mb_idx = BP_FW_MB_IDX(bp);
5786 ++bp->fw_drv_pulse_wr_seq;
5787 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5788 drv_pulse = bp->fw_drv_pulse_wr_seq;
5789 bnx2x_drv_pulse(bp);
5791 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5792 MCP_PULSE_SEQ_MASK);
5793 /* The delta between driver pulse and mcp response
5794 * should not get too big. If the MFW is more than 5 pulses
5795 * behind, we should worry about it enough to generate an error
5798 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5799 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5800 drv_pulse, mcp_pulse);
5803 if (bp->state == BNX2X_STATE_OPEN)
5804 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5806 /* sample pf vf bulletin board for new posts from pf */
5808 bnx2x_timer_sriov(bp);
5810 mod_timer(&bp->timer, jiffies + bp->current_interval);
5813 /* end of Statistics */
5818 * nic init service functions
5821 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5824 if (!(len%4) && !(addr%4))
5825 for (i = 0; i < len; i += 4)
5826 REG_WR(bp, addr + i, fill);
5828 for (i = 0; i < len; i++)
5829 REG_WR8(bp, addr + i, fill);
5832 /* helper: writes FP SP data to FW - data_size in dwords */
5833 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5839 for (index = 0; index < data_size; index++)
5840 REG_WR(bp, BAR_CSTRORM_INTMEM +
5841 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5843 *(sb_data_p + index));
5846 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5850 struct hc_status_block_data_e2 sb_data_e2;
5851 struct hc_status_block_data_e1x sb_data_e1x;
5853 /* disable the function first */
5854 if (!CHIP_IS_E1x(bp)) {
5855 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5856 sb_data_e2.common.state = SB_DISABLED;
5857 sb_data_e2.common.p_func.vf_valid = false;
5858 sb_data_p = (u32 *)&sb_data_e2;
5859 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5861 memset(&sb_data_e1x, 0,
5862 sizeof(struct hc_status_block_data_e1x));
5863 sb_data_e1x.common.state = SB_DISABLED;
5864 sb_data_e1x.common.p_func.vf_valid = false;
5865 sb_data_p = (u32 *)&sb_data_e1x;
5866 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5868 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5870 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5871 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5872 CSTORM_STATUS_BLOCK_SIZE);
5873 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5874 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5875 CSTORM_SYNC_BLOCK_SIZE);
5878 /* helper: writes SP SB data to FW */
5879 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5880 struct hc_sp_status_block_data *sp_sb_data)
5882 int func = BP_FUNC(bp);
5884 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5885 REG_WR(bp, BAR_CSTRORM_INTMEM +
5886 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5888 *((u32 *)sp_sb_data + i));
5891 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5893 int func = BP_FUNC(bp);
5894 struct hc_sp_status_block_data sp_sb_data;
5895 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5897 sp_sb_data.state = SB_DISABLED;
5898 sp_sb_data.p_func.vf_valid = false;
5900 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5902 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5903 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5904 CSTORM_SP_STATUS_BLOCK_SIZE);
5905 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5906 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5907 CSTORM_SP_SYNC_BLOCK_SIZE);
5910 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5911 int igu_sb_id, int igu_seg_id)
5913 hc_sm->igu_sb_id = igu_sb_id;
5914 hc_sm->igu_seg_id = igu_seg_id;
5915 hc_sm->timer_value = 0xFF;
5916 hc_sm->time_to_expire = 0xFFFFFFFF;
5919 /* allocates state machine ids. */
5920 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5922 /* zero out state machine indices */
5924 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5927 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5928 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5929 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5930 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5934 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5935 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5938 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5939 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5940 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5941 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5942 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5943 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5944 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5945 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5948 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5949 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5953 struct hc_status_block_data_e2 sb_data_e2;
5954 struct hc_status_block_data_e1x sb_data_e1x;
5955 struct hc_status_block_sm *hc_sm_p;
5959 if (CHIP_INT_MODE_IS_BC(bp))
5960 igu_seg_id = HC_SEG_ACCESS_NORM;
5962 igu_seg_id = IGU_SEG_ACCESS_NORM;
5964 bnx2x_zero_fp_sb(bp, fw_sb_id);
5966 if (!CHIP_IS_E1x(bp)) {
5967 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5968 sb_data_e2.common.state = SB_ENABLED;
5969 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5970 sb_data_e2.common.p_func.vf_id = vfid;
5971 sb_data_e2.common.p_func.vf_valid = vf_valid;
5972 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5973 sb_data_e2.common.same_igu_sb_1b = true;
5974 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5975 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5976 hc_sm_p = sb_data_e2.common.state_machine;
5977 sb_data_p = (u32 *)&sb_data_e2;
5978 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5979 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5981 memset(&sb_data_e1x, 0,
5982 sizeof(struct hc_status_block_data_e1x));
5983 sb_data_e1x.common.state = SB_ENABLED;
5984 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5985 sb_data_e1x.common.p_func.vf_id = 0xff;
5986 sb_data_e1x.common.p_func.vf_valid = false;
5987 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5988 sb_data_e1x.common.same_igu_sb_1b = true;
5989 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5990 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5991 hc_sm_p = sb_data_e1x.common.state_machine;
5992 sb_data_p = (u32 *)&sb_data_e1x;
5993 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5994 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5997 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5998 igu_sb_id, igu_seg_id);
5999 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
6000 igu_sb_id, igu_seg_id);
6002 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
6004 /* write indices to HW - PCI guarantees endianity of regpairs */
6005 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
6008 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6009 u16 tx_usec, u16 rx_usec)
6011 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6013 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6014 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6016 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6017 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6019 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6020 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6024 static void bnx2x_init_def_sb(struct bnx2x *bp)
6026 struct host_sp_status_block *def_sb = bp->def_status_blk;
6027 dma_addr_t mapping = bp->def_status_blk_mapping;
6028 int igu_sp_sb_index;
6030 int port = BP_PORT(bp);
6031 int func = BP_FUNC(bp);
6032 int reg_offset, reg_offset_en5;
6035 struct hc_sp_status_block_data sp_sb_data;
6036 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6038 if (CHIP_INT_MODE_IS_BC(bp)) {
6039 igu_sp_sb_index = DEF_SB_IGU_ID;
6040 igu_seg_id = HC_SEG_ACCESS_DEF;
6042 igu_sp_sb_index = bp->igu_dsb_id;
6043 igu_seg_id = IGU_SEG_ACCESS_DEF;
6047 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6048 atten_status_block);
6049 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6053 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6054 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6055 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6056 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6057 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6059 /* take care of sig[0]..sig[4] */
6060 for (sindex = 0; sindex < 4; sindex++)
6061 bp->attn_group[index].sig[sindex] =
6062 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6064 if (!CHIP_IS_E1x(bp))
6066 * enable5 is separate from the rest of the registers,
6067 * and therefore the address skip is 4
6068 * and not 16 between the different groups
6070 bp->attn_group[index].sig[4] = REG_RD(bp,
6071 reg_offset_en5 + 0x4*index);
6073 bp->attn_group[index].sig[4] = 0;
6076 if (bp->common.int_block == INT_BLOCK_HC) {
6077 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6078 HC_REG_ATTN_MSG0_ADDR_L);
6080 REG_WR(bp, reg_offset, U64_LO(section));
6081 REG_WR(bp, reg_offset + 4, U64_HI(section));
6082 } else if (!CHIP_IS_E1x(bp)) {
6083 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6084 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6087 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6090 bnx2x_zero_sp_sb(bp);
6092 /* PCI guarantees endianity of regpairs */
6093 sp_sb_data.state = SB_ENABLED;
6094 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6095 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6096 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6097 sp_sb_data.igu_seg_id = igu_seg_id;
6098 sp_sb_data.p_func.pf_id = func;
6099 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6100 sp_sb_data.p_func.vf_id = 0xff;
6102 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6104 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6107 void bnx2x_update_coalesce(struct bnx2x *bp)
6111 for_each_eth_queue(bp, i)
6112 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6113 bp->tx_ticks, bp->rx_ticks);
6116 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6118 spin_lock_init(&bp->spq_lock);
6119 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6121 bp->spq_prod_idx = 0;
6122 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6123 bp->spq_prod_bd = bp->spq;
6124 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6127 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6130 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6131 union event_ring_elem *elem =
6132 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6134 elem->next_page.addr.hi =
6135 cpu_to_le32(U64_HI(bp->eq_mapping +
6136 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6137 elem->next_page.addr.lo =
6138 cpu_to_le32(U64_LO(bp->eq_mapping +
6139 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6142 bp->eq_prod = NUM_EQ_DESC;
6143 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6144 /* we want a warning message before it gets wrought... */
6145 atomic_set(&bp->eq_spq_left,
6146 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6149 /* called with netif_addr_lock_bh() */
6150 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6151 unsigned long rx_mode_flags,
6152 unsigned long rx_accept_flags,
6153 unsigned long tx_accept_flags,
6154 unsigned long ramrod_flags)
6156 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6159 memset(&ramrod_param, 0, sizeof(ramrod_param));
6161 /* Prepare ramrod parameters */
6162 ramrod_param.cid = 0;
6163 ramrod_param.cl_id = cl_id;
6164 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6165 ramrod_param.func_id = BP_FUNC(bp);
6167 ramrod_param.pstate = &bp->sp_state;
6168 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6170 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6171 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6173 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6175 ramrod_param.ramrod_flags = ramrod_flags;
6176 ramrod_param.rx_mode_flags = rx_mode_flags;
6178 ramrod_param.rx_accept_flags = rx_accept_flags;
6179 ramrod_param.tx_accept_flags = tx_accept_flags;
6181 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6183 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6190 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6191 unsigned long *rx_accept_flags,
6192 unsigned long *tx_accept_flags)
6194 /* Clear the flags first */
6195 *rx_accept_flags = 0;
6196 *tx_accept_flags = 0;
6199 case BNX2X_RX_MODE_NONE:
6201 * 'drop all' supersedes any accept flags that may have been
6202 * passed to the function.
6205 case BNX2X_RX_MODE_NORMAL:
6206 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6207 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6208 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6210 /* internal switching mode */
6211 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6212 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6213 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6215 if (bp->accept_any_vlan) {
6216 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6217 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6221 case BNX2X_RX_MODE_ALLMULTI:
6222 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6223 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6224 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6226 /* internal switching mode */
6227 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6228 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6229 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6231 if (bp->accept_any_vlan) {
6232 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6233 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6237 case BNX2X_RX_MODE_PROMISC:
6238 /* According to definition of SI mode, iface in promisc mode
6239 * should receive matched and unmatched (in resolution of port)
6242 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6243 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6244 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6245 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6247 /* internal switching mode */
6248 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6249 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6252 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6254 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6256 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6257 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6261 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6268 /* called with netif_addr_lock_bh() */
6269 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6271 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6272 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6276 /* Configure rx_mode of FCoE Queue */
6277 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6279 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6284 __set_bit(RAMROD_RX, &ramrod_flags);
6285 __set_bit(RAMROD_TX, &ramrod_flags);
6287 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6288 rx_accept_flags, tx_accept_flags,
6292 static void bnx2x_init_internal_common(struct bnx2x *bp)
6296 /* Zero this manually as its initialization is
6297 currently missing in the initTool */
6298 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6299 REG_WR(bp, BAR_USTRORM_INTMEM +
6300 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6301 if (!CHIP_IS_E1x(bp)) {
6302 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6303 CHIP_INT_MODE_IS_BC(bp) ?
6304 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6308 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6310 switch (load_code) {
6311 case FW_MSG_CODE_DRV_LOAD_COMMON:
6312 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6313 bnx2x_init_internal_common(bp);
6316 case FW_MSG_CODE_DRV_LOAD_PORT:
6320 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6321 /* internal memory per function is
6322 initialized inside bnx2x_pf_init */
6326 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6331 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6333 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6336 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6338 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6341 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6343 if (CHIP_IS_E1x(fp->bp))
6344 return BP_L_ID(fp->bp) + fp->index;
6345 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6346 return bnx2x_fp_igu_sb_id(fp);
6349 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6351 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6353 unsigned long q_type = 0;
6354 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6355 fp->rx_queue = fp_idx;
6357 fp->cl_id = bnx2x_fp_cl_id(fp);
6358 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6359 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6360 /* qZone id equals to FW (per path) client id */
6361 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6364 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6366 /* Setup SB indices */
6367 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6369 /* Configure Queue State object */
6370 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6371 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6373 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6376 for_each_cos_in_tx_queue(fp, cos) {
6377 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6378 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6379 FP_COS_TO_TXQ(fp, cos, bp),
6380 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6381 cids[cos] = fp->txdata_ptr[cos]->cid;
6384 /* nothing more for vf to do here */
6388 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6389 fp->fw_sb_id, fp->igu_sb_id);
6390 bnx2x_update_fpsb_idx(fp);
6391 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6392 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6393 bnx2x_sp_mapping(bp, q_rdata), q_type);
6396 * Configure classification DBs: Always enable Tx switching
6398 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6401 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6402 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6406 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6410 for (i = 1; i <= NUM_TX_RINGS; i++) {
6411 struct eth_tx_next_bd *tx_next_bd =
6412 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6414 tx_next_bd->addr_hi =
6415 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6416 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6417 tx_next_bd->addr_lo =
6418 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6419 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6422 *txdata->tx_cons_sb = cpu_to_le16(0);
6424 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6425 txdata->tx_db.data.zero_fill1 = 0;
6426 txdata->tx_db.data.prod = 0;
6428 txdata->tx_pkt_prod = 0;
6429 txdata->tx_pkt_cons = 0;
6430 txdata->tx_bd_prod = 0;
6431 txdata->tx_bd_cons = 0;
6435 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6439 for_each_tx_queue_cnic(bp, i)
6440 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6443 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6448 for_each_eth_queue(bp, i)
6449 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6450 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6453 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6455 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6456 unsigned long q_type = 0;
6458 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6459 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6460 BNX2X_FCOE_ETH_CL_ID_IDX);
6461 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6462 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6463 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6464 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6465 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6466 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6469 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6471 /* qZone id equals to FW (per path) client id */
6472 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6474 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6475 bnx2x_rx_ustorm_prods_offset(fp);
6477 /* Configure Queue State object */
6478 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6479 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6481 /* No multi-CoS for FCoE L2 client */
6482 BUG_ON(fp->max_cos != 1);
6484 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6485 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6486 bnx2x_sp_mapping(bp, q_rdata), q_type);
6489 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6490 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6494 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6497 bnx2x_init_fcoe_fp(bp);
6499 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6500 BNX2X_VF_ID_INVALID, false,
6501 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6503 /* ensure status block indices were read */
6505 bnx2x_init_rx_rings_cnic(bp);
6506 bnx2x_init_tx_rings_cnic(bp);
6513 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6517 /* Setup NIC internals and enable interrupts */
6518 for_each_eth_queue(bp, i)
6519 bnx2x_init_eth_fp(bp, i);
6521 /* ensure status block indices were read */
6523 bnx2x_init_rx_rings(bp);
6524 bnx2x_init_tx_rings(bp);
6527 /* Initialize MOD_ABS interrupts */
6528 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6529 bp->common.shmem_base,
6530 bp->common.shmem2_base, BP_PORT(bp));
6532 /* initialize the default status block and sp ring */
6533 bnx2x_init_def_sb(bp);
6534 bnx2x_update_dsb_idx(bp);
6535 bnx2x_init_sp_ring(bp);
6537 bnx2x_memset_stats(bp);
6541 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6543 bnx2x_init_eq_ring(bp);
6544 bnx2x_init_internal(bp, load_code);
6546 bnx2x_stats_init(bp);
6548 /* flush all before enabling interrupts */
6552 bnx2x_int_enable(bp);
6554 /* Check for SPIO5 */
6555 bnx2x_attn_int_deasserted0(bp,
6556 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6557 AEU_INPUTS_ATTN_BITS_SPIO5);
6560 /* gzip service functions */
6561 static int bnx2x_gunzip_init(struct bnx2x *bp)
6563 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6564 &bp->gunzip_mapping, GFP_KERNEL);
6565 if (bp->gunzip_buf == NULL)
6568 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6569 if (bp->strm == NULL)
6572 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6573 if (bp->strm->workspace == NULL)
6583 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6584 bp->gunzip_mapping);
6585 bp->gunzip_buf = NULL;
6588 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6592 static void bnx2x_gunzip_end(struct bnx2x *bp)
6595 vfree(bp->strm->workspace);
6600 if (bp->gunzip_buf) {
6601 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6602 bp->gunzip_mapping);
6603 bp->gunzip_buf = NULL;
6607 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6611 /* check gzip header */
6612 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6613 BNX2X_ERR("Bad gzip header\n");
6621 if (zbuf[3] & FNAME)
6622 while ((zbuf[n++] != 0) && (n < len));
6624 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6625 bp->strm->avail_in = len - n;
6626 bp->strm->next_out = bp->gunzip_buf;
6627 bp->strm->avail_out = FW_BUF_SIZE;
6629 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6633 rc = zlib_inflate(bp->strm, Z_FINISH);
6634 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6635 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6638 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6639 if (bp->gunzip_outlen & 0x3)
6641 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6643 bp->gunzip_outlen >>= 2;
6645 zlib_inflateEnd(bp->strm);
6647 if (rc == Z_STREAM_END)
6653 /* nic load/unload */
6656 * General service functions
6659 /* send a NIG loopback debug packet */
6660 static void bnx2x_lb_pckt(struct bnx2x *bp)
6664 /* Ethernet source and destination addresses */
6665 wb_write[0] = 0x55555555;
6666 wb_write[1] = 0x55555555;
6667 wb_write[2] = 0x20; /* SOP */
6668 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6670 /* NON-IP protocol */
6671 wb_write[0] = 0x09000000;
6672 wb_write[1] = 0x55555555;
6673 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6674 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6677 /* some of the internal memories
6678 * are not directly readable from the driver
6679 * to test them we send debug packets
6681 static int bnx2x_int_mem_test(struct bnx2x *bp)
6687 if (CHIP_REV_IS_FPGA(bp))
6689 else if (CHIP_REV_IS_EMUL(bp))
6694 /* Disable inputs of parser neighbor blocks */
6695 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6696 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6697 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6698 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6700 /* Write 0 to parser credits for CFC search request */
6701 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6703 /* send Ethernet packet */
6706 /* TODO do i reset NIG statistic? */
6707 /* Wait until NIG register shows 1 packet of size 0x10 */
6708 count = 1000 * factor;
6711 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6712 val = *bnx2x_sp(bp, wb_data[0]);
6716 usleep_range(10000, 20000);
6720 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6724 /* Wait until PRS register shows 1 packet */
6725 count = 1000 * factor;
6727 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6731 usleep_range(10000, 20000);
6735 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6739 /* Reset and init BRB, PRS */
6740 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6742 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6744 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6745 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6747 DP(NETIF_MSG_HW, "part2\n");
6749 /* Disable inputs of parser neighbor blocks */
6750 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6751 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6752 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6753 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6755 /* Write 0 to parser credits for CFC search request */
6756 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6758 /* send 10 Ethernet packets */
6759 for (i = 0; i < 10; i++)
6762 /* Wait until NIG register shows 10 + 1
6763 packets of size 11*0x10 = 0xb0 */
6764 count = 1000 * factor;
6767 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6768 val = *bnx2x_sp(bp, wb_data[0]);
6772 usleep_range(10000, 20000);
6776 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6780 /* Wait until PRS register shows 2 packets */
6781 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6783 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6785 /* Write 1 to parser credits for CFC search request */
6786 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6788 /* Wait until PRS register shows 3 packets */
6789 msleep(10 * factor);
6790 /* Wait until NIG register shows 1 packet of size 0x10 */
6791 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6793 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6795 /* clear NIG EOP FIFO */
6796 for (i = 0; i < 11; i++)
6797 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6798 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6800 BNX2X_ERR("clear of NIG failed\n");
6804 /* Reset and init BRB, PRS, NIG */
6805 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6807 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6809 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6810 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6811 if (!CNIC_SUPPORT(bp))
6813 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6815 /* Enable inputs of parser neighbor blocks */
6816 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6817 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6818 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6819 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6821 DP(NETIF_MSG_HW, "done\n");
6826 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6830 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6831 if (!CHIP_IS_E1x(bp))
6832 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6834 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6835 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6836 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6838 * mask read length error interrupts in brb for parser
6839 * (parsing unit and 'checksum and crc' unit)
6840 * these errors are legal (PU reads fixed length and CAC can cause
6841 * read length error on truncated packets)
6843 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6844 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6845 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6846 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6847 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6848 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6849 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6850 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6851 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6852 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6853 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6854 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6855 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6856 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6857 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6858 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6859 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6860 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6861 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6863 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6864 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6865 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6866 if (!CHIP_IS_E1x(bp))
6867 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6868 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6869 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6871 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6872 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6873 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6874 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6876 if (!CHIP_IS_E1x(bp))
6877 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6878 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6880 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6881 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6882 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6883 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6886 static void bnx2x_reset_common(struct bnx2x *bp)
6891 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6894 if (CHIP_IS_E3(bp)) {
6895 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6896 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6899 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6902 static void bnx2x_setup_dmae(struct bnx2x *bp)
6905 spin_lock_init(&bp->dmae_lock);
6908 static void bnx2x_init_pxp(struct bnx2x *bp)
6911 int r_order, w_order;
6913 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6914 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6915 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6917 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6919 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6923 bnx2x_init_pxp_arb(bp, r_order, w_order);
6926 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6936 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6937 SHARED_HW_CFG_FAN_FAILURE_MASK;
6939 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6943 * The fan failure mechanism is usually related to the PHY type since
6944 * the power consumption of the board is affected by the PHY. Currently,
6945 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6947 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6948 for (port = PORT_0; port < PORT_MAX; port++) {
6950 bnx2x_fan_failure_det_req(
6952 bp->common.shmem_base,
6953 bp->common.shmem2_base,
6957 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6959 if (is_required == 0)
6962 /* Fan failure is indicated by SPIO 5 */
6963 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6965 /* set to active low mode */
6966 val = REG_RD(bp, MISC_REG_SPIO_INT);
6967 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6968 REG_WR(bp, MISC_REG_SPIO_INT, val);
6970 /* enable interrupt to signal the IGU */
6971 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6972 val |= MISC_SPIO_SPIO5;
6973 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6976 void bnx2x_pf_disable(struct bnx2x *bp)
6978 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6979 val &= ~IGU_PF_CONF_FUNC_EN;
6981 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6982 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6983 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6986 static void bnx2x__common_init_phy(struct bnx2x *bp)
6988 u32 shmem_base[2], shmem2_base[2];
6989 /* Avoid common init in case MFW supports LFA */
6990 if (SHMEM2_RD(bp, size) >
6991 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6993 shmem_base[0] = bp->common.shmem_base;
6994 shmem2_base[0] = bp->common.shmem2_base;
6995 if (!CHIP_IS_E1x(bp)) {
6997 SHMEM2_RD(bp, other_shmem_base_addr);
6999 SHMEM2_RD(bp, other_shmem2_base_addr);
7001 bnx2x_acquire_phy_lock(bp);
7002 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
7003 bp->common.chip_id);
7004 bnx2x_release_phy_lock(bp);
7007 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7009 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7010 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7011 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7012 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7013 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7015 /* make sure this value is 0 */
7016 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7018 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7019 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7020 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7021 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7024 static void bnx2x_set_endianity(struct bnx2x *bp)
7027 bnx2x_config_endianity(bp, 1);
7029 bnx2x_config_endianity(bp, 0);
7033 static void bnx2x_reset_endianity(struct bnx2x *bp)
7035 bnx2x_config_endianity(bp, 0);
7039 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7041 * @bp: driver handle
7043 static int bnx2x_init_hw_common(struct bnx2x *bp)
7047 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
7050 * take the RESET lock to protect undi_unload flow from accessing
7051 * registers while we're resetting the chip
7053 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7055 bnx2x_reset_common(bp);
7056 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7059 if (CHIP_IS_E3(bp)) {
7060 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7061 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7063 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7065 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7067 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7069 if (!CHIP_IS_E1x(bp)) {
7073 * 4-port mode or 2-port mode we need to turn of master-enable
7074 * for everyone, after that, turn it back on for self.
7075 * so, we disregard multi-function or not, and always disable
7076 * for all functions on the given path, this means 0,2,4,6 for
7077 * path 0 and 1,3,5,7 for path 1
7079 for (abs_func_id = BP_PATH(bp);
7080 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7081 if (abs_func_id == BP_ABS_FUNC(bp)) {
7083 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7088 bnx2x_pretend_func(bp, abs_func_id);
7089 /* clear pf enable */
7090 bnx2x_pf_disable(bp);
7091 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7095 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7096 if (CHIP_IS_E1(bp)) {
7097 /* enable HW interrupt from PXP on USDM overflow
7098 bit 16 on INT_MASK_0 */
7099 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7102 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7104 bnx2x_set_endianity(bp);
7105 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7107 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7108 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7110 /* let the HW do it's magic ... */
7112 /* finish PXP init */
7113 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7115 BNX2X_ERR("PXP2 CFG failed\n");
7118 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7120 BNX2X_ERR("PXP2 RD_INIT failed\n");
7124 /* Timers bug workaround E2 only. We need to set the entire ILT to
7125 * have entries with value "0" and valid bit on.
7126 * This needs to be done by the first PF that is loaded in a path
7127 * (i.e. common phase)
7129 if (!CHIP_IS_E1x(bp)) {
7130 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7131 * (i.e. vnic3) to start even if it is marked as "scan-off".
7132 * This occurs when a different function (func2,3) is being marked
7133 * as "scan-off". Real-life scenario for example: if a driver is being
7134 * load-unloaded while func6,7 are down. This will cause the timer to access
7135 * the ilt, translate to a logical address and send a request to read/write.
7136 * Since the ilt for the function that is down is not valid, this will cause
7137 * a translation error which is unrecoverable.
7138 * The Workaround is intended to make sure that when this happens nothing fatal
7139 * will occur. The workaround:
7140 * 1. First PF driver which loads on a path will:
7141 * a. After taking the chip out of reset, by using pretend,
7142 * it will write "0" to the following registers of
7144 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7145 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7146 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7147 * And for itself it will write '1' to
7148 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7149 * dmae-operations (writing to pram for example.)
7150 * note: can be done for only function 6,7 but cleaner this
7152 * b. Write zero+valid to the entire ILT.
7153 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7154 * VNIC3 (of that port). The range allocated will be the
7155 * entire ILT. This is needed to prevent ILT range error.
7156 * 2. Any PF driver load flow:
7157 * a. ILT update with the physical addresses of the allocated
7159 * b. Wait 20msec. - note that this timeout is needed to make
7160 * sure there are no requests in one of the PXP internal
7161 * queues with "old" ILT addresses.
7162 * c. PF enable in the PGLC.
7163 * d. Clear the was_error of the PF in the PGLC. (could have
7164 * occurred while driver was down)
7165 * e. PF enable in the CFC (WEAK + STRONG)
7166 * f. Timers scan enable
7167 * 3. PF driver unload flow:
7168 * a. Clear the Timers scan_en.
7169 * b. Polling for scan_on=0 for that PF.
7170 * c. Clear the PF enable bit in the PXP.
7171 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7172 * e. Write zero+valid to all ILT entries (The valid bit must
7174 * f. If this is VNIC 3 of a port then also init
7175 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7176 * to the last entry in the ILT.
7179 * Currently the PF error in the PGLC is non recoverable.
7180 * In the future the there will be a recovery routine for this error.
7181 * Currently attention is masked.
7182 * Having an MCP lock on the load/unload process does not guarantee that
7183 * there is no Timer disable during Func6/7 enable. This is because the
7184 * Timers scan is currently being cleared by the MCP on FLR.
7185 * Step 2.d can be done only for PF6/7 and the driver can also check if
7186 * there is error before clearing it. But the flow above is simpler and
7188 * All ILT entries are written by zero+valid and not just PF6/7
7189 * ILT entries since in the future the ILT entries allocation for
7190 * PF-s might be dynamic.
7192 struct ilt_client_info ilt_cli;
7193 struct bnx2x_ilt ilt;
7194 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7195 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7197 /* initialize dummy TM client */
7199 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7200 ilt_cli.client_num = ILT_CLIENT_TM;
7202 /* Step 1: set zeroes to all ilt page entries with valid bit on
7203 * Step 2: set the timers first/last ilt entry to point
7204 * to the entire range to prevent ILT range error for 3rd/4th
7205 * vnic (this code assumes existence of the vnic)
7207 * both steps performed by call to bnx2x_ilt_client_init_op()
7208 * with dummy TM client
7210 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7211 * and his brother are split registers
7213 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7214 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7215 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7217 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7218 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7219 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7222 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7223 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7225 if (!CHIP_IS_E1x(bp)) {
7226 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7227 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7228 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7230 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7232 /* let the HW do it's magic ... */
7235 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7236 } while (factor-- && (val != 1));
7239 BNX2X_ERR("ATC_INIT failed\n");
7244 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7246 bnx2x_iov_init_dmae(bp);
7248 /* clean the DMAE memory */
7250 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7252 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7254 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7256 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7258 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7260 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7261 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7262 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7263 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7265 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7267 /* QM queues pointers table */
7268 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7270 /* soft reset pulse */
7271 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7272 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7274 if (CNIC_SUPPORT(bp))
7275 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7277 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7279 if (!CHIP_REV_IS_SLOW(bp))
7280 /* enable hw interrupt from doorbell Q */
7281 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7283 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7285 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7286 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7288 if (!CHIP_IS_E1(bp))
7289 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7291 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7292 if (IS_MF_AFEX(bp)) {
7293 /* configure that VNTag and VLAN headers must be
7294 * received in afex mode
7296 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7297 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7298 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7299 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7300 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7302 /* Bit-map indicating which L2 hdrs may appear
7303 * after the basic Ethernet header
7305 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7306 bp->path_has_ovlan ? 7 : 6);
7310 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7311 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7312 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7313 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7315 if (!CHIP_IS_E1x(bp)) {
7316 /* reset VFC memories */
7317 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7318 VFC_MEMORIES_RST_REG_CAM_RST |
7319 VFC_MEMORIES_RST_REG_RAM_RST);
7320 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7321 VFC_MEMORIES_RST_REG_CAM_RST |
7322 VFC_MEMORIES_RST_REG_RAM_RST);
7327 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7328 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7329 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7330 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7333 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7338 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7339 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7340 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7342 if (!CHIP_IS_E1x(bp)) {
7343 if (IS_MF_AFEX(bp)) {
7344 /* configure that VNTag and VLAN headers must be
7347 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7348 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7349 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7350 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7351 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7353 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7354 bp->path_has_ovlan ? 7 : 6);
7358 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7360 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7362 if (CNIC_SUPPORT(bp)) {
7363 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7364 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7365 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7366 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7367 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7368 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7369 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7370 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7371 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7372 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7374 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7376 if (sizeof(union cdu_context) != 1024)
7377 /* we currently assume that a context is 1024 bytes */
7378 dev_alert(&bp->pdev->dev,
7379 "please adjust the size of cdu_context(%ld)\n",
7380 (long)sizeof(union cdu_context));
7382 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7383 val = (4 << 24) + (0 << 12) + 1024;
7384 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7386 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7387 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7388 /* enable context validation interrupt from CFC */
7389 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7391 /* set the thresholds to prevent CFC/CDU race */
7392 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7394 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7396 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7397 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7399 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7400 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7402 /* Reset PCIE errors for debug */
7403 REG_WR(bp, 0x2814, 0xffffffff);
7404 REG_WR(bp, 0x3820, 0xffffffff);
7406 if (!CHIP_IS_E1x(bp)) {
7407 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7408 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7409 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7410 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7411 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7412 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7413 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7414 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7415 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7416 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7417 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7420 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7421 if (!CHIP_IS_E1(bp)) {
7422 /* in E3 this done in per-port section */
7423 if (!CHIP_IS_E3(bp))
7424 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7426 if (CHIP_IS_E1H(bp))
7427 /* not applicable for E2 (and above ...) */
7428 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7430 if (CHIP_REV_IS_SLOW(bp))
7433 /* finish CFC init */
7434 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7436 BNX2X_ERR("CFC LL_INIT failed\n");
7439 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7441 BNX2X_ERR("CFC AC_INIT failed\n");
7444 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7446 BNX2X_ERR("CFC CAM_INIT failed\n");
7449 REG_WR(bp, CFC_REG_DEBUG0, 0);
7451 if (CHIP_IS_E1(bp)) {
7452 /* read NIG statistic
7453 to see if this is our first up since powerup */
7454 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7455 val = *bnx2x_sp(bp, wb_data[0]);
7457 /* do internal memory self test */
7458 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7459 BNX2X_ERR("internal mem self test failed\n");
7464 bnx2x_setup_fan_failure_detection(bp);
7466 /* clear PXP2 attentions */
7467 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7469 bnx2x_enable_blocks_attention(bp);
7470 bnx2x_enable_blocks_parity(bp);
7472 if (!BP_NOMCP(bp)) {
7473 if (CHIP_IS_E1x(bp))
7474 bnx2x__common_init_phy(bp);
7476 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7478 if (SHMEM2_HAS(bp, netproc_fw_ver))
7479 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7485 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7487 * @bp: driver handle
7489 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7491 int rc = bnx2x_init_hw_common(bp);
7496 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7498 bnx2x__common_init_phy(bp);
7503 static int bnx2x_init_hw_port(struct bnx2x *bp)
7505 int port = BP_PORT(bp);
7506 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7510 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7512 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7514 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7515 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7516 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7518 /* Timers bug workaround: disables the pf_master bit in pglue at
7519 * common phase, we need to enable it here before any dmae access are
7520 * attempted. Therefore we manually added the enable-master to the
7521 * port phase (it also happens in the function phase)
7523 if (!CHIP_IS_E1x(bp))
7524 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7526 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7527 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7528 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7529 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7531 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7532 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7533 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7534 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7536 /* QM cid (connection) count */
7537 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7539 if (CNIC_SUPPORT(bp)) {
7540 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7541 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7542 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7545 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7547 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7549 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7552 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7553 else if (bp->dev->mtu > 4096) {
7554 if (bp->flags & ONE_PORT_FLAG)
7558 /* (24*1024 + val*4)/256 */
7559 low = 96 + (val/64) +
7560 ((val % 64) ? 1 : 0);
7563 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7564 high = low + 56; /* 14*1024/256 */
7565 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7566 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7569 if (CHIP_MODE_IS_4_PORT(bp))
7570 REG_WR(bp, (BP_PORT(bp) ?
7571 BRB1_REG_MAC_GUARANTIED_1 :
7572 BRB1_REG_MAC_GUARANTIED_0), 40);
7574 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7575 if (CHIP_IS_E3B0(bp)) {
7576 if (IS_MF_AFEX(bp)) {
7577 /* configure headers for AFEX mode */
7578 REG_WR(bp, BP_PORT(bp) ?
7579 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7580 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7581 REG_WR(bp, BP_PORT(bp) ?
7582 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7583 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7584 REG_WR(bp, BP_PORT(bp) ?
7585 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7586 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7588 /* Ovlan exists only if we are in multi-function +
7589 * switch-dependent mode, in switch-independent there
7590 * is no ovlan headers
7592 REG_WR(bp, BP_PORT(bp) ?
7593 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7594 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7595 (bp->path_has_ovlan ? 7 : 6));
7599 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7600 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7601 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7602 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7604 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7605 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7606 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7607 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7609 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7610 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7612 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7614 if (CHIP_IS_E1x(bp)) {
7615 /* configure PBF to work without PAUSE mtu 9000 */
7616 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7618 /* update threshold */
7619 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7620 /* update init credit */
7621 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7624 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7626 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7629 if (CNIC_SUPPORT(bp))
7630 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7632 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7633 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7635 if (CHIP_IS_E1(bp)) {
7636 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7637 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7639 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7641 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7643 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7644 /* init aeu_mask_attn_func_0/1:
7645 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7646 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7647 * bits 4-7 are used for "per vn group attention" */
7648 val = IS_MF(bp) ? 0xF7 : 0x7;
7649 /* Enable DCBX attention for all but E1 */
7650 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7651 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7653 /* SCPAD_PARITY should NOT trigger close the gates */
7654 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7657 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7659 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7662 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7664 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7666 if (!CHIP_IS_E1x(bp)) {
7667 /* Bit-map indicating which L2 hdrs may appear after the
7668 * basic Ethernet header
7671 REG_WR(bp, BP_PORT(bp) ?
7672 NIG_REG_P1_HDRS_AFTER_BASIC :
7673 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7675 REG_WR(bp, BP_PORT(bp) ?
7676 NIG_REG_P1_HDRS_AFTER_BASIC :
7677 NIG_REG_P0_HDRS_AFTER_BASIC,
7678 IS_MF_SD(bp) ? 7 : 6);
7681 REG_WR(bp, BP_PORT(bp) ?
7682 NIG_REG_LLH1_MF_MODE :
7683 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7685 if (!CHIP_IS_E3(bp))
7686 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7688 if (!CHIP_IS_E1(bp)) {
7689 /* 0x2 disable mf_ov, 0x1 enable */
7690 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7691 (IS_MF_SD(bp) ? 0x1 : 0x2));
7693 if (!CHIP_IS_E1x(bp)) {
7695 switch (bp->mf_mode) {
7696 case MULTI_FUNCTION_SD:
7699 case MULTI_FUNCTION_SI:
7700 case MULTI_FUNCTION_AFEX:
7705 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7706 NIG_REG_LLH0_CLS_TYPE), val);
7709 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7710 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7711 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7715 /* If SPIO5 is set to generate interrupts, enable it for this port */
7716 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7717 if (val & MISC_SPIO_SPIO5) {
7718 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7719 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7720 val = REG_RD(bp, reg_addr);
7721 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7722 REG_WR(bp, reg_addr, val);
7728 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7734 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7736 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7738 wb_write[0] = ONCHIP_ADDR1(addr);
7739 wb_write[1] = ONCHIP_ADDR2(addr);
7740 REG_WR_DMAE(bp, reg, wb_write, 2);
7743 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7745 u32 data, ctl, cnt = 100;
7746 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7747 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7748 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7749 u32 sb_bit = 1 << (idu_sb_id%32);
7750 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7751 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7753 /* Not supported in BC mode */
7754 if (CHIP_INT_MODE_IS_BC(bp))
7757 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7758 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7759 IGU_REGULAR_CLEANUP_SET |
7760 IGU_REGULAR_BCLEANUP;
7762 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7763 func_encode << IGU_CTRL_REG_FID_SHIFT |
7764 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7766 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7767 data, igu_addr_data);
7768 REG_WR(bp, igu_addr_data, data);
7771 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7773 REG_WR(bp, igu_addr_ctl, ctl);
7777 /* wait for clean up to finish */
7778 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7781 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7783 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7784 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7788 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7790 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7793 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7795 u32 i, base = FUNC_ILT_BASE(func);
7796 for (i = base; i < base + ILT_PER_FUNC; i++)
7797 bnx2x_ilt_wr(bp, i, 0);
7800 static void bnx2x_init_searcher(struct bnx2x *bp)
7802 int port = BP_PORT(bp);
7803 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7804 /* T1 hash bits value determines the T1 number of entries */
7805 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7808 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7811 struct bnx2x_func_state_params func_params = {NULL};
7812 struct bnx2x_func_switch_update_params *switch_update_params =
7813 &func_params.params.switch_update;
7815 /* Prepare parameters for function state transitions */
7816 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7817 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7819 func_params.f_obj = &bp->func_obj;
7820 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7822 /* Function parameters */
7823 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7824 &switch_update_params->changes);
7826 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7827 &switch_update_params->changes);
7829 rc = bnx2x_func_state_change(bp, &func_params);
7834 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7836 int rc, i, port = BP_PORT(bp);
7837 int vlan_en = 0, mac_en[NUM_MACS];
7839 /* Close input from network */
7840 if (bp->mf_mode == SINGLE_FUNCTION) {
7841 bnx2x_set_rx_filter(&bp->link_params, 0);
7843 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7844 NIG_REG_LLH0_FUNC_EN);
7845 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7846 NIG_REG_LLH0_FUNC_EN, 0);
7847 for (i = 0; i < NUM_MACS; i++) {
7848 mac_en[i] = REG_RD(bp, port ?
7849 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7851 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7853 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7855 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7859 /* Close BMC to host */
7860 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7861 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7863 /* Suspend Tx switching to the PF. Completion of this ramrod
7864 * further guarantees that all the packets of that PF / child
7865 * VFs in BRB were processed by the Parser, so it is safe to
7866 * change the NIC_MODE register.
7868 rc = bnx2x_func_switch_update(bp, 1);
7870 BNX2X_ERR("Can't suspend tx-switching!\n");
7874 /* Change NIC_MODE register */
7875 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7877 /* Open input from network */
7878 if (bp->mf_mode == SINGLE_FUNCTION) {
7879 bnx2x_set_rx_filter(&bp->link_params, 1);
7881 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7882 NIG_REG_LLH0_FUNC_EN, vlan_en);
7883 for (i = 0; i < NUM_MACS; i++) {
7884 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7886 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7891 /* Enable BMC to host */
7892 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7893 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7895 /* Resume Tx switching to the PF */
7896 rc = bnx2x_func_switch_update(bp, 0);
7898 BNX2X_ERR("Can't resume tx-switching!\n");
7902 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7906 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7910 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7912 if (CONFIGURE_NIC_MODE(bp)) {
7913 /* Configure searcher as part of function hw init */
7914 bnx2x_init_searcher(bp);
7916 /* Reset NIC mode */
7917 rc = bnx2x_reset_nic_mode(bp);
7919 BNX2X_ERR("Can't change NIC mode!\n");
7926 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7927 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7928 * the addresses of the transaction, resulting in was-error bit set in the pci
7929 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7930 * to clear the interrupt which detected this from the pglueb and the was done
7933 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7935 if (!CHIP_IS_E1x(bp))
7936 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7937 1 << BP_ABS_FUNC(bp));
7940 static int bnx2x_init_hw_func(struct bnx2x *bp)
7942 int port = BP_PORT(bp);
7943 int func = BP_FUNC(bp);
7944 int init_phase = PHASE_PF0 + func;
7945 struct bnx2x_ilt *ilt = BP_ILT(bp);
7948 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7949 int i, main_mem_width, rc;
7951 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7953 /* FLR cleanup - hmmm */
7954 if (!CHIP_IS_E1x(bp)) {
7955 rc = bnx2x_pf_flr_clnup(bp);
7962 /* set MSI reconfigure capability */
7963 if (bp->common.int_block == INT_BLOCK_HC) {
7964 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7965 val = REG_RD(bp, addr);
7966 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7967 REG_WR(bp, addr, val);
7970 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7971 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7974 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7977 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7978 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7980 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7981 * those of the VFs, so start line should be reset
7983 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7984 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7985 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7986 ilt->lines[cdu_ilt_start + i].page_mapping =
7987 bp->context[i].cxt_mapping;
7988 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7991 bnx2x_ilt_init_op(bp, INITOP_SET);
7993 if (!CONFIGURE_NIC_MODE(bp)) {
7994 bnx2x_init_searcher(bp);
7995 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7996 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7999 REG_WR(bp, PRS_REG_NIC_MODE, 1);
8000 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
8003 if (!CHIP_IS_E1x(bp)) {
8004 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
8006 /* Turn on a single ISR mode in IGU if driver is going to use
8009 if (!(bp->flags & USING_MSIX_FLAG))
8010 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8012 * Timers workaround bug: function init part.
8013 * Need to wait 20msec after initializing ILT,
8014 * needed to make sure there are no requests in
8015 * one of the PXP internal queues with "old" ILT addresses
8019 * Master enable - Due to WB DMAE writes performed before this
8020 * register is re-initialized as part of the regular function
8023 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8024 /* Enable the function in IGU */
8025 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8030 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8032 bnx2x_clean_pglue_errors(bp);
8034 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8035 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8036 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8037 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8038 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8039 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8040 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8041 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8042 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8043 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8044 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8045 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8046 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8048 if (!CHIP_IS_E1x(bp))
8049 REG_WR(bp, QM_REG_PF_EN, 1);
8051 if (!CHIP_IS_E1x(bp)) {
8052 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8053 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8054 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8055 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8057 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8059 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8060 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8061 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8063 bnx2x_iov_init_dq(bp);
8065 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8066 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8067 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8068 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8069 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8070 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8071 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8072 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8073 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8074 if (!CHIP_IS_E1x(bp))
8075 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8077 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8079 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8081 if (!CHIP_IS_E1x(bp))
8082 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8085 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8086 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8087 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8092 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8094 /* HC init per function */
8095 if (bp->common.int_block == INT_BLOCK_HC) {
8096 if (CHIP_IS_E1H(bp)) {
8097 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8099 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8100 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8102 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8105 int num_segs, sb_idx, prod_offset;
8107 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8109 if (!CHIP_IS_E1x(bp)) {
8110 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8111 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8114 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8116 if (!CHIP_IS_E1x(bp)) {
8120 * E2 mode: address 0-135 match to the mapping memory;
8121 * 136 - PF0 default prod; 137 - PF1 default prod;
8122 * 138 - PF2 default prod; 139 - PF3 default prod;
8123 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8124 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8127 * E1.5 mode - In backward compatible mode;
8128 * for non default SB; each even line in the memory
8129 * holds the U producer and each odd line hold
8130 * the C producer. The first 128 producers are for
8131 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8132 * producers are for the DSB for each PF.
8133 * Each PF has five segments: (the order inside each
8134 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8135 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8136 * 144-147 attn prods;
8138 /* non-default-status-blocks */
8139 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8140 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8141 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8142 prod_offset = (bp->igu_base_sb + sb_idx) *
8145 for (i = 0; i < num_segs; i++) {
8146 addr = IGU_REG_PROD_CONS_MEMORY +
8147 (prod_offset + i) * 4;
8148 REG_WR(bp, addr, 0);
8150 /* send consumer update with value 0 */
8151 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8152 USTORM_ID, 0, IGU_INT_NOP, 1);
8153 bnx2x_igu_clear_sb(bp,
8154 bp->igu_base_sb + sb_idx);
8157 /* default-status-blocks */
8158 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8159 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8161 if (CHIP_MODE_IS_4_PORT(bp))
8162 dsb_idx = BP_FUNC(bp);
8164 dsb_idx = BP_VN(bp);
8166 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8167 IGU_BC_BASE_DSB_PROD + dsb_idx :
8168 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8171 * igu prods come in chunks of E1HVN_MAX (4) -
8172 * does not matters what is the current chip mode
8174 for (i = 0; i < (num_segs * E1HVN_MAX);
8176 addr = IGU_REG_PROD_CONS_MEMORY +
8177 (prod_offset + i)*4;
8178 REG_WR(bp, addr, 0);
8180 /* send consumer update with 0 */
8181 if (CHIP_INT_MODE_IS_BC(bp)) {
8182 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8183 USTORM_ID, 0, IGU_INT_NOP, 1);
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185 CSTORM_ID, 0, IGU_INT_NOP, 1);
8186 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8187 XSTORM_ID, 0, IGU_INT_NOP, 1);
8188 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8189 TSTORM_ID, 0, IGU_INT_NOP, 1);
8190 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8191 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8193 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8194 USTORM_ID, 0, IGU_INT_NOP, 1);
8195 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8196 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8198 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8200 /* !!! These should become driver const once
8201 rf-tool supports split-68 const */
8202 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8203 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8204 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8205 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8206 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8207 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8211 /* Reset PCIE errors for debug */
8212 REG_WR(bp, 0x2114, 0xffffffff);
8213 REG_WR(bp, 0x2120, 0xffffffff);
8215 if (CHIP_IS_E1x(bp)) {
8216 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8217 main_mem_base = HC_REG_MAIN_MEMORY +
8218 BP_PORT(bp) * (main_mem_size * 4);
8219 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8222 val = REG_RD(bp, main_mem_prty_clr);
8225 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8228 /* Clear "false" parity errors in MSI-X table */
8229 for (i = main_mem_base;
8230 i < main_mem_base + main_mem_size * 4;
8231 i += main_mem_width) {
8232 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8233 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8234 i, main_mem_width / 4);
8236 /* Clear HC parity attention */
8237 REG_RD(bp, main_mem_prty_clr);
8240 #ifdef BNX2X_STOP_ON_ERROR
8241 /* Enable STORMs SP logging */
8242 REG_WR8(bp, BAR_USTRORM_INTMEM +
8243 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8244 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8245 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8246 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8247 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8248 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8249 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8252 bnx2x_phy_probe(&bp->link_params);
8257 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8259 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8261 if (!CHIP_IS_E1x(bp))
8262 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8263 sizeof(struct host_hc_status_block_e2));
8265 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8266 sizeof(struct host_hc_status_block_e1x));
8268 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8271 void bnx2x_free_mem(struct bnx2x *bp)
8275 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8276 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8281 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8282 sizeof(struct host_sp_status_block));
8284 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8285 sizeof(struct bnx2x_slowpath));
8287 for (i = 0; i < L2_ILT_LINES(bp); i++)
8288 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8289 bp->context[i].size);
8290 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8292 BNX2X_FREE(bp->ilt->lines);
8294 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8296 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8297 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8299 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8301 bnx2x_iov_free_mem(bp);
8304 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8306 if (!CHIP_IS_E1x(bp)) {
8307 /* size = the status block + ramrod buffers */
8308 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8309 sizeof(struct host_hc_status_block_e2));
8310 if (!bp->cnic_sb.e2_sb)
8313 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8314 sizeof(struct host_hc_status_block_e1x));
8315 if (!bp->cnic_sb.e1x_sb)
8319 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8320 /* allocate searcher T2 table, as it wasn't allocated before */
8321 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8326 /* write address to which L5 should insert its values */
8327 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8328 &bp->slowpath->drv_info_to_mcp;
8330 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8336 bnx2x_free_mem_cnic(bp);
8337 BNX2X_ERR("Can't allocate memory\n");
8341 int bnx2x_alloc_mem(struct bnx2x *bp)
8343 int i, allocated, context_size;
8345 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8346 /* allocate searcher T2 table */
8347 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8352 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8353 sizeof(struct host_sp_status_block));
8354 if (!bp->def_status_blk)
8357 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8358 sizeof(struct bnx2x_slowpath));
8362 /* Allocate memory for CDU context:
8363 * This memory is allocated separately and not in the generic ILT
8364 * functions because CDU differs in few aspects:
8365 * 1. There are multiple entities allocating memory for context -
8366 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8367 * its own ILT lines.
8368 * 2. Since CDU page-size is not a single 4KB page (which is the case
8369 * for the other ILT clients), to be efficient we want to support
8370 * allocation of sub-page-size in the last entry.
8371 * 3. Context pointers are used by the driver to pass to FW / update
8372 * the context (for the other ILT clients the pointers are used just to
8373 * free the memory during unload).
8375 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8377 for (i = 0, allocated = 0; allocated < context_size; i++) {
8378 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8379 (context_size - allocated));
8380 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8381 bp->context[i].size);
8382 if (!bp->context[i].vcxt)
8384 allocated += bp->context[i].size;
8386 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8388 if (!bp->ilt->lines)
8391 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8394 if (bnx2x_iov_alloc_mem(bp))
8397 /* Slow path ring */
8398 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8403 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8404 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8412 BNX2X_ERR("Can't allocate memory\n");
8417 * Init service functions
8420 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8421 struct bnx2x_vlan_mac_obj *obj, bool set,
8422 int mac_type, unsigned long *ramrod_flags)
8425 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8427 memset(&ramrod_param, 0, sizeof(ramrod_param));
8429 /* Fill general parameters */
8430 ramrod_param.vlan_mac_obj = obj;
8431 ramrod_param.ramrod_flags = *ramrod_flags;
8433 /* Fill a user request section if needed */
8434 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8435 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8437 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8439 /* Set the command: ADD or DEL */
8441 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8443 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8446 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8448 if (rc == -EEXIST) {
8449 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8450 /* do not treat adding same MAC as error */
8453 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8458 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8459 struct bnx2x_vlan_mac_obj *obj, bool set,
8460 unsigned long *ramrod_flags)
8463 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8465 memset(&ramrod_param, 0, sizeof(ramrod_param));
8467 /* Fill general parameters */
8468 ramrod_param.vlan_mac_obj = obj;
8469 ramrod_param.ramrod_flags = *ramrod_flags;
8471 /* Fill a user request section if needed */
8472 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8473 ramrod_param.user_req.u.vlan.vlan = vlan;
8474 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags);
8475 /* Set the command: ADD or DEL */
8477 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8479 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8482 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8484 if (rc == -EEXIST) {
8485 /* Do not treat adding same vlan as error. */
8486 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8488 } else if (rc < 0) {
8489 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8495 void bnx2x_clear_vlan_info(struct bnx2x *bp)
8497 struct bnx2x_vlan_entry *vlan;
8499 /* Mark that hw forgot all entries */
8500 list_for_each_entry(vlan, &bp->vlan_reg, link)
8506 static int bnx2x_del_all_vlans(struct bnx2x *bp)
8508 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj;
8509 unsigned long ramrod_flags = 0, vlan_flags = 0;
8512 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8513 __set_bit(BNX2X_VLAN, &vlan_flags);
8514 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags);
8518 bnx2x_clear_vlan_info(bp);
8523 int bnx2x_del_all_macs(struct bnx2x *bp,
8524 struct bnx2x_vlan_mac_obj *mac_obj,
8525 int mac_type, bool wait_for_comp)
8528 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8530 /* Wait for completion of requested */
8532 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8534 /* Set the mac type of addresses we want to clear */
8535 __set_bit(mac_type, &vlan_mac_flags);
8537 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8539 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8544 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8547 unsigned long ramrod_flags = 0;
8549 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8550 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8551 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8552 &bp->sp_objs->mac_obj, set,
8553 BNX2X_ETH_MAC, &ramrod_flags);
8555 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8556 bp->fp->index, set);
8560 int bnx2x_setup_leading(struct bnx2x *bp)
8563 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8565 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8569 * bnx2x_set_int_mode - configure interrupt mode
8571 * @bp: driver handle
8573 * In case of MSI-X it will also try to enable MSI-X.
8575 int bnx2x_set_int_mode(struct bnx2x *bp)
8579 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8580 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8585 case BNX2X_INT_MODE_MSIX:
8586 /* attempt to enable msix */
8587 rc = bnx2x_enable_msix(bp);
8593 /* vfs use only msix */
8594 if (rc && IS_VF(bp))
8597 /* failed to enable multiple MSI-X */
8598 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8600 1 + bp->num_cnic_queues);
8602 /* falling through... */
8603 case BNX2X_INT_MODE_MSI:
8604 bnx2x_enable_msi(bp);
8606 /* falling through... */
8607 case BNX2X_INT_MODE_INTX:
8608 bp->num_ethernet_queues = 1;
8609 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8610 BNX2X_DEV_INFO("set number of queues to 1\n");
8613 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8619 /* must be called prior to any HW initializations */
8620 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8623 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8624 return L2_ILT_LINES(bp);
8627 void bnx2x_ilt_set_info(struct bnx2x *bp)
8629 struct ilt_client_info *ilt_client;
8630 struct bnx2x_ilt *ilt = BP_ILT(bp);
8633 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8634 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8637 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8638 ilt_client->client_num = ILT_CLIENT_CDU;
8639 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8640 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8641 ilt_client->start = line;
8642 line += bnx2x_cid_ilt_lines(bp);
8644 if (CNIC_SUPPORT(bp))
8645 line += CNIC_ILT_LINES;
8646 ilt_client->end = line - 1;
8648 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8651 ilt_client->page_size,
8653 ilog2(ilt_client->page_size >> 12));
8656 if (QM_INIT(bp->qm_cid_count)) {
8657 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8658 ilt_client->client_num = ILT_CLIENT_QM;
8659 ilt_client->page_size = QM_ILT_PAGE_SZ;
8660 ilt_client->flags = 0;
8661 ilt_client->start = line;
8663 /* 4 bytes for each cid */
8664 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8667 ilt_client->end = line - 1;
8670 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8673 ilt_client->page_size,
8675 ilog2(ilt_client->page_size >> 12));
8678 if (CNIC_SUPPORT(bp)) {
8680 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8681 ilt_client->client_num = ILT_CLIENT_SRC;
8682 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8683 ilt_client->flags = 0;
8684 ilt_client->start = line;
8685 line += SRC_ILT_LINES;
8686 ilt_client->end = line - 1;
8689 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8692 ilt_client->page_size,
8694 ilog2(ilt_client->page_size >> 12));
8697 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8698 ilt_client->client_num = ILT_CLIENT_TM;
8699 ilt_client->page_size = TM_ILT_PAGE_SZ;
8700 ilt_client->flags = 0;
8701 ilt_client->start = line;
8702 line += TM_ILT_LINES;
8703 ilt_client->end = line - 1;
8706 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8709 ilt_client->page_size,
8711 ilog2(ilt_client->page_size >> 12));
8714 BUG_ON(line > ILT_MAX_LINES);
8718 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8720 * @bp: driver handle
8721 * @fp: pointer to fastpath
8722 * @init_params: pointer to parameters structure
8724 * parameters configured:
8725 * - HC configuration
8726 * - Queue's CDU context
8728 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8729 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8732 int cxt_index, cxt_offset;
8734 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8735 if (!IS_FCOE_FP(fp)) {
8736 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8737 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8739 /* If HC is supported, enable host coalescing in the transition
8742 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8743 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8746 init_params->rx.hc_rate = bp->rx_ticks ?
8747 (1000000 / bp->rx_ticks) : 0;
8748 init_params->tx.hc_rate = bp->tx_ticks ?
8749 (1000000 / bp->tx_ticks) : 0;
8752 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8756 * CQ index among the SB indices: FCoE clients uses the default
8757 * SB, therefore it's different.
8759 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8760 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8763 /* set maximum number of COSs supported by this queue */
8764 init_params->max_cos = fp->max_cos;
8766 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8767 fp->index, init_params->max_cos);
8769 /* set the context pointers queue object */
8770 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8771 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8772 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8774 init_params->cxts[cos] =
8775 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8779 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8780 struct bnx2x_queue_state_params *q_params,
8781 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8782 int tx_index, bool leading)
8784 memset(tx_only_params, 0, sizeof(*tx_only_params));
8786 /* Set the command */
8787 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8789 /* Set tx-only QUEUE flags: don't zero statistics */
8790 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8792 /* choose the index of the cid to send the slow path on */
8793 tx_only_params->cid_index = tx_index;
8795 /* Set general TX_ONLY_SETUP parameters */
8796 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8798 /* Set Tx TX_ONLY_SETUP parameters */
8799 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8802 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8803 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8804 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8805 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8807 /* send the ramrod */
8808 return bnx2x_queue_state_change(bp, q_params);
8812 * bnx2x_setup_queue - setup queue
8814 * @bp: driver handle
8815 * @fp: pointer to fastpath
8816 * @leading: is leading
8818 * This function performs 2 steps in a Queue state machine
8819 * actually: 1) RESET->INIT 2) INIT->SETUP
8822 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8825 struct bnx2x_queue_state_params q_params = {NULL};
8826 struct bnx2x_queue_setup_params *setup_params =
8827 &q_params.params.setup;
8828 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8829 &q_params.params.tx_only;
8833 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8835 /* reset IGU state skip FCoE L2 queue */
8836 if (!IS_FCOE_FP(fp))
8837 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8840 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8841 /* We want to wait for completion in this context */
8842 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8844 /* Prepare the INIT parameters */
8845 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8847 /* Set the command */
8848 q_params.cmd = BNX2X_Q_CMD_INIT;
8850 /* Change the state to INIT */
8851 rc = bnx2x_queue_state_change(bp, &q_params);
8853 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8857 DP(NETIF_MSG_IFUP, "init complete\n");
8859 /* Now move the Queue to the SETUP state... */
8860 memset(setup_params, 0, sizeof(*setup_params));
8862 /* Set QUEUE flags */
8863 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8865 /* Set general SETUP parameters */
8866 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8867 FIRST_TX_COS_INDEX);
8869 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8870 &setup_params->rxq_params);
8872 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8873 FIRST_TX_COS_INDEX);
8875 /* Set the command */
8876 q_params.cmd = BNX2X_Q_CMD_SETUP;
8879 bp->fcoe_init = true;
8881 /* Change the state to SETUP */
8882 rc = bnx2x_queue_state_change(bp, &q_params);
8884 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8888 /* loop through the relevant tx-only indices */
8889 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8890 tx_index < fp->max_cos;
8893 /* prepare and send tx-only ramrod*/
8894 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8895 tx_only_params, tx_index, leading);
8897 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8898 fp->index, tx_index);
8906 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8908 struct bnx2x_fastpath *fp = &bp->fp[index];
8909 struct bnx2x_fp_txdata *txdata;
8910 struct bnx2x_queue_state_params q_params = {NULL};
8913 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8915 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8916 /* We want to wait for completion in this context */
8917 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8919 /* close tx-only connections */
8920 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8921 tx_index < fp->max_cos;
8924 /* ascertain this is a normal queue*/
8925 txdata = fp->txdata_ptr[tx_index];
8927 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8930 /* send halt terminate on tx-only connection */
8931 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8932 memset(&q_params.params.terminate, 0,
8933 sizeof(q_params.params.terminate));
8934 q_params.params.terminate.cid_index = tx_index;
8936 rc = bnx2x_queue_state_change(bp, &q_params);
8940 /* send halt terminate on tx-only connection */
8941 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8942 memset(&q_params.params.cfc_del, 0,
8943 sizeof(q_params.params.cfc_del));
8944 q_params.params.cfc_del.cid_index = tx_index;
8945 rc = bnx2x_queue_state_change(bp, &q_params);
8949 /* Stop the primary connection: */
8950 /* ...halt the connection */
8951 q_params.cmd = BNX2X_Q_CMD_HALT;
8952 rc = bnx2x_queue_state_change(bp, &q_params);
8956 /* ...terminate the connection */
8957 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8958 memset(&q_params.params.terminate, 0,
8959 sizeof(q_params.params.terminate));
8960 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8961 rc = bnx2x_queue_state_change(bp, &q_params);
8964 /* ...delete cfc entry */
8965 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8966 memset(&q_params.params.cfc_del, 0,
8967 sizeof(q_params.params.cfc_del));
8968 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8969 return bnx2x_queue_state_change(bp, &q_params);
8972 static void bnx2x_reset_func(struct bnx2x *bp)
8974 int port = BP_PORT(bp);
8975 int func = BP_FUNC(bp);
8978 /* Disable the function in the FW */
8979 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8980 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8981 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8982 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8985 for_each_eth_queue(bp, i) {
8986 struct bnx2x_fastpath *fp = &bp->fp[i];
8987 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8988 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8992 if (CNIC_LOADED(bp))
8994 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8995 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8996 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8999 REG_WR8(bp, BAR_CSTRORM_INTMEM +
9000 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
9003 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
9004 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
9008 if (bp->common.int_block == INT_BLOCK_HC) {
9009 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
9010 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
9012 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
9013 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
9016 if (CNIC_LOADED(bp)) {
9017 /* Disable Timer scan */
9018 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
9020 * Wait for at least 10ms and up to 2 second for the timers
9023 for (i = 0; i < 200; i++) {
9024 usleep_range(10000, 20000);
9025 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
9030 bnx2x_clear_func_ilt(bp, func);
9032 /* Timers workaround bug for E2: if this is vnic-3,
9033 * we need to set the entire ilt range for this timers.
9035 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
9036 struct ilt_client_info ilt_cli;
9037 /* use dummy TM client */
9038 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9040 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9041 ilt_cli.client_num = ILT_CLIENT_TM;
9043 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9046 /* this assumes that reset_port() called before reset_func()*/
9047 if (!CHIP_IS_E1x(bp))
9048 bnx2x_pf_disable(bp);
9053 static void bnx2x_reset_port(struct bnx2x *bp)
9055 int port = BP_PORT(bp);
9058 /* Reset physical Link */
9059 bnx2x__link_reset(bp);
9061 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9063 /* Do not rcv packets to BRB */
9064 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9065 /* Do not direct rcv packets that are not for MCP to the BRB */
9066 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9067 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9070 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9073 /* Check for BRB port occupancy */
9074 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9076 DP(NETIF_MSG_IFDOWN,
9077 "BRB1 is not empty %d blocks are occupied\n", val);
9079 /* TODO: Close Doorbell port? */
9082 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9084 struct bnx2x_func_state_params func_params = {NULL};
9086 /* Prepare parameters for function state transitions */
9087 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9089 func_params.f_obj = &bp->func_obj;
9090 func_params.cmd = BNX2X_F_CMD_HW_RESET;
9092 func_params.params.hw_init.load_phase = load_code;
9094 return bnx2x_func_state_change(bp, &func_params);
9097 static int bnx2x_func_stop(struct bnx2x *bp)
9099 struct bnx2x_func_state_params func_params = {NULL};
9102 /* Prepare parameters for function state transitions */
9103 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9104 func_params.f_obj = &bp->func_obj;
9105 func_params.cmd = BNX2X_F_CMD_STOP;
9108 * Try to stop the function the 'good way'. If fails (in case
9109 * of a parity error during bnx2x_chip_cleanup()) and we are
9110 * not in a debug mode, perform a state transaction in order to
9111 * enable further HW_RESET transaction.
9113 rc = bnx2x_func_state_change(bp, &func_params);
9115 #ifdef BNX2X_STOP_ON_ERROR
9118 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9119 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9120 return bnx2x_func_state_change(bp, &func_params);
9128 * bnx2x_send_unload_req - request unload mode from the MCP.
9130 * @bp: driver handle
9131 * @unload_mode: requested function's unload mode
9133 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9135 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9138 int port = BP_PORT(bp);
9140 /* Select the UNLOAD request mode */
9141 if (unload_mode == UNLOAD_NORMAL)
9142 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9144 else if (bp->flags & NO_WOL_FLAG)
9145 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9148 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9149 u8 *mac_addr = bp->dev->dev_addr;
9150 struct pci_dev *pdev = bp->pdev;
9154 /* The mac address is written to entries 1-4 to
9155 * preserve entry 0 which is used by the PMF
9157 u8 entry = (BP_VN(bp) + 1)*8;
9159 val = (mac_addr[0] << 8) | mac_addr[1];
9160 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9162 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9163 (mac_addr[4] << 8) | mac_addr[5];
9164 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9166 /* Enable the PME and clear the status */
9167 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9168 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9169 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9171 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9174 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9176 /* Send the request to the MCP */
9178 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9180 int path = BP_PATH(bp);
9182 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9183 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9184 bnx2x_load_count[path][2]);
9185 bnx2x_load_count[path][0]--;
9186 bnx2x_load_count[path][1 + port]--;
9187 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9188 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9189 bnx2x_load_count[path][2]);
9190 if (bnx2x_load_count[path][0] == 0)
9191 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9192 else if (bnx2x_load_count[path][1 + port] == 0)
9193 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9195 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9202 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9204 * @bp: driver handle
9205 * @keep_link: true iff link should be kept up
9207 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9209 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9211 /* Report UNLOAD_DONE to MCP */
9213 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9216 static int bnx2x_func_wait_started(struct bnx2x *bp)
9219 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9225 * (assumption: No Attention from MCP at this stage)
9226 * PMF probably in the middle of TX disable/enable transaction
9227 * 1. Sync IRS for default SB
9228 * 2. Sync SP queue - this guarantees us that attention handling started
9229 * 3. Wait, that TX disable/enable transaction completes
9231 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9232 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9233 * received completion for the transaction the state is TX_STOPPED.
9234 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9238 /* make sure default SB ISR is done */
9240 synchronize_irq(bp->msix_table[0].vector);
9242 synchronize_irq(bp->pdev->irq);
9244 flush_workqueue(bnx2x_wq);
9245 flush_workqueue(bnx2x_iov_wq);
9247 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9248 BNX2X_F_STATE_STARTED && tout--)
9251 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9252 BNX2X_F_STATE_STARTED) {
9253 #ifdef BNX2X_STOP_ON_ERROR
9254 BNX2X_ERR("Wrong function state\n");
9258 * Failed to complete the transaction in a "good way"
9259 * Force both transactions with CLR bit
9261 struct bnx2x_func_state_params func_params = {NULL};
9263 DP(NETIF_MSG_IFDOWN,
9264 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9266 func_params.f_obj = &bp->func_obj;
9267 __set_bit(RAMROD_DRV_CLR_ONLY,
9268 &func_params.ramrod_flags);
9270 /* STARTED-->TX_ST0PPED */
9271 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9272 bnx2x_func_state_change(bp, &func_params);
9274 /* TX_ST0PPED-->STARTED */
9275 func_params.cmd = BNX2X_F_CMD_TX_START;
9276 return bnx2x_func_state_change(bp, &func_params);
9283 static void bnx2x_disable_ptp(struct bnx2x *bp)
9285 int port = BP_PORT(bp);
9287 /* Disable sending PTP packets to host */
9288 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9289 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9291 /* Reset PTP event detection rules */
9292 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9293 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9294 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9295 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9296 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9297 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9298 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9299 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9301 /* Disable the PTP feature */
9302 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9303 NIG_REG_P0_PTP_EN, 0x0);
9306 /* Called during unload, to stop PTP-related stuff */
9307 static void bnx2x_stop_ptp(struct bnx2x *bp)
9309 /* Cancel PTP work queue. Should be done after the Tx queues are
9310 * drained to prevent additional scheduling.
9312 cancel_work_sync(&bp->ptp_task);
9314 if (bp->ptp_tx_skb) {
9315 dev_kfree_skb_any(bp->ptp_tx_skb);
9316 bp->ptp_tx_skb = NULL;
9319 /* Disable PTP in HW */
9320 bnx2x_disable_ptp(bp);
9322 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9325 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9327 int port = BP_PORT(bp);
9330 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9333 /* Wait until tx fastpath tasks complete */
9334 for_each_tx_queue(bp, i) {
9335 struct bnx2x_fastpath *fp = &bp->fp[i];
9337 for_each_cos_in_tx_queue(fp, cos)
9338 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9339 #ifdef BNX2X_STOP_ON_ERROR
9345 /* Give HW time to discard old tx messages */
9346 usleep_range(1000, 2000);
9348 /* Clean all ETH MACs */
9349 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9352 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9354 /* Clean up UC list */
9355 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9358 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9361 /* The whole *vlan_obj structure may be not initialized if VLAN
9362 * filtering offload is not supported by hardware. Currently this is
9363 * true for all hardware covered by CHIP_IS_E1x().
9365 if (!CHIP_IS_E1x(bp)) {
9366 /* Remove all currently configured VLANs */
9367 rc = bnx2x_del_all_vlans(bp);
9369 BNX2X_ERR("Failed to delete all VLANs\n");
9373 if (!CHIP_IS_E1(bp))
9374 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9376 /* Set "drop all" (stop Rx).
9377 * We need to take a netif_addr_lock() here in order to prevent
9378 * a race between the completion code and this code.
9380 netif_addr_lock_bh(bp->dev);
9381 /* Schedule the rx_mode command */
9382 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9383 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9385 bnx2x_set_storm_rx_mode(bp);
9387 /* Cleanup multicast configuration */
9388 rparam.mcast_obj = &bp->mcast_obj;
9389 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9391 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9393 netif_addr_unlock_bh(bp->dev);
9395 bnx2x_iov_chip_cleanup(bp);
9398 * Send the UNLOAD_REQUEST to the MCP. This will return if
9399 * this function should perform FUNC, PORT or COMMON HW
9402 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9405 * (assumption: No Attention from MCP at this stage)
9406 * PMF probably in the middle of TX disable/enable transaction
9408 rc = bnx2x_func_wait_started(bp);
9410 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9411 #ifdef BNX2X_STOP_ON_ERROR
9416 /* Close multi and leading connections
9417 * Completions for ramrods are collected in a synchronous way
9419 for_each_eth_queue(bp, i)
9420 if (bnx2x_stop_queue(bp, i))
9421 #ifdef BNX2X_STOP_ON_ERROR
9427 if (CNIC_LOADED(bp)) {
9428 for_each_cnic_queue(bp, i)
9429 if (bnx2x_stop_queue(bp, i))
9430 #ifdef BNX2X_STOP_ON_ERROR
9437 /* If SP settings didn't get completed so far - something
9438 * very wrong has happen.
9440 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9441 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9443 #ifndef BNX2X_STOP_ON_ERROR
9446 rc = bnx2x_func_stop(bp);
9448 BNX2X_ERR("Function stop failed!\n");
9449 #ifdef BNX2X_STOP_ON_ERROR
9454 /* stop_ptp should be after the Tx queues are drained to prevent
9455 * scheduling to the cancelled PTP work queue. It should also be after
9456 * function stop ramrod is sent, since as part of this ramrod FW access
9459 if (bp->flags & PTP_SUPPORTED)
9462 /* Disable HW interrupts, NAPI */
9463 bnx2x_netif_stop(bp, 1);
9464 /* Delete all NAPI objects */
9465 bnx2x_del_all_napi(bp);
9466 if (CNIC_LOADED(bp))
9467 bnx2x_del_all_napi_cnic(bp);
9472 /* Reset the chip, unless PCI function is offline. If we reach this
9473 * point following a PCI error handling, it means device is really
9474 * in a bad state and we're about to remove it, so reset the chip
9475 * is not a good idea.
9477 if (!pci_channel_offline(bp->pdev)) {
9478 rc = bnx2x_reset_hw(bp, reset_code);
9480 BNX2X_ERR("HW_RESET failed\n");
9483 /* Report UNLOAD_DONE to MCP */
9484 bnx2x_send_unload_done(bp, keep_link);
9487 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9491 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9493 if (CHIP_IS_E1(bp)) {
9494 int port = BP_PORT(bp);
9495 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9496 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9498 val = REG_RD(bp, addr);
9500 REG_WR(bp, addr, val);
9502 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9503 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9504 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9505 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9509 /* Close gates #2, #3 and #4: */
9510 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9514 /* Gates #2 and #4a are closed/opened for "not E1" only */
9515 if (!CHIP_IS_E1(bp)) {
9517 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9519 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9523 if (CHIP_IS_E1x(bp)) {
9524 /* Prevent interrupts from HC on both ports */
9525 val = REG_RD(bp, HC_REG_CONFIG_1);
9526 REG_WR(bp, HC_REG_CONFIG_1,
9527 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9528 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9530 val = REG_RD(bp, HC_REG_CONFIG_0);
9531 REG_WR(bp, HC_REG_CONFIG_0,
9532 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9533 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9535 /* Prevent incoming interrupts in IGU */
9536 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9538 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9540 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9541 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9544 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9545 close ? "closing" : "opening");
9549 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9551 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9553 /* Do some magic... */
9554 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9555 *magic_val = val & SHARED_MF_CLP_MAGIC;
9556 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9560 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9562 * @bp: driver handle
9563 * @magic_val: old value of the `magic' bit.
9565 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9567 /* Restore the `magic' bit value... */
9568 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9569 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9570 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9574 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9576 * @bp: driver handle
9577 * @magic_val: old value of 'magic' bit.
9579 * Takes care of CLP configurations.
9581 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9584 u32 validity_offset;
9586 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9588 /* Set `magic' bit in order to save MF config */
9589 if (!CHIP_IS_E1(bp))
9590 bnx2x_clp_reset_prep(bp, magic_val);
9592 /* Get shmem offset */
9593 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9595 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9597 /* Clear validity map flags */
9599 REG_WR(bp, shmem + validity_offset, 0);
9602 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9603 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9606 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9608 * @bp: driver handle
9610 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9612 /* special handling for emulation and FPGA,
9613 wait 10 times longer */
9614 if (CHIP_REV_IS_SLOW(bp))
9615 msleep(MCP_ONE_TIMEOUT*10);
9617 msleep(MCP_ONE_TIMEOUT);
9621 * initializes bp->common.shmem_base and waits for validity signature to appear
9623 static int bnx2x_init_shmem(struct bnx2x *bp)
9629 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9631 /* If we read all 0xFFs, means we are in PCI error state and
9632 * should bail out to avoid crashes on adapter's FW reads.
9634 if (bp->common.shmem_base == 0xFFFFFFFF) {
9635 bp->flags |= NO_MCP_FLAG;
9639 if (bp->common.shmem_base) {
9640 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9641 if (val & SHR_MEM_VALIDITY_MB)
9645 bnx2x_mcp_wait_one(bp);
9647 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9649 BNX2X_ERR("BAD MCP validity signature\n");
9654 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9656 int rc = bnx2x_init_shmem(bp);
9658 /* Restore the `magic' bit value */
9659 if (!CHIP_IS_E1(bp))
9660 bnx2x_clp_reset_done(bp, magic_val);
9665 static void bnx2x_pxp_prep(struct bnx2x *bp)
9667 if (!CHIP_IS_E1(bp)) {
9668 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9669 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9675 * Reset the whole chip except for:
9677 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9680 * - MISC (including AEU)
9684 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9686 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9687 u32 global_bits2, stay_reset2;
9690 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9691 * (per chip) blocks.
9694 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9695 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9697 /* Don't reset the following blocks.
9698 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9699 * reset, as in 4 port device they might still be owned
9700 * by the MCP (there is only one leader per path).
9703 MISC_REGISTERS_RESET_REG_1_RST_HC |
9704 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9705 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9708 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9709 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9710 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9711 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9712 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9713 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9714 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9715 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9716 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9717 MISC_REGISTERS_RESET_REG_2_PGLC |
9718 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9719 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9720 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9721 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9722 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9723 MISC_REGISTERS_RESET_REG_2_UMAC1;
9726 * Keep the following blocks in reset:
9727 * - all xxMACs are handled by the bnx2x_link code.
9730 MISC_REGISTERS_RESET_REG_2_XMAC |
9731 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9733 /* Full reset masks according to the chip */
9734 reset_mask1 = 0xffffffff;
9737 reset_mask2 = 0xffff;
9738 else if (CHIP_IS_E1H(bp))
9739 reset_mask2 = 0x1ffff;
9740 else if (CHIP_IS_E2(bp))
9741 reset_mask2 = 0xfffff;
9742 else /* CHIP_IS_E3 */
9743 reset_mask2 = 0x3ffffff;
9745 /* Don't reset global blocks unless we need to */
9747 reset_mask2 &= ~global_bits2;
9750 * In case of attention in the QM, we need to reset PXP
9751 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9752 * because otherwise QM reset would release 'close the gates' shortly
9753 * before resetting the PXP, then the PSWRQ would send a write
9754 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9755 * read the payload data from PSWWR, but PSWWR would not
9756 * respond. The write queue in PGLUE would stuck, dmae commands
9757 * would not return. Therefore it's important to reset the second
9758 * reset register (containing the
9759 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9760 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9763 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9764 reset_mask2 & (~not_reset_mask2));
9766 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9767 reset_mask1 & (~not_reset_mask1));
9772 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9773 reset_mask2 & (~stay_reset2));
9778 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9783 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9784 * It should get cleared in no more than 1s.
9786 * @bp: driver handle
9788 * It should get cleared in no more than 1s. Returns 0 if
9789 * pending writes bit gets cleared.
9791 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9797 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9802 usleep_range(1000, 2000);
9803 } while (cnt-- > 0);
9806 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9814 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9818 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9821 /* Empty the Tetris buffer, wait for 1s */
9823 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9824 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9825 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9826 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9827 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9829 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9831 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9832 ((port_is_idle_0 & 0x1) == 0x1) &&
9833 ((port_is_idle_1 & 0x1) == 0x1) &&
9834 (pgl_exp_rom2 == 0xffffffff) &&
9835 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9837 usleep_range(1000, 2000);
9838 } while (cnt-- > 0);
9841 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9842 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9843 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9850 /* Close gates #2, #3 and #4 */
9851 bnx2x_set_234_gates(bp, true);
9853 /* Poll for IGU VQs for 57712 and newer chips */
9854 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9857 /* TBD: Indicate that "process kill" is in progress to MCP */
9859 /* Clear "unprepared" bit */
9860 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9863 /* Make sure all is written to the chip before the reset */
9866 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9867 * PSWHST, GRC and PSWRD Tetris buffer.
9869 usleep_range(1000, 2000);
9871 /* Prepare to chip reset: */
9874 bnx2x_reset_mcp_prep(bp, &val);
9880 /* reset the chip */
9881 bnx2x_process_kill_chip_reset(bp, global);
9884 /* clear errors in PGB */
9885 if (!CHIP_IS_E1x(bp))
9886 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9888 /* Recover after reset: */
9890 if (global && bnx2x_reset_mcp_comp(bp, val))
9893 /* TBD: Add resetting the NO_MCP mode DB here */
9895 /* Open the gates #2, #3 and #4 */
9896 bnx2x_set_234_gates(bp, false);
9898 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9899 * reset state, re-enable attentions. */
9904 static int bnx2x_leader_reset(struct bnx2x *bp)
9907 bool global = bnx2x_reset_is_global(bp);
9910 /* if not going to reset MCP - load "fake" driver to reset HW while
9911 * driver is owner of the HW
9913 if (!global && !BP_NOMCP(bp)) {
9914 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9915 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9917 BNX2X_ERR("MCP response failure, aborting\n");
9919 goto exit_leader_reset;
9921 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9922 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9923 BNX2X_ERR("MCP unexpected resp, aborting\n");
9925 goto exit_leader_reset2;
9927 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9929 BNX2X_ERR("MCP response failure, aborting\n");
9931 goto exit_leader_reset2;
9935 /* Try to recover after the failure */
9936 if (bnx2x_process_kill(bp, global)) {
9937 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9940 goto exit_leader_reset2;
9944 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9947 bnx2x_set_reset_done(bp);
9949 bnx2x_clear_reset_global(bp);
9952 /* unload "fake driver" if it was loaded */
9953 if (!global && !BP_NOMCP(bp)) {
9954 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9955 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9959 bnx2x_release_leader_lock(bp);
9964 static void bnx2x_recovery_failed(struct bnx2x *bp)
9966 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9968 /* Disconnect this device */
9969 netif_device_detach(bp->dev);
9972 * Block ifup for all function on this engine until "process kill"
9975 bnx2x_set_reset_in_progress(bp);
9977 /* Shut down the power */
9978 bnx2x_set_power_state(bp, PCI_D3hot);
9980 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9986 * Assumption: runs under rtnl lock. This together with the fact
9987 * that it's called only from bnx2x_sp_rtnl() ensure that it
9988 * will never be called when netif_running(bp->dev) is false.
9990 static void bnx2x_parity_recover(struct bnx2x *bp)
9992 u32 error_recovered, error_unrecovered;
9993 bool is_parity, global = false;
9994 #ifdef CONFIG_BNX2X_SRIOV
9997 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) {
9998 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
10001 vf->state = VF_LOST;
10004 DP(NETIF_MSG_HW, "Handling parity\n");
10006 switch (bp->recovery_state) {
10007 case BNX2X_RECOVERY_INIT:
10008 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
10009 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
10010 WARN_ON(!is_parity);
10012 /* Try to get a LEADER_LOCK HW lock */
10013 if (bnx2x_trylock_leader_lock(bp)) {
10014 bnx2x_set_reset_in_progress(bp);
10016 * Check if there is a global attention and if
10017 * there was a global attention, set the global
10022 bnx2x_set_reset_global(bp);
10027 /* Stop the driver */
10028 /* If interface has been removed - break */
10029 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
10032 bp->recovery_state = BNX2X_RECOVERY_WAIT;
10034 /* Ensure "is_leader", MCP command sequence and
10035 * "recovery_state" update values are seen on other
10041 case BNX2X_RECOVERY_WAIT:
10042 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
10043 if (bp->is_leader) {
10044 int other_engine = BP_PATH(bp) ? 0 : 1;
10045 bool other_load_status =
10046 bnx2x_get_load_status(bp, other_engine);
10048 bnx2x_get_load_status(bp, BP_PATH(bp));
10049 global = bnx2x_reset_is_global(bp);
10052 * In case of a parity in a global block, let
10053 * the first leader that performs a
10054 * leader_reset() reset the global blocks in
10055 * order to clear global attentions. Otherwise
10056 * the gates will remain closed for that
10060 (global && other_load_status)) {
10061 /* Wait until all other functions get
10064 schedule_delayed_work(&bp->sp_rtnl_task,
10068 /* If all other functions got down -
10069 * try to bring the chip back to
10070 * normal. In any case it's an exit
10071 * point for a leader.
10073 if (bnx2x_leader_reset(bp)) {
10074 bnx2x_recovery_failed(bp);
10078 /* If we are here, means that the
10079 * leader has succeeded and doesn't
10080 * want to be a leader any more. Try
10081 * to continue as a none-leader.
10085 } else { /* non-leader */
10086 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10087 /* Try to get a LEADER_LOCK HW lock as
10088 * long as a former leader may have
10089 * been unloaded by the user or
10090 * released a leadership by another
10093 if (bnx2x_trylock_leader_lock(bp)) {
10094 /* I'm a leader now! Restart a
10101 schedule_delayed_work(&bp->sp_rtnl_task,
10107 * If there was a global attention, wait
10108 * for it to be cleared.
10110 if (bnx2x_reset_is_global(bp)) {
10111 schedule_delayed_work(
10118 bp->eth_stats.recoverable_error;
10119 error_unrecovered =
10120 bp->eth_stats.unrecoverable_error;
10121 bp->recovery_state =
10122 BNX2X_RECOVERY_NIC_LOADING;
10123 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10124 error_unrecovered++;
10125 netdev_err(bp->dev,
10126 "Recovery failed. Power cycle needed\n");
10127 /* Disconnect this device */
10128 netif_device_detach(bp->dev);
10129 /* Shut down the power */
10130 bnx2x_set_power_state(
10134 bp->recovery_state =
10135 BNX2X_RECOVERY_DONE;
10139 bp->eth_stats.recoverable_error =
10141 bp->eth_stats.unrecoverable_error =
10153 static int bnx2x_udp_port_update(struct bnx2x *bp)
10155 struct bnx2x_func_switch_update_params *switch_update_params;
10156 struct bnx2x_func_state_params func_params = {NULL};
10157 struct bnx2x_udp_tunnel *udp_tunnel;
10158 u16 vxlan_port = 0, geneve_port = 0;
10161 switch_update_params = &func_params.params.switch_update;
10163 /* Prepare parameters for function state transitions */
10164 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10165 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10167 func_params.f_obj = &bp->func_obj;
10168 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10170 /* Function parameters */
10171 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10172 &switch_update_params->changes);
10174 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10175 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10176 geneve_port = udp_tunnel->dst_port;
10177 switch_update_params->geneve_dst_port = geneve_port;
10180 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10181 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10182 vxlan_port = udp_tunnel->dst_port;
10183 switch_update_params->vxlan_dst_port = vxlan_port;
10186 /* Re-enable inner-rss for the offloaded UDP tunnels */
10187 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10188 &switch_update_params->changes);
10190 rc = bnx2x_func_state_change(bp, &func_params);
10192 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10193 vxlan_port, geneve_port, rc);
10196 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10197 vxlan_port, geneve_port);
10202 static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10203 enum bnx2x_udp_port_type type)
10205 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10207 if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
10210 if (udp_port->count && udp_port->dst_port == port) {
10215 if (udp_port->count) {
10217 "UDP tunnel [%d] - destination port limit reached\n",
10222 udp_port->dst_port = port;
10223 udp_port->count = 1;
10224 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10227 static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10228 enum bnx2x_udp_port_type type)
10230 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10232 if (!IS_PF(bp) || CHIP_IS_E1x(bp))
10235 if (!udp_port->count || udp_port->dst_port != port) {
10236 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10241 /* Remove reference, and make certain it's no longer in use */
10243 if (udp_port->count)
10245 udp_port->dst_port = 0;
10247 if (netif_running(bp->dev))
10248 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10250 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10254 static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10255 struct udp_tunnel_info *ti)
10257 struct bnx2x *bp = netdev_priv(netdev);
10258 u16 t_port = ntohs(ti->port);
10260 switch (ti->type) {
10261 case UDP_TUNNEL_TYPE_VXLAN:
10262 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10264 case UDP_TUNNEL_TYPE_GENEVE:
10265 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10272 static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10273 struct udp_tunnel_info *ti)
10275 struct bnx2x *bp = netdev_priv(netdev);
10276 u16 t_port = ntohs(ti->port);
10278 switch (ti->type) {
10279 case UDP_TUNNEL_TYPE_VXLAN:
10280 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10282 case UDP_TUNNEL_TYPE_GENEVE:
10283 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10290 static int bnx2x_close(struct net_device *dev);
10292 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10293 * scheduled on a general queue in order to prevent a dead lock.
10295 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10297 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10301 if (!netif_running(bp->dev)) {
10306 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10307 #ifdef BNX2X_STOP_ON_ERROR
10308 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10309 "you will need to reboot when done\n");
10310 goto sp_rtnl_not_reset;
10313 * Clear all pending SP commands as we are going to reset the
10316 bp->sp_rtnl_state = 0;
10319 bnx2x_parity_recover(bp);
10325 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10326 #ifdef BNX2X_STOP_ON_ERROR
10327 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10328 "you will need to reboot when done\n");
10329 goto sp_rtnl_not_reset;
10333 * Clear all pending SP commands as we are going to reset the
10336 bp->sp_rtnl_state = 0;
10339 /* Immediately indicate link as down */
10340 bp->link_vars.link_up = 0;
10341 bp->force_link_down = true;
10342 netif_carrier_off(bp->dev);
10343 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10345 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10346 bnx2x_nic_load(bp, LOAD_NORMAL);
10351 #ifdef BNX2X_STOP_ON_ERROR
10354 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10355 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10356 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10357 bnx2x_after_function_update(bp);
10359 * in case of fan failure we need to reset id if the "stop on error"
10360 * debug flag is set, since we trying to prevent permanent overheating
10363 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10364 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10365 netif_device_detach(bp->dev);
10366 bnx2x_close(bp->dev);
10371 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10373 "sending set mcast vf pf channel message from rtnl sp-task\n");
10374 bnx2x_vfpf_set_mcast(bp->dev);
10376 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10377 &bp->sp_rtnl_state)){
10378 if (netif_carrier_ok(bp->dev)) {
10379 bnx2x_tx_disable(bp);
10380 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10384 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10385 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10386 bnx2x_set_rx_mode_inner(bp);
10389 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10390 &bp->sp_rtnl_state))
10391 bnx2x_pf_set_vfs_vlan(bp);
10393 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10394 bnx2x_dcbx_stop_hw_tx(bp);
10395 bnx2x_dcbx_resume_hw_tx(bp);
10398 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10399 &bp->sp_rtnl_state))
10400 bnx2x_update_mng_version(bp);
10402 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state))
10403 bnx2x_handle_update_svid_cmd(bp);
10405 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
10406 &bp->sp_rtnl_state)) {
10407 if (bnx2x_udp_port_update(bp)) {
10408 /* On error, forget configuration */
10409 memset(bp->udp_tunnel_ports, 0,
10410 sizeof(struct bnx2x_udp_tunnel) *
10411 BNX2X_UDP_PORT_MAX);
10413 /* Since we don't store additional port information,
10414 * if no ports are configured for any feature ask for
10415 * information about currently configured ports.
10417 if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10418 !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10419 udp_tunnel_get_rx_info(bp->dev);
10423 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10424 * can be called from other contexts as well)
10428 /* enable SR-IOV if applicable */
10429 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10430 &bp->sp_rtnl_state)) {
10431 bnx2x_disable_sriov(bp);
10432 bnx2x_enable_sriov(bp);
10436 static void bnx2x_period_task(struct work_struct *work)
10438 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10440 if (!netif_running(bp->dev))
10441 goto period_task_exit;
10443 if (CHIP_REV_IS_SLOW(bp)) {
10444 BNX2X_ERR("period task called on emulation, ignoring\n");
10445 goto period_task_exit;
10448 bnx2x_acquire_phy_lock(bp);
10450 * The barrier is needed to ensure the ordering between the writing to
10451 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10452 * the reading here.
10455 if (bp->port.pmf) {
10456 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10458 /* Re-queue task in 1 sec */
10459 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10462 bnx2x_release_phy_lock(bp);
10468 * Init service functions
10471 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10473 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10474 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10475 return base + (BP_ABS_FUNC(bp)) * stride;
10478 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10479 u8 port, u32 reset_reg,
10480 struct bnx2x_mac_vals *vals)
10482 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10485 if (!(mask & reset_reg))
10488 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10489 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10490 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10491 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10492 REG_WR(bp, vals->umac_addr[port], 0);
10497 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10498 struct bnx2x_mac_vals *vals)
10500 u32 val, base_addr, offset, mask, reset_reg;
10501 bool mac_stopped = false;
10502 u8 port = BP_PORT(bp);
10504 /* reset addresses as they also mark which values were changed */
10505 memset(vals, 0, sizeof(*vals));
10507 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10509 if (!CHIP_IS_E3(bp)) {
10510 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10511 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10512 if ((mask & reset_reg) && val) {
10514 BNX2X_DEV_INFO("Disable bmac Rx\n");
10515 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10516 : NIG_REG_INGRESS_BMAC0_MEM;
10517 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10518 : BIGMAC_REGISTER_BMAC_CONTROL;
10521 * use rd/wr since we cannot use dmae. This is safe
10522 * since MCP won't access the bus due to the request
10523 * to unload, and no function on the path can be
10524 * loaded at this time.
10526 wb_data[0] = REG_RD(bp, base_addr + offset);
10527 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10528 vals->bmac_addr = base_addr + offset;
10529 vals->bmac_val[0] = wb_data[0];
10530 vals->bmac_val[1] = wb_data[1];
10531 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10532 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10533 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10535 BNX2X_DEV_INFO("Disable emac Rx\n");
10536 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10537 vals->emac_val = REG_RD(bp, vals->emac_addr);
10538 REG_WR(bp, vals->emac_addr, 0);
10539 mac_stopped = true;
10541 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10542 BNX2X_DEV_INFO("Disable xmac Rx\n");
10543 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10544 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10545 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10547 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10549 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10550 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10551 REG_WR(bp, vals->xmac_addr, 0);
10552 mac_stopped = true;
10555 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10557 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10565 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10566 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10567 0x1848 + ((f) << 4))
10568 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10569 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10570 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10572 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10573 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10574 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10576 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10578 /* UNDI marks its presence in DORQ -
10579 * it initializes CID offset for normal bell to 0x7
10581 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10582 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10585 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10586 BNX2X_DEV_INFO("UNDI previously loaded\n");
10593 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10598 if (BP_FUNC(bp) < 2)
10599 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10601 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10603 tmp_reg = REG_RD(bp, addr);
10604 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10605 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10607 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10608 REG_WR(bp, addr, tmp_reg);
10610 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10611 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10614 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10616 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10617 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10619 BNX2X_ERR("MCP response failure, aborting\n");
10626 static struct bnx2x_prev_path_list *
10627 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10629 struct bnx2x_prev_path_list *tmp_list;
10631 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10632 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10633 bp->pdev->bus->number == tmp_list->bus &&
10634 BP_PATH(bp) == tmp_list->path)
10640 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10642 struct bnx2x_prev_path_list *tmp_list;
10645 rc = down_interruptible(&bnx2x_prev_sem);
10647 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10651 tmp_list = bnx2x_prev_path_get_entry(bp);
10656 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10660 up(&bnx2x_prev_sem);
10665 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10667 struct bnx2x_prev_path_list *tmp_list;
10670 if (down_trylock(&bnx2x_prev_sem))
10673 tmp_list = bnx2x_prev_path_get_entry(bp);
10675 if (tmp_list->aer) {
10676 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10680 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10685 up(&bnx2x_prev_sem);
10690 bool bnx2x_port_after_undi(struct bnx2x *bp)
10692 struct bnx2x_prev_path_list *entry;
10695 down(&bnx2x_prev_sem);
10697 entry = bnx2x_prev_path_get_entry(bp);
10698 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10700 up(&bnx2x_prev_sem);
10705 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10707 struct bnx2x_prev_path_list *tmp_list;
10710 rc = down_interruptible(&bnx2x_prev_sem);
10712 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10716 /* Check whether the entry for this path already exists */
10717 tmp_list = bnx2x_prev_path_get_entry(bp);
10719 if (!tmp_list->aer) {
10720 BNX2X_ERR("Re-Marking the path.\n");
10722 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10726 up(&bnx2x_prev_sem);
10729 up(&bnx2x_prev_sem);
10731 /* Create an entry for this path and add it */
10732 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10734 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10738 tmp_list->bus = bp->pdev->bus->number;
10739 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10740 tmp_list->path = BP_PATH(bp);
10742 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10744 rc = down_interruptible(&bnx2x_prev_sem);
10746 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10749 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10751 list_add(&tmp_list->list, &bnx2x_prev_list);
10752 up(&bnx2x_prev_sem);
10758 static int bnx2x_do_flr(struct bnx2x *bp)
10760 struct pci_dev *dev = bp->pdev;
10762 if (CHIP_IS_E1x(bp)) {
10763 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10767 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10768 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10769 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10770 bp->common.bc_ver);
10774 if (!pci_wait_for_pending_transaction(dev))
10775 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10777 BNX2X_DEV_INFO("Initiating FLR\n");
10778 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10783 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10787 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10789 /* Test if previous unload process was already finished for this path */
10790 if (bnx2x_prev_is_path_marked(bp))
10791 return bnx2x_prev_mcp_done(bp);
10793 BNX2X_DEV_INFO("Path is unmarked\n");
10795 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10796 if (bnx2x_prev_is_after_undi(bp))
10799 /* If function has FLR capabilities, and existing FW version matches
10800 * the one required, then FLR will be sufficient to clean any residue
10801 * left by previous driver
10803 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10806 /* fw version is good */
10807 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10808 rc = bnx2x_do_flr(bp);
10812 /* FLR was performed */
10813 BNX2X_DEV_INFO("FLR successful\n");
10817 BNX2X_DEV_INFO("Could not FLR\n");
10820 /* Close the MCP request, return failure*/
10821 rc = bnx2x_prev_mcp_done(bp);
10823 rc = BNX2X_PREV_WAIT_NEEDED;
10828 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10830 u32 reset_reg, tmp_reg = 0, rc;
10831 bool prev_undi = false;
10832 struct bnx2x_mac_vals mac_vals;
10834 /* It is possible a previous function received 'common' answer,
10835 * but hasn't loaded yet, therefore creating a scenario of
10836 * multiple functions receiving 'common' on the same path.
10838 BNX2X_DEV_INFO("Common unload Flow\n");
10840 memset(&mac_vals, 0, sizeof(mac_vals));
10842 if (bnx2x_prev_is_path_marked(bp))
10843 return bnx2x_prev_mcp_done(bp);
10845 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10847 /* Reset should be performed after BRB is emptied */
10848 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10849 u32 timer_count = 1000;
10851 /* Close the MAC Rx to prevent BRB from filling up */
10852 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10854 /* close LLH filters for both ports towards the BRB */
10855 bnx2x_set_rx_filter(&bp->link_params, 0);
10856 bp->link_params.port ^= 1;
10857 bnx2x_set_rx_filter(&bp->link_params, 0);
10858 bp->link_params.port ^= 1;
10860 /* Check if the UNDI driver was previously loaded */
10861 if (bnx2x_prev_is_after_undi(bp)) {
10863 /* clear the UNDI indication */
10864 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10865 /* clear possible idle check errors */
10866 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10868 if (!CHIP_IS_E1x(bp))
10869 /* block FW from writing to host */
10870 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10872 /* wait until BRB is empty */
10873 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10874 while (timer_count) {
10875 u32 prev_brb = tmp_reg;
10877 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10881 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10883 /* reset timer as long as BRB actually gets emptied */
10884 if (prev_brb > tmp_reg)
10885 timer_count = 1000;
10889 /* If UNDI resides in memory, manually increment it */
10891 bnx2x_prev_unload_undi_inc(bp, 1);
10897 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10900 /* No packets are in the pipeline, path is ready for reset */
10901 bnx2x_reset_common(bp);
10903 if (mac_vals.xmac_addr)
10904 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10905 if (mac_vals.umac_addr[0])
10906 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10907 if (mac_vals.umac_addr[1])
10908 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10909 if (mac_vals.emac_addr)
10910 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10911 if (mac_vals.bmac_addr) {
10912 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10913 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10916 rc = bnx2x_prev_mark_path(bp, prev_undi);
10918 bnx2x_prev_mcp_done(bp);
10922 return bnx2x_prev_mcp_done(bp);
10925 static int bnx2x_prev_unload(struct bnx2x *bp)
10927 int time_counter = 10;
10928 u32 rc, fw, hw_lock_reg, hw_lock_val;
10929 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10931 /* clear hw from errors which may have resulted from an interrupted
10932 * dmae transaction.
10934 bnx2x_clean_pglue_errors(bp);
10936 /* Release previously held locks */
10937 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10938 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10939 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10941 hw_lock_val = REG_RD(bp, hw_lock_reg);
10943 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10944 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10945 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10946 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10949 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10950 REG_WR(bp, hw_lock_reg, 0xffffffff);
10952 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10954 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10955 BNX2X_DEV_INFO("Release previously held alr\n");
10956 bnx2x_release_alr(bp);
10961 /* Lock MCP using an unload request */
10962 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10964 BNX2X_ERR("MCP response failure, aborting\n");
10969 rc = down_interruptible(&bnx2x_prev_sem);
10971 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10974 /* If Path is marked by EEH, ignore unload status */
10975 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10976 bnx2x_prev_path_get_entry(bp)->aer);
10977 up(&bnx2x_prev_sem);
10980 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10981 rc = bnx2x_prev_unload_common(bp);
10985 /* non-common reply from MCP might require looping */
10986 rc = bnx2x_prev_unload_uncommon(bp);
10987 if (rc != BNX2X_PREV_WAIT_NEEDED)
10991 } while (--time_counter);
10993 if (!time_counter || rc) {
10994 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10995 rc = -EPROBE_DEFER;
10998 /* Mark function if its port was used to boot from SAN */
10999 if (bnx2x_port_after_undi(bp))
11000 bp->link_params.feature_config_flags |=
11001 FEATURE_CONFIG_BOOT_FROM_SAN;
11003 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
11008 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
11010 u32 val, val2, val3, val4, id, boot_mode;
11013 /* Get the chip revision id and number. */
11014 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
11015 val = REG_RD(bp, MISC_REG_CHIP_NUM);
11016 id = ((val & 0xffff) << 16);
11017 val = REG_RD(bp, MISC_REG_CHIP_REV);
11018 id |= ((val & 0xf) << 12);
11020 /* Metal is read from PCI regs, but we can't access >=0x400 from
11021 * the configuration space (so we need to reg_rd)
11023 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
11024 id |= (((val >> 24) & 0xf) << 4);
11025 val = REG_RD(bp, MISC_REG_BOND_ID);
11027 bp->common.chip_id = id;
11029 /* force 57811 according to MISC register */
11030 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
11031 if (CHIP_IS_57810(bp))
11032 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
11033 (bp->common.chip_id & 0x0000FFFF);
11034 else if (CHIP_IS_57810_MF(bp))
11035 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
11036 (bp->common.chip_id & 0x0000FFFF);
11037 bp->common.chip_id |= 0x1;
11040 /* Set doorbell size */
11041 bp->db_size = (1 << BNX2X_DB_SHIFT);
11043 if (!CHIP_IS_E1x(bp)) {
11044 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
11045 if ((val & 1) == 0)
11046 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
11048 val = (val >> 1) & 1;
11049 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
11051 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
11054 if (CHIP_MODE_IS_4_PORT(bp))
11055 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
11057 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
11059 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
11060 bp->pfid = bp->pf_num; /* 0..7 */
11063 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
11065 bp->link_params.chip_id = bp->common.chip_id;
11066 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
11068 val = (REG_RD(bp, 0x2874) & 0x55);
11069 if ((bp->common.chip_id & 0x1) ||
11070 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
11071 bp->flags |= ONE_PORT_FLAG;
11072 BNX2X_DEV_INFO("single port device\n");
11075 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
11076 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
11077 (val & MCPR_NVM_CFG4_FLASH_SIZE));
11078 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11079 bp->common.flash_size, bp->common.flash_size);
11081 bnx2x_init_shmem(bp);
11083 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11084 MISC_REG_GENERIC_CR_1 :
11085 MISC_REG_GENERIC_CR_0));
11087 bp->link_params.shmem_base = bp->common.shmem_base;
11088 bp->link_params.shmem2_base = bp->common.shmem2_base;
11089 if (SHMEM2_RD(bp, size) >
11090 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11091 bp->link_params.lfa_base =
11092 REG_RD(bp, bp->common.shmem2_base +
11093 (u32)offsetof(struct shmem2_region,
11094 lfa_host_addr[BP_PORT(bp)]));
11096 bp->link_params.lfa_base = 0;
11097 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11098 bp->common.shmem_base, bp->common.shmem2_base);
11100 if (!bp->common.shmem_base) {
11101 BNX2X_DEV_INFO("MCP not active\n");
11102 bp->flags |= NO_MCP_FLAG;
11106 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11107 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11109 bp->link_params.hw_led_mode = ((bp->common.hw_config &
11110 SHARED_HW_CFG_LED_MODE_MASK) >>
11111 SHARED_HW_CFG_LED_MODE_SHIFT);
11113 bp->link_params.feature_config_flags = 0;
11114 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11115 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11116 bp->link_params.feature_config_flags |=
11117 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11119 bp->link_params.feature_config_flags &=
11120 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11122 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11123 bp->common.bc_ver = val;
11124 BNX2X_DEV_INFO("bc_ver %X\n", val);
11125 if (val < BNX2X_BC_VER) {
11126 /* for now only warn
11127 * later we might need to enforce this */
11128 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11129 BNX2X_BC_VER, val);
11131 bp->link_params.feature_config_flags |=
11132 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11133 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11135 bp->link_params.feature_config_flags |=
11136 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11137 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11138 bp->link_params.feature_config_flags |=
11139 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11140 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11141 bp->link_params.feature_config_flags |=
11142 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11143 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11145 bp->link_params.feature_config_flags |=
11146 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11147 FEATURE_CONFIG_MT_SUPPORT : 0;
11149 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11150 BC_SUPPORTS_PFC_STATS : 0;
11152 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11153 BC_SUPPORTS_FCOE_FEATURES : 0;
11155 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11156 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11158 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11159 BC_SUPPORTS_RMMOD_CMD : 0;
11161 boot_mode = SHMEM_RD(bp,
11162 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11163 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11164 switch (boot_mode) {
11165 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11166 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11168 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11169 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11171 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11172 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11174 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11175 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11179 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11180 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11182 BNX2X_DEV_INFO("%sWoL capable\n",
11183 (bp->flags & NO_WOL_FLAG) ? "not " : "");
11185 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11186 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11187 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11188 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11190 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11191 val, val2, val3, val4);
11194 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11195 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11197 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11199 int pfid = BP_FUNC(bp);
11202 u8 fid, igu_sb_cnt = 0;
11204 bp->igu_base_sb = 0xff;
11205 if (CHIP_INT_MODE_IS_BC(bp)) {
11206 int vn = BP_VN(bp);
11207 igu_sb_cnt = bp->igu_sb_cnt;
11208 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11211 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11212 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11217 /* IGU in normal mode - read CAM */
11218 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11220 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11221 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11223 fid = IGU_FID(val);
11224 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11225 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11227 if (IGU_VEC(val) == 0)
11228 /* default status block */
11229 bp->igu_dsb_id = igu_sb_id;
11231 if (bp->igu_base_sb == 0xff)
11232 bp->igu_base_sb = igu_sb_id;
11238 #ifdef CONFIG_PCI_MSI
11239 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11240 * optional that number of CAM entries will not be equal to the value
11241 * advertised in PCI.
11242 * Driver should use the minimal value of both as the actual status
11245 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11248 if (igu_sb_cnt == 0) {
11249 BNX2X_ERR("CAM configuration error\n");
11256 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11258 int cfg_size = 0, idx, port = BP_PORT(bp);
11260 /* Aggregation of supported attributes of all external phys */
11261 bp->port.supported[0] = 0;
11262 bp->port.supported[1] = 0;
11263 switch (bp->link_params.num_phys) {
11265 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11269 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11273 if (bp->link_params.multi_phy_config &
11274 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11275 bp->port.supported[1] =
11276 bp->link_params.phy[EXT_PHY1].supported;
11277 bp->port.supported[0] =
11278 bp->link_params.phy[EXT_PHY2].supported;
11280 bp->port.supported[0] =
11281 bp->link_params.phy[EXT_PHY1].supported;
11282 bp->port.supported[1] =
11283 bp->link_params.phy[EXT_PHY2].supported;
11289 if (!(bp->port.supported[0] || bp->port.supported[1])) {
11290 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11292 dev_info.port_hw_config[port].external_phy_config),
11294 dev_info.port_hw_config[port].external_phy_config2));
11298 if (CHIP_IS_E3(bp))
11299 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11301 switch (switch_cfg) {
11302 case SWITCH_CFG_1G:
11303 bp->port.phy_addr = REG_RD(
11304 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11306 case SWITCH_CFG_10G:
11307 bp->port.phy_addr = REG_RD(
11308 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11311 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11312 bp->port.link_config[0]);
11316 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11317 /* mask what we support according to speed_cap_mask per configuration */
11318 for (idx = 0; idx < cfg_size; idx++) {
11319 if (!(bp->link_params.speed_cap_mask[idx] &
11320 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11321 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11323 if (!(bp->link_params.speed_cap_mask[idx] &
11324 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11325 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11327 if (!(bp->link_params.speed_cap_mask[idx] &
11328 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11329 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11331 if (!(bp->link_params.speed_cap_mask[idx] &
11332 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11333 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11335 if (!(bp->link_params.speed_cap_mask[idx] &
11336 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11337 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11338 SUPPORTED_1000baseT_Full);
11340 if (!(bp->link_params.speed_cap_mask[idx] &
11341 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11342 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11344 if (!(bp->link_params.speed_cap_mask[idx] &
11345 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11346 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11348 if (!(bp->link_params.speed_cap_mask[idx] &
11349 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11350 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11353 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11354 bp->port.supported[1]);
11357 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11359 u32 link_config, idx, cfg_size = 0;
11360 bp->port.advertising[0] = 0;
11361 bp->port.advertising[1] = 0;
11362 switch (bp->link_params.num_phys) {
11371 for (idx = 0; idx < cfg_size; idx++) {
11372 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11373 link_config = bp->port.link_config[idx];
11374 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11375 case PORT_FEATURE_LINK_SPEED_AUTO:
11376 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11377 bp->link_params.req_line_speed[idx] =
11379 bp->port.advertising[idx] |=
11380 bp->port.supported[idx];
11381 if (bp->link_params.phy[EXT_PHY1].type ==
11382 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11383 bp->port.advertising[idx] |=
11384 (SUPPORTED_100baseT_Half |
11385 SUPPORTED_100baseT_Full);
11387 /* force 10G, no AN */
11388 bp->link_params.req_line_speed[idx] =
11390 bp->port.advertising[idx] |=
11391 (ADVERTISED_10000baseT_Full |
11397 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11398 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11399 bp->link_params.req_line_speed[idx] =
11401 bp->port.advertising[idx] |=
11402 (ADVERTISED_10baseT_Full |
11405 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11407 bp->link_params.speed_cap_mask[idx]);
11412 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11413 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11414 bp->link_params.req_line_speed[idx] =
11416 bp->link_params.req_duplex[idx] =
11418 bp->port.advertising[idx] |=
11419 (ADVERTISED_10baseT_Half |
11422 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11424 bp->link_params.speed_cap_mask[idx]);
11429 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11430 if (bp->port.supported[idx] &
11431 SUPPORTED_100baseT_Full) {
11432 bp->link_params.req_line_speed[idx] =
11434 bp->port.advertising[idx] |=
11435 (ADVERTISED_100baseT_Full |
11438 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11440 bp->link_params.speed_cap_mask[idx]);
11445 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11446 if (bp->port.supported[idx] &
11447 SUPPORTED_100baseT_Half) {
11448 bp->link_params.req_line_speed[idx] =
11450 bp->link_params.req_duplex[idx] =
11452 bp->port.advertising[idx] |=
11453 (ADVERTISED_100baseT_Half |
11456 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11458 bp->link_params.speed_cap_mask[idx]);
11463 case PORT_FEATURE_LINK_SPEED_1G:
11464 if (bp->port.supported[idx] &
11465 SUPPORTED_1000baseT_Full) {
11466 bp->link_params.req_line_speed[idx] =
11468 bp->port.advertising[idx] |=
11469 (ADVERTISED_1000baseT_Full |
11471 } else if (bp->port.supported[idx] &
11472 SUPPORTED_1000baseKX_Full) {
11473 bp->link_params.req_line_speed[idx] =
11475 bp->port.advertising[idx] |=
11476 ADVERTISED_1000baseKX_Full;
11478 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11480 bp->link_params.speed_cap_mask[idx]);
11485 case PORT_FEATURE_LINK_SPEED_2_5G:
11486 if (bp->port.supported[idx] &
11487 SUPPORTED_2500baseX_Full) {
11488 bp->link_params.req_line_speed[idx] =
11490 bp->port.advertising[idx] |=
11491 (ADVERTISED_2500baseX_Full |
11494 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11496 bp->link_params.speed_cap_mask[idx]);
11501 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11502 if (bp->port.supported[idx] &
11503 SUPPORTED_10000baseT_Full) {
11504 bp->link_params.req_line_speed[idx] =
11506 bp->port.advertising[idx] |=
11507 (ADVERTISED_10000baseT_Full |
11509 } else if (bp->port.supported[idx] &
11510 SUPPORTED_10000baseKR_Full) {
11511 bp->link_params.req_line_speed[idx] =
11513 bp->port.advertising[idx] |=
11514 (ADVERTISED_10000baseKR_Full |
11517 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11519 bp->link_params.speed_cap_mask[idx]);
11523 case PORT_FEATURE_LINK_SPEED_20G:
11524 bp->link_params.req_line_speed[idx] = SPEED_20000;
11528 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11530 bp->link_params.req_line_speed[idx] =
11532 bp->port.advertising[idx] =
11533 bp->port.supported[idx];
11537 bp->link_params.req_flow_ctrl[idx] = (link_config &
11538 PORT_FEATURE_FLOW_CONTROL_MASK);
11539 if (bp->link_params.req_flow_ctrl[idx] ==
11540 BNX2X_FLOW_CTRL_AUTO) {
11541 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11542 bp->link_params.req_flow_ctrl[idx] =
11543 BNX2X_FLOW_CTRL_NONE;
11545 bnx2x_set_requested_fc(bp);
11548 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11549 bp->link_params.req_line_speed[idx],
11550 bp->link_params.req_duplex[idx],
11551 bp->link_params.req_flow_ctrl[idx],
11552 bp->port.advertising[idx]);
11556 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11558 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11559 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11560 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11561 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11564 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11566 int port = BP_PORT(bp);
11568 u32 ext_phy_type, ext_phy_config, eee_mode;
11570 bp->link_params.bp = bp;
11571 bp->link_params.port = port;
11573 bp->link_params.lane_config =
11574 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11576 bp->link_params.speed_cap_mask[0] =
11578 dev_info.port_hw_config[port].speed_capability_mask) &
11579 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11580 bp->link_params.speed_cap_mask[1] =
11582 dev_info.port_hw_config[port].speed_capability_mask2) &
11583 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11584 bp->port.link_config[0] =
11585 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11587 bp->port.link_config[1] =
11588 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11590 bp->link_params.multi_phy_config =
11591 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11592 /* If the device is capable of WoL, set the default state according
11595 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11596 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11597 (config & PORT_FEATURE_WOL_ENABLED));
11599 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11600 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11601 bp->flags |= NO_ISCSI_FLAG;
11602 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11603 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11604 bp->flags |= NO_FCOE_FLAG;
11606 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11607 bp->link_params.lane_config,
11608 bp->link_params.speed_cap_mask[0],
11609 bp->port.link_config[0]);
11611 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11612 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11613 bnx2x_phy_probe(&bp->link_params);
11614 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11616 bnx2x_link_settings_requested(bp);
11619 * If connected directly, work with the internal PHY, otherwise, work
11620 * with the external PHY
11624 dev_info.port_hw_config[port].external_phy_config);
11625 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11626 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11627 bp->mdio.prtad = bp->port.phy_addr;
11629 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11630 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11632 XGXS_EXT_PHY_ADDR(ext_phy_config);
11634 /* Configure link feature according to nvram value */
11635 eee_mode = (((SHMEM_RD(bp, dev_info.
11636 port_feature_config[port].eee_power_mode)) &
11637 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11638 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11639 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11640 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11641 EEE_MODE_ENABLE_LPI |
11642 EEE_MODE_OUTPUT_TIME;
11644 bp->link_params.eee_mode = 0;
11648 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11650 u32 no_flags = NO_ISCSI_FLAG;
11651 int port = BP_PORT(bp);
11652 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11653 drv_lic_key[port].max_iscsi_conn);
11655 if (!CNIC_SUPPORT(bp)) {
11656 bp->flags |= no_flags;
11660 /* Get the number of maximum allowed iSCSI connections */
11661 bp->cnic_eth_dev.max_iscsi_conn =
11662 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11663 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11665 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11666 bp->cnic_eth_dev.max_iscsi_conn);
11669 * If maximum allowed number of connections is zero -
11670 * disable the feature.
11672 if (!bp->cnic_eth_dev.max_iscsi_conn)
11673 bp->flags |= no_flags;
11676 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11679 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11680 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11681 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11682 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11685 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11686 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11687 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11688 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11691 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11698 /* iterate over absolute function ids for this path: */
11699 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11700 if (IS_MF_SD(bp)) {
11701 u32 cfg = MF_CFG_RD(bp,
11702 func_mf_config[fid].config);
11704 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11705 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11706 FUNC_MF_CFG_PROTOCOL_FCOE))
11709 u32 cfg = MF_CFG_RD(bp,
11710 func_ext_config[fid].
11713 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11714 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11719 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11721 for (port = 0; port < port_cnt; port++) {
11722 u32 lic = SHMEM_RD(bp,
11723 drv_lic_key[port].max_fcoe_conn) ^
11724 FW_ENCODE_32BIT_PATTERN;
11733 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11735 int port = BP_PORT(bp);
11736 int func = BP_ABS_FUNC(bp);
11737 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11738 drv_lic_key[port].max_fcoe_conn);
11739 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11741 if (!CNIC_SUPPORT(bp)) {
11742 bp->flags |= NO_FCOE_FLAG;
11746 /* Get the number of maximum allowed FCoE connections */
11747 bp->cnic_eth_dev.max_fcoe_conn =
11748 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11749 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11751 /* Calculate the number of maximum allowed FCoE tasks */
11752 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11754 /* check if FCoE resources must be shared between different functions */
11756 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11758 /* Read the WWN: */
11761 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11763 dev_info.port_hw_config[port].
11764 fcoe_wwn_port_name_upper);
11765 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11767 dev_info.port_hw_config[port].
11768 fcoe_wwn_port_name_lower);
11771 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11773 dev_info.port_hw_config[port].
11774 fcoe_wwn_node_name_upper);
11775 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11777 dev_info.port_hw_config[port].
11778 fcoe_wwn_node_name_lower);
11779 } else if (!IS_MF_SD(bp)) {
11780 /* Read the WWN info only if the FCoE feature is enabled for
11783 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11784 bnx2x_get_ext_wwn_info(bp, func);
11786 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11787 bnx2x_get_ext_wwn_info(bp, func);
11790 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11793 * If maximum allowed number of connections is zero -
11794 * disable the feature.
11796 if (!bp->cnic_eth_dev.max_fcoe_conn) {
11797 bp->flags |= NO_FCOE_FLAG;
11798 eth_zero_addr(bp->fip_mac);
11802 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11805 * iSCSI may be dynamically disabled but reading
11806 * info here we will decrease memory usage by driver
11807 * if the feature is disabled for good
11809 bnx2x_get_iscsi_info(bp);
11810 bnx2x_get_fcoe_info(bp);
11813 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11816 int func = BP_ABS_FUNC(bp);
11817 int port = BP_PORT(bp);
11818 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11819 u8 *fip_mac = bp->fip_mac;
11822 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11823 * FCoE MAC then the appropriate feature should be disabled.
11824 * In non SD mode features configuration comes from struct
11827 if (!IS_MF_SD(bp)) {
11828 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11829 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11830 val2 = MF_CFG_RD(bp, func_ext_config[func].
11831 iscsi_mac_addr_upper);
11832 val = MF_CFG_RD(bp, func_ext_config[func].
11833 iscsi_mac_addr_lower);
11834 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11836 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11838 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11841 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11842 val2 = MF_CFG_RD(bp, func_ext_config[func].
11843 fcoe_mac_addr_upper);
11844 val = MF_CFG_RD(bp, func_ext_config[func].
11845 fcoe_mac_addr_lower);
11846 bnx2x_set_mac_buf(fip_mac, val, val2);
11848 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11850 bp->flags |= NO_FCOE_FLAG;
11853 bp->mf_ext_config = cfg;
11855 } else { /* SD MODE */
11856 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11857 /* use primary mac as iscsi mac */
11858 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11860 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11862 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11863 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11864 /* use primary mac as fip mac */
11865 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11866 BNX2X_DEV_INFO("SD FCoE MODE\n");
11868 ("Read FIP MAC: %pM\n", fip_mac);
11872 /* If this is a storage-only interface, use SAN mac as
11873 * primary MAC. Notice that for SD this is already the case,
11874 * as the SAN mac was copied from the primary MAC.
11876 if (IS_MF_FCOE_AFEX(bp))
11877 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11879 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11881 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11883 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11885 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11886 fcoe_fip_mac_upper);
11887 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11888 fcoe_fip_mac_lower);
11889 bnx2x_set_mac_buf(fip_mac, val, val2);
11892 /* Disable iSCSI OOO if MAC configuration is invalid. */
11893 if (!is_valid_ether_addr(iscsi_mac)) {
11894 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11895 eth_zero_addr(iscsi_mac);
11898 /* Disable FCoE if MAC configuration is invalid. */
11899 if (!is_valid_ether_addr(fip_mac)) {
11900 bp->flags |= NO_FCOE_FLAG;
11901 eth_zero_addr(bp->fip_mac);
11905 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11908 int func = BP_ABS_FUNC(bp);
11909 int port = BP_PORT(bp);
11911 /* Zero primary MAC configuration */
11912 eth_zero_addr(bp->dev->dev_addr);
11914 if (BP_NOMCP(bp)) {
11915 BNX2X_ERROR("warning: random MAC workaround active\n");
11916 eth_hw_addr_random(bp->dev);
11917 } else if (IS_MF(bp)) {
11918 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11919 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11920 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11921 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11922 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11924 if (CNIC_SUPPORT(bp))
11925 bnx2x_get_cnic_mac_hwinfo(bp);
11927 /* in SF read MACs from port configuration */
11928 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11929 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11930 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11932 if (CNIC_SUPPORT(bp))
11933 bnx2x_get_cnic_mac_hwinfo(bp);
11936 if (!BP_NOMCP(bp)) {
11937 /* Read physical port identifier from shmem */
11938 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11939 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11940 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11941 bp->flags |= HAS_PHYS_PORT_ID;
11944 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11946 if (!is_valid_ether_addr(bp->dev->dev_addr))
11947 dev_err(&bp->pdev->dev,
11948 "bad Ethernet MAC address configuration: %pM\n"
11949 "change it manually before bringing up the appropriate network interface\n",
11950 bp->dev->dev_addr);
11953 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11961 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11962 /* Take function: tmp = func */
11963 tmp = BP_ABS_FUNC(bp);
11964 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11965 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11967 /* Take port: tmp = port */
11970 dev_info.port_hw_config[tmp].generic_features);
11971 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11976 static void validate_set_si_mode(struct bnx2x *bp)
11978 u8 func = BP_ABS_FUNC(bp);
11981 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11983 /* check for legal mac (upper bytes) */
11984 if (val != 0xffff) {
11985 bp->mf_mode = MULTI_FUNCTION_SI;
11986 bp->mf_config[BP_VN(bp)] =
11987 MF_CFG_RD(bp, func_mf_config[func].config);
11989 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11992 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11994 int /*abs*/func = BP_ABS_FUNC(bp);
11996 u32 val = 0, val2 = 0;
11999 /* Validate that chip access is feasible */
12000 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
12001 dev_err(&bp->pdev->dev,
12002 "Chip read returns all Fs. Preventing probe from continuing\n");
12006 bnx2x_get_common_hwinfo(bp);
12009 * initialize IGU parameters
12011 if (CHIP_IS_E1x(bp)) {
12012 bp->common.int_block = INT_BLOCK_HC;
12014 bp->igu_dsb_id = DEF_SB_IGU_ID;
12015 bp->igu_base_sb = 0;
12017 bp->common.int_block = INT_BLOCK_IGU;
12019 /* do not allow device reset during IGU info processing */
12020 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12022 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
12024 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12027 BNX2X_DEV_INFO("FORCING Normal Mode\n");
12029 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
12030 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
12031 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
12033 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12035 usleep_range(1000, 2000);
12038 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12039 dev_err(&bp->pdev->dev,
12040 "FORCING Normal Mode failed!!!\n");
12041 bnx2x_release_hw_lock(bp,
12042 HW_LOCK_RESOURCE_RESET);
12047 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12048 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
12049 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
12051 BNX2X_DEV_INFO("IGU Normal Mode\n");
12053 rc = bnx2x_get_igu_cam_info(bp);
12054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12060 * set base FW non-default (fast path) status block id, this value is
12061 * used to initialize the fw_sb_id saved on the fp/queue structure to
12062 * determine the id used by the FW.
12064 if (CHIP_IS_E1x(bp))
12065 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
12067 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
12068 * the same queue are indicated on the same IGU SB). So we prefer
12069 * FW and IGU SBs to be the same value.
12071 bp->base_fw_ndsb = bp->igu_base_sb;
12073 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
12074 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12075 bp->igu_sb_cnt, bp->base_fw_ndsb);
12078 * Initialize MF configuration
12083 bp->mf_sub_mode = 0;
12085 mfw_vn = BP_FW_MB_IDX(bp);
12087 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
12088 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12089 bp->common.shmem2_base, SHMEM2_RD(bp, size),
12090 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12092 if (SHMEM2_HAS(bp, mf_cfg_addr))
12093 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12095 bp->common.mf_cfg_base = bp->common.shmem_base +
12096 offsetof(struct shmem_region, func_mb) +
12097 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
12099 * get mf configuration:
12100 * 1. Existence of MF configuration
12101 * 2. MAC address must be legal (check only upper bytes)
12102 * for Switch-Independent mode;
12103 * OVLAN must be legal for Switch-Dependent mode
12104 * 3. SF_MODE configures specific MF mode
12106 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12107 /* get mf configuration */
12109 dev_info.shared_feature_config.config);
12110 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12113 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12114 validate_set_si_mode(bp);
12116 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12117 if ((!CHIP_IS_E1x(bp)) &&
12118 (MF_CFG_RD(bp, func_mf_config[func].
12119 mac_upper) != 0xffff) &&
12121 afex_driver_support))) {
12122 bp->mf_mode = MULTI_FUNCTION_AFEX;
12123 bp->mf_config[vn] = MF_CFG_RD(bp,
12124 func_mf_config[func].config);
12126 BNX2X_DEV_INFO("can not configure afex mode\n");
12129 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12130 /* get OV configuration */
12131 val = MF_CFG_RD(bp,
12132 func_mf_config[FUNC_0].e1hov_tag);
12133 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12135 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12136 bp->mf_mode = MULTI_FUNCTION_SD;
12137 bp->mf_config[vn] = MF_CFG_RD(bp,
12138 func_mf_config[func].config);
12140 BNX2X_DEV_INFO("illegal OV for SD\n");
12142 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12143 bp->mf_mode = MULTI_FUNCTION_SD;
12144 bp->mf_sub_mode = SUB_MF_MODE_BD;
12145 bp->mf_config[vn] =
12147 func_mf_config[func].config);
12149 if (SHMEM2_HAS(bp, mtu_size)) {
12150 int mtu_idx = BP_FW_MB_IDX(bp);
12154 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12155 mtu_size = (u16)mtu;
12156 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12159 /* if valid: update device mtu */
12160 if ((mtu_size >= ETH_MIN_PACKET_SIZE) &&
12162 ETH_MAX_JUMBO_PACKET_SIZE))
12163 bp->dev->mtu = mtu_size;
12166 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12167 bp->mf_mode = MULTI_FUNCTION_SD;
12168 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12169 bp->mf_config[vn] =
12171 func_mf_config[func].config);
12173 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12174 bp->mf_config[vn] = 0;
12176 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12177 val2 = SHMEM_RD(bp,
12178 dev_info.shared_hw_config.config_3);
12179 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12181 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12182 validate_set_si_mode(bp);
12184 SUB_MF_MODE_NPAR1_DOT_5;
12187 /* Unknown configuration */
12188 bp->mf_config[vn] = 0;
12189 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12194 /* Unknown configuration: reset mf_config */
12195 bp->mf_config[vn] = 0;
12196 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12200 BNX2X_DEV_INFO("%s function mode\n",
12201 IS_MF(bp) ? "multi" : "single");
12203 switch (bp->mf_mode) {
12204 case MULTI_FUNCTION_SD:
12205 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12206 FUNC_MF_CFG_E1HOV_TAG_MASK;
12207 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12209 bp->path_has_ovlan = true;
12211 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12212 func, bp->mf_ov, bp->mf_ov);
12213 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12214 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12215 dev_err(&bp->pdev->dev,
12216 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12218 bp->path_has_ovlan = true;
12220 dev_err(&bp->pdev->dev,
12221 "No valid MF OV for func %d, aborting\n",
12226 case MULTI_FUNCTION_AFEX:
12227 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12229 case MULTI_FUNCTION_SI:
12230 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12235 dev_err(&bp->pdev->dev,
12236 "VN %d is in a single function mode, aborting\n",
12243 /* check if other port on the path needs ovlan:
12244 * Since MF configuration is shared between ports
12245 * Possible mixed modes are only
12246 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12248 if (CHIP_MODE_IS_4_PORT(bp) &&
12249 !bp->path_has_ovlan &&
12251 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12252 u8 other_port = !BP_PORT(bp);
12253 u8 other_func = BP_PATH(bp) + 2*other_port;
12254 val = MF_CFG_RD(bp,
12255 func_mf_config[other_func].e1hov_tag);
12256 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12257 bp->path_has_ovlan = true;
12261 /* adjust igu_sb_cnt to MF for E1H */
12262 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12263 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12266 bnx2x_get_port_hwinfo(bp);
12268 /* Get MAC addresses */
12269 bnx2x_get_mac_hwinfo(bp);
12271 bnx2x_get_cnic_info(bp);
12276 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12278 int cnt, i, block_end, rodi;
12279 char vpd_start[BNX2X_VPD_LEN+1];
12280 char str_id_reg[VENDOR_ID_LEN+1];
12281 char str_id_cap[VENDOR_ID_LEN+1];
12283 char *vpd_extended_data = NULL;
12286 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12287 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12289 if (cnt < BNX2X_VPD_LEN)
12290 goto out_not_found;
12292 /* VPD RO tag should be first tag after identifier string, hence
12293 * we should be able to find it in first BNX2X_VPD_LEN chars
12295 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12296 PCI_VPD_LRDT_RO_DATA);
12298 goto out_not_found;
12300 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12301 pci_vpd_lrdt_size(&vpd_start[i]);
12303 i += PCI_VPD_LRDT_TAG_SIZE;
12305 if (block_end > BNX2X_VPD_LEN) {
12306 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12307 if (vpd_extended_data == NULL)
12308 goto out_not_found;
12310 /* read rest of vpd image into vpd_extended_data */
12311 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12312 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12313 block_end - BNX2X_VPD_LEN,
12314 vpd_extended_data + BNX2X_VPD_LEN);
12315 if (cnt < (block_end - BNX2X_VPD_LEN))
12316 goto out_not_found;
12317 vpd_data = vpd_extended_data;
12319 vpd_data = vpd_start;
12321 /* now vpd_data holds full vpd content in both cases */
12323 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12324 PCI_VPD_RO_KEYWORD_MFR_ID);
12326 goto out_not_found;
12328 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12330 if (len != VENDOR_ID_LEN)
12331 goto out_not_found;
12333 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12335 /* vendor specific info */
12336 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12337 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12338 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12339 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12341 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12342 PCI_VPD_RO_KEYWORD_VENDOR0);
12344 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12346 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12348 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12349 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12350 bp->fw_ver[len] = ' ';
12353 kfree(vpd_extended_data);
12357 kfree(vpd_extended_data);
12361 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12365 if (CHIP_REV_IS_FPGA(bp))
12366 SET_FLAGS(flags, MODE_FPGA);
12367 else if (CHIP_REV_IS_EMUL(bp))
12368 SET_FLAGS(flags, MODE_EMUL);
12370 SET_FLAGS(flags, MODE_ASIC);
12372 if (CHIP_MODE_IS_4_PORT(bp))
12373 SET_FLAGS(flags, MODE_PORT4);
12375 SET_FLAGS(flags, MODE_PORT2);
12377 if (CHIP_IS_E2(bp))
12378 SET_FLAGS(flags, MODE_E2);
12379 else if (CHIP_IS_E3(bp)) {
12380 SET_FLAGS(flags, MODE_E3);
12381 if (CHIP_REV(bp) == CHIP_REV_Ax)
12382 SET_FLAGS(flags, MODE_E3_A0);
12383 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12384 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12388 SET_FLAGS(flags, MODE_MF);
12389 switch (bp->mf_mode) {
12390 case MULTI_FUNCTION_SD:
12391 SET_FLAGS(flags, MODE_MF_SD);
12393 case MULTI_FUNCTION_SI:
12394 SET_FLAGS(flags, MODE_MF_SI);
12396 case MULTI_FUNCTION_AFEX:
12397 SET_FLAGS(flags, MODE_MF_AFEX);
12401 SET_FLAGS(flags, MODE_SF);
12403 #if defined(__LITTLE_ENDIAN)
12404 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12405 #else /*(__BIG_ENDIAN)*/
12406 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12408 INIT_MODE_FLAGS(bp) = flags;
12411 static int bnx2x_init_bp(struct bnx2x *bp)
12416 mutex_init(&bp->port.phy_mutex);
12417 mutex_init(&bp->fw_mb_mutex);
12418 mutex_init(&bp->drv_info_mutex);
12419 sema_init(&bp->stats_lock, 1);
12420 bp->drv_info_mng_owner = false;
12421 INIT_LIST_HEAD(&bp->vlan_reg);
12423 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12424 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12425 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12426 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12428 rc = bnx2x_get_hwinfo(bp);
12432 eth_zero_addr(bp->dev->dev_addr);
12435 bnx2x_set_modes_bitmap(bp);
12437 rc = bnx2x_alloc_mem_bp(bp);
12441 bnx2x_read_fwinfo(bp);
12443 func = BP_FUNC(bp);
12445 /* need to reset chip if undi was active */
12446 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12449 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12450 DRV_MSG_SEQ_NUMBER_MASK;
12451 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12453 rc = bnx2x_prev_unload(bp);
12455 bnx2x_free_mem_bp(bp);
12460 if (CHIP_REV_IS_FPGA(bp))
12461 dev_err(&bp->pdev->dev, "FPGA detected\n");
12463 if (BP_NOMCP(bp) && (func == 0))
12464 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12466 bp->disable_tpa = disable_tpa;
12467 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12468 /* Reduce memory usage in kdump environment by disabling TPA */
12469 bp->disable_tpa |= is_kdump_kernel();
12471 /* Set TPA flags */
12472 if (bp->disable_tpa) {
12473 bp->dev->hw_features &= ~NETIF_F_LRO;
12474 bp->dev->features &= ~NETIF_F_LRO;
12477 if (CHIP_IS_E1(bp))
12478 bp->dropless_fc = 0;
12480 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12484 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12486 bp->rx_ring_size = MAX_RX_AVAIL;
12488 /* make sure that the numbers are in the right granularity */
12489 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12490 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12492 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12494 init_timer(&bp->timer);
12495 bp->timer.expires = jiffies + bp->current_interval;
12496 bp->timer.data = (unsigned long) bp;
12497 bp->timer.function = bnx2x_timer;
12499 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12500 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12501 SHMEM2_HAS(bp, dcbx_en) &&
12502 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12503 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12504 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
12505 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12506 bnx2x_dcbx_init_params(bp);
12508 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12511 if (CHIP_IS_E1x(bp))
12512 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12514 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12516 /* multiple tx priority */
12519 else if (CHIP_IS_E1x(bp))
12520 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12521 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12522 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12523 else if (CHIP_IS_E3B0(bp))
12524 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12526 BNX2X_ERR("unknown chip %x revision %x\n",
12527 CHIP_NUM(bp), CHIP_REV(bp));
12528 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12530 /* We need at least one default status block for slow-path events,
12531 * second status block for the L2 queue, and a third status block for
12532 * CNIC if supported.
12535 bp->min_msix_vec_cnt = 1;
12536 else if (CNIC_SUPPORT(bp))
12537 bp->min_msix_vec_cnt = 3;
12538 else /* PF w/o cnic */
12539 bp->min_msix_vec_cnt = 2;
12540 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12542 bp->dump_preset_idx = 1;
12544 if (CHIP_IS_E3B0(bp))
12545 bp->flags |= PTP_SUPPORTED;
12550 /****************************************************************************
12551 * General service functions
12552 ****************************************************************************/
12555 * net_device service functions
12558 /* called with rtnl_lock */
12559 static int bnx2x_open(struct net_device *dev)
12561 struct bnx2x *bp = netdev_priv(dev);
12564 bp->stats_init = true;
12566 netif_carrier_off(dev);
12568 bnx2x_set_power_state(bp, PCI_D0);
12570 /* If parity had happen during the unload, then attentions
12571 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12572 * want the first function loaded on the current engine to
12573 * complete the recovery.
12574 * Parity recovery is only relevant for PF driver.
12577 int other_engine = BP_PATH(bp) ? 0 : 1;
12578 bool other_load_status, load_status;
12579 bool global = false;
12581 other_load_status = bnx2x_get_load_status(bp, other_engine);
12582 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12583 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12584 bnx2x_chk_parity_attn(bp, &global, true)) {
12586 /* If there are attentions and they are in a
12587 * global blocks, set the GLOBAL_RESET bit
12588 * regardless whether it will be this function
12589 * that will complete the recovery or not.
12592 bnx2x_set_reset_global(bp);
12594 /* Only the first function on the current
12595 * engine should try to recover in open. In case
12596 * of attentions in global blocks only the first
12597 * in the chip should try to recover.
12599 if ((!load_status &&
12600 (!global || !other_load_status)) &&
12601 bnx2x_trylock_leader_lock(bp) &&
12602 !bnx2x_leader_reset(bp)) {
12603 netdev_info(bp->dev,
12604 "Recovered in open\n");
12608 /* recovery has failed... */
12609 bnx2x_set_power_state(bp, PCI_D3hot);
12610 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12612 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12613 "If you still see this message after a few retries then power cycle is required.\n");
12620 bp->recovery_state = BNX2X_RECOVERY_DONE;
12621 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12626 udp_tunnel_get_rx_info(dev);
12631 /* called with rtnl_lock */
12632 static int bnx2x_close(struct net_device *dev)
12634 struct bnx2x *bp = netdev_priv(dev);
12636 /* Unload the driver, release IRQs */
12637 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12642 struct bnx2x_mcast_list_elem_group
12644 struct list_head mcast_group_link;
12645 struct bnx2x_mcast_list_elem mcast_elems[];
12648 #define MCAST_ELEMS_PER_PG \
12649 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12650 sizeof(struct bnx2x_mcast_list_elem))
12652 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12654 struct bnx2x_mcast_list_elem_group *current_mcast_group;
12656 while (!list_empty(mcast_group_list)) {
12657 current_mcast_group = list_first_entry(mcast_group_list,
12658 struct bnx2x_mcast_list_elem_group,
12660 list_del(¤t_mcast_group->mcast_group_link);
12661 free_page((unsigned long)current_mcast_group);
12665 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12666 struct bnx2x_mcast_ramrod_params *p,
12667 struct list_head *mcast_group_list)
12669 struct bnx2x_mcast_list_elem *mc_mac;
12670 struct netdev_hw_addr *ha;
12671 struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12672 int mc_count = netdev_mc_count(bp->dev);
12675 INIT_LIST_HEAD(&p->mcast_list);
12676 netdev_for_each_mc_addr(ha, bp->dev) {
12678 current_mcast_group =
12679 (struct bnx2x_mcast_list_elem_group *)
12680 __get_free_page(GFP_ATOMIC);
12681 if (!current_mcast_group) {
12682 bnx2x_free_mcast_macs_list(mcast_group_list);
12683 BNX2X_ERR("Failed to allocate mc MAC list\n");
12686 list_add(¤t_mcast_group->mcast_group_link,
12689 mc_mac = ¤t_mcast_group->mcast_elems[offset];
12690 mc_mac->mac = bnx2x_mc_addr(ha);
12691 list_add_tail(&mc_mac->link, &p->mcast_list);
12693 if (offset == MCAST_ELEMS_PER_PG)
12696 p->mcast_list_len = mc_count;
12701 * bnx2x_set_uc_list - configure a new unicast MACs list.
12703 * @bp: driver handle
12705 * We will use zero (0) as a MAC type for these MACs.
12707 static int bnx2x_set_uc_list(struct bnx2x *bp)
12710 struct net_device *dev = bp->dev;
12711 struct netdev_hw_addr *ha;
12712 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12713 unsigned long ramrod_flags = 0;
12715 /* First schedule a cleanup up of old configuration */
12716 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12718 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12722 netdev_for_each_uc_addr(ha, dev) {
12723 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12724 BNX2X_UC_LIST_MAC, &ramrod_flags);
12725 if (rc == -EEXIST) {
12727 "Failed to schedule ADD operations: %d\n", rc);
12728 /* do not treat adding same MAC as error */
12731 } else if (rc < 0) {
12733 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12739 /* Execute the pending commands */
12740 __set_bit(RAMROD_CONT, &ramrod_flags);
12741 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12742 BNX2X_UC_LIST_MAC, &ramrod_flags);
12745 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
12747 LIST_HEAD(mcast_group_list);
12748 struct net_device *dev = bp->dev;
12749 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12752 rparam.mcast_obj = &bp->mcast_obj;
12754 /* first, clear all configured multicast MACs */
12755 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12757 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12761 /* then, configure a new MACs list */
12762 if (netdev_mc_count(dev)) {
12763 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12767 /* Now add the new MACs */
12768 rc = bnx2x_config_mcast(bp, &rparam,
12769 BNX2X_MCAST_CMD_ADD);
12771 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12774 bnx2x_free_mcast_macs_list(&mcast_group_list);
12780 static int bnx2x_set_mc_list(struct bnx2x *bp)
12782 LIST_HEAD(mcast_group_list);
12783 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12784 struct net_device *dev = bp->dev;
12787 /* On older adapters, we need to flush and re-add filters */
12788 if (CHIP_IS_E1x(bp))
12789 return bnx2x_set_mc_list_e1x(bp);
12791 rparam.mcast_obj = &bp->mcast_obj;
12793 if (netdev_mc_count(dev)) {
12794 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12798 /* Override the curently configured set of mc filters */
12799 rc = bnx2x_config_mcast(bp, &rparam,
12800 BNX2X_MCAST_CMD_SET);
12802 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12805 bnx2x_free_mcast_macs_list(&mcast_group_list);
12807 /* If no mc addresses are required, flush the configuration */
12808 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12810 BNX2X_ERR("Failed to clear multicast configuration %d\n",
12817 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12818 static void bnx2x_set_rx_mode(struct net_device *dev)
12820 struct bnx2x *bp = netdev_priv(dev);
12822 if (bp->state != BNX2X_STATE_OPEN) {
12823 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12826 /* Schedule an SP task to handle rest of change */
12827 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12832 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12834 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12836 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12838 netif_addr_lock_bh(bp->dev);
12840 if (bp->dev->flags & IFF_PROMISC) {
12841 rx_mode = BNX2X_RX_MODE_PROMISC;
12842 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12843 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12845 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12848 /* some multicasts */
12849 if (bnx2x_set_mc_list(bp) < 0)
12850 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12852 /* release bh lock, as bnx2x_set_uc_list might sleep */
12853 netif_addr_unlock_bh(bp->dev);
12854 if (bnx2x_set_uc_list(bp) < 0)
12855 rx_mode = BNX2X_RX_MODE_PROMISC;
12856 netif_addr_lock_bh(bp->dev);
12858 /* configuring mcast to a vf involves sleeping (when we
12859 * wait for the pf's response).
12861 bnx2x_schedule_sp_rtnl(bp,
12862 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12866 bp->rx_mode = rx_mode;
12867 /* handle ISCSI SD mode */
12868 if (IS_MF_ISCSI_ONLY(bp))
12869 bp->rx_mode = BNX2X_RX_MODE_NONE;
12871 /* Schedule the rx_mode command */
12872 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12873 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12874 netif_addr_unlock_bh(bp->dev);
12879 bnx2x_set_storm_rx_mode(bp);
12880 netif_addr_unlock_bh(bp->dev);
12882 /* VF will need to request the PF to make this change, and so
12883 * the VF needs to release the bottom-half lock prior to the
12884 * request (as it will likely require sleep on the VF side)
12886 netif_addr_unlock_bh(bp->dev);
12887 bnx2x_vfpf_storm_rx_mode(bp);
12891 /* called with rtnl_lock */
12892 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12893 int devad, u16 addr)
12895 struct bnx2x *bp = netdev_priv(netdev);
12899 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12900 prtad, devad, addr);
12902 /* The HW expects different devad if CL22 is used */
12903 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12905 bnx2x_acquire_phy_lock(bp);
12906 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12907 bnx2x_release_phy_lock(bp);
12908 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12915 /* called with rtnl_lock */
12916 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12917 u16 addr, u16 value)
12919 struct bnx2x *bp = netdev_priv(netdev);
12923 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12924 prtad, devad, addr, value);
12926 /* The HW expects different devad if CL22 is used */
12927 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12929 bnx2x_acquire_phy_lock(bp);
12930 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12931 bnx2x_release_phy_lock(bp);
12935 /* called with rtnl_lock */
12936 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12938 struct bnx2x *bp = netdev_priv(dev);
12939 struct mii_ioctl_data *mdio = if_mii(ifr);
12941 if (!netif_running(dev))
12945 case SIOCSHWTSTAMP:
12946 return bnx2x_hwtstamp_ioctl(bp, ifr);
12948 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12949 mdio->phy_id, mdio->reg_num, mdio->val_in);
12950 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12954 #ifdef CONFIG_NET_POLL_CONTROLLER
12955 static void poll_bnx2x(struct net_device *dev)
12957 struct bnx2x *bp = netdev_priv(dev);
12960 for_each_eth_queue(bp, i) {
12961 struct bnx2x_fastpath *fp = &bp->fp[i];
12962 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12967 static int bnx2x_validate_addr(struct net_device *dev)
12969 struct bnx2x *bp = netdev_priv(dev);
12971 /* query the bulletin board for mac address configured by the PF */
12973 bnx2x_sample_bulletin(bp);
12975 if (!is_valid_ether_addr(dev->dev_addr)) {
12976 BNX2X_ERR("Non-valid Ethernet address\n");
12977 return -EADDRNOTAVAIL;
12982 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12983 struct netdev_phys_item_id *ppid)
12985 struct bnx2x *bp = netdev_priv(netdev);
12987 if (!(bp->flags & HAS_PHYS_PORT_ID))
12988 return -EOPNOTSUPP;
12990 ppid->id_len = sizeof(bp->phys_port_id);
12991 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12996 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12997 struct net_device *dev,
12998 netdev_features_t features)
13001 * A skb with gso_size + header length > 9700 will cause a
13002 * firmware panic. Drop GSO support.
13004 * Eventually the upper layer should not pass these packets down.
13006 * For speed, if the gso_size is <= 9000, assume there will
13007 * not be 700 bytes of headers and pass it through. Only do a
13008 * full (slow) validation if the gso_size is > 9000.
13010 * (Due to the way SKB_BY_FRAGS works this will also do a full
13011 * validation in that case.)
13013 if (unlikely(skb_is_gso(skb) &&
13014 (skb_shinfo(skb)->gso_size > 9000) &&
13015 !skb_gso_validate_mac_len(skb, 9700)))
13016 features &= ~NETIF_F_GSO_MASK;
13018 features = vlan_features_check(skb, features);
13019 return vxlan_features_check(skb, features);
13022 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
13027 unsigned long ramrod_flags = 0;
13029 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13030 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
13031 add, &ramrod_flags);
13033 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
13039 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
13041 struct bnx2x_vlan_entry *vlan;
13044 /* Configure all non-configured entries */
13045 list_for_each_entry(vlan, &bp->vlan_reg, link) {
13049 if (bp->vlan_cnt >= bp->vlan_credit)
13052 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
13054 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
13058 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
13066 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
13068 bool need_accept_any_vlan;
13070 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
13072 if (bp->accept_any_vlan != need_accept_any_vlan) {
13073 bp->accept_any_vlan = need_accept_any_vlan;
13074 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
13075 bp->accept_any_vlan ? "raised" : "cleared");
13078 bnx2x_set_rx_mode_inner(bp);
13080 bnx2x_vfpf_storm_rx_mode(bp);
13085 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
13087 /* Don't set rx mode here. Our caller will do it. */
13088 bnx2x_vlan_configure(bp, false);
13093 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
13095 struct bnx2x *bp = netdev_priv(dev);
13096 struct bnx2x_vlan_entry *vlan;
13098 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
13100 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
13106 list_add_tail(&vlan->link, &bp->vlan_reg);
13108 if (netif_running(dev))
13109 bnx2x_vlan_configure(bp, true);
13114 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13116 struct bnx2x *bp = netdev_priv(dev);
13117 struct bnx2x_vlan_entry *vlan;
13118 bool found = false;
13121 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13123 list_for_each_entry(vlan, &bp->vlan_reg, link)
13124 if (vlan->vid == vid) {
13130 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13134 if (netif_running(dev) && vlan->hw) {
13135 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13136 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13140 list_del(&vlan->link);
13143 if (netif_running(dev))
13144 bnx2x_vlan_configure(bp, true);
13146 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13151 static const struct net_device_ops bnx2x_netdev_ops = {
13152 .ndo_open = bnx2x_open,
13153 .ndo_stop = bnx2x_close,
13154 .ndo_start_xmit = bnx2x_start_xmit,
13155 .ndo_select_queue = bnx2x_select_queue,
13156 .ndo_set_rx_mode = bnx2x_set_rx_mode,
13157 .ndo_set_mac_address = bnx2x_change_mac_addr,
13158 .ndo_validate_addr = bnx2x_validate_addr,
13159 .ndo_do_ioctl = bnx2x_ioctl,
13160 .ndo_change_mtu = bnx2x_change_mtu,
13161 .ndo_fix_features = bnx2x_fix_features,
13162 .ndo_set_features = bnx2x_set_features,
13163 .ndo_tx_timeout = bnx2x_tx_timeout,
13164 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
13165 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
13166 #ifdef CONFIG_NET_POLL_CONTROLLER
13167 .ndo_poll_controller = poll_bnx2x,
13169 .ndo_setup_tc = __bnx2x_setup_tc,
13170 #ifdef CONFIG_BNX2X_SRIOV
13171 .ndo_set_vf_mac = bnx2x_set_vf_mac,
13172 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
13173 .ndo_get_vf_config = bnx2x_get_vf_config,
13175 #ifdef NETDEV_FCOE_WWNN
13176 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
13179 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
13180 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
13181 .ndo_features_check = bnx2x_features_check,
13182 .ndo_udp_tunnel_add = bnx2x_udp_tunnel_add,
13183 .ndo_udp_tunnel_del = bnx2x_udp_tunnel_del,
13186 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13188 struct device *dev = &bp->pdev->dev;
13190 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13191 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13192 dev_err(dev, "System does not support DMA, aborting\n");
13199 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13201 if (bp->flags & AER_ENABLED) {
13202 pci_disable_pcie_error_reporting(bp->pdev);
13203 bp->flags &= ~AER_ENABLED;
13207 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13208 struct net_device *dev, unsigned long board_type)
13212 bool chip_is_e1x = (board_type == BCM57710 ||
13213 board_type == BCM57711 ||
13214 board_type == BCM57711E);
13216 SET_NETDEV_DEV(dev, &pdev->dev);
13221 rc = pci_enable_device(pdev);
13223 dev_err(&bp->pdev->dev,
13224 "Cannot enable PCI device, aborting\n");
13228 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13229 dev_err(&bp->pdev->dev,
13230 "Cannot find PCI device base address, aborting\n");
13232 goto err_out_disable;
13235 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13236 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13238 goto err_out_disable;
13241 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13242 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13243 PCICFG_REVESION_ID_ERROR_VAL) {
13244 pr_err("PCI device error, probably due to fan failure, aborting\n");
13246 goto err_out_disable;
13249 if (atomic_read(&pdev->enable_cnt) == 1) {
13250 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13252 dev_err(&bp->pdev->dev,
13253 "Cannot obtain PCI resources, aborting\n");
13254 goto err_out_disable;
13257 pci_set_master(pdev);
13258 pci_save_state(pdev);
13262 if (!pdev->pm_cap) {
13263 dev_err(&bp->pdev->dev,
13264 "Cannot find power management capability, aborting\n");
13266 goto err_out_release;
13270 if (!pci_is_pcie(pdev)) {
13271 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13273 goto err_out_release;
13276 rc = bnx2x_set_coherency_mask(bp);
13278 goto err_out_release;
13280 dev->mem_start = pci_resource_start(pdev, 0);
13281 dev->base_addr = dev->mem_start;
13282 dev->mem_end = pci_resource_end(pdev, 0);
13284 dev->irq = pdev->irq;
13286 bp->regview = pci_ioremap_bar(pdev, 0);
13287 if (!bp->regview) {
13288 dev_err(&bp->pdev->dev,
13289 "Cannot map register space, aborting\n");
13291 goto err_out_release;
13294 /* In E1/E1H use pci device function given by kernel.
13295 * In E2/E3 read physical function from ME register since these chips
13296 * support Physical Device Assignment where kernel BDF maybe arbitrary
13297 * (depending on hypervisor).
13300 bp->pf_num = PCI_FUNC(pdev->devfn);
13303 pci_read_config_dword(bp->pdev,
13304 PCICFG_ME_REGISTER, &pci_cfg_dword);
13305 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13306 ME_REG_ABS_PF_NUM_SHIFT);
13308 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13310 /* clean indirect addresses */
13311 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13312 PCICFG_VENDOR_ID_OFFSET);
13314 /* Set PCIe reset type to fundamental for EEH recovery */
13315 pdev->needs_freset = 1;
13317 /* AER (Advanced Error reporting) configuration */
13318 rc = pci_enable_pcie_error_reporting(pdev);
13320 bp->flags |= AER_ENABLED;
13322 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13325 * Clean the following indirect addresses for all functions since it
13326 * is not used by the driver.
13329 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13330 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13331 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13332 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13335 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13336 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13337 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13338 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13341 /* Enable internal target-read (in case we are probed after PF
13342 * FLR). Must be done prior to any BAR read access. Only for
13347 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13350 dev->watchdog_timeo = TX_TIMEOUT;
13352 dev->netdev_ops = &bnx2x_netdev_ops;
13353 bnx2x_set_ethtool_ops(bp, dev);
13355 dev->priv_flags |= IFF_UNICAST_FLT;
13357 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13358 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13359 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13360 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13361 if (!chip_is_e1x) {
13362 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13363 NETIF_F_GSO_IPXIP4 |
13364 NETIF_F_GSO_UDP_TUNNEL |
13365 NETIF_F_GSO_UDP_TUNNEL_CSUM |
13366 NETIF_F_GSO_PARTIAL;
13368 dev->hw_enc_features =
13369 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13370 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13371 NETIF_F_GSO_IPXIP4 |
13372 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13373 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13374 NETIF_F_GSO_PARTIAL;
13376 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13377 NETIF_F_GSO_UDP_TUNNEL_CSUM;
13380 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13381 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13385 bp->accept_any_vlan = true;
13387 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13389 /* For VF we'll know whether to enable VLAN filtering after
13390 * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13393 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13394 dev->features |= NETIF_F_HIGHDMA;
13396 /* Add Loopback capability to the device */
13397 dev->hw_features |= NETIF_F_LOOPBACK;
13400 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13403 /* MTU range, 46 - 9600 */
13404 dev->min_mtu = ETH_MIN_PACKET_SIZE;
13405 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE;
13407 /* get_port_hwinfo() will set prtad and mmds properly */
13408 bp->mdio.prtad = MDIO_PRTAD_NONE;
13410 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13411 bp->mdio.dev = dev;
13412 bp->mdio.mdio_read = bnx2x_mdio_read;
13413 bp->mdio.mdio_write = bnx2x_mdio_write;
13418 if (atomic_read(&pdev->enable_cnt) == 1)
13419 pci_release_regions(pdev);
13422 pci_disable_device(pdev);
13430 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13432 const __be32 *source = (const __be32 *)_source;
13433 u32 *target = (u32 *)_target;
13436 for (i = 0; i < n/4; i++)
13437 target[i] = be32_to_cpu(source[i]);
13441 Ops array is stored in the following format:
13442 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13444 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13446 const __be32 *source = (const __be32 *)_source;
13447 struct raw_op *target = (struct raw_op *)_target;
13450 for (i = 0, j = 0; i < n/8; i++, j += 2) {
13451 tmp = be32_to_cpu(source[j]);
13452 target[i].op = (tmp >> 24) & 0xff;
13453 target[i].offset = tmp & 0xffffff;
13454 target[i].raw_data = be32_to_cpu(source[j + 1]);
13458 /* IRO array is stored in the following format:
13459 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13461 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13463 const __be32 *source = (const __be32 *)_source;
13464 struct iro *target = (struct iro *)_target;
13467 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13468 target[i].base = be32_to_cpu(source[j]);
13470 tmp = be32_to_cpu(source[j]);
13471 target[i].m1 = (tmp >> 16) & 0xffff;
13472 target[i].m2 = tmp & 0xffff;
13474 tmp = be32_to_cpu(source[j]);
13475 target[i].m3 = (tmp >> 16) & 0xffff;
13476 target[i].size = tmp & 0xffff;
13481 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13483 const __be16 *source = (const __be16 *)_source;
13484 u16 *target = (u16 *)_target;
13487 for (i = 0; i < n/2; i++)
13488 target[i] = be16_to_cpu(source[i]);
13491 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13493 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13494 bp->arr = kmalloc(len, GFP_KERNEL); \
13497 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13498 (u8 *)bp->arr, len); \
13501 static int bnx2x_init_firmware(struct bnx2x *bp)
13503 const char *fw_file_name;
13504 struct bnx2x_fw_file_hdr *fw_hdr;
13510 if (CHIP_IS_E1(bp))
13511 fw_file_name = FW_FILE_NAME_E1;
13512 else if (CHIP_IS_E1H(bp))
13513 fw_file_name = FW_FILE_NAME_E1H;
13514 else if (!CHIP_IS_E1x(bp))
13515 fw_file_name = FW_FILE_NAME_E2;
13517 BNX2X_ERR("Unsupported chip revision\n");
13520 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13522 rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13524 BNX2X_ERR("Can't load firmware file %s\n",
13526 goto request_firmware_exit;
13531 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13532 goto request_firmware_exit;
13535 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13537 /* Initialize the pointers to the init arrays */
13540 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13543 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13546 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13549 /* STORMs firmware */
13550 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13551 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13552 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13553 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13554 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13555 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13556 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13557 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13558 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13559 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13560 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13561 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13562 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13563 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13564 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13565 be32_to_cpu(fw_hdr->csem_pram_data.offset);
13567 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13572 kfree(bp->init_ops_offsets);
13573 init_offsets_alloc_err:
13574 kfree(bp->init_ops);
13575 init_ops_alloc_err:
13576 kfree(bp->init_data);
13577 request_firmware_exit:
13578 release_firmware(bp->firmware);
13579 bp->firmware = NULL;
13584 static void bnx2x_release_firmware(struct bnx2x *bp)
13586 kfree(bp->init_ops_offsets);
13587 kfree(bp->init_ops);
13588 kfree(bp->init_data);
13589 release_firmware(bp->firmware);
13590 bp->firmware = NULL;
13593 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13594 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13595 .init_hw_cmn = bnx2x_init_hw_common,
13596 .init_hw_port = bnx2x_init_hw_port,
13597 .init_hw_func = bnx2x_init_hw_func,
13599 .reset_hw_cmn = bnx2x_reset_common,
13600 .reset_hw_port = bnx2x_reset_port,
13601 .reset_hw_func = bnx2x_reset_func,
13603 .gunzip_init = bnx2x_gunzip_init,
13604 .gunzip_end = bnx2x_gunzip_end,
13606 .init_fw = bnx2x_init_firmware,
13607 .release_fw = bnx2x_release_firmware,
13610 void bnx2x__init_func_obj(struct bnx2x *bp)
13612 /* Prepare DMAE related driver resources */
13613 bnx2x_setup_dmae(bp);
13615 bnx2x_init_func_obj(bp, &bp->func_obj,
13616 bnx2x_sp(bp, func_rdata),
13617 bnx2x_sp_mapping(bp, func_rdata),
13618 bnx2x_sp(bp, func_afex_rdata),
13619 bnx2x_sp_mapping(bp, func_afex_rdata),
13620 &bnx2x_func_sp_drv);
13623 /* must be called after sriov-enable */
13624 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13626 int cid_count = BNX2X_L2_MAX_CID(bp);
13629 cid_count += BNX2X_VF_CIDS;
13631 if (CNIC_SUPPORT(bp))
13632 cid_count += CNIC_CID_MAX;
13634 return roundup(cid_count, QM_CID_ROUND);
13638 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13643 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13649 * If MSI-X is not supported - return number of SBs needed to support
13650 * one fast path queue: one FP queue + SB for CNIC
13652 if (!pdev->msix_cap) {
13653 dev_info(&pdev->dev, "no msix capability found\n");
13654 return 1 + cnic_cnt;
13656 dev_info(&pdev->dev, "msix capability found\n");
13659 * The value in the PCI configuration space is the index of the last
13660 * entry, namely one less than the actual size of the table, which is
13661 * exactly what we want to return from this function: number of all SBs
13662 * without the default SB.
13663 * For VFs there is no default SB, then we return (index+1).
13665 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13667 index = control & PCI_MSIX_FLAGS_QSIZE;
13672 static int set_max_cos_est(int chip_id)
13678 return BNX2X_MULTI_TX_COS_E1X;
13681 return BNX2X_MULTI_TX_COS_E2_E3A0;
13686 case BCM57840_4_10:
13687 case BCM57840_2_20:
13693 return BNX2X_MULTI_TX_COS_E3B0;
13701 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13706 static int set_is_vf(int chip_id)
13720 /* nig_tsgen registers relative address */
13721 #define tsgen_ctrl 0x0
13722 #define tsgen_freecount 0x10
13723 #define tsgen_synctime_t0 0x20
13724 #define tsgen_offset_t0 0x28
13725 #define tsgen_drift_t0 0x30
13726 #define tsgen_synctime_t1 0x58
13727 #define tsgen_offset_t1 0x60
13728 #define tsgen_drift_t1 0x68
13730 /* FW workaround for setting drift */
13731 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13732 int best_val, int best_period)
13734 struct bnx2x_func_state_params func_params = {NULL};
13735 struct bnx2x_func_set_timesync_params *set_timesync_params =
13736 &func_params.params.set_timesync;
13738 /* Prepare parameters for function state transitions */
13739 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13740 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13742 func_params.f_obj = &bp->func_obj;
13743 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13745 /* Function parameters */
13746 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13747 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13748 set_timesync_params->add_sub_drift_adjust_value =
13749 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13750 set_timesync_params->drift_adjust_value = best_val;
13751 set_timesync_params->drift_adjust_period = best_period;
13753 return bnx2x_func_state_change(bp, &func_params);
13756 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13758 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13761 int val, period, period1, period2, dif, dif1, dif2;
13762 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13764 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13766 if (!netif_running(bp->dev)) {
13768 "PTP adjfreq called while the interface is down\n");
13779 best_period = 0x1FFFFFF;
13780 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13784 /* Changed not to allow val = 8, 16, 24 as these values
13785 * are not supported in workaround.
13787 for (val = 0; val <= 31; val++) {
13788 if ((val & 0x7) == 0)
13790 period1 = val * 1000000 / ppb;
13791 period2 = period1 + 1;
13793 dif1 = ppb - (val * 1000000 / period1);
13795 dif1 = BNX2X_MAX_PHC_DRIFT;
13798 dif2 = ppb - (val * 1000000 / period2);
13801 dif = (dif1 < dif2) ? dif1 : dif2;
13802 period = (dif1 < dif2) ? period1 : period2;
13803 if (dif < best_dif) {
13806 best_period = period;
13811 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13814 BNX2X_ERR("Failed to set drift\n");
13818 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13824 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13826 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13828 if (!netif_running(bp->dev)) {
13830 "PTP adjtime called while the interface is down\n");
13834 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13836 timecounter_adjtime(&bp->timecounter, delta);
13841 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13843 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13846 if (!netif_running(bp->dev)) {
13848 "PTP gettime called while the interface is down\n");
13852 ns = timecounter_read(&bp->timecounter);
13854 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13856 *ts = ns_to_timespec64(ns);
13861 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13862 const struct timespec64 *ts)
13864 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13867 if (!netif_running(bp->dev)) {
13869 "PTP settime called while the interface is down\n");
13873 ns = timespec64_to_ns(ts);
13875 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13877 /* Re-init the timecounter */
13878 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13883 /* Enable (or disable) ancillary features of the phc subsystem */
13884 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13885 struct ptp_clock_request *rq, int on)
13887 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13889 BNX2X_ERR("PHC ancillary features are not supported\n");
13893 static void bnx2x_register_phc(struct bnx2x *bp)
13895 /* Fill the ptp_clock_info struct and register PTP clock*/
13896 bp->ptp_clock_info.owner = THIS_MODULE;
13897 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13898 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13899 bp->ptp_clock_info.n_alarm = 0;
13900 bp->ptp_clock_info.n_ext_ts = 0;
13901 bp->ptp_clock_info.n_per_out = 0;
13902 bp->ptp_clock_info.pps = 0;
13903 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13904 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13905 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13906 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13907 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13909 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13910 if (IS_ERR(bp->ptp_clock)) {
13911 bp->ptp_clock = NULL;
13912 BNX2X_ERR("PTP clock registeration failed\n");
13916 static int bnx2x_init_one(struct pci_dev *pdev,
13917 const struct pci_device_id *ent)
13919 struct net_device *dev = NULL;
13921 enum pcie_link_width pcie_width;
13922 enum pci_bus_speed pcie_speed;
13923 int rc, max_non_def_sbs;
13924 int rx_count, tx_count, rss_count, doorbell_size;
13929 /* Management FW 'remembers' living interfaces. Allow it some time
13930 * to forget previously living interfaces, allowing a proper re-load.
13932 if (is_kdump_kernel()) {
13933 ktime_t now = ktime_get_boottime();
13934 ktime_t fw_ready_time = ktime_set(5, 0);
13936 if (ktime_before(now, fw_ready_time))
13937 msleep(ktime_ms_delta(fw_ready_time, now));
13940 /* An estimated maximum supported CoS number according to the chip
13942 * We will try to roughly estimate the maximum number of CoSes this chip
13943 * may support in order to minimize the memory allocated for Tx
13944 * netdev_queue's. This number will be accurately calculated during the
13945 * initialization of bp->max_cos based on the chip versions AND chip
13946 * revision in the bnx2x_init_bp().
13948 max_cos_est = set_max_cos_est(ent->driver_data);
13949 if (max_cos_est < 0)
13950 return max_cos_est;
13951 is_vf = set_is_vf(ent->driver_data);
13952 cnic_cnt = is_vf ? 0 : 1;
13954 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13956 /* add another SB for VF as it has no default SB */
13957 max_non_def_sbs += is_vf ? 1 : 0;
13959 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13960 rss_count = max_non_def_sbs - cnic_cnt;
13965 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13966 rx_count = rss_count + cnic_cnt;
13968 /* Maximum number of netdev Tx queues:
13969 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13971 tx_count = rss_count * max_cos_est + cnic_cnt;
13973 /* dev zeroed in init_etherdev */
13974 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13978 bp = netdev_priv(dev);
13982 bp->flags |= IS_VF_FLAG;
13984 bp->igu_sb_cnt = max_non_def_sbs;
13985 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13986 bp->msg_enable = debug;
13987 bp->cnic_support = cnic_cnt;
13988 bp->cnic_probe = bnx2x_cnic_probe;
13990 pci_set_drvdata(pdev, dev);
13992 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13998 BNX2X_DEV_INFO("This is a %s function\n",
13999 IS_PF(bp) ? "physical" : "virtual");
14000 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
14001 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
14002 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
14003 tx_count, rx_count);
14005 rc = bnx2x_init_bp(bp);
14007 goto init_one_exit;
14009 /* Map doorbells here as we need the real value of bp->max_cos which
14010 * is initialized in bnx2x_init_bp() to determine the number of
14014 bp->doorbells = bnx2x_vf_doorbells(bp);
14015 rc = bnx2x_vf_pci_alloc(bp);
14017 goto init_one_freemem;
14019 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
14020 if (doorbell_size > pci_resource_len(pdev, 2)) {
14021 dev_err(&bp->pdev->dev,
14022 "Cannot map doorbells, bar size too small, aborting\n");
14024 goto init_one_freemem;
14026 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
14029 if (!bp->doorbells) {
14030 dev_err(&bp->pdev->dev,
14031 "Cannot map doorbell space, aborting\n");
14033 goto init_one_freemem;
14037 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
14039 goto init_one_freemem;
14041 #ifdef CONFIG_BNX2X_SRIOV
14042 /* VF with OLD Hypervisor or old PF do not support filtering */
14043 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
14044 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14045 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14050 /* Enable SRIOV if capability found in configuration space */
14051 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
14053 goto init_one_freemem;
14055 /* calc qm_cid_count */
14056 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
14057 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
14059 /* disable FCOE L2 queue for E1x*/
14060 if (CHIP_IS_E1x(bp))
14061 bp->flags |= NO_FCOE_FLAG;
14063 /* Set bp->num_queues for MSI-X mode*/
14064 bnx2x_set_num_queues(bp);
14066 /* Configure interrupt mode: try to enable MSI-X/MSI if
14069 rc = bnx2x_set_int_mode(bp);
14071 dev_err(&pdev->dev, "Cannot set interrupts\n");
14072 goto init_one_freemem;
14074 BNX2X_DEV_INFO("set interrupts successfully\n");
14076 /* register the net device */
14077 rc = register_netdev(dev);
14079 dev_err(&pdev->dev, "Cannot register net device\n");
14080 goto init_one_freemem;
14082 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
14084 if (!NO_FCOE(bp)) {
14085 /* Add storage MAC address */
14087 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14090 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
14091 pcie_speed == PCI_SPEED_UNKNOWN ||
14092 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
14093 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
14096 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
14097 board_info[ent->driver_data].name,
14098 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14100 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
14101 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
14102 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
14104 dev->base_addr, bp->pdev->irq, dev->dev_addr);
14106 bnx2x_register_phc(bp);
14108 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14109 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14114 bnx2x_free_mem_bp(bp);
14117 bnx2x_disable_pcie_error_reporting(bp);
14120 iounmap(bp->regview);
14122 if (IS_PF(bp) && bp->doorbells)
14123 iounmap(bp->doorbells);
14127 if (atomic_read(&pdev->enable_cnt) == 1)
14128 pci_release_regions(pdev);
14130 pci_disable_device(pdev);
14135 static void __bnx2x_remove(struct pci_dev *pdev,
14136 struct net_device *dev,
14138 bool remove_netdev)
14140 if (bp->ptp_clock) {
14141 ptp_clock_unregister(bp->ptp_clock);
14142 bp->ptp_clock = NULL;
14145 /* Delete storage MAC address */
14146 if (!NO_FCOE(bp)) {
14148 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14153 /* Delete app tlvs from dcbnl */
14154 bnx2x_dcbnl_update_applist(bp, true);
14159 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14160 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14162 /* Close the interface - either directly or implicitly */
14163 if (remove_netdev) {
14164 unregister_netdev(dev);
14171 bnx2x_iov_remove_one(bp);
14173 /* Power on: we can't let PCI layer write to us while we are in D3 */
14175 bnx2x_set_power_state(bp, PCI_D0);
14176 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14178 /* Set endianity registers to reset values in case next driver
14179 * boots in different endianty environment.
14181 bnx2x_reset_endianity(bp);
14184 /* Disable MSI/MSI-X */
14185 bnx2x_disable_msi(bp);
14189 bnx2x_set_power_state(bp, PCI_D3hot);
14191 /* Make sure RESET task is not scheduled before continuing */
14192 cancel_delayed_work_sync(&bp->sp_rtnl_task);
14194 /* send message via vfpf channel to release the resources of this vf */
14196 bnx2x_vfpf_release(bp);
14198 /* Assumes no further PCIe PM changes will occur */
14199 if (system_state == SYSTEM_POWER_OFF) {
14200 pci_wake_from_d3(pdev, bp->wol);
14201 pci_set_power_state(pdev, PCI_D3hot);
14204 bnx2x_disable_pcie_error_reporting(bp);
14205 if (remove_netdev) {
14207 iounmap(bp->regview);
14209 /* For vfs, doorbells are part of the regview and were unmapped
14210 * along with it. FW is only loaded by PF.
14214 iounmap(bp->doorbells);
14216 bnx2x_release_firmware(bp);
14218 bnx2x_vf_pci_dealloc(bp);
14220 bnx2x_free_mem_bp(bp);
14224 if (atomic_read(&pdev->enable_cnt) == 1)
14225 pci_release_regions(pdev);
14227 pci_disable_device(pdev);
14231 static void bnx2x_remove_one(struct pci_dev *pdev)
14233 struct net_device *dev = pci_get_drvdata(pdev);
14237 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14240 bp = netdev_priv(dev);
14242 __bnx2x_remove(pdev, dev, bp, true);
14245 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14247 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14249 bp->rx_mode = BNX2X_RX_MODE_NONE;
14251 if (CNIC_LOADED(bp))
14252 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14255 bnx2x_tx_disable(bp);
14256 /* Delete all NAPI objects */
14257 bnx2x_del_all_napi(bp);
14258 if (CNIC_LOADED(bp))
14259 bnx2x_del_all_napi_cnic(bp);
14260 netdev_reset_tc(bp->dev);
14262 del_timer_sync(&bp->timer);
14263 cancel_delayed_work_sync(&bp->sp_task);
14264 cancel_delayed_work_sync(&bp->period_task);
14266 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14267 bp->stats_state = STATS_STATE_DISABLED;
14268 up(&bp->stats_lock);
14271 bnx2x_save_statistics(bp);
14273 netif_carrier_off(bp->dev);
14279 * bnx2x_io_error_detected - called when PCI error is detected
14280 * @pdev: Pointer to PCI device
14281 * @state: The current pci connection state
14283 * This function is called after a PCI bus error affecting
14284 * this device has been detected.
14286 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14287 pci_channel_state_t state)
14289 struct net_device *dev = pci_get_drvdata(pdev);
14290 struct bnx2x *bp = netdev_priv(dev);
14294 BNX2X_ERR("IO error detected\n");
14296 netif_device_detach(dev);
14298 if (state == pci_channel_io_perm_failure) {
14300 return PCI_ERS_RESULT_DISCONNECT;
14303 if (netif_running(dev))
14304 bnx2x_eeh_nic_unload(bp);
14306 bnx2x_prev_path_mark_eeh(bp);
14308 pci_disable_device(pdev);
14312 /* Request a slot reset */
14313 return PCI_ERS_RESULT_NEED_RESET;
14317 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14318 * @pdev: Pointer to PCI device
14320 * Restart the card from scratch, as if from a cold-boot.
14322 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14324 struct net_device *dev = pci_get_drvdata(pdev);
14325 struct bnx2x *bp = netdev_priv(dev);
14329 BNX2X_ERR("IO slot reset initializing...\n");
14330 if (pci_enable_device(pdev)) {
14331 dev_err(&pdev->dev,
14332 "Cannot re-enable PCI device after reset\n");
14334 return PCI_ERS_RESULT_DISCONNECT;
14337 pci_set_master(pdev);
14338 pci_restore_state(pdev);
14339 pci_save_state(pdev);
14341 if (netif_running(dev))
14342 bnx2x_set_power_state(bp, PCI_D0);
14344 if (netif_running(dev)) {
14345 BNX2X_ERR("IO slot reset --> driver unload\n");
14347 /* MCP should have been reset; Need to wait for validity */
14348 if (bnx2x_init_shmem(bp)) {
14350 return PCI_ERS_RESULT_DISCONNECT;
14353 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14357 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14358 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14359 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14361 bnx2x_drain_tx_queues(bp);
14362 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14363 bnx2x_netif_stop(bp, 1);
14364 bnx2x_free_irq(bp);
14366 /* Report UNLOAD_DONE to MCP */
14367 bnx2x_send_unload_done(bp, true);
14372 bnx2x_prev_unload(bp);
14374 /* We should have reseted the engine, so It's fair to
14375 * assume the FW will no longer write to the bnx2x driver.
14377 bnx2x_squeeze_objects(bp);
14378 bnx2x_free_skbs(bp);
14379 for_each_rx_queue(bp, i)
14380 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14381 bnx2x_free_fp_mem(bp);
14382 bnx2x_free_mem(bp);
14384 bp->state = BNX2X_STATE_CLOSED;
14389 /* If AER, perform cleanup of the PCIe registers */
14390 if (bp->flags & AER_ENABLED) {
14391 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14392 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14394 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14397 return PCI_ERS_RESULT_RECOVERED;
14401 * bnx2x_io_resume - called when traffic can start flowing again
14402 * @pdev: Pointer to PCI device
14404 * This callback is called when the error recovery driver tells us that
14405 * its OK to resume normal operation.
14407 static void bnx2x_io_resume(struct pci_dev *pdev)
14409 struct net_device *dev = pci_get_drvdata(pdev);
14410 struct bnx2x *bp = netdev_priv(dev);
14412 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14413 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14419 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14420 DRV_MSG_SEQ_NUMBER_MASK;
14422 if (netif_running(dev))
14423 bnx2x_nic_load(bp, LOAD_NORMAL);
14425 netif_device_attach(dev);
14430 static const struct pci_error_handlers bnx2x_err_handler = {
14431 .error_detected = bnx2x_io_error_detected,
14432 .slot_reset = bnx2x_io_slot_reset,
14433 .resume = bnx2x_io_resume,
14436 static void bnx2x_shutdown(struct pci_dev *pdev)
14438 struct net_device *dev = pci_get_drvdata(pdev);
14444 bp = netdev_priv(dev);
14449 netif_device_detach(dev);
14452 /* Don't remove the netdevice, as there are scenarios which will cause
14453 * the kernel to hang, e.g., when trying to remove bnx2i while the
14454 * rootfs is mounted from SAN.
14456 __bnx2x_remove(pdev, dev, bp, false);
14459 static struct pci_driver bnx2x_pci_driver = {
14460 .name = DRV_MODULE_NAME,
14461 .id_table = bnx2x_pci_tbl,
14462 .probe = bnx2x_init_one,
14463 .remove = bnx2x_remove_one,
14464 .suspend = bnx2x_suspend,
14465 .resume = bnx2x_resume,
14466 .err_handler = &bnx2x_err_handler,
14467 #ifdef CONFIG_BNX2X_SRIOV
14468 .sriov_configure = bnx2x_sriov_configure,
14470 .shutdown = bnx2x_shutdown,
14473 static int __init bnx2x_init(void)
14477 pr_info("%s", version);
14479 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14480 if (bnx2x_wq == NULL) {
14481 pr_err("Cannot create workqueue\n");
14484 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14485 if (!bnx2x_iov_wq) {
14486 pr_err("Cannot create iov workqueue\n");
14487 destroy_workqueue(bnx2x_wq);
14491 ret = pci_register_driver(&bnx2x_pci_driver);
14493 pr_err("Cannot register driver\n");
14494 destroy_workqueue(bnx2x_wq);
14495 destroy_workqueue(bnx2x_iov_wq);
14500 static void __exit bnx2x_cleanup(void)
14502 struct list_head *pos, *q;
14504 pci_unregister_driver(&bnx2x_pci_driver);
14506 destroy_workqueue(bnx2x_wq);
14507 destroy_workqueue(bnx2x_iov_wq);
14509 /* Free globally allocated resources */
14510 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14511 struct bnx2x_prev_path_list *tmp =
14512 list_entry(pos, struct bnx2x_prev_path_list, list);
14518 void bnx2x_notify_link_changed(struct bnx2x *bp)
14520 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14523 module_init(bnx2x_init);
14524 module_exit(bnx2x_cleanup);
14527 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14529 * @bp: driver handle
14530 * @set: set or clear the CAM entry
14532 * This function will wait until the ramrod completion returns.
14533 * Return 0 if success, -ENODEV if ramrod doesn't return.
14535 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14537 unsigned long ramrod_flags = 0;
14539 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14540 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14541 &bp->iscsi_l2_mac_obj, true,
14542 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14545 /* count denotes the number of new completions we have seen */
14546 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14548 struct eth_spe *spe;
14549 int cxt_index, cxt_offset;
14551 #ifdef BNX2X_STOP_ON_ERROR
14552 if (unlikely(bp->panic))
14556 spin_lock_bh(&bp->spq_lock);
14557 BUG_ON(bp->cnic_spq_pending < count);
14558 bp->cnic_spq_pending -= count;
14560 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14561 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14562 & SPE_HDR_CONN_TYPE) >>
14563 SPE_HDR_CONN_TYPE_SHIFT;
14564 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14565 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14567 /* Set validation for iSCSI L2 client before sending SETUP
14570 if (type == ETH_CONNECTION_TYPE) {
14571 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14572 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14574 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14575 (cxt_index * ILT_PAGE_CIDS);
14576 bnx2x_set_ctx_validation(bp,
14577 &bp->context[cxt_index].
14578 vcxt[cxt_offset].eth,
14579 BNX2X_ISCSI_ETH_CID(bp));
14584 * There may be not more than 8 L2, not more than 8 L5 SPEs
14585 * and in the air. We also check that number of outstanding
14586 * COMMON ramrods is not more than the EQ and SPQ can
14589 if (type == ETH_CONNECTION_TYPE) {
14590 if (!atomic_read(&bp->cq_spq_left))
14593 atomic_dec(&bp->cq_spq_left);
14594 } else if (type == NONE_CONNECTION_TYPE) {
14595 if (!atomic_read(&bp->eq_spq_left))
14598 atomic_dec(&bp->eq_spq_left);
14599 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14600 (type == FCOE_CONNECTION_TYPE)) {
14601 if (bp->cnic_spq_pending >=
14602 bp->cnic_eth_dev.max_kwqe_pending)
14605 bp->cnic_spq_pending++;
14607 BNX2X_ERR("Unknown SPE type: %d\n", type);
14612 spe = bnx2x_sp_get_next(bp);
14613 *spe = *bp->cnic_kwq_cons;
14615 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14616 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14618 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14619 bp->cnic_kwq_cons = bp->cnic_kwq;
14621 bp->cnic_kwq_cons++;
14623 bnx2x_sp_prod_update(bp);
14624 spin_unlock_bh(&bp->spq_lock);
14627 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14628 struct kwqe_16 *kwqes[], u32 count)
14630 struct bnx2x *bp = netdev_priv(dev);
14633 #ifdef BNX2X_STOP_ON_ERROR
14634 if (unlikely(bp->panic)) {
14635 BNX2X_ERR("Can't post to SP queue while panic\n");
14640 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14641 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14642 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14646 spin_lock_bh(&bp->spq_lock);
14648 for (i = 0; i < count; i++) {
14649 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14651 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14654 *bp->cnic_kwq_prod = *spe;
14656 bp->cnic_kwq_pending++;
14658 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14659 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14660 spe->data.update_data_addr.hi,
14661 spe->data.update_data_addr.lo,
14662 bp->cnic_kwq_pending);
14664 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14665 bp->cnic_kwq_prod = bp->cnic_kwq;
14667 bp->cnic_kwq_prod++;
14670 spin_unlock_bh(&bp->spq_lock);
14672 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14673 bnx2x_cnic_sp_post(bp, 0);
14678 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14680 struct cnic_ops *c_ops;
14683 mutex_lock(&bp->cnic_mutex);
14684 c_ops = rcu_dereference_protected(bp->cnic_ops,
14685 lockdep_is_held(&bp->cnic_mutex));
14687 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14688 mutex_unlock(&bp->cnic_mutex);
14693 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14695 struct cnic_ops *c_ops;
14699 c_ops = rcu_dereference(bp->cnic_ops);
14701 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14708 * for commands that have no data
14710 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14712 struct cnic_ctl_info ctl = {0};
14716 return bnx2x_cnic_ctl_send(bp, &ctl);
14719 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14721 struct cnic_ctl_info ctl = {0};
14723 /* first we tell CNIC and only then we count this as a completion */
14724 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14725 ctl.data.comp.cid = cid;
14726 ctl.data.comp.error = err;
14728 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14729 bnx2x_cnic_sp_post(bp, 0);
14732 /* Called with netif_addr_lock_bh() taken.
14733 * Sets an rx_mode config for an iSCSI ETH client.
14735 * Completion should be checked outside.
14737 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14739 unsigned long accept_flags = 0, ramrod_flags = 0;
14740 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14741 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14744 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14745 * because it's the only way for UIO Queue to accept
14746 * multicasts (in non-promiscuous mode only one Queue per
14747 * function will receive multicast packets (leading in our
14750 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14751 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14752 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14753 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14755 /* Clear STOP_PENDING bit if START is requested */
14756 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14758 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14760 /* Clear START_PENDING bit if STOP is requested */
14761 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14763 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14764 set_bit(sched_state, &bp->sp_state);
14766 __set_bit(RAMROD_RX, &ramrod_flags);
14767 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14772 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14774 struct bnx2x *bp = netdev_priv(dev);
14777 switch (ctl->cmd) {
14778 case DRV_CTL_CTXTBL_WR_CMD: {
14779 u32 index = ctl->data.io.offset;
14780 dma_addr_t addr = ctl->data.io.dma_addr;
14782 bnx2x_ilt_wr(bp, index, addr);
14786 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14787 int count = ctl->data.credit.credit_count;
14789 bnx2x_cnic_sp_post(bp, count);
14793 /* rtnl_lock is held. */
14794 case DRV_CTL_START_L2_CMD: {
14795 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14796 unsigned long sp_bits = 0;
14798 /* Configure the iSCSI classification object */
14799 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14800 cp->iscsi_l2_client_id,
14801 cp->iscsi_l2_cid, BP_FUNC(bp),
14802 bnx2x_sp(bp, mac_rdata),
14803 bnx2x_sp_mapping(bp, mac_rdata),
14804 BNX2X_FILTER_MAC_PENDING,
14805 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14808 /* Set iSCSI MAC address */
14809 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14816 /* Start accepting on iSCSI L2 ring */
14818 netif_addr_lock_bh(dev);
14819 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14820 netif_addr_unlock_bh(dev);
14822 /* bits to wait on */
14823 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14824 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14826 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14827 BNX2X_ERR("rx_mode completion timed out!\n");
14832 /* rtnl_lock is held. */
14833 case DRV_CTL_STOP_L2_CMD: {
14834 unsigned long sp_bits = 0;
14836 /* Stop accepting on iSCSI L2 ring */
14837 netif_addr_lock_bh(dev);
14838 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14839 netif_addr_unlock_bh(dev);
14841 /* bits to wait on */
14842 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14843 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14845 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14846 BNX2X_ERR("rx_mode completion timed out!\n");
14851 /* Unset iSCSI L2 MAC */
14852 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14853 BNX2X_ISCSI_ETH_MAC, true);
14856 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14857 int count = ctl->data.credit.credit_count;
14859 smp_mb__before_atomic();
14860 atomic_add(count, &bp->cq_spq_left);
14861 smp_mb__after_atomic();
14864 case DRV_CTL_ULP_REGISTER_CMD: {
14865 int ulp_type = ctl->data.register_data.ulp_type;
14867 if (CHIP_IS_E3(bp)) {
14868 int idx = BP_FW_MB_IDX(bp);
14869 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14870 int path = BP_PATH(bp);
14871 int port = BP_PORT(bp);
14873 u32 scratch_offset;
14876 /* first write capability to shmem2 */
14877 if (ulp_type == CNIC_ULP_ISCSI)
14878 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14879 else if (ulp_type == CNIC_ULP_FCOE)
14880 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14881 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14883 if ((ulp_type != CNIC_ULP_FCOE) ||
14884 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14885 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14888 /* if reached here - should write fcoe capabilities */
14889 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14890 if (!scratch_offset)
14892 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14893 fcoe_features[path][port]);
14894 host_addr = (u32 *) &(ctl->data.register_data.
14896 for (i = 0; i < sizeof(struct fcoe_capabilities);
14898 REG_WR(bp, scratch_offset + i,
14899 *(host_addr + i/4));
14901 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14905 case DRV_CTL_ULP_UNREGISTER_CMD: {
14906 int ulp_type = ctl->data.ulp_type;
14908 if (CHIP_IS_E3(bp)) {
14909 int idx = BP_FW_MB_IDX(bp);
14912 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14913 if (ulp_type == CNIC_ULP_ISCSI)
14914 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14915 else if (ulp_type == CNIC_ULP_FCOE)
14916 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14917 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14919 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14924 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14928 /* For storage-only interfaces, change driver state */
14929 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14930 switch (ctl->drv_state) {
14934 bnx2x_set_os_driver_state(bp,
14935 OS_DRIVER_STATE_ACTIVE);
14938 bnx2x_set_os_driver_state(bp,
14939 OS_DRIVER_STATE_DISABLED);
14942 bnx2x_set_os_driver_state(bp,
14943 OS_DRIVER_STATE_NOT_LOADED);
14946 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14953 static int bnx2x_get_fc_npiv(struct net_device *dev,
14954 struct cnic_fc_npiv_tbl *cnic_tbl)
14956 struct bnx2x *bp = netdev_priv(dev);
14957 struct bdn_fc_npiv_tbl *tbl = NULL;
14958 u32 offset, entries;
14962 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14965 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14967 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14969 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14973 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14975 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14978 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14980 /* Read the table contents from nvram */
14981 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14982 BNX2X_ERR("Failed to read FC-NPIV table\n");
14986 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14987 * the number of entries back to cpu endianness.
14989 entries = tbl->fc_npiv_cfg.num_of_npiv;
14990 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14991 tbl->fc_npiv_cfg.num_of_npiv = entries;
14993 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14995 "No FC-NPIV table [valid, simply not present]\n");
14997 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14998 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14999 tbl->fc_npiv_cfg.num_of_npiv);
15002 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
15003 tbl->fc_npiv_cfg.num_of_npiv);
15006 /* Copy the data into cnic-provided struct */
15007 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
15008 for (i = 0; i < cnic_tbl->count; i++) {
15009 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
15010 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
15019 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
15021 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15023 if (bp->flags & USING_MSIX_FLAG) {
15024 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
15025 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
15026 cp->irq_arr[0].vector = bp->msix_table[1].vector;
15028 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
15029 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
15031 if (!CHIP_IS_E1x(bp))
15032 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
15034 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
15036 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
15037 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
15038 cp->irq_arr[1].status_blk = bp->def_status_blk;
15039 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
15040 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
15045 void bnx2x_setup_cnic_info(struct bnx2x *bp)
15047 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15049 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15050 bnx2x_cid_ilt_lines(bp);
15051 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15052 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15053 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15055 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
15056 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
15059 if (NO_ISCSI_OOO(bp))
15060 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15063 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
15066 struct bnx2x *bp = netdev_priv(dev);
15067 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15070 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
15073 BNX2X_ERR("NULL ops received\n");
15077 if (!CNIC_SUPPORT(bp)) {
15078 BNX2X_ERR("Can't register CNIC when not supported\n");
15079 return -EOPNOTSUPP;
15082 if (!CNIC_LOADED(bp)) {
15083 rc = bnx2x_load_cnic(bp);
15085 BNX2X_ERR("CNIC-related load failed\n");
15090 bp->cnic_enabled = true;
15092 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15096 bp->cnic_kwq_cons = bp->cnic_kwq;
15097 bp->cnic_kwq_prod = bp->cnic_kwq;
15098 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15100 bp->cnic_spq_pending = 0;
15101 bp->cnic_kwq_pending = 0;
15103 bp->cnic_data = data;
15106 cp->drv_state |= CNIC_DRV_STATE_REGD;
15107 cp->iro_arr = bp->iro_arr;
15109 bnx2x_setup_cnic_irq_info(bp);
15111 rcu_assign_pointer(bp->cnic_ops, ops);
15113 /* Schedule driver to read CNIC driver versions */
15114 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15119 static int bnx2x_unregister_cnic(struct net_device *dev)
15121 struct bnx2x *bp = netdev_priv(dev);
15122 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15124 mutex_lock(&bp->cnic_mutex);
15126 RCU_INIT_POINTER(bp->cnic_ops, NULL);
15127 mutex_unlock(&bp->cnic_mutex);
15129 bp->cnic_enabled = false;
15130 kfree(bp->cnic_kwq);
15131 bp->cnic_kwq = NULL;
15136 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
15138 struct bnx2x *bp = netdev_priv(dev);
15139 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15141 /* If both iSCSI and FCoE are disabled - return NULL in
15142 * order to indicate CNIC that it should not try to work
15143 * with this device.
15145 if (NO_ISCSI(bp) && NO_FCOE(bp))
15148 cp->drv_owner = THIS_MODULE;
15149 cp->chip_id = CHIP_ID(bp);
15150 cp->pdev = bp->pdev;
15151 cp->io_base = bp->regview;
15152 cp->io_base2 = bp->doorbells;
15153 cp->max_kwqe_pending = 8;
15154 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15155 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15156 bnx2x_cid_ilt_lines(bp);
15157 cp->ctx_tbl_len = CNIC_ILT_LINES;
15158 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15159 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15160 cp->drv_ctl = bnx2x_drv_ctl;
15161 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15162 cp->drv_register_cnic = bnx2x_register_cnic;
15163 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15164 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15165 cp->iscsi_l2_client_id =
15166 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15167 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15169 if (NO_ISCSI_OOO(bp))
15170 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15173 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15176 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15179 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15181 cp->ctx_tbl_offset,
15187 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15189 struct bnx2x *bp = fp->bp;
15190 u32 offset = BAR_USTRORM_INTMEM;
15193 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15194 else if (!CHIP_IS_E1x(bp))
15195 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15197 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15202 /* called only on E1H or E2.
15203 * When pretending to be PF, the pretend value is the function number 0...7
15204 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15207 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15211 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15214 /* get my own pretend register */
15215 pretend_reg = bnx2x_get_pretend_reg(bp);
15216 REG_WR(bp, pretend_reg, pretend_func_val);
15217 REG_RD(bp, pretend_reg);
15221 static void bnx2x_ptp_task(struct work_struct *work)
15223 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15224 int port = BP_PORT(bp);
15227 struct skb_shared_hwtstamps shhwtstamps;
15231 /* FW may take a while to complete timestamping; try a bit and if it's
15232 * still not complete, may indicate an error state - bail out then.
15234 for (i = 0; i < 10; i++) {
15235 /* Read Tx timestamp registers */
15236 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15237 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15238 if (val_seq & 0x10000) {
15246 /* There is a valid timestamp value */
15247 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15248 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15250 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15251 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15252 /* Reset timestamp register to allow new timestamp */
15253 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15254 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15255 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15257 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15258 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15259 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15261 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15265 "Tx timestamp is not recorded (register read=%u)\n",
15267 bp->eth_stats.ptp_skip_tx_ts++;
15270 dev_kfree_skb_any(bp->ptp_tx_skb);
15271 bp->ptp_tx_skb = NULL;
15274 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15276 int port = BP_PORT(bp);
15279 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15280 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15282 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15283 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15285 /* Reset timestamp register to allow new timestamp */
15286 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15287 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15289 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15291 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15293 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15298 static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15300 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15301 int port = BP_PORT(bp);
15305 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15306 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15307 phc_cycles = wb_data[1];
15308 phc_cycles = (phc_cycles << 32) + wb_data[0];
15310 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15315 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15317 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15318 bp->cyclecounter.read = bnx2x_cyclecounter_read;
15319 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15320 bp->cyclecounter.shift = 0;
15321 bp->cyclecounter.mult = 1;
15324 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15326 struct bnx2x_func_state_params func_params = {NULL};
15327 struct bnx2x_func_set_timesync_params *set_timesync_params =
15328 &func_params.params.set_timesync;
15330 /* Prepare parameters for function state transitions */
15331 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15332 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15334 func_params.f_obj = &bp->func_obj;
15335 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15337 /* Function parameters */
15338 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15339 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15341 return bnx2x_func_state_change(bp, &func_params);
15344 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15346 struct bnx2x_queue_state_params q_params;
15349 /* send queue update ramrod to enable PTP packets */
15350 memset(&q_params, 0, sizeof(q_params));
15351 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15352 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15353 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15354 &q_params.params.update.update_flags);
15355 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15356 &q_params.params.update.update_flags);
15358 /* send the ramrod on all the queues of the PF */
15359 for_each_eth_queue(bp, i) {
15360 struct bnx2x_fastpath *fp = &bp->fp[i];
15362 /* Set the appropriate Queue object */
15363 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15365 /* Update the Queue state */
15366 rc = bnx2x_queue_state_change(bp, &q_params);
15368 BNX2X_ERR("Failed to enable PTP packets\n");
15376 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15378 int port = BP_PORT(bp);
15381 if (!bp->hwtstamp_ioctl_called)
15384 switch (bp->tx_type) {
15385 case HWTSTAMP_TX_ON:
15386 bp->flags |= TX_TIMESTAMPING_EN;
15387 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15388 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15389 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15390 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15392 case HWTSTAMP_TX_ONESTEP_SYNC:
15393 BNX2X_ERR("One-step timestamping is not supported\n");
15397 switch (bp->rx_filter) {
15398 case HWTSTAMP_FILTER_NONE:
15400 case HWTSTAMP_FILTER_ALL:
15401 case HWTSTAMP_FILTER_SOME:
15402 case HWTSTAMP_FILTER_NTP_ALL:
15403 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15405 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15406 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15407 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15408 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15409 /* Initialize PTP detection for UDP/IPv4 events */
15410 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15411 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15412 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15413 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15415 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15416 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15417 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15418 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15419 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15420 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15421 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15422 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15423 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15425 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15426 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15427 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15428 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15429 /* Initialize PTP detection L2 events */
15430 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15431 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15432 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15433 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15436 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15437 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15438 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15439 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15440 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15441 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15442 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15443 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15444 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15448 /* Indicate to FW that this PF expects recorded PTP packets */
15449 rc = bnx2x_enable_ptp_packets(bp);
15453 /* Enable sending PTP packets to host */
15454 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15455 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15460 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15462 struct hwtstamp_config config;
15465 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15467 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15470 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15471 config.tx_type, config.rx_filter);
15473 if (config.flags) {
15474 BNX2X_ERR("config.flags is reserved for future use\n");
15478 bp->hwtstamp_ioctl_called = 1;
15479 bp->tx_type = config.tx_type;
15480 bp->rx_filter = config.rx_filter;
15482 rc = bnx2x_configure_ptp_filters(bp);
15486 config.rx_filter = bp->rx_filter;
15488 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15492 /* Configures HW for PTP */
15493 static int bnx2x_configure_ptp(struct bnx2x *bp)
15495 int rc, port = BP_PORT(bp);
15498 /* Reset PTP event detection rules - will be configured in the IOCTL */
15499 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15500 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15501 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15502 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15503 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15504 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15505 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15506 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15508 /* Disable PTP packets to host - will be configured in the IOCTL*/
15509 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15510 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15512 /* Enable the PTP feature */
15513 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15514 NIG_REG_P0_PTP_EN, 0x3F);
15516 /* Enable the free-running counter */
15519 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15521 /* Reset drift register (offset register is not reset) */
15522 rc = bnx2x_send_reset_timesync_ramrod(bp);
15524 BNX2X_ERR("Failed to reset PHC drift register\n");
15528 /* Reset possibly old timestamps */
15529 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15530 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15531 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15532 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15537 /* Called during load, to initialize PTP-related stuff */
15538 void bnx2x_init_ptp(struct bnx2x *bp)
15542 /* Configure PTP in HW */
15543 rc = bnx2x_configure_ptp(bp);
15545 BNX2X_ERR("Stopping PTP initialization\n");
15549 /* Init work queue for Tx timestamping */
15550 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15552 /* Init cyclecounter and timecounter. This is done only in the first
15553 * load. If done in every load, PTP application will fail when doing
15554 * unload / load (e.g. MTU change) while it is running.
15556 if (!bp->timecounter_init_done) {
15557 bnx2x_init_cyclecounter(bp);
15558 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15559 ktime_to_ns(ktime_get_real()));
15560 bp->timecounter_init_done = 1;
15563 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");