drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/ethtool.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/types.h>
  25 #include <linux/sched.h>
  26 #include <linux/crc32.h>
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29 #include "bnx2x_dump.h"
  30 #include "bnx2x_init.h"
  31
  32 /* Note: in the format strings below %s is replaced by the queue-name which is
  33  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  34  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  35  */
  36 #define MAX_QUEUE_NAME_LEN      4
  37 static const struct {
  38         long offset;
  39         int size;
  40         char string[ETH_GSTRING_LEN];
  41 } bnx2x_q_stats_arr[] = {
  42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  43         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  44                                                 8, "[%s]: rx_ucast_packets" },
  45         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  46                                                 8, "[%s]: rx_mcast_packets" },
  47         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  48                                                 8, "[%s]: rx_bcast_packets" },
  49         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  50         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  51                                          4, "[%s]: rx_phy_ip_err_discards"},
  52         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  53                                          4, "[%s]: rx_skb_alloc_discard" },
  54         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  55
  56         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_ucast_packets" },
  59         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_mcast_packets" },
  61         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  62                                                 8, "[%s]: tx_bcast_packets" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  64                                                 8, "[%s]: tpa_aggregations" },
  65         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  66                                         8, "[%s]: tpa_aggregated_frames"},
  67         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  68         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  69                                         4, "[%s]: driver_filtered_tx_pkt" }
  70 };
  71
  72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  73
  74 static const struct {
  75         long offset;
  76         int size;
  77         u32 flags;
  78 #define STATS_FLAGS_PORT                1
  79 #define STATS_FLAGS_FUNC                2
  80 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  81         char string[ETH_GSTRING_LEN];
  82 } bnx2x_stats_arr[] = {
  83 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  85         { STATS_OFFSET32(error_bytes_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  87         { STATS_OFFSET32(total_unicast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  89         { STATS_OFFSET32(total_multicast_packets_received_hi),
  90                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  91         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  92                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  93         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  95         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  97         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  99         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
 101 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 102                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 103         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 104                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 105         { STATS_OFFSET32(no_buff_discard_hi),
 106                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 107         { STATS_OFFSET32(mac_filter_discard),
 108                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 109         { STATS_OFFSET32(mf_tag_discard),
 110                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 111         { STATS_OFFSET32(pfc_frames_received_hi),
 112                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 113         { STATS_OFFSET32(pfc_frames_sent_hi),
 114                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 115         { STATS_OFFSET32(brb_drop_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 117         { STATS_OFFSET32(brb_truncate_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 119         { STATS_OFFSET32(pause_frames_received_hi),
 120                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 121         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 122                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 123         { STATS_OFFSET32(nig_timer_max),
 124                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 125 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 126                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 127         { STATS_OFFSET32(rx_skb_alloc_failed),
 128                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 129         { STATS_OFFSET32(hw_csum_err),
 130                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 131
 132         { STATS_OFFSET32(total_bytes_transmitted_hi),
 133                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 134         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 135                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 136         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 138         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 139                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 140         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 141                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 142         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 144         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 146 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 150         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 152         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 154         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 157                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 159                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 164         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 166 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 168         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 169                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 170         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 171                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 172         { STATS_OFFSET32(pause_frames_sent_hi),
 173                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 174         { STATS_OFFSET32(total_tpa_aggregations_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 176         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 177                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 178         { STATS_OFFSET32(total_tpa_bytes_hi),
 179                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 180         { STATS_OFFSET32(recoverable_error),
 181                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 182         { STATS_OFFSET32(unrecoverable_error),
 183                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 184         { STATS_OFFSET32(driver_filtered_tx_pkt),
 185                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
 186         { STATS_OFFSET32(eee_tx_lpi),
 187                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 188 };
 189
 190 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 191
 192 static int bnx2x_get_port_type(struct bnx2x *bp)
 193 {
 194         int port_type;
 195         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 196         switch (bp->link_params.phy[phy_idx].media_type) {
 197         case ETH_PHY_SFPP_10G_FIBER:
 198         case ETH_PHY_SFP_1G_FIBER:
 199         case ETH_PHY_XFP_FIBER:
 200         case ETH_PHY_KR:
 201         case ETH_PHY_CX4:
 202                 port_type = PORT_FIBRE;
 203                 break;
 204         case ETH_PHY_DA_TWINAX:
 205                 port_type = PORT_DA;
 206                 break;
 207         case ETH_PHY_BASE_T:
 208                 port_type = PORT_TP;
 209                 break;
 210         case ETH_PHY_NOT_PRESENT:
 211                 port_type = PORT_NONE;
 212                 break;
 213         case ETH_PHY_UNSPECIFIED:
 214         default:
 215                 port_type = PORT_OTHER;
 216                 break;
 217         }
 218         return port_type;
 219 }
 220
 221 static int bnx2x_get_vf_settings(struct net_device *dev,
 222                                  struct ethtool_cmd *cmd)
 223 {
 224         struct bnx2x *bp = netdev_priv(dev);
 225
 226         if (bp->state == BNX2X_STATE_OPEN) {
 227                 if (test_bit(BNX2X_LINK_REPORT_FD,
 228                              &bp->vf_link_vars.link_report_flags))
 229                         cmd->duplex = DUPLEX_FULL;
 230                 else
 231                         cmd->duplex = DUPLEX_HALF;
 232
 233                 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
 234         } else {
 235                 cmd->duplex = DUPLEX_UNKNOWN;
 236                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 237         }
 238
 239         cmd->port               = PORT_OTHER;
 240         cmd->phy_address        = 0;
 241         cmd->transceiver        = XCVR_INTERNAL;
 242         cmd->autoneg            = AUTONEG_DISABLE;
 243         cmd->maxtxpkt           = 0;
 244         cmd->maxrxpkt           = 0;
 245
 246         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 247            "  supported 0x%x  advertising 0x%x  speed %u\n"
 248            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 249            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 250            cmd->cmd, cmd->supported, cmd->advertising,
 251            ethtool_cmd_speed(cmd),
 252            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 253            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 254
 255         return 0;
 256 }
 257
 258 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 259 {
 260         struct bnx2x *bp = netdev_priv(dev);
 261         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 262         u32 media_type;
 263
 264         /* Dual Media boards present all available port types */
 265         cmd->supported = bp->port.supported[cfg_idx] |
 266                 (bp->port.supported[cfg_idx ^ 1] &
 267                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 268         cmd->advertising = bp->port.advertising[cfg_idx];
 269         media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
 270         if (media_type == ETH_PHY_SFP_1G_FIBER) {
 271                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 272                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 273         }
 274
 275         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 276             !(bp->flags & MF_FUNC_DIS)) {
 277                 cmd->duplex = bp->link_vars.duplex;
 278
 279                 if (IS_MF(bp) && !BP_NOMCP(bp))
 280                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 281                 else
 282                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 283         } else {
 284                 cmd->duplex = DUPLEX_UNKNOWN;
 285                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 286         }
 287
 288         cmd->port = bnx2x_get_port_type(bp);
 289
 290         cmd->phy_address = bp->mdio.prtad;
 291         cmd->transceiver = XCVR_INTERNAL;
 292
 293         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 294                 cmd->autoneg = AUTONEG_ENABLE;
 295         else
 296                 cmd->autoneg = AUTONEG_DISABLE;
 297
 298         /* Publish LP advertised speeds and FC */
 299         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 300                 u32 status = bp->link_vars.link_status;
 301
 302                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 303                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 304                         cmd->lp_advertising |= ADVERTISED_Pause;
 305                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 306                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 307
 308                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 309                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 310                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 311                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 312                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 313                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 314                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 315                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 316                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 317                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 318                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
 319                         if (media_type == ETH_PHY_KR) {
 320                                 cmd->lp_advertising |=
 321                                         ADVERTISED_1000baseKX_Full;
 322                         } else {
 323                                 cmd->lp_advertising |=
 324                                         ADVERTISED_1000baseT_Full;
 325                         }
 326                 }
 327                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 328                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 329                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
 330                         if (media_type == ETH_PHY_KR) {
 331                                 cmd->lp_advertising |=
 332                                         ADVERTISED_10000baseKR_Full;
 333                         } else {
 334                                 cmd->lp_advertising |=
 335                                         ADVERTISED_10000baseT_Full;
 336                         }
 337                 }
 338                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 339                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
 340         }
 341
 342         cmd->maxtxpkt = 0;
 343         cmd->maxrxpkt = 0;
 344
 345         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 346            "  supported 0x%x  advertising 0x%x  speed %u\n"
 347            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 348            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 349            cmd->cmd, cmd->supported, cmd->advertising,
 350            ethtool_cmd_speed(cmd),
 351            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 352            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 353
 354         return 0;
 355 }
 356
 357 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 358 {
 359         struct bnx2x *bp = netdev_priv(dev);
 360         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 361         u32 speed, phy_idx;
 362
 363         if (IS_MF_SD(bp))
 364                 return 0;
 365
 366         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 367            "  supported 0x%x  advertising 0x%x  speed %u\n"
 368            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 369            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 370            cmd->cmd, cmd->supported, cmd->advertising,
 371            ethtool_cmd_speed(cmd),
 372            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 373            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 374
 375         speed = ethtool_cmd_speed(cmd);
 376
 377         /* If received a request for an unknown duplex, assume full*/
 378         if (cmd->duplex == DUPLEX_UNKNOWN)
 379                 cmd->duplex = DUPLEX_FULL;
 380
 381         if (IS_MF_SI(bp)) {
 382                 u32 part;
 383                 u32 line_speed = bp->link_vars.line_speed;
 384
 385                 /* use 10G if no link detected */
 386                 if (!line_speed)
 387                         line_speed = 10000;
 388
 389                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 390                         DP(BNX2X_MSG_ETHTOOL,
 391                            "To set speed BC %X or higher is required, please upgrade BC\n",
 392                            REQ_BC_VER_4_SET_MF_BW);
 393                         return -EINVAL;
 394                 }
 395
 396                 part = (speed * 100) / line_speed;
 397
 398                 if (line_speed < speed || !part) {
 399                         DP(BNX2X_MSG_ETHTOOL,
 400                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 401                         return -EINVAL;
 402                 }
 403
 404                 if (bp->state != BNX2X_STATE_OPEN)
 405                         /* store value for following "load" */
 406                         bp->pending_max = part;
 407                 else
 408                         bnx2x_update_max_mf_config(bp, part);
 409
 410                 return 0;
 411         }
 412
 413         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 414         old_multi_phy_config = bp->link_params.multi_phy_config;
 415         if (cmd->port != bnx2x_get_port_type(bp)) {
 416                 switch (cmd->port) {
 417                 case PORT_TP:
 418                         if (!(bp->port.supported[0] & SUPPORTED_TP ||
 419                               bp->port.supported[1] & SUPPORTED_TP)) {
 420                                 DP(BNX2X_MSG_ETHTOOL,
 421                                    "Unsupported port type\n");
 422                                 return -EINVAL;
 423                         }
 424                         bp->link_params.multi_phy_config &=
 425                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
 426                         if (bp->link_params.multi_phy_config &
 427                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 428                                 bp->link_params.multi_phy_config |=
 429                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 430                         else
 431                                 bp->link_params.multi_phy_config |=
 432                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 433                         break;
 434                 case PORT_FIBRE:
 435                 case PORT_DA:
 436                 case PORT_NONE:
 437                         if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 438                               bp->port.supported[1] & SUPPORTED_FIBRE)) {
 439                                 DP(BNX2X_MSG_ETHTOOL,
 440                                    "Unsupported port type\n");
 441                                 return -EINVAL;
 442                         }
 443                         bp->link_params.multi_phy_config &=
 444                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
 445                         if (bp->link_params.multi_phy_config &
 446                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 447                                 bp->link_params.multi_phy_config |=
 448                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 449                         else
 450                                 bp->link_params.multi_phy_config |=
 451                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 452                         break;
 453                 default:
 454                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 455                         return -EINVAL;
 456                 }
 457         }
 458         /* Save new config in case command complete successfully */
 459         new_multi_phy_config = bp->link_params.multi_phy_config;
 460         /* Get the new cfg_idx */
 461         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 462         /* Restore old config in case command failed */
 463         bp->link_params.multi_phy_config = old_multi_phy_config;
 464         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 465
 466         if (cmd->autoneg == AUTONEG_ENABLE) {
 467                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 468                 if (bp->link_params.phy[EXT_PHY1].type ==
 469                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 470                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 471                                                SUPPORTED_100baseT_Full);
 472                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 473                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 474                         return -EINVAL;
 475                 }
 476
 477                 /* advertise the requested speed and duplex if supported */
 478                 if (cmd->advertising & ~an_supported_speed) {
 479                         DP(BNX2X_MSG_ETHTOOL,
 480                            "Advertisement parameters are not supported\n");
 481                         return -EINVAL;
 482                 }
 483
 484                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 485                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 486                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 487                                          cmd->advertising);
 488                 if (cmd->advertising) {
 489
 490                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 491                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 492                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 493                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 494                         }
 495                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 496                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 497                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 498
 499                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 500                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 501                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 502
 503                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 504                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 505                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 506                         }
 507                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 508                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 509                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 510                         }
 511                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 512                                                 ADVERTISED_1000baseKX_Full))
 513                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 514                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 515
 516                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 517                                                 ADVERTISED_10000baseKX4_Full |
 518                                                 ADVERTISED_10000baseKR_Full))
 519                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 520                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 521
 522                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
 523                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 524                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 525                 }
 526         } else { /* forced speed */
 527                 /* advertise the requested speed and duplex if supported */
 528                 switch (speed) {
 529                 case SPEED_10:
 530                         if (cmd->duplex == DUPLEX_FULL) {
 531                                 if (!(bp->port.supported[cfg_idx] &
 532                                       SUPPORTED_10baseT_Full)) {
 533                                         DP(BNX2X_MSG_ETHTOOL,
 534                                            "10M full not supported\n");
 535                                         return -EINVAL;
 536                                 }
 537
 538                                 advertising = (ADVERTISED_10baseT_Full |
 539                                                ADVERTISED_TP);
 540                         } else {
 541                                 if (!(bp->port.supported[cfg_idx] &
 542                                       SUPPORTED_10baseT_Half)) {
 543                                         DP(BNX2X_MSG_ETHTOOL,
 544                                            "10M half not supported\n");
 545                                         return -EINVAL;
 546                                 }
 547
 548                                 advertising = (ADVERTISED_10baseT_Half |
 549                                                ADVERTISED_TP);
 550                         }
 551                         break;
 552
 553                 case SPEED_100:
 554                         if (cmd->duplex == DUPLEX_FULL) {
 555                                 if (!(bp->port.supported[cfg_idx] &
 556                                                 SUPPORTED_100baseT_Full)) {
 557                                         DP(BNX2X_MSG_ETHTOOL,
 558                                            "100M full not supported\n");
 559                                         return -EINVAL;
 560                                 }
 561
 562                                 advertising = (ADVERTISED_100baseT_Full |
 563                                                ADVERTISED_TP);
 564                         } else {
 565                                 if (!(bp->port.supported[cfg_idx] &
 566                                                 SUPPORTED_100baseT_Half)) {
 567                                         DP(BNX2X_MSG_ETHTOOL,
 568                                            "100M half not supported\n");
 569                                         return -EINVAL;
 570                                 }
 571
 572                                 advertising = (ADVERTISED_100baseT_Half |
 573                                                ADVERTISED_TP);
 574                         }
 575                         break;
 576
 577                 case SPEED_1000:
 578                         if (cmd->duplex != DUPLEX_FULL) {
 579                                 DP(BNX2X_MSG_ETHTOOL,
 580                                    "1G half not supported\n");
 581                                 return -EINVAL;
 582                         }
 583
 584                         if (bp->port.supported[cfg_idx] &
 585                              SUPPORTED_1000baseT_Full) {
 586                                 advertising = (ADVERTISED_1000baseT_Full |
 587                                                ADVERTISED_TP);
 588
 589                         } else if (bp->port.supported[cfg_idx] &
 590                                    SUPPORTED_1000baseKX_Full) {
 591                                 advertising = ADVERTISED_1000baseKX_Full;
 592                         } else {
 593                                 DP(BNX2X_MSG_ETHTOOL,
 594                                    "1G full not supported\n");
 595                                 return -EINVAL;
 596                         }
 597
 598                         break;
 599
 600                 case SPEED_2500:
 601                         if (cmd->duplex != DUPLEX_FULL) {
 602                                 DP(BNX2X_MSG_ETHTOOL,
 603                                    "2.5G half not supported\n");
 604                                 return -EINVAL;
 605                         }
 606
 607                         if (!(bp->port.supported[cfg_idx]
 608                               & SUPPORTED_2500baseX_Full)) {
 609                                 DP(BNX2X_MSG_ETHTOOL,
 610                                    "2.5G full not supported\n");
 611                                 return -EINVAL;
 612                         }
 613
 614                         advertising = (ADVERTISED_2500baseX_Full |
 615                                        ADVERTISED_TP);
 616                         break;
 617
 618                 case SPEED_10000:
 619                         if (cmd->duplex != DUPLEX_FULL) {
 620                                 DP(BNX2X_MSG_ETHTOOL,
 621                                    "10G half not supported\n");
 622                                 return -EINVAL;
 623                         }
 624                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 625                         if ((bp->port.supported[cfg_idx] &
 626                              SUPPORTED_10000baseT_Full) &&
 627                             (bp->link_params.phy[phy_idx].media_type !=
 628                              ETH_PHY_SFP_1G_FIBER)) {
 629                                 advertising = (ADVERTISED_10000baseT_Full |
 630                                                ADVERTISED_FIBRE);
 631                         } else if (bp->port.supported[cfg_idx] &
 632                                SUPPORTED_10000baseKR_Full) {
 633                                 advertising = (ADVERTISED_10000baseKR_Full |
 634                                                ADVERTISED_FIBRE);
 635                         } else {
 636                                 DP(BNX2X_MSG_ETHTOOL,
 637                                    "10G full not supported\n");
 638                                 return -EINVAL;
 639                         }
 640
 641                         break;
 642
 643                 default:
 644                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 645                         return -EINVAL;
 646                 }
 647
 648                 bp->link_params.req_line_speed[cfg_idx] = speed;
 649                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 650                 bp->port.advertising[cfg_idx] = advertising;
 651         }
 652
 653         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 654            "  req_duplex %d  advertising 0x%x\n",
 655            bp->link_params.req_line_speed[cfg_idx],
 656            bp->link_params.req_duplex[cfg_idx],
 657            bp->port.advertising[cfg_idx]);
 658
 659         /* Set new config */
 660         bp->link_params.multi_phy_config = new_multi_phy_config;
 661         if (netif_running(dev)) {
 662                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 663                 bnx2x_force_link_reset(bp);
 664                 bnx2x_link_set(bp);
 665         }
 666
 667         return 0;
 668 }
 669
 670 #define DUMP_ALL_PRESETS                0x1FFF
 671 #define DUMP_MAX_PRESETS                13
 672
 673 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 674 {
 675         if (CHIP_IS_E1(bp))
 676                 return dump_num_registers[0][preset-1];
 677         else if (CHIP_IS_E1H(bp))
 678                 return dump_num_registers[1][preset-1];
 679         else if (CHIP_IS_E2(bp))
 680                 return dump_num_registers[2][preset-1];
 681         else if (CHIP_IS_E3A0(bp))
 682                 return dump_num_registers[3][preset-1];
 683         else if (CHIP_IS_E3B0(bp))
 684                 return dump_num_registers[4][preset-1];
 685         else
 686                 return 0;
 687 }
 688
 689 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 690 {
 691         u32 preset_idx;
 692         int regdump_len = 0;
 693
 694         /* Calculate the total preset regs length */
 695         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 696                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 697
 698         return regdump_len;
 699 }
 700
 701 static int bnx2x_get_regs_len(struct net_device *dev)
 702 {
 703         struct bnx2x *bp = netdev_priv(dev);
 704         int regdump_len = 0;
 705
 706         if (IS_VF(bp))
 707                 return 0;
 708
 709         regdump_len = __bnx2x_get_regs_len(bp);
 710         regdump_len *= 4;
 711         regdump_len += sizeof(struct dump_header);
 712
 713         return regdump_len;
 714 }
 715
 716 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 717 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 718 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 719 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 720 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 721
 722 #define IS_REG_IN_PRESET(presets, idx)  \
 723                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 724
 725 /******* Paged registers info selectors ********/
 726 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 727 {
 728         if (CHIP_IS_E2(bp))
 729                 return page_vals_e2;
 730         else if (CHIP_IS_E3(bp))
 731                 return page_vals_e3;
 732         else
 733                 return NULL;
 734 }
 735
 736 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 737 {
 738         if (CHIP_IS_E2(bp))
 739                 return PAGE_MODE_VALUES_E2;
 740         else if (CHIP_IS_E3(bp))
 741                 return PAGE_MODE_VALUES_E3;
 742         else
 743                 return 0;
 744 }
 745
 746 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 747 {
 748         if (CHIP_IS_E2(bp))
 749                 return page_write_regs_e2;
 750         else if (CHIP_IS_E3(bp))
 751                 return page_write_regs_e3;
 752         else
 753                 return NULL;
 754 }
 755
 756 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 757 {
 758         if (CHIP_IS_E2(bp))
 759                 return PAGE_WRITE_REGS_E2;
 760         else if (CHIP_IS_E3(bp))
 761                 return PAGE_WRITE_REGS_E3;
 762         else
 763                 return 0;
 764 }
 765
 766 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 767 {
 768         if (CHIP_IS_E2(bp))
 769                 return page_read_regs_e2;
 770         else if (CHIP_IS_E3(bp))
 771                 return page_read_regs_e3;
 772         else
 773                 return NULL;
 774 }
 775
 776 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 777 {
 778         if (CHIP_IS_E2(bp))
 779                 return PAGE_READ_REGS_E2;
 780         else if (CHIP_IS_E3(bp))
 781                 return PAGE_READ_REGS_E3;
 782         else
 783                 return 0;
 784 }
 785
 786 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 787                                        const struct reg_addr *reg_info)
 788 {
 789         if (CHIP_IS_E1(bp))
 790                 return IS_E1_REG(reg_info->chips);
 791         else if (CHIP_IS_E1H(bp))
 792                 return IS_E1H_REG(reg_info->chips);
 793         else if (CHIP_IS_E2(bp))
 794                 return IS_E2_REG(reg_info->chips);
 795         else if (CHIP_IS_E3A0(bp))
 796                 return IS_E3A0_REG(reg_info->chips);
 797         else if (CHIP_IS_E3B0(bp))
 798                 return IS_E3B0_REG(reg_info->chips);
 799         else
 800                 return false;
 801 }
 802
 803 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 804         const struct wreg_addr *wreg_info)
 805 {
 806         if (CHIP_IS_E1(bp))
 807                 return IS_E1_REG(wreg_info->chips);
 808         else if (CHIP_IS_E1H(bp))
 809                 return IS_E1H_REG(wreg_info->chips);
 810         else if (CHIP_IS_E2(bp))
 811                 return IS_E2_REG(wreg_info->chips);
 812         else if (CHIP_IS_E3A0(bp))
 813                 return IS_E3A0_REG(wreg_info->chips);
 814         else if (CHIP_IS_E3B0(bp))
 815                 return IS_E3B0_REG(wreg_info->chips);
 816         else
 817                 return false;
 818 }
 819
 820 /**
 821  * bnx2x_read_pages_regs - read "paged" registers
 822  *
 823  * @bp          device handle
 824  * @p           output buffer
 825  *
 826  * Reads "paged" memories: memories that may only be read by first writing to a
 827  * specific address ("write address") and then reading from a specific address
 828  * ("read address"). There may be more than one write address per "page" and
 829  * more than one read address per write address.
 830  */
 831 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 832 {
 833         u32 i, j, k, n;
 834
 835         /* addresses of the paged registers */
 836         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 837         /* number of paged registers */
 838         int num_pages = __bnx2x_get_page_reg_num(bp);
 839         /* write addresses */
 840         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 841         /* number of write addresses */
 842         int write_num = __bnx2x_get_page_write_num(bp);
 843         /* read addresses info */
 844         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 845         /* number of read addresses */
 846         int read_num = __bnx2x_get_page_read_num(bp);
 847         u32 addr, size;
 848
 849         for (i = 0; i < num_pages; i++) {
 850                 for (j = 0; j < write_num; j++) {
 851                         REG_WR(bp, write_addr[j], page_addr[i]);
 852
 853                         for (k = 0; k < read_num; k++) {
 854                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 855                                                      preset)) {
 856                                         size = read_addr[k].size;
 857                                         for (n = 0; n < size; n++) {
 858                                                 addr = read_addr[k].addr + n*4;
 859                                                 *p++ = REG_RD(bp, addr);
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865 }
 866
 867 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 868 {
 869         u32 i, j, addr;
 870         const struct wreg_addr *wreg_addr_p = NULL;
 871
 872         if (CHIP_IS_E1(bp))
 873                 wreg_addr_p = &wreg_addr_e1;
 874         else if (CHIP_IS_E1H(bp))
 875                 wreg_addr_p = &wreg_addr_e1h;
 876         else if (CHIP_IS_E2(bp))
 877                 wreg_addr_p = &wreg_addr_e2;
 878         else if (CHIP_IS_E3A0(bp))
 879                 wreg_addr_p = &wreg_addr_e3;
 880         else if (CHIP_IS_E3B0(bp))
 881                 wreg_addr_p = &wreg_addr_e3b0;
 882
 883         /* Read the idle_chk registers */
 884         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 885                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 886                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 887                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 888                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 889                 }
 890         }
 891
 892         /* Read the regular registers */
 893         for (i = 0; i < REGS_COUNT; i++) {
 894                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 895                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 896                         for (j = 0; j < reg_addrs[i].size; j++)
 897                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 898                 }
 899         }
 900
 901         /* Read the CAM registers */
 902         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 903             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 904                 for (i = 0; i < wreg_addr_p->size; i++) {
 905                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 906
 907                         /* In case of wreg_addr register, read additional
 908                            registers from read_regs array
 909                         */
 910                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 911                                 addr = *(wreg_addr_p->read_regs);
 912                                 *p++ = REG_RD(bp, addr + j*4);
 913                         }
 914                 }
 915         }
 916
 917         /* Paged registers are supported in E2 & E3 only */
 918         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 919                 /* Read "paged" registers */
 920                 bnx2x_read_pages_regs(bp, p, preset);
 921         }
 922
 923         return 0;
 924 }
 925
 926 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 927 {
 928         u32 preset_idx;
 929
 930         /* Read all registers, by reading all preset registers */
 931         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 932                 /* Skip presets with IOR */
 933                 if ((preset_idx == 2) ||
 934                     (preset_idx == 5) ||
 935                     (preset_idx == 8) ||
 936                     (preset_idx == 11))
 937                         continue;
 938                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 939                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 940         }
 941 }
 942
 943 static void bnx2x_get_regs(struct net_device *dev,
 944                            struct ethtool_regs *regs, void *_p)
 945 {
 946         u32 *p = _p;
 947         struct bnx2x *bp = netdev_priv(dev);
 948         struct dump_header dump_hdr = {0};
 949
 950         regs->version = 2;
 951         memset(p, 0, regs->len);
 952
 953         if (!netif_running(bp->dev))
 954                 return;
 955
 956         /* Disable parity attentions as long as following dump may
 957          * cause false alarms by reading never written registers. We
 958          * will re-enable parity attentions right after the dump.
 959          */
 960
 961         bnx2x_disable_blocks_parity(bp);
 962
 963         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 964         dump_hdr.preset = DUMP_ALL_PRESETS;
 965         dump_hdr.version = BNX2X_DUMP_VERSION;
 966
 967         /* dump_meta_data presents OR of CHIP and PATH. */
 968         if (CHIP_IS_E1(bp)) {
 969                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 970         } else if (CHIP_IS_E1H(bp)) {
 971                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 972         } else if (CHIP_IS_E2(bp)) {
 973                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 974                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 975         } else if (CHIP_IS_E3A0(bp)) {
 976                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 977                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 978         } else if (CHIP_IS_E3B0(bp)) {
 979                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 980                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 981         }
 982
 983         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 984         p += dump_hdr.header_size + 1;
 985
 986         /* Actually read the registers */
 987         __bnx2x_get_regs(bp, p);
 988
 989         /* Re-enable parity attentions */
 990         bnx2x_clear_blocks_parity(bp);
 991         bnx2x_enable_blocks_parity(bp);
 992 }
 993
 994 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 995 {
 996         struct bnx2x *bp = netdev_priv(dev);
 997         int regdump_len = 0;
 998
 999         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1000         regdump_len *= 4;
1001         regdump_len += sizeof(struct dump_header);
1002
1003         return regdump_len;
1004 }
1005
1006 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1007 {
1008         struct bnx2x *bp = netdev_priv(dev);
1009
1010         /* Use the ethtool_dump "flag" field as the dump preset index */
1011         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1012                 return -EINVAL;
1013
1014         bp->dump_preset_idx = val->flag;
1015         return 0;
1016 }
1017
1018 static int bnx2x_get_dump_flag(struct net_device *dev,
1019                                struct ethtool_dump *dump)
1020 {
1021         struct bnx2x *bp = netdev_priv(dev);
1022
1023         dump->version = BNX2X_DUMP_VERSION;
1024         dump->flag = bp->dump_preset_idx;
1025         /* Calculate the requested preset idx length */
1026         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1027         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1028            bp->dump_preset_idx, dump->len);
1029         return 0;
1030 }
1031
1032 static int bnx2x_get_dump_data(struct net_device *dev,
1033                                struct ethtool_dump *dump,
1034                                void *buffer)
1035 {
1036         u32 *p = buffer;
1037         struct bnx2x *bp = netdev_priv(dev);
1038         struct dump_header dump_hdr = {0};
1039
1040         /* Disable parity attentions as long as following dump may
1041          * cause false alarms by reading never written registers. We
1042          * will re-enable parity attentions right after the dump.
1043          */
1044
1045         bnx2x_disable_blocks_parity(bp);
1046
1047         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1048         dump_hdr.preset = bp->dump_preset_idx;
1049         dump_hdr.version = BNX2X_DUMP_VERSION;
1050
1051         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1052
1053         /* dump_meta_data presents OR of CHIP and PATH. */
1054         if (CHIP_IS_E1(bp)) {
1055                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1056         } else if (CHIP_IS_E1H(bp)) {
1057                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1058         } else if (CHIP_IS_E2(bp)) {
1059                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1060                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1061         } else if (CHIP_IS_E3A0(bp)) {
1062                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1063                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1064         } else if (CHIP_IS_E3B0(bp)) {
1065                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1066                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1067         }
1068
1069         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1070         p += dump_hdr.header_size + 1;
1071
1072         /* Actually read the registers */
1073         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1074
1075         /* Re-enable parity attentions */
1076         bnx2x_clear_blocks_parity(bp);
1077         bnx2x_enable_blocks_parity(bp);
1078
1079         return 0;
1080 }
1081
1082 static void bnx2x_get_drvinfo(struct net_device *dev,
1083                               struct ethtool_drvinfo *info)
1084 {
1085         struct bnx2x *bp = netdev_priv(dev);
1086
1087         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1088         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1089
1090         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1091
1092         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1093 }
1094
1095 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1096 {
1097         struct bnx2x *bp = netdev_priv(dev);
1098
1099         if (bp->flags & NO_WOL_FLAG) {
1100                 wol->supported = 0;
1101                 wol->wolopts = 0;
1102         } else {
1103                 wol->supported = WAKE_MAGIC;
1104                 if (bp->wol)
1105                         wol->wolopts = WAKE_MAGIC;
1106                 else
1107                         wol->wolopts = 0;
1108         }
1109         memset(&wol->sopass, 0, sizeof(wol->sopass));
1110 }
1111
1112 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1113 {
1114         struct bnx2x *bp = netdev_priv(dev);
1115
1116         if (wol->wolopts & ~WAKE_MAGIC) {
1117                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1118                 return -EINVAL;
1119         }
1120
1121         if (wol->wolopts & WAKE_MAGIC) {
1122                 if (bp->flags & NO_WOL_FLAG) {
1123                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1124                         return -EINVAL;
1125                 }
1126                 bp->wol = 1;
1127         } else
1128                 bp->wol = 0;
1129
1130         if (SHMEM2_HAS(bp, curr_cfg))
1131                 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1132
1133         return 0;
1134 }
1135
1136 static u32 bnx2x_get_msglevel(struct net_device *dev)
1137 {
1138         struct bnx2x *bp = netdev_priv(dev);
1139
1140         return bp->msg_enable;
1141 }
1142
1143 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1144 {
1145         struct bnx2x *bp = netdev_priv(dev);
1146
1147         if (capable(CAP_NET_ADMIN)) {
1148                 /* dump MCP trace */
1149                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1150                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1151                 bp->msg_enable = level;
1152         }
1153 }
1154
1155 static int bnx2x_nway_reset(struct net_device *dev)
1156 {
1157         struct bnx2x *bp = netdev_priv(dev);
1158
1159         if (!bp->port.pmf)
1160                 return 0;
1161
1162         if (netif_running(dev)) {
1163                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1164                 bnx2x_force_link_reset(bp);
1165                 bnx2x_link_set(bp);
1166         }
1167
1168         return 0;
1169 }
1170
1171 static u32 bnx2x_get_link(struct net_device *dev)
1172 {
1173         struct bnx2x *bp = netdev_priv(dev);
1174
1175         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1176                 return 0;
1177
1178         if (IS_VF(bp))
1179                 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1180                                  &bp->vf_link_vars.link_report_flags);
1181
1182         return bp->link_vars.link_up;
1183 }
1184
1185 static int bnx2x_get_eeprom_len(struct net_device *dev)
1186 {
1187         struct bnx2x *bp = netdev_priv(dev);
1188
1189         return bp->common.flash_size;
1190 }
1191
1192 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1193  * had we done things the other way around, if two pfs from the same port would
1194  * attempt to access nvram at the same time, we could run into a scenario such
1195  * as:
1196  * pf A takes the port lock.
1197  * pf B succeeds in taking the same lock since they are from the same port.
1198  * pf A takes the per pf misc lock. Performs eeprom access.
1199  * pf A finishes. Unlocks the per pf misc lock.
1200  * Pf B takes the lock and proceeds to perform it's own access.
1201  * pf A unlocks the per port lock, while pf B is still working (!).
1202  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1203  * access corrupted by pf B)
1204  */
1205 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1206 {
1207         int port = BP_PORT(bp);
1208         int count, i;
1209         u32 val;
1210
1211         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1212         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1213
1214         /* adjust timeout for emulation/FPGA */
1215         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1216         if (CHIP_REV_IS_SLOW(bp))
1217                 count *= 100;
1218
1219         /* request access to nvram interface */
1220         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1221                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1222
1223         for (i = 0; i < count*10; i++) {
1224                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1225                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1226                         break;
1227
1228                 udelay(5);
1229         }
1230
1231         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1232                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1233                    "cannot get access to nvram interface\n");
1234                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1235                 return -EBUSY;
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1242 {
1243         int port = BP_PORT(bp);
1244         int count, i;
1245         u32 val;
1246
1247         /* adjust timeout for emulation/FPGA */
1248         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1249         if (CHIP_REV_IS_SLOW(bp))
1250                 count *= 100;
1251
1252         /* relinquish nvram interface */
1253         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1254                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1255
1256         for (i = 0; i < count*10; i++) {
1257                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1258                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1259                         break;
1260
1261                 udelay(5);
1262         }
1263
1264         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1265                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1266                    "cannot free access to nvram interface\n");
1267                 return -EBUSY;
1268         }
1269
1270         /* release HW lock: protect against other PFs in PF Direct Assignment */
1271         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1272         return 0;
1273 }
1274
1275 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1276 {
1277         u32 val;
1278
1279         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1280
1281         /* enable both bits, even on read */
1282         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1283                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1284                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1285 }
1286
1287 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1288 {
1289         u32 val;
1290
1291         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1292
1293         /* disable both bits, even after read */
1294         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1295                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1296                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1297 }
1298
1299 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1300                                   u32 cmd_flags)
1301 {
1302         int count, i, rc;
1303         u32 val;
1304
1305         /* build the command word */
1306         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1307
1308         /* need to clear DONE bit separately */
1309         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1310
1311         /* address of the NVRAM to read from */
1312         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1313                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1314
1315         /* issue a read command */
1316         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1317
1318         /* adjust timeout for emulation/FPGA */
1319         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1320         if (CHIP_REV_IS_SLOW(bp))
1321                 count *= 100;
1322
1323         /* wait for completion */
1324         *ret_val = 0;
1325         rc = -EBUSY;
1326         for (i = 0; i < count; i++) {
1327                 udelay(5);
1328                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1329
1330                 if (val & MCPR_NVM_COMMAND_DONE) {
1331                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1332                         /* we read nvram data in cpu order
1333                          * but ethtool sees it as an array of bytes
1334                          * converting to big-endian will do the work
1335                          */
1336                         *ret_val = cpu_to_be32(val);
1337                         rc = 0;
1338                         break;
1339                 }
1340         }
1341         if (rc == -EBUSY)
1342                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1343                    "nvram read timeout expired\n");
1344         return rc;
1345 }
1346
1347 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1348                      int buf_size)
1349 {
1350         int rc;
1351         u32 cmd_flags;
1352         __be32 val;
1353
1354         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1355                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1356                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1357                    offset, buf_size);
1358                 return -EINVAL;
1359         }
1360
1361         if (offset + buf_size > bp->common.flash_size) {
1362                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1363                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1364                    offset, buf_size, bp->common.flash_size);
1365                 return -EINVAL;
1366         }
1367
1368         /* request access to nvram interface */
1369         rc = bnx2x_acquire_nvram_lock(bp);
1370         if (rc)
1371                 return rc;
1372
1373         /* enable access to nvram interface */
1374         bnx2x_enable_nvram_access(bp);
1375
1376         /* read the first word(s) */
1377         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1378         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1379                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1380                 memcpy(ret_buf, &val, 4);
1381
1382                 /* advance to the next dword */
1383                 offset += sizeof(u32);
1384                 ret_buf += sizeof(u32);
1385                 buf_size -= sizeof(u32);
1386                 cmd_flags = 0;
1387         }
1388
1389         if (rc == 0) {
1390                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1391                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1392                 memcpy(ret_buf, &val, 4);
1393         }
1394
1395         /* disable access to nvram interface */
1396         bnx2x_disable_nvram_access(bp);
1397         bnx2x_release_nvram_lock(bp);
1398
1399         return rc;
1400 }
1401
1402 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1403                               int buf_size)
1404 {
1405         int rc;
1406
1407         rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1408
1409         if (!rc) {
1410                 __be32 *be = (__be32 *)buf;
1411
1412                 while ((buf_size -= 4) >= 0)
1413                         *buf++ = be32_to_cpu(*be++);
1414         }
1415
1416         return rc;
1417 }
1418
1419 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1420 {
1421         int rc = 1;
1422         u16 pm = 0;
1423         struct net_device *dev = pci_get_drvdata(bp->pdev);
1424
1425         if (bp->pdev->pm_cap)
1426                 rc = pci_read_config_word(bp->pdev,
1427                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1428
1429         if ((rc && !netif_running(dev)) ||
1430             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1431                 return false;
1432
1433         return true;
1434 }
1435
1436 static int bnx2x_get_eeprom(struct net_device *dev,
1437                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1438 {
1439         struct bnx2x *bp = netdev_priv(dev);
1440
1441         if (!bnx2x_is_nvm_accessible(bp)) {
1442                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1443                    "cannot access eeprom when the interface is down\n");
1444                 return -EAGAIN;
1445         }
1446
1447         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1448            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1449            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1450            eeprom->len, eeprom->len);
1451
1452         /* parameters already validated in ethtool_get_eeprom */
1453
1454         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1455 }
1456
1457 static int bnx2x_get_module_eeprom(struct net_device *dev,
1458                                    struct ethtool_eeprom *ee,
1459                                    u8 *data)
1460 {
1461         struct bnx2x *bp = netdev_priv(dev);
1462         int rc = -EINVAL, phy_idx;
1463         u8 *user_data = data;
1464         unsigned int start_addr = ee->offset, xfer_size = 0;
1465
1466         if (!bnx2x_is_nvm_accessible(bp)) {
1467                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1468                    "cannot access eeprom when the interface is down\n");
1469                 return -EAGAIN;
1470         }
1471
1472         phy_idx = bnx2x_get_cur_phy_idx(bp);
1473
1474         /* Read A0 section */
1475         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1476                 /* Limit transfer size to the A0 section boundary */
1477                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1478                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1479                 else
1480                         xfer_size = ee->len;
1481                 bnx2x_acquire_phy_lock(bp);
1482                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1483                                                   &bp->link_params,
1484                                                   I2C_DEV_ADDR_A0,
1485                                                   start_addr,
1486                                                   xfer_size,
1487                                                   user_data);
1488                 bnx2x_release_phy_lock(bp);
1489                 if (rc) {
1490                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1491
1492                         return -EINVAL;
1493                 }
1494                 user_data += xfer_size;
1495                 start_addr += xfer_size;
1496         }
1497
1498         /* Read A2 section */
1499         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1500             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1501                 xfer_size = ee->len - xfer_size;
1502                 /* Limit transfer size to the A2 section boundary */
1503                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1504                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1505                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1506                 bnx2x_acquire_phy_lock(bp);
1507                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1508                                                   &bp->link_params,
1509                                                   I2C_DEV_ADDR_A2,
1510                                                   start_addr,
1511                                                   xfer_size,
1512                                                   user_data);
1513                 bnx2x_release_phy_lock(bp);
1514                 if (rc) {
1515                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1516                         return -EINVAL;
1517                 }
1518         }
1519         return rc;
1520 }
1521
1522 static int bnx2x_get_module_info(struct net_device *dev,
1523                                  struct ethtool_modinfo *modinfo)
1524 {
1525         struct bnx2x *bp = netdev_priv(dev);
1526         int phy_idx, rc;
1527         u8 sff8472_comp, diag_type;
1528
1529         if (!bnx2x_is_nvm_accessible(bp)) {
1530                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1531                    "cannot access eeprom when the interface is down\n");
1532                 return -EAGAIN;
1533         }
1534         phy_idx = bnx2x_get_cur_phy_idx(bp);
1535         bnx2x_acquire_phy_lock(bp);
1536         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1537                                           &bp->link_params,
1538                                           I2C_DEV_ADDR_A0,
1539                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1540                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1541                                           &sff8472_comp);
1542         bnx2x_release_phy_lock(bp);
1543         if (rc) {
1544                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1545                 return -EINVAL;
1546         }
1547
1548         bnx2x_acquire_phy_lock(bp);
1549         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1550                                           &bp->link_params,
1551                                           I2C_DEV_ADDR_A0,
1552                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1553                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1554                                           &diag_type);
1555         bnx2x_release_phy_lock(bp);
1556         if (rc) {
1557                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1558                 return -EINVAL;
1559         }
1560
1561         if (!sff8472_comp ||
1562             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1563             !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
1564                 modinfo->type = ETH_MODULE_SFF_8079;
1565                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1566         } else {
1567                 modinfo->type = ETH_MODULE_SFF_8472;
1568                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1569         }
1570         return 0;
1571 }
1572
1573 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1574                                    u32 cmd_flags)
1575 {
1576         int count, i, rc;
1577
1578         /* build the command word */
1579         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1580
1581         /* need to clear DONE bit separately */
1582         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1583
1584         /* write the data */
1585         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1586
1587         /* address of the NVRAM to write to */
1588         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1589                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1590
1591         /* issue the write command */
1592         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1593
1594         /* adjust timeout for emulation/FPGA */
1595         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1596         if (CHIP_REV_IS_SLOW(bp))
1597                 count *= 100;
1598
1599         /* wait for completion */
1600         rc = -EBUSY;
1601         for (i = 0; i < count; i++) {
1602                 udelay(5);
1603                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1604                 if (val & MCPR_NVM_COMMAND_DONE) {
1605                         rc = 0;
1606                         break;
1607                 }
1608         }
1609
1610         if (rc == -EBUSY)
1611                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1612                    "nvram write timeout expired\n");
1613         return rc;
1614 }
1615
1616 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1617
1618 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1619                               int buf_size)
1620 {
1621         int rc;
1622         u32 cmd_flags, align_offset, val;
1623         __be32 val_be;
1624
1625         if (offset + buf_size > bp->common.flash_size) {
1626                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1627                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1628                    offset, buf_size, bp->common.flash_size);
1629                 return -EINVAL;
1630         }
1631
1632         /* request access to nvram interface */
1633         rc = bnx2x_acquire_nvram_lock(bp);
1634         if (rc)
1635                 return rc;
1636
1637         /* enable access to nvram interface */
1638         bnx2x_enable_nvram_access(bp);
1639
1640         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1641         align_offset = (offset & ~0x03);
1642         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1643
1644         if (rc == 0) {
1645                 /* nvram data is returned as an array of bytes
1646                  * convert it back to cpu order
1647                  */
1648                 val = be32_to_cpu(val_be);
1649
1650                 val &= ~le32_to_cpu((__force __le32)
1651                                     (0xff << BYTE_OFFSET(offset)));
1652                 val |= le32_to_cpu((__force __le32)
1653                                    (*data_buf << BYTE_OFFSET(offset)));
1654
1655                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1656                                              cmd_flags);
1657         }
1658
1659         /* disable access to nvram interface */
1660         bnx2x_disable_nvram_access(bp);
1661         bnx2x_release_nvram_lock(bp);
1662
1663         return rc;
1664 }
1665
1666 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1667                              int buf_size)
1668 {
1669         int rc;
1670         u32 cmd_flags;
1671         u32 val;
1672         u32 written_so_far;
1673
1674         if (buf_size == 1)      /* ethtool */
1675                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1676
1677         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1678                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1679                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1680                    offset, buf_size);
1681                 return -EINVAL;
1682         }
1683
1684         if (offset + buf_size > bp->common.flash_size) {
1685                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1686                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1687                    offset, buf_size, bp->common.flash_size);
1688                 return -EINVAL;
1689         }
1690
1691         /* request access to nvram interface */
1692         rc = bnx2x_acquire_nvram_lock(bp);
1693         if (rc)
1694                 return rc;
1695
1696         /* enable access to nvram interface */
1697         bnx2x_enable_nvram_access(bp);
1698
1699         written_so_far = 0;
1700         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1701         while ((written_so_far < buf_size) && (rc == 0)) {
1702                 if (written_so_far == (buf_size - sizeof(u32)))
1703                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1704                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1705                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1706                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1707                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1708
1709                 memcpy(&val, data_buf, 4);
1710
1711                 /* Notice unlike bnx2x_nvram_read_dword() this will not
1712                  * change val using be32_to_cpu(), which causes data to flip
1713                  * if the eeprom is read and then written back. This is due
1714                  * to tools utilizing this functionality that would break
1715                  * if this would be resolved.
1716                  */
1717                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1718
1719                 /* advance to the next dword */
1720                 offset += sizeof(u32);
1721                 data_buf += sizeof(u32);
1722                 written_so_far += sizeof(u32);
1723
1724                 /* At end of each 4Kb page, release nvram lock to allow MFW
1725                  * chance to take it for its own use.
1726                  */
1727                 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1728                     (written_so_far < buf_size)) {
1729                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1730                            "Releasing NVM lock after offset 0x%x\n",
1731                            (u32)(offset - sizeof(u32)));
1732                         bnx2x_release_nvram_lock(bp);
1733                         usleep_range(1000, 2000);
1734                         rc = bnx2x_acquire_nvram_lock(bp);
1735                         if (rc)
1736                                 return rc;
1737                 }
1738
1739                 cmd_flags = 0;
1740         }
1741
1742         /* disable access to nvram interface */
1743         bnx2x_disable_nvram_access(bp);
1744         bnx2x_release_nvram_lock(bp);
1745
1746         return rc;
1747 }
1748
1749 static int bnx2x_set_eeprom(struct net_device *dev,
1750                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1751 {
1752         struct bnx2x *bp = netdev_priv(dev);
1753         int port = BP_PORT(bp);
1754         int rc = 0;
1755         u32 ext_phy_config;
1756
1757         if (!bnx2x_is_nvm_accessible(bp)) {
1758                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1759                    "cannot access eeprom when the interface is down\n");
1760                 return -EAGAIN;
1761         }
1762
1763         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1764            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1765            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1766            eeprom->len, eeprom->len);
1767
1768         /* parameters already validated in ethtool_set_eeprom */
1769
1770         /* PHY eeprom can be accessed only by the PMF */
1771         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1772             !bp->port.pmf) {
1773                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1774                    "wrong magic or interface is not pmf\n");
1775                 return -EINVAL;
1776         }
1777
1778         ext_phy_config =
1779                 SHMEM_RD(bp,
1780                          dev_info.port_hw_config[port].external_phy_config);
1781
1782         if (eeprom->magic == 0x50485950) {
1783                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1784                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1785
1786                 bnx2x_acquire_phy_lock(bp);
1787                 rc |= bnx2x_link_reset(&bp->link_params,
1788                                        &bp->link_vars, 0);
1789                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1790                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1791                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1792                                        MISC_REGISTERS_GPIO_HIGH, port);
1793                 bnx2x_release_phy_lock(bp);
1794                 bnx2x_link_report(bp);
1795
1796         } else if (eeprom->magic == 0x50485952) {
1797                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1798                 if (bp->state == BNX2X_STATE_OPEN) {
1799                         bnx2x_acquire_phy_lock(bp);
1800                         rc |= bnx2x_link_reset(&bp->link_params,
1801                                                &bp->link_vars, 1);
1802
1803                         rc |= bnx2x_phy_init(&bp->link_params,
1804                                              &bp->link_vars);
1805                         bnx2x_release_phy_lock(bp);
1806                         bnx2x_calc_fc_adv(bp);
1807                 }
1808         } else if (eeprom->magic == 0x53985943) {
1809                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1810                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1811                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1812
1813                         /* DSP Remove Download Mode */
1814                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1815                                        MISC_REGISTERS_GPIO_LOW, port);
1816
1817                         bnx2x_acquire_phy_lock(bp);
1818
1819                         bnx2x_sfx7101_sp_sw_reset(bp,
1820                                                 &bp->link_params.phy[EXT_PHY1]);
1821
1822                         /* wait 0.5 sec to allow it to run */
1823                         msleep(500);
1824                         bnx2x_ext_phy_hw_reset(bp, port);
1825                         msleep(500);
1826                         bnx2x_release_phy_lock(bp);
1827                 }
1828         } else
1829                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1830
1831         return rc;
1832 }
1833
1834 static int bnx2x_get_coalesce(struct net_device *dev,
1835                               struct ethtool_coalesce *coal)
1836 {
1837         struct bnx2x *bp = netdev_priv(dev);
1838
1839         memset(coal, 0, sizeof(struct ethtool_coalesce));
1840
1841         coal->rx_coalesce_usecs = bp->rx_ticks;
1842         coal->tx_coalesce_usecs = bp->tx_ticks;
1843
1844         return 0;
1845 }
1846
1847 static int bnx2x_set_coalesce(struct net_device *dev,
1848                               struct ethtool_coalesce *coal)
1849 {
1850         struct bnx2x *bp = netdev_priv(dev);
1851
1852         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1853         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1854                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1855
1856         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1857         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1858                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1859
1860         if (netif_running(dev))
1861                 bnx2x_update_coalesce(bp);
1862
1863         return 0;
1864 }
1865
1866 static void bnx2x_get_ringparam(struct net_device *dev,
1867                                 struct ethtool_ringparam *ering)
1868 {
1869         struct bnx2x *bp = netdev_priv(dev);
1870
1871         ering->rx_max_pending = MAX_RX_AVAIL;
1872
1873         if (bp->rx_ring_size)
1874                 ering->rx_pending = bp->rx_ring_size;
1875         else
1876                 ering->rx_pending = MAX_RX_AVAIL;
1877
1878         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1879         ering->tx_pending = bp->tx_ring_size;
1880 }
1881
1882 static int bnx2x_set_ringparam(struct net_device *dev,
1883                                struct ethtool_ringparam *ering)
1884 {
1885         struct bnx2x *bp = netdev_priv(dev);
1886
1887         DP(BNX2X_MSG_ETHTOOL,
1888            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1889            ering->rx_pending, ering->tx_pending);
1890
1891         if (pci_num_vf(bp->pdev)) {
1892                 DP(BNX2X_MSG_IOV,
1893                    "VFs are enabled, can not change ring parameters\n");
1894                 return -EPERM;
1895         }
1896
1897         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1898                 DP(BNX2X_MSG_ETHTOOL,
1899                    "Handling parity error recovery. Try again later\n");
1900                 return -EAGAIN;
1901         }
1902
1903         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1904             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1905                                                     MIN_RX_SIZE_TPA)) ||
1906             (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1907             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1908                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1909                 return -EINVAL;
1910         }
1911
1912         bp->rx_ring_size = ering->rx_pending;
1913         bp->tx_ring_size = ering->tx_pending;
1914
1915         return bnx2x_reload_if_running(dev);
1916 }
1917
1918 static void bnx2x_get_pauseparam(struct net_device *dev,
1919                                  struct ethtool_pauseparam *epause)
1920 {
1921         struct bnx2x *bp = netdev_priv(dev);
1922         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1923         int cfg_reg;
1924
1925         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1926                            BNX2X_FLOW_CTRL_AUTO);
1927
1928         if (!epause->autoneg)
1929                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1930         else
1931                 cfg_reg = bp->link_params.req_fc_auto_adv;
1932
1933         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1934                             BNX2X_FLOW_CTRL_RX);
1935         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1936                             BNX2X_FLOW_CTRL_TX);
1937
1938         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1939            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1940            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1941 }
1942
1943 static int bnx2x_set_pauseparam(struct net_device *dev,
1944                                 struct ethtool_pauseparam *epause)
1945 {
1946         struct bnx2x *bp = netdev_priv(dev);
1947         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1948         if (IS_MF(bp))
1949                 return 0;
1950
1951         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1952            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1953            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1954
1955         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1956
1957         if (epause->rx_pause)
1958                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1959
1960         if (epause->tx_pause)
1961                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1962
1963         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1964                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1965
1966         if (epause->autoneg) {
1967                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1968                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1969                         return -EINVAL;
1970                 }
1971
1972                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1973                         bp->link_params.req_flow_ctrl[cfg_idx] =
1974                                 BNX2X_FLOW_CTRL_AUTO;
1975                 }
1976                 bp->link_params.req_fc_auto_adv = 0;
1977                 if (epause->rx_pause)
1978                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1979
1980                 if (epause->tx_pause)
1981                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1982
1983                 if (!bp->link_params.req_fc_auto_adv)
1984                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1985         }
1986
1987         DP(BNX2X_MSG_ETHTOOL,
1988            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1989
1990         if (netif_running(dev)) {
1991                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1992                 bnx2x_force_link_reset(bp);
1993                 bnx2x_link_set(bp);
1994         }
1995
1996         return 0;
1997 }
1998
1999 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2000         "register_test (offline)    ",
2001         "memory_test (offline)      ",
2002         "int_loopback_test (offline)",
2003         "ext_loopback_test (offline)",
2004         "nvram_test (online)        ",
2005         "interrupt_test (online)    ",
2006         "link_test (online)         "
2007 };
2008
2009 enum {
2010         BNX2X_PRI_FLAG_ISCSI,
2011         BNX2X_PRI_FLAG_FCOE,
2012         BNX2X_PRI_FLAG_STORAGE,
2013         BNX2X_PRI_FLAG_LEN,
2014 };
2015
2016 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2017         "iSCSI offload support",
2018         "FCoE offload support",
2019         "Storage only interface"
2020 };
2021
2022 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2023 {
2024         u32 modes = 0;
2025
2026         if (eee_adv & SHMEM_EEE_100M_ADV)
2027                 modes |= ADVERTISED_100baseT_Full;
2028         if (eee_adv & SHMEM_EEE_1G_ADV)
2029                 modes |= ADVERTISED_1000baseT_Full;
2030         if (eee_adv & SHMEM_EEE_10G_ADV)
2031                 modes |= ADVERTISED_10000baseT_Full;
2032
2033         return modes;
2034 }
2035
2036 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2037 {
2038         u32 eee_adv = 0;
2039         if (modes & ADVERTISED_100baseT_Full)
2040                 eee_adv |= SHMEM_EEE_100M_ADV;
2041         if (modes & ADVERTISED_1000baseT_Full)
2042                 eee_adv |= SHMEM_EEE_1G_ADV;
2043         if (modes & ADVERTISED_10000baseT_Full)
2044                 eee_adv |= SHMEM_EEE_10G_ADV;
2045
2046         return eee_adv << shift;
2047 }
2048
2049 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2050 {
2051         struct bnx2x *bp = netdev_priv(dev);
2052         u32 eee_cfg;
2053
2054         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2055                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2056                 return -EOPNOTSUPP;
2057         }
2058
2059         eee_cfg = bp->link_vars.eee_status;
2060
2061         edata->supported =
2062                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2063                                  SHMEM_EEE_SUPPORTED_SHIFT);
2064
2065         edata->advertised =
2066                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2067                                  SHMEM_EEE_ADV_STATUS_SHIFT);
2068         edata->lp_advertised =
2069                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2070                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2071
2072         /* SHMEM value is in 16u units --> Convert to 1u units. */
2073         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2074
2075         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2076         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2077         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2078
2079         return 0;
2080 }
2081
2082 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2083 {
2084         struct bnx2x *bp = netdev_priv(dev);
2085         u32 eee_cfg;
2086         u32 advertised;
2087
2088         if (IS_MF(bp))
2089                 return 0;
2090
2091         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2092                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2093                 return -EOPNOTSUPP;
2094         }
2095
2096         eee_cfg = bp->link_vars.eee_status;
2097
2098         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2099                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2100                 return -EOPNOTSUPP;
2101         }
2102
2103         advertised = bnx2x_adv_to_eee(edata->advertised,
2104                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2105         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2106                 DP(BNX2X_MSG_ETHTOOL,
2107                    "Direct manipulation of EEE advertisement is not supported\n");
2108                 return -EINVAL;
2109         }
2110
2111         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2112                 DP(BNX2X_MSG_ETHTOOL,
2113                    "Maximal Tx Lpi timer supported is %x(u)\n",
2114                    EEE_MODE_TIMER_MASK);
2115                 return -EINVAL;
2116         }
2117         if (edata->tx_lpi_enabled &&
2118             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2119                 DP(BNX2X_MSG_ETHTOOL,
2120                    "Minimal Tx Lpi timer supported is %d(u)\n",
2121                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2122                 return -EINVAL;
2123         }
2124
2125         /* All is well; Apply changes*/
2126         if (edata->eee_enabled)
2127                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2128         else
2129                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2130
2131         if (edata->tx_lpi_enabled)
2132                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2133         else
2134                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2135
2136         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2137         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2138                                     EEE_MODE_TIMER_MASK) |
2139                                     EEE_MODE_OVERRIDE_NVRAM |
2140                                     EEE_MODE_OUTPUT_TIME;
2141
2142         /* Restart link to propagate changes */
2143         if (netif_running(dev)) {
2144                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2145                 bnx2x_force_link_reset(bp);
2146                 bnx2x_link_set(bp);
2147         }
2148
2149         return 0;
2150 }
2151
2152 enum {
2153         BNX2X_CHIP_E1_OFST = 0,
2154         BNX2X_CHIP_E1H_OFST,
2155         BNX2X_CHIP_E2_OFST,
2156         BNX2X_CHIP_E3_OFST,
2157         BNX2X_CHIP_E3B0_OFST,
2158         BNX2X_CHIP_MAX_OFST
2159 };
2160
2161 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2162 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2163 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2164 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2165 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2166
2167 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2168 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2169
2170 static int bnx2x_test_registers(struct bnx2x *bp)
2171 {
2172         int idx, i, rc = -ENODEV;
2173         u32 wr_val = 0, hw;
2174         int port = BP_PORT(bp);
2175         static const struct {
2176                 u32 hw;
2177                 u32 offset0;
2178                 u32 offset1;
2179                 u32 mask;
2180         } reg_tbl[] = {
2181 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2182                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2183                 { BNX2X_CHIP_MASK_ALL,
2184                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2185                 { BNX2X_CHIP_MASK_E1X,
2186                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2187                 { BNX2X_CHIP_MASK_ALL,
2188                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2189                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2190                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2191                 { BNX2X_CHIP_MASK_E3B0,
2192                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2193                 { BNX2X_CHIP_MASK_ALL,
2194                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2195                 { BNX2X_CHIP_MASK_ALL,
2196                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2197                 { BNX2X_CHIP_MASK_ALL,
2198                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2199                 { BNX2X_CHIP_MASK_ALL,
2200                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2201 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2202                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2203                 { BNX2X_CHIP_MASK_ALL,
2204                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2205                 { BNX2X_CHIP_MASK_ALL,
2206                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2207                 { BNX2X_CHIP_MASK_ALL,
2208                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2209                 { BNX2X_CHIP_MASK_ALL,
2210                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2211                 { BNX2X_CHIP_MASK_ALL,
2212                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2213                 { BNX2X_CHIP_MASK_ALL,
2214                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2215                 { BNX2X_CHIP_MASK_ALL,
2216                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2217                 { BNX2X_CHIP_MASK_ALL,
2218                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2219                 { BNX2X_CHIP_MASK_ALL,
2220                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2221 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2222                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2223                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2224                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2225                 { BNX2X_CHIP_MASK_ALL,
2226                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2227                 { BNX2X_CHIP_MASK_ALL,
2228                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2229                 { BNX2X_CHIP_MASK_ALL,
2230                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2231                 { BNX2X_CHIP_MASK_ALL,
2232                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2233                 { BNX2X_CHIP_MASK_ALL,
2234                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2235                 { BNX2X_CHIP_MASK_ALL,
2236                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2237                 { BNX2X_CHIP_MASK_ALL,
2238                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2239                 { BNX2X_CHIP_MASK_ALL,
2240                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2241 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2242                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2243                 { BNX2X_CHIP_MASK_ALL,
2244                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2245                 { BNX2X_CHIP_MASK_ALL,
2246                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2247                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2248                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2249                 { BNX2X_CHIP_MASK_ALL,
2250                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2251                 { BNX2X_CHIP_MASK_ALL,
2252                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2253                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2254                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2255                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2256                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2257
2258                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2259         };
2260
2261         if (!bnx2x_is_nvm_accessible(bp)) {
2262                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2263                    "cannot access eeprom when the interface is down\n");
2264                 return rc;
2265         }
2266
2267         if (CHIP_IS_E1(bp))
2268                 hw = BNX2X_CHIP_MASK_E1;
2269         else if (CHIP_IS_E1H(bp))
2270                 hw = BNX2X_CHIP_MASK_E1H;
2271         else if (CHIP_IS_E2(bp))
2272                 hw = BNX2X_CHIP_MASK_E2;
2273         else if (CHIP_IS_E3B0(bp))
2274                 hw = BNX2X_CHIP_MASK_E3B0;
2275         else /* e3 A0 */
2276                 hw = BNX2X_CHIP_MASK_E3;
2277
2278         /* Repeat the test twice:
2279          * First by writing 0x00000000, second by writing 0xffffffff
2280          */
2281         for (idx = 0; idx < 2; idx++) {
2282
2283                 switch (idx) {
2284                 case 0:
2285                         wr_val = 0;
2286                         break;
2287                 case 1:
2288                         wr_val = 0xffffffff;
2289                         break;
2290                 }
2291
2292                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2293                         u32 offset, mask, save_val, val;
2294                         if (!(hw & reg_tbl[i].hw))
2295                                 continue;
2296
2297                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2298                         mask = reg_tbl[i].mask;
2299
2300                         save_val = REG_RD(bp, offset);
2301
2302                         REG_WR(bp, offset, wr_val & mask);
2303
2304                         val = REG_RD(bp, offset);
2305
2306                         /* Restore the original register's value */
2307                         REG_WR(bp, offset, save_val);
2308
2309                         /* verify value is as expected */
2310                         if ((val & mask) != (wr_val & mask)) {
2311                                 DP(BNX2X_MSG_ETHTOOL,
2312                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2313                                    offset, val, wr_val, mask);
2314                                 goto test_reg_exit;
2315                         }
2316                 }
2317         }
2318
2319         rc = 0;
2320
2321 test_reg_exit:
2322         return rc;
2323 }
2324
2325 static int bnx2x_test_memory(struct bnx2x *bp)
2326 {
2327         int i, j, rc = -ENODEV;
2328         u32 val, index;
2329         static const struct {
2330                 u32 offset;
2331                 int size;
2332         } mem_tbl[] = {
2333                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2334                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2335                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2336                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2337                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2338                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2339                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2340
2341                 { 0xffffffff, 0 }
2342         };
2343
2344         static const struct {
2345                 char *name;
2346                 u32 offset;
2347                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2348         } prty_tbl[] = {
2349                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2350                         {0x3ffc0, 0,   0, 0} },
2351                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2352                         {0x2,     0x2, 0, 0} },
2353                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2354                         {0,       0,   0, 0} },
2355                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2356                         {0x3ffc0, 0,   0, 0} },
2357                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2358                         {0x3ffc0, 0,   0, 0} },
2359                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2360                         {0x3ffc1, 0,   0, 0} },
2361
2362                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2363         };
2364
2365         if (!bnx2x_is_nvm_accessible(bp)) {
2366                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2367                    "cannot access eeprom when the interface is down\n");
2368                 return rc;
2369         }
2370
2371         if (CHIP_IS_E1(bp))
2372                 index = BNX2X_CHIP_E1_OFST;
2373         else if (CHIP_IS_E1H(bp))
2374                 index = BNX2X_CHIP_E1H_OFST;
2375         else if (CHIP_IS_E2(bp))
2376                 index = BNX2X_CHIP_E2_OFST;
2377         else /* e3 */
2378                 index = BNX2X_CHIP_E3_OFST;
2379
2380         /* pre-Check the parity status */
2381         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2382                 val = REG_RD(bp, prty_tbl[i].offset);
2383                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2384                         DP(BNX2X_MSG_ETHTOOL,
2385                            "%s is 0x%x\n", prty_tbl[i].name, val);
2386                         goto test_mem_exit;
2387                 }
2388         }
2389
2390         /* Go through all the memories */
2391         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2392                 for (j = 0; j < mem_tbl[i].size; j++)
2393                         REG_RD(bp, mem_tbl[i].offset + j*4);
2394
2395         /* Check the parity status */
2396         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2397                 val = REG_RD(bp, prty_tbl[i].offset);
2398                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2399                         DP(BNX2X_MSG_ETHTOOL,
2400                            "%s is 0x%x\n", prty_tbl[i].name, val);
2401                         goto test_mem_exit;
2402                 }
2403         }
2404
2405         rc = 0;
2406
2407 test_mem_exit:
2408         return rc;
2409 }
2410
2411 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2412 {
2413         int cnt = 1400;
2414
2415         if (link_up) {
2416                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2417                         msleep(20);
2418
2419                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2420                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2421
2422                 cnt = 1400;
2423                 while (!bp->link_vars.link_up && cnt--)
2424                         msleep(20);
2425
2426                 if (cnt <= 0 && !bp->link_vars.link_up)
2427                         DP(BNX2X_MSG_ETHTOOL,
2428                            "Timeout waiting for link init\n");
2429         }
2430 }
2431
2432 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2433 {
2434         unsigned int pkt_size, num_pkts, i;
2435         struct sk_buff *skb;
2436         unsigned char *packet;
2437         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2438         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2439         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2440         u16 tx_start_idx, tx_idx;
2441         u16 rx_start_idx, rx_idx;
2442         u16 pkt_prod, bd_prod;
2443         struct sw_tx_bd *tx_buf;
2444         struct eth_tx_start_bd *tx_start_bd;
2445         dma_addr_t mapping;
2446         union eth_rx_cqe *cqe;
2447         u8 cqe_fp_flags, cqe_fp_type;
2448         struct sw_rx_bd *rx_buf;
2449         u16 len;
2450         int rc = -ENODEV;
2451         u8 *data;
2452         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2453                                                        txdata->txq_index);
2454
2455         /* check the loopback mode */
2456         switch (loopback_mode) {
2457         case BNX2X_PHY_LOOPBACK:
2458                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2459                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2460                         return -EINVAL;
2461                 }
2462                 break;
2463         case BNX2X_MAC_LOOPBACK:
2464                 if (CHIP_IS_E3(bp)) {
2465                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2466                         if (bp->port.supported[cfg_idx] &
2467                             (SUPPORTED_10000baseT_Full |
2468                              SUPPORTED_20000baseMLD2_Full |
2469                              SUPPORTED_20000baseKR2_Full))
2470                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2471                         else
2472                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2473                 } else
2474                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2475
2476                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2477                 break;
2478         case BNX2X_EXT_LOOPBACK:
2479                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2480                         DP(BNX2X_MSG_ETHTOOL,
2481                            "Can't configure external loopback\n");
2482                         return -EINVAL;
2483                 }
2484                 break;
2485         default:
2486                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2487                 return -EINVAL;
2488         }
2489
2490         /* prepare the loopback packet */
2491         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2492                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2493         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2494         if (!skb) {
2495                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2496                 rc = -ENOMEM;
2497                 goto test_loopback_exit;
2498         }
2499         packet = skb_put(skb, pkt_size);
2500         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2501         eth_zero_addr(packet + ETH_ALEN);
2502         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2503         for (i = ETH_HLEN; i < pkt_size; i++)
2504                 packet[i] = (unsigned char) (i & 0xff);
2505         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2506                                  skb_headlen(skb), DMA_TO_DEVICE);
2507         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2508                 rc = -ENOMEM;
2509                 dev_kfree_skb(skb);
2510                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2511                 goto test_loopback_exit;
2512         }
2513
2514         /* send the loopback packet */
2515         num_pkts = 0;
2516         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2517         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2518
2519         netdev_tx_sent_queue(txq, skb->len);
2520
2521         pkt_prod = txdata->tx_pkt_prod++;
2522         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2523         tx_buf->first_bd = txdata->tx_bd_prod;
2524         tx_buf->skb = skb;
2525         tx_buf->flags = 0;
2526
2527         bd_prod = TX_BD(txdata->tx_bd_prod);
2528         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2529         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2530         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2531         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2532         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2533         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2534         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2535         SET_FLAG(tx_start_bd->general_data,
2536                  ETH_TX_START_BD_HDR_NBDS,
2537                  1);
2538         SET_FLAG(tx_start_bd->general_data,
2539                  ETH_TX_START_BD_PARSE_NBDS,
2540                  0);
2541
2542         /* turn on parsing and get a BD */
2543         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2544
2545         if (CHIP_IS_E1x(bp)) {
2546                 u16 global_data = 0;
2547                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2548                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2549                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2550                 SET_FLAG(global_data,
2551                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2552                 pbd_e1x->global_data = cpu_to_le16(global_data);
2553         } else {
2554                 u32 parsing_data = 0;
2555                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2556                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2557                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2558                 SET_FLAG(parsing_data,
2559                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2560                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2561         }
2562         wmb();
2563
2564         txdata->tx_db.data.prod += 2;
2565         barrier();
2566         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2567
2568         mmiowb();
2569         barrier();
2570
2571         num_pkts++;
2572         txdata->tx_bd_prod += 2; /* start + pbd */
2573
2574         udelay(100);
2575
2576         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2577         if (tx_idx != tx_start_idx + num_pkts)
2578                 goto test_loopback_exit;
2579
2580         /* Unlike HC IGU won't generate an interrupt for status block
2581          * updates that have been performed while interrupts were
2582          * disabled.
2583          */
2584         if (bp->common.int_block == INT_BLOCK_IGU) {
2585                 /* Disable local BHes to prevent a dead-lock situation between
2586                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2587                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2588                  */
2589                 local_bh_disable();
2590                 bnx2x_tx_int(bp, txdata);
2591                 local_bh_enable();
2592         }
2593
2594         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2595         if (rx_idx != rx_start_idx + num_pkts)
2596                 goto test_loopback_exit;
2597
2598         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2599         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2600         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2601         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2602                 goto test_loopback_rx_exit;
2603
2604         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2605         if (len != pkt_size)
2606                 goto test_loopback_rx_exit;
2607
2608         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2609         dma_sync_single_for_cpu(&bp->pdev->dev,
2610                                    dma_unmap_addr(rx_buf, mapping),
2611                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2612         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2613         for (i = ETH_HLEN; i < pkt_size; i++)
2614                 if (*(data + i) != (unsigned char) (i & 0xff))
2615                         goto test_loopback_rx_exit;
2616
2617         rc = 0;
2618
2619 test_loopback_rx_exit:
2620
2621         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2622         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2623         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2624         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2625
2626         /* Update producers */
2627         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2628                              fp_rx->rx_sge_prod);
2629
2630 test_loopback_exit:
2631         bp->link_params.loopback_mode = LOOPBACK_NONE;
2632
2633         return rc;
2634 }
2635
2636 static int bnx2x_test_loopback(struct bnx2x *bp)
2637 {
2638         int rc = 0, res;
2639
2640         if (BP_NOMCP(bp))
2641                 return rc;
2642
2643         if (!netif_running(bp->dev))
2644                 return BNX2X_LOOPBACK_FAILED;
2645
2646         bnx2x_netif_stop(bp, 1);
2647         bnx2x_acquire_phy_lock(bp);
2648
2649         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2650         if (res) {
2651                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2652                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2653         }
2654
2655         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2656         if (res) {
2657                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2658                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2659         }
2660
2661         bnx2x_release_phy_lock(bp);
2662         bnx2x_netif_start(bp);
2663
2664         return rc;
2665 }
2666
2667 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2668 {
2669         int rc;
2670         u8 is_serdes =
2671                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2672
2673         if (BP_NOMCP(bp))
2674                 return -ENODEV;
2675
2676         if (!netif_running(bp->dev))
2677                 return BNX2X_EXT_LOOPBACK_FAILED;
2678
2679         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2680         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2681         if (rc) {
2682                 DP(BNX2X_MSG_ETHTOOL,
2683                    "Can't perform self-test, nic_load (for external lb) failed\n");
2684                 return -ENODEV;
2685         }
2686         bnx2x_wait_for_link(bp, 1, is_serdes);
2687
2688         bnx2x_netif_stop(bp, 1);
2689
2690         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2691         if (rc)
2692                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2693
2694         bnx2x_netif_start(bp);
2695
2696         return rc;
2697 }
2698
2699 struct code_entry {
2700         u32 sram_start_addr;
2701         u32 code_attribute;
2702 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2703 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2704 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2705 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2706         u32 nvm_start_addr;
2707 };
2708
2709 #define CODE_ENTRY_MAX                  16
2710 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2711 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2712 #define NVRAM_DIR_OFFSET                0x14
2713
2714 #define EXTENDED_DIR_EXISTS(code)                                         \
2715         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2716          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2717
2718 #define CRC32_RESIDUAL                  0xdebb20e3
2719 #define CRC_BUFF_SIZE                   256
2720
2721 static int bnx2x_nvram_crc(struct bnx2x *bp,
2722                            int offset,
2723                            int size,
2724                            u8 *buff)
2725 {
2726         u32 crc = ~0;
2727         int rc = 0, done = 0;
2728
2729         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2730            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2731
2732         while (done < size) {
2733                 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2734
2735                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2736
2737                 if (rc)
2738                         return rc;
2739
2740                 crc = crc32_le(crc, buff, count);
2741                 done += count;
2742         }
2743
2744         if (crc != CRC32_RESIDUAL)
2745                 rc = -EINVAL;
2746
2747         return rc;
2748 }
2749
2750 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2751                                 struct code_entry *entry,
2752                                 u8 *buff)
2753 {
2754         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2755         u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2756         int rc;
2757
2758         /* Zero-length images and AFEX profiles do not have CRC */
2759         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2760                 return 0;
2761
2762         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2763         if (rc)
2764                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2765                    "image %x has failed crc test (rc %d)\n", type, rc);
2766
2767         return rc;
2768 }
2769
2770 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2771 {
2772         int rc;
2773         struct code_entry entry;
2774
2775         rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2776         if (rc)
2777                 return rc;
2778
2779         return bnx2x_test_nvram_dir(bp, &entry, buff);
2780 }
2781
2782 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2783 {
2784         u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2785         struct code_entry entry;
2786         int i;
2787
2788         rc = bnx2x_nvram_read32(bp,
2789                                 dir_offset +
2790                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2791                                 (u32 *)&entry, sizeof(entry));
2792         if (rc)
2793                 return rc;
2794
2795         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2796                 return 0;
2797
2798         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2799                                 &cnt, sizeof(u32));
2800         if (rc)
2801                 return rc;
2802
2803         dir_offset = entry.nvm_start_addr + 8;
2804
2805         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2806                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2807                                               sizeof(struct code_entry) * i,
2808                                           buff);
2809                 if (rc)
2810                         return rc;
2811         }
2812
2813         return 0;
2814 }
2815
2816 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2817 {
2818         u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2819         int i;
2820
2821         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2822
2823         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2824                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2825                                               sizeof(struct code_entry) * i,
2826                                           buff);
2827                 if (rc)
2828                         return rc;
2829         }
2830
2831         return bnx2x_test_nvram_ext_dirs(bp, buff);
2832 }
2833
2834 struct crc_pair {
2835         int offset;
2836         int size;
2837 };
2838
2839 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2840                                 const struct crc_pair *nvram_tbl, u8 *buf)
2841 {
2842         int i;
2843
2844         for (i = 0; nvram_tbl[i].size; i++) {
2845                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2846                                          nvram_tbl[i].size, buf);
2847                 if (rc) {
2848                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2849                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2850                            i, rc);
2851                         return rc;
2852                 }
2853         }
2854
2855         return 0;
2856 }
2857
2858 static int bnx2x_test_nvram(struct bnx2x *bp)
2859 {
2860         const struct crc_pair nvram_tbl[] = {
2861                 {     0,  0x14 }, /* bootstrap */
2862                 {  0x14,  0xec }, /* dir */
2863                 { 0x100, 0x350 }, /* manuf_info */
2864                 { 0x450,  0xf0 }, /* feature_info */
2865                 { 0x640,  0x64 }, /* upgrade_key_info */
2866                 { 0x708,  0x70 }, /* manuf_key_info */
2867                 {     0,     0 }
2868         };
2869         const struct crc_pair nvram_tbl2[] = {
2870                 { 0x7e8, 0x350 }, /* manuf_info2 */
2871                 { 0xb38,  0xf0 }, /* feature_info */
2872                 {     0,     0 }
2873         };
2874
2875         u8 *buf;
2876         int rc;
2877         u32 magic;
2878
2879         if (BP_NOMCP(bp))
2880                 return 0;
2881
2882         buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2883         if (!buf) {
2884                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2885                 rc = -ENOMEM;
2886                 goto test_nvram_exit;
2887         }
2888
2889         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2890         if (rc) {
2891                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2892                    "magic value read (rc %d)\n", rc);
2893                 goto test_nvram_exit;
2894         }
2895
2896         if (magic != 0x669955aa) {
2897                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2898                    "wrong magic value (0x%08x)\n", magic);
2899                 rc = -ENODEV;
2900                 goto test_nvram_exit;
2901         }
2902
2903         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2904         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2905         if (rc)
2906                 goto test_nvram_exit;
2907
2908         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2909                 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2910                            SHARED_HW_CFG_HIDE_PORT1;
2911
2912                 if (!hide) {
2913                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2914                            "Port 1 CRC test-set\n");
2915                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2916                         if (rc)
2917                                 goto test_nvram_exit;
2918                 }
2919         }
2920
2921         rc = bnx2x_test_nvram_dirs(bp, buf);
2922
2923 test_nvram_exit:
2924         kfree(buf);
2925         return rc;
2926 }
2927
2928 /* Send an EMPTY ramrod on the first queue */
2929 static int bnx2x_test_intr(struct bnx2x *bp)
2930 {
2931         struct bnx2x_queue_state_params params = {NULL};
2932
2933         if (!netif_running(bp->dev)) {
2934                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2935                    "cannot access eeprom when the interface is down\n");
2936                 return -ENODEV;
2937         }
2938
2939         params.q_obj = &bp->sp_objs->q_obj;
2940         params.cmd = BNX2X_Q_CMD_EMPTY;
2941
2942         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2943
2944         return bnx2x_queue_state_change(bp, &params);
2945 }
2946
2947 static void bnx2x_self_test(struct net_device *dev,
2948                             struct ethtool_test *etest, u64 *buf)
2949 {
2950         struct bnx2x *bp = netdev_priv(dev);
2951         u8 is_serdes, link_up;
2952         int rc, cnt = 0;
2953
2954         if (pci_num_vf(bp->pdev)) {
2955                 DP(BNX2X_MSG_IOV,
2956                    "VFs are enabled, can not perform self test\n");
2957                 return;
2958         }
2959
2960         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2961                 netdev_err(bp->dev,
2962                            "Handling parity error recovery. Try again later\n");
2963                 etest->flags |= ETH_TEST_FL_FAILED;
2964                 return;
2965         }
2966
2967         DP(BNX2X_MSG_ETHTOOL,
2968            "Self-test command parameters: offline = %d, external_lb = %d\n",
2969            (etest->flags & ETH_TEST_FL_OFFLINE),
2970            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2971
2972         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2973
2974         if (bnx2x_test_nvram(bp) != 0) {
2975                 if (!IS_MF(bp))
2976                         buf[4] = 1;
2977                 else
2978                         buf[0] = 1;
2979                 etest->flags |= ETH_TEST_FL_FAILED;
2980         }
2981
2982         if (!netif_running(dev)) {
2983                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2984                 return;
2985         }
2986
2987         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2988         link_up = bp->link_vars.link_up;
2989         /* offline tests are not supported in MF mode */
2990         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2991                 int port = BP_PORT(bp);
2992                 u32 val;
2993
2994                 /* save current value of input enable for TX port IF */
2995                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2996                 /* disable input for TX port IF */
2997                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2998
2999                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3000                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3001                 if (rc) {
3002                         etest->flags |= ETH_TEST_FL_FAILED;
3003                         DP(BNX2X_MSG_ETHTOOL,
3004                            "Can't perform self-test, nic_load (for offline) failed\n");
3005                         return;
3006                 }
3007
3008                 /* wait until link state is restored */
3009                 bnx2x_wait_for_link(bp, 1, is_serdes);
3010
3011                 if (bnx2x_test_registers(bp) != 0) {
3012                         buf[0] = 1;
3013                         etest->flags |= ETH_TEST_FL_FAILED;
3014                 }
3015                 if (bnx2x_test_memory(bp) != 0) {
3016                         buf[1] = 1;
3017                         etest->flags |= ETH_TEST_FL_FAILED;
3018                 }
3019
3020                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3021                 if (buf[2] != 0)
3022                         etest->flags |= ETH_TEST_FL_FAILED;
3023
3024                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3025                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3026                         if (buf[3] != 0)
3027                                 etest->flags |= ETH_TEST_FL_FAILED;
3028                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3029                 }
3030
3031                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3032
3033                 /* restore input for TX port IF */
3034                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3035                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3036                 if (rc) {
3037                         etest->flags |= ETH_TEST_FL_FAILED;
3038                         DP(BNX2X_MSG_ETHTOOL,
3039                            "Can't perform self-test, nic_load (for online) failed\n");
3040                         return;
3041                 }
3042                 /* wait until link state is restored */
3043                 bnx2x_wait_for_link(bp, link_up, is_serdes);
3044         }
3045
3046         if (bnx2x_test_intr(bp) != 0) {
3047                 if (!IS_MF(bp))
3048                         buf[5] = 1;
3049                 else
3050                         buf[1] = 1;
3051                 etest->flags |= ETH_TEST_FL_FAILED;
3052         }
3053
3054         if (link_up) {
3055                 cnt = 100;
3056                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3057                         msleep(20);
3058         }
3059
3060         if (!cnt) {
3061                 if (!IS_MF(bp))
3062                         buf[6] = 1;
3063                 else
3064                         buf[2] = 1;
3065                 etest->flags |= ETH_TEST_FL_FAILED;
3066         }
3067 }
3068
3069 #define IS_PORT_STAT(i) \
3070         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3071 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3072 #define HIDE_PORT_STAT(bp) \
3073                 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3074                  IS_VF(bp))
3075
3076 /* ethtool statistics are displayed for all regular ethernet queues and the
3077  * fcoe L2 queue if not disabled
3078  */
3079 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3080 {
3081         return BNX2X_NUM_ETH_QUEUES(bp);
3082 }
3083
3084 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3085 {
3086         struct bnx2x *bp = netdev_priv(dev);
3087         int i, num_strings = 0;
3088
3089         switch (stringset) {
3090         case ETH_SS_STATS:
3091                 if (is_multi(bp)) {
3092                         num_strings = bnx2x_num_stat_queues(bp) *
3093                                       BNX2X_NUM_Q_STATS;
3094                 } else
3095                         num_strings = 0;
3096                 if (HIDE_PORT_STAT(bp)) {
3097                         for (i = 0; i < BNX2X_NUM_STATS; i++)
3098                                 if (IS_FUNC_STAT(i))
3099                                         num_strings++;
3100                 } else
3101                         num_strings += BNX2X_NUM_STATS;
3102
3103                 return num_strings;
3104
3105         case ETH_SS_TEST:
3106                 return BNX2X_NUM_TESTS(bp);
3107
3108         case ETH_SS_PRIV_FLAGS:
3109                 return BNX2X_PRI_FLAG_LEN;
3110
3111         default:
3112                 return -EINVAL;
3113         }
3114 }
3115
3116 static u32 bnx2x_get_private_flags(struct net_device *dev)
3117 {
3118         struct bnx2x *bp = netdev_priv(dev);
3119         u32 flags = 0;
3120
3121         flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3122         flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3123         flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3124
3125         return flags;
3126 }
3127
3128 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3129 {
3130         struct bnx2x *bp = netdev_priv(dev);
3131         int i, j, k, start;
3132         char queue_name[MAX_QUEUE_NAME_LEN+1];
3133
3134         switch (stringset) {
3135         case ETH_SS_STATS:
3136                 k = 0;
3137                 if (is_multi(bp)) {
3138                         for_each_eth_queue(bp, i) {
3139                                 memset(queue_name, 0, sizeof(queue_name));
3140                                 sprintf(queue_name, "%d", i);
3141                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3142                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3143                                                 ETH_GSTRING_LEN,
3144                                                 bnx2x_q_stats_arr[j].string,
3145                                                 queue_name);
3146                                 k += BNX2X_NUM_Q_STATS;
3147                         }
3148                 }
3149
3150                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3151                         if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3152                                 continue;
3153                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3154                                    bnx2x_stats_arr[i].string);
3155                         j++;
3156                 }
3157
3158                 break;
3159
3160         case ETH_SS_TEST:
3161                 /* First 4 tests cannot be done in MF mode */
3162                 if (!IS_MF(bp))
3163                         start = 0;
3164                 else
3165                         start = 4;
3166                 memcpy(buf, bnx2x_tests_str_arr + start,
3167                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3168                 break;
3169
3170         case ETH_SS_PRIV_FLAGS:
3171                 memcpy(buf, bnx2x_private_arr,
3172                        ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3173                 break;
3174         }
3175 }
3176
3177 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3178                                     struct ethtool_stats *stats, u64 *buf)
3179 {
3180         struct bnx2x *bp = netdev_priv(dev);
3181         u32 *hw_stats, *offset;
3182         int i, j, k = 0;
3183
3184         if (is_multi(bp)) {
3185                 for_each_eth_queue(bp, i) {
3186                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3187                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3188                                 if (bnx2x_q_stats_arr[j].size == 0) {
3189                                         /* skip this counter */
3190                                         buf[k + j] = 0;
3191                                         continue;
3192                                 }
3193                                 offset = (hw_stats +
3194                                           bnx2x_q_stats_arr[j].offset);
3195                                 if (bnx2x_q_stats_arr[j].size == 4) {
3196                                         /* 4-byte counter */
3197                                         buf[k + j] = (u64) *offset;
3198                                         continue;
3199                                 }
3200                                 /* 8-byte counter */
3201                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3202                         }
3203                         k += BNX2X_NUM_Q_STATS;
3204                 }
3205         }
3206
3207         hw_stats = (u32 *)&bp->eth_stats;
3208         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3209                 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3210                         continue;
3211                 if (bnx2x_stats_arr[i].size == 0) {
3212                         /* skip this counter */
3213                         buf[k + j] = 0;
3214                         j++;
3215                         continue;
3216                 }
3217                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3218                 if (bnx2x_stats_arr[i].size == 4) {
3219                         /* 4-byte counter */
3220                         buf[k + j] = (u64) *offset;
3221                         j++;
3222                         continue;
3223                 }
3224                 /* 8-byte counter */
3225                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3226                 j++;
3227         }
3228 }
3229
3230 static int bnx2x_set_phys_id(struct net_device *dev,
3231                              enum ethtool_phys_id_state state)
3232 {
3233         struct bnx2x *bp = netdev_priv(dev);
3234
3235         if (!bnx2x_is_nvm_accessible(bp)) {
3236                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3237                    "cannot access eeprom when the interface is down\n");
3238                 return -EAGAIN;
3239         }
3240
3241         switch (state) {
3242         case ETHTOOL_ID_ACTIVE:
3243                 return 1;       /* cycle on/off once per second */
3244
3245         case ETHTOOL_ID_ON:
3246                 bnx2x_acquire_phy_lock(bp);
3247                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3248                               LED_MODE_ON, SPEED_1000);
3249                 bnx2x_release_phy_lock(bp);
3250                 break;
3251
3252         case ETHTOOL_ID_OFF:
3253                 bnx2x_acquire_phy_lock(bp);
3254                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3255                               LED_MODE_FRONT_PANEL_OFF, 0);
3256                 bnx2x_release_phy_lock(bp);
3257                 break;
3258
3259         case ETHTOOL_ID_INACTIVE:
3260                 bnx2x_acquire_phy_lock(bp);
3261                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3262                               LED_MODE_OPER,
3263                               bp->link_vars.line_speed);
3264                 bnx2x_release_phy_lock(bp);
3265         }
3266
3267         return 0;
3268 }
3269
3270 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3271 {
3272         switch (info->flow_type) {
3273         case TCP_V4_FLOW:
3274         case TCP_V6_FLOW:
3275                 info->data = RXH_IP_SRC | RXH_IP_DST |
3276                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3277                 break;
3278         case UDP_V4_FLOW:
3279                 if (bp->rss_conf_obj.udp_rss_v4)
3280                         info->data = RXH_IP_SRC | RXH_IP_DST |
3281                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3282                 else
3283                         info->data = RXH_IP_SRC | RXH_IP_DST;
3284                 break;
3285         case UDP_V6_FLOW:
3286                 if (bp->rss_conf_obj.udp_rss_v6)
3287                         info->data = RXH_IP_SRC | RXH_IP_DST |
3288                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3289                 else
3290                         info->data = RXH_IP_SRC | RXH_IP_DST;
3291                 break;
3292         case IPV4_FLOW:
3293         case IPV6_FLOW:
3294                 info->data = RXH_IP_SRC | RXH_IP_DST;
3295                 break;
3296         default:
3297                 info->data = 0;
3298                 break;
3299         }
3300
3301         return 0;
3302 }
3303
3304 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3305                            u32 *rules __always_unused)
3306 {
3307         struct bnx2x *bp = netdev_priv(dev);
3308
3309         switch (info->cmd) {
3310         case ETHTOOL_GRXRINGS:
3311                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3312                 return 0;
3313         case ETHTOOL_GRXFH:
3314                 return bnx2x_get_rss_flags(bp, info);
3315         default:
3316                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3317                 return -EOPNOTSUPP;
3318         }
3319 }
3320
3321 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3322 {
3323         int udp_rss_requested;
3324
3325         DP(BNX2X_MSG_ETHTOOL,
3326            "Set rss flags command parameters: flow type = %d, data = %llu\n",
3327            info->flow_type, info->data);
3328
3329         switch (info->flow_type) {
3330         case TCP_V4_FLOW:
3331         case TCP_V6_FLOW:
3332                 /* For TCP only 4-tupple hash is supported */
3333                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3334                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3335                         DP(BNX2X_MSG_ETHTOOL,
3336                            "Command parameters not supported\n");
3337                         return -EINVAL;
3338                 }
3339                 return 0;
3340
3341         case UDP_V4_FLOW:
3342         case UDP_V6_FLOW:
3343                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3344                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3345                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
3346                         udp_rss_requested = 1;
3347                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3348                         udp_rss_requested = 0;
3349                 else
3350                         return -EINVAL;
3351
3352                 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3353                         DP(BNX2X_MSG_ETHTOOL,
3354                            "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3355                         return -EINVAL;
3356                 }
3357
3358                 if ((info->flow_type == UDP_V4_FLOW) &&
3359                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3360                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3361                         DP(BNX2X_MSG_ETHTOOL,
3362                            "rss re-configured, UDP 4-tupple %s\n",
3363                            udp_rss_requested ? "enabled" : "disabled");
3364                         if (bp->state == BNX2X_STATE_OPEN)
3365                                 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3366                                                  true);
3367                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3368                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3369                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3370                         DP(BNX2X_MSG_ETHTOOL,
3371                            "rss re-configured, UDP 4-tupple %s\n",
3372                            udp_rss_requested ? "enabled" : "disabled");
3373                         if (bp->state == BNX2X_STATE_OPEN)
3374                                 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3375                                                  true);
3376                 }
3377                 return 0;
3378
3379         case IPV4_FLOW:
3380         case IPV6_FLOW:
3381                 /* For IP only 2-tupple hash is supported */
3382                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3383                         DP(BNX2X_MSG_ETHTOOL,
3384                            "Command parameters not supported\n");
3385                         return -EINVAL;
3386                 }
3387                 return 0;
3388
3389         case SCTP_V4_FLOW:
3390         case AH_ESP_V4_FLOW:
3391         case AH_V4_FLOW:
3392         case ESP_V4_FLOW:
3393         case SCTP_V6_FLOW:
3394         case AH_ESP_V6_FLOW:
3395         case AH_V6_FLOW:
3396         case ESP_V6_FLOW:
3397         case IP_USER_FLOW:
3398         case ETHER_FLOW:
3399                 /* RSS is not supported for these protocols */
3400                 if (info->data) {
3401                         DP(BNX2X_MSG_ETHTOOL,
3402                            "Command parameters not supported\n");
3403                         return -EINVAL;
3404                 }
3405                 return 0;
3406
3407         default:
3408                 return -EINVAL;
3409         }
3410 }
3411
3412 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3413 {
3414         struct bnx2x *bp = netdev_priv(dev);
3415
3416         switch (info->cmd) {
3417         case ETHTOOL_SRXFH:
3418                 return bnx2x_set_rss_flags(bp, info);
3419         default:
3420                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3421                 return -EOPNOTSUPP;
3422         }
3423 }
3424
3425 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3426 {
3427         return T_ETH_INDIRECTION_TABLE_SIZE;
3428 }
3429
3430 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3431                           u8 *hfunc)
3432 {
3433         struct bnx2x *bp = netdev_priv(dev);
3434         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3435         size_t i;
3436
3437         if (hfunc)
3438                 *hfunc = ETH_RSS_HASH_TOP;
3439         if (!indir)
3440                 return 0;
3441
3442         /* Get the current configuration of the RSS indirection table */
3443         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3444
3445         /*
3446          * We can't use a memcpy() as an internal storage of an
3447          * indirection table is a u8 array while indir->ring_index
3448          * points to an array of u32.
3449          *
3450          * Indirection table contains the FW Client IDs, so we need to
3451          * align the returned table to the Client ID of the leading RSS
3452          * queue.
3453          */
3454         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3455                 indir[i] = ind_table[i] - bp->fp->cl_id;
3456
3457         return 0;
3458 }
3459
3460 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3461                           const u8 *key, const u8 hfunc)
3462 {
3463         struct bnx2x *bp = netdev_priv(dev);
3464         size_t i;
3465
3466         /* We require at least one supported parameter to be changed and no
3467          * change in any of the unsupported parameters
3468          */
3469         if (key ||
3470             (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3471                 return -EOPNOTSUPP;
3472
3473         if (!indir)
3474                 return 0;
3475
3476         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3477                 /*
3478                  * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3479                  * as an internal storage of an indirection table is a u8 array
3480                  * while indir->ring_index points to an array of u32.
3481                  *
3482                  * Indirection table contains the FW Client IDs, so we need to
3483                  * align the received table to the Client ID of the leading RSS
3484                  * queue
3485                  */
3486                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3487         }
3488
3489         if (bp->state == BNX2X_STATE_OPEN)
3490                 return bnx2x_config_rss_eth(bp, false);
3491
3492         return 0;
3493 }
3494
3495 /**
3496  * bnx2x_get_channels - gets the number of RSS queues.
3497  *
3498  * @dev:                net device
3499  * @channels:           returns the number of max / current queues
3500  */
3501 static void bnx2x_get_channels(struct net_device *dev,
3502                                struct ethtool_channels *channels)
3503 {
3504         struct bnx2x *bp = netdev_priv(dev);
3505
3506         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3507         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3508 }
3509
3510 /**
3511  * bnx2x_change_num_queues - change the number of RSS queues.
3512  *
3513  * @bp:                 bnx2x private structure
3514  *
3515  * Re-configure interrupt mode to get the new number of MSI-X
3516  * vectors and re-add NAPI objects.
3517  */
3518 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3519 {
3520         bnx2x_disable_msi(bp);
3521         bp->num_ethernet_queues = num_rss;
3522         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3523         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3524         bnx2x_set_int_mode(bp);
3525 }
3526
3527 /**
3528  * bnx2x_set_channels - sets the number of RSS queues.
3529  *
3530  * @dev:                net device
3531  * @channels:           includes the number of queues requested
3532  */
3533 static int bnx2x_set_channels(struct net_device *dev,
3534                               struct ethtool_channels *channels)
3535 {
3536         struct bnx2x *bp = netdev_priv(dev);
3537
3538         DP(BNX2X_MSG_ETHTOOL,
3539            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3540            channels->rx_count, channels->tx_count, channels->other_count,
3541            channels->combined_count);
3542
3543         if (pci_num_vf(bp->pdev)) {
3544                 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3545                 return -EPERM;
3546         }
3547
3548         /* We don't support separate rx / tx channels.
3549          * We don't allow setting 'other' channels.
3550          */
3551         if (channels->rx_count || channels->tx_count || channels->other_count
3552             || (channels->combined_count == 0) ||
3553             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3554                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3555                 return -EINVAL;
3556         }
3557
3558         /* Check if there was a change in the active parameters */
3559         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3560                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3561                 return 0;
3562         }
3563
3564         /* Set the requested number of queues in bp context.
3565          * Note that the actual number of queues created during load may be
3566          * less than requested if memory is low.
3567          */
3568         if (unlikely(!netif_running(dev))) {
3569                 bnx2x_change_num_queues(bp, channels->combined_count);
3570                 return 0;
3571         }
3572         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3573         bnx2x_change_num_queues(bp, channels->combined_count);
3574         return bnx2x_nic_load(bp, LOAD_NORMAL);
3575 }
3576
3577 static int bnx2x_get_ts_info(struct net_device *dev,
3578                              struct ethtool_ts_info *info)
3579 {
3580         struct bnx2x *bp = netdev_priv(dev);
3581
3582         if (bp->flags & PTP_SUPPORTED) {
3583                 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3584                                         SOF_TIMESTAMPING_RX_SOFTWARE |
3585                                         SOF_TIMESTAMPING_SOFTWARE |
3586                                         SOF_TIMESTAMPING_TX_HARDWARE |
3587                                         SOF_TIMESTAMPING_RX_HARDWARE |
3588                                         SOF_TIMESTAMPING_RAW_HARDWARE;
3589
3590                 if (bp->ptp_clock)
3591                         info->phc_index = ptp_clock_index(bp->ptp_clock);
3592                 else
3593                         info->phc_index = -1;
3594
3595                 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3596                                    (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3597                                    (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3598                                    (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3599
3600                 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3601
3602                 return 0;
3603         }
3604
3605         return ethtool_op_get_ts_info(dev, info);
3606 }
3607
3608 static const struct ethtool_ops bnx2x_ethtool_ops = {
3609         .get_settings           = bnx2x_get_settings,
3610         .set_settings           = bnx2x_set_settings,
3611         .get_drvinfo            = bnx2x_get_drvinfo,
3612         .get_regs_len           = bnx2x_get_regs_len,
3613         .get_regs               = bnx2x_get_regs,
3614         .get_dump_flag          = bnx2x_get_dump_flag,
3615         .get_dump_data          = bnx2x_get_dump_data,
3616         .set_dump               = bnx2x_set_dump,
3617         .get_wol                = bnx2x_get_wol,
3618         .set_wol                = bnx2x_set_wol,
3619         .get_msglevel           = bnx2x_get_msglevel,
3620         .set_msglevel           = bnx2x_set_msglevel,
3621         .nway_reset             = bnx2x_nway_reset,
3622         .get_link               = bnx2x_get_link,
3623         .get_eeprom_len         = bnx2x_get_eeprom_len,
3624         .get_eeprom             = bnx2x_get_eeprom,
3625         .set_eeprom             = bnx2x_set_eeprom,
3626         .get_coalesce           = bnx2x_get_coalesce,
3627         .set_coalesce           = bnx2x_set_coalesce,
3628         .get_ringparam          = bnx2x_get_ringparam,
3629         .set_ringparam          = bnx2x_set_ringparam,
3630         .get_pauseparam         = bnx2x_get_pauseparam,
3631         .set_pauseparam         = bnx2x_set_pauseparam,
3632         .self_test              = bnx2x_self_test,
3633         .get_sset_count         = bnx2x_get_sset_count,
3634         .get_priv_flags         = bnx2x_get_private_flags,
3635         .get_strings            = bnx2x_get_strings,
3636         .set_phys_id            = bnx2x_set_phys_id,
3637         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3638         .get_rxnfc              = bnx2x_get_rxnfc,
3639         .set_rxnfc              = bnx2x_set_rxnfc,
3640         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3641         .get_rxfh               = bnx2x_get_rxfh,
3642         .set_rxfh               = bnx2x_set_rxfh,
3643         .get_channels           = bnx2x_get_channels,
3644         .set_channels           = bnx2x_set_channels,
3645         .get_module_info        = bnx2x_get_module_info,
3646         .get_module_eeprom      = bnx2x_get_module_eeprom,
3647         .get_eee                = bnx2x_get_eee,
3648         .set_eee                = bnx2x_set_eee,
3649         .get_ts_info            = bnx2x_get_ts_info,
3650 };
3651
3652 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3653         .get_settings           = bnx2x_get_vf_settings,
3654         .get_drvinfo            = bnx2x_get_drvinfo,
3655         .get_msglevel           = bnx2x_get_msglevel,
3656         .set_msglevel           = bnx2x_set_msglevel,
3657         .get_link               = bnx2x_get_link,
3658         .get_coalesce           = bnx2x_get_coalesce,
3659         .get_ringparam          = bnx2x_get_ringparam,
3660         .set_ringparam          = bnx2x_set_ringparam,
3661         .get_sset_count         = bnx2x_get_sset_count,
3662         .get_strings            = bnx2x_get_strings,
3663         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3664         .get_rxnfc              = bnx2x_get_rxnfc,
3665         .set_rxnfc              = bnx2x_set_rxnfc,
3666         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3667         .get_rxfh               = bnx2x_get_rxfh,
3668         .set_rxfh               = bnx2x_set_rxfh,
3669         .get_channels           = bnx2x_get_channels,
3670         .set_channels           = bnx2x_set_channels,
3671 };
3672
3673 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3674 {
3675         netdev->ethtool_ops = (IS_PF(bp)) ?
3676                 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3677 }