1 /* bnx2.c: QLogic bnx2 network driver.
3 * Copyright (c) 2004-2014 Broadcom Corporation
4 * Copyright (c) 2014-2015 QLogic Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
10 * Written by: Michael Chan (mchan@broadcom.com)
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
18 #include <linux/stringify.h>
19 #include <linux/kernel.h>
20 #include <linux/timer.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/bitops.h>
34 #include <linux/delay.h>
35 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/firmware.h>
50 #include <linux/log2.h>
51 #include <linux/aer.h>
52 #include <linux/crash_dump.h>
54 #if IS_ENABLED(CONFIG_CNIC)
61 #define DRV_MODULE_NAME "bnx2"
62 #define FW_MIPS_FILE_06 "/*(DEBLOBBED)*/"
63 #define FW_RV2P_FILE_06 "/*(DEBLOBBED)*/"
64 #define FW_MIPS_FILE_09 "/*(DEBLOBBED)*/"
65 #define FW_RV2P_FILE_09_Ax "/*(DEBLOBBED)*/"
66 #define FW_RV2P_FILE_09 "/*(DEBLOBBED)*/"
68 #define RUN_AT(x) (jiffies + (x))
70 /* Time in jiffies before concluding the transmitter is hung. */
71 #define TX_TIMEOUT (5*HZ)
73 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
74 MODULE_DESCRIPTION("QLogic BCM5706/5708/5709/5716 Driver");
75 MODULE_LICENSE("GPL");
78 static int disable_msi = 0;
80 module_param(disable_msi, int, 0444);
81 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97 /* indexed by board_t, above */
101 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
102 { "HP NC370T Multifunction Gigabit Server Adapter" },
103 { "HP NC370i Multifunction Gigabit Server Adapter" },
104 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
105 { "HP NC370F Multifunction Gigabit Server Adapter" },
106 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
107 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
108 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
109 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
110 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
111 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
114 static const struct pci_device_id bnx2_pci_tbl[] = {
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
118 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
124 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
133 { PCI_VENDOR_ID_BROADCOM, 0x163b,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
135 { PCI_VENDOR_ID_BROADCOM, 0x163c,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
140 static const struct flash_spec flash_table[] =
142 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
143 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
145 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
146 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
147 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
149 /* Expansion entry 0001 */
150 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
151 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
154 /* Saifun SA25F010 (non-buffered flash) */
155 /* strap, cfg1, & write1 need updates */
156 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
159 "Non-buffered flash (128kB)"},
160 /* Saifun SA25F020 (non-buffered flash) */
161 /* strap, cfg1, & write1 need updates */
162 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
163 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
164 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
165 "Non-buffered flash (256kB)"},
166 /* Expansion entry 0100 */
167 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
168 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
169 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
171 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
172 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
174 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
175 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
176 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
177 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
179 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
180 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
181 /* Saifun SA25F005 (non-buffered flash) */
182 /* strap, cfg1, & write1 need updates */
183 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
184 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
185 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
186 "Non-buffered flash (64kB)"},
188 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
189 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
190 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
192 /* Expansion entry 1001 */
193 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
197 /* Expansion entry 1010 */
198 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
200 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
202 /* ATMEL AT45DB011B (buffered flash) */
203 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
204 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
205 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
206 "Buffered flash (128kB)"},
207 /* Expansion entry 1100 */
208 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
210 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
212 /* Expansion entry 1101 */
213 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
214 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
215 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
217 /* Ateml Expansion entry 1110 */
218 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
219 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
220 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
221 "Entry 1110 (Atmel)"},
222 /* ATMEL AT45DB021B (buffered flash) */
223 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
224 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
225 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
226 "Buffered flash (256kB)"},
229 static const struct flash_spec flash_5709 = {
230 .flags = BNX2_NV_BUFFERED,
231 .page_bits = BCM5709_FLASH_PAGE_BITS,
232 .page_size = BCM5709_FLASH_PAGE_SIZE,
233 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
234 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
235 .name = "5709 Buffered flash (256kB)",
238 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
240 static void bnx2_init_napi(struct bnx2 *bp);
241 static void bnx2_del_napi(struct bnx2 *bp);
243 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
247 /* The ring uses 256 indices for 255 entries, one of them
248 * needs to be skipped.
250 diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
251 if (unlikely(diff >= BNX2_TX_DESC_CNT)) {
253 if (diff == BNX2_TX_DESC_CNT)
254 diff = BNX2_MAX_TX_DESC_CNT;
256 return bp->tx_ring_size - diff;
260 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
265 spin_lock_irqsave(&bp->indirect_lock, flags);
266 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
267 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
268 spin_unlock_irqrestore(&bp->indirect_lock, flags);
273 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
277 spin_lock_irqsave(&bp->indirect_lock, flags);
278 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
279 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
280 spin_unlock_irqrestore(&bp->indirect_lock, flags);
284 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
286 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
290 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
292 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
296 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
301 spin_lock_irqsave(&bp->indirect_lock, flags);
302 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
305 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
306 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
307 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
308 for (i = 0; i < 5; i++) {
309 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
310 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
315 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
316 BNX2_WR(bp, BNX2_CTX_DATA, val);
318 spin_unlock_irqrestore(&bp->indirect_lock, flags);
323 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
325 struct bnx2 *bp = netdev_priv(dev);
326 struct drv_ctl_io *io = &info->data.io;
329 case DRV_CTL_IO_WR_CMD:
330 bnx2_reg_wr_ind(bp, io->offset, io->data);
332 case DRV_CTL_IO_RD_CMD:
333 io->data = bnx2_reg_rd_ind(bp, io->offset);
335 case DRV_CTL_CTX_WR_CMD:
336 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
344 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
346 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
347 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
350 if (bp->flags & BNX2_FLAG_USING_MSIX) {
351 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
352 bnapi->cnic_present = 0;
353 sb_id = bp->irq_nvecs;
354 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
356 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
357 bnapi->cnic_tag = bnapi->last_status_idx;
358 bnapi->cnic_present = 1;
360 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
363 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
364 cp->irq_arr[0].status_blk = (void *)
365 ((unsigned long) bnapi->status_blk.msi +
366 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
367 cp->irq_arr[0].status_blk_num = sb_id;
371 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
374 struct bnx2 *bp = netdev_priv(dev);
375 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
380 if (cp->drv_state & CNIC_DRV_STATE_REGD)
383 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
386 bp->cnic_data = data;
387 rcu_assign_pointer(bp->cnic_ops, ops);
390 cp->drv_state = CNIC_DRV_STATE_REGD;
392 bnx2_setup_cnic_irq_info(bp);
397 static int bnx2_unregister_cnic(struct net_device *dev)
399 struct bnx2 *bp = netdev_priv(dev);
400 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
401 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
403 mutex_lock(&bp->cnic_lock);
405 bnapi->cnic_present = 0;
406 RCU_INIT_POINTER(bp->cnic_ops, NULL);
407 mutex_unlock(&bp->cnic_lock);
412 static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
414 struct bnx2 *bp = netdev_priv(dev);
415 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
417 if (!cp->max_iscsi_conn)
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
432 bnx2_cnic_stop(struct bnx2 *bp)
434 struct cnic_ops *c_ops;
435 struct cnic_ctl_info info;
437 mutex_lock(&bp->cnic_lock);
438 c_ops = rcu_dereference_protected(bp->cnic_ops,
439 lockdep_is_held(&bp->cnic_lock));
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
444 mutex_unlock(&bp->cnic_lock);
448 bnx2_cnic_start(struct bnx2 *bp)
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
453 mutex_lock(&bp->cnic_lock);
454 c_ops = rcu_dereference_protected(bp->cnic_ops,
455 lockdep_is_held(&bp->cnic_lock));
457 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
458 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
460 bnapi->cnic_tag = bnapi->last_status_idx;
462 info.cmd = CNIC_CTL_START_CMD;
463 c_ops->cnic_ctl(bp->cnic_data, &info);
465 mutex_unlock(&bp->cnic_lock);
471 bnx2_cnic_stop(struct bnx2 *bp)
476 bnx2_cnic_start(struct bnx2 *bp)
483 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
488 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
489 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
490 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
492 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
493 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
498 val1 = (bp->phy_addr << 21) | (reg << 16) |
499 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
500 BNX2_EMAC_MDIO_COMM_START_BUSY;
501 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
503 for (i = 0; i < 50; i++) {
506 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
507 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
510 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
511 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
517 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
526 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
527 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
528 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
530 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
531 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
540 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
545 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
546 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
547 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
549 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
550 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
555 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
556 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
557 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
558 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
560 for (i = 0; i < 50; i++) {
563 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
564 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
570 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
575 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
576 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
577 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
579 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
580 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
589 bnx2_disable_int(struct bnx2 *bp)
592 struct bnx2_napi *bnapi;
594 for (i = 0; i < bp->irq_nvecs; i++) {
595 bnapi = &bp->bnx2_napi[i];
596 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
597 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
599 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
603 bnx2_enable_int(struct bnx2 *bp)
606 struct bnx2_napi *bnapi;
608 for (i = 0; i < bp->irq_nvecs; i++) {
609 bnapi = &bp->bnx2_napi[i];
611 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
612 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
613 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
614 bnapi->last_status_idx);
616 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
617 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
618 bnapi->last_status_idx);
620 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
624 bnx2_disable_int_sync(struct bnx2 *bp)
628 atomic_inc(&bp->intr_sem);
629 if (!netif_running(bp->dev))
632 bnx2_disable_int(bp);
633 for (i = 0; i < bp->irq_nvecs; i++)
634 synchronize_irq(bp->irq_tbl[i].vector);
638 bnx2_napi_disable(struct bnx2 *bp)
642 for (i = 0; i < bp->irq_nvecs; i++)
643 napi_disable(&bp->bnx2_napi[i].napi);
647 bnx2_napi_enable(struct bnx2 *bp)
651 for (i = 0; i < bp->irq_nvecs; i++)
652 napi_enable(&bp->bnx2_napi[i].napi);
656 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
660 if (netif_running(bp->dev)) {
661 bnx2_napi_disable(bp);
662 netif_tx_disable(bp->dev);
664 bnx2_disable_int_sync(bp);
665 netif_carrier_off(bp->dev); /* prevent tx timeout */
669 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
671 if (atomic_dec_and_test(&bp->intr_sem)) {
672 if (netif_running(bp->dev)) {
673 netif_tx_wake_all_queues(bp->dev);
674 spin_lock_bh(&bp->phy_lock);
676 netif_carrier_on(bp->dev);
677 spin_unlock_bh(&bp->phy_lock);
678 bnx2_napi_enable(bp);
687 bnx2_free_tx_mem(struct bnx2 *bp)
691 for (i = 0; i < bp->num_tx_rings; i++) {
692 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
693 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
695 if (txr->tx_desc_ring) {
696 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
698 txr->tx_desc_mapping);
699 txr->tx_desc_ring = NULL;
701 kfree(txr->tx_buf_ring);
702 txr->tx_buf_ring = NULL;
707 bnx2_free_rx_mem(struct bnx2 *bp)
711 for (i = 0; i < bp->num_rx_rings; i++) {
712 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
713 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
716 for (j = 0; j < bp->rx_max_ring; j++) {
717 if (rxr->rx_desc_ring[j])
718 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
719 rxr->rx_desc_ring[j],
720 rxr->rx_desc_mapping[j]);
721 rxr->rx_desc_ring[j] = NULL;
723 vfree(rxr->rx_buf_ring);
724 rxr->rx_buf_ring = NULL;
726 for (j = 0; j < bp->rx_max_pg_ring; j++) {
727 if (rxr->rx_pg_desc_ring[j])
728 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
729 rxr->rx_pg_desc_ring[j],
730 rxr->rx_pg_desc_mapping[j]);
731 rxr->rx_pg_desc_ring[j] = NULL;
733 vfree(rxr->rx_pg_ring);
734 rxr->rx_pg_ring = NULL;
739 bnx2_alloc_tx_mem(struct bnx2 *bp)
743 for (i = 0; i < bp->num_tx_rings; i++) {
744 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
745 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
747 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
748 if (!txr->tx_buf_ring)
752 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
753 &txr->tx_desc_mapping, GFP_KERNEL);
754 if (!txr->tx_desc_ring)
761 bnx2_alloc_rx_mem(struct bnx2 *bp)
765 for (i = 0; i < bp->num_rx_rings; i++) {
766 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
767 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
771 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));
772 if (!rxr->rx_buf_ring)
775 for (j = 0; j < bp->rx_max_ring; j++) {
776 rxr->rx_desc_ring[j] =
777 dma_alloc_coherent(&bp->pdev->dev,
779 &rxr->rx_desc_mapping[j],
781 if (!rxr->rx_desc_ring[j])
786 if (bp->rx_pg_ring_size) {
788 vzalloc(array_size(SW_RXPG_RING_SIZE,
789 bp->rx_max_pg_ring));
790 if (!rxr->rx_pg_ring)
795 for (j = 0; j < bp->rx_max_pg_ring; j++) {
796 rxr->rx_pg_desc_ring[j] =
797 dma_alloc_coherent(&bp->pdev->dev,
799 &rxr->rx_pg_desc_mapping[j],
801 if (!rxr->rx_pg_desc_ring[j])
810 bnx2_free_stats_blk(struct net_device *dev)
812 struct bnx2 *bp = netdev_priv(dev);
814 if (bp->status_blk) {
815 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
817 bp->status_blk_mapping);
818 bp->status_blk = NULL;
819 bp->stats_blk = NULL;
824 bnx2_alloc_stats_blk(struct net_device *dev)
828 struct bnx2 *bp = netdev_priv(dev);
830 /* Combine status and statistics blocks into one allocation. */
831 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
832 if (bp->flags & BNX2_FLAG_MSIX_CAP)
833 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
834 BNX2_SBLK_MSIX_ALIGN_SIZE);
835 bp->status_stats_size = status_blk_size +
836 sizeof(struct statistics_block);
837 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
838 &bp->status_blk_mapping, GFP_KERNEL);
842 bp->status_blk = status_blk;
843 bp->stats_blk = status_blk + status_blk_size;
844 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
850 bnx2_free_mem(struct bnx2 *bp)
853 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
855 bnx2_free_tx_mem(bp);
856 bnx2_free_rx_mem(bp);
858 for (i = 0; i < bp->ctx_pages; i++) {
859 if (bp->ctx_blk[i]) {
860 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,
862 bp->ctx_blk_mapping[i]);
863 bp->ctx_blk[i] = NULL;
867 if (bnapi->status_blk.msi)
868 bnapi->status_blk.msi = NULL;
872 bnx2_alloc_mem(struct bnx2 *bp)
875 struct bnx2_napi *bnapi;
877 bnapi = &bp->bnx2_napi[0];
878 bnapi->status_blk.msi = bp->status_blk;
879 bnapi->hw_tx_cons_ptr =
880 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
881 bnapi->hw_rx_cons_ptr =
882 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
883 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
884 for (i = 1; i < bp->irq_nvecs; i++) {
885 struct status_block_msix *sblk;
887 bnapi = &bp->bnx2_napi[i];
889 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
890 bnapi->status_blk.msix = sblk;
891 bnapi->hw_tx_cons_ptr =
892 &sblk->status_tx_quick_consumer_index;
893 bnapi->hw_rx_cons_ptr =
894 &sblk->status_rx_quick_consumer_index;
895 bnapi->int_num = i << 24;
899 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
900 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;
901 if (bp->ctx_pages == 0)
903 for (i = 0; i < bp->ctx_pages; i++) {
904 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
906 &bp->ctx_blk_mapping[i],
913 err = bnx2_alloc_rx_mem(bp);
917 err = bnx2_alloc_tx_mem(bp);
929 bnx2_report_fw_link(struct bnx2 *bp)
931 u32 fw_link_status = 0;
933 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
939 switch (bp->line_speed) {
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_10HALF;
944 fw_link_status = BNX2_LINK_STATUS_10FULL;
947 if (bp->duplex == DUPLEX_HALF)
948 fw_link_status = BNX2_LINK_STATUS_100HALF;
950 fw_link_status = BNX2_LINK_STATUS_100FULL;
953 if (bp->duplex == DUPLEX_HALF)
954 fw_link_status = BNX2_LINK_STATUS_1000HALF;
956 fw_link_status = BNX2_LINK_STATUS_1000FULL;
959 if (bp->duplex == DUPLEX_HALF)
960 fw_link_status = BNX2_LINK_STATUS_2500HALF;
962 fw_link_status = BNX2_LINK_STATUS_2500FULL;
966 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
969 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
971 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
972 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
974 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
975 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
976 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
978 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
982 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
984 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
988 bnx2_xceiver_str(struct bnx2 *bp)
990 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
991 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
996 bnx2_report_link(struct bnx2 *bp)
999 netif_carrier_on(bp->dev);
1000 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
1001 bnx2_xceiver_str(bp),
1003 bp->duplex == DUPLEX_FULL ? "full" : "half");
1005 if (bp->flow_ctrl) {
1006 if (bp->flow_ctrl & FLOW_CTRL_RX) {
1007 pr_cont(", receive ");
1008 if (bp->flow_ctrl & FLOW_CTRL_TX)
1009 pr_cont("& transmit ");
1012 pr_cont(", transmit ");
1014 pr_cont("flow control ON");
1018 netif_carrier_off(bp->dev);
1019 netdev_err(bp->dev, "NIC %s Link is Down\n",
1020 bnx2_xceiver_str(bp));
1023 bnx2_report_fw_link(bp);
1027 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1029 u32 local_adv, remote_adv;
1032 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1033 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1035 if (bp->duplex == DUPLEX_FULL) {
1036 bp->flow_ctrl = bp->req_flow_ctrl;
1041 if (bp->duplex != DUPLEX_FULL) {
1045 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1046 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
1049 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1050 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1051 bp->flow_ctrl |= FLOW_CTRL_TX;
1052 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1053 bp->flow_ctrl |= FLOW_CTRL_RX;
1057 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1058 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1060 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1061 u32 new_local_adv = 0;
1062 u32 new_remote_adv = 0;
1064 if (local_adv & ADVERTISE_1000XPAUSE)
1065 new_local_adv |= ADVERTISE_PAUSE_CAP;
1066 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1067 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1068 if (remote_adv & ADVERTISE_1000XPAUSE)
1069 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1070 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1071 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1073 local_adv = new_local_adv;
1074 remote_adv = new_remote_adv;
1077 /* See Table 28B-3 of 802.3ab-1999 spec. */
1078 if (local_adv & ADVERTISE_PAUSE_CAP) {
1079 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1080 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1081 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1083 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1084 bp->flow_ctrl = FLOW_CTRL_RX;
1088 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1089 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1093 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1094 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1095 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1097 bp->flow_ctrl = FLOW_CTRL_TX;
1103 bnx2_5709s_linkup(struct bnx2 *bp)
1109 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1110 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1111 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1113 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1114 bp->line_speed = bp->req_line_speed;
1115 bp->duplex = bp->req_duplex;
1118 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1120 case MII_BNX2_GP_TOP_AN_SPEED_10:
1121 bp->line_speed = SPEED_10;
1123 case MII_BNX2_GP_TOP_AN_SPEED_100:
1124 bp->line_speed = SPEED_100;
1126 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1127 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1128 bp->line_speed = SPEED_1000;
1130 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1131 bp->line_speed = SPEED_2500;
1134 if (val & MII_BNX2_GP_TOP_AN_FD)
1135 bp->duplex = DUPLEX_FULL;
1137 bp->duplex = DUPLEX_HALF;
1142 bnx2_5708s_linkup(struct bnx2 *bp)
1147 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1148 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1149 case BCM5708S_1000X_STAT1_SPEED_10:
1150 bp->line_speed = SPEED_10;
1152 case BCM5708S_1000X_STAT1_SPEED_100:
1153 bp->line_speed = SPEED_100;
1155 case BCM5708S_1000X_STAT1_SPEED_1G:
1156 bp->line_speed = SPEED_1000;
1158 case BCM5708S_1000X_STAT1_SPEED_2G5:
1159 bp->line_speed = SPEED_2500;
1162 if (val & BCM5708S_1000X_STAT1_FD)
1163 bp->duplex = DUPLEX_FULL;
1165 bp->duplex = DUPLEX_HALF;
1171 bnx2_5706s_linkup(struct bnx2 *bp)
1173 u32 bmcr, local_adv, remote_adv, common;
1176 bp->line_speed = SPEED_1000;
1178 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1179 if (bmcr & BMCR_FULLDPLX) {
1180 bp->duplex = DUPLEX_FULL;
1183 bp->duplex = DUPLEX_HALF;
1186 if (!(bmcr & BMCR_ANENABLE)) {
1190 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1191 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1193 common = local_adv & remote_adv;
1194 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1196 if (common & ADVERTISE_1000XFULL) {
1197 bp->duplex = DUPLEX_FULL;
1200 bp->duplex = DUPLEX_HALF;
1208 bnx2_copper_linkup(struct bnx2 *bp)
1212 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;
1214 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1215 if (bmcr & BMCR_ANENABLE) {
1216 u32 local_adv, remote_adv, common;
1218 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1219 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1221 common = local_adv & (remote_adv >> 2);
1222 if (common & ADVERTISE_1000FULL) {
1223 bp->line_speed = SPEED_1000;
1224 bp->duplex = DUPLEX_FULL;
1226 else if (common & ADVERTISE_1000HALF) {
1227 bp->line_speed = SPEED_1000;
1228 bp->duplex = DUPLEX_HALF;
1231 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1232 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1234 common = local_adv & remote_adv;
1235 if (common & ADVERTISE_100FULL) {
1236 bp->line_speed = SPEED_100;
1237 bp->duplex = DUPLEX_FULL;
1239 else if (common & ADVERTISE_100HALF) {
1240 bp->line_speed = SPEED_100;
1241 bp->duplex = DUPLEX_HALF;
1243 else if (common & ADVERTISE_10FULL) {
1244 bp->line_speed = SPEED_10;
1245 bp->duplex = DUPLEX_FULL;
1247 else if (common & ADVERTISE_10HALF) {
1248 bp->line_speed = SPEED_10;
1249 bp->duplex = DUPLEX_HALF;
1258 if (bmcr & BMCR_SPEED100) {
1259 bp->line_speed = SPEED_100;
1262 bp->line_speed = SPEED_10;
1264 if (bmcr & BMCR_FULLDPLX) {
1265 bp->duplex = DUPLEX_FULL;
1268 bp->duplex = DUPLEX_HALF;
1275 bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);
1276 if (ext_status & EXT_STATUS_MDIX)
1277 bp->phy_flags |= BNX2_PHY_FLAG_MDIX;
1284 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1286 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1288 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1289 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1292 if (bp->flow_ctrl & FLOW_CTRL_TX)
1293 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
1295 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1299 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1304 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1307 bnx2_init_rx_context(bp, cid);
1312 bnx2_set_mac_link(struct bnx2 *bp)
1316 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1317 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1318 (bp->duplex == DUPLEX_HALF)) {
1319 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1322 /* Configure the EMAC mode register. */
1323 val = BNX2_RD(bp, BNX2_EMAC_MODE);
1325 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1326 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1327 BNX2_EMAC_MODE_25G_MODE);
1330 switch (bp->line_speed) {
1332 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {
1333 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1338 val |= BNX2_EMAC_MODE_PORT_MII;
1341 val |= BNX2_EMAC_MODE_25G_MODE;
1344 val |= BNX2_EMAC_MODE_PORT_GMII;
1349 val |= BNX2_EMAC_MODE_PORT_GMII;
1352 /* Set the MAC to operate in the appropriate duplex mode. */
1353 if (bp->duplex == DUPLEX_HALF)
1354 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1355 BNX2_WR(bp, BNX2_EMAC_MODE, val);
1357 /* Enable/disable rx PAUSE. */
1358 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1360 if (bp->flow_ctrl & FLOW_CTRL_RX)
1361 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1362 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1364 /* Enable/disable tx PAUSE. */
1365 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
1366 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1368 if (bp->flow_ctrl & FLOW_CTRL_TX)
1369 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1370 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
1372 /* Acknowledge the interrupt. */
1373 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1375 bnx2_init_all_rx_contexts(bp);
1379 bnx2_enable_bmsr1(struct bnx2 *bp)
1381 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1382 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
1383 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1384 MII_BNX2_BLK_ADDR_GP_STATUS);
1388 bnx2_disable_bmsr1(struct bnx2 *bp)
1390 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1391 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
1392 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1393 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1397 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1402 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1405 if (bp->autoneg & AUTONEG_SPEED)
1406 bp->advertising |= ADVERTISED_2500baseX_Full;
1408 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1409 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1411 bnx2_read_phy(bp, bp->mii_up1, &up1);
1412 if (!(up1 & BCM5708S_UP1_2G5)) {
1413 up1 |= BCM5708S_UP1_2G5;
1414 bnx2_write_phy(bp, bp->mii_up1, up1);
1418 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1419 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1420 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1426 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1431 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1434 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1435 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1437 bnx2_read_phy(bp, bp->mii_up1, &up1);
1438 if (up1 & BCM5708S_UP1_2G5) {
1439 up1 &= ~BCM5708S_UP1_2G5;
1440 bnx2_write_phy(bp, bp->mii_up1, up1);
1444 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1445 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1446 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1452 bnx2_enable_forced_2g5(struct bnx2 *bp)
1457 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1460 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
1463 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1464 MII_BNX2_BLK_ADDR_SERDES_DIG);
1465 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1466 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1467 val |= MII_BNX2_SD_MISC1_FORCE |
1468 MII_BNX2_SD_MISC1_FORCE_2_5G;
1469 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1472 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1473 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1474 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1476 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
1477 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1479 bmcr |= BCM5708S_BMCR_FORCE_2500;
1487 if (bp->autoneg & AUTONEG_SPEED) {
1488 bmcr &= ~BMCR_ANENABLE;
1489 if (bp->req_duplex == DUPLEX_FULL)
1490 bmcr |= BMCR_FULLDPLX;
1492 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1496 bnx2_disable_forced_2g5(struct bnx2 *bp)
1501 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1504 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
1507 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1508 MII_BNX2_BLK_ADDR_SERDES_DIG);
1509 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1510 val &= ~MII_BNX2_SD_MISC1_FORCE;
1511 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1514 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1515 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1516 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1518 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
1519 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1521 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1529 if (bp->autoneg & AUTONEG_SPEED)
1530 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1531 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1535 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1539 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1540 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1542 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1544 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1548 bnx2_set_link(struct bnx2 *bp)
1553 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1558 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1561 link_up = bp->link_up;
1563 bnx2_enable_bmsr1(bp);
1564 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1565 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1566 bnx2_disable_bmsr1(bp);
1568 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1569 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {
1572 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1573 bnx2_5706s_force_link_dn(bp, 0);
1574 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1576 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
1578 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1579 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1580 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1582 if ((val & BNX2_EMAC_STATUS_LINK) &&
1583 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1584 bmsr |= BMSR_LSTATUS;
1586 bmsr &= ~BMSR_LSTATUS;
1589 if (bmsr & BMSR_LSTATUS) {
1592 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1593 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
1594 bnx2_5706s_linkup(bp);
1595 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
1596 bnx2_5708s_linkup(bp);
1597 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1598 bnx2_5709s_linkup(bp);
1601 bnx2_copper_linkup(bp);
1603 bnx2_resolve_flow_ctrl(bp);
1606 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1607 (bp->autoneg & AUTONEG_SPEED))
1608 bnx2_disable_forced_2g5(bp);
1610 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1613 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1614 bmcr |= BMCR_ANENABLE;
1615 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1617 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1622 if (bp->link_up != link_up) {
1623 bnx2_report_link(bp);
1626 bnx2_set_mac_link(bp);
1632 bnx2_reset_phy(struct bnx2 *bp)
1637 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1639 #define PHY_RESET_MAX_WAIT 100
1640 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1643 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1644 if (!(reg & BMCR_RESET)) {
1649 if (i == PHY_RESET_MAX_WAIT) {
1656 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1660 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1661 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1663 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1664 adv = ADVERTISE_1000XPAUSE;
1667 adv = ADVERTISE_PAUSE_CAP;
1670 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1671 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1672 adv = ADVERTISE_1000XPSE_ASYM;
1675 adv = ADVERTISE_PAUSE_ASYM;
1678 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1679 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1680 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1683 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1689 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1692 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1693 __releases(&bp->phy_lock)
1694 __acquires(&bp->phy_lock)
1696 u32 speed_arg = 0, pause_adv;
1698 pause_adv = bnx2_phy_get_pause_adv(bp);
1700 if (bp->autoneg & AUTONEG_SPEED) {
1701 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1702 if (bp->advertising & ADVERTISED_10baseT_Half)
1703 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1704 if (bp->advertising & ADVERTISED_10baseT_Full)
1705 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1706 if (bp->advertising & ADVERTISED_100baseT_Half)
1707 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1708 if (bp->advertising & ADVERTISED_100baseT_Full)
1709 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1710 if (bp->advertising & ADVERTISED_1000baseT_Full)
1711 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1712 if (bp->advertising & ADVERTISED_2500baseX_Full)
1713 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1715 if (bp->req_line_speed == SPEED_2500)
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1717 else if (bp->req_line_speed == SPEED_1000)
1718 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1719 else if (bp->req_line_speed == SPEED_100) {
1720 if (bp->req_duplex == DUPLEX_FULL)
1721 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1723 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1724 } else if (bp->req_line_speed == SPEED_10) {
1725 if (bp->req_duplex == DUPLEX_FULL)
1726 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1728 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1732 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1733 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1734 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1735 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1737 if (port == PORT_TP)
1738 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1739 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1741 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1743 spin_unlock_bh(&bp->phy_lock);
1744 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1745 spin_lock_bh(&bp->phy_lock);
1751 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1752 __releases(&bp->phy_lock)
1753 __acquires(&bp->phy_lock)
1758 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1759 return bnx2_setup_remote_phy(bp, port);
1761 if (!(bp->autoneg & AUTONEG_SPEED)) {
1763 int force_link_down = 0;
1765 if (bp->req_line_speed == SPEED_2500) {
1766 if (!bnx2_test_and_enable_2g5(bp))
1767 force_link_down = 1;
1768 } else if (bp->req_line_speed == SPEED_1000) {
1769 if (bnx2_test_and_disable_2g5(bp))
1770 force_link_down = 1;
1772 bnx2_read_phy(bp, bp->mii_adv, &adv);
1773 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1775 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1776 new_bmcr = bmcr & ~BMCR_ANENABLE;
1777 new_bmcr |= BMCR_SPEED1000;
1779 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
1780 if (bp->req_line_speed == SPEED_2500)
1781 bnx2_enable_forced_2g5(bp);
1782 else if (bp->req_line_speed == SPEED_1000) {
1783 bnx2_disable_forced_2g5(bp);
1784 new_bmcr &= ~0x2000;
1787 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
1788 if (bp->req_line_speed == SPEED_2500)
1789 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1791 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1794 if (bp->req_duplex == DUPLEX_FULL) {
1795 adv |= ADVERTISE_1000XFULL;
1796 new_bmcr |= BMCR_FULLDPLX;
1799 adv |= ADVERTISE_1000XHALF;
1800 new_bmcr &= ~BMCR_FULLDPLX;
1802 if ((new_bmcr != bmcr) || (force_link_down)) {
1803 /* Force a link down visible on the other side */
1805 bnx2_write_phy(bp, bp->mii_adv, adv &
1806 ~(ADVERTISE_1000XFULL |
1807 ADVERTISE_1000XHALF));
1808 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1809 BMCR_ANRESTART | BMCR_ANENABLE);
1812 netif_carrier_off(bp->dev);
1813 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1814 bnx2_report_link(bp);
1816 bnx2_write_phy(bp, bp->mii_adv, adv);
1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1819 bnx2_resolve_flow_ctrl(bp);
1820 bnx2_set_mac_link(bp);
1825 bnx2_test_and_enable_2g5(bp);
1827 if (bp->advertising & ADVERTISED_1000baseT_Full)
1828 new_adv |= ADVERTISE_1000XFULL;
1830 new_adv |= bnx2_phy_get_pause_adv(bp);
1832 bnx2_read_phy(bp, bp->mii_adv, &adv);
1833 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1835 bp->serdes_an_pending = 0;
1836 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1837 /* Force a link down visible on the other side */
1839 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1840 spin_unlock_bh(&bp->phy_lock);
1842 spin_lock_bh(&bp->phy_lock);
1845 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1846 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1848 /* Speed up link-up time when the link partner
1849 * does not autonegotiate which is very common
1850 * in blade servers. Some blade servers use
1851 * IPMI for kerboard input and it's important
1852 * to minimize link disruptions. Autoneg. involves
1853 * exchanging base pages plus 3 next pages and
1854 * normally completes in about 120 msec.
1856 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1857 bp->serdes_an_pending = 1;
1858 mod_timer(&bp->timer, jiffies + bp->current_interval);
1860 bnx2_resolve_flow_ctrl(bp);
1861 bnx2_set_mac_link(bp);
1867 #define ETHTOOL_ALL_FIBRE_SPEED \
1868 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1869 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1870 (ADVERTISED_1000baseT_Full)
1872 #define ETHTOOL_ALL_COPPER_SPEED \
1873 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1874 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1875 ADVERTISED_1000baseT_Full)
1877 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1878 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1880 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1883 bnx2_set_default_remote_link(struct bnx2 *bp)
1887 if (bp->phy_port == PORT_TP)
1888 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1890 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1892 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1893 bp->req_line_speed = 0;
1894 bp->autoneg |= AUTONEG_SPEED;
1895 bp->advertising = ADVERTISED_Autoneg;
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1897 bp->advertising |= ADVERTISED_10baseT_Half;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1899 bp->advertising |= ADVERTISED_10baseT_Full;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->advertising |= ADVERTISED_100baseT_Half;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1903 bp->advertising |= ADVERTISED_100baseT_Full;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1905 bp->advertising |= ADVERTISED_1000baseT_Full;
1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1907 bp->advertising |= ADVERTISED_2500baseX_Full;
1910 bp->advertising = 0;
1911 bp->req_duplex = DUPLEX_FULL;
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1913 bp->req_line_speed = SPEED_10;
1914 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1915 bp->req_duplex = DUPLEX_HALF;
1917 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1918 bp->req_line_speed = SPEED_100;
1919 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1920 bp->req_duplex = DUPLEX_HALF;
1922 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1923 bp->req_line_speed = SPEED_1000;
1924 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1925 bp->req_line_speed = SPEED_2500;
1930 bnx2_set_default_link(struct bnx2 *bp)
1932 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1933 bnx2_set_default_remote_link(bp);
1937 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1938 bp->req_line_speed = 0;
1939 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1942 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1944 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1945 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1946 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1948 bp->req_line_speed = bp->line_speed = SPEED_1000;
1949 bp->req_duplex = DUPLEX_FULL;
1952 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1956 bnx2_send_heart_beat(struct bnx2 *bp)
1961 spin_lock(&bp->indirect_lock);
1962 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1963 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1964 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1965 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1966 spin_unlock(&bp->indirect_lock);
1970 bnx2_remote_phy_event(struct bnx2 *bp)
1973 u8 link_up = bp->link_up;
1976 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1978 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1979 bnx2_send_heart_beat(bp);
1981 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1983 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1989 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1990 bp->duplex = DUPLEX_FULL;
1992 case BNX2_LINK_STATUS_10HALF:
1993 bp->duplex = DUPLEX_HALF;
1995 case BNX2_LINK_STATUS_10FULL:
1996 bp->line_speed = SPEED_10;
1998 case BNX2_LINK_STATUS_100HALF:
1999 bp->duplex = DUPLEX_HALF;
2001 case BNX2_LINK_STATUS_100BASE_T4:
2002 case BNX2_LINK_STATUS_100FULL:
2003 bp->line_speed = SPEED_100;
2005 case BNX2_LINK_STATUS_1000HALF:
2006 bp->duplex = DUPLEX_HALF;
2008 case BNX2_LINK_STATUS_1000FULL:
2009 bp->line_speed = SPEED_1000;
2011 case BNX2_LINK_STATUS_2500HALF:
2012 bp->duplex = DUPLEX_HALF;
2014 case BNX2_LINK_STATUS_2500FULL:
2015 bp->line_speed = SPEED_2500;
2023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2025 if (bp->duplex == DUPLEX_FULL)
2026 bp->flow_ctrl = bp->req_flow_ctrl;
2028 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2029 bp->flow_ctrl |= FLOW_CTRL_TX;
2030 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2031 bp->flow_ctrl |= FLOW_CTRL_RX;
2034 old_port = bp->phy_port;
2035 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2036 bp->phy_port = PORT_FIBRE;
2038 bp->phy_port = PORT_TP;
2040 if (old_port != bp->phy_port)
2041 bnx2_set_default_link(bp);
2044 if (bp->link_up != link_up)
2045 bnx2_report_link(bp);
2047 bnx2_set_mac_link(bp);
2051 bnx2_set_remote_link(struct bnx2 *bp)
2055 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2057 case BNX2_FW_EVT_CODE_LINK_EVENT:
2058 bnx2_remote_phy_event(bp);
2060 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2062 bnx2_send_heart_beat(bp);
2069 bnx2_setup_copper_phy(struct bnx2 *bp)
2070 __releases(&bp->phy_lock)
2071 __acquires(&bp->phy_lock)
2073 u32 bmcr, adv_reg, new_adv = 0;
2076 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2078 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2079 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2080 ADVERTISE_PAUSE_ASYM);
2082 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);
2084 if (bp->autoneg & AUTONEG_SPEED) {
2086 u32 new_adv1000 = 0;
2088 new_adv |= bnx2_phy_get_pause_adv(bp);
2090 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2091 adv1000_reg &= PHY_ALL_1000_SPEED;
2093 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
2094 if ((adv1000_reg != new_adv1000) ||
2095 (adv_reg != new_adv) ||
2096 ((bmcr & BMCR_ANENABLE) == 0)) {
2098 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2099 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
2100 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2103 else if (bp->link_up) {
2104 /* Flow ctrl may have changed from auto to forced */
2105 /* or vice-versa. */
2107 bnx2_resolve_flow_ctrl(bp);
2108 bnx2_set_mac_link(bp);
2113 /* advertise nothing when forcing speed */
2114 if (adv_reg != new_adv)
2115 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2118 if (bp->req_line_speed == SPEED_100) {
2119 new_bmcr |= BMCR_SPEED100;
2121 if (bp->req_duplex == DUPLEX_FULL) {
2122 new_bmcr |= BMCR_FULLDPLX;
2124 if (new_bmcr != bmcr) {
2127 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2128 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2130 if (bmsr & BMSR_LSTATUS) {
2131 /* Force link down */
2132 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2133 spin_unlock_bh(&bp->phy_lock);
2135 spin_lock_bh(&bp->phy_lock);
2137 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2138 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2141 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2143 /* Normally, the new speed is setup after the link has
2144 * gone down and up again. In some cases, link will not go
2145 * down so we need to set up the new speed here.
2147 if (bmsr & BMSR_LSTATUS) {
2148 bp->line_speed = bp->req_line_speed;
2149 bp->duplex = bp->req_duplex;
2150 bnx2_resolve_flow_ctrl(bp);
2151 bnx2_set_mac_link(bp);
2154 bnx2_resolve_flow_ctrl(bp);
2155 bnx2_set_mac_link(bp);
2161 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2162 __releases(&bp->phy_lock)
2163 __acquires(&bp->phy_lock)
2165 if (bp->loopback == MAC_LOOPBACK)
2168 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2169 return bnx2_setup_serdes_phy(bp, port);
2172 return bnx2_setup_copper_phy(bp);
2177 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2181 bp->mii_bmcr = MII_BMCR + 0x10;
2182 bp->mii_bmsr = MII_BMSR + 0x10;
2183 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2184 bp->mii_adv = MII_ADVERTISE + 0x10;
2185 bp->mii_lpa = MII_LPA + 0x10;
2186 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2188 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2189 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2191 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2195 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2197 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2198 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2199 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2200 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2202 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2203 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2204 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2205 val |= BCM5708S_UP1_2G5;
2207 val &= ~BCM5708S_UP1_2G5;
2208 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2210 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2211 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2212 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2213 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2215 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2217 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2218 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2219 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2221 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2227 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2234 bp->mii_up1 = BCM5708S_UP1;
2236 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2237 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2238 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2240 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2241 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2242 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2244 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2245 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2246 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2248 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2249 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2250 val |= BCM5708S_UP1_2G5;
2251 bnx2_write_phy(bp, BCM5708S_UP1, val);
2254 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
2255 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
2256 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {
2257 /* increase tx signal amplitude */
2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2259 BCM5708S_BLK_ADDR_TX_MISC);
2260 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2261 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2262 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2263 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2266 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2267 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2272 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2273 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2274 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2275 BCM5708S_BLK_ADDR_TX_MISC);
2276 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2277 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2278 BCM5708S_BLK_ADDR_DIG);
2285 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2290 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2292 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
2293 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2295 if (bp->dev->mtu > ETH_DATA_LEN) {
2298 /* Set extended packet length bit */
2299 bnx2_write_phy(bp, 0x18, 0x7);
2300 bnx2_read_phy(bp, 0x18, &val);
2301 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2303 bnx2_write_phy(bp, 0x1c, 0x6c00);
2304 bnx2_read_phy(bp, 0x1c, &val);
2305 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2310 bnx2_write_phy(bp, 0x18, 0x7);
2311 bnx2_read_phy(bp, 0x18, &val);
2312 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2314 bnx2_write_phy(bp, 0x1c, 0x6c00);
2315 bnx2_read_phy(bp, 0x1c, &val);
2316 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2323 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2330 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2331 bnx2_write_phy(bp, 0x18, 0x0c00);
2332 bnx2_write_phy(bp, 0x17, 0x000a);
2333 bnx2_write_phy(bp, 0x15, 0x310b);
2334 bnx2_write_phy(bp, 0x17, 0x201f);
2335 bnx2_write_phy(bp, 0x15, 0x9506);
2336 bnx2_write_phy(bp, 0x17, 0x401f);
2337 bnx2_write_phy(bp, 0x15, 0x14e2);
2338 bnx2_write_phy(bp, 0x18, 0x0400);
2341 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2342 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2343 MII_BNX2_DSP_EXPAND_REG | 0x8);
2344 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2346 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2349 if (bp->dev->mtu > ETH_DATA_LEN) {
2350 /* Set extended packet length bit */
2351 bnx2_write_phy(bp, 0x18, 0x7);
2352 bnx2_read_phy(bp, 0x18, &val);
2353 bnx2_write_phy(bp, 0x18, val | 0x4000);
2355 bnx2_read_phy(bp, 0x10, &val);
2356 bnx2_write_phy(bp, 0x10, val | 0x1);
2359 bnx2_write_phy(bp, 0x18, 0x7);
2360 bnx2_read_phy(bp, 0x18, &val);
2361 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2363 bnx2_read_phy(bp, 0x10, &val);
2364 bnx2_write_phy(bp, 0x10, val & ~0x1);
2367 /* ethernet@wirespeed */
2368 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
2369 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
2370 val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED;
2373 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
2374 val |= AUX_CTL_MISC_CTL_AUTOMDIX;
2376 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
2382 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2383 __releases(&bp->phy_lock)
2384 __acquires(&bp->phy_lock)
2389 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2390 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2392 bp->mii_bmcr = MII_BMCR;
2393 bp->mii_bmsr = MII_BMSR;
2394 bp->mii_bmsr1 = MII_BMSR;
2395 bp->mii_adv = MII_ADVERTISE;
2396 bp->mii_lpa = MII_LPA;
2398 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2400 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2403 bnx2_read_phy(bp, MII_PHYSID1, &val);
2404 bp->phy_id = val << 16;
2405 bnx2_read_phy(bp, MII_PHYSID2, &val);
2406 bp->phy_id |= val & 0xffff;
2408 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2409 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
2410 rc = bnx2_init_5706s_phy(bp, reset_phy);
2411 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
2412 rc = bnx2_init_5708s_phy(bp, reset_phy);
2413 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
2414 rc = bnx2_init_5709s_phy(bp, reset_phy);
2417 rc = bnx2_init_copper_phy(bp, reset_phy);
2422 rc = bnx2_setup_phy(bp, bp->phy_port);
2428 bnx2_set_mac_loopback(struct bnx2 *bp)
2432 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2433 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2434 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2435 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2440 static int bnx2_test_link(struct bnx2 *);
2443 bnx2_set_phy_loopback(struct bnx2 *bp)
2448 spin_lock_bh(&bp->phy_lock);
2449 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2451 spin_unlock_bh(&bp->phy_lock);
2455 for (i = 0; i < 10; i++) {
2456 if (bnx2_test_link(bp) == 0)
2461 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2462 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2463 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2464 BNX2_EMAC_MODE_25G_MODE);
2466 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2467 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2473 bnx2_dump_mcp_state(struct bnx2 *bp)
2475 struct net_device *dev = bp->dev;
2478 netdev_err(dev, "<--- start MCP states dump --->\n");
2479 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
2480 mcp_p0 = BNX2_MCP_STATE_P0;
2481 mcp_p1 = BNX2_MCP_STATE_P1;
2483 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2484 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2486 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2487 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2488 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2489 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2490 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2491 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2492 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2493 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2494 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2495 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2496 netdev_err(dev, "DEBUG: shmem states:\n");
2497 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2498 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2499 bnx2_shmem_rd(bp, BNX2_FW_MB),
2500 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2501 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2502 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2503 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2504 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2505 pr_cont(" condition[%08x]\n",
2506 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2507 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
2508 DP_SHMEM_LINE(bp, 0x3cc);
2509 DP_SHMEM_LINE(bp, 0x3dc);
2510 DP_SHMEM_LINE(bp, 0x3ec);
2511 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2512 netdev_err(dev, "<--- end MCP states dump --->\n");
2516 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2522 msg_data |= bp->fw_wr_seq;
2523 bp->fw_last_msg = msg_data;
2525 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2530 /* wait for an acknowledgement. */
2531 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2534 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2536 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2539 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2542 /* If we timed out, inform the firmware that this is the case. */
2543 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2544 msg_data &= ~BNX2_DRV_MSG_CODE;
2545 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2547 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2549 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2550 bnx2_dump_mcp_state(bp);
2556 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2563 bnx2_init_5709_context(struct bnx2 *bp)
2568 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2569 val |= (BNX2_PAGE_BITS - 8) << 16;
2570 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
2571 for (i = 0; i < 10; i++) {
2572 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
2573 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2577 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2580 for (i = 0; i < bp->ctx_pages; i++) {
2584 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);
2588 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2589 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2590 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2591 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2592 (u64) bp->ctx_blk_mapping[i] >> 32);
2593 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2594 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2595 for (j = 0; j < 10; j++) {
2597 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2598 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2602 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2611 bnx2_init_context(struct bnx2 *bp)
2617 u32 vcid_addr, pcid_addr, offset;
2622 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
2625 vcid_addr = GET_PCID_ADDR(vcid);
2627 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2632 pcid_addr = GET_PCID_ADDR(new_vcid);
2635 vcid_addr = GET_CID_ADDR(vcid);
2636 pcid_addr = vcid_addr;
2639 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2640 vcid_addr += (i << PHY_CTX_SHIFT);
2641 pcid_addr += (i << PHY_CTX_SHIFT);
2643 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2644 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2646 /* Zero out the context. */
2647 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2648 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2654 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2660 good_mbuf = kmalloc_array(512, sizeof(u16), GFP_KERNEL);
2664 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2665 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2669 /* Allocate a bunch of mbufs and save the good ones in an array. */
2670 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2671 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2672 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2673 BNX2_RBUF_COMMAND_ALLOC_REQ);
2675 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2677 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2679 /* The addresses with Bit 9 set are bad memory blocks. */
2680 if (!(val & (1 << 9))) {
2681 good_mbuf[good_mbuf_cnt] = (u16) val;
2685 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2688 /* Free the good ones back to the mbuf pool thus discarding
2689 * all the bad ones. */
2690 while (good_mbuf_cnt) {
2693 val = good_mbuf[good_mbuf_cnt];
2694 val = (val << 9) | val | 1;
2696 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2703 bnx2_set_mac_addr(struct bnx2 *bp, const u8 *mac_addr, u32 pos)
2707 val = (mac_addr[0] << 8) | mac_addr[1];
2709 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2711 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2712 (mac_addr[4] << 8) | mac_addr[5];
2714 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2718 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2721 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2722 struct bnx2_rx_bd *rxbd =
2723 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
2724 struct page *page = alloc_page(gfp);
2728 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
2730 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2736 dma_unmap_addr_set(rx_pg, mapping, mapping);
2737 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2738 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2743 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2745 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2746 struct page *page = rx_pg->page;
2751 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2752 PAGE_SIZE, DMA_FROM_DEVICE);
2759 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2762 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2764 struct bnx2_rx_bd *rxbd =
2765 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
2767 data = kmalloc(bp->rx_buf_size, gfp);
2771 mapping = dma_map_single(&bp->pdev->dev,
2773 bp->rx_buf_use_size,
2775 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2780 rx_buf->data = data;
2781 dma_unmap_addr_set(rx_buf, mapping, mapping);
2783 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2784 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2786 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2792 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2794 struct status_block *sblk = bnapi->status_blk.msi;
2795 u32 new_link_state, old_link_state;
2798 new_link_state = sblk->status_attn_bits & event;
2799 old_link_state = sblk->status_attn_bits_ack & event;
2800 if (new_link_state != old_link_state) {
2802 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2804 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2812 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2814 spin_lock(&bp->phy_lock);
2816 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2818 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2819 bnx2_set_remote_link(bp);
2821 spin_unlock(&bp->phy_lock);
2826 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2830 cons = READ_ONCE(*bnapi->hw_tx_cons_ptr);
2832 if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT))
2838 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2840 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2841 u16 hw_cons, sw_cons, sw_ring_cons;
2842 int tx_pkt = 0, index;
2843 unsigned int tx_bytes = 0;
2844 struct netdev_queue *txq;
2846 index = (bnapi - bp->bnx2_napi);
2847 txq = netdev_get_tx_queue(bp->dev, index);
2849 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2850 sw_cons = txr->tx_cons;
2852 while (sw_cons != hw_cons) {
2853 struct bnx2_sw_tx_bd *tx_buf;
2854 struct sk_buff *skb;
2857 sw_ring_cons = BNX2_TX_RING_IDX(sw_cons);
2859 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2862 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2863 prefetch(&skb->end);
2865 /* partial BD completions possible with TSO packets */
2866 if (tx_buf->is_gso) {
2867 u16 last_idx, last_ring_idx;
2869 last_idx = sw_cons + tx_buf->nr_frags + 1;
2870 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2871 if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) {
2874 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2879 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
2880 skb_headlen(skb), DMA_TO_DEVICE);
2883 last = tx_buf->nr_frags;
2885 for (i = 0; i < last; i++) {
2886 struct bnx2_sw_tx_bd *tx_buf;
2888 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
2890 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)];
2891 dma_unmap_page(&bp->pdev->dev,
2892 dma_unmap_addr(tx_buf, mapping),
2893 skb_frag_size(&skb_shinfo(skb)->frags[i]),
2897 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
2899 tx_bytes += skb->len;
2900 dev_kfree_skb_any(skb);
2902 if (tx_pkt == budget)
2905 if (hw_cons == sw_cons)
2906 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2909 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
2910 txr->hw_tx_cons = hw_cons;
2911 txr->tx_cons = sw_cons;
2913 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2914 * before checking for netif_tx_queue_stopped(). Without the
2915 * memory barrier, there is a small possibility that bnx2_start_xmit()
2916 * will miss it and cause the queue to be stopped forever.
2920 if (unlikely(netif_tx_queue_stopped(txq)) &&
2921 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2922 __netif_tx_lock(txq, smp_processor_id());
2923 if ((netif_tx_queue_stopped(txq)) &&
2924 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2925 netif_tx_wake_queue(txq);
2926 __netif_tx_unlock(txq);
2933 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2934 struct sk_buff *skb, int count)
2936 struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg;
2937 struct bnx2_rx_bd *cons_bd, *prod_bd;
2940 u16 cons = rxr->rx_pg_cons;
2942 cons_rx_pg = &rxr->rx_pg_ring[cons];
2944 /* The caller was unable to allocate a new page to replace the
2945 * last one in the frags array, so we need to recycle that page
2946 * and then free the skb.
2950 struct skb_shared_info *shinfo;
2952 shinfo = skb_shinfo(skb);
2954 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2955 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
2957 cons_rx_pg->page = page;
2961 hw_prod = rxr->rx_pg_prod;
2963 for (i = 0; i < count; i++) {
2964 prod = BNX2_RX_PG_RING_IDX(hw_prod);
2966 prod_rx_pg = &rxr->rx_pg_ring[prod];
2967 cons_rx_pg = &rxr->rx_pg_ring[cons];
2968 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)]
2969 [BNX2_RX_IDX(cons)];
2970 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)]
2971 [BNX2_RX_IDX(prod)];
2974 prod_rx_pg->page = cons_rx_pg->page;
2975 cons_rx_pg->page = NULL;
2976 dma_unmap_addr_set(prod_rx_pg, mapping,
2977 dma_unmap_addr(cons_rx_pg, mapping));
2979 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2980 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2983 cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons));
2984 hw_prod = BNX2_NEXT_RX_BD(hw_prod);
2986 rxr->rx_pg_prod = hw_prod;
2987 rxr->rx_pg_cons = cons;
2991 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2992 u8 *data, u16 cons, u16 prod)
2994 struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf;
2995 struct bnx2_rx_bd *cons_bd, *prod_bd;
2997 cons_rx_buf = &rxr->rx_buf_ring[cons];
2998 prod_rx_buf = &rxr->rx_buf_ring[prod];
3000 dma_sync_single_for_device(&bp->pdev->dev,
3001 dma_unmap_addr(cons_rx_buf, mapping),
3002 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, DMA_FROM_DEVICE);
3004 rxr->rx_prod_bseq += bp->rx_buf_use_size;
3006 prod_rx_buf->data = data;
3011 dma_unmap_addr_set(prod_rx_buf, mapping,
3012 dma_unmap_addr(cons_rx_buf, mapping));
3014 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)];
3015 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)];
3016 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
3017 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
3020 static struct sk_buff *
3021 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
3022 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
3026 u16 prod = ring_idx & 0xffff;
3027 struct sk_buff *skb;
3029 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
3030 if (unlikely(err)) {
3031 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
3034 unsigned int raw_len = len + 4;
3035 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3037 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3042 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
3044 skb = build_skb(data, 0);
3049 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
3054 unsigned int i, frag_len, frag_size, pages;
3055 struct bnx2_sw_pg *rx_pg;
3056 u16 pg_cons = rxr->rx_pg_cons;
3057 u16 pg_prod = rxr->rx_pg_prod;
3059 frag_size = len + 4 - hdr_len;
3060 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3061 skb_put(skb, hdr_len);
3063 for (i = 0; i < pages; i++) {
3064 dma_addr_t mapping_old;
3066 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3067 if (unlikely(frag_len <= 4)) {
3068 unsigned int tail = 4 - frag_len;
3070 rxr->rx_pg_cons = pg_cons;
3071 rxr->rx_pg_prod = pg_prod;
3072 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3079 &skb_shinfo(skb)->frags[i - 1];
3080 skb_frag_size_sub(frag, tail);
3081 skb->data_len -= tail;
3085 rx_pg = &rxr->rx_pg_ring[pg_cons];
3087 /* Don't unmap yet. If we're unable to allocate a new
3088 * page, we need to recycle the page and the DMA addr.
3090 mapping_old = dma_unmap_addr(rx_pg, mapping);
3094 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3097 err = bnx2_alloc_rx_page(bp, rxr,
3098 BNX2_RX_PG_RING_IDX(pg_prod),
3100 if (unlikely(err)) {
3101 rxr->rx_pg_cons = pg_cons;
3102 rxr->rx_pg_prod = pg_prod;
3103 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3108 dma_unmap_page(&bp->pdev->dev, mapping_old,
3109 PAGE_SIZE, DMA_FROM_DEVICE);
3111 frag_size -= frag_len;
3112 skb->data_len += frag_len;
3113 skb->truesize += PAGE_SIZE;
3114 skb->len += frag_len;
3116 pg_prod = BNX2_NEXT_RX_BD(pg_prod);
3117 pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons));
3119 rxr->rx_pg_prod = pg_prod;
3120 rxr->rx_pg_cons = pg_cons;
3126 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3130 cons = READ_ONCE(*bnapi->hw_rx_cons_ptr);
3132 if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT))
3138 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3140 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3141 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3142 struct l2_fhdr *rx_hdr;
3143 int rx_pkt = 0, pg_ring_used = 0;
3148 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3149 sw_cons = rxr->rx_cons;
3150 sw_prod = rxr->rx_prod;
3152 /* Memory barrier necessary as speculative reads of the rx
3153 * buffer can be ahead of the index in the status block
3156 while (sw_cons != hw_cons) {
3157 unsigned int len, hdr_len;
3159 struct bnx2_sw_bd *rx_buf, *next_rx_buf;
3160 struct sk_buff *skb;
3161 dma_addr_t dma_addr;
3165 sw_ring_cons = BNX2_RX_RING_IDX(sw_cons);
3166 sw_ring_prod = BNX2_RX_RING_IDX(sw_prod);
3168 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3169 data = rx_buf->data;
3170 rx_buf->data = NULL;
3172 rx_hdr = get_l2_fhdr(data);
3175 dma_addr = dma_unmap_addr(rx_buf, mapping);
3177 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
3178 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3181 next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons));
3182 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx];
3183 prefetch(get_l2_fhdr(next_rx_buf->data));
3185 len = rx_hdr->l2_fhdr_pkt_len;
3186 status = rx_hdr->l2_fhdr_status;
3189 if (status & L2_FHDR_STATUS_SPLIT) {
3190 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3192 } else if (len > bp->rx_jumbo_thresh) {
3193 hdr_len = bp->rx_jumbo_thresh;
3197 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3198 L2_FHDR_ERRORS_PHY_DECODE |
3199 L2_FHDR_ERRORS_ALIGNMENT |
3200 L2_FHDR_ERRORS_TOO_SHORT |
3201 L2_FHDR_ERRORS_GIANT_FRAME))) {
3203 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
3208 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3210 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3217 if (len <= bp->rx_copy_thresh) {
3218 skb = netdev_alloc_skb(bp->dev, len + 6);
3220 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
3227 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3229 skb_reserve(skb, 6);
3232 bnx2_reuse_rx_data(bp, rxr, data,
3233 sw_ring_cons, sw_ring_prod);
3236 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3237 (sw_ring_cons << 16) | sw_ring_prod);
3241 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3242 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3243 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag);
3245 skb->protocol = eth_type_trans(skb, bp->dev);
3247 if (len > (bp->dev->mtu + ETH_HLEN) &&
3248 skb->protocol != htons(0x8100) &&
3249 skb->protocol != htons(ETH_P_8021AD)) {
3256 skb_checksum_none_assert(skb);
3257 if ((bp->dev->features & NETIF_F_RXCSUM) &&
3258 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3259 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3261 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3262 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3263 skb->ip_summed = CHECKSUM_UNNECESSARY;
3265 if ((bp->dev->features & NETIF_F_RXHASH) &&
3266 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3267 L2_FHDR_STATUS_USE_RXHASH))
3268 skb_set_hash(skb, rx_hdr->l2_fhdr_hash,
3271 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3272 napi_gro_receive(&bnapi->napi, skb);
3276 sw_cons = BNX2_NEXT_RX_BD(sw_cons);
3277 sw_prod = BNX2_NEXT_RX_BD(sw_prod);
3279 if (rx_pkt == budget)
3282 /* Refresh hw_cons to see if there is new work */
3283 if (sw_cons == hw_cons) {
3284 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3288 rxr->rx_cons = sw_cons;
3289 rxr->rx_prod = sw_prod;
3292 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3294 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3296 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3302 /* MSI ISR - The only difference between this and the INTx ISR
3303 * is that the MSI interrupt is always serviced.
3306 bnx2_msi(int irq, void *dev_instance)
3308 struct bnx2_napi *bnapi = dev_instance;
3309 struct bnx2 *bp = bnapi->bp;
3311 prefetch(bnapi->status_blk.msi);
3312 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3313 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3314 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3316 /* Return here if interrupt is disabled. */
3317 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3320 napi_schedule(&bnapi->napi);
3326 bnx2_msi_1shot(int irq, void *dev_instance)
3328 struct bnx2_napi *bnapi = dev_instance;
3329 struct bnx2 *bp = bnapi->bp;
3331 prefetch(bnapi->status_blk.msi);
3333 /* Return here if interrupt is disabled. */
3334 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3337 napi_schedule(&bnapi->napi);
3343 bnx2_interrupt(int irq, void *dev_instance)
3345 struct bnx2_napi *bnapi = dev_instance;
3346 struct bnx2 *bp = bnapi->bp;
3347 struct status_block *sblk = bnapi->status_blk.msi;
3349 /* When using INTx, it is possible for the interrupt to arrive
3350 * at the CPU before the status block posted prior to the
3351 * interrupt. Reading a register will flush the status block.
3352 * When using MSI, the MSI message will always complete after
3353 * the status block write.
3355 if ((sblk->status_idx == bnapi->last_status_idx) &&
3356 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3357 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3360 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3361 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3362 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3364 /* Read back to deassert IRQ immediately to avoid too many
3365 * spurious interrupts.
3367 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3369 /* Return here if interrupt is shared and is disabled. */
3370 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3373 if (napi_schedule_prep(&bnapi->napi)) {
3374 bnapi->last_status_idx = sblk->status_idx;
3375 __napi_schedule(&bnapi->napi);
3382 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3384 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3385 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3387 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3388 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3393 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3394 STATUS_ATTN_BITS_TIMER_ABORT)
3397 bnx2_has_work(struct bnx2_napi *bnapi)
3399 struct status_block *sblk = bnapi->status_blk.msi;
3401 if (bnx2_has_fast_work(bnapi))
3405 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3409 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3410 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3417 bnx2_chk_missed_msi(struct bnx2 *bp)
3419 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3422 if (bnx2_has_work(bnapi)) {
3423 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3424 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3427 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3428 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3429 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3430 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3431 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3435 bp->idle_chk_status_idx = bnapi->last_status_idx;
3439 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3441 struct cnic_ops *c_ops;
3443 if (!bnapi->cnic_present)
3447 c_ops = rcu_dereference(bp->cnic_ops);
3449 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3450 bnapi->status_blk.msi);
3455 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3457 struct status_block *sblk = bnapi->status_blk.msi;
3458 u32 status_attn_bits = sblk->status_attn_bits;
3459 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3461 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3462 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3464 bnx2_phy_int(bp, bnapi);
3466 /* This is needed to take care of transient status
3467 * during link changes.
3469 BNX2_WR(bp, BNX2_HC_COMMAND,
3470 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3471 BNX2_RD(bp, BNX2_HC_COMMAND);
3475 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3476 int work_done, int budget)
3478 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3479 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3481 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3482 bnx2_tx_int(bp, bnapi, 0);
3484 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3485 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3490 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3492 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3493 struct bnx2 *bp = bnapi->bp;
3495 struct status_block_msix *sblk = bnapi->status_blk.msix;
3498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3499 if (unlikely(work_done >= budget))
3502 bnapi->last_status_idx = sblk->status_idx;
3503 /* status idx must be read before checking for more work. */
3505 if (likely(!bnx2_has_fast_work(bnapi))) {
3507 napi_complete_done(napi, work_done);
3508 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3509 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3510 bnapi->last_status_idx);
3517 static int bnx2_poll(struct napi_struct *napi, int budget)
3519 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3520 struct bnx2 *bp = bnapi->bp;
3522 struct status_block *sblk = bnapi->status_blk.msi;
3525 bnx2_poll_link(bp, bnapi);
3527 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3530 bnx2_poll_cnic(bp, bnapi);
3533 /* bnapi->last_status_idx is used below to tell the hw how
3534 * much work has been processed, so we must read it before
3535 * checking for more work.
3537 bnapi->last_status_idx = sblk->status_idx;
3539 if (unlikely(work_done >= budget))
3543 if (likely(!bnx2_has_work(bnapi))) {
3544 napi_complete_done(napi, work_done);
3545 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3546 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3547 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3548 bnapi->last_status_idx);
3551 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3552 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3553 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3554 bnapi->last_status_idx);
3556 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3557 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3558 bnapi->last_status_idx);
3566 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3567 * from set_multicast.
3570 bnx2_set_rx_mode(struct net_device *dev)
3572 struct bnx2 *bp = netdev_priv(dev);
3573 u32 rx_mode, sort_mode;
3574 struct netdev_hw_addr *ha;
3577 if (!netif_running(dev))
3580 spin_lock_bh(&bp->phy_lock);
3582 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3583 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3584 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3585 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
3586 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3587 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3588 if (dev->flags & IFF_PROMISC) {
3589 /* Promiscuous mode. */
3590 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3591 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3592 BNX2_RPM_SORT_USER0_PROM_VLAN;
3594 else if (dev->flags & IFF_ALLMULTI) {
3595 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3596 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3599 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3602 /* Accept one or more multicast(s). */
3603 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3608 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3610 netdev_for_each_mc_addr(ha, dev) {
3611 crc = ether_crc_le(ETH_ALEN, ha->addr);
3613 regidx = (bit & 0xe0) >> 5;
3615 mc_filter[regidx] |= (1 << bit);
3618 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3619 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3623 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3626 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3627 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3628 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3629 BNX2_RPM_SORT_USER0_PROM_VLAN;
3630 } else if (!(dev->flags & IFF_PROMISC)) {
3631 /* Add all entries into to the match filter list */
3633 netdev_for_each_uc_addr(ha, dev) {
3634 bnx2_set_mac_addr(bp, ha->addr,
3635 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3637 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3643 if (rx_mode != bp->rx_mode) {
3644 bp->rx_mode = rx_mode;
3645 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3648 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3649 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3650 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3652 spin_unlock_bh(&bp->phy_lock);
3656 check_fw_section(const struct firmware *fw,
3657 const struct bnx2_fw_file_section *section,
3658 u32 alignment, bool non_empty)
3660 u32 offset = be32_to_cpu(section->offset);
3661 u32 len = be32_to_cpu(section->len);
3663 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3665 if ((non_empty && len == 0) || len > fw->size - offset ||
3666 len & (alignment - 1))
3672 check_mips_fw_entry(const struct firmware *fw,
3673 const struct bnx2_mips_fw_file_entry *entry)
3675 if (check_fw_section(fw, &entry->text, 4, true) ||
3676 check_fw_section(fw, &entry->data, 4, false) ||
3677 check_fw_section(fw, &entry->rodata, 4, false))
3682 static void bnx2_release_firmware(struct bnx2 *bp)
3684 if (bp->rv2p_firmware) {
3685 release_firmware(bp->mips_firmware);
3686 release_firmware(bp->rv2p_firmware);
3687 bp->rv2p_firmware = NULL;
3691 static int bnx2_request_uncached_firmware(struct bnx2 *bp)
3693 const char *mips_fw_file, *rv2p_fw_file;
3694 const struct bnx2_mips_fw_file *mips_fw;
3695 const struct bnx2_rv2p_fw_file *rv2p_fw;
3698 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
3699 mips_fw_file = FW_MIPS_FILE_09;
3700 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||
3701 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))
3702 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3704 rv2p_fw_file = FW_RV2P_FILE_09;
3706 mips_fw_file = FW_MIPS_FILE_06;
3707 rv2p_fw_file = FW_RV2P_FILE_06;
3710 rc = reject_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3712 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3716 rc = reject_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3718 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3719 goto err_release_mips_firmware;
3721 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3722 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3723 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3724 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3725 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3726 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3727 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3728 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3729 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3731 goto err_release_firmware;
3733 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3734 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3735 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3736 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3738 goto err_release_firmware;
3743 err_release_firmware:
3744 release_firmware(bp->rv2p_firmware);
3745 bp->rv2p_firmware = NULL;
3746 err_release_mips_firmware:
3747 release_firmware(bp->mips_firmware);
3751 static int bnx2_request_firmware(struct bnx2 *bp)
3753 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
3757 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3760 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3761 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3762 rv2p_code |= RV2P_BD_PAGE_SIZE;
3769 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3770 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3772 u32 rv2p_code_len, file_offset;
3777 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3778 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3780 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3782 if (rv2p_proc == RV2P_PROC1) {
3783 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3784 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3786 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3787 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3790 for (i = 0; i < rv2p_code_len; i += 8) {
3791 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3793 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3796 val = (i / 8) | cmd;
3797 BNX2_WR(bp, addr, val);
3800 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3801 for (i = 0; i < 8; i++) {
3804 loc = be32_to_cpu(fw_entry->fixup[i]);
3805 if (loc && ((loc * 4) < rv2p_code_len)) {
3806 code = be32_to_cpu(*(rv2p_code + loc - 1));
3807 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3808 code = be32_to_cpu(*(rv2p_code + loc));
3809 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3810 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3812 val = (loc / 2) | cmd;
3813 BNX2_WR(bp, addr, val);
3817 /* Reset the processor, un-stall is done later. */
3818 if (rv2p_proc == RV2P_PROC1) {
3819 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3822 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3829 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3830 const struct bnx2_mips_fw_file_entry *fw_entry)
3832 u32 addr, len, file_offset;
3838 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3839 val |= cpu_reg->mode_value_halt;
3840 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3841 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3843 /* Load the Text area. */
3844 addr = be32_to_cpu(fw_entry->text.addr);
3845 len = be32_to_cpu(fw_entry->text.len);
3846 file_offset = be32_to_cpu(fw_entry->text.offset);
3847 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3849 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3853 for (j = 0; j < (len / 4); j++, offset += 4)
3854 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3857 /* Load the Data area. */
3858 addr = be32_to_cpu(fw_entry->data.addr);
3859 len = be32_to_cpu(fw_entry->data.len);
3860 file_offset = be32_to_cpu(fw_entry->data.offset);
3861 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3863 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3867 for (j = 0; j < (len / 4); j++, offset += 4)
3868 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3871 /* Load the Read-Only area. */
3872 addr = be32_to_cpu(fw_entry->rodata.addr);
3873 len = be32_to_cpu(fw_entry->rodata.len);
3874 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3875 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3877 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3881 for (j = 0; j < (len / 4); j++, offset += 4)
3882 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3885 /* Clear the pre-fetch instruction. */
3886 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3888 val = be32_to_cpu(fw_entry->start_addr);
3889 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3891 /* Start the CPU. */
3892 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3893 val &= ~cpu_reg->mode_value_halt;
3894 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3895 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3901 bnx2_init_cpus(struct bnx2 *bp)
3903 const struct bnx2_mips_fw_file *mips_fw =
3904 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3905 const struct bnx2_rv2p_fw_file *rv2p_fw =
3906 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3909 /* Initialize the RV2P processor. */
3910 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3911 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3913 /* Initialize the RX Processor. */
3914 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3918 /* Initialize the TX Processor. */
3919 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3923 /* Initialize the TX Patch-up Processor. */
3924 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3928 /* Initialize the Completion Processor. */
3929 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3933 /* Initialize the Command Processor. */
3934 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3941 bnx2_setup_wol(struct bnx2 *bp)
3950 autoneg = bp->autoneg;
3951 advertising = bp->advertising;
3953 if (bp->phy_port == PORT_TP) {
3954 bp->autoneg = AUTONEG_SPEED;
3955 bp->advertising = ADVERTISED_10baseT_Half |
3956 ADVERTISED_10baseT_Full |
3957 ADVERTISED_100baseT_Half |
3958 ADVERTISED_100baseT_Full |
3962 spin_lock_bh(&bp->phy_lock);
3963 bnx2_setup_phy(bp, bp->phy_port);
3964 spin_unlock_bh(&bp->phy_lock);
3966 bp->autoneg = autoneg;
3967 bp->advertising = advertising;
3969 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3971 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3973 /* Enable port mode. */
3974 val &= ~BNX2_EMAC_MODE_PORT;
3975 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3976 BNX2_EMAC_MODE_ACPI_RCVD |
3977 BNX2_EMAC_MODE_MPKT;
3978 if (bp->phy_port == PORT_TP) {
3979 val |= BNX2_EMAC_MODE_PORT_MII;
3981 val |= BNX2_EMAC_MODE_PORT_GMII;
3982 if (bp->line_speed == SPEED_2500)
3983 val |= BNX2_EMAC_MODE_25G_MODE;
3986 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3988 /* receive all multicast */
3989 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3990 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3993 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
3995 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
3996 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3997 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
3998 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
4000 /* Need to enable EMAC and RPM for WOL. */
4001 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4002 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
4003 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
4004 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
4006 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4007 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4008 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4010 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4012 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4015 if (!(bp->flags & BNX2_FLAG_NO_WOL)) {
4018 wol_msg |= BNX2_DRV_MSG_DATA_WAIT3;
4019 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {
4020 bnx2_fw_sync(bp, wol_msg, 1, 0);
4023 /* Tell firmware not to power down the PHY yet, otherwise
4024 * the chip will take a long time to respond to MMIO reads.
4026 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
4027 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,
4028 val | BNX2_PORT_FEATURE_ASF_ENABLED);
4029 bnx2_fw_sync(bp, wol_msg, 1, 0);
4030 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
4036 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
4042 pci_enable_wake(bp->pdev, PCI_D0, false);
4043 pci_set_power_state(bp->pdev, PCI_D0);
4045 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4046 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
4047 val &= ~BNX2_EMAC_MODE_MPKT;
4048 BNX2_WR(bp, BNX2_EMAC_MODE, val);
4050 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4051 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4052 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4057 pci_wake_from_d3(bp->pdev, bp->wol);
4058 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4059 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
4062 pci_set_power_state(bp->pdev, PCI_D3hot);
4066 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4069 /* Tell firmware not to power down the PHY yet,
4070 * otherwise the other port may not respond to
4073 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
4074 val &= ~BNX2_CONDITION_PM_STATE_MASK;
4075 val |= BNX2_CONDITION_PM_STATE_UNPREP;
4076 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
4078 pci_set_power_state(bp->pdev, PCI_D3hot);
4080 /* No more memory access after this point until
4081 * device is brought back to D0.
4092 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4097 /* Request access to the flash interface. */
4098 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4099 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4100 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4101 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4107 if (j >= NVRAM_TIMEOUT_COUNT)
4114 bnx2_release_nvram_lock(struct bnx2 *bp)
4119 /* Relinquish nvram interface. */
4120 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4122 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4123 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4124 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4130 if (j >= NVRAM_TIMEOUT_COUNT)
4138 bnx2_enable_nvram_write(struct bnx2 *bp)
4142 val = BNX2_RD(bp, BNX2_MISC_CFG);
4143 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4145 if (bp->flash_info->flags & BNX2_NV_WREN) {
4148 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4149 BNX2_WR(bp, BNX2_NVM_COMMAND,
4150 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4152 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4155 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4156 if (val & BNX2_NVM_COMMAND_DONE)
4160 if (j >= NVRAM_TIMEOUT_COUNT)
4167 bnx2_disable_nvram_write(struct bnx2 *bp)
4171 val = BNX2_RD(bp, BNX2_MISC_CFG);
4172 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4177 bnx2_enable_nvram_access(struct bnx2 *bp)
4181 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4182 /* Enable both bits, even on read. */
4183 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4184 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4188 bnx2_disable_nvram_access(struct bnx2 *bp)
4192 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4193 /* Disable both bits, even after read. */
4194 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4195 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4196 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4200 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4205 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4206 /* Buffered flash, no erase needed */
4209 /* Build an erase command */
4210 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4211 BNX2_NVM_COMMAND_DOIT;
4213 /* Need to clear DONE bit separately. */
4214 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4216 /* Address of the NVRAM to read from. */
4217 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4219 /* Issue an erase command. */
4220 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4222 /* Wait for completion. */
4223 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4228 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4229 if (val & BNX2_NVM_COMMAND_DONE)
4233 if (j >= NVRAM_TIMEOUT_COUNT)
4240 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4245 /* Build the command word. */
4246 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4248 /* Calculate an offset of a buffered flash, not needed for 5709. */
4249 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4250 offset = ((offset / bp->flash_info->page_size) <<
4251 bp->flash_info->page_bits) +
4252 (offset % bp->flash_info->page_size);
4255 /* Need to clear DONE bit separately. */
4256 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4258 /* Address of the NVRAM to read from. */
4259 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4261 /* Issue a read command. */
4262 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4264 /* Wait for completion. */
4265 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4270 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4271 if (val & BNX2_NVM_COMMAND_DONE) {
4272 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
4273 memcpy(ret_val, &v, 4);
4277 if (j >= NVRAM_TIMEOUT_COUNT)
4285 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4291 /* Build the command word. */
4292 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4294 /* Calculate an offset of a buffered flash, not needed for 5709. */
4295 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4296 offset = ((offset / bp->flash_info->page_size) <<
4297 bp->flash_info->page_bits) +
4298 (offset % bp->flash_info->page_size);
4301 /* Need to clear DONE bit separately. */
4302 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4304 memcpy(&val32, val, 4);
4306 /* Write the data. */
4307 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4309 /* Address of the NVRAM to write to. */
4310 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4312 /* Issue the write command. */
4313 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4315 /* Wait for completion. */
4316 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4319 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4322 if (j >= NVRAM_TIMEOUT_COUNT)
4329 bnx2_init_nvram(struct bnx2 *bp)
4332 int j, entry_count, rc = 0;
4333 const struct flash_spec *flash;
4335 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4336 bp->flash_info = &flash_5709;
4337 goto get_flash_size;
4340 /* Determine the selected interface. */
4341 val = BNX2_RD(bp, BNX2_NVM_CFG1);
4343 entry_count = ARRAY_SIZE(flash_table);
4345 if (val & 0x40000000) {
4347 /* Flash interface has been reconfigured */
4348 for (j = 0, flash = &flash_table[0]; j < entry_count;
4350 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4351 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4352 bp->flash_info = flash;
4359 /* Not yet been reconfigured */
4361 if (val & (1 << 23))
4362 mask = FLASH_BACKUP_STRAP_MASK;
4364 mask = FLASH_STRAP_MASK;
4366 for (j = 0, flash = &flash_table[0]; j < entry_count;
4369 if ((val & mask) == (flash->strapping & mask)) {
4370 bp->flash_info = flash;
4372 /* Request access to the flash interface. */
4373 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4376 /* Enable access to flash interface */
4377 bnx2_enable_nvram_access(bp);
4379 /* Reconfigure the flash interface */
4380 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4381 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4382 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4383 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4385 /* Disable access to flash interface */
4386 bnx2_disable_nvram_access(bp);
4387 bnx2_release_nvram_lock(bp);
4392 } /* if (val & 0x40000000) */
4394 if (j == entry_count) {
4395 bp->flash_info = NULL;
4396 pr_alert("Unknown flash/EEPROM type\n");
4401 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4402 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4404 bp->flash_size = val;
4406 bp->flash_size = bp->flash_info->total_size;
4412 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4416 u32 cmd_flags, offset32, len32, extra;
4421 /* Request access to the flash interface. */
4422 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4425 /* Enable access to flash interface */
4426 bnx2_enable_nvram_access(bp);
4439 pre_len = 4 - (offset & 3);
4441 if (pre_len >= len32) {
4443 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4444 BNX2_NVM_COMMAND_LAST;
4447 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4450 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4455 memcpy(ret_buf, buf + (offset & 3), pre_len);
4462 extra = 4 - (len32 & 3);
4463 len32 = (len32 + 4) & ~3;
4470 cmd_flags = BNX2_NVM_COMMAND_LAST;
4472 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4473 BNX2_NVM_COMMAND_LAST;
4475 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4477 memcpy(ret_buf, buf, 4 - extra);
4479 else if (len32 > 0) {
4482 /* Read the first word. */
4486 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4488 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4490 /* Advance to the next dword. */
4495 while (len32 > 4 && rc == 0) {
4496 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4498 /* Advance to the next dword. */
4507 cmd_flags = BNX2_NVM_COMMAND_LAST;
4508 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4510 memcpy(ret_buf, buf, 4 - extra);
4513 /* Disable access to flash interface */
4514 bnx2_disable_nvram_access(bp);
4516 bnx2_release_nvram_lock(bp);
4522 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4525 u32 written, offset32, len32;
4526 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4528 int align_start, align_end;
4533 align_start = align_end = 0;
4535 if ((align_start = (offset32 & 3))) {
4537 len32 += align_start;
4540 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4545 align_end = 4 - (len32 & 3);
4547 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4551 if (align_start || align_end) {
4552 align_buf = kmalloc(len32, GFP_KERNEL);
4556 memcpy(align_buf, start, 4);
4559 memcpy(align_buf + len32 - 4, end, 4);
4561 memcpy(align_buf + align_start, data_buf, buf_size);
4565 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4566 flash_buffer = kmalloc(264, GFP_KERNEL);
4567 if (!flash_buffer) {
4569 goto nvram_write_end;
4574 while ((written < len32) && (rc == 0)) {
4575 u32 page_start, page_end, data_start, data_end;
4576 u32 addr, cmd_flags;
4579 /* Find the page_start addr */
4580 page_start = offset32 + written;
4581 page_start -= (page_start % bp->flash_info->page_size);
4582 /* Find the page_end addr */
4583 page_end = page_start + bp->flash_info->page_size;
4584 /* Find the data_start addr */
4585 data_start = (written == 0) ? offset32 : page_start;
4586 /* Find the data_end addr */
4587 data_end = (page_end > offset32 + len32) ?
4588 (offset32 + len32) : page_end;
4590 /* Request access to the flash interface. */
4591 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4592 goto nvram_write_end;
4594 /* Enable access to flash interface */
4595 bnx2_enable_nvram_access(bp);
4597 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4598 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4601 /* Read the whole page into the buffer
4602 * (non-buffer flash only) */
4603 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4604 if (j == (bp->flash_info->page_size - 4)) {
4605 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4607 rc = bnx2_nvram_read_dword(bp,
4613 goto nvram_write_end;
4619 /* Enable writes to flash interface (unlock write-protect) */
4620 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4621 goto nvram_write_end;
4623 /* Loop to write back the buffer data from page_start to
4626 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4627 /* Erase the page */
4628 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4629 goto nvram_write_end;
4631 /* Re-enable the write again for the actual write */
4632 bnx2_enable_nvram_write(bp);
4634 for (addr = page_start; addr < data_start;
4635 addr += 4, i += 4) {
4637 rc = bnx2_nvram_write_dword(bp, addr,
4638 &flash_buffer[i], cmd_flags);
4641 goto nvram_write_end;
4647 /* Loop to write the new data from data_start to data_end */
4648 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4649 if ((addr == page_end - 4) ||
4650 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4651 (addr == data_end - 4))) {
4653 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4655 rc = bnx2_nvram_write_dword(bp, addr, buf,
4659 goto nvram_write_end;
4665 /* Loop to write back the buffer data from data_end
4667 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4668 for (addr = data_end; addr < page_end;
4669 addr += 4, i += 4) {
4671 if (addr == page_end-4) {
4672 cmd_flags = BNX2_NVM_COMMAND_LAST;
4674 rc = bnx2_nvram_write_dword(bp, addr,
4675 &flash_buffer[i], cmd_flags);
4678 goto nvram_write_end;
4684 /* Disable writes to flash interface (lock write-protect) */
4685 bnx2_disable_nvram_write(bp);
4687 /* Disable access to flash interface */
4688 bnx2_disable_nvram_access(bp);
4689 bnx2_release_nvram_lock(bp);
4691 /* Increment written */
4692 written += data_end - data_start;
4696 kfree(flash_buffer);
4702 bnx2_init_fw_cap(struct bnx2 *bp)
4706 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4707 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4709 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4710 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4712 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4713 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4716 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4717 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4718 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4721 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4722 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4725 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4727 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4728 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4729 bp->phy_port = PORT_FIBRE;
4731 bp->phy_port = PORT_TP;
4733 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4734 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4737 if (netif_running(bp->dev) && sig)
4738 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4742 bnx2_setup_msix_tbl(struct bnx2 *bp)
4744 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4746 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4747 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4751 bnx2_wait_dma_complete(struct bnx2 *bp)
4757 * Wait for the current PCI transaction to complete before
4760 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
4761 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
4762 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4763 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4764 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4765 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4766 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4767 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4770 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4771 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4772 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4773 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4775 for (i = 0; i < 100; i++) {
4777 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4778 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4788 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4794 /* Wait for the current PCI transaction to complete before
4795 * issuing a reset. */
4796 bnx2_wait_dma_complete(bp);
4798 /* Wait for the firmware to tell us it is ok to issue a reset. */
4799 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4801 /* Deposit a driver reset signature so the firmware knows that
4802 * this is a soft reset. */
4803 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4804 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4806 /* Do a dummy read to force the chip to complete all current transaction
4807 * before we issue a reset. */
4808 val = BNX2_RD(bp, BNX2_MISC_ID);
4810 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4811 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4812 BNX2_RD(bp, BNX2_MISC_COMMAND);
4815 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4816 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4818 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4821 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4822 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4823 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4826 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4828 /* Reading back any register after chip reset will hang the
4829 * bus on 5706 A0 and A1. The msleep below provides plenty
4830 * of margin for write posting.
4832 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4833 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))
4836 /* Reset takes approximate 30 usec */
4837 for (i = 0; i < 10; i++) {
4838 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4839 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4840 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4845 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4846 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4847 pr_err("Chip reset did not complete\n");
4852 /* Make sure byte swapping is properly configured. */
4853 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
4854 if (val != 0x01020304) {
4855 pr_err("Chip not in correct endian mode\n");
4859 /* Wait for the firmware to finish its initialization. */
4860 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4864 spin_lock_bh(&bp->phy_lock);
4865 old_port = bp->phy_port;
4866 bnx2_init_fw_cap(bp);
4867 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4868 old_port != bp->phy_port)
4869 bnx2_set_default_remote_link(bp);
4870 spin_unlock_bh(&bp->phy_lock);
4872 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
4873 /* Adjust the voltage regular to two steps lower. The default
4874 * of this register is 0x0000000e. */
4875 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4877 /* Remove bad rbuf memory from the free pool. */
4878 rc = bnx2_alloc_bad_rbuf(bp);
4881 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4882 bnx2_setup_msix_tbl(bp);
4883 /* Prevent MSIX table reads and write from timing out */
4884 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
4885 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4892 bnx2_init_chip(struct bnx2 *bp)
4897 /* Make sure the interrupt is not active. */
4898 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4900 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4901 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4903 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4905 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4906 DMA_READ_CHANS << 12 |
4907 DMA_WRITE_CHANS << 16;
4909 val |= (0x2 << 20) | (1 << 11);
4911 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4914 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&
4915 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&
4916 !(bp->flags & BNX2_FLAG_PCIX))
4917 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4919 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
4921 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
4922 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
4923 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4924 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
4927 if (bp->flags & BNX2_FLAG_PCIX) {
4930 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4932 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4933 val16 & ~PCI_X_CMD_ERO);
4936 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4937 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4938 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4939 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4941 /* Initialize context mapping and zero out the quick contexts. The
4942 * context block must have already been enabled. */
4943 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4944 rc = bnx2_init_5709_context(bp);
4948 bnx2_init_context(bp);
4950 if ((rc = bnx2_init_cpus(bp)) != 0)
4953 bnx2_init_nvram(bp);
4955 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4957 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
4958 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4959 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4960 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4961 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4962 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
4963 val |= BNX2_MQ_CONFIG_HALT_DIS;
4966 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
4968 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4969 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4970 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4972 val = (BNX2_PAGE_BITS - 8) << 24;
4973 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
4975 /* Configure page size. */
4976 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
4977 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4978 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
4979 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
4981 val = bp->mac_addr[0] +
4982 (bp->mac_addr[1] << 8) +
4983 (bp->mac_addr[2] << 16) +
4985 (bp->mac_addr[4] << 8) +
4986 (bp->mac_addr[5] << 16);
4987 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4989 /* Program the MTU. Also include 4 bytes for CRC32. */
4991 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4992 if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4))
4993 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4994 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4996 if (mtu < ETH_DATA_LEN)
4999 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
5000 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
5001 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
5003 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
5004 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5005 bp->bnx2_napi[i].last_status_idx = 0;
5007 bp->idle_chk_status_idx = 0xffff;
5009 /* Set up how to generate a link change interrupt. */
5010 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
5012 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
5013 (u64) bp->status_blk_mapping & 0xffffffff);
5014 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
5016 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
5017 (u64) bp->stats_blk_mapping & 0xffffffff);
5018 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
5019 (u64) bp->stats_blk_mapping >> 32);
5021 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
5022 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
5024 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
5025 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
5027 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
5028 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
5030 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
5032 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
5034 BNX2_WR(bp, BNX2_HC_COM_TICKS,
5035 (bp->com_ticks_int << 16) | bp->com_ticks);
5037 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
5038 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
5040 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
5041 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
5043 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
5044 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5046 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)
5047 val = BNX2_HC_CONFIG_COLLECT_STATS;
5049 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
5050 BNX2_HC_CONFIG_COLLECT_STATS;
5053 if (bp->flags & BNX2_FLAG_USING_MSIX) {
5054 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
5055 BNX2_HC_MSIX_BIT_VECTOR_VAL);
5057 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
5060 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
5061 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5063 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5065 if (bp->rx_ticks < 25)
5066 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5068 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5070 for (i = 1; i < bp->irq_nvecs; i++) {
5071 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5072 BNX2_HC_SB_CONFIG_1;
5075 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5076 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
5077 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5079 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
5080 (bp->tx_quick_cons_trip_int << 16) |
5081 bp->tx_quick_cons_trip);
5083 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
5084 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5086 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5087 (bp->rx_quick_cons_trip_int << 16) |
5088 bp->rx_quick_cons_trip);
5090 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5091 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5094 /* Clear internal stats counters. */
5095 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5097 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5099 /* Initialize the receive filter. */
5100 bnx2_set_rx_mode(bp->dev);
5102 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
5103 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5104 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5105 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5107 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5110 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5111 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5115 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
5121 bnx2_clear_ring_states(struct bnx2 *bp)
5123 struct bnx2_napi *bnapi;
5124 struct bnx2_tx_ring_info *txr;
5125 struct bnx2_rx_ring_info *rxr;
5128 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5129 bnapi = &bp->bnx2_napi[i];
5130 txr = &bnapi->tx_ring;
5131 rxr = &bnapi->rx_ring;
5134 txr->hw_tx_cons = 0;
5135 rxr->rx_prod_bseq = 0;
5138 rxr->rx_pg_prod = 0;
5139 rxr->rx_pg_cons = 0;
5144 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5146 u32 val, offset0, offset1, offset2, offset3;
5147 u32 cid_addr = GET_CID_ADDR(cid);
5149 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
5150 offset0 = BNX2_L2CTX_TYPE_XI;
5151 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5152 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5153 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5155 offset0 = BNX2_L2CTX_TYPE;
5156 offset1 = BNX2_L2CTX_CMD_TYPE;
5157 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5158 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5160 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5161 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5163 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5164 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5166 val = (u64) txr->tx_desc_mapping >> 32;
5167 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5169 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5170 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5174 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5176 struct bnx2_tx_bd *txbd;
5178 struct bnx2_napi *bnapi;
5179 struct bnx2_tx_ring_info *txr;
5181 bnapi = &bp->bnx2_napi[ring_num];
5182 txr = &bnapi->tx_ring;
5187 cid = TX_TSS_CID + ring_num - 1;
5189 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5191 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT];
5193 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5194 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5197 txr->tx_prod_bseq = 0;
5199 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5200 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5202 bnx2_init_tx_context(bp, cid, txr);
5206 bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[],
5207 u32 buf_size, int num_rings)
5210 struct bnx2_rx_bd *rxbd;
5212 for (i = 0; i < num_rings; i++) {
5215 rxbd = &rx_ring[i][0];
5216 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) {
5217 rxbd->rx_bd_len = buf_size;
5218 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5220 if (i == (num_rings - 1))
5224 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5225 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5230 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5233 u16 prod, ring_prod;
5234 u32 cid, rx_cid_addr, val;
5235 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5236 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5241 cid = RX_RSS_CID + ring_num - 1;
5243 rx_cid_addr = GET_CID_ADDR(cid);
5245 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5246 bp->rx_buf_use_size, bp->rx_max_ring);
5248 bnx2_init_rx_context(bp, cid);
5250 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
5251 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5252 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5255 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5256 if (bp->rx_pg_ring_size) {
5257 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5258 rxr->rx_pg_desc_mapping,
5259 PAGE_SIZE, bp->rx_max_pg_ring);
5260 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5261 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5262 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5263 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5265 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5266 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5268 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5269 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5271 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5272 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5275 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5278 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5279 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5281 ring_prod = prod = rxr->rx_pg_prod;
5282 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5283 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5284 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5285 ring_num, i, bp->rx_pg_ring_size);
5288 prod = BNX2_NEXT_RX_BD(prod);
5289 ring_prod = BNX2_RX_PG_RING_IDX(prod);
5291 rxr->rx_pg_prod = prod;
5293 ring_prod = prod = rxr->rx_prod;
5294 for (i = 0; i < bp->rx_ring_size; i++) {
5295 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5296 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5297 ring_num, i, bp->rx_ring_size);
5300 prod = BNX2_NEXT_RX_BD(prod);
5301 ring_prod = BNX2_RX_RING_IDX(prod);
5303 rxr->rx_prod = prod;
5305 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5306 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5307 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5309 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5310 BNX2_WR16(bp, rxr->rx_bidx_addr, prod);
5312 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5316 bnx2_init_all_rings(struct bnx2 *bp)
5321 bnx2_clear_ring_states(bp);
5323 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5324 for (i = 0; i < bp->num_tx_rings; i++)
5325 bnx2_init_tx_ring(bp, i);
5327 if (bp->num_tx_rings > 1)
5328 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5331 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5332 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5334 for (i = 0; i < bp->num_rx_rings; i++)
5335 bnx2_init_rx_ring(bp, i);
5337 if (bp->num_rx_rings > 1) {
5340 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5341 int shift = (i % 8) << 2;
5343 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5345 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5346 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5347 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5348 BNX2_RLUP_RSS_COMMAND_WRITE |
5349 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5354 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5355 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5357 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5362 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5364 u32 max, num_rings = 1;
5366 while (ring_size > BNX2_MAX_RX_DESC_CNT) {
5367 ring_size -= BNX2_MAX_RX_DESC_CNT;
5370 /* round to next power of 2 */
5372 while ((max & num_rings) == 0)
5375 if (num_rings != max)
5382 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5384 u32 rx_size, rx_space, jumbo_size;
5386 /* 8 for CRC and VLAN */
5387 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5389 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5390 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5392 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5393 bp->rx_pg_ring_size = 0;
5394 bp->rx_max_pg_ring = 0;
5395 bp->rx_max_pg_ring_idx = 0;
5396 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5397 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5399 jumbo_size = size * pages;
5400 if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT)
5401 jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
5403 bp->rx_pg_ring_size = jumbo_size;
5404 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5405 BNX2_MAX_RX_PG_RINGS);
5406 bp->rx_max_pg_ring_idx =
5407 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;
5408 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5409 bp->rx_copy_thresh = 0;
5412 bp->rx_buf_use_size = rx_size;
5413 /* hw alignment + build_skb() overhead*/
5414 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5415 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5416 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5417 bp->rx_ring_size = size;
5418 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);
5419 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;
5423 bnx2_free_tx_skbs(struct bnx2 *bp)
5427 for (i = 0; i < bp->num_tx_rings; i++) {
5428 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5429 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5432 if (!txr->tx_buf_ring)
5435 for (j = 0; j < BNX2_TX_DESC_CNT; ) {
5436 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5437 struct sk_buff *skb = tx_buf->skb;
5441 j = BNX2_NEXT_TX_BD(j);
5445 dma_unmap_single(&bp->pdev->dev,
5446 dma_unmap_addr(tx_buf, mapping),
5452 last = tx_buf->nr_frags;
5453 j = BNX2_NEXT_TX_BD(j);
5454 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) {
5455 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)];
5456 dma_unmap_page(&bp->pdev->dev,
5457 dma_unmap_addr(tx_buf, mapping),
5458 skb_frag_size(&skb_shinfo(skb)->frags[k]),
5463 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
5468 bnx2_free_rx_skbs(struct bnx2 *bp)
5472 for (i = 0; i < bp->num_rx_rings; i++) {
5473 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5474 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5477 if (!rxr->rx_buf_ring)
5480 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5481 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5482 u8 *data = rx_buf->data;
5487 dma_unmap_single(&bp->pdev->dev,
5488 dma_unmap_addr(rx_buf, mapping),
5489 bp->rx_buf_use_size,
5492 rx_buf->data = NULL;
5496 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5497 bnx2_free_rx_page(bp, rxr, j);
5502 bnx2_free_skbs(struct bnx2 *bp)
5504 bnx2_free_tx_skbs(bp);
5505 bnx2_free_rx_skbs(bp);
5509 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5513 rc = bnx2_reset_chip(bp, reset_code);
5518 if ((rc = bnx2_init_chip(bp)) != 0)
5521 bnx2_init_all_rings(bp);
5526 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5530 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5533 spin_lock_bh(&bp->phy_lock);
5534 bnx2_init_phy(bp, reset_phy);
5536 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5537 bnx2_remote_phy_event(bp);
5538 spin_unlock_bh(&bp->phy_lock);
5543 bnx2_shutdown_chip(struct bnx2 *bp)
5547 if (bp->flags & BNX2_FLAG_NO_WOL)
5548 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5550 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5552 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5554 return bnx2_reset_chip(bp, reset_code);
5558 bnx2_test_registers(struct bnx2 *bp)
5562 static const struct {
5565 #define BNX2_FL_NOT_5709 1
5569 { 0x006c, 0, 0x00000000, 0x0000003f },
5570 { 0x0090, 0, 0xffffffff, 0x00000000 },
5571 { 0x0094, 0, 0x00000000, 0x00000000 },
5573 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5574 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5575 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5576 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5577 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5578 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5579 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5580 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5581 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5583 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5584 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5585 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5586 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5587 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5588 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5590 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5591 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5592 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5594 { 0x1000, 0, 0x00000000, 0x00000001 },
5595 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5597 { 0x1408, 0, 0x01c00800, 0x00000000 },
5598 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5599 { 0x14a8, 0, 0x00000000, 0x000001ff },
5600 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5601 { 0x14b0, 0, 0x00000002, 0x00000001 },
5602 { 0x14b8, 0, 0x00000000, 0x00000000 },
5603 { 0x14c0, 0, 0x00000000, 0x00000009 },
5604 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5605 { 0x14cc, 0, 0x00000000, 0x00000001 },
5606 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5608 { 0x1800, 0, 0x00000000, 0x00000001 },
5609 { 0x1804, 0, 0x00000000, 0x00000003 },
5611 { 0x2800, 0, 0x00000000, 0x00000001 },
5612 { 0x2804, 0, 0x00000000, 0x00003f01 },
5613 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5614 { 0x2810, 0, 0xffff0000, 0x00000000 },
5615 { 0x2814, 0, 0xffff0000, 0x00000000 },
5616 { 0x2818, 0, 0xffff0000, 0x00000000 },
5617 { 0x281c, 0, 0xffff0000, 0x00000000 },
5618 { 0x2834, 0, 0xffffffff, 0x00000000 },
5619 { 0x2840, 0, 0x00000000, 0xffffffff },
5620 { 0x2844, 0, 0x00000000, 0xffffffff },
5621 { 0x2848, 0, 0xffffffff, 0x00000000 },
5622 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5624 { 0x2c00, 0, 0x00000000, 0x00000011 },
5625 { 0x2c04, 0, 0x00000000, 0x00030007 },
5627 { 0x3c00, 0, 0x00000000, 0x00000001 },
5628 { 0x3c04, 0, 0x00000000, 0x00070000 },
5629 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5630 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5631 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5632 { 0x3c14, 0, 0x00000000, 0xffffffff },
5633 { 0x3c18, 0, 0x00000000, 0xffffffff },
5634 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5635 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5637 { 0x5004, 0, 0x00000000, 0x0000007f },
5638 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5640 { 0x5c00, 0, 0x00000000, 0x00000001 },
5641 { 0x5c04, 0, 0x00000000, 0x0003000f },
5642 { 0x5c08, 0, 0x00000003, 0x00000000 },
5643 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5644 { 0x5c10, 0, 0x00000000, 0xffffffff },
5645 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5646 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5647 { 0x5c88, 0, 0x00000000, 0x00077373 },
5648 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5650 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5651 { 0x680c, 0, 0xffffffff, 0x00000000 },
5652 { 0x6810, 0, 0xffffffff, 0x00000000 },
5653 { 0x6814, 0, 0xffffffff, 0x00000000 },
5654 { 0x6818, 0, 0xffffffff, 0x00000000 },
5655 { 0x681c, 0, 0xffffffff, 0x00000000 },
5656 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5657 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5658 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5659 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5660 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5661 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5662 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5663 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5664 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5665 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5666 { 0x684c, 0, 0xffffffff, 0x00000000 },
5667 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5668 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5669 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5670 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5671 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5672 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5674 { 0xffff, 0, 0x00000000, 0x00000000 },
5679 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5682 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5683 u32 offset, rw_mask, ro_mask, save_val, val;
5684 u16 flags = reg_tbl[i].flags;
5686 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5689 offset = (u32) reg_tbl[i].offset;
5690 rw_mask = reg_tbl[i].rw_mask;
5691 ro_mask = reg_tbl[i].ro_mask;
5693 save_val = readl(bp->regview + offset);
5695 writel(0, bp->regview + offset);
5697 val = readl(bp->regview + offset);
5698 if ((val & rw_mask) != 0) {
5702 if ((val & ro_mask) != (save_val & ro_mask)) {
5706 writel(0xffffffff, bp->regview + offset);
5708 val = readl(bp->regview + offset);
5709 if ((val & rw_mask) != rw_mask) {
5713 if ((val & ro_mask) != (save_val & ro_mask)) {
5717 writel(save_val, bp->regview + offset);
5721 writel(save_val, bp->regview + offset);
5729 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5731 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5732 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5735 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5738 for (offset = 0; offset < size; offset += 4) {
5740 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5742 if (bnx2_reg_rd_ind(bp, start + offset) !=
5752 bnx2_test_memory(struct bnx2 *bp)
5756 static struct mem_entry {
5759 } mem_tbl_5706[] = {
5760 { 0x60000, 0x4000 },
5761 { 0xa0000, 0x3000 },
5762 { 0xe0000, 0x4000 },
5763 { 0x120000, 0x4000 },
5764 { 0x1a0000, 0x4000 },
5765 { 0x160000, 0x4000 },
5769 { 0x60000, 0x4000 },
5770 { 0xa0000, 0x3000 },
5771 { 0xe0000, 0x4000 },
5772 { 0x120000, 0x4000 },
5773 { 0x1a0000, 0x4000 },
5776 struct mem_entry *mem_tbl;
5778 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5779 mem_tbl = mem_tbl_5709;
5781 mem_tbl = mem_tbl_5706;
5783 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5784 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5785 mem_tbl[i].len)) != 0) {
5793 #define BNX2_MAC_LOOPBACK 0
5794 #define BNX2_PHY_LOOPBACK 1
5797 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5799 unsigned int pkt_size, num_pkts, i;
5800 struct sk_buff *skb;
5802 unsigned char *packet;
5803 u16 rx_start_idx, rx_idx;
5805 struct bnx2_tx_bd *txbd;
5806 struct bnx2_sw_bd *rx_buf;
5807 struct l2_fhdr *rx_hdr;
5809 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5810 struct bnx2_tx_ring_info *txr;
5811 struct bnx2_rx_ring_info *rxr;
5815 txr = &tx_napi->tx_ring;
5816 rxr = &bnapi->rx_ring;
5817 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5818 bp->loopback = MAC_LOOPBACK;
5819 bnx2_set_mac_loopback(bp);
5821 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5822 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5825 bp->loopback = PHY_LOOPBACK;
5826 bnx2_set_phy_loopback(bp);
5831 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5832 skb = netdev_alloc_skb(bp->dev, pkt_size);
5835 packet = skb_put(skb, pkt_size);
5836 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
5837 memset(packet + ETH_ALEN, 0x0, 8);
5838 for (i = 14; i < pkt_size; i++)
5839 packet[i] = (unsigned char) (i & 0xff);
5841 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5843 if (dma_mapping_error(&bp->pdev->dev, map)) {
5848 BNX2_WR(bp, BNX2_HC_COMMAND,
5849 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5851 BNX2_RD(bp, BNX2_HC_COMMAND);
5854 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5858 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)];
5860 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5861 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5862 txbd->tx_bd_mss_nbytes = pkt_size;
5863 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5866 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod);
5867 txr->tx_prod_bseq += pkt_size;
5869 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5870 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5874 BNX2_WR(bp, BNX2_HC_COMMAND,
5875 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5877 BNX2_RD(bp, BNX2_HC_COMMAND);
5881 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
5884 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5885 goto loopback_test_done;
5887 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5888 if (rx_idx != rx_start_idx + num_pkts) {
5889 goto loopback_test_done;
5892 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5893 data = rx_buf->data;
5895 rx_hdr = get_l2_fhdr(data);
5896 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
5898 dma_sync_single_for_cpu(&bp->pdev->dev,
5899 dma_unmap_addr(rx_buf, mapping),
5900 bp->rx_buf_use_size, DMA_FROM_DEVICE);
5902 if (rx_hdr->l2_fhdr_status &
5903 (L2_FHDR_ERRORS_BAD_CRC |
5904 L2_FHDR_ERRORS_PHY_DECODE |
5905 L2_FHDR_ERRORS_ALIGNMENT |
5906 L2_FHDR_ERRORS_TOO_SHORT |
5907 L2_FHDR_ERRORS_GIANT_FRAME)) {
5909 goto loopback_test_done;
5912 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5913 goto loopback_test_done;
5916 for (i = 14; i < pkt_size; i++) {
5917 if (*(data + i) != (unsigned char) (i & 0xff)) {
5918 goto loopback_test_done;
5929 #define BNX2_MAC_LOOPBACK_FAILED 1
5930 #define BNX2_PHY_LOOPBACK_FAILED 2
5931 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5932 BNX2_PHY_LOOPBACK_FAILED)
5935 bnx2_test_loopback(struct bnx2 *bp)
5939 if (!netif_running(bp->dev))
5940 return BNX2_LOOPBACK_FAILED;
5942 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5943 spin_lock_bh(&bp->phy_lock);
5944 bnx2_init_phy(bp, 1);
5945 spin_unlock_bh(&bp->phy_lock);
5946 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5947 rc |= BNX2_MAC_LOOPBACK_FAILED;
5948 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5949 rc |= BNX2_PHY_LOOPBACK_FAILED;
5953 #define NVRAM_SIZE 0x200
5954 #define CRC32_RESIDUAL 0xdebb20e3
5957 bnx2_test_nvram(struct bnx2 *bp)
5959 __be32 buf[NVRAM_SIZE / 4];
5960 u8 *data = (u8 *) buf;
5964 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5965 goto test_nvram_done;
5967 magic = be32_to_cpu(buf[0]);
5968 if (magic != 0x669955aa) {
5970 goto test_nvram_done;
5973 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5974 goto test_nvram_done;
5976 csum = ether_crc_le(0x100, data);
5977 if (csum != CRC32_RESIDUAL) {
5979 goto test_nvram_done;
5982 csum = ether_crc_le(0x100, data + 0x100);
5983 if (csum != CRC32_RESIDUAL) {
5992 bnx2_test_link(struct bnx2 *bp)
5996 if (!netif_running(bp->dev))
5999 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6004 spin_lock_bh(&bp->phy_lock);
6005 bnx2_enable_bmsr1(bp);
6006 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
6007 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
6008 bnx2_disable_bmsr1(bp);
6009 spin_unlock_bh(&bp->phy_lock);
6011 if (bmsr & BMSR_LSTATUS) {
6018 bnx2_test_intr(struct bnx2 *bp)
6023 if (!netif_running(bp->dev))
6026 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
6028 /* This register is not touched during run-time. */
6029 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
6030 BNX2_RD(bp, BNX2_HC_COMMAND);
6032 for (i = 0; i < 10; i++) {
6033 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
6039 msleep_interruptible(10);
6047 /* Determining link for parallel detection. */
6049 bnx2_5706_serdes_has_link(struct bnx2 *bp)
6051 u32 mode_ctl, an_dbg, exp;
6053 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
6056 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
6057 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
6059 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
6062 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6063 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6064 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6066 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
6069 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6070 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6071 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6073 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6080 bnx2_5706_serdes_timer(struct bnx2 *bp)
6084 spin_lock(&bp->phy_lock);
6085 if (bp->serdes_an_pending) {
6086 bp->serdes_an_pending--;
6088 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6091 bp->current_interval = BNX2_TIMER_INTERVAL;
6093 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6095 if (bmcr & BMCR_ANENABLE) {
6096 if (bnx2_5706_serdes_has_link(bp)) {
6097 bmcr &= ~BMCR_ANENABLE;
6098 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6099 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6100 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
6104 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
6105 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
6108 bnx2_write_phy(bp, 0x17, 0x0f01);
6109 bnx2_read_phy(bp, 0x15, &phy2);
6113 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6114 bmcr |= BMCR_ANENABLE;
6115 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6117 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6120 bp->current_interval = BNX2_TIMER_INTERVAL;
6125 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6126 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6127 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6129 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6130 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6131 bnx2_5706s_force_link_dn(bp, 1);
6132 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6135 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6138 spin_unlock(&bp->phy_lock);
6142 bnx2_5708_serdes_timer(struct bnx2 *bp)
6144 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6147 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6148 bp->serdes_an_pending = 0;
6152 spin_lock(&bp->phy_lock);
6153 if (bp->serdes_an_pending)
6154 bp->serdes_an_pending--;
6155 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6158 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6159 if (bmcr & BMCR_ANENABLE) {
6160 bnx2_enable_forced_2g5(bp);
6161 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6163 bnx2_disable_forced_2g5(bp);
6164 bp->serdes_an_pending = 2;
6165 bp->current_interval = BNX2_TIMER_INTERVAL;
6169 bp->current_interval = BNX2_TIMER_INTERVAL;
6171 spin_unlock(&bp->phy_lock);
6175 bnx2_timer(struct timer_list *t)
6177 struct bnx2 *bp = from_timer(bp, t, timer);
6179 if (!netif_running(bp->dev))
6182 if (atomic_read(&bp->intr_sem) != 0)
6183 goto bnx2_restart_timer;
6185 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6186 BNX2_FLAG_USING_MSI)
6187 bnx2_chk_missed_msi(bp);
6189 bnx2_send_heart_beat(bp);
6191 bp->stats_blk->stat_FwRxDrop =
6192 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6194 /* workaround occasional corrupted counters */
6195 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6196 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6197 BNX2_HC_COMMAND_STATS_NOW);
6199 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6200 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
6201 bnx2_5706_serdes_timer(bp);
6203 bnx2_5708_serdes_timer(bp);
6207 mod_timer(&bp->timer, jiffies + bp->current_interval);
6211 bnx2_request_irq(struct bnx2 *bp)
6213 unsigned long flags;
6214 struct bnx2_irq *irq;
6217 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6220 flags = IRQF_SHARED;
6222 for (i = 0; i < bp->irq_nvecs; i++) {
6223 irq = &bp->irq_tbl[i];
6224 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6234 __bnx2_free_irq(struct bnx2 *bp)
6236 struct bnx2_irq *irq;
6239 for (i = 0; i < bp->irq_nvecs; i++) {
6240 irq = &bp->irq_tbl[i];
6242 free_irq(irq->vector, &bp->bnx2_napi[i]);
6248 bnx2_free_irq(struct bnx2 *bp)
6251 __bnx2_free_irq(bp);
6252 if (bp->flags & BNX2_FLAG_USING_MSI)
6253 pci_disable_msi(bp->pdev);
6254 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6255 pci_disable_msix(bp->pdev);
6257 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6261 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6264 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6265 struct net_device *dev = bp->dev;
6266 const int len = sizeof(bp->irq_tbl[0].name);
6268 bnx2_setup_msix_tbl(bp);
6269 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6270 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6271 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6273 /* Need to flush the previous three writes to ensure MSI-X
6274 * is setup properly */
6275 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
6277 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6278 msix_ent[i].entry = i;
6279 msix_ent[i].vector = 0;
6282 total_vecs = msix_vecs;
6286 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,
6287 BNX2_MIN_MSIX_VEC, total_vecs);
6291 msix_vecs = total_vecs;
6295 bp->irq_nvecs = msix_vecs;
6296 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6297 for (i = 0; i < total_vecs; i++) {
6298 bp->irq_tbl[i].vector = msix_ent[i].vector;
6299 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6300 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6305 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6307 int cpus = netif_get_num_default_rss_queues();
6310 if (!bp->num_req_rx_rings)
6311 msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
6312 else if (!bp->num_req_tx_rings)
6313 msix_vecs = max(cpus, bp->num_req_rx_rings);
6315 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
6317 msix_vecs = min(msix_vecs, RX_MAX_RINGS);
6319 bp->irq_tbl[0].handler = bnx2_interrupt;
6320 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6322 bp->irq_tbl[0].vector = bp->pdev->irq;
6324 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
6325 bnx2_enable_msix(bp, msix_vecs);
6327 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6328 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6329 if (pci_enable_msi(bp->pdev) == 0) {
6330 bp->flags |= BNX2_FLAG_USING_MSI;
6331 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
6332 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6333 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6335 bp->irq_tbl[0].handler = bnx2_msi;
6337 bp->irq_tbl[0].vector = bp->pdev->irq;
6341 if (!bp->num_req_tx_rings)
6342 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6344 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
6346 if (!bp->num_req_rx_rings)
6347 bp->num_rx_rings = bp->irq_nvecs;
6349 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
6351 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
6353 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
6356 /* Called with rtnl_lock */
6358 bnx2_open(struct net_device *dev)
6360 struct bnx2 *bp = netdev_priv(dev);
6363 rc = bnx2_request_firmware(bp);
6367 netif_carrier_off(dev);
6369 bnx2_disable_int(bp);
6371 rc = bnx2_setup_int_mode(bp, disable_msi);
6375 bnx2_napi_enable(bp);
6376 rc = bnx2_alloc_mem(bp);
6380 rc = bnx2_request_irq(bp);
6384 rc = bnx2_init_nic(bp, 1);
6388 mod_timer(&bp->timer, jiffies + bp->current_interval);
6390 atomic_set(&bp->intr_sem, 0);
6392 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6394 bnx2_enable_int(bp);
6396 if (bp->flags & BNX2_FLAG_USING_MSI) {
6397 /* Test MSI to make sure it is working
6398 * If MSI test fails, go back to INTx mode
6400 if (bnx2_test_intr(bp) != 0) {
6401 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6403 bnx2_disable_int(bp);
6406 bnx2_setup_int_mode(bp, 1);
6408 rc = bnx2_init_nic(bp, 0);
6411 rc = bnx2_request_irq(bp);
6414 del_timer_sync(&bp->timer);
6417 bnx2_enable_int(bp);
6420 if (bp->flags & BNX2_FLAG_USING_MSI)
6421 netdev_info(dev, "using MSI\n");
6422 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6423 netdev_info(dev, "using MSIX\n");
6425 netif_tx_start_all_queues(dev);
6430 bnx2_napi_disable(bp);
6435 bnx2_release_firmware(bp);
6440 bnx2_reset_task(struct work_struct *work)
6442 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6447 if (!netif_running(bp->dev)) {
6452 bnx2_netif_stop(bp, true);
6454 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);
6455 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
6456 /* in case PCI block has reset */
6457 pci_restore_state(bp->pdev);
6458 pci_save_state(bp->pdev);
6460 rc = bnx2_init_nic(bp, 1);
6462 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6463 bnx2_napi_enable(bp);
6469 atomic_set(&bp->intr_sem, 1);
6470 bnx2_netif_start(bp, true);
6474 #define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
6477 bnx2_dump_ftq(struct bnx2 *bp)
6480 u32 reg, bdidx, cid, valid;
6481 struct net_device *dev = bp->dev;
6482 static const struct ftq_reg {
6486 BNX2_FTQ_ENTRY(RV2P_P),
6487 BNX2_FTQ_ENTRY(RV2P_T),
6488 BNX2_FTQ_ENTRY(RV2P_M),
6489 BNX2_FTQ_ENTRY(TBDR_),
6490 BNX2_FTQ_ENTRY(TDMA_),
6491 BNX2_FTQ_ENTRY(TXP_),
6492 BNX2_FTQ_ENTRY(TXP_),
6493 BNX2_FTQ_ENTRY(TPAT_),
6494 BNX2_FTQ_ENTRY(RXP_C),
6495 BNX2_FTQ_ENTRY(RXP_),
6496 BNX2_FTQ_ENTRY(COM_COMXQ_),
6497 BNX2_FTQ_ENTRY(COM_COMTQ_),
6498 BNX2_FTQ_ENTRY(COM_COMQ_),
6499 BNX2_FTQ_ENTRY(CP_CPQ_),
6502 netdev_err(dev, "<--- start FTQ dump --->\n");
6503 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
6504 netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
6505 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6507 netdev_err(dev, "CPU states:\n");
6508 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
6509 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
6510 reg, bnx2_reg_rd_ind(bp, reg),
6511 bnx2_reg_rd_ind(bp, reg + 4),
6512 bnx2_reg_rd_ind(bp, reg + 8),
6513 bnx2_reg_rd_ind(bp, reg + 0x1c),
6514 bnx2_reg_rd_ind(bp, reg + 0x1c),
6515 bnx2_reg_rd_ind(bp, reg + 0x20));
6517 netdev_err(dev, "<--- end FTQ dump --->\n");
6518 netdev_err(dev, "<--- start TBDC dump --->\n");
6519 netdev_err(dev, "TBDC free cnt: %ld\n",
6520 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
6521 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
6522 for (i = 0; i < 0x20; i++) {
6525 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6526 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6527 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
6528 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6529 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
6530 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
6533 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6534 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6535 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
6536 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
6537 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
6538 bdidx >> 24, (valid >> 8) & 0x0ff);
6540 netdev_err(dev, "<--- end TBDC dump --->\n");
6544 bnx2_dump_state(struct bnx2 *bp)
6546 struct net_device *dev = bp->dev;
6549 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6550 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6551 atomic_read(&bp->intr_sem), val1);
6552 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6553 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6554 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
6555 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6556 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6557 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
6558 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6559 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6560 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6561 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6562 if (bp->flags & BNX2_FLAG_USING_MSIX)
6563 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6564 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6568 bnx2_tx_timeout(struct net_device *dev, unsigned int txqueue)
6570 struct bnx2 *bp = netdev_priv(dev);
6573 bnx2_dump_state(bp);
6574 bnx2_dump_mcp_state(bp);
6576 /* This allows the netif to be shutdown gracefully before resetting */
6577 schedule_work(&bp->reset_task);
6580 /* Called with netif_tx_lock.
6581 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6582 * netif_wake_queue().
6585 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6587 struct bnx2 *bp = netdev_priv(dev);
6589 struct bnx2_tx_bd *txbd;
6590 struct bnx2_sw_tx_bd *tx_buf;
6591 u32 len, vlan_tag_flags, last_frag, mss;
6592 u16 prod, ring_prod;
6594 struct bnx2_napi *bnapi;
6595 struct bnx2_tx_ring_info *txr;
6596 struct netdev_queue *txq;
6598 /* Determine which tx ring we will be placed on */
6599 i = skb_get_queue_mapping(skb);
6600 bnapi = &bp->bnx2_napi[i];
6601 txr = &bnapi->tx_ring;
6602 txq = netdev_get_tx_queue(dev, i);
6604 if (unlikely(bnx2_tx_avail(bp, txr) <
6605 (skb_shinfo(skb)->nr_frags + 1))) {
6606 netif_tx_stop_queue(txq);
6607 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6609 return NETDEV_TX_BUSY;
6611 len = skb_headlen(skb);
6612 prod = txr->tx_prod;
6613 ring_prod = BNX2_TX_RING_IDX(prod);
6616 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6617 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6620 if (skb_vlan_tag_present(skb)) {
6622 (TX_BD_FLAGS_VLAN_TAG | (skb_vlan_tag_get(skb) << 16));
6625 if ((mss = skb_shinfo(skb)->gso_size)) {
6629 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6631 tcp_opt_len = tcp_optlen(skb);
6633 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6634 u32 tcp_off = skb_transport_offset(skb) -
6635 sizeof(struct ipv6hdr) - ETH_HLEN;
6637 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6638 TX_BD_FLAGS_SW_FLAGS;
6639 if (likely(tcp_off == 0))
6640 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6643 vlan_tag_flags |= ((tcp_off & 0x3) <<
6644 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6645 ((tcp_off & 0x10) <<
6646 TX_BD_FLAGS_TCP6_OFF4_SHL);
6647 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6651 if (tcp_opt_len || (iph->ihl > 5)) {
6652 vlan_tag_flags |= ((iph->ihl - 5) +
6653 (tcp_opt_len >> 2)) << 8;
6659 mapping = dma_map_single(&bp->pdev->dev, skb->data, len,
6661 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
6662 dev_kfree_skb_any(skb);
6663 return NETDEV_TX_OK;
6666 tx_buf = &txr->tx_buf_ring[ring_prod];
6668 dma_unmap_addr_set(tx_buf, mapping, mapping);
6670 txbd = &txr->tx_desc_ring[ring_prod];
6672 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6673 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6674 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6675 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6677 last_frag = skb_shinfo(skb)->nr_frags;
6678 tx_buf->nr_frags = last_frag;
6679 tx_buf->is_gso = skb_is_gso(skb);
6681 for (i = 0; i < last_frag; i++) {
6682 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6684 prod = BNX2_NEXT_TX_BD(prod);
6685 ring_prod = BNX2_TX_RING_IDX(prod);
6686 txbd = &txr->tx_desc_ring[ring_prod];
6688 len = skb_frag_size(frag);
6689 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
6691 if (dma_mapping_error(&bp->pdev->dev, mapping))
6693 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6696 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6697 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6698 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6699 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6702 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6704 /* Sync BD data before updating TX mailbox */
6707 netdev_tx_sent_queue(txq, skb->len);
6709 prod = BNX2_NEXT_TX_BD(prod);
6710 txr->tx_prod_bseq += skb->len;
6712 BNX2_WR16(bp, txr->tx_bidx_addr, prod);
6713 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6715 txr->tx_prod = prod;
6717 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6718 netif_tx_stop_queue(txq);
6720 /* netif_tx_stop_queue() must be done before checking
6721 * tx index in bnx2_tx_avail() below, because in
6722 * bnx2_tx_int(), we update tx index before checking for
6723 * netif_tx_queue_stopped().
6726 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6727 netif_tx_wake_queue(txq);
6730 return NETDEV_TX_OK;
6732 /* save value of frag that failed */
6735 /* start back at beginning and unmap skb */
6736 prod = txr->tx_prod;
6737 ring_prod = BNX2_TX_RING_IDX(prod);
6738 tx_buf = &txr->tx_buf_ring[ring_prod];
6740 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6741 skb_headlen(skb), DMA_TO_DEVICE);
6743 /* unmap remaining mapped pages */
6744 for (i = 0; i < last_frag; i++) {
6745 prod = BNX2_NEXT_TX_BD(prod);
6746 ring_prod = BNX2_TX_RING_IDX(prod);
6747 tx_buf = &txr->tx_buf_ring[ring_prod];
6748 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6749 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6753 dev_kfree_skb_any(skb);
6754 return NETDEV_TX_OK;
6757 /* Called with rtnl_lock */
6759 bnx2_close(struct net_device *dev)
6761 struct bnx2 *bp = netdev_priv(dev);
6763 bnx2_disable_int_sync(bp);
6764 bnx2_napi_disable(bp);
6765 netif_tx_disable(dev);
6766 del_timer_sync(&bp->timer);
6767 bnx2_shutdown_chip(bp);
6773 netif_carrier_off(bp->dev);
6778 bnx2_save_stats(struct bnx2 *bp)
6780 u32 *hw_stats = (u32 *) bp->stats_blk;
6781 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6784 /* The 1st 10 counters are 64-bit counters */
6785 for (i = 0; i < 20; i += 2) {
6789 hi = temp_stats[i] + hw_stats[i];
6790 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6791 if (lo > 0xffffffff)
6794 temp_stats[i + 1] = lo & 0xffffffff;
6797 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6798 temp_stats[i] += hw_stats[i];
6801 #define GET_64BIT_NET_STATS64(ctr) \
6802 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
6804 #define GET_64BIT_NET_STATS(ctr) \
6805 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6806 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6808 #define GET_32BIT_NET_STATS(ctr) \
6809 (unsigned long) (bp->stats_blk->ctr + \
6810 bp->temp_stats_blk->ctr)
6813 bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
6815 struct bnx2 *bp = netdev_priv(dev);
6820 net_stats->rx_packets =
6821 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6822 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6823 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6825 net_stats->tx_packets =
6826 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6827 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6828 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6830 net_stats->rx_bytes =
6831 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6833 net_stats->tx_bytes =
6834 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6836 net_stats->multicast =
6837 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
6839 net_stats->collisions =
6840 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6842 net_stats->rx_length_errors =
6843 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6844 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6846 net_stats->rx_over_errors =
6847 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6848 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6850 net_stats->rx_frame_errors =
6851 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6853 net_stats->rx_crc_errors =
6854 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6856 net_stats->rx_errors = net_stats->rx_length_errors +
6857 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6858 net_stats->rx_crc_errors;
6860 net_stats->tx_aborted_errors =
6861 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6862 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6864 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
6865 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
6866 net_stats->tx_carrier_errors = 0;
6868 net_stats->tx_carrier_errors =
6869 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6872 net_stats->tx_errors =
6873 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6874 net_stats->tx_aborted_errors +
6875 net_stats->tx_carrier_errors;
6877 net_stats->rx_missed_errors =
6878 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6879 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6880 GET_32BIT_NET_STATS(stat_FwRxDrop);
6884 /* All ethtool functions called with rtnl_lock */
6887 bnx2_get_link_ksettings(struct net_device *dev,
6888 struct ethtool_link_ksettings *cmd)
6890 struct bnx2 *bp = netdev_priv(dev);
6891 int support_serdes = 0, support_copper = 0;
6892 u32 supported, advertising;
6894 supported = SUPPORTED_Autoneg;
6895 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6898 } else if (bp->phy_port == PORT_FIBRE)
6903 if (support_serdes) {
6904 supported |= SUPPORTED_1000baseT_Full |
6906 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6907 supported |= SUPPORTED_2500baseX_Full;
6909 if (support_copper) {
6910 supported |= SUPPORTED_10baseT_Half |
6911 SUPPORTED_10baseT_Full |
6912 SUPPORTED_100baseT_Half |
6913 SUPPORTED_100baseT_Full |
6914 SUPPORTED_1000baseT_Full |
6918 spin_lock_bh(&bp->phy_lock);
6919 cmd->base.port = bp->phy_port;
6920 advertising = bp->advertising;
6922 if (bp->autoneg & AUTONEG_SPEED) {
6923 cmd->base.autoneg = AUTONEG_ENABLE;
6925 cmd->base.autoneg = AUTONEG_DISABLE;
6928 if (netif_carrier_ok(dev)) {
6929 cmd->base.speed = bp->line_speed;
6930 cmd->base.duplex = bp->duplex;
6931 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {
6932 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)
6933 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
6935 cmd->base.eth_tp_mdix = ETH_TP_MDI;
6939 cmd->base.speed = SPEED_UNKNOWN;
6940 cmd->base.duplex = DUPLEX_UNKNOWN;
6942 spin_unlock_bh(&bp->phy_lock);
6944 cmd->base.phy_address = bp->phy_addr;
6946 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
6948 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
6955 bnx2_set_link_ksettings(struct net_device *dev,
6956 const struct ethtool_link_ksettings *cmd)
6958 struct bnx2 *bp = netdev_priv(dev);
6959 u8 autoneg = bp->autoneg;
6960 u8 req_duplex = bp->req_duplex;
6961 u16 req_line_speed = bp->req_line_speed;
6962 u32 advertising = bp->advertising;
6965 spin_lock_bh(&bp->phy_lock);
6967 if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE)
6968 goto err_out_unlock;
6970 if (cmd->base.port != bp->phy_port &&
6971 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6972 goto err_out_unlock;
6974 /* If device is down, we can store the settings only if the user
6975 * is setting the currently active port.
6977 if (!netif_running(dev) && cmd->base.port != bp->phy_port)
6978 goto err_out_unlock;
6980 if (cmd->base.autoneg == AUTONEG_ENABLE) {
6981 autoneg |= AUTONEG_SPEED;
6983 ethtool_convert_link_mode_to_legacy_u32(
6984 &advertising, cmd->link_modes.advertising);
6986 if (cmd->base.port == PORT_TP) {
6987 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6989 advertising = ETHTOOL_ALL_COPPER_SPEED;
6991 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6993 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6995 advertising |= ADVERTISED_Autoneg;
6998 u32 speed = cmd->base.speed;
7000 if (cmd->base.port == PORT_FIBRE) {
7001 if ((speed != SPEED_1000 &&
7002 speed != SPEED_2500) ||
7003 (cmd->base.duplex != DUPLEX_FULL))
7004 goto err_out_unlock;
7006 if (speed == SPEED_2500 &&
7007 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7008 goto err_out_unlock;
7009 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7010 goto err_out_unlock;
7012 autoneg &= ~AUTONEG_SPEED;
7013 req_line_speed = speed;
7014 req_duplex = cmd->base.duplex;
7018 bp->autoneg = autoneg;
7019 bp->advertising = advertising;
7020 bp->req_line_speed = req_line_speed;
7021 bp->req_duplex = req_duplex;
7024 /* If device is down, the new settings will be picked up when it is
7027 if (netif_running(dev))
7028 err = bnx2_setup_phy(bp, cmd->base.port);
7031 spin_unlock_bh(&bp->phy_lock);
7037 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7039 struct bnx2 *bp = netdev_priv(dev);
7041 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
7042 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
7043 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
7046 #define BNX2_REGDUMP_LEN (32 * 1024)
7049 bnx2_get_regs_len(struct net_device *dev)
7051 return BNX2_REGDUMP_LEN;
7055 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
7057 u32 *p = _p, i, offset;
7059 struct bnx2 *bp = netdev_priv(dev);
7060 static const u32 reg_boundaries[] = {
7061 0x0000, 0x0098, 0x0400, 0x045c,
7062 0x0800, 0x0880, 0x0c00, 0x0c10,
7063 0x0c30, 0x0d08, 0x1000, 0x101c,
7064 0x1040, 0x1048, 0x1080, 0x10a4,
7065 0x1400, 0x1490, 0x1498, 0x14f0,
7066 0x1500, 0x155c, 0x1580, 0x15dc,
7067 0x1600, 0x1658, 0x1680, 0x16d8,
7068 0x1800, 0x1820, 0x1840, 0x1854,
7069 0x1880, 0x1894, 0x1900, 0x1984,
7070 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
7071 0x1c80, 0x1c94, 0x1d00, 0x1d84,
7072 0x2000, 0x2030, 0x23c0, 0x2400,
7073 0x2800, 0x2820, 0x2830, 0x2850,
7074 0x2b40, 0x2c10, 0x2fc0, 0x3058,
7075 0x3c00, 0x3c94, 0x4000, 0x4010,
7076 0x4080, 0x4090, 0x43c0, 0x4458,
7077 0x4c00, 0x4c18, 0x4c40, 0x4c54,
7078 0x4fc0, 0x5010, 0x53c0, 0x5444,
7079 0x5c00, 0x5c18, 0x5c80, 0x5c90,
7080 0x5fc0, 0x6000, 0x6400, 0x6428,
7081 0x6800, 0x6848, 0x684c, 0x6860,
7082 0x6888, 0x6910, 0x8000
7087 memset(p, 0, BNX2_REGDUMP_LEN);
7089 if (!netif_running(bp->dev))
7093 offset = reg_boundaries[0];
7095 while (offset < BNX2_REGDUMP_LEN) {
7096 *p++ = BNX2_RD(bp, offset);
7098 if (offset == reg_boundaries[i + 1]) {
7099 offset = reg_boundaries[i + 2];
7100 p = (u32 *) (orig_p + offset);
7107 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7109 struct bnx2 *bp = netdev_priv(dev);
7111 if (bp->flags & BNX2_FLAG_NO_WOL) {
7116 wol->supported = WAKE_MAGIC;
7118 wol->wolopts = WAKE_MAGIC;
7122 memset(&wol->sopass, 0, sizeof(wol->sopass));
7126 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7128 struct bnx2 *bp = netdev_priv(dev);
7130 if (wol->wolopts & ~WAKE_MAGIC)
7133 if (wol->wolopts & WAKE_MAGIC) {
7134 if (bp->flags & BNX2_FLAG_NO_WOL)
7143 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
7149 bnx2_nway_reset(struct net_device *dev)
7151 struct bnx2 *bp = netdev_priv(dev);
7154 if (!netif_running(dev))
7157 if (!(bp->autoneg & AUTONEG_SPEED)) {
7161 spin_lock_bh(&bp->phy_lock);
7163 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7166 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7167 spin_unlock_bh(&bp->phy_lock);
7171 /* Force a link down visible on the other side */
7172 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7173 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
7174 spin_unlock_bh(&bp->phy_lock);
7178 spin_lock_bh(&bp->phy_lock);
7180 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
7181 bp->serdes_an_pending = 1;
7182 mod_timer(&bp->timer, jiffies + bp->current_interval);
7185 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
7186 bmcr &= ~BMCR_LOOPBACK;
7187 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
7189 spin_unlock_bh(&bp->phy_lock);
7195 bnx2_get_link(struct net_device *dev)
7197 struct bnx2 *bp = netdev_priv(dev);
7203 bnx2_get_eeprom_len(struct net_device *dev)
7205 struct bnx2 *bp = netdev_priv(dev);
7207 if (!bp->flash_info)
7210 return (int) bp->flash_size;
7214 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7217 struct bnx2 *bp = netdev_priv(dev);
7220 /* parameters already validated in ethtool_get_eeprom */
7222 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7228 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7231 struct bnx2 *bp = netdev_priv(dev);
7234 /* parameters already validated in ethtool_set_eeprom */
7236 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7241 static int bnx2_get_coalesce(struct net_device *dev,
7242 struct ethtool_coalesce *coal,
7243 struct kernel_ethtool_coalesce *kernel_coal,
7244 struct netlink_ext_ack *extack)
7246 struct bnx2 *bp = netdev_priv(dev);
7248 memset(coal, 0, sizeof(struct ethtool_coalesce));
7250 coal->rx_coalesce_usecs = bp->rx_ticks;
7251 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7252 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7253 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7255 coal->tx_coalesce_usecs = bp->tx_ticks;
7256 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7257 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7258 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7260 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7265 static int bnx2_set_coalesce(struct net_device *dev,
7266 struct ethtool_coalesce *coal,
7267 struct kernel_ethtool_coalesce *kernel_coal,
7268 struct netlink_ext_ack *extack)
7270 struct bnx2 *bp = netdev_priv(dev);
7272 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7273 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7275 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7276 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7278 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7279 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7281 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7282 if (bp->rx_quick_cons_trip_int > 0xff)
7283 bp->rx_quick_cons_trip_int = 0xff;
7285 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7286 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7288 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7289 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7291 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7292 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7294 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7295 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7298 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7299 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7300 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7301 bp->stats_ticks = USEC_PER_SEC;
7303 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7304 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7305 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7307 if (netif_running(bp->dev)) {
7308 bnx2_netif_stop(bp, true);
7309 bnx2_init_nic(bp, 0);
7310 bnx2_netif_start(bp, true);
7317 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering,
7318 struct kernel_ethtool_ringparam *kernel_ering,
7319 struct netlink_ext_ack *extack)
7321 struct bnx2 *bp = netdev_priv(dev);
7323 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT;
7324 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
7326 ering->rx_pending = bp->rx_ring_size;
7327 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7329 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT;
7330 ering->tx_pending = bp->tx_ring_size;
7334 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
7336 if (netif_running(bp->dev)) {
7337 /* Reset will erase chipset stats; save them */
7338 bnx2_save_stats(bp);
7340 bnx2_netif_stop(bp, true);
7341 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7346 __bnx2_free_irq(bp);
7352 bnx2_set_rx_ring_size(bp, rx);
7353 bp->tx_ring_size = tx;
7355 if (netif_running(bp->dev)) {
7359 rc = bnx2_setup_int_mode(bp, disable_msi);
7364 rc = bnx2_alloc_mem(bp);
7367 rc = bnx2_request_irq(bp);
7370 rc = bnx2_init_nic(bp, 0);
7373 bnx2_napi_enable(bp);
7378 mutex_lock(&bp->cnic_lock);
7379 /* Let cnic know about the new status block. */
7380 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7381 bnx2_setup_cnic_irq_info(bp);
7382 mutex_unlock(&bp->cnic_lock);
7384 bnx2_netif_start(bp, true);
7390 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering,
7391 struct kernel_ethtool_ringparam *kernel_ering,
7392 struct netlink_ext_ack *extack)
7394 struct bnx2 *bp = netdev_priv(dev);
7397 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) ||
7398 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) ||
7399 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7403 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
7409 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7411 struct bnx2 *bp = netdev_priv(dev);
7413 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7414 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7415 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7419 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7421 struct bnx2 *bp = netdev_priv(dev);
7423 bp->req_flow_ctrl = 0;
7424 if (epause->rx_pause)
7425 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7426 if (epause->tx_pause)
7427 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7429 if (epause->autoneg) {
7430 bp->autoneg |= AUTONEG_FLOW_CTRL;
7433 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7436 if (netif_running(dev)) {
7437 spin_lock_bh(&bp->phy_lock);
7438 bnx2_setup_phy(bp, bp->phy_port);
7439 spin_unlock_bh(&bp->phy_lock);
7446 char string[ETH_GSTRING_LEN];
7447 } bnx2_stats_str_arr[] = {
7449 { "rx_error_bytes" },
7451 { "tx_error_bytes" },
7452 { "rx_ucast_packets" },
7453 { "rx_mcast_packets" },
7454 { "rx_bcast_packets" },
7455 { "tx_ucast_packets" },
7456 { "tx_mcast_packets" },
7457 { "tx_bcast_packets" },
7458 { "tx_mac_errors" },
7459 { "tx_carrier_errors" },
7460 { "rx_crc_errors" },
7461 { "rx_align_errors" },
7462 { "tx_single_collisions" },
7463 { "tx_multi_collisions" },
7465 { "tx_excess_collisions" },
7466 { "tx_late_collisions" },
7467 { "tx_total_collisions" },
7470 { "rx_undersize_packets" },
7471 { "rx_oversize_packets" },
7472 { "rx_64_byte_packets" },
7473 { "rx_65_to_127_byte_packets" },
7474 { "rx_128_to_255_byte_packets" },
7475 { "rx_256_to_511_byte_packets" },
7476 { "rx_512_to_1023_byte_packets" },
7477 { "rx_1024_to_1522_byte_packets" },
7478 { "rx_1523_to_9022_byte_packets" },
7479 { "tx_64_byte_packets" },
7480 { "tx_65_to_127_byte_packets" },
7481 { "tx_128_to_255_byte_packets" },
7482 { "tx_256_to_511_byte_packets" },
7483 { "tx_512_to_1023_byte_packets" },
7484 { "tx_1024_to_1522_byte_packets" },
7485 { "tx_1523_to_9022_byte_packets" },
7486 { "rx_xon_frames" },
7487 { "rx_xoff_frames" },
7488 { "tx_xon_frames" },
7489 { "tx_xoff_frames" },
7490 { "rx_mac_ctrl_frames" },
7491 { "rx_filtered_packets" },
7492 { "rx_ftq_discards" },
7494 { "rx_fw_discards" },
7497 #define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr)
7499 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7501 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7502 STATS_OFFSET32(stat_IfHCInOctets_hi),
7503 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7504 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7505 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7506 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7507 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7508 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7509 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7510 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7511 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7512 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7513 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7514 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7515 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7516 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7517 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7518 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7519 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7520 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7521 STATS_OFFSET32(stat_EtherStatsCollisions),
7522 STATS_OFFSET32(stat_EtherStatsFragments),
7523 STATS_OFFSET32(stat_EtherStatsJabbers),
7524 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7525 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7526 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7527 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7528 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7529 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7530 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7531 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7532 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7533 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7534 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7535 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7536 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7537 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7538 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7539 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7540 STATS_OFFSET32(stat_XonPauseFramesReceived),
7541 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7542 STATS_OFFSET32(stat_OutXonSent),
7543 STATS_OFFSET32(stat_OutXoffSent),
7544 STATS_OFFSET32(stat_MacControlFramesReceived),
7545 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7546 STATS_OFFSET32(stat_IfInFTQDiscards),
7547 STATS_OFFSET32(stat_IfInMBUFDiscards),
7548 STATS_OFFSET32(stat_FwRxDrop),
7551 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7552 * skipped because of errata.
7554 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7555 8,0,8,8,8,8,8,8,8,8,
7556 4,0,4,4,4,4,4,4,4,4,
7557 4,4,4,4,4,4,4,4,4,4,
7558 4,4,4,4,4,4,4,4,4,4,
7562 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7563 8,0,8,8,8,8,8,8,8,8,
7564 4,4,4,4,4,4,4,4,4,4,
7565 4,4,4,4,4,4,4,4,4,4,
7566 4,4,4,4,4,4,4,4,4,4,
7570 #define BNX2_NUM_TESTS 6
7573 char string[ETH_GSTRING_LEN];
7574 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7575 { "register_test (offline)" },
7576 { "memory_test (offline)" },
7577 { "loopback_test (offline)" },
7578 { "nvram_test (online)" },
7579 { "interrupt_test (online)" },
7580 { "link_test (online)" },
7584 bnx2_get_sset_count(struct net_device *dev, int sset)
7588 return BNX2_NUM_TESTS;
7590 return BNX2_NUM_STATS;
7597 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7599 struct bnx2 *bp = netdev_priv(dev);
7601 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7602 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7605 bnx2_netif_stop(bp, true);
7606 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7609 if (bnx2_test_registers(bp) != 0) {
7611 etest->flags |= ETH_TEST_FL_FAILED;
7613 if (bnx2_test_memory(bp) != 0) {
7615 etest->flags |= ETH_TEST_FL_FAILED;
7617 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7618 etest->flags |= ETH_TEST_FL_FAILED;
7620 if (!netif_running(bp->dev))
7621 bnx2_shutdown_chip(bp);
7623 bnx2_init_nic(bp, 1);
7624 bnx2_netif_start(bp, true);
7627 /* wait for link up */
7628 for (i = 0; i < 7; i++) {
7631 msleep_interruptible(1000);
7635 if (bnx2_test_nvram(bp) != 0) {
7637 etest->flags |= ETH_TEST_FL_FAILED;
7639 if (bnx2_test_intr(bp) != 0) {
7641 etest->flags |= ETH_TEST_FL_FAILED;
7644 if (bnx2_test_link(bp) != 0) {
7646 etest->flags |= ETH_TEST_FL_FAILED;
7652 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7654 switch (stringset) {
7656 memcpy(buf, bnx2_stats_str_arr,
7657 sizeof(bnx2_stats_str_arr));
7660 memcpy(buf, bnx2_tests_str_arr,
7661 sizeof(bnx2_tests_str_arr));
7667 bnx2_get_ethtool_stats(struct net_device *dev,
7668 struct ethtool_stats *stats, u64 *buf)
7670 struct bnx2 *bp = netdev_priv(dev);
7672 u32 *hw_stats = (u32 *) bp->stats_blk;
7673 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7674 u8 *stats_len_arr = NULL;
7677 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7681 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
7682 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||
7683 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||
7684 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
7685 stats_len_arr = bnx2_5706_stats_len_arr;
7687 stats_len_arr = bnx2_5708_stats_len_arr;
7689 for (i = 0; i < BNX2_NUM_STATS; i++) {
7690 unsigned long offset;
7692 if (stats_len_arr[i] == 0) {
7693 /* skip this counter */
7698 offset = bnx2_stats_offset_arr[i];
7699 if (stats_len_arr[i] == 4) {
7700 /* 4-byte counter */
7701 buf[i] = (u64) *(hw_stats + offset) +
7702 *(temp_stats + offset);
7705 /* 8-byte counter */
7706 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7707 *(hw_stats + offset + 1) +
7708 (((u64) *(temp_stats + offset)) << 32) +
7709 *(temp_stats + offset + 1);
7714 bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
7716 struct bnx2 *bp = netdev_priv(dev);
7719 case ETHTOOL_ID_ACTIVE:
7720 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7721 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7722 return 1; /* cycle on/off once per second */
7725 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7726 BNX2_EMAC_LED_1000MB_OVERRIDE |
7727 BNX2_EMAC_LED_100MB_OVERRIDE |
7728 BNX2_EMAC_LED_10MB_OVERRIDE |
7729 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7730 BNX2_EMAC_LED_TRAFFIC);
7733 case ETHTOOL_ID_OFF:
7734 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7737 case ETHTOOL_ID_INACTIVE:
7738 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7739 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7747 bnx2_set_features(struct net_device *dev, netdev_features_t features)
7749 struct bnx2 *bp = netdev_priv(dev);
7751 /* TSO with VLAN tag won't work with current firmware */
7752 if (features & NETIF_F_HW_VLAN_CTAG_TX)
7753 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7755 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7757 if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) !=
7758 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7759 netif_running(dev)) {
7760 bnx2_netif_stop(bp, false);
7761 dev->features = features;
7762 bnx2_set_rx_mode(dev);
7763 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7764 bnx2_netif_start(bp, false);
7771 static void bnx2_get_channels(struct net_device *dev,
7772 struct ethtool_channels *channels)
7774 struct bnx2 *bp = netdev_priv(dev);
7775 u32 max_rx_rings = 1;
7776 u32 max_tx_rings = 1;
7778 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7779 max_rx_rings = RX_MAX_RINGS;
7780 max_tx_rings = TX_MAX_RINGS;
7783 channels->max_rx = max_rx_rings;
7784 channels->max_tx = max_tx_rings;
7785 channels->max_other = 0;
7786 channels->max_combined = 0;
7787 channels->rx_count = bp->num_rx_rings;
7788 channels->tx_count = bp->num_tx_rings;
7789 channels->other_count = 0;
7790 channels->combined_count = 0;
7793 static int bnx2_set_channels(struct net_device *dev,
7794 struct ethtool_channels *channels)
7796 struct bnx2 *bp = netdev_priv(dev);
7797 u32 max_rx_rings = 1;
7798 u32 max_tx_rings = 1;
7801 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7802 max_rx_rings = RX_MAX_RINGS;
7803 max_tx_rings = TX_MAX_RINGS;
7805 if (channels->rx_count > max_rx_rings ||
7806 channels->tx_count > max_tx_rings)
7809 bp->num_req_rx_rings = channels->rx_count;
7810 bp->num_req_tx_rings = channels->tx_count;
7812 if (netif_running(dev))
7813 rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
7814 bp->tx_ring_size, true);
7819 static const struct ethtool_ops bnx2_ethtool_ops = {
7820 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
7821 ETHTOOL_COALESCE_MAX_FRAMES |
7822 ETHTOOL_COALESCE_USECS_IRQ |
7823 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
7824 ETHTOOL_COALESCE_STATS_BLOCK_USECS,
7825 .get_drvinfo = bnx2_get_drvinfo,
7826 .get_regs_len = bnx2_get_regs_len,
7827 .get_regs = bnx2_get_regs,
7828 .get_wol = bnx2_get_wol,
7829 .set_wol = bnx2_set_wol,
7830 .nway_reset = bnx2_nway_reset,
7831 .get_link = bnx2_get_link,
7832 .get_eeprom_len = bnx2_get_eeprom_len,
7833 .get_eeprom = bnx2_get_eeprom,
7834 .set_eeprom = bnx2_set_eeprom,
7835 .get_coalesce = bnx2_get_coalesce,
7836 .set_coalesce = bnx2_set_coalesce,
7837 .get_ringparam = bnx2_get_ringparam,
7838 .set_ringparam = bnx2_set_ringparam,
7839 .get_pauseparam = bnx2_get_pauseparam,
7840 .set_pauseparam = bnx2_set_pauseparam,
7841 .self_test = bnx2_self_test,
7842 .get_strings = bnx2_get_strings,
7843 .set_phys_id = bnx2_set_phys_id,
7844 .get_ethtool_stats = bnx2_get_ethtool_stats,
7845 .get_sset_count = bnx2_get_sset_count,
7846 .get_channels = bnx2_get_channels,
7847 .set_channels = bnx2_set_channels,
7848 .get_link_ksettings = bnx2_get_link_ksettings,
7849 .set_link_ksettings = bnx2_set_link_ksettings,
7852 /* Called with rtnl_lock */
7854 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7856 struct mii_ioctl_data *data = if_mii(ifr);
7857 struct bnx2 *bp = netdev_priv(dev);
7862 data->phy_id = bp->phy_addr;
7868 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7871 if (!netif_running(dev))
7874 spin_lock_bh(&bp->phy_lock);
7875 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7876 spin_unlock_bh(&bp->phy_lock);
7878 data->val_out = mii_regval;
7884 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7887 if (!netif_running(dev))
7890 spin_lock_bh(&bp->phy_lock);
7891 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7892 spin_unlock_bh(&bp->phy_lock);
7903 /* Called with rtnl_lock */
7905 bnx2_change_mac_addr(struct net_device *dev, void *p)
7907 struct sockaddr *addr = p;
7908 struct bnx2 *bp = netdev_priv(dev);
7910 if (!is_valid_ether_addr(addr->sa_data))
7911 return -EADDRNOTAVAIL;
7913 eth_hw_addr_set(dev, addr->sa_data);
7914 if (netif_running(dev))
7915 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7920 /* Called with rtnl_lock */
7922 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7924 struct bnx2 *bp = netdev_priv(dev);
7927 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7931 #ifdef CONFIG_NET_POLL_CONTROLLER
7933 poll_bnx2(struct net_device *dev)
7935 struct bnx2 *bp = netdev_priv(dev);
7938 for (i = 0; i < bp->irq_nvecs; i++) {
7939 struct bnx2_irq *irq = &bp->irq_tbl[i];
7941 disable_irq(irq->vector);
7942 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7943 enable_irq(irq->vector);
7949 bnx2_get_5709_media(struct bnx2 *bp)
7951 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7952 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7955 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7957 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7958 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7962 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7963 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7965 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7967 if (bp->func == 0) {
7972 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7980 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7987 bnx2_get_pci_speed(struct bnx2 *bp)
7991 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
7992 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7995 bp->flags |= BNX2_FLAG_PCIX;
7997 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7999 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
8001 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
8002 bp->bus_speed_mhz = 133;
8005 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
8006 bp->bus_speed_mhz = 100;
8009 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
8010 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
8011 bp->bus_speed_mhz = 66;
8014 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
8015 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
8016 bp->bus_speed_mhz = 50;
8019 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
8020 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
8021 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
8022 bp->bus_speed_mhz = 33;
8027 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
8028 bp->bus_speed_mhz = 66;
8030 bp->bus_speed_mhz = 33;
8033 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
8034 bp->flags |= BNX2_FLAG_PCI_32BIT;
8039 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
8045 #define BNX2_VPD_NVRAM_OFFSET 0x300
8046 #define BNX2_VPD_LEN 128
8047 #define BNX2_MAX_VER_SLEN 30
8049 data = kmalloc(BNX2_VPD_LEN, GFP_KERNEL);
8053 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data, BNX2_VPD_LEN);
8057 for (i = 0; i < BNX2_VPD_LEN; i += 4)
8058 swab32s((u32 *)&data[i]);
8060 j = pci_vpd_find_ro_info_keyword(data, BNX2_VPD_LEN,
8061 PCI_VPD_RO_KEYWORD_MFR_ID, &len);
8065 if (len != 4 || memcmp(&data[j], "1028", 4))
8068 j = pci_vpd_find_ro_info_keyword(data, BNX2_VPD_LEN,
8069 PCI_VPD_RO_KEYWORD_VENDOR0,
8074 if (len > BNX2_MAX_VER_SLEN)
8077 memcpy(bp->fw_version, &data[j], len);
8078 bp->fw_version[len] = ' ';
8085 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
8090 u64 dma_mask, persist_dma_mask;
8093 SET_NETDEV_DEV(dev, &pdev->dev);
8094 bp = netdev_priv(dev);
8099 bp->temp_stats_blk =
8100 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
8102 if (!bp->temp_stats_blk) {
8107 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8108 rc = pci_enable_device(pdev);
8110 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
8114 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8116 "Cannot find PCI device base address, aborting\n");
8118 goto err_out_disable;
8121 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8123 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
8124 goto err_out_disable;
8127 pci_set_master(pdev);
8129 bp->pm_cap = pdev->pm_cap;
8130 if (bp->pm_cap == 0) {
8132 "Cannot find power management capability, aborting\n");
8134 goto err_out_release;
8140 spin_lock_init(&bp->phy_lock);
8141 spin_lock_init(&bp->indirect_lock);
8143 mutex_init(&bp->cnic_lock);
8145 INIT_WORK(&bp->reset_task, bnx2_reset_task);
8147 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
8148 TX_MAX_TSS_RINGS + 1));
8150 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
8152 goto err_out_release;
8155 /* Configure byte swap and enable write to the reg_window registers.
8156 * Rely on CPU to do target byte swapping on big endian systems
8157 * The chip's target access swapping will not swap all accesses
8159 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8160 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
8161 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
8163 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
8165 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
8166 if (!pci_is_pcie(pdev)) {
8167 dev_err(&pdev->dev, "Not PCIE, aborting\n");
8171 bp->flags |= BNX2_FLAG_PCIE;
8172 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
8173 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
8175 /* AER (Advanced Error Reporting) hooks */
8176 err = pci_enable_pcie_error_reporting(pdev);
8178 bp->flags |= BNX2_FLAG_AER_ENABLED;
8181 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8182 if (bp->pcix_cap == 0) {
8184 "Cannot find PCIX capability, aborting\n");
8188 bp->flags |= BNX2_FLAG_BROKEN_STATS;
8191 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8192 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {
8194 bp->flags |= BNX2_FLAG_MSIX_CAP;
8197 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&
8198 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {
8200 bp->flags |= BNX2_FLAG_MSI_CAP;
8203 /* 5708 cannot support DMA addresses > 40-bit. */
8204 if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
8205 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
8207 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
8209 /* Configure DMA attributes. */
8210 if (dma_set_mask(&pdev->dev, dma_mask) == 0) {
8211 dev->features |= NETIF_F_HIGHDMA;
8212 rc = dma_set_coherent_mask(&pdev->dev, persist_dma_mask);
8215 "dma_set_coherent_mask failed, aborting\n");
8218 } else if ((rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) != 0) {
8219 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8223 if (!(bp->flags & BNX2_FLAG_PCIE))
8224 bnx2_get_pci_speed(bp);
8226 /* 5706A0 may falsely detect SERR and PERR. */
8227 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
8228 reg = BNX2_RD(bp, PCI_COMMAND);
8229 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8230 BNX2_WR(bp, PCI_COMMAND, reg);
8231 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&
8232 !(bp->flags & BNX2_FLAG_PCIX)) {
8234 "5706 A1 can only be used in a PCIX bus, aborting\n");
8239 bnx2_init_nvram(bp);
8241 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8243 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
8246 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8247 BNX2_SHM_HDR_SIGNATURE_SIG) {
8248 u32 off = bp->func << 2;
8250 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8252 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8254 /* Get the permanent MAC address. First we need to make sure the
8255 * firmware is actually running.
8257 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8259 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8260 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8261 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8266 bnx2_read_vpd_fw_ver(bp);
8268 j = strlen(bp->fw_version);
8269 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8270 for (i = 0; i < 3 && j < 24; i++) {
8274 bp->fw_version[j++] = 'b';
8275 bp->fw_version[j++] = 'c';
8276 bp->fw_version[j++] = ' ';
8278 num = (u8) (reg >> (24 - (i * 8)));
8279 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8280 if (num >= k || !skip0 || k == 1) {
8281 bp->fw_version[j++] = (num / k) + '0';
8286 bp->fw_version[j++] = '.';
8288 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8289 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8292 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8293 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8295 for (i = 0; i < 30; i++) {
8296 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8297 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8302 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8303 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8304 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8305 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8306 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8309 bp->fw_version[j++] = ' ';
8310 for (i = 0; i < 3 && j < 28; i++) {
8311 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8312 reg = be32_to_cpu(reg);
8313 memcpy(&bp->fw_version[j], ®, 4);
8318 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8319 bp->mac_addr[0] = (u8) (reg >> 8);
8320 bp->mac_addr[1] = (u8) reg;
8322 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8323 bp->mac_addr[2] = (u8) (reg >> 24);
8324 bp->mac_addr[3] = (u8) (reg >> 16);
8325 bp->mac_addr[4] = (u8) (reg >> 8);
8326 bp->mac_addr[5] = (u8) reg;
8328 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;
8329 bnx2_set_rx_ring_size(bp, 255);
8331 bp->tx_quick_cons_trip_int = 2;
8332 bp->tx_quick_cons_trip = 20;
8333 bp->tx_ticks_int = 18;
8336 bp->rx_quick_cons_trip_int = 2;
8337 bp->rx_quick_cons_trip = 12;
8338 bp->rx_ticks_int = 18;
8341 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8343 bp->current_interval = BNX2_TIMER_INTERVAL;
8347 /* allocate stats_blk */
8348 rc = bnx2_alloc_stats_blk(dev);
8352 /* Disable WOL support if we are running on a SERDES chip. */
8353 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8354 bnx2_get_5709_media(bp);
8355 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)
8356 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8358 bp->phy_port = PORT_TP;
8359 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8360 bp->phy_port = PORT_FIBRE;
8361 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8362 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8363 bp->flags |= BNX2_FLAG_NO_WOL;
8366 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {
8367 /* Don't do parallel detect on this board because of
8368 * some board problems. The link will not go down
8369 * if we do parallel detect.
8371 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8372 pdev->subsystem_device == 0x310c)
8373 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8376 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8377 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8379 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||
8380 BNX2_CHIP(bp) == BNX2_CHIP_5708)
8381 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8382 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8383 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||
8384 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))
8385 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8387 bnx2_init_fw_cap(bp);
8389 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
8390 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
8391 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||
8392 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8393 bp->flags |= BNX2_FLAG_NO_WOL;
8397 if (bp->flags & BNX2_FLAG_NO_WOL)
8398 device_set_wakeup_capable(&bp->pdev->dev, false);
8400 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
8402 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
8403 bp->tx_quick_cons_trip_int =
8404 bp->tx_quick_cons_trip;
8405 bp->tx_ticks_int = bp->tx_ticks;
8406 bp->rx_quick_cons_trip_int =
8407 bp->rx_quick_cons_trip;
8408 bp->rx_ticks_int = bp->rx_ticks;
8409 bp->comp_prod_trip_int = bp->comp_prod_trip;
8410 bp->com_ticks_int = bp->com_ticks;
8411 bp->cmd_ticks_int = bp->cmd_ticks;
8414 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8416 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8417 * with byte enables disabled on the unused 32-bit word. This is legal
8418 * but causes problems on the AMD 8132 which will eventually stop
8419 * responding after a while.
8421 * AMD believes this incompatibility is unique to the 5706, and
8422 * prefers to locally disable MSI rather than globally disabling it.
8424 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {
8425 struct pci_dev *amd_8132 = NULL;
8427 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8428 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8431 if (amd_8132->revision >= 0x10 &&
8432 amd_8132->revision <= 0x13) {
8434 pci_dev_put(amd_8132);
8440 bnx2_set_default_link(bp);
8441 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8443 timer_setup(&bp->timer, bnx2_timer, 0);
8444 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8447 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8448 bp->cnic_eth_dev.max_iscsi_conn =
8449 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8450 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
8451 bp->cnic_probe = bnx2_cnic_probe;
8453 pci_save_state(pdev);
8458 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
8459 pci_disable_pcie_error_reporting(pdev);
8460 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8463 pci_iounmap(pdev, bp->regview);
8467 pci_release_regions(pdev);
8470 pci_disable_device(pdev);
8473 kfree(bp->temp_stats_blk);
8479 bnx2_bus_string(struct bnx2 *bp, char *str)
8483 if (bp->flags & BNX2_FLAG_PCIE) {
8484 s += sprintf(s, "PCI Express");
8486 s += sprintf(s, "PCI");
8487 if (bp->flags & BNX2_FLAG_PCIX)
8488 s += sprintf(s, "-X");
8489 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8490 s += sprintf(s, " 32-bit");
8492 s += sprintf(s, " 64-bit");
8493 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8499 bnx2_del_napi(struct bnx2 *bp)
8503 for (i = 0; i < bp->irq_nvecs; i++)
8504 netif_napi_del(&bp->bnx2_napi[i].napi);
8508 bnx2_init_napi(struct bnx2 *bp)
8512 for (i = 0; i < bp->irq_nvecs; i++) {
8513 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8514 int (*poll)(struct napi_struct *, int);
8519 poll = bnx2_poll_msix;
8521 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8526 static const struct net_device_ops bnx2_netdev_ops = {
8527 .ndo_open = bnx2_open,
8528 .ndo_start_xmit = bnx2_start_xmit,
8529 .ndo_stop = bnx2_close,
8530 .ndo_get_stats64 = bnx2_get_stats64,
8531 .ndo_set_rx_mode = bnx2_set_rx_mode,
8532 .ndo_eth_ioctl = bnx2_ioctl,
8533 .ndo_validate_addr = eth_validate_addr,
8534 .ndo_set_mac_address = bnx2_change_mac_addr,
8535 .ndo_change_mtu = bnx2_change_mtu,
8536 .ndo_set_features = bnx2_set_features,
8537 .ndo_tx_timeout = bnx2_tx_timeout,
8538 #ifdef CONFIG_NET_POLL_CONTROLLER
8539 .ndo_poll_controller = poll_bnx2,
8544 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8546 struct net_device *dev;
8551 /* dev zeroed in init_etherdev */
8552 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8556 rc = bnx2_init_board(pdev, dev);
8560 dev->netdev_ops = &bnx2_netdev_ops;
8561 dev->watchdog_timeo = TX_TIMEOUT;
8562 dev->ethtool_ops = &bnx2_ethtool_ops;
8564 bp = netdev_priv(dev);
8566 pci_set_drvdata(pdev, dev);
8569 * In-flight DMA from 1st kernel could continue going in kdump kernel.
8570 * New io-page table has been created before bnx2 does reset at open stage.
8571 * We have to wait for the in-flight DMA to complete to avoid it look up
8572 * into the newly created io-page table.
8574 if (is_kdump_kernel())
8575 bnx2_wait_dma_complete(bp);
8577 eth_hw_addr_set(dev, bp->mac_addr);
8579 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8580 NETIF_F_TSO | NETIF_F_TSO_ECN |
8581 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8583 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8584 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8586 dev->vlan_features = dev->hw_features;
8587 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8588 dev->features |= dev->hw_features;
8589 dev->priv_flags |= IFF_UNICAST_FLT;
8590 dev->min_mtu = MIN_ETHERNET_PACKET_SIZE;
8591 dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE;
8593 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
8594 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8596 if ((rc = register_netdev(dev))) {
8597 dev_err(&pdev->dev, "Cannot register net device\n");
8601 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, "
8602 "node addr %pM\n", board_info[ent->driver_data].name,
8603 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8604 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),
8605 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
8606 pdev->irq, dev->dev_addr);
8611 pci_iounmap(pdev, bp->regview);
8612 pci_release_regions(pdev);
8613 pci_disable_device(pdev);
8615 bnx2_free_stats_blk(dev);
8621 bnx2_remove_one(struct pci_dev *pdev)
8623 struct net_device *dev = pci_get_drvdata(pdev);
8624 struct bnx2 *bp = netdev_priv(dev);
8626 unregister_netdev(dev);
8628 del_timer_sync(&bp->timer);
8629 cancel_work_sync(&bp->reset_task);
8631 pci_iounmap(bp->pdev, bp->regview);
8633 bnx2_free_stats_blk(dev);
8634 kfree(bp->temp_stats_blk);
8636 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
8637 pci_disable_pcie_error_reporting(pdev);
8638 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8641 bnx2_release_firmware(bp);
8645 pci_release_regions(pdev);
8646 pci_disable_device(pdev);
8649 #ifdef CONFIG_PM_SLEEP
8651 bnx2_suspend(struct device *device)
8653 struct net_device *dev = dev_get_drvdata(device);
8654 struct bnx2 *bp = netdev_priv(dev);
8656 if (netif_running(dev)) {
8657 cancel_work_sync(&bp->reset_task);
8658 bnx2_netif_stop(bp, true);
8659 netif_device_detach(dev);
8660 del_timer_sync(&bp->timer);
8661 bnx2_shutdown_chip(bp);
8662 __bnx2_free_irq(bp);
8670 bnx2_resume(struct device *device)
8672 struct net_device *dev = dev_get_drvdata(device);
8673 struct bnx2 *bp = netdev_priv(dev);
8675 if (!netif_running(dev))
8678 bnx2_set_power_state(bp, PCI_D0);
8679 netif_device_attach(dev);
8680 bnx2_request_irq(bp);
8681 bnx2_init_nic(bp, 1);
8682 bnx2_netif_start(bp, true);
8686 static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume);
8687 #define BNX2_PM_OPS (&bnx2_pm_ops)
8691 #define BNX2_PM_OPS NULL
8693 #endif /* CONFIG_PM_SLEEP */
8695 * bnx2_io_error_detected - called when PCI error is detected
8696 * @pdev: Pointer to PCI device
8697 * @state: The current pci connection state
8699 * This function is called after a PCI bus error affecting
8700 * this device has been detected.
8702 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8703 pci_channel_state_t state)
8705 struct net_device *dev = pci_get_drvdata(pdev);
8706 struct bnx2 *bp = netdev_priv(dev);
8709 netif_device_detach(dev);
8711 if (state == pci_channel_io_perm_failure) {
8713 return PCI_ERS_RESULT_DISCONNECT;
8716 if (netif_running(dev)) {
8717 bnx2_netif_stop(bp, true);
8718 del_timer_sync(&bp->timer);
8719 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8722 pci_disable_device(pdev);
8725 /* Request a slot slot reset. */
8726 return PCI_ERS_RESULT_NEED_RESET;
8730 * bnx2_io_slot_reset - called after the pci bus has been reset.
8731 * @pdev: Pointer to PCI device
8733 * Restart the card from scratch, as if from a cold-boot.
8735 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8737 struct net_device *dev = pci_get_drvdata(pdev);
8738 struct bnx2 *bp = netdev_priv(dev);
8739 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8743 if (pci_enable_device(pdev)) {
8745 "Cannot re-enable PCI device after reset\n");
8747 pci_set_master(pdev);
8748 pci_restore_state(pdev);
8749 pci_save_state(pdev);
8751 if (netif_running(dev))
8752 err = bnx2_init_nic(bp, 1);
8755 result = PCI_ERS_RESULT_RECOVERED;
8758 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) {
8759 bnx2_napi_enable(bp);
8764 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
8771 * bnx2_io_resume - called when traffic can start flowing again.
8772 * @pdev: Pointer to PCI device
8774 * This callback is called when the error recovery driver tells us that
8775 * its OK to resume normal operation.
8777 static void bnx2_io_resume(struct pci_dev *pdev)
8779 struct net_device *dev = pci_get_drvdata(pdev);
8780 struct bnx2 *bp = netdev_priv(dev);
8783 if (netif_running(dev))
8784 bnx2_netif_start(bp, true);
8786 netif_device_attach(dev);
8790 static void bnx2_shutdown(struct pci_dev *pdev)
8792 struct net_device *dev = pci_get_drvdata(pdev);
8798 bp = netdev_priv(dev);
8803 if (netif_running(dev))
8806 if (system_state == SYSTEM_POWER_OFF)
8807 bnx2_set_power_state(bp, PCI_D3hot);
8812 static const struct pci_error_handlers bnx2_err_handler = {
8813 .error_detected = bnx2_io_error_detected,
8814 .slot_reset = bnx2_io_slot_reset,
8815 .resume = bnx2_io_resume,
8818 static struct pci_driver bnx2_pci_driver = {
8819 .name = DRV_MODULE_NAME,
8820 .id_table = bnx2_pci_tbl,
8821 .probe = bnx2_init_one,
8822 .remove = bnx2_remove_one,
8823 .driver.pm = BNX2_PM_OPS,
8824 .err_handler = &bnx2_err_handler,
8825 .shutdown = bnx2_shutdown,
8828 module_pci_driver(bnx2_pci_driver);