2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/bcma/bcma.h>
13 #include <linux/etherdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/bcm47xx_nvram.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
20 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
21 u32 value, int timeout)
26 for (i = 0; i < timeout / 10; i++) {
27 val = bgmac_read(bgmac, reg);
28 if ((val & mask) == value)
32 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
36 /**************************************************
38 **************************************************/
40 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
48 /* Suspend DMA TX ring first.
49 * bgmac_wait_value doesn't support waiting for any of few values, so
50 * implement whole loop here.
52 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
53 BGMAC_DMA_TX_SUSPEND);
54 for (i = 0; i < 10000 / 10; i++) {
55 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
56 val &= BGMAC_DMA_TX_STAT;
57 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
58 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
59 val == BGMAC_DMA_TX_STAT_STOPPED) {
66 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
67 ring->mmio_base, val);
69 /* Remove SUSPEND bit */
70 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
71 if (!bgmac_wait_value(bgmac,
72 ring->mmio_base + BGMAC_DMA_TX_STATUS,
73 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
75 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
78 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
79 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
80 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
85 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
86 struct bgmac_dma_ring *ring)
90 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
91 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
92 ctl &= ~BGMAC_DMA_TX_BL_MASK;
93 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
95 ctl &= ~BGMAC_DMA_TX_MR_MASK;
96 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
98 ctl &= ~BGMAC_DMA_TX_PC_MASK;
99 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
101 ctl &= ~BGMAC_DMA_TX_PT_MASK;
102 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
104 ctl |= BGMAC_DMA_TX_ENABLE;
105 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
106 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
110 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
111 int i, int len, u32 ctl0)
113 struct bgmac_slot_info *slot;
114 struct bgmac_dma_desc *dma_desc;
117 if (i == BGMAC_TX_RING_SLOTS - 1)
118 ctl0 |= BGMAC_DESC_CTL0_EOT;
120 ctl1 = len & BGMAC_DESC_CTL1_LEN;
122 slot = &ring->slots[i];
123 dma_desc = &ring->cpu_base[i];
124 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
125 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
126 dma_desc->ctl0 = cpu_to_le32(ctl0);
127 dma_desc->ctl1 = cpu_to_le32(ctl1);
130 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
131 struct bgmac_dma_ring *ring,
134 struct device *dma_dev = bgmac->dma_dev;
135 struct net_device *net_dev = bgmac->net_dev;
136 int index = ring->end % BGMAC_TX_RING_SLOTS;
137 struct bgmac_slot_info *slot = &ring->slots[index];
142 if (skb->len > BGMAC_DESC_CTL1_LEN) {
143 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
147 if (skb->ip_summed == CHECKSUM_PARTIAL)
148 skb_checksum_help(skb);
150 nr_frags = skb_shinfo(skb)->nr_frags;
152 /* ring->end - ring->start will return the number of valid slots,
153 * even when ring->end overflows
155 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
156 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
157 netif_stop_queue(net_dev);
158 return NETDEV_TX_BUSY;
161 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
163 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
166 flags = BGMAC_DESC_CTL0_SOF;
168 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
170 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
173 for (i = 0; i < nr_frags; i++) {
174 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
175 int len = skb_frag_size(frag);
177 index = (index + 1) % BGMAC_TX_RING_SLOTS;
178 slot = &ring->slots[index];
179 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
181 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
184 if (i == nr_frags - 1)
185 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
187 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
191 ring->end += nr_frags + 1;
192 netdev_sent_queue(net_dev, skb->len);
196 /* Increase ring->end to point empty slot. We tell hardware the first
197 * slot it should *not* read.
199 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
201 (ring->end % BGMAC_TX_RING_SLOTS) *
202 sizeof(struct bgmac_dma_desc));
204 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
205 netif_stop_queue(net_dev);
210 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
214 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
215 struct bgmac_slot_info *slot = &ring->slots[index];
216 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
217 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
219 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
223 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
228 net_dev->stats.tx_dropped++;
229 net_dev->stats.tx_errors++;
233 /* Free transmitted packets */
234 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
236 struct device *dma_dev = bgmac->dma_dev;
239 unsigned bytes_compl = 0, pkts_compl = 0;
241 /* The last slot that hardware didn't consume yet */
242 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
243 empty_slot &= BGMAC_DMA_TX_STATDPTR;
244 empty_slot -= ring->index_base;
245 empty_slot &= BGMAC_DMA_TX_STATDPTR;
246 empty_slot /= sizeof(struct bgmac_dma_desc);
248 while (ring->start != ring->end) {
249 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
250 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
254 if (slot_idx == empty_slot)
257 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
258 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
259 len = ctl1 & BGMAC_DESC_CTL1_LEN;
260 if (ctl0 & BGMAC_DESC_CTL0_SOF)
261 /* Unmap no longer used buffer */
262 dma_unmap_single(dma_dev, slot->dma_addr, len,
265 dma_unmap_page(dma_dev, slot->dma_addr, len,
269 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
270 bgmac->net_dev->stats.tx_packets++;
271 bytes_compl += slot->skb->len;
274 /* Free memory! :) */
275 dev_kfree_skb(slot->skb);
287 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
289 if (netif_queue_stopped(bgmac->net_dev))
290 netif_wake_queue(bgmac->net_dev);
293 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
295 if (!ring->mmio_base)
298 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
299 if (!bgmac_wait_value(bgmac,
300 ring->mmio_base + BGMAC_DMA_RX_STATUS,
301 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
303 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
307 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
308 struct bgmac_dma_ring *ring)
312 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
314 /* preserve ONLY bits 16-17 from current hardware value */
315 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
317 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
318 ctl &= ~BGMAC_DMA_RX_BL_MASK;
319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
321 ctl &= ~BGMAC_DMA_RX_PC_MASK;
322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
324 ctl &= ~BGMAC_DMA_RX_PT_MASK;
325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
327 ctl |= BGMAC_DMA_RX_ENABLE;
328 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
329 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
330 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
331 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
334 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
335 struct bgmac_slot_info *slot)
337 struct device *dma_dev = bgmac->dma_dev;
339 struct bgmac_rx_header *rx;
343 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
347 /* Poison - if everything goes fine, hardware will overwrite it */
348 rx = buf + BGMAC_RX_BUF_OFFSET;
349 rx->len = cpu_to_le16(0xdead);
350 rx->flags = cpu_to_le16(0xbeef);
352 /* Map skb for the DMA */
353 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
354 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
355 if (dma_mapping_error(dma_dev, dma_addr)) {
356 netdev_err(bgmac->net_dev, "DMA mapping error\n");
357 put_page(virt_to_head_page(buf));
361 /* Update the slot */
363 slot->dma_addr = dma_addr;
368 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
369 struct bgmac_dma_ring *ring)
373 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
375 ring->end * sizeof(struct bgmac_dma_desc));
378 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
379 struct bgmac_dma_ring *ring, int desc_idx)
381 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
382 u32 ctl0 = 0, ctl1 = 0;
384 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
385 ctl0 |= BGMAC_DESC_CTL0_EOT;
386 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
387 /* Is there any BGMAC device that requires extension? */
388 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
389 * B43_DMA64_DCTL1_ADDREXT_MASK;
392 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
393 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
394 dma_desc->ctl0 = cpu_to_le32(ctl0);
395 dma_desc->ctl1 = cpu_to_le32(ctl1);
397 ring->end = desc_idx;
400 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
401 struct bgmac_slot_info *slot)
403 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
405 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
407 rx->len = cpu_to_le16(0xdead);
408 rx->flags = cpu_to_le16(0xbeef);
409 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
413 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
419 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
420 end_slot &= BGMAC_DMA_RX_STATDPTR;
421 end_slot -= ring->index_base;
422 end_slot &= BGMAC_DMA_RX_STATDPTR;
423 end_slot /= sizeof(struct bgmac_dma_desc);
425 while (ring->start != end_slot) {
426 struct device *dma_dev = bgmac->dma_dev;
427 struct bgmac_slot_info *slot = &ring->slots[ring->start];
428 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
430 void *buf = slot->buf;
431 dma_addr_t dma_addr = slot->dma_addr;
435 /* Prepare new skb as replacement */
436 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
437 bgmac_dma_rx_poison_buf(dma_dev, slot);
441 /* Unmap buffer to make it accessible to the CPU */
442 dma_unmap_single(dma_dev, dma_addr,
443 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
445 /* Get info from the header */
446 len = le16_to_cpu(rx->len);
447 flags = le16_to_cpu(rx->flags);
449 /* Check for poison and drop or pass the packet */
450 if (len == 0xdead && flags == 0xbeef) {
451 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
453 put_page(virt_to_head_page(buf));
454 bgmac->net_dev->stats.rx_errors++;
458 if (len > BGMAC_RX_ALLOC_SIZE) {
459 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
461 put_page(virt_to_head_page(buf));
462 bgmac->net_dev->stats.rx_length_errors++;
463 bgmac->net_dev->stats.rx_errors++;
470 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
471 if (unlikely(!skb)) {
472 netdev_err(bgmac->net_dev, "build_skb failed\n");
473 put_page(virt_to_head_page(buf));
474 bgmac->net_dev->stats.rx_errors++;
477 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
478 BGMAC_RX_BUF_OFFSET + len);
479 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
480 BGMAC_RX_BUF_OFFSET);
482 skb_checksum_none_assert(skb);
483 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
484 bgmac->net_dev->stats.rx_bytes += len;
485 bgmac->net_dev->stats.rx_packets++;
486 napi_gro_receive(&bgmac->napi, skb);
490 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
492 if (++ring->start >= BGMAC_RX_RING_SLOTS)
495 if (handled >= weight) /* Should never be greater */
499 bgmac_dma_rx_update_index(bgmac, ring);
504 /* Does ring support unaligned addressing? */
505 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
506 struct bgmac_dma_ring *ring,
507 enum bgmac_dma_ring_type ring_type)
510 case BGMAC_DMA_RING_TX:
511 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
513 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
516 case BGMAC_DMA_RING_RX:
517 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
519 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
526 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
527 struct bgmac_dma_ring *ring)
529 struct device *dma_dev = bgmac->dma_dev;
530 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
531 struct bgmac_slot_info *slot;
534 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
535 u32 ctl1 = le32_to_cpu(dma_desc[i].ctl1);
536 unsigned int len = ctl1 & BGMAC_DESC_CTL1_LEN;
538 slot = &ring->slots[i];
539 dev_kfree_skb(slot->skb);
545 dma_unmap_single(dma_dev, slot->dma_addr,
548 dma_unmap_page(dma_dev, slot->dma_addr,
553 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
554 struct bgmac_dma_ring *ring)
556 struct device *dma_dev = bgmac->dma_dev;
557 struct bgmac_slot_info *slot;
560 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
561 slot = &ring->slots[i];
565 dma_unmap_single(dma_dev, slot->dma_addr,
568 put_page(virt_to_head_page(slot->buf));
573 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
574 struct bgmac_dma_ring *ring,
577 struct device *dma_dev = bgmac->dma_dev;
583 /* Free ring of descriptors */
584 size = num_slots * sizeof(struct bgmac_dma_desc);
585 dma_free_coherent(dma_dev, size, ring->cpu_base,
589 static void bgmac_dma_cleanup(struct bgmac *bgmac)
593 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
594 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
596 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
597 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
600 static void bgmac_dma_free(struct bgmac *bgmac)
604 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
605 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
606 BGMAC_TX_RING_SLOTS);
608 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
609 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
610 BGMAC_RX_RING_SLOTS);
613 static int bgmac_dma_alloc(struct bgmac *bgmac)
615 struct device *dma_dev = bgmac->dma_dev;
616 struct bgmac_dma_ring *ring;
617 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
618 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
619 int size; /* ring size: different for Tx and Rx */
623 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
624 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
626 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
627 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
628 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
633 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
634 ring = &bgmac->tx_ring[i];
635 ring->mmio_base = ring_base[i];
637 /* Alloc ring of descriptors */
638 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
639 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
642 if (!ring->cpu_base) {
643 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
648 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
651 ring->index_base = lower_32_bits(ring->dma_base);
653 ring->index_base = 0;
655 /* No need to alloc TX slots yet */
658 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
659 ring = &bgmac->rx_ring[i];
660 ring->mmio_base = ring_base[i];
662 /* Alloc ring of descriptors */
663 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
664 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
667 if (!ring->cpu_base) {
668 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
674 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
677 ring->index_base = lower_32_bits(ring->dma_base);
679 ring->index_base = 0;
685 bgmac_dma_free(bgmac);
689 static int bgmac_dma_init(struct bgmac *bgmac)
691 struct bgmac_dma_ring *ring;
694 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
695 ring = &bgmac->tx_ring[i];
697 if (!ring->unaligned)
698 bgmac_dma_tx_enable(bgmac, ring);
699 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
700 lower_32_bits(ring->dma_base));
701 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
702 upper_32_bits(ring->dma_base));
704 bgmac_dma_tx_enable(bgmac, ring);
707 ring->end = 0; /* Points the slot that should *not* be read */
710 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
713 ring = &bgmac->rx_ring[i];
715 if (!ring->unaligned)
716 bgmac_dma_rx_enable(bgmac, ring);
717 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
718 lower_32_bits(ring->dma_base));
719 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
720 upper_32_bits(ring->dma_base));
722 bgmac_dma_rx_enable(bgmac, ring);
726 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
727 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
731 bgmac_dma_rx_setup_desc(bgmac, ring, j);
734 bgmac_dma_rx_update_index(bgmac, ring);
740 bgmac_dma_cleanup(bgmac);
745 /**************************************************
747 **************************************************/
749 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
750 * nothing to change? Try if after stabilizng driver.
752 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
755 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
756 u32 new_val = (cmdcfg & mask) | set;
759 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
760 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
762 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
764 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
767 if (new_val != cmdcfg || force)
768 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
770 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
774 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
778 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
779 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
780 tmp = (addr[4] << 8) | addr[5];
781 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
784 static void bgmac_set_rx_mode(struct net_device *net_dev)
786 struct bgmac *bgmac = netdev_priv(net_dev);
788 if (net_dev->flags & IFF_PROMISC)
789 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
791 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
794 #if 0 /* We don't use that regs yet */
795 static void bgmac_chip_stats_update(struct bgmac *bgmac)
799 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
800 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
801 bgmac->mib_tx_regs[i] =
803 BGMAC_TX_GOOD_OCTETS + (i * 4));
804 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
805 bgmac->mib_rx_regs[i] =
807 BGMAC_RX_GOOD_OCTETS + (i * 4));
810 /* TODO: what else? how to handle BCM4706? Specs are needed */
814 static void bgmac_clear_mib(struct bgmac *bgmac)
818 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
821 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
822 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
823 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
824 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
825 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
828 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
829 static void bgmac_mac_speed(struct bgmac *bgmac)
831 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
834 switch (bgmac->mac_speed) {
836 set |= BGMAC_CMDCFG_ES_10;
839 set |= BGMAC_CMDCFG_ES_100;
842 set |= BGMAC_CMDCFG_ES_1000;
845 set |= BGMAC_CMDCFG_ES_2500;
848 dev_err(bgmac->dev, "Unsupported speed: %d\n",
852 if (bgmac->mac_duplex == DUPLEX_HALF)
853 set |= BGMAC_CMDCFG_HD;
855 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
858 static void bgmac_miiconfig(struct bgmac *bgmac)
860 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
861 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
862 bgmac_idm_write(bgmac, BCMA_IOCTL,
863 bgmac_idm_read(bgmac, BCMA_IOCTL) |
864 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN);
866 bgmac->mac_speed = SPEED_2500;
867 bgmac->mac_duplex = DUPLEX_FULL;
868 bgmac_mac_speed(bgmac);
872 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
873 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
874 if (imode == 0 || imode == 1) {
875 bgmac->mac_speed = SPEED_100;
876 bgmac->mac_duplex = DUPLEX_FULL;
877 bgmac_mac_speed(bgmac);
882 static void bgmac_chip_reset_idm_config(struct bgmac *bgmac)
886 iost = bgmac_idm_read(bgmac, BCMA_IOST);
887 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
888 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
890 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
891 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
894 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
895 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
896 if (!bgmac->has_robosw)
897 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
899 bgmac_clk_enable(bgmac, flags);
902 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
903 bgmac_idm_write(bgmac, BCMA_IOCTL,
904 bgmac_idm_read(bgmac, BCMA_IOCTL) &
905 ~BGMAC_BCMA_IOCTL_SW_RESET);
908 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
909 static void bgmac_chip_reset(struct bgmac *bgmac)
914 if (bgmac_clk_enabled(bgmac)) {
915 if (!bgmac->stats_grabbed) {
916 /* bgmac_chip_stats_update(bgmac); */
917 bgmac->stats_grabbed = true;
920 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
921 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
923 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
926 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
927 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
929 /* TODO: Clear software multicast filter list */
932 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK))
933 bgmac_chip_reset_idm_config(bgmac);
935 /* Request Misc PLL for corerev > 2 */
936 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
937 bgmac_set(bgmac, BCMA_CLKCTLST,
938 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
939 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
940 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
941 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
945 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
947 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
948 BGMAC_CHIPCTL_1_IF_TYPE_MII;
951 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
952 if (kstrtou8(buf, 0, &et_swtype))
953 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
958 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
959 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
960 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
961 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
962 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
963 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
965 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
966 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
968 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
969 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
970 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
974 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
975 if (kstrtou8(buf, 0, &et_swtype))
976 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
978 sw_type = (et_swtype & 0x0f) << 12;
979 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
980 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
981 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
983 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
984 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
986 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
987 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
988 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
991 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
992 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
993 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
994 * be keps until taking MAC out of the reset.
996 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
997 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
999 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1001 bgmac_cmdcfg_maskset(bgmac,
1013 BGMAC_CMDCFG_PAD_EN |
1020 bgmac->mac_speed = SPEED_UNKNOWN;
1021 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1023 bgmac_clear_mib(bgmac);
1024 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1025 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1026 BCMA_GMAC_CMN_PC_MTE);
1028 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1029 bgmac_miiconfig(bgmac);
1031 bgmac->mii_bus->reset(bgmac->mii_bus);
1033 netdev_reset_queue(bgmac->net_dev);
1036 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1038 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1041 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1043 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1044 bgmac_read(bgmac, BGMAC_INT_MASK);
1047 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1048 static void bgmac_enable(struct bgmac *bgmac)
1054 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1055 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1057 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1059 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1060 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1063 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1064 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1066 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1068 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1069 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1070 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
1071 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1072 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1074 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1075 BGMAC_FEAT_FLW_CTRL2)) {
1078 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1081 fl_ctl = 0x03cb04cb;
1083 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1084 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1087 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1092 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1093 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1094 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1095 mdp = (bp_clk * 128 / 1000) - 3;
1096 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1097 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1101 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1102 static void bgmac_chip_init(struct bgmac *bgmac)
1104 /* Clear any erroneously pending interrupts */
1105 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1107 /* 1 interrupt per received frame */
1108 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1110 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1111 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1113 bgmac_set_rx_mode(bgmac->net_dev);
1115 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1117 if (bgmac->loopback)
1118 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1120 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1122 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1124 bgmac_chip_intrs_on(bgmac);
1126 bgmac_enable(bgmac);
1129 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1131 struct bgmac *bgmac = netdev_priv(dev_id);
1133 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1134 int_status &= bgmac->int_mask;
1139 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1141 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1143 /* Disable new interrupts until handling existing ones */
1144 bgmac_chip_intrs_off(bgmac);
1146 napi_schedule(&bgmac->napi);
1151 static int bgmac_poll(struct napi_struct *napi, int weight)
1153 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1157 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1159 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1160 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1162 /* Poll again if more events arrived in the meantime */
1163 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1166 if (handled < weight) {
1167 napi_complete_done(napi, handled);
1168 bgmac_chip_intrs_on(bgmac);
1174 /**************************************************
1176 **************************************************/
1178 static int bgmac_open(struct net_device *net_dev)
1180 struct bgmac *bgmac = netdev_priv(net_dev);
1183 bgmac_chip_reset(bgmac);
1185 err = bgmac_dma_init(bgmac);
1189 /* Specs say about reclaiming rings here, but we do that in DMA init */
1190 bgmac_chip_init(bgmac);
1192 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1193 KBUILD_MODNAME, net_dev);
1195 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1196 bgmac_dma_cleanup(bgmac);
1199 napi_enable(&bgmac->napi);
1201 phy_start(net_dev->phydev);
1203 netif_start_queue(net_dev);
1208 static int bgmac_stop(struct net_device *net_dev)
1210 struct bgmac *bgmac = netdev_priv(net_dev);
1212 netif_carrier_off(net_dev);
1214 phy_stop(net_dev->phydev);
1216 napi_disable(&bgmac->napi);
1217 bgmac_chip_intrs_off(bgmac);
1218 free_irq(bgmac->irq, net_dev);
1220 bgmac_chip_reset(bgmac);
1221 bgmac_dma_cleanup(bgmac);
1226 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1227 struct net_device *net_dev)
1229 struct bgmac *bgmac = netdev_priv(net_dev);
1230 struct bgmac_dma_ring *ring;
1232 /* No QOS support yet */
1233 ring = &bgmac->tx_ring[0];
1234 return bgmac_dma_tx_add(bgmac, ring, skb);
1237 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1239 struct bgmac *bgmac = netdev_priv(net_dev);
1240 struct sockaddr *sa = addr;
1243 ret = eth_prepare_mac_addr_change(net_dev, addr);
1247 ether_addr_copy(net_dev->dev_addr, sa->sa_data);
1248 bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1250 eth_commit_mac_addr_change(net_dev, addr);
1254 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1256 if (!netif_running(net_dev))
1259 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1262 static const struct net_device_ops bgmac_netdev_ops = {
1263 .ndo_open = bgmac_open,
1264 .ndo_stop = bgmac_stop,
1265 .ndo_start_xmit = bgmac_start_xmit,
1266 .ndo_set_rx_mode = bgmac_set_rx_mode,
1267 .ndo_set_mac_address = bgmac_set_mac_address,
1268 .ndo_validate_addr = eth_validate_addr,
1269 .ndo_do_ioctl = bgmac_ioctl,
1272 /**************************************************
1274 **************************************************/
1282 static struct bgmac_stat bgmac_get_strings_stats[] = {
1283 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1284 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1285 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1286 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1287 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1288 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1289 { 4, BGMAC_TX_LEN_64, "tx_64" },
1290 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1291 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1292 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1293 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1294 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1295 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1296 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1297 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1298 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1299 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1300 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1301 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1302 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1303 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1304 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1305 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1306 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1307 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1308 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1309 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1310 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1311 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1312 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1313 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1314 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1315 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1316 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1317 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1318 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1319 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1320 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1321 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1322 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1323 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1324 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1325 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1326 { 4, BGMAC_RX_LEN_64, "rx_64" },
1327 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1328 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1329 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1330 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1331 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1332 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1333 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1334 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1335 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1336 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1337 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1338 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1339 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1340 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1341 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1342 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1343 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1344 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1345 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1346 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1347 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1348 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1351 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1353 static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1355 switch (string_set) {
1357 return BGMAC_STATS_LEN;
1363 static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1368 if (stringset != ETH_SS_STATS)
1371 for (i = 0; i < BGMAC_STATS_LEN; i++)
1372 strlcpy(data + i * ETH_GSTRING_LEN,
1373 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1376 static void bgmac_get_ethtool_stats(struct net_device *dev,
1377 struct ethtool_stats *ss, uint64_t *data)
1379 struct bgmac *bgmac = netdev_priv(dev);
1380 const struct bgmac_stat *s;
1384 if (!netif_running(dev))
1387 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1388 s = &bgmac_get_strings_stats[i];
1391 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1392 val |= bgmac_read(bgmac, s->offset);
1397 static void bgmac_get_drvinfo(struct net_device *net_dev,
1398 struct ethtool_drvinfo *info)
1400 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1401 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1404 static const struct ethtool_ops bgmac_ethtool_ops = {
1405 .get_strings = bgmac_get_strings,
1406 .get_sset_count = bgmac_get_sset_count,
1407 .get_ethtool_stats = bgmac_get_ethtool_stats,
1408 .get_drvinfo = bgmac_get_drvinfo,
1409 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1410 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1413 /**************************************************
1415 **************************************************/
1417 void bgmac_adjust_link(struct net_device *net_dev)
1419 struct bgmac *bgmac = netdev_priv(net_dev);
1420 struct phy_device *phy_dev = net_dev->phydev;
1421 bool update = false;
1423 if (phy_dev->link) {
1424 if (phy_dev->speed != bgmac->mac_speed) {
1425 bgmac->mac_speed = phy_dev->speed;
1429 if (phy_dev->duplex != bgmac->mac_duplex) {
1430 bgmac->mac_duplex = phy_dev->duplex;
1436 bgmac_mac_speed(bgmac);
1437 phy_print_status(phy_dev);
1440 EXPORT_SYMBOL_GPL(bgmac_adjust_link);
1442 int bgmac_phy_connect_direct(struct bgmac *bgmac)
1444 struct fixed_phy_status fphy_status = {
1446 .speed = SPEED_1000,
1447 .duplex = DUPLEX_FULL,
1449 struct phy_device *phy_dev;
1452 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1453 if (!phy_dev || IS_ERR(phy_dev)) {
1454 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1458 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1459 PHY_INTERFACE_MODE_MII);
1461 dev_err(bgmac->dev, "Connecting PHY failed\n");
1467 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
1469 struct bgmac *bgmac_alloc(struct device *dev)
1471 struct net_device *net_dev;
1472 struct bgmac *bgmac;
1474 /* Allocation and references */
1475 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
1479 net_dev->netdev_ops = &bgmac_netdev_ops;
1480 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1482 bgmac = netdev_priv(net_dev);
1484 bgmac->net_dev = net_dev;
1488 EXPORT_SYMBOL_GPL(bgmac_alloc);
1490 int bgmac_enet_probe(struct bgmac *bgmac)
1492 struct net_device *net_dev = bgmac->net_dev;
1495 net_dev->irq = bgmac->irq;
1496 SET_NETDEV_DEV(net_dev, bgmac->dev);
1497 dev_set_drvdata(bgmac->dev, bgmac);
1499 if (!is_valid_ether_addr(net_dev->dev_addr)) {
1500 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1502 eth_hw_addr_random(net_dev);
1503 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1507 /* This (reset &) enable is not preset in specs or reference driver but
1508 * Broadcom does it in arch PCI code when enabling fake PCI device.
1510 bgmac_clk_enable(bgmac, 0);
1512 /* This seems to be fixing IRQ by assigning OOB #6 to the core */
1513 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
1514 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1515 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1518 bgmac_chip_reset(bgmac);
1520 err = bgmac_dma_alloc(bgmac);
1522 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1526 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1527 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1528 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1530 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1532 err = bgmac_phy_connect(bgmac);
1534 dev_err(bgmac->dev, "Cannot connect to phy\n");
1538 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1539 net_dev->hw_features = net_dev->features;
1540 net_dev->vlan_features = net_dev->features;
1542 err = register_netdev(bgmac->net_dev);
1544 dev_err(bgmac->dev, "Cannot register net device\n");
1545 goto err_phy_disconnect;
1548 netif_carrier_off(net_dev);
1553 phy_disconnect(net_dev->phydev);
1555 bgmac_dma_free(bgmac);
1560 EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1562 void bgmac_enet_remove(struct bgmac *bgmac)
1564 unregister_netdev(bgmac->net_dev);
1565 phy_disconnect(bgmac->net_dev->phydev);
1566 netif_napi_del(&bgmac->napi);
1567 bgmac_dma_free(bgmac);
1568 free_netdev(bgmac->net_dev);
1570 EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1572 int bgmac_enet_suspend(struct bgmac *bgmac)
1574 if (!netif_running(bgmac->net_dev))
1577 phy_stop(bgmac->net_dev->phydev);
1579 netif_stop_queue(bgmac->net_dev);
1581 napi_disable(&bgmac->napi);
1583 netif_tx_lock(bgmac->net_dev);
1584 netif_device_detach(bgmac->net_dev);
1585 netif_tx_unlock(bgmac->net_dev);
1587 bgmac_chip_intrs_off(bgmac);
1588 bgmac_chip_reset(bgmac);
1589 bgmac_dma_cleanup(bgmac);
1593 EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
1595 int bgmac_enet_resume(struct bgmac *bgmac)
1599 if (!netif_running(bgmac->net_dev))
1602 rc = bgmac_dma_init(bgmac);
1606 bgmac_chip_init(bgmac);
1608 napi_enable(&bgmac->napi);
1610 netif_tx_lock(bgmac->net_dev);
1611 netif_device_attach(bgmac->net_dev);
1612 netif_tx_unlock(bgmac->net_dev);
1614 netif_start_queue(bgmac->net_dev);
1616 phy_start(bgmac->net_dev->phydev);
1620 EXPORT_SYMBOL_GPL(bgmac_enet_resume);
1622 MODULE_AUTHOR("Rafał Miłecki");
1623 MODULE_LICENSE("GPL");