2 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 * Copyright (C) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifndef __BCM_SYSPORT_H
12 #define __BCM_SYSPORT_H
14 #include <linux/ethtool.h>
15 #include <linux/if_vlan.h>
17 /* Receive/transmit descriptor format */
18 #define DESC_ADDR_HI_STATUS_LEN 0x00
19 #define DESC_ADDR_HI_SHIFT 0
20 #define DESC_ADDR_HI_MASK 0xff
21 #define DESC_STATUS_SHIFT 8
22 #define DESC_STATUS_MASK 0x3ff
23 #define DESC_LEN_SHIFT 18
24 #define DESC_LEN_MASK 0x7fff
25 #define DESC_ADDR_LO 0x04
27 /* HW supports 40-bit addressing hence the */
28 #define DESC_SIZE (WORDS_PER_DESC * sizeof(u32))
30 /* Default RX buffer allocation size */
31 #define RX_BUF_LENGTH 2048
33 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526.
34 * 1536 is multiple of 256 bytes
36 #define ENET_BRCM_TAG_LEN 4
38 #define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
39 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
41 /* Transmit status block */
44 #define PCP_DEI_MASK 0xf
46 #define VID_MASK 0xfff
48 #define L4_CSUM_PTR_MASK 0x1ff
49 #define L4_PTR_SHIFT 9
50 #define L4_PTR_MASK 0x1ff
51 #define L4_UDP (1 << 18)
52 #define L4_LENGTH_VALID (1 << 19)
53 #define DEST_MAP_SHIFT 20
54 #define DEST_MAP_MASK 0x1ff
57 /* Receive status block uses the same
58 * definitions as the DMA descriptor
65 /* Common Receive/Transmit status bits */
66 #define DESC_L4_CSUM (1 << 7)
67 #define DESC_SOP (1 << 8)
68 #define DESC_EOP (1 << 9)
70 /* Receive Status bits */
71 #define RX_STATUS_UCAST 0
72 #define RX_STATUS_BCAST 0x04
73 #define RX_STATUS_MCAST 0x08
74 #define RX_STATUS_L2_MCAST 0x0c
75 #define RX_STATUS_ERR (1 << 4)
76 #define RX_STATUS_OVFLOW (1 << 5)
77 #define RX_STATUS_PARSE_FAIL (1 << 6)
79 /* Transmit Status bits */
80 #define TX_STATUS_VLAN_NO_ACT 0x00
81 #define TX_STATUS_VLAN_PCP_TSB 0x01
82 #define TX_STATUS_VLAN_QUEUE 0x02
83 #define TX_STATUS_VLAN_VID_TSB 0x03
84 #define TX_STATUS_OWR_CRC (1 << 2)
85 #define TX_STATUS_APP_CRC (1 << 3)
86 #define TX_STATUS_BRCM_TAG_NO_ACT 0
87 #define TX_STATUS_BRCM_TAG_ZERO 0x10
88 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20
89 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30
90 #define TX_STATUS_SKIP_BYTES (1 << 6)
92 /* Specific register definitions */
93 #define SYS_PORT_TOPCTRL_OFFSET 0
95 #define REV_MASK 0xffff
97 #define RX_FLUSH_CNTL 0x04
98 #define RX_FLUSH (1 << 0)
100 #define TX_FLUSH_CNTL 0x08
101 #define TX_FLUSH (1 << 0)
103 #define MISC_CNTL 0x0c
104 #define SYS_CLK_SEL (1 << 0)
105 #define TDMA_EOP_SEL (1 << 1)
107 /* Level-2 Interrupt controller offsets and defines */
108 #define SYS_PORT_INTRL2_0_OFFSET 0x200
109 #define SYS_PORT_INTRL2_1_OFFSET 0x240
110 #define INTRL2_CPU_STATUS 0x00
111 #define INTRL2_CPU_SET 0x04
112 #define INTRL2_CPU_CLEAR 0x08
113 #define INTRL2_CPU_MASK_STATUS 0x0c
114 #define INTRL2_CPU_MASK_SET 0x10
115 #define INTRL2_CPU_MASK_CLEAR 0x14
117 /* Level-2 instance 0 interrupt bits */
118 #define INTRL2_0_GISB_ERR (1 << 0)
119 #define INTRL2_0_RBUF_OVFLOW (1 << 1)
120 #define INTRL2_0_TBUF_UNDFLOW (1 << 2)
121 #define INTRL2_0_MPD (1 << 3)
122 #define INTRL2_0_BRCM_MATCH_TAG (1 << 4)
123 #define INTRL2_0_RDMA_MBDONE (1 << 5)
124 #define INTRL2_0_OVER_MAX_THRESH (1 << 6)
125 #define INTRL2_0_BELOW_HYST_THRESH (1 << 7)
126 #define INTRL2_0_FREE_LIST_EMPTY (1 << 8)
127 #define INTRL2_0_TX_RING_FULL (1 << 9)
128 #define INTRL2_0_DESC_ALLOC_ERR (1 << 10)
129 #define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11)
131 /* RXCHK offset and defines */
132 #define SYS_PORT_RXCHK_OFFSET 0x300
134 #define RXCHK_CONTROL 0x00
135 #define RXCHK_EN (1 << 0)
136 #define RXCHK_SKIP_FCS (1 << 1)
137 #define RXCHK_BAD_CSUM_DIS (1 << 2)
138 #define RXCHK_BRCM_TAG_EN (1 << 3)
139 #define RXCHK_BRCM_TAG_MATCH_SHIFT 4
140 #define RXCHK_BRCM_TAG_MATCH_MASK 0xff
141 #define RXCHK_PARSE_TNL (1 << 12)
142 #define RXCHK_VIOL_EN (1 << 13)
143 #define RXCHK_VIOL_DIS (1 << 14)
144 #define RXCHK_INCOM_PKT (1 << 15)
145 #define RXCHK_V6_DUPEXT_EN (1 << 16)
146 #define RXCHK_V6_DUPEXT_DIS (1 << 17)
147 #define RXCHK_ETHERTYPE_DIS (1 << 18)
148 #define RXCHK_L2_HDR_DIS (1 << 19)
149 #define RXCHK_L3_HDR_DIS (1 << 20)
150 #define RXCHK_MAC_RX_ERR_DIS (1 << 21)
151 #define RXCHK_PARSE_AUTH (1 << 22)
153 #define RXCHK_BRCM_TAG0 0x04
154 #define RXCHK_BRCM_TAG(i) ((i) * RXCHK_BRCM_TAG0)
155 #define RXCHK_BRCM_TAG0_MASK 0x24
156 #define RXCHK_BRCM_TAG_MASK(i) ((i) * RXCHK_BRCM_TAG0_MASK)
157 #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44
158 #define RXCHK_ETHERTYPE 0x48
159 #define RXCHK_BAD_CSUM_CNTR 0x4C
160 #define RXCHK_OTHER_DISC_CNTR 0x50
162 /* TXCHCK offsets and defines */
163 #define SYS_PORT_TXCHK_OFFSET 0x380
164 #define TXCHK_PKT_RDY_THRESH 0x00
166 /* Receive buffer offset and defines */
167 #define SYS_PORT_RBUF_OFFSET 0x400
169 #define RBUF_CONTROL 0x00
170 #define RBUF_RSB_EN (1 << 0)
171 #define RBUF_4B_ALGN (1 << 1)
172 #define RBUF_BRCM_TAG_STRIP (1 << 2)
173 #define RBUF_BAD_PKT_DISC (1 << 3)
174 #define RBUF_RESUME_THRESH_SHIFT 4
175 #define RBUF_RESUME_THRESH_MASK 0xff
176 #define RBUF_OK_TO_SEND_SHIFT 12
177 #define RBUF_OK_TO_SEND_MASK 0xff
178 #define RBUF_CRC_REPLACE (1 << 20)
179 #define RBUF_OK_TO_SEND_MODE (1 << 21)
180 #define RBUF_RSB_SWAP (1 << 22)
181 #define RBUF_ACPI_EN (1 << 23)
183 #define RBUF_PKT_RDY_THRESH 0x04
185 #define RBUF_STATUS 0x08
186 #define RBUF_WOL_MODE (1 << 0)
187 #define RBUF_MPD (1 << 1)
188 #define RBUF_ACPI (1 << 2)
190 #define RBUF_OVFL_DISC_CNTR 0x0c
191 #define RBUF_ERR_PKT_CNTR 0x10
193 /* Transmit buffer offset and defines */
194 #define SYS_PORT_TBUF_OFFSET 0x600
196 #define TBUF_CONTROL 0x00
197 #define TBUF_BP_EN (1 << 0)
198 #define TBUF_MAX_PKT_THRESH_SHIFT 1
199 #define TBUF_MAX_PKT_THRESH_MASK 0x1f
200 #define TBUF_FULL_THRESH_SHIFT 8
201 #define TBUF_FULL_THRESH_MASK 0x1f
203 /* UniMAC offset and defines */
204 #define SYS_PORT_UMAC_OFFSET 0x800
206 #define UMAC_CMD 0x008
207 #define CMD_TX_EN (1 << 0)
208 #define CMD_RX_EN (1 << 1)
209 #define CMD_SPEED_SHIFT 2
210 #define CMD_SPEED_10 0
211 #define CMD_SPEED_100 1
212 #define CMD_SPEED_1000 2
213 #define CMD_SPEED_2500 3
214 #define CMD_SPEED_MASK 3
215 #define CMD_PROMISC (1 << 4)
216 #define CMD_PAD_EN (1 << 5)
217 #define CMD_CRC_FWD (1 << 6)
218 #define CMD_PAUSE_FWD (1 << 7)
219 #define CMD_RX_PAUSE_IGNORE (1 << 8)
220 #define CMD_TX_ADDR_INS (1 << 9)
221 #define CMD_HD_EN (1 << 10)
222 #define CMD_SW_RESET (1 << 13)
223 #define CMD_LCL_LOOP_EN (1 << 15)
224 #define CMD_AUTO_CONFIG (1 << 22)
225 #define CMD_CNTL_FRM_EN (1 << 23)
226 #define CMD_NO_LEN_CHK (1 << 24)
227 #define CMD_RMT_LOOP_EN (1 << 25)
228 #define CMD_PRBL_EN (1 << 27)
229 #define CMD_TX_PAUSE_IGNORE (1 << 28)
230 #define CMD_TX_RX_EN (1 << 29)
231 #define CMD_RUNT_FILTER_DIS (1 << 30)
233 #define UMAC_MAC0 0x00c
234 #define UMAC_MAC1 0x010
235 #define UMAC_MAX_FRAME_LEN 0x014
237 #define UMAC_TX_FLUSH 0x334
239 #define UMAC_MIB_START 0x400
241 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
242 * between the end of TX stats and the beginning of the RX RUNT
244 #define UMAC_MIB_STAT_OFFSET 0xc
246 #define UMAC_MIB_CTRL 0x580
247 #define MIB_RX_CNT_RST (1 << 0)
248 #define MIB_RUNT_CNT_RST (1 << 1)
249 #define MIB_TX_CNT_RST (1 << 2)
251 #define UMAC_MPD_CTRL 0x620
252 #define MPD_EN (1 << 0)
253 #define MSEQ_LEN_SHIFT 16
254 #define MSEQ_LEN_MASK 0xff
255 #define PSW_EN (1 << 27)
257 #define UMAC_PSW_MS 0x624
258 #define UMAC_PSW_LS 0x628
259 #define UMAC_MDF_CTRL 0x650
260 #define UMAC_MDF_ADDR 0x654
262 /* Receive DMA offset and defines */
263 #define SYS_PORT_RDMA_OFFSET 0x2000
265 #define RDMA_CONTROL 0x1000
266 #define RDMA_EN (1 << 0)
267 #define RDMA_RING_CFG (1 << 1)
268 #define RDMA_DISC_EN (1 << 2)
269 #define RDMA_BUF_DATA_OFFSET_SHIFT 4
270 #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff
272 #define RDMA_STATUS 0x1004
273 #define RDMA_DISABLED (1 << 0)
274 #define RDMA_DESC_RAM_INIT_BUSY (1 << 1)
275 #define RDMA_BP_STATUS (1 << 2)
277 #define RDMA_SCB_BURST_SIZE 0x1008
279 #define RDMA_RING_BUF_SIZE 0x100c
280 #define RDMA_RING_SIZE_SHIFT 16
282 #define RDMA_WRITE_PTR_HI 0x1010
283 #define RDMA_WRITE_PTR_LO 0x1014
284 #define RDMA_PROD_INDEX 0x1018
285 #define RDMA_PROD_INDEX_MASK 0xffff
287 #define RDMA_CONS_INDEX 0x101c
288 #define RDMA_CONS_INDEX_MASK 0xffff
290 #define RDMA_START_ADDR_HI 0x1020
291 #define RDMA_START_ADDR_LO 0x1024
292 #define RDMA_END_ADDR_HI 0x1028
293 #define RDMA_END_ADDR_LO 0x102c
295 #define RDMA_MBDONE_INTR 0x1030
296 #define RDMA_INTR_THRESH_MASK 0x1ff
297 #define RDMA_TIMEOUT_SHIFT 16
298 #define RDMA_TIMEOUT_MASK 0xffff
300 #define RDMA_XON_XOFF_THRESH 0x1034
301 #define RDMA_XON_XOFF_THRESH_MASK 0xffff
302 #define RDMA_XOFF_THRESH_SHIFT 16
304 #define RDMA_READ_PTR_HI 0x1038
305 #define RDMA_READ_PTR_LO 0x103c
307 #define RDMA_OVERRIDE 0x1040
308 #define RDMA_LE_MODE (1 << 0)
309 #define RDMA_REG_MODE (1 << 1)
311 #define RDMA_TEST 0x1044
312 #define RDMA_TP_OUT_SEL (1 << 0)
313 #define RDMA_MEM_SEL (1 << 1)
315 #define RDMA_DEBUG 0x1048
317 /* Transmit DMA offset and defines */
318 #define TDMA_NUM_RINGS 32 /* rings = queues */
319 #define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */
321 #define SYS_PORT_TDMA_OFFSET 0x4000
322 #define TDMA_WRITE_PORT_OFFSET 0x0000
323 #define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \
324 (i) * TDMA_PORT_SIZE)
325 #define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \
326 sizeof(u32) + (i) * TDMA_PORT_SIZE)
328 #define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \
329 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
330 #define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \
331 (i) * TDMA_PORT_SIZE)
332 #define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \
333 sizeof(u32) + (i) * TDMA_PORT_SIZE)
335 #define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \
336 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
337 #define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \
340 #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \
341 (TDMA_NUM_RINGS * sizeof(u32)))
343 /* Register offsets and defines relatives to a specific ring number */
344 #define RING_HEAD_TAIL_PTR 0x00
345 #define RING_HEAD_MASK 0x7ff
346 #define RING_TAIL_SHIFT 11
347 #define RING_TAIL_MASK 0x7ff
348 #define RING_FLUSH (1 << 24)
349 #define RING_EN (1 << 25)
351 #define RING_COUNT 0x04
352 #define RING_COUNT_MASK 0x7ff
353 #define RING_BUFF_DONE_SHIFT 11
354 #define RING_BUFF_DONE_MASK 0x7ff
356 #define RING_MAX_HYST 0x08
357 #define RING_MAX_THRESH_MASK 0x7ff
358 #define RING_HYST_THRESH_SHIFT 11
359 #define RING_HYST_THRESH_MASK 0x7ff
361 #define RING_INTR_CONTROL 0x0c
362 #define RING_INTR_THRESH_MASK 0x7ff
363 #define RING_EMPTY_INTR_EN (1 << 15)
364 #define RING_TIMEOUT_SHIFT 16
365 #define RING_TIMEOUT_MASK 0xffff
367 #define RING_PROD_CONS_INDEX 0x10
368 #define RING_PROD_INDEX_MASK 0xffff
369 #define RING_CONS_INDEX_SHIFT 16
370 #define RING_CONS_INDEX_MASK 0xffff
372 #define RING_MAPPING 0x14
373 #define RING_QID_MASK 0x3
374 #define RING_PORT_ID_SHIFT 3
375 #define RING_PORT_ID_MASK 0x7
376 #define RING_IGNORE_STATUS (1 << 6)
377 #define RING_FAILOVER_EN (1 << 7)
378 #define RING_CREDIT_SHIFT 8
379 #define RING_CREDIT_MASK 0xffff
381 #define RING_PCP_DEI_VID 0x18
382 #define RING_VID_MASK 0x7ff
383 #define RING_DEI (1 << 12)
384 #define RING_PCP_SHIFT 13
385 #define RING_PCP_MASK 0x7
386 #define RING_PKT_SIZE_ADJ_SHIFT 16
387 #define RING_PKT_SIZE_ADJ_MASK 0xf
389 #define TDMA_DESC_RING_SIZE 28
391 /* Defininition for a given TX ring base address */
392 #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \
393 ((i) * TDMA_DESC_RING_SIZE))
395 /* Ring indexed register addreses */
396 #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \
398 #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \
400 #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \
402 #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \
404 #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
405 (TDMA_DESC_RING_BASE(i) + \
406 RING_PROD_CONS_INDEX)
407 #define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \
409 #define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \
412 #define TDMA_CONTROL 0x600
413 #define TDMA_EN (1 << 0)
414 #define TSB_EN (1 << 1)
415 #define TSB_SWAP (1 << 2)
416 #define ACB_ALGO (1 << 3)
417 #define BUF_DATA_OFFSET_SHIFT 4
418 #define BUF_DATA_OFFSET_MASK 0x3ff
419 #define VLAN_EN (1 << 14)
420 #define SW_BRCM_TAG (1 << 15)
421 #define WNC_KPT_SIZE_UPDATE (1 << 16)
422 #define SYNC_PKT_SIZE (1 << 17)
423 #define ACH_TXDONE_DELAY_SHIFT 18
424 #define ACH_TXDONE_DELAY_MASK 0xff
426 #define TDMA_STATUS 0x604
427 #define TDMA_DISABLED (1 << 0)
428 #define TDMA_LL_RAM_INIT_BUSY (1 << 1)
430 #define TDMA_SCB_BURST_SIZE 0x608
431 #define TDMA_OVER_MAX_THRESH_STATUS 0x60c
432 #define TDMA_OVER_HYST_THRESH_STATUS 0x610
433 #define TDMA_TPID 0x614
435 #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618
436 #define TDMA_FREE_HEAD_MASK 0x7ff
437 #define TDMA_FREE_TAIL_SHIFT 11
438 #define TDMA_FREE_TAIL_MASK 0x7ff
440 #define TDMA_FREE_LIST_COUNT 0x61c
441 #define TDMA_FREE_LIST_COUNT_MASK 0x7ff
443 #define TDMA_TIER2_ARB_CTRL 0x620
444 #define TDMA_ARB_MODE_RR 0
445 #define TDMA_ARB_MODE_WEIGHT_RR 0x1
446 #define TDMA_ARB_MODE_STRICT 0x2
447 #define TDMA_ARB_MODE_DEFICIT_RR 0x3
448 #define TDMA_CREDIT_SHIFT 4
449 #define TDMA_CREDIT_MASK 0xffff
451 #define TDMA_TIER1_ARB_0_CTRL 0x624
452 #define TDMA_ARB_EN (1 << 0)
454 #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628
455 #define TDMA_TIER1_ARB_1_CTRL 0x62c
456 #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630
457 #define TDMA_TIER1_ARB_2_CTRL 0x634
458 #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638
459 #define TDMA_TIER1_ARB_3_CTRL 0x63c
460 #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640
462 #define TDMA_SCB_ENDIAN_OVERRIDE 0x644
463 #define TDMA_LE_MODE (1 << 0)
464 #define TDMA_REG_MODE (1 << 1)
466 #define TDMA_TEST 0x648
467 #define TDMA_TP_OUT_SEL (1 << 0)
468 #define TDMA_MEM_TM (1 << 1)
470 #define TDMA_DEBUG 0x64c
472 /* Transmit/Receive descriptor */
478 /* Number of Receive hardware descriptor words */
479 #define NUM_HW_RX_DESC_WORDS 1024
480 /* Real number of usable descriptors */
481 #define NUM_RX_DESC (NUM_HW_RX_DESC_WORDS / WORDS_PER_DESC)
483 /* Internal linked-list RAM has up to 1536 entries */
484 #define NUM_TX_DESC 1536
486 #define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32))
488 /* Rx/Tx common counter group.*/
489 struct bcm_sysport_pkt_counters {
490 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */
491 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */
492 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */
493 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */
494 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */
495 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */
496 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */
497 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/
498 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/
499 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/
502 /* RSV, Receive Status Vector */
503 struct bcm_sysport_rx_counters {
504 struct bcm_sysport_pkt_counters pkt_cnt;
505 u32 pkt; /* RO (0x428) Received pkt count*/
506 u32 bytes; /* RO Received byte count */
507 u32 mca; /* RO # of Received multicast pkt */
508 u32 bca; /* RO # of Receive broadcast pkt */
509 u32 fcs; /* RO # of Received FCS error */
510 u32 cf; /* RO # of Received control frame pkt*/
511 u32 pf; /* RO # of Received pause frame pkt */
512 u32 uo; /* RO # of unknown op code pkt */
513 u32 aln; /* RO # of alignment error count */
514 u32 flr; /* RO # of frame length out of range count */
515 u32 cde; /* RO # of code error pkt */
516 u32 fcr; /* RO # of carrier sense error pkt */
517 u32 ovr; /* RO # of oversize pkt*/
518 u32 jbr; /* RO # of jabber count */
519 u32 mtue; /* RO # of MTU error pkt*/
520 u32 pok; /* RO # of Received good pkt */
521 u32 uc; /* RO # of unicast pkt */
522 u32 ppp; /* RO # of PPP pkt */
523 u32 rcrc; /* RO (0x470),# of CRC match pkt */
526 /* TSV, Transmit Status Vector */
527 struct bcm_sysport_tx_counters {
528 struct bcm_sysport_pkt_counters pkt_cnt;
529 u32 pkts; /* RO (0x4a8) Transmited pkt */
530 u32 mca; /* RO # of xmited multicast pkt */
531 u32 bca; /* RO # of xmited broadcast pkt */
532 u32 pf; /* RO # of xmited pause frame count */
533 u32 cf; /* RO # of xmited control frame count */
534 u32 fcs; /* RO # of xmited FCS error count */
535 u32 ovr; /* RO # of xmited oversize pkt */
536 u32 drf; /* RO # of xmited deferral pkt */
537 u32 edf; /* RO # of xmited Excessive deferral pkt*/
538 u32 scl; /* RO # of xmited single collision pkt */
539 u32 mcl; /* RO # of xmited multiple collision pkt*/
540 u32 lcl; /* RO # of xmited late collision pkt */
541 u32 ecl; /* RO # of xmited excessive collision pkt*/
542 u32 frg; /* RO # of xmited fragments pkt*/
543 u32 ncl; /* RO # of xmited total collision count */
544 u32 jbr; /* RO # of xmited jabber count*/
545 u32 bytes; /* RO # of xmited byte count */
546 u32 pok; /* RO # of xmited good pkt */
547 u32 uc; /* RO (0x4f0) # of xmited unicast pkt */
550 struct bcm_sysport_mib {
551 struct bcm_sysport_rx_counters rx;
552 struct bcm_sysport_tx_counters tx;
555 u32 rx_runt_fcs_align;
558 u32 rxchk_other_pkt_disc;
561 u32 alloc_rx_buff_failed;
566 /* HW maintains a large list of counters */
567 enum bcm_sysport_stat_type {
568 BCM_SYSPORT_STAT_NETDEV = -1,
569 BCM_SYSPORT_STAT_MIB_RX,
570 BCM_SYSPORT_STAT_MIB_TX,
571 BCM_SYSPORT_STAT_RUNT,
572 BCM_SYSPORT_STAT_RXCHK,
573 BCM_SYSPORT_STAT_RBUF,
574 BCM_SYSPORT_STAT_SOFT,
577 /* Macros to help define ethtool statistics */
578 #define STAT_NETDEV(m) { \
579 .stat_string = __stringify(m), \
580 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
581 .stat_offset = offsetof(struct net_device_stats, m), \
582 .type = BCM_SYSPORT_STAT_NETDEV, \
585 #define STAT_MIB(str, m, _type) { \
586 .stat_string = str, \
587 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
588 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
592 #define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX)
593 #define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX)
594 #define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT)
595 #define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT)
597 #define STAT_RXCHK(str, m, ofs) { \
598 .stat_string = str, \
599 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
600 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
601 .type = BCM_SYSPORT_STAT_RXCHK, \
605 #define STAT_RBUF(str, m, ofs) { \
606 .stat_string = str, \
607 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
608 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
609 .type = BCM_SYSPORT_STAT_RBUF, \
613 struct bcm_sysport_stats {
614 char stat_string[ETH_GSTRING_LEN];
617 enum bcm_sysport_stat_type type;
618 /* reg offset from UMAC base for misc counters */
622 /* Software house keeping helper structure */
623 struct bcm_sysport_cb {
624 struct sk_buff *skb; /* SKB for RX packets */
625 void __iomem *bd_addr; /* Buffer descriptor PHYS addr */
627 DEFINE_DMA_UNMAP_ADDR(dma_addr);
628 DEFINE_DMA_UNMAP_LEN(dma_len);
631 /* Software view of the TX ring */
632 struct bcm_sysport_tx_ring {
633 spinlock_t lock; /* Ring lock for tx reclaim/xmit */
634 struct napi_struct napi; /* NAPI per tx queue */
635 dma_addr_t desc_dma; /* DMA cookie */
636 unsigned int index; /* Ring index */
637 unsigned int size; /* Ring current size */
638 unsigned int alloc_size; /* Ring one-time allocated size */
639 unsigned int desc_count; /* Number of descriptors */
640 unsigned int curr_desc; /* Current descriptor */
641 unsigned int c_index; /* Last consumer index */
642 unsigned int clean_index; /* Current clean index */
643 struct bcm_sysport_cb *cbs; /* Transmit control blocks */
644 struct dma_desc *desc_cpu; /* CPU view of the descriptor */
645 struct bcm_sysport_priv *priv; /* private context backpointer */
648 /* Driver private structure */
649 struct bcm_sysport_priv {
655 struct napi_struct napi ____cacheline_aligned;
656 struct net_device *netdev;
657 struct platform_device *pdev;
663 spinlock_t desc_lock;
664 struct bcm_sysport_tx_ring tx_rings[TDMA_NUM_RINGS];
667 void __iomem *rx_bds;
668 struct bcm_sysport_cb *rx_cbs;
669 unsigned int num_rx_bds;
670 unsigned int rx_read_ptr;
671 unsigned int rx_c_index;
674 struct device_node *phy_dn;
675 phy_interface_t phy_interface;
681 unsigned int rx_chk_en:1;
682 unsigned int tsb_en:1;
683 unsigned int crc_fwd:1;
686 u8 sopass[SOPASS_MAX];
687 unsigned int wol_irq_disabled:1;
689 /* MIB related fields */
690 struct bcm_sysport_mib mib;
695 #endif /* __BCM_SYSPORT_H */