1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef BCM63XX_ENET_H_
3 #define BCM63XX_ENET_H_
5 #include <linux/types.h>
7 #include <linux/mutex.h>
9 #include <linux/platform_device.h>
11 #include <bcm63xx_regs.h>
12 #include <bcm63xx_irq.h>
13 #include <bcm63xx_io.h>
14 #include <bcm63xx_iudma.h>
16 /* default number of descriptor */
17 #define BCMENET_DEF_RX_DESC 64
18 #define BCMENET_DEF_TX_DESC 32
20 /* maximum burst len for dma (4 bytes unit) */
21 #define BCMENET_DMA_MAXBURST 16
22 #define BCMENETSW_DMA_MAXBURST 8
24 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
25 * must be low enough so that a DMA transfer of above burst length can
26 * not overflow the fifo */
27 #define BCMENET_TX_FIFO_TRESH 32
30 * hardware maximum rx/tx packet size including FCS, max mtu is
31 * actually 2047, but if we set max rx size register to 2047 we won't
32 * get overflow information if packet size is 2048 or above
34 #define BCMENET_MAX_MTU 2046
37 * MIB Counters register definitions
39 #define ETH_MIB_TX_GD_OCTETS 0
40 #define ETH_MIB_TX_GD_PKTS 1
41 #define ETH_MIB_TX_ALL_OCTETS 2
42 #define ETH_MIB_TX_ALL_PKTS 3
43 #define ETH_MIB_TX_BRDCAST 4
44 #define ETH_MIB_TX_MULT 5
45 #define ETH_MIB_TX_64 6
46 #define ETH_MIB_TX_65_127 7
47 #define ETH_MIB_TX_128_255 8
48 #define ETH_MIB_TX_256_511 9
49 #define ETH_MIB_TX_512_1023 10
50 #define ETH_MIB_TX_1024_MAX 11
51 #define ETH_MIB_TX_JAB 12
52 #define ETH_MIB_TX_OVR 13
53 #define ETH_MIB_TX_FRAG 14
54 #define ETH_MIB_TX_UNDERRUN 15
55 #define ETH_MIB_TX_COL 16
56 #define ETH_MIB_TX_1_COL 17
57 #define ETH_MIB_TX_M_COL 18
58 #define ETH_MIB_TX_EX_COL 19
59 #define ETH_MIB_TX_LATE 20
60 #define ETH_MIB_TX_DEF 21
61 #define ETH_MIB_TX_CRS 22
62 #define ETH_MIB_TX_PAUSE 23
64 #define ETH_MIB_RX_GD_OCTETS 32
65 #define ETH_MIB_RX_GD_PKTS 33
66 #define ETH_MIB_RX_ALL_OCTETS 34
67 #define ETH_MIB_RX_ALL_PKTS 35
68 #define ETH_MIB_RX_BRDCAST 36
69 #define ETH_MIB_RX_MULT 37
70 #define ETH_MIB_RX_64 38
71 #define ETH_MIB_RX_65_127 39
72 #define ETH_MIB_RX_128_255 40
73 #define ETH_MIB_RX_256_511 41
74 #define ETH_MIB_RX_512_1023 42
75 #define ETH_MIB_RX_1024_MAX 43
76 #define ETH_MIB_RX_JAB 44
77 #define ETH_MIB_RX_OVR 45
78 #define ETH_MIB_RX_FRAG 46
79 #define ETH_MIB_RX_DROP 47
80 #define ETH_MIB_RX_CRC_ALIGN 48
81 #define ETH_MIB_RX_UND 49
82 #define ETH_MIB_RX_CRC 50
83 #define ETH_MIB_RX_ALIGN 51
84 #define ETH_MIB_RX_SYM 52
85 #define ETH_MIB_RX_PAUSE 53
86 #define ETH_MIB_RX_CNTRL 54
90 * SW MIB Counters register definitions
92 #define ETHSW_MIB_TX_ALL_OCT 0
93 #define ETHSW_MIB_TX_DROP_PKTS 2
94 #define ETHSW_MIB_TX_QOS_PKTS 3
95 #define ETHSW_MIB_TX_BRDCAST 4
96 #define ETHSW_MIB_TX_MULT 5
97 #define ETHSW_MIB_TX_UNI 6
98 #define ETHSW_MIB_TX_COL 7
99 #define ETHSW_MIB_TX_1_COL 8
100 #define ETHSW_MIB_TX_M_COL 9
101 #define ETHSW_MIB_TX_DEF 10
102 #define ETHSW_MIB_TX_LATE 11
103 #define ETHSW_MIB_TX_EX_COL 12
104 #define ETHSW_MIB_TX_PAUSE 14
105 #define ETHSW_MIB_TX_QOS_OCT 15
107 #define ETHSW_MIB_RX_ALL_OCT 17
108 #define ETHSW_MIB_RX_UND 19
109 #define ETHSW_MIB_RX_PAUSE 20
110 #define ETHSW_MIB_RX_64 21
111 #define ETHSW_MIB_RX_65_127 22
112 #define ETHSW_MIB_RX_128_255 23
113 #define ETHSW_MIB_RX_256_511 24
114 #define ETHSW_MIB_RX_512_1023 25
115 #define ETHSW_MIB_RX_1024_1522 26
116 #define ETHSW_MIB_RX_OVR 27
117 #define ETHSW_MIB_RX_JAB 28
118 #define ETHSW_MIB_RX_ALIGN 29
119 #define ETHSW_MIB_RX_CRC 30
120 #define ETHSW_MIB_RX_GD_OCT 31
121 #define ETHSW_MIB_RX_DROP 33
122 #define ETHSW_MIB_RX_UNI 34
123 #define ETHSW_MIB_RX_MULT 35
124 #define ETHSW_MIB_RX_BRDCAST 36
125 #define ETHSW_MIB_RX_SA_CHANGE 37
126 #define ETHSW_MIB_RX_FRAG 38
127 #define ETHSW_MIB_RX_OVR_DISC 39
128 #define ETHSW_MIB_RX_SYM 40
129 #define ETHSW_MIB_RX_QOS_PKTS 41
130 #define ETHSW_MIB_RX_QOS_OCT 42
131 #define ETHSW_MIB_RX_1523_2047 44
132 #define ETHSW_MIB_RX_2048_4095 45
133 #define ETHSW_MIB_RX_4096_8191 46
134 #define ETHSW_MIB_RX_8192_9728 47
137 struct bcm_enet_mib_counters {
195 struct bcm_enet_priv {
197 /* mac id (from platform device id) */
200 /* base remapped address of device */
203 /* mac irq, rx_dma irq, tx_dma irq */
208 /* hw view of rx & tx dma ring */
209 dma_addr_t rx_desc_dma;
210 dma_addr_t tx_desc_dma;
212 /* allocated size (in bytes) for rx & tx dma ring */
213 unsigned int rx_desc_alloc_size;
214 unsigned int tx_desc_alloc_size;
217 struct napi_struct napi;
219 /* dma channel id for rx */
222 /* number of dma desc in rx ring */
225 /* cpu view of rx dma ring */
226 struct bcm_enet_desc *rx_desc_cpu;
228 /* current number of armed descriptor given to hardware for rx */
231 /* next rx descriptor to fetch from hardware */
234 /* next dirty rx descriptor to refill */
237 /* size of allocated rx skbs */
238 unsigned int rx_skb_size;
240 /* list of skb given to hw for rx */
241 struct sk_buff **rx_skb;
243 /* used when rx skb allocation failed, so we defer rx queue
245 struct timer_list rx_timeout;
247 /* lock rx_timeout against rx normal operation */
251 /* dma channel id for tx */
254 /* number of dma desc in tx ring */
257 /* maximum dma burst size */
260 /* cpu view of rx dma ring */
261 struct bcm_enet_desc *tx_desc_cpu;
263 /* number of available descriptor for tx */
266 /* next tx descriptor avaiable */
269 /* next dirty tx descriptor to reclaim */
272 /* list of skb given to hw for tx */
273 struct sk_buff **tx_skb;
275 /* lock used by tx reclaim and xmit */
279 /* set if internal phy is ignored and external mii interface
281 int use_external_mii;
283 /* set if a phy is connected, phy address must be known,
284 * probing is not possible */
288 /* set if connected phy has an associated irq */
289 int has_phy_interrupt;
292 /* used when a phy is connected (phylib used) */
293 struct mii_bus *mii_bus;
298 /* used when no phy is connected */
300 int force_duplex_full;
302 /* pause parameters */
308 struct bcm_enet_mib_counters mib;
310 /* after mib interrupt, mib registers update is done in this
312 struct work_struct mib_update_task;
314 /* lock mib update between userspace request and workqueue */
315 struct mutex mib_update_lock;
320 /* phy clock if internal phy is used */
323 /* network device reference */
324 struct net_device *net_dev;
326 /* platform device reference */
327 struct platform_device *pdev;
329 /* maximum hardware transmit/receive size */
334 /* port mapping for switch devices */
336 struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
337 int sw_port_link[ENETSW_MAX_PORT];
339 /* used to poll switch port state */
340 struct timer_list swphy_poll;
341 spinlock_t enetsw_mdio_lock;
343 /* dma channel enable mask */
344 u32 dma_chan_en_mask;
346 /* dma channel interrupt mask */
347 u32 dma_chan_int_mask;
349 /* DMA engine has internal SRAM */
352 /* dma channel width */
353 unsigned int dma_chan_width;
355 /* dma descriptor shift value */
356 unsigned int dma_desc_shift;
360 #endif /* ! BCM63XX_ENET_H_ */