drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(struct timer_list *t)
 299 {
 300         struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout);
 301         struct net_device *dev = priv->net_dev;
 302
 303         spin_lock(&priv->rx_lock);
 304         bcm_enet_refill_rx(dev);
 305         spin_unlock(&priv->rx_lock);
 306 }
 307
 308 /*
 309  * extract packet from rx queue
 310  */
 311 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 312 {
 313         struct bcm_enet_priv *priv;
 314         struct device *kdev;
 315         int processed;
 316
 317         priv = netdev_priv(dev);
 318         kdev = &priv->pdev->dev;
 319         processed = 0;
 320
 321         /* don't scan ring further than number of refilled
 322          * descriptor */
 323         if (budget > priv->rx_desc_count)
 324                 budget = priv->rx_desc_count;
 325
 326         do {
 327                 struct bcm_enet_desc *desc;
 328                 struct sk_buff *skb;
 329                 int desc_idx;
 330                 u32 len_stat;
 331                 unsigned int len;
 332
 333                 desc_idx = priv->rx_curr_desc;
 334                 desc = &priv->rx_desc_cpu[desc_idx];
 335
 336                 /* make sure we actually read the descriptor status at
 337                  * each loop */
 338                 rmb();
 339
 340                 len_stat = desc->len_stat;
 341
 342                 /* break if dma ownership belongs to hw */
 343                 if (len_stat & DMADESC_OWNER_MASK)
 344                         break;
 345
 346                 processed++;
 347                 priv->rx_curr_desc++;
 348                 if (priv->rx_curr_desc == priv->rx_ring_size)
 349                         priv->rx_curr_desc = 0;
 350                 priv->rx_desc_count--;
 351
 352                 /* if the packet does not have start of packet _and_
 353                  * end of packet flag set, then just recycle it */
 354                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 355                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 356                         dev->stats.rx_dropped++;
 357                         continue;
 358                 }
 359
 360                 /* recycle packet if it's marked as bad */
 361                 if (!priv->enet_is_sw &&
 362                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 363                         dev->stats.rx_errors++;
 364
 365                         if (len_stat & DMADESC_OVSIZE_MASK)
 366                                 dev->stats.rx_length_errors++;
 367                         if (len_stat & DMADESC_CRC_MASK)
 368                                 dev->stats.rx_crc_errors++;
 369                         if (len_stat & DMADESC_UNDER_MASK)
 370                                 dev->stats.rx_frame_errors++;
 371                         if (len_stat & DMADESC_OV_MASK)
 372                                 dev->stats.rx_fifo_errors++;
 373                         continue;
 374                 }
 375
 376                 /* valid packet */
 377                 skb = priv->rx_skb[desc_idx];
 378                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 379                 /* don't include FCS */
 380                 len -= 4;
 381
 382                 if (len < copybreak) {
 383                         struct sk_buff *nskb;
 384
 385                         nskb = napi_alloc_skb(&priv->napi, len);
 386                         if (!nskb) {
 387                                 /* forget packet, just rearm desc */
 388                                 dev->stats.rx_dropped++;
 389                                 continue;
 390                         }
 391
 392                         dma_sync_single_for_cpu(kdev, desc->address,
 393                                                 len, DMA_FROM_DEVICE);
 394                         memcpy(nskb->data, skb->data, len);
 395                         dma_sync_single_for_device(kdev, desc->address,
 396                                                    len, DMA_FROM_DEVICE);
 397                         skb = nskb;
 398                 } else {
 399                         dma_unmap_single(&priv->pdev->dev, desc->address,
 400                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 401                         priv->rx_skb[desc_idx] = NULL;
 402                 }
 403
 404                 skb_put(skb, len);
 405                 skb->protocol = eth_type_trans(skb, dev);
 406                 dev->stats.rx_packets++;
 407                 dev->stats.rx_bytes += len;
 408                 netif_receive_skb(skb);
 409
 410         } while (--budget > 0);
 411
 412         if (processed || !priv->rx_desc_count) {
 413                 bcm_enet_refill_rx(dev);
 414
 415                 /* kick rx dma */
 416                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 417                                          ENETDMAC_CHANCFG, priv->rx_chan);
 418         }
 419
 420         return processed;
 421 }
 422
 423
 424 /*
 425  * try to or force reclaim of transmitted buffers
 426  */
 427 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 428 {
 429         struct bcm_enet_priv *priv;
 430         int released;
 431
 432         priv = netdev_priv(dev);
 433         released = 0;
 434
 435         while (priv->tx_desc_count < priv->tx_ring_size) {
 436                 struct bcm_enet_desc *desc;
 437                 struct sk_buff *skb;
 438
 439                 /* We run in a bh and fight against start_xmit, which
 440                  * is called with bh disabled  */
 441                 spin_lock(&priv->tx_lock);
 442
 443                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 444
 445                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 446                         spin_unlock(&priv->tx_lock);
 447                         break;
 448                 }
 449
 450                 /* ensure other field of the descriptor were not read
 451                  * before we checked ownership */
 452                 rmb();
 453
 454                 skb = priv->tx_skb[priv->tx_dirty_desc];
 455                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 456                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 457                                  DMA_TO_DEVICE);
 458
 459                 priv->tx_dirty_desc++;
 460                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 461                         priv->tx_dirty_desc = 0;
 462                 priv->tx_desc_count++;
 463
 464                 spin_unlock(&priv->tx_lock);
 465
 466                 if (desc->len_stat & DMADESC_UNDER_MASK)
 467                         dev->stats.tx_errors++;
 468
 469                 dev_kfree_skb(skb);
 470                 released++;
 471         }
 472
 473         if (netif_queue_stopped(dev) && released)
 474                 netif_wake_queue(dev);
 475
 476         return released;
 477 }
 478
 479 /*
 480  * poll func, called by network core
 481  */
 482 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 483 {
 484         struct bcm_enet_priv *priv;
 485         struct net_device *dev;
 486         int rx_work_done;
 487
 488         priv = container_of(napi, struct bcm_enet_priv, napi);
 489         dev = priv->net_dev;
 490
 491         /* ack interrupts */
 492         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 493                          ENETDMAC_IR, priv->rx_chan);
 494         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 495                          ENETDMAC_IR, priv->tx_chan);
 496
 497         /* reclaim sent skb */
 498         bcm_enet_tx_reclaim(dev, 0);
 499
 500         spin_lock(&priv->rx_lock);
 501         rx_work_done = bcm_enet_receive_queue(dev, budget);
 502         spin_unlock(&priv->rx_lock);
 503
 504         if (rx_work_done >= budget) {
 505                 /* rx queue is not yet empty/clean */
 506                 return rx_work_done;
 507         }
 508
 509         /* no more packet in rx/tx queue, remove device from poll
 510          * queue */
 511         napi_complete_done(napi, rx_work_done);
 512
 513         /* restore rx/tx interrupt */
 514         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 515                          ENETDMAC_IRMASK, priv->rx_chan);
 516         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 517                          ENETDMAC_IRMASK, priv->tx_chan);
 518
 519         return rx_work_done;
 520 }
 521
 522 /*
 523  * mac interrupt handler
 524  */
 525 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 526 {
 527         struct net_device *dev;
 528         struct bcm_enet_priv *priv;
 529         u32 stat;
 530
 531         dev = dev_id;
 532         priv = netdev_priv(dev);
 533
 534         stat = enet_readl(priv, ENET_IR_REG);
 535         if (!(stat & ENET_IR_MIB))
 536                 return IRQ_NONE;
 537
 538         /* clear & mask interrupt */
 539         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 540         enet_writel(priv, 0, ENET_IRMASK_REG);
 541
 542         /* read mib registers in workqueue */
 543         schedule_work(&priv->mib_update_task);
 544
 545         return IRQ_HANDLED;
 546 }
 547
 548 /*
 549  * rx/tx dma interrupt handler
 550  */
 551 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 552 {
 553         struct net_device *dev;
 554         struct bcm_enet_priv *priv;
 555
 556         dev = dev_id;
 557         priv = netdev_priv(dev);
 558
 559         /* mask rx/tx interrupts */
 560         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 561         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 562
 563         napi_schedule(&priv->napi);
 564
 565         return IRQ_HANDLED;
 566 }
 567
 568 /*
 569  * tx request callback
 570  */
 571 static netdev_tx_t
 572 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 573 {
 574         struct bcm_enet_priv *priv;
 575         struct bcm_enet_desc *desc;
 576         u32 len_stat;
 577         netdev_tx_t ret;
 578
 579         priv = netdev_priv(dev);
 580
 581         /* lock against tx reclaim */
 582         spin_lock(&priv->tx_lock);
 583
 584         /* make sure  the tx hw queue  is not full,  should not happen
 585          * since we stop queue before it's the case */
 586         if (unlikely(!priv->tx_desc_count)) {
 587                 netif_stop_queue(dev);
 588                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 589                         "available?\n");
 590                 ret = NETDEV_TX_BUSY;
 591                 goto out_unlock;
 592         }
 593
 594         /* pad small packets sent on a switch device */
 595         if (priv->enet_is_sw && skb->len < 64) {
 596                 int needed = 64 - skb->len;
 597                 char *data;
 598
 599                 if (unlikely(skb_tailroom(skb) < needed)) {
 600                         struct sk_buff *nskb;
 601
 602                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 603                         if (!nskb) {
 604                                 ret = NETDEV_TX_BUSY;
 605                                 goto out_unlock;
 606                         }
 607                         dev_kfree_skb(skb);
 608                         skb = nskb;
 609                 }
 610                 data = skb_put_zero(skb, needed);
 611         }
 612
 613         /* point to the next available desc */
 614         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 615         priv->tx_skb[priv->tx_curr_desc] = skb;
 616
 617         /* fill descriptor */
 618         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 619                                        DMA_TO_DEVICE);
 620
 621         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 622         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 623                 DMADESC_APPEND_CRC |
 624                 DMADESC_OWNER_MASK;
 625
 626         priv->tx_curr_desc++;
 627         if (priv->tx_curr_desc == priv->tx_ring_size) {
 628                 priv->tx_curr_desc = 0;
 629                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 630         }
 631         priv->tx_desc_count--;
 632
 633         /* dma might be already polling, make sure we update desc
 634          * fields in correct order */
 635         wmb();
 636         desc->len_stat = len_stat;
 637         wmb();
 638
 639         /* kick tx dma */
 640         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 641                                  ENETDMAC_CHANCFG, priv->tx_chan);
 642
 643         /* stop queue if no more desc available */
 644         if (!priv->tx_desc_count)
 645                 netif_stop_queue(dev);
 646
 647         dev->stats.tx_bytes += skb->len;
 648         dev->stats.tx_packets++;
 649         ret = NETDEV_TX_OK;
 650
 651 out_unlock:
 652         spin_unlock(&priv->tx_lock);
 653         return ret;
 654 }
 655
 656 /*
 657  * Change the interface's mac address.
 658  */
 659 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 660 {
 661         struct bcm_enet_priv *priv;
 662         struct sockaddr *addr = p;
 663         u32 val;
 664
 665         priv = netdev_priv(dev);
 666         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 667
 668         /* use perfect match register 0 to store my mac address */
 669         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 670                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 671         enet_writel(priv, val, ENET_PML_REG(0));
 672
 673         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 674         val |= ENET_PMH_DATAVALID_MASK;
 675         enet_writel(priv, val, ENET_PMH_REG(0));
 676
 677         return 0;
 678 }
 679
 680 /*
 681  * Change rx mode (promiscuous/allmulti) and update multicast list
 682  */
 683 static void bcm_enet_set_multicast_list(struct net_device *dev)
 684 {
 685         struct bcm_enet_priv *priv;
 686         struct netdev_hw_addr *ha;
 687         u32 val;
 688         int i;
 689
 690         priv = netdev_priv(dev);
 691
 692         val = enet_readl(priv, ENET_RXCFG_REG);
 693
 694         if (dev->flags & IFF_PROMISC)
 695                 val |= ENET_RXCFG_PROMISC_MASK;
 696         else
 697                 val &= ~ENET_RXCFG_PROMISC_MASK;
 698
 699         /* only 3 perfect match registers left, first one is used for
 700          * own mac address */
 701         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 702                 val |= ENET_RXCFG_ALLMCAST_MASK;
 703         else
 704                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 705
 706         /* no need to set perfect match registers if we catch all
 707          * multicast */
 708         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 709                 enet_writel(priv, val, ENET_RXCFG_REG);
 710                 return;
 711         }
 712
 713         i = 0;
 714         netdev_for_each_mc_addr(ha, dev) {
 715                 u8 *dmi_addr;
 716                 u32 tmp;
 717
 718                 if (i == 3)
 719                         break;
 720                 /* update perfect match registers */
 721                 dmi_addr = ha->addr;
 722                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 723                         (dmi_addr[4] << 8) | dmi_addr[5];
 724                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 725
 726                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 727                 tmp |= ENET_PMH_DATAVALID_MASK;
 728                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 729         }
 730
 731         for (; i < 3; i++) {
 732                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 733                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 734         }
 735
 736         enet_writel(priv, val, ENET_RXCFG_REG);
 737 }
 738
 739 /*
 740  * set mac duplex parameters
 741  */
 742 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 743 {
 744         u32 val;
 745
 746         val = enet_readl(priv, ENET_TXCTL_REG);
 747         if (fullduplex)
 748                 val |= ENET_TXCTL_FD_MASK;
 749         else
 750                 val &= ~ENET_TXCTL_FD_MASK;
 751         enet_writel(priv, val, ENET_TXCTL_REG);
 752 }
 753
 754 /*
 755  * set mac flow control parameters
 756  */
 757 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 758 {
 759         u32 val;
 760
 761         /* rx flow control (pause frame handling) */
 762         val = enet_readl(priv, ENET_RXCFG_REG);
 763         if (rx_en)
 764                 val |= ENET_RXCFG_ENFLOW_MASK;
 765         else
 766                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 767         enet_writel(priv, val, ENET_RXCFG_REG);
 768
 769         if (!priv->dma_has_sram)
 770                 return;
 771
 772         /* tx flow control (pause frame generation) */
 773         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 774         if (tx_en)
 775                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 776         else
 777                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 778         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 779 }
 780
 781 /*
 782  * link changed callback (from phylib)
 783  */
 784 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 785 {
 786         struct bcm_enet_priv *priv;
 787         struct phy_device *phydev;
 788         int status_changed;
 789
 790         priv = netdev_priv(dev);
 791         phydev = dev->phydev;
 792         status_changed = 0;
 793
 794         if (priv->old_link != phydev->link) {
 795                 status_changed = 1;
 796                 priv->old_link = phydev->link;
 797         }
 798
 799         /* reflect duplex change in mac configuration */
 800         if (phydev->link && phydev->duplex != priv->old_duplex) {
 801                 bcm_enet_set_duplex(priv,
 802                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 803                 status_changed = 1;
 804                 priv->old_duplex = phydev->duplex;
 805         }
 806
 807         /* enable flow control if remote advertise it (trust phylib to
 808          * check that duplex is full */
 809         if (phydev->link && phydev->pause != priv->old_pause) {
 810                 int rx_pause_en, tx_pause_en;
 811
 812                 if (phydev->pause) {
 813                         /* pause was advertised by lpa and us */
 814                         rx_pause_en = 1;
 815                         tx_pause_en = 1;
 816                 } else if (!priv->pause_auto) {
 817                         /* pause setting overridden by user */
 818                         rx_pause_en = priv->pause_rx;
 819                         tx_pause_en = priv->pause_tx;
 820                 } else {
 821                         rx_pause_en = 0;
 822                         tx_pause_en = 0;
 823                 }
 824
 825                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 826                 status_changed = 1;
 827                 priv->old_pause = phydev->pause;
 828         }
 829
 830         if (status_changed) {
 831                 pr_info("%s: link %s", dev->name, phydev->link ?
 832                         "UP" : "DOWN");
 833                 if (phydev->link)
 834                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 835                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 836                                phydev->pause == 1 ? "rx&tx" : "off");
 837
 838                 pr_cont("\n");
 839         }
 840 }
 841
 842 /*
 843  * link changed callback (if phylib is not used)
 844  */
 845 static void bcm_enet_adjust_link(struct net_device *dev)
 846 {
 847         struct bcm_enet_priv *priv;
 848
 849         priv = netdev_priv(dev);
 850         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 851         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 852         netif_carrier_on(dev);
 853
 854         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 855                 dev->name,
 856                 priv->force_speed_100 ? 100 : 10,
 857                 priv->force_duplex_full ? "full" : "half",
 858                 priv->pause_rx ? "rx" : "off",
 859                 priv->pause_tx ? "tx" : "off");
 860 }
 861
 862 /*
 863  * open callback, allocate dma rings & buffers and start rx operation
 864  */
 865 static int bcm_enet_open(struct net_device *dev)
 866 {
 867         struct bcm_enet_priv *priv;
 868         struct sockaddr addr;
 869         struct device *kdev;
 870         struct phy_device *phydev;
 871         int i, ret;
 872         unsigned int size;
 873         char phy_id[MII_BUS_ID_SIZE + 3];
 874         void *p;
 875         u32 val;
 876
 877         priv = netdev_priv(dev);
 878         kdev = &priv->pdev->dev;
 879
 880         if (priv->has_phy) {
 881                 /* connect to PHY */
 882                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 883                          priv->mii_bus->id, priv->phy_id);
 884
 885                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 886                                      PHY_INTERFACE_MODE_MII);
 887
 888                 if (IS_ERR(phydev)) {
 889                         dev_err(kdev, "could not attach to PHY\n");
 890                         return PTR_ERR(phydev);
 891                 }
 892
 893                 /* mask with MAC supported features */
 894                 phydev->supported &= (SUPPORTED_10baseT_Half |
 895                                       SUPPORTED_10baseT_Full |
 896                                       SUPPORTED_100baseT_Half |
 897                                       SUPPORTED_100baseT_Full |
 898                                       SUPPORTED_Autoneg |
 899                                       SUPPORTED_Pause |
 900                                       SUPPORTED_MII);
 901                 phydev->advertising = phydev->supported;
 902
 903                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 904                         phydev->advertising |= SUPPORTED_Pause;
 905                 else
 906                         phydev->advertising &= ~SUPPORTED_Pause;
 907
 908                 phy_attached_info(phydev);
 909
 910                 priv->old_link = 0;
 911                 priv->old_duplex = -1;
 912                 priv->old_pause = -1;
 913         } else {
 914                 phydev = NULL;
 915         }
 916
 917         /* mask all interrupts and request them */
 918         enet_writel(priv, 0, ENET_IRMASK_REG);
 919         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 920         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 921
 922         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 923         if (ret)
 924                 goto out_phy_disconnect;
 925
 926         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 927                           dev->name, dev);
 928         if (ret)
 929                 goto out_freeirq;
 930
 931         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 932                           0, dev->name, dev);
 933         if (ret)
 934                 goto out_freeirq_rx;
 935
 936         /* initialize perfect match registers */
 937         for (i = 0; i < 4; i++) {
 938                 enet_writel(priv, 0, ENET_PML_REG(i));
 939                 enet_writel(priv, 0, ENET_PMH_REG(i));
 940         }
 941
 942         /* write device mac address */
 943         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 944         bcm_enet_set_mac_address(dev, &addr);
 945
 946         /* allocate rx dma ring */
 947         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 948         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 949         if (!p) {
 950                 ret = -ENOMEM;
 951                 goto out_freeirq_tx;
 952         }
 953
 954         priv->rx_desc_alloc_size = size;
 955         priv->rx_desc_cpu = p;
 956
 957         /* allocate tx dma ring */
 958         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 959         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 960         if (!p) {
 961                 ret = -ENOMEM;
 962                 goto out_free_rx_ring;
 963         }
 964
 965         priv->tx_desc_alloc_size = size;
 966         priv->tx_desc_cpu = p;
 967
 968         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 969                                GFP_KERNEL);
 970         if (!priv->tx_skb) {
 971                 ret = -ENOMEM;
 972                 goto out_free_tx_ring;
 973         }
 974
 975         priv->tx_desc_count = priv->tx_ring_size;
 976         priv->tx_dirty_desc = 0;
 977         priv->tx_curr_desc = 0;
 978         spin_lock_init(&priv->tx_lock);
 979
 980         /* init & fill rx ring with skbs */
 981         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 982                                GFP_KERNEL);
 983         if (!priv->rx_skb) {
 984                 ret = -ENOMEM;
 985                 goto out_free_tx_skb;
 986         }
 987
 988         priv->rx_desc_count = 0;
 989         priv->rx_dirty_desc = 0;
 990         priv->rx_curr_desc = 0;
 991
 992         /* initialize flow control buffer allocation */
 993         if (priv->dma_has_sram)
 994                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 995                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 996         else
 997                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 998                                 ENETDMAC_BUFALLOC, priv->rx_chan);
 999
1000         if (bcm_enet_refill_rx(dev)) {
1001                 dev_err(kdev, "cannot allocate rx skb queue\n");
1002                 ret = -ENOMEM;
1003                 goto out;
1004         }
1005
1006         /* write rx & tx ring addresses */
1007         if (priv->dma_has_sram) {
1008                 enet_dmas_writel(priv, priv->rx_desc_dma,
1009                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1010                 enet_dmas_writel(priv, priv->tx_desc_dma,
1011                          ENETDMAS_RSTART_REG, priv->tx_chan);
1012         } else {
1013                 enet_dmac_writel(priv, priv->rx_desc_dma,
1014                                 ENETDMAC_RSTART, priv->rx_chan);
1015                 enet_dmac_writel(priv, priv->tx_desc_dma,
1016                                 ENETDMAC_RSTART, priv->tx_chan);
1017         }
1018
1019         /* clear remaining state ram for rx & tx channel */
1020         if (priv->dma_has_sram) {
1021                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1022                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1027         } else {
1028                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1029                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1030         }
1031
1032         /* set max rx/tx length */
1033         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1034         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1035
1036         /* set dma maximum burst len */
1037         enet_dmac_writel(priv, priv->dma_maxburst,
1038                          ENETDMAC_MAXBURST, priv->rx_chan);
1039         enet_dmac_writel(priv, priv->dma_maxburst,
1040                          ENETDMAC_MAXBURST, priv->tx_chan);
1041
1042         /* set correct transmit fifo watermark */
1043         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1044
1045         /* set flow control low/high threshold to 1/3 / 2/3 */
1046         if (priv->dma_has_sram) {
1047                 val = priv->rx_ring_size / 3;
1048                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1049                 val = (priv->rx_ring_size * 2) / 3;
1050                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1051         } else {
1052                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1053                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1054                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1055         }
1056
1057         /* all set, enable mac and interrupts, start dma engine and
1058          * kick rx dma channel */
1059         wmb();
1060         val = enet_readl(priv, ENET_CTL_REG);
1061         val |= ENET_CTL_ENABLE_MASK;
1062         enet_writel(priv, val, ENET_CTL_REG);
1063         if (priv->dma_has_sram)
1064                 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1065         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1066                          ENETDMAC_CHANCFG, priv->rx_chan);
1067
1068         /* watch "mib counters about to overflow" interrupt */
1069         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1070         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1071
1072         /* watch "packet transferred" interrupt in rx and tx */
1073         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1074                          ENETDMAC_IR, priv->rx_chan);
1075         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076                          ENETDMAC_IR, priv->tx_chan);
1077
1078         /* make sure we enable napi before rx interrupt  */
1079         napi_enable(&priv->napi);
1080
1081         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1082                          ENETDMAC_IRMASK, priv->rx_chan);
1083         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084                          ENETDMAC_IRMASK, priv->tx_chan);
1085
1086         if (phydev)
1087                 phy_start(phydev);
1088         else
1089                 bcm_enet_adjust_link(dev);
1090
1091         netif_start_queue(dev);
1092         return 0;
1093
1094 out:
1095         for (i = 0; i < priv->rx_ring_size; i++) {
1096                 struct bcm_enet_desc *desc;
1097
1098                 if (!priv->rx_skb[i])
1099                         continue;
1100
1101                 desc = &priv->rx_desc_cpu[i];
1102                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1103                                  DMA_FROM_DEVICE);
1104                 kfree_skb(priv->rx_skb[i]);
1105         }
1106         kfree(priv->rx_skb);
1107
1108 out_free_tx_skb:
1109         kfree(priv->tx_skb);
1110
1111 out_free_tx_ring:
1112         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1113                           priv->tx_desc_cpu, priv->tx_desc_dma);
1114
1115 out_free_rx_ring:
1116         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1117                           priv->rx_desc_cpu, priv->rx_desc_dma);
1118
1119 out_freeirq_tx:
1120         free_irq(priv->irq_tx, dev);
1121
1122 out_freeirq_rx:
1123         free_irq(priv->irq_rx, dev);
1124
1125 out_freeirq:
1126         free_irq(dev->irq, dev);
1127
1128 out_phy_disconnect:
1129         if (phydev)
1130                 phy_disconnect(phydev);
1131
1132         return ret;
1133 }
1134
1135 /*
1136  * disable mac
1137  */
1138 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1139 {
1140         int limit;
1141         u32 val;
1142
1143         val = enet_readl(priv, ENET_CTL_REG);
1144         val |= ENET_CTL_DISABLE_MASK;
1145         enet_writel(priv, val, ENET_CTL_REG);
1146
1147         limit = 1000;
1148         do {
1149                 u32 val;
1150
1151                 val = enet_readl(priv, ENET_CTL_REG);
1152                 if (!(val & ENET_CTL_DISABLE_MASK))
1153                         break;
1154                 udelay(1);
1155         } while (limit--);
1156 }
1157
1158 /*
1159  * disable dma in given channel
1160  */
1161 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1162 {
1163         int limit;
1164
1165         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1166
1167         limit = 1000;
1168         do {
1169                 u32 val;
1170
1171                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1172                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1173                         break;
1174                 udelay(1);
1175         } while (limit--);
1176 }
1177
1178 /*
1179  * stop callback
1180  */
1181 static int bcm_enet_stop(struct net_device *dev)
1182 {
1183         struct bcm_enet_priv *priv;
1184         struct device *kdev;
1185         int i;
1186
1187         priv = netdev_priv(dev);
1188         kdev = &priv->pdev->dev;
1189
1190         netif_stop_queue(dev);
1191         napi_disable(&priv->napi);
1192         if (priv->has_phy)
1193                 phy_stop(dev->phydev);
1194         del_timer_sync(&priv->rx_timeout);
1195
1196         /* mask all interrupts */
1197         enet_writel(priv, 0, ENET_IRMASK_REG);
1198         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1199         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1200
1201         /* make sure no mib update is scheduled */
1202         cancel_work_sync(&priv->mib_update_task);
1203
1204         /* disable dma & mac */
1205         bcm_enet_disable_dma(priv, priv->tx_chan);
1206         bcm_enet_disable_dma(priv, priv->rx_chan);
1207         bcm_enet_disable_mac(priv);
1208
1209         /* force reclaim of all tx buffers */
1210         bcm_enet_tx_reclaim(dev, 1);
1211
1212         /* free the rx skb ring */
1213         for (i = 0; i < priv->rx_ring_size; i++) {
1214                 struct bcm_enet_desc *desc;
1215
1216                 if (!priv->rx_skb[i])
1217                         continue;
1218
1219                 desc = &priv->rx_desc_cpu[i];
1220                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1221                                  DMA_FROM_DEVICE);
1222                 kfree_skb(priv->rx_skb[i]);
1223         }
1224
1225         /* free remaining allocated memory */
1226         kfree(priv->rx_skb);
1227         kfree(priv->tx_skb);
1228         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1229                           priv->rx_desc_cpu, priv->rx_desc_dma);
1230         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1231                           priv->tx_desc_cpu, priv->tx_desc_dma);
1232         free_irq(priv->irq_tx, dev);
1233         free_irq(priv->irq_rx, dev);
1234         free_irq(dev->irq, dev);
1235
1236         /* release phy */
1237         if (priv->has_phy)
1238                 phy_disconnect(dev->phydev);
1239
1240         return 0;
1241 }
1242
1243 /*
1244  * ethtool callbacks
1245  */
1246 struct bcm_enet_stats {
1247         char stat_string[ETH_GSTRING_LEN];
1248         int sizeof_stat;
1249         int stat_offset;
1250         int mib_reg;
1251 };
1252
1253 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1254                      offsetof(struct bcm_enet_priv, m)
1255 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1256                      offsetof(struct net_device_stats, m)
1257
1258 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1259         { "rx_packets", DEV_STAT(rx_packets), -1 },
1260         { "tx_packets", DEV_STAT(tx_packets), -1 },
1261         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1262         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1263         { "rx_errors", DEV_STAT(rx_errors), -1 },
1264         { "tx_errors", DEV_STAT(tx_errors), -1 },
1265         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1266         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1267
1268         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1269         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1270         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1271         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1272         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1273         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1274         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1275         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1276         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1277         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1278         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1279         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1280         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1281         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1282         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1283         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1284         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1285         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1286         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1287         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1288         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1289
1290         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1291         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1292         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1293         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1294         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1295         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1296         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1297         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1298         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1299         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1300         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1301         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1302         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1303         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1304         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1305         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1306         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1307         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1308         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1309         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1310         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1311         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1312
1313 };
1314
1315 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1316
1317 static const u32 unused_mib_regs[] = {
1318         ETH_MIB_TX_ALL_OCTETS,
1319         ETH_MIB_TX_ALL_PKTS,
1320         ETH_MIB_RX_ALL_OCTETS,
1321         ETH_MIB_RX_ALL_PKTS,
1322 };
1323
1324
1325 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1326                                  struct ethtool_drvinfo *drvinfo)
1327 {
1328         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1329         strlcpy(drvinfo->version, bcm_enet_driver_version,
1330                 sizeof(drvinfo->version));
1331         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1332         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1333 }
1334
1335 static int bcm_enet_get_sset_count(struct net_device *netdev,
1336                                         int string_set)
1337 {
1338         switch (string_set) {
1339         case ETH_SS_STATS:
1340                 return BCM_ENET_STATS_LEN;
1341         default:
1342                 return -EINVAL;
1343         }
1344 }
1345
1346 static void bcm_enet_get_strings(struct net_device *netdev,
1347                                  u32 stringset, u8 *data)
1348 {
1349         int i;
1350
1351         switch (stringset) {
1352         case ETH_SS_STATS:
1353                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1354                         memcpy(data + i * ETH_GSTRING_LEN,
1355                                bcm_enet_gstrings_stats[i].stat_string,
1356                                ETH_GSTRING_LEN);
1357                 }
1358                 break;
1359         }
1360 }
1361
1362 static void update_mib_counters(struct bcm_enet_priv *priv)
1363 {
1364         int i;
1365
1366         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1367                 const struct bcm_enet_stats *s;
1368                 u32 val;
1369                 char *p;
1370
1371                 s = &bcm_enet_gstrings_stats[i];
1372                 if (s->mib_reg == -1)
1373                         continue;
1374
1375                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1376                 p = (char *)priv + s->stat_offset;
1377
1378                 if (s->sizeof_stat == sizeof(u64))
1379                         *(u64 *)p += val;
1380                 else
1381                         *(u32 *)p += val;
1382         }
1383
1384         /* also empty unused mib counters to make sure mib counter
1385          * overflow interrupt is cleared */
1386         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1387                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1388 }
1389
1390 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1391 {
1392         struct bcm_enet_priv *priv;
1393
1394         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1395         mutex_lock(&priv->mib_update_lock);
1396         update_mib_counters(priv);
1397         mutex_unlock(&priv->mib_update_lock);
1398
1399         /* reenable mib interrupt */
1400         if (netif_running(priv->net_dev))
1401                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1402 }
1403
1404 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1405                                        struct ethtool_stats *stats,
1406                                        u64 *data)
1407 {
1408         struct bcm_enet_priv *priv;
1409         int i;
1410
1411         priv = netdev_priv(netdev);
1412
1413         mutex_lock(&priv->mib_update_lock);
1414         update_mib_counters(priv);
1415
1416         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1417                 const struct bcm_enet_stats *s;
1418                 char *p;
1419
1420                 s = &bcm_enet_gstrings_stats[i];
1421                 if (s->mib_reg == -1)
1422                         p = (char *)&netdev->stats;
1423                 else
1424                         p = (char *)priv;
1425                 p += s->stat_offset;
1426                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1427                         *(u64 *)p : *(u32 *)p;
1428         }
1429         mutex_unlock(&priv->mib_update_lock);
1430 }
1431
1432 static int bcm_enet_nway_reset(struct net_device *dev)
1433 {
1434         struct bcm_enet_priv *priv;
1435
1436         priv = netdev_priv(dev);
1437         if (priv->has_phy)
1438                 return phy_ethtool_nway_reset(dev);
1439
1440         return -EOPNOTSUPP;
1441 }
1442
1443 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1444                                        struct ethtool_link_ksettings *cmd)
1445 {
1446         struct bcm_enet_priv *priv;
1447         u32 supported, advertising;
1448
1449         priv = netdev_priv(dev);
1450
1451         if (priv->has_phy) {
1452                 if (!dev->phydev)
1453                         return -ENODEV;
1454
1455                 phy_ethtool_ksettings_get(dev->phydev, cmd);
1456
1457                 return 0;
1458         } else {
1459                 cmd->base.autoneg = 0;
1460                 cmd->base.speed = (priv->force_speed_100) ?
1461                         SPEED_100 : SPEED_10;
1462                 cmd->base.duplex = (priv->force_duplex_full) ?
1463                         DUPLEX_FULL : DUPLEX_HALF;
1464                 supported = ADVERTISED_10baseT_Half |
1465                         ADVERTISED_10baseT_Full |
1466                         ADVERTISED_100baseT_Half |
1467                         ADVERTISED_100baseT_Full;
1468                 advertising = 0;
1469                 ethtool_convert_legacy_u32_to_link_mode(
1470                         cmd->link_modes.supported, supported);
1471                 ethtool_convert_legacy_u32_to_link_mode(
1472                         cmd->link_modes.advertising, advertising);
1473                 cmd->base.port = PORT_MII;
1474         }
1475         return 0;
1476 }
1477
1478 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1479                                        const struct ethtool_link_ksettings *cmd)
1480 {
1481         struct bcm_enet_priv *priv;
1482
1483         priv = netdev_priv(dev);
1484         if (priv->has_phy) {
1485                 if (!dev->phydev)
1486                         return -ENODEV;
1487                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1488         } else {
1489
1490                 if (cmd->base.autoneg ||
1491                     (cmd->base.speed != SPEED_100 &&
1492                      cmd->base.speed != SPEED_10) ||
1493                     cmd->base.port != PORT_MII)
1494                         return -EINVAL;
1495
1496                 priv->force_speed_100 =
1497                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1498                 priv->force_duplex_full =
1499                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1500
1501                 if (netif_running(dev))
1502                         bcm_enet_adjust_link(dev);
1503                 return 0;
1504         }
1505 }
1506
1507 static void bcm_enet_get_ringparam(struct net_device *dev,
1508                                    struct ethtool_ringparam *ering)
1509 {
1510         struct bcm_enet_priv *priv;
1511
1512         priv = netdev_priv(dev);
1513
1514         /* rx/tx ring is actually only limited by memory */
1515         ering->rx_max_pending = 8192;
1516         ering->tx_max_pending = 8192;
1517         ering->rx_pending = priv->rx_ring_size;
1518         ering->tx_pending = priv->tx_ring_size;
1519 }
1520
1521 static int bcm_enet_set_ringparam(struct net_device *dev,
1522                                   struct ethtool_ringparam *ering)
1523 {
1524         struct bcm_enet_priv *priv;
1525         int was_running;
1526
1527         priv = netdev_priv(dev);
1528
1529         was_running = 0;
1530         if (netif_running(dev)) {
1531                 bcm_enet_stop(dev);
1532                 was_running = 1;
1533         }
1534
1535         priv->rx_ring_size = ering->rx_pending;
1536         priv->tx_ring_size = ering->tx_pending;
1537
1538         if (was_running) {
1539                 int err;
1540
1541                 err = bcm_enet_open(dev);
1542                 if (err)
1543                         dev_close(dev);
1544                 else
1545                         bcm_enet_set_multicast_list(dev);
1546         }
1547         return 0;
1548 }
1549
1550 static void bcm_enet_get_pauseparam(struct net_device *dev,
1551                                     struct ethtool_pauseparam *ecmd)
1552 {
1553         struct bcm_enet_priv *priv;
1554
1555         priv = netdev_priv(dev);
1556         ecmd->autoneg = priv->pause_auto;
1557         ecmd->rx_pause = priv->pause_rx;
1558         ecmd->tx_pause = priv->pause_tx;
1559 }
1560
1561 static int bcm_enet_set_pauseparam(struct net_device *dev,
1562                                    struct ethtool_pauseparam *ecmd)
1563 {
1564         struct bcm_enet_priv *priv;
1565
1566         priv = netdev_priv(dev);
1567
1568         if (priv->has_phy) {
1569                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1570                         /* asymetric pause mode not supported,
1571                          * actually possible but integrated PHY has RO
1572                          * asym_pause bit */
1573                         return -EINVAL;
1574                 }
1575         } else {
1576                 /* no pause autoneg on direct mii connection */
1577                 if (ecmd->autoneg)
1578                         return -EINVAL;
1579         }
1580
1581         priv->pause_auto = ecmd->autoneg;
1582         priv->pause_rx = ecmd->rx_pause;
1583         priv->pause_tx = ecmd->tx_pause;
1584
1585         return 0;
1586 }
1587
1588 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1589         .get_strings            = bcm_enet_get_strings,
1590         .get_sset_count         = bcm_enet_get_sset_count,
1591         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1592         .nway_reset             = bcm_enet_nway_reset,
1593         .get_drvinfo            = bcm_enet_get_drvinfo,
1594         .get_link               = ethtool_op_get_link,
1595         .get_ringparam          = bcm_enet_get_ringparam,
1596         .set_ringparam          = bcm_enet_set_ringparam,
1597         .get_pauseparam         = bcm_enet_get_pauseparam,
1598         .set_pauseparam         = bcm_enet_set_pauseparam,
1599         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1600         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1601 };
1602
1603 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1604 {
1605         struct bcm_enet_priv *priv;
1606
1607         priv = netdev_priv(dev);
1608         if (priv->has_phy) {
1609                 if (!dev->phydev)
1610                         return -ENODEV;
1611                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1612         } else {
1613                 struct mii_if_info mii;
1614
1615                 mii.dev = dev;
1616                 mii.mdio_read = bcm_enet_mdio_read_mii;
1617                 mii.mdio_write = bcm_enet_mdio_write_mii;
1618                 mii.phy_id = 0;
1619                 mii.phy_id_mask = 0x3f;
1620                 mii.reg_num_mask = 0x1f;
1621                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1622         }
1623 }
1624
1625 /*
1626  * adjust mtu, can't be called while device is running
1627  */
1628 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1629 {
1630         struct bcm_enet_priv *priv = netdev_priv(dev);
1631         int actual_mtu = new_mtu;
1632
1633         if (netif_running(dev))
1634                 return -EBUSY;
1635
1636         /* add ethernet header + vlan tag size */
1637         actual_mtu += VLAN_ETH_HLEN;
1638
1639         /*
1640          * setup maximum size before we get overflow mark in
1641          * descriptor, note that this will not prevent reception of
1642          * big frames, they will be split into multiple buffers
1643          * anyway
1644          */
1645         priv->hw_mtu = actual_mtu;
1646
1647         /*
1648          * align rx buffer size to dma burst len, account FCS since
1649          * it's appended
1650          */
1651         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1652                                   priv->dma_maxburst * 4);
1653
1654         dev->mtu = new_mtu;
1655         return 0;
1656 }
1657
1658 /*
1659  * preinit hardware to allow mii operation while device is down
1660  */
1661 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1662 {
1663         u32 val;
1664         int limit;
1665
1666         /* make sure mac is disabled */
1667         bcm_enet_disable_mac(priv);
1668
1669         /* soft reset mac */
1670         val = ENET_CTL_SRESET_MASK;
1671         enet_writel(priv, val, ENET_CTL_REG);
1672         wmb();
1673
1674         limit = 1000;
1675         do {
1676                 val = enet_readl(priv, ENET_CTL_REG);
1677                 if (!(val & ENET_CTL_SRESET_MASK))
1678                         break;
1679                 udelay(1);
1680         } while (limit--);
1681
1682         /* select correct mii interface */
1683         val = enet_readl(priv, ENET_CTL_REG);
1684         if (priv->use_external_mii)
1685                 val |= ENET_CTL_EPHYSEL_MASK;
1686         else
1687                 val &= ~ENET_CTL_EPHYSEL_MASK;
1688         enet_writel(priv, val, ENET_CTL_REG);
1689
1690         /* turn on mdc clock */
1691         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1692                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1693
1694         /* set mib counters to self-clear when read */
1695         val = enet_readl(priv, ENET_MIBCTL_REG);
1696         val |= ENET_MIBCTL_RDCLEAR_MASK;
1697         enet_writel(priv, val, ENET_MIBCTL_REG);
1698 }
1699
1700 static const struct net_device_ops bcm_enet_ops = {
1701         .ndo_open               = bcm_enet_open,
1702         .ndo_stop               = bcm_enet_stop,
1703         .ndo_start_xmit         = bcm_enet_start_xmit,
1704         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1705         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1706         .ndo_do_ioctl           = bcm_enet_ioctl,
1707         .ndo_change_mtu         = bcm_enet_change_mtu,
1708 };
1709
1710 /*
1711  * allocate netdevice, request register memory and register device.
1712  */
1713 static int bcm_enet_probe(struct platform_device *pdev)
1714 {
1715         struct bcm_enet_priv *priv;
1716         struct net_device *dev;
1717         struct bcm63xx_enet_platform_data *pd;
1718         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1719         struct mii_bus *bus;
1720         int i, ret;
1721
1722         if (!bcm_enet_shared_base[0])
1723                 return -EPROBE_DEFER;
1724
1725         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1726         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1727         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1728         if (!res_irq || !res_irq_rx || !res_irq_tx)
1729                 return -ENODEV;
1730
1731         ret = 0;
1732         dev = alloc_etherdev(sizeof(*priv));
1733         if (!dev)
1734                 return -ENOMEM;
1735         priv = netdev_priv(dev);
1736
1737         priv->enet_is_sw = false;
1738         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1739
1740         ret = bcm_enet_change_mtu(dev, dev->mtu);
1741         if (ret)
1742                 goto out;
1743
1744         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1745         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1746         if (IS_ERR(priv->base)) {
1747                 ret = PTR_ERR(priv->base);
1748                 goto out;
1749         }
1750
1751         dev->irq = priv->irq = res_irq->start;
1752         priv->irq_rx = res_irq_rx->start;
1753         priv->irq_tx = res_irq_tx->start;
1754
1755         priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
1756         if (IS_ERR(priv->mac_clk)) {
1757                 ret = PTR_ERR(priv->mac_clk);
1758                 goto out;
1759         }
1760         ret = clk_prepare_enable(priv->mac_clk);
1761         if (ret)
1762                 goto out;
1763
1764         /* initialize default and fetch platform data */
1765         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1766         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1767
1768         pd = dev_get_platdata(&pdev->dev);
1769         if (pd) {
1770                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1771                 priv->has_phy = pd->has_phy;
1772                 priv->phy_id = pd->phy_id;
1773                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1774                 priv->phy_interrupt = pd->phy_interrupt;
1775                 priv->use_external_mii = !pd->use_internal_phy;
1776                 priv->pause_auto = pd->pause_auto;
1777                 priv->pause_rx = pd->pause_rx;
1778                 priv->pause_tx = pd->pause_tx;
1779                 priv->force_duplex_full = pd->force_duplex_full;
1780                 priv->force_speed_100 = pd->force_speed_100;
1781                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1782                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1783                 priv->dma_chan_width = pd->dma_chan_width;
1784                 priv->dma_has_sram = pd->dma_has_sram;
1785                 priv->dma_desc_shift = pd->dma_desc_shift;
1786                 priv->rx_chan = pd->rx_chan;
1787                 priv->tx_chan = pd->tx_chan;
1788         }
1789
1790         if (priv->has_phy && !priv->use_external_mii) {
1791                 /* using internal PHY, enable clock */
1792                 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
1793                 if (IS_ERR(priv->phy_clk)) {
1794                         ret = PTR_ERR(priv->phy_clk);
1795                         priv->phy_clk = NULL;
1796                         goto out_disable_clk_mac;
1797                 }
1798                 ret = clk_prepare_enable(priv->phy_clk);
1799                 if (ret)
1800                         goto out_disable_clk_mac;
1801         }
1802
1803         /* do minimal hardware init to be able to probe mii bus */
1804         bcm_enet_hw_preinit(priv);
1805
1806         /* MII bus registration */
1807         if (priv->has_phy) {
1808
1809                 priv->mii_bus = mdiobus_alloc();
1810                 if (!priv->mii_bus) {
1811                         ret = -ENOMEM;
1812                         goto out_uninit_hw;
1813                 }
1814
1815                 bus = priv->mii_bus;
1816                 bus->name = "bcm63xx_enet MII bus";
1817                 bus->parent = &pdev->dev;
1818                 bus->priv = priv;
1819                 bus->read = bcm_enet_mdio_read_phylib;
1820                 bus->write = bcm_enet_mdio_write_phylib;
1821                 sprintf(bus->id, "%s-%d", pdev->name, pdev->id);
1822
1823                 /* only probe bus where we think the PHY is, because
1824                  * the mdio read operation return 0 instead of 0xffff
1825                  * if a slave is not present on hw */
1826                 bus->phy_mask = ~(1 << priv->phy_id);
1827
1828                 if (priv->has_phy_interrupt)
1829                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1830
1831                 ret = mdiobus_register(bus);
1832                 if (ret) {
1833                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1834                         goto out_free_mdio;
1835                 }
1836         } else {
1837
1838                 /* run platform code to initialize PHY device */
1839                 if (pd && pd->mii_config &&
1840                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1841                                    bcm_enet_mdio_write_mii)) {
1842                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1843                         goto out_uninit_hw;
1844                 }
1845         }
1846
1847         spin_lock_init(&priv->rx_lock);
1848
1849         /* init rx timeout (used for oom) */
1850         timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
1851
1852         /* init the mib update lock&work */
1853         mutex_init(&priv->mib_update_lock);
1854         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1855
1856         /* zero mib counters */
1857         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1858                 enet_writel(priv, 0, ENET_MIB_REG(i));
1859
1860         /* register netdevice */
1861         dev->netdev_ops = &bcm_enet_ops;
1862         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1863
1864         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1865         /* MTU range: 46 - 2028 */
1866         dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1867         dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1868         SET_NETDEV_DEV(dev, &pdev->dev);
1869
1870         ret = register_netdev(dev);
1871         if (ret)
1872                 goto out_unregister_mdio;
1873
1874         netif_carrier_off(dev);
1875         platform_set_drvdata(pdev, dev);
1876         priv->pdev = pdev;
1877         priv->net_dev = dev;
1878
1879         return 0;
1880
1881 out_unregister_mdio:
1882         if (priv->mii_bus)
1883                 mdiobus_unregister(priv->mii_bus);
1884
1885 out_free_mdio:
1886         if (priv->mii_bus)
1887                 mdiobus_free(priv->mii_bus);
1888
1889 out_uninit_hw:
1890         /* turn off mdc clock */
1891         enet_writel(priv, 0, ENET_MIISC_REG);
1892         clk_disable_unprepare(priv->phy_clk);
1893
1894 out_disable_clk_mac:
1895         clk_disable_unprepare(priv->mac_clk);
1896 out:
1897         free_netdev(dev);
1898         return ret;
1899 }
1900
1901
1902 /*
1903  * exit func, stops hardware and unregisters netdevice
1904  */
1905 static int bcm_enet_remove(struct platform_device *pdev)
1906 {
1907         struct bcm_enet_priv *priv;
1908         struct net_device *dev;
1909
1910         /* stop netdevice */
1911         dev = platform_get_drvdata(pdev);
1912         priv = netdev_priv(dev);
1913         unregister_netdev(dev);
1914
1915         /* turn off mdc clock */
1916         enet_writel(priv, 0, ENET_MIISC_REG);
1917
1918         if (priv->has_phy) {
1919                 mdiobus_unregister(priv->mii_bus);
1920                 mdiobus_free(priv->mii_bus);
1921         } else {
1922                 struct bcm63xx_enet_platform_data *pd;
1923
1924                 pd = dev_get_platdata(&pdev->dev);
1925                 if (pd && pd->mii_config)
1926                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1927                                        bcm_enet_mdio_write_mii);
1928         }
1929
1930         /* disable hw block clocks */
1931         clk_disable_unprepare(priv->phy_clk);
1932         clk_disable_unprepare(priv->mac_clk);
1933
1934         free_netdev(dev);
1935         return 0;
1936 }
1937
1938 struct platform_driver bcm63xx_enet_driver = {
1939         .probe  = bcm_enet_probe,
1940         .remove = bcm_enet_remove,
1941         .driver = {
1942                 .name   = "bcm63xx_enet",
1943                 .owner  = THIS_MODULE,
1944         },
1945 };
1946
1947 /*
1948  * switch mii access callbacks
1949  */
1950 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1951                                 int ext, int phy_id, int location)
1952 {
1953         u32 reg;
1954         int ret;
1955
1956         spin_lock_bh(&priv->enetsw_mdio_lock);
1957         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1958
1959         reg = ENETSW_MDIOC_RD_MASK |
1960                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1961                 (location << ENETSW_MDIOC_REG_SHIFT);
1962
1963         if (ext)
1964                 reg |= ENETSW_MDIOC_EXT_MASK;
1965
1966         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1967         udelay(50);
1968         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1969         spin_unlock_bh(&priv->enetsw_mdio_lock);
1970         return ret;
1971 }
1972
1973 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1974                                  int ext, int phy_id, int location,
1975                                  uint16_t data)
1976 {
1977         u32 reg;
1978
1979         spin_lock_bh(&priv->enetsw_mdio_lock);
1980         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1981
1982         reg = ENETSW_MDIOC_WR_MASK |
1983                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1984                 (location << ENETSW_MDIOC_REG_SHIFT);
1985
1986         if (ext)
1987                 reg |= ENETSW_MDIOC_EXT_MASK;
1988
1989         reg |= data;
1990
1991         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1992         udelay(50);
1993         spin_unlock_bh(&priv->enetsw_mdio_lock);
1994 }
1995
1996 static inline int bcm_enet_port_is_rgmii(int portid)
1997 {
1998         return portid >= ENETSW_RGMII_PORT0;
1999 }
2000
2001 /*
2002  * enet sw PHY polling
2003  */
2004 static void swphy_poll_timer(struct timer_list *t)
2005 {
2006         struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll);
2007         unsigned int i;
2008
2009         for (i = 0; i < priv->num_ports; i++) {
2010                 struct bcm63xx_enetsw_port *port;
2011                 int val, j, up, advertise, lpa, speed, duplex, media;
2012                 int external_phy = bcm_enet_port_is_rgmii(i);
2013                 u8 override;
2014
2015                 port = &priv->used_ports[i];
2016                 if (!port->used)
2017                         continue;
2018
2019                 if (port->bypass_link)
2020                         continue;
2021
2022                 /* dummy read to clear */
2023                 for (j = 0; j < 2; j++)
2024                         val = bcmenet_sw_mdio_read(priv, external_phy,
2025                                                    port->phy_id, MII_BMSR);
2026
2027                 if (val == 0xffff)
2028                         continue;
2029
2030                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2031                 if (!(up ^ priv->sw_port_link[i]))
2032                         continue;
2033
2034                 priv->sw_port_link[i] = up;
2035
2036                 /* link changed */
2037                 if (!up) {
2038                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2039                                  port->name);
2040                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2041                                       ENETSW_PORTOV_REG(i));
2042                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2043                                       ENETSW_PTCTRL_TXDIS_MASK,
2044                                       ENETSW_PTCTRL_REG(i));
2045                         continue;
2046                 }
2047
2048                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2049                                                  port->phy_id, MII_ADVERTISE);
2050
2051                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2052                                            MII_LPA);
2053
2054                 /* figure out media and duplex from advertise and LPA values */
2055                 media = mii_nway_result(lpa & advertise);
2056                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2057
2058                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2059                         speed = 100;
2060                 else
2061                         speed = 10;
2062
2063                 if (val & BMSR_ESTATEN) {
2064                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2065                                                 port->phy_id, MII_CTRL1000);
2066
2067                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2068                                                 port->phy_id, MII_STAT1000);
2069
2070                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2071                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2072                                 speed = 1000;
2073                                 duplex = (lpa & LPA_1000FULL);
2074                         }
2075                 }
2076
2077                 dev_info(&priv->pdev->dev,
2078                          "link UP on %s, %dMbps, %s-duplex\n",
2079                          port->name, speed, duplex ? "full" : "half");
2080
2081                 override = ENETSW_PORTOV_ENABLE_MASK |
2082                         ENETSW_PORTOV_LINKUP_MASK;
2083
2084                 if (speed == 1000)
2085                         override |= ENETSW_IMPOV_1000_MASK;
2086                 else if (speed == 100)
2087                         override |= ENETSW_IMPOV_100_MASK;
2088                 if (duplex)
2089                         override |= ENETSW_IMPOV_FDX_MASK;
2090
2091                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2092                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2093         }
2094
2095         priv->swphy_poll.expires = jiffies + HZ;
2096         add_timer(&priv->swphy_poll);
2097 }
2098
2099 /*
2100  * open callback, allocate dma rings & buffers and start rx operation
2101  */
2102 static int bcm_enetsw_open(struct net_device *dev)
2103 {
2104         struct bcm_enet_priv *priv;
2105         struct device *kdev;
2106         int i, ret;
2107         unsigned int size;
2108         void *p;
2109         u32 val;
2110
2111         priv = netdev_priv(dev);
2112         kdev = &priv->pdev->dev;
2113
2114         /* mask all interrupts and request them */
2115         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2116         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2117
2118         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2119                           0, dev->name, dev);
2120         if (ret)
2121                 goto out_freeirq;
2122
2123         if (priv->irq_tx != -1) {
2124                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2125                                   0, dev->name, dev);
2126                 if (ret)
2127                         goto out_freeirq_rx;
2128         }
2129
2130         /* allocate rx dma ring */
2131         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2132         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2133         if (!p) {
2134                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2135                 ret = -ENOMEM;
2136                 goto out_freeirq_tx;
2137         }
2138
2139         priv->rx_desc_alloc_size = size;
2140         priv->rx_desc_cpu = p;
2141
2142         /* allocate tx dma ring */
2143         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2144         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2145         if (!p) {
2146                 dev_err(kdev, "cannot allocate tx ring\n");
2147                 ret = -ENOMEM;
2148                 goto out_free_rx_ring;
2149         }
2150
2151         priv->tx_desc_alloc_size = size;
2152         priv->tx_desc_cpu = p;
2153
2154         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
2155                                GFP_KERNEL);
2156         if (!priv->tx_skb) {
2157                 dev_err(kdev, "cannot allocate rx skb queue\n");
2158                 ret = -ENOMEM;
2159                 goto out_free_tx_ring;
2160         }
2161
2162         priv->tx_desc_count = priv->tx_ring_size;
2163         priv->tx_dirty_desc = 0;
2164         priv->tx_curr_desc = 0;
2165         spin_lock_init(&priv->tx_lock);
2166
2167         /* init & fill rx ring with skbs */
2168         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
2169                                GFP_KERNEL);
2170         if (!priv->rx_skb) {
2171                 dev_err(kdev, "cannot allocate rx skb queue\n");
2172                 ret = -ENOMEM;
2173                 goto out_free_tx_skb;
2174         }
2175
2176         priv->rx_desc_count = 0;
2177         priv->rx_dirty_desc = 0;
2178         priv->rx_curr_desc = 0;
2179
2180         /* disable all ports */
2181         for (i = 0; i < priv->num_ports; i++) {
2182                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2183                               ENETSW_PORTOV_REG(i));
2184                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2185                               ENETSW_PTCTRL_TXDIS_MASK,
2186                               ENETSW_PTCTRL_REG(i));
2187
2188                 priv->sw_port_link[i] = 0;
2189         }
2190
2191         /* reset mib */
2192         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2193         val |= ENETSW_GMCR_RST_MIB_MASK;
2194         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2195         mdelay(1);
2196         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2197         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2198         mdelay(1);
2199
2200         /* force CPU port state */
2201         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2202         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2203         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2204
2205         /* enable switch forward engine */
2206         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2207         val |= ENETSW_SWMODE_FWD_EN_MASK;
2208         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2209
2210         /* enable jumbo on all ports */
2211         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2212         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2213
2214         /* initialize flow control buffer allocation */
2215         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2216                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2217
2218         if (bcm_enet_refill_rx(dev)) {
2219                 dev_err(kdev, "cannot allocate rx skb queue\n");
2220                 ret = -ENOMEM;
2221                 goto out;
2222         }
2223
2224         /* write rx & tx ring addresses */
2225         enet_dmas_writel(priv, priv->rx_desc_dma,
2226                          ENETDMAS_RSTART_REG, priv->rx_chan);
2227         enet_dmas_writel(priv, priv->tx_desc_dma,
2228                          ENETDMAS_RSTART_REG, priv->tx_chan);
2229
2230         /* clear remaining state ram for rx & tx channel */
2231         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2232         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2233         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2234         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2235         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2236         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2237
2238         /* set dma maximum burst len */
2239         enet_dmac_writel(priv, priv->dma_maxburst,
2240                          ENETDMAC_MAXBURST, priv->rx_chan);
2241         enet_dmac_writel(priv, priv->dma_maxburst,
2242                          ENETDMAC_MAXBURST, priv->tx_chan);
2243
2244         /* set flow control low/high threshold to 1/3 / 2/3 */
2245         val = priv->rx_ring_size / 3;
2246         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2247         val = (priv->rx_ring_size * 2) / 3;
2248         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2249
2250         /* all set, enable mac and interrupts, start dma engine and
2251          * kick rx dma channel
2252          */
2253         wmb();
2254         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2255         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2256                          ENETDMAC_CHANCFG, priv->rx_chan);
2257
2258         /* watch "packet transferred" interrupt in rx and tx */
2259         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2260                          ENETDMAC_IR, priv->rx_chan);
2261         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2262                          ENETDMAC_IR, priv->tx_chan);
2263
2264         /* make sure we enable napi before rx interrupt  */
2265         napi_enable(&priv->napi);
2266
2267         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2268                          ENETDMAC_IRMASK, priv->rx_chan);
2269         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2270                          ENETDMAC_IRMASK, priv->tx_chan);
2271
2272         netif_carrier_on(dev);
2273         netif_start_queue(dev);
2274
2275         /* apply override config for bypass_link ports here. */
2276         for (i = 0; i < priv->num_ports; i++) {
2277                 struct bcm63xx_enetsw_port *port;
2278                 u8 override;
2279                 port = &priv->used_ports[i];
2280                 if (!port->used)
2281                         continue;
2282
2283                 if (!port->bypass_link)
2284                         continue;
2285
2286                 override = ENETSW_PORTOV_ENABLE_MASK |
2287                         ENETSW_PORTOV_LINKUP_MASK;
2288
2289                 switch (port->force_speed) {
2290                 case 1000:
2291                         override |= ENETSW_IMPOV_1000_MASK;
2292                         break;
2293                 case 100:
2294                         override |= ENETSW_IMPOV_100_MASK;
2295                         break;
2296                 case 10:
2297                         break;
2298                 default:
2299                         pr_warn("invalid forced speed on port %s: assume 10\n",
2300                                port->name);
2301                         break;
2302                 }
2303
2304                 if (port->force_duplex_full)
2305                         override |= ENETSW_IMPOV_FDX_MASK;
2306
2307
2308                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2309                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2310         }
2311
2312         /* start phy polling timer */
2313         timer_setup(&priv->swphy_poll, swphy_poll_timer, 0);
2314         mod_timer(&priv->swphy_poll, jiffies);
2315         return 0;
2316
2317 out:
2318         for (i = 0; i < priv->rx_ring_size; i++) {
2319                 struct bcm_enet_desc *desc;
2320
2321                 if (!priv->rx_skb[i])
2322                         continue;
2323
2324                 desc = &priv->rx_desc_cpu[i];
2325                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2326                                  DMA_FROM_DEVICE);
2327                 kfree_skb(priv->rx_skb[i]);
2328         }
2329         kfree(priv->rx_skb);
2330
2331 out_free_tx_skb:
2332         kfree(priv->tx_skb);
2333
2334 out_free_tx_ring:
2335         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2336                           priv->tx_desc_cpu, priv->tx_desc_dma);
2337
2338 out_free_rx_ring:
2339         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2340                           priv->rx_desc_cpu, priv->rx_desc_dma);
2341
2342 out_freeirq_tx:
2343         if (priv->irq_tx != -1)
2344                 free_irq(priv->irq_tx, dev);
2345
2346 out_freeirq_rx:
2347         free_irq(priv->irq_rx, dev);
2348
2349 out_freeirq:
2350         return ret;
2351 }
2352
2353 /* stop callback */
2354 static int bcm_enetsw_stop(struct net_device *dev)
2355 {
2356         struct bcm_enet_priv *priv;
2357         struct device *kdev;
2358         int i;
2359
2360         priv = netdev_priv(dev);
2361         kdev = &priv->pdev->dev;
2362
2363         del_timer_sync(&priv->swphy_poll);
2364         netif_stop_queue(dev);
2365         napi_disable(&priv->napi);
2366         del_timer_sync(&priv->rx_timeout);
2367
2368         /* mask all interrupts */
2369         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2370         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2371
2372         /* disable dma & mac */
2373         bcm_enet_disable_dma(priv, priv->tx_chan);
2374         bcm_enet_disable_dma(priv, priv->rx_chan);
2375
2376         /* force reclaim of all tx buffers */
2377         bcm_enet_tx_reclaim(dev, 1);
2378
2379         /* free the rx skb ring */
2380         for (i = 0; i < priv->rx_ring_size; i++) {
2381                 struct bcm_enet_desc *desc;
2382
2383                 if (!priv->rx_skb[i])
2384                         continue;
2385
2386                 desc = &priv->rx_desc_cpu[i];
2387                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2388                                  DMA_FROM_DEVICE);
2389                 kfree_skb(priv->rx_skb[i]);
2390         }
2391
2392         /* free remaining allocated memory */
2393         kfree(priv->rx_skb);
2394         kfree(priv->tx_skb);
2395         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2396                           priv->rx_desc_cpu, priv->rx_desc_dma);
2397         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2398                           priv->tx_desc_cpu, priv->tx_desc_dma);
2399         if (priv->irq_tx != -1)
2400                 free_irq(priv->irq_tx, dev);
2401         free_irq(priv->irq_rx, dev);
2402
2403         return 0;
2404 }
2405
2406 /* try to sort out phy external status by walking the used_port field
2407  * in the bcm_enet_priv structure. in case the phy address is not
2408  * assigned to any physical port on the switch, assume it is external
2409  * (and yell at the user).
2410  */
2411 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2412 {
2413         int i;
2414
2415         for (i = 0; i < priv->num_ports; ++i) {
2416                 if (!priv->used_ports[i].used)
2417                         continue;
2418                 if (priv->used_ports[i].phy_id == phy_id)
2419                         return bcm_enet_port_is_rgmii(i);
2420         }
2421
2422         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2423                     phy_id);
2424         return 1;
2425 }
2426
2427 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2428  * external/internal status of the given phy_id first.
2429  */
2430 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2431                                     int location)
2432 {
2433         struct bcm_enet_priv *priv;
2434
2435         priv = netdev_priv(dev);
2436         return bcmenet_sw_mdio_read(priv,
2437                                     bcm_enetsw_phy_is_external(priv, phy_id),
2438                                     phy_id, location);
2439 }
2440
2441 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2442  * external/internal status of the given phy_id first.
2443  */
2444 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2445                                       int location,
2446                                       int val)
2447 {
2448         struct bcm_enet_priv *priv;
2449
2450         priv = netdev_priv(dev);
2451         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2452                               phy_id, location, val);
2453 }
2454
2455 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2456 {
2457         struct mii_if_info mii;
2458
2459         mii.dev = dev;
2460         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2461         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2462         mii.phy_id = 0;
2463         mii.phy_id_mask = 0x3f;
2464         mii.reg_num_mask = 0x1f;
2465         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2466
2467 }
2468
2469 static const struct net_device_ops bcm_enetsw_ops = {
2470         .ndo_open               = bcm_enetsw_open,
2471         .ndo_stop               = bcm_enetsw_stop,
2472         .ndo_start_xmit         = bcm_enet_start_xmit,
2473         .ndo_change_mtu         = bcm_enet_change_mtu,
2474         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2475 };
2476
2477
2478 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2479         { "rx_packets", DEV_STAT(rx_packets), -1 },
2480         { "tx_packets", DEV_STAT(tx_packets), -1 },
2481         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2482         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2483         { "rx_errors", DEV_STAT(rx_errors), -1 },
2484         { "tx_errors", DEV_STAT(tx_errors), -1 },
2485         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2486         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2487
2488         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2489         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2490         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2491         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2492         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2493         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2494         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2495         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2496         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2497         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2498           ETHSW_MIB_RX_1024_1522 },
2499         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2500           ETHSW_MIB_RX_1523_2047 },
2501         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2502           ETHSW_MIB_RX_2048_4095 },
2503         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2504           ETHSW_MIB_RX_4096_8191 },
2505         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2506           ETHSW_MIB_RX_8192_9728 },
2507         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2508         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2509         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2510         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2511         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2512
2513         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2514         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2515         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2516         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2517         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2518         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2519
2520 };
2521
2522 #define BCM_ENETSW_STATS_LEN    \
2523         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2524
2525 static void bcm_enetsw_get_strings(struct net_device *netdev,
2526                                    u32 stringset, u8 *data)
2527 {
2528         int i;
2529
2530         switch (stringset) {
2531         case ETH_SS_STATS:
2532                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2533                         memcpy(data + i * ETH_GSTRING_LEN,
2534                                bcm_enetsw_gstrings_stats[i].stat_string,
2535                                ETH_GSTRING_LEN);
2536                 }
2537                 break;
2538         }
2539 }
2540
2541 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2542                                      int string_set)
2543 {
2544         switch (string_set) {
2545         case ETH_SS_STATS:
2546                 return BCM_ENETSW_STATS_LEN;
2547         default:
2548                 return -EINVAL;
2549         }
2550 }
2551
2552 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2553                                    struct ethtool_drvinfo *drvinfo)
2554 {
2555         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2556         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2557         strncpy(drvinfo->fw_version, "N/A", 32);
2558         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2559 }
2560
2561 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2562                                          struct ethtool_stats *stats,
2563                                          u64 *data)
2564 {
2565         struct bcm_enet_priv *priv;
2566         int i;
2567
2568         priv = netdev_priv(netdev);
2569
2570         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2571                 const struct bcm_enet_stats *s;
2572                 u32 lo, hi;
2573                 char *p;
2574                 int reg;
2575
2576                 s = &bcm_enetsw_gstrings_stats[i];
2577
2578                 reg = s->mib_reg;
2579                 if (reg == -1)
2580                         continue;
2581
2582                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2583                 p = (char *)priv + s->stat_offset;
2584
2585                 if (s->sizeof_stat == sizeof(u64)) {
2586                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2587                         *(u64 *)p = ((u64)hi << 32 | lo);
2588                 } else {
2589                         *(u32 *)p = lo;
2590                 }
2591         }
2592
2593         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2594                 const struct bcm_enet_stats *s;
2595                 char *p;
2596
2597                 s = &bcm_enetsw_gstrings_stats[i];
2598
2599                 if (s->mib_reg == -1)
2600                         p = (char *)&netdev->stats + s->stat_offset;
2601                 else
2602                         p = (char *)priv + s->stat_offset;
2603
2604                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2605                         *(u64 *)p : *(u32 *)p;
2606         }
2607 }
2608
2609 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2610                                      struct ethtool_ringparam *ering)
2611 {
2612         struct bcm_enet_priv *priv;
2613
2614         priv = netdev_priv(dev);
2615
2616         /* rx/tx ring is actually only limited by memory */
2617         ering->rx_max_pending = 8192;
2618         ering->tx_max_pending = 8192;
2619         ering->rx_mini_max_pending = 0;
2620         ering->rx_jumbo_max_pending = 0;
2621         ering->rx_pending = priv->rx_ring_size;
2622         ering->tx_pending = priv->tx_ring_size;
2623 }
2624
2625 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2626                                     struct ethtool_ringparam *ering)
2627 {
2628         struct bcm_enet_priv *priv;
2629         int was_running;
2630
2631         priv = netdev_priv(dev);
2632
2633         was_running = 0;
2634         if (netif_running(dev)) {
2635                 bcm_enetsw_stop(dev);
2636                 was_running = 1;
2637         }
2638
2639         priv->rx_ring_size = ering->rx_pending;
2640         priv->tx_ring_size = ering->tx_pending;
2641
2642         if (was_running) {
2643                 int err;
2644
2645                 err = bcm_enetsw_open(dev);
2646                 if (err)
2647                         dev_close(dev);
2648         }
2649         return 0;
2650 }
2651
2652 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2653         .get_strings            = bcm_enetsw_get_strings,
2654         .get_sset_count         = bcm_enetsw_get_sset_count,
2655         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2656         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2657         .get_ringparam          = bcm_enetsw_get_ringparam,
2658         .set_ringparam          = bcm_enetsw_set_ringparam,
2659 };
2660
2661 /* allocate netdevice, request register memory and register device. */
2662 static int bcm_enetsw_probe(struct platform_device *pdev)
2663 {
2664         struct bcm_enet_priv *priv;
2665         struct net_device *dev;
2666         struct bcm63xx_enetsw_platform_data *pd;
2667         struct resource *res_mem;
2668         int ret, irq_rx, irq_tx;
2669
2670         if (!bcm_enet_shared_base[0])
2671                 return -EPROBE_DEFER;
2672
2673         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2674         irq_rx = platform_get_irq(pdev, 0);
2675         irq_tx = platform_get_irq(pdev, 1);
2676         if (!res_mem || irq_rx < 0)
2677                 return -ENODEV;
2678
2679         ret = 0;
2680         dev = alloc_etherdev(sizeof(*priv));
2681         if (!dev)
2682                 return -ENOMEM;
2683         priv = netdev_priv(dev);
2684         memset(priv, 0, sizeof(*priv));
2685
2686         /* initialize default and fetch platform data */
2687         priv->enet_is_sw = true;
2688         priv->irq_rx = irq_rx;
2689         priv->irq_tx = irq_tx;
2690         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2691         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2692         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2693
2694         pd = dev_get_platdata(&pdev->dev);
2695         if (pd) {
2696                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2697                 memcpy(priv->used_ports, pd->used_ports,
2698                        sizeof(pd->used_ports));
2699                 priv->num_ports = pd->num_ports;
2700                 priv->dma_has_sram = pd->dma_has_sram;
2701                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2702                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2703                 priv->dma_chan_width = pd->dma_chan_width;
2704         }
2705
2706         ret = bcm_enet_change_mtu(dev, dev->mtu);
2707         if (ret)
2708                 goto out;
2709
2710         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
2711         if (IS_ERR(priv->base)) {
2712                 ret = PTR_ERR(priv->base);
2713                 goto out;
2714         }
2715
2716         priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
2717         if (IS_ERR(priv->mac_clk)) {
2718                 ret = PTR_ERR(priv->mac_clk);
2719                 goto out;
2720         }
2721         ret = clk_prepare_enable(priv->mac_clk);
2722         if (ret)
2723                 goto out;
2724
2725         priv->rx_chan = 0;
2726         priv->tx_chan = 1;
2727         spin_lock_init(&priv->rx_lock);
2728
2729         /* init rx timeout (used for oom) */
2730         timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
2731
2732         /* register netdevice */
2733         dev->netdev_ops = &bcm_enetsw_ops;
2734         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2735         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2736         SET_NETDEV_DEV(dev, &pdev->dev);
2737
2738         spin_lock_init(&priv->enetsw_mdio_lock);
2739
2740         ret = register_netdev(dev);
2741         if (ret)
2742                 goto out_disable_clk;
2743
2744         netif_carrier_off(dev);
2745         platform_set_drvdata(pdev, dev);
2746         priv->pdev = pdev;
2747         priv->net_dev = dev;
2748
2749         return 0;
2750
2751 out_disable_clk:
2752         clk_disable_unprepare(priv->mac_clk);
2753 out:
2754         free_netdev(dev);
2755         return ret;
2756 }
2757
2758
2759 /* exit func, stops hardware and unregisters netdevice */
2760 static int bcm_enetsw_remove(struct platform_device *pdev)
2761 {
2762         struct bcm_enet_priv *priv;
2763         struct net_device *dev;
2764
2765         /* stop netdevice */
2766         dev = platform_get_drvdata(pdev);
2767         priv = netdev_priv(dev);
2768         unregister_netdev(dev);
2769
2770         clk_disable_unprepare(priv->mac_clk);
2771
2772         free_netdev(dev);
2773         return 0;
2774 }
2775
2776 struct platform_driver bcm63xx_enetsw_driver = {
2777         .probe  = bcm_enetsw_probe,
2778         .remove = bcm_enetsw_remove,
2779         .driver = {
2780                 .name   = "bcm63xx_enetsw",
2781                 .owner  = THIS_MODULE,
2782         },
2783 };
2784
2785 /* reserve & remap memory space shared between all macs */
2786 static int bcm_enet_shared_probe(struct platform_device *pdev)
2787 {
2788         struct resource *res;
2789         void __iomem *p[3];
2790         unsigned int i;
2791
2792         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2793
2794         for (i = 0; i < 3; i++) {
2795                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2796                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2797                 if (IS_ERR(p[i]))
2798                         return PTR_ERR(p[i]);
2799         }
2800
2801         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2802
2803         return 0;
2804 }
2805
2806 static int bcm_enet_shared_remove(struct platform_device *pdev)
2807 {
2808         return 0;
2809 }
2810
2811 /* this "shared" driver is needed because both macs share a single
2812  * address space
2813  */
2814 struct platform_driver bcm63xx_enet_shared_driver = {
2815         .probe  = bcm_enet_shared_probe,
2816         .remove = bcm_enet_shared_remove,
2817         .driver = {
2818                 .name   = "bcm63xx_enet_shared",
2819                 .owner  = THIS_MODULE,
2820         },
2821 };
2822
2823 static struct platform_driver * const drivers[] = {
2824         &bcm63xx_enet_shared_driver,
2825         &bcm63xx_enet_driver,
2826         &bcm63xx_enetsw_driver,
2827 };
2828
2829 /* entry point */
2830 static int __init bcm_enet_init(void)
2831 {
2832         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2833 }
2834
2835 static void __exit bcm_enet_exit(void)
2836 {
2837         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2838 }
2839
2840
2841 module_init(bcm_enet_init);
2842 module_exit(bcm_enet_exit);
2843
2844 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2845 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2846 MODULE_LICENSE("GPL");