drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete_done(napi, rx_work_done);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static netdev_tx_t
 575 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 576 {
 577         struct bcm_enet_priv *priv;
 578         struct bcm_enet_desc *desc;
 579         u32 len_stat;
 580         netdev_tx_t ret;
 581
 582         priv = netdev_priv(dev);
 583
 584         /* lock against tx reclaim */
 585         spin_lock(&priv->tx_lock);
 586
 587         /* make sure  the tx hw queue  is not full,  should not happen
 588          * since we stop queue before it's the case */
 589         if (unlikely(!priv->tx_desc_count)) {
 590                 netif_stop_queue(dev);
 591                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 592                         "available?\n");
 593                 ret = NETDEV_TX_BUSY;
 594                 goto out_unlock;
 595         }
 596
 597         /* pad small packets sent on a switch device */
 598         if (priv->enet_is_sw && skb->len < 64) {
 599                 int needed = 64 - skb->len;
 600                 char *data;
 601
 602                 if (unlikely(skb_tailroom(skb) < needed)) {
 603                         struct sk_buff *nskb;
 604
 605                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 606                         if (!nskb) {
 607                                 ret = NETDEV_TX_BUSY;
 608                                 goto out_unlock;
 609                         }
 610                         dev_kfree_skb(skb);
 611                         skb = nskb;
 612                 }
 613                 data = skb_put_zero(skb, needed);
 614         }
 615
 616         /* point to the next available desc */
 617         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 618         priv->tx_skb[priv->tx_curr_desc] = skb;
 619
 620         /* fill descriptor */
 621         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 622                                        DMA_TO_DEVICE);
 623
 624         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 625         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 626                 DMADESC_APPEND_CRC |
 627                 DMADESC_OWNER_MASK;
 628
 629         priv->tx_curr_desc++;
 630         if (priv->tx_curr_desc == priv->tx_ring_size) {
 631                 priv->tx_curr_desc = 0;
 632                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 633         }
 634         priv->tx_desc_count--;
 635
 636         /* dma might be already polling, make sure we update desc
 637          * fields in correct order */
 638         wmb();
 639         desc->len_stat = len_stat;
 640         wmb();
 641
 642         /* kick tx dma */
 643         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 644                                  ENETDMAC_CHANCFG, priv->tx_chan);
 645
 646         /* stop queue if no more desc available */
 647         if (!priv->tx_desc_count)
 648                 netif_stop_queue(dev);
 649
 650         dev->stats.tx_bytes += skb->len;
 651         dev->stats.tx_packets++;
 652         ret = NETDEV_TX_OK;
 653
 654 out_unlock:
 655         spin_unlock(&priv->tx_lock);
 656         return ret;
 657 }
 658
 659 /*
 660  * Change the interface's mac address.
 661  */
 662 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 663 {
 664         struct bcm_enet_priv *priv;
 665         struct sockaddr *addr = p;
 666         u32 val;
 667
 668         priv = netdev_priv(dev);
 669         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 670
 671         /* use perfect match register 0 to store my mac address */
 672         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 673                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 674         enet_writel(priv, val, ENET_PML_REG(0));
 675
 676         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 677         val |= ENET_PMH_DATAVALID_MASK;
 678         enet_writel(priv, val, ENET_PMH_REG(0));
 679
 680         return 0;
 681 }
 682
 683 /*
 684  * Change rx mode (promiscuous/allmulti) and update multicast list
 685  */
 686 static void bcm_enet_set_multicast_list(struct net_device *dev)
 687 {
 688         struct bcm_enet_priv *priv;
 689         struct netdev_hw_addr *ha;
 690         u32 val;
 691         int i;
 692
 693         priv = netdev_priv(dev);
 694
 695         val = enet_readl(priv, ENET_RXCFG_REG);
 696
 697         if (dev->flags & IFF_PROMISC)
 698                 val |= ENET_RXCFG_PROMISC_MASK;
 699         else
 700                 val &= ~ENET_RXCFG_PROMISC_MASK;
 701
 702         /* only 3 perfect match registers left, first one is used for
 703          * own mac address */
 704         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 705                 val |= ENET_RXCFG_ALLMCAST_MASK;
 706         else
 707                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 708
 709         /* no need to set perfect match registers if we catch all
 710          * multicast */
 711         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 712                 enet_writel(priv, val, ENET_RXCFG_REG);
 713                 return;
 714         }
 715
 716         i = 0;
 717         netdev_for_each_mc_addr(ha, dev) {
 718                 u8 *dmi_addr;
 719                 u32 tmp;
 720
 721                 if (i == 3)
 722                         break;
 723                 /* update perfect match registers */
 724                 dmi_addr = ha->addr;
 725                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 726                         (dmi_addr[4] << 8) | dmi_addr[5];
 727                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 728
 729                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 730                 tmp |= ENET_PMH_DATAVALID_MASK;
 731                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 732         }
 733
 734         for (; i < 3; i++) {
 735                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 736                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 737         }
 738
 739         enet_writel(priv, val, ENET_RXCFG_REG);
 740 }
 741
 742 /*
 743  * set mac duplex parameters
 744  */
 745 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 746 {
 747         u32 val;
 748
 749         val = enet_readl(priv, ENET_TXCTL_REG);
 750         if (fullduplex)
 751                 val |= ENET_TXCTL_FD_MASK;
 752         else
 753                 val &= ~ENET_TXCTL_FD_MASK;
 754         enet_writel(priv, val, ENET_TXCTL_REG);
 755 }
 756
 757 /*
 758  * set mac flow control parameters
 759  */
 760 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 761 {
 762         u32 val;
 763
 764         /* rx flow control (pause frame handling) */
 765         val = enet_readl(priv, ENET_RXCFG_REG);
 766         if (rx_en)
 767                 val |= ENET_RXCFG_ENFLOW_MASK;
 768         else
 769                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 770         enet_writel(priv, val, ENET_RXCFG_REG);
 771
 772         if (!priv->dma_has_sram)
 773                 return;
 774
 775         /* tx flow control (pause frame generation) */
 776         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 777         if (tx_en)
 778                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 779         else
 780                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 781         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 782 }
 783
 784 /*
 785  * link changed callback (from phylib)
 786  */
 787 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 788 {
 789         struct bcm_enet_priv *priv;
 790         struct phy_device *phydev;
 791         int status_changed;
 792
 793         priv = netdev_priv(dev);
 794         phydev = dev->phydev;
 795         status_changed = 0;
 796
 797         if (priv->old_link != phydev->link) {
 798                 status_changed = 1;
 799                 priv->old_link = phydev->link;
 800         }
 801
 802         /* reflect duplex change in mac configuration */
 803         if (phydev->link && phydev->duplex != priv->old_duplex) {
 804                 bcm_enet_set_duplex(priv,
 805                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 806                 status_changed = 1;
 807                 priv->old_duplex = phydev->duplex;
 808         }
 809
 810         /* enable flow control if remote advertise it (trust phylib to
 811          * check that duplex is full */
 812         if (phydev->link && phydev->pause != priv->old_pause) {
 813                 int rx_pause_en, tx_pause_en;
 814
 815                 if (phydev->pause) {
 816                         /* pause was advertised by lpa and us */
 817                         rx_pause_en = 1;
 818                         tx_pause_en = 1;
 819                 } else if (!priv->pause_auto) {
 820                         /* pause setting overridden by user */
 821                         rx_pause_en = priv->pause_rx;
 822                         tx_pause_en = priv->pause_tx;
 823                 } else {
 824                         rx_pause_en = 0;
 825                         tx_pause_en = 0;
 826                 }
 827
 828                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 829                 status_changed = 1;
 830                 priv->old_pause = phydev->pause;
 831         }
 832
 833         if (status_changed) {
 834                 pr_info("%s: link %s", dev->name, phydev->link ?
 835                         "UP" : "DOWN");
 836                 if (phydev->link)
 837                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 838                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 839                                phydev->pause == 1 ? "rx&tx" : "off");
 840
 841                 pr_cont("\n");
 842         }
 843 }
 844
 845 /*
 846  * link changed callback (if phylib is not used)
 847  */
 848 static void bcm_enet_adjust_link(struct net_device *dev)
 849 {
 850         struct bcm_enet_priv *priv;
 851
 852         priv = netdev_priv(dev);
 853         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 854         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 855         netif_carrier_on(dev);
 856
 857         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 858                 dev->name,
 859                 priv->force_speed_100 ? 100 : 10,
 860                 priv->force_duplex_full ? "full" : "half",
 861                 priv->pause_rx ? "rx" : "off",
 862                 priv->pause_tx ? "tx" : "off");
 863 }
 864
 865 /*
 866  * open callback, allocate dma rings & buffers and start rx operation
 867  */
 868 static int bcm_enet_open(struct net_device *dev)
 869 {
 870         struct bcm_enet_priv *priv;
 871         struct sockaddr addr;
 872         struct device *kdev;
 873         struct phy_device *phydev;
 874         int i, ret;
 875         unsigned int size;
 876         char phy_id[MII_BUS_ID_SIZE + 3];
 877         void *p;
 878         u32 val;
 879
 880         priv = netdev_priv(dev);
 881         kdev = &priv->pdev->dev;
 882
 883         if (priv->has_phy) {
 884                 /* connect to PHY */
 885                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 886                          priv->mii_bus->id, priv->phy_id);
 887
 888                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 889                                      PHY_INTERFACE_MODE_MII);
 890
 891                 if (IS_ERR(phydev)) {
 892                         dev_err(kdev, "could not attach to PHY\n");
 893                         return PTR_ERR(phydev);
 894                 }
 895
 896                 /* mask with MAC supported features */
 897                 phydev->supported &= (SUPPORTED_10baseT_Half |
 898                                       SUPPORTED_10baseT_Full |
 899                                       SUPPORTED_100baseT_Half |
 900                                       SUPPORTED_100baseT_Full |
 901                                       SUPPORTED_Autoneg |
 902                                       SUPPORTED_Pause |
 903                                       SUPPORTED_MII);
 904                 phydev->advertising = phydev->supported;
 905
 906                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 907                         phydev->advertising |= SUPPORTED_Pause;
 908                 else
 909                         phydev->advertising &= ~SUPPORTED_Pause;
 910
 911                 phy_attached_info(phydev);
 912
 913                 priv->old_link = 0;
 914                 priv->old_duplex = -1;
 915                 priv->old_pause = -1;
 916         } else {
 917                 phydev = NULL;
 918         }
 919
 920         /* mask all interrupts and request them */
 921         enet_writel(priv, 0, ENET_IRMASK_REG);
 922         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 923         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 924
 925         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 926         if (ret)
 927                 goto out_phy_disconnect;
 928
 929         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 930                           dev->name, dev);
 931         if (ret)
 932                 goto out_freeirq;
 933
 934         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 935                           0, dev->name, dev);
 936         if (ret)
 937                 goto out_freeirq_rx;
 938
 939         /* initialize perfect match registers */
 940         for (i = 0; i < 4; i++) {
 941                 enet_writel(priv, 0, ENET_PML_REG(i));
 942                 enet_writel(priv, 0, ENET_PMH_REG(i));
 943         }
 944
 945         /* write device mac address */
 946         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 947         bcm_enet_set_mac_address(dev, &addr);
 948
 949         /* allocate rx dma ring */
 950         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 951         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 952         if (!p) {
 953                 ret = -ENOMEM;
 954                 goto out_freeirq_tx;
 955         }
 956
 957         priv->rx_desc_alloc_size = size;
 958         priv->rx_desc_cpu = p;
 959
 960         /* allocate tx dma ring */
 961         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 962         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 963         if (!p) {
 964                 ret = -ENOMEM;
 965                 goto out_free_rx_ring;
 966         }
 967
 968         priv->tx_desc_alloc_size = size;
 969         priv->tx_desc_cpu = p;
 970
 971         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 972                                GFP_KERNEL);
 973         if (!priv->tx_skb) {
 974                 ret = -ENOMEM;
 975                 goto out_free_tx_ring;
 976         }
 977
 978         priv->tx_desc_count = priv->tx_ring_size;
 979         priv->tx_dirty_desc = 0;
 980         priv->tx_curr_desc = 0;
 981         spin_lock_init(&priv->tx_lock);
 982
 983         /* init & fill rx ring with skbs */
 984         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 985                                GFP_KERNEL);
 986         if (!priv->rx_skb) {
 987                 ret = -ENOMEM;
 988                 goto out_free_tx_skb;
 989         }
 990
 991         priv->rx_desc_count = 0;
 992         priv->rx_dirty_desc = 0;
 993         priv->rx_curr_desc = 0;
 994
 995         /* initialize flow control buffer allocation */
 996         if (priv->dma_has_sram)
 997                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 998                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 999         else
1000                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1001                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1002
1003         if (bcm_enet_refill_rx(dev)) {
1004                 dev_err(kdev, "cannot allocate rx skb queue\n");
1005                 ret = -ENOMEM;
1006                 goto out;
1007         }
1008
1009         /* write rx & tx ring addresses */
1010         if (priv->dma_has_sram) {
1011                 enet_dmas_writel(priv, priv->rx_desc_dma,
1012                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1013                 enet_dmas_writel(priv, priv->tx_desc_dma,
1014                          ENETDMAS_RSTART_REG, priv->tx_chan);
1015         } else {
1016                 enet_dmac_writel(priv, priv->rx_desc_dma,
1017                                 ENETDMAC_RSTART, priv->rx_chan);
1018                 enet_dmac_writel(priv, priv->tx_desc_dma,
1019                                 ENETDMAC_RSTART, priv->tx_chan);
1020         }
1021
1022         /* clear remaining state ram for rx & tx channel */
1023         if (priv->dma_has_sram) {
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1028                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1029                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1030         } else {
1031                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1032                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1033         }
1034
1035         /* set max rx/tx length */
1036         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1037         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1038
1039         /* set dma maximum burst len */
1040         enet_dmac_writel(priv, priv->dma_maxburst,
1041                          ENETDMAC_MAXBURST, priv->rx_chan);
1042         enet_dmac_writel(priv, priv->dma_maxburst,
1043                          ENETDMAC_MAXBURST, priv->tx_chan);
1044
1045         /* set correct transmit fifo watermark */
1046         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1047
1048         /* set flow control low/high threshold to 1/3 / 2/3 */
1049         if (priv->dma_has_sram) {
1050                 val = priv->rx_ring_size / 3;
1051                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1052                 val = (priv->rx_ring_size * 2) / 3;
1053                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1054         } else {
1055                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1056                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1057                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1058         }
1059
1060         /* all set, enable mac and interrupts, start dma engine and
1061          * kick rx dma channel */
1062         wmb();
1063         val = enet_readl(priv, ENET_CTL_REG);
1064         val |= ENET_CTL_ENABLE_MASK;
1065         enet_writel(priv, val, ENET_CTL_REG);
1066         if (priv->dma_has_sram)
1067                 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1068         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1069                          ENETDMAC_CHANCFG, priv->rx_chan);
1070
1071         /* watch "mib counters about to overflow" interrupt */
1072         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1073         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1074
1075         /* watch "packet transferred" interrupt in rx and tx */
1076         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1077                          ENETDMAC_IR, priv->rx_chan);
1078         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1079                          ENETDMAC_IR, priv->tx_chan);
1080
1081         /* make sure we enable napi before rx interrupt  */
1082         napi_enable(&priv->napi);
1083
1084         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1085                          ENETDMAC_IRMASK, priv->rx_chan);
1086         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1087                          ENETDMAC_IRMASK, priv->tx_chan);
1088
1089         if (phydev)
1090                 phy_start(phydev);
1091         else
1092                 bcm_enet_adjust_link(dev);
1093
1094         netif_start_queue(dev);
1095         return 0;
1096
1097 out:
1098         for (i = 0; i < priv->rx_ring_size; i++) {
1099                 struct bcm_enet_desc *desc;
1100
1101                 if (!priv->rx_skb[i])
1102                         continue;
1103
1104                 desc = &priv->rx_desc_cpu[i];
1105                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1106                                  DMA_FROM_DEVICE);
1107                 kfree_skb(priv->rx_skb[i]);
1108         }
1109         kfree(priv->rx_skb);
1110
1111 out_free_tx_skb:
1112         kfree(priv->tx_skb);
1113
1114 out_free_tx_ring:
1115         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1116                           priv->tx_desc_cpu, priv->tx_desc_dma);
1117
1118 out_free_rx_ring:
1119         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1120                           priv->rx_desc_cpu, priv->rx_desc_dma);
1121
1122 out_freeirq_tx:
1123         free_irq(priv->irq_tx, dev);
1124
1125 out_freeirq_rx:
1126         free_irq(priv->irq_rx, dev);
1127
1128 out_freeirq:
1129         free_irq(dev->irq, dev);
1130
1131 out_phy_disconnect:
1132         if (phydev)
1133                 phy_disconnect(phydev);
1134
1135         return ret;
1136 }
1137
1138 /*
1139  * disable mac
1140  */
1141 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1142 {
1143         int limit;
1144         u32 val;
1145
1146         val = enet_readl(priv, ENET_CTL_REG);
1147         val |= ENET_CTL_DISABLE_MASK;
1148         enet_writel(priv, val, ENET_CTL_REG);
1149
1150         limit = 1000;
1151         do {
1152                 u32 val;
1153
1154                 val = enet_readl(priv, ENET_CTL_REG);
1155                 if (!(val & ENET_CTL_DISABLE_MASK))
1156                         break;
1157                 udelay(1);
1158         } while (limit--);
1159 }
1160
1161 /*
1162  * disable dma in given channel
1163  */
1164 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1165 {
1166         int limit;
1167
1168         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1169
1170         limit = 1000;
1171         do {
1172                 u32 val;
1173
1174                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1175                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1176                         break;
1177                 udelay(1);
1178         } while (limit--);
1179 }
1180
1181 /*
1182  * stop callback
1183  */
1184 static int bcm_enet_stop(struct net_device *dev)
1185 {
1186         struct bcm_enet_priv *priv;
1187         struct device *kdev;
1188         int i;
1189
1190         priv = netdev_priv(dev);
1191         kdev = &priv->pdev->dev;
1192
1193         netif_stop_queue(dev);
1194         napi_disable(&priv->napi);
1195         if (priv->has_phy)
1196                 phy_stop(dev->phydev);
1197         del_timer_sync(&priv->rx_timeout);
1198
1199         /* mask all interrupts */
1200         enet_writel(priv, 0, ENET_IRMASK_REG);
1201         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1202         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1203
1204         /* make sure no mib update is scheduled */
1205         cancel_work_sync(&priv->mib_update_task);
1206
1207         /* disable dma & mac */
1208         bcm_enet_disable_dma(priv, priv->tx_chan);
1209         bcm_enet_disable_dma(priv, priv->rx_chan);
1210         bcm_enet_disable_mac(priv);
1211
1212         /* force reclaim of all tx buffers */
1213         bcm_enet_tx_reclaim(dev, 1);
1214
1215         /* free the rx skb ring */
1216         for (i = 0; i < priv->rx_ring_size; i++) {
1217                 struct bcm_enet_desc *desc;
1218
1219                 if (!priv->rx_skb[i])
1220                         continue;
1221
1222                 desc = &priv->rx_desc_cpu[i];
1223                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1224                                  DMA_FROM_DEVICE);
1225                 kfree_skb(priv->rx_skb[i]);
1226         }
1227
1228         /* free remaining allocated memory */
1229         kfree(priv->rx_skb);
1230         kfree(priv->tx_skb);
1231         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1232                           priv->rx_desc_cpu, priv->rx_desc_dma);
1233         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1234                           priv->tx_desc_cpu, priv->tx_desc_dma);
1235         free_irq(priv->irq_tx, dev);
1236         free_irq(priv->irq_rx, dev);
1237         free_irq(dev->irq, dev);
1238
1239         /* release phy */
1240         if (priv->has_phy)
1241                 phy_disconnect(dev->phydev);
1242
1243         return 0;
1244 }
1245
1246 /*
1247  * ethtool callbacks
1248  */
1249 struct bcm_enet_stats {
1250         char stat_string[ETH_GSTRING_LEN];
1251         int sizeof_stat;
1252         int stat_offset;
1253         int mib_reg;
1254 };
1255
1256 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1257                      offsetof(struct bcm_enet_priv, m)
1258 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1259                      offsetof(struct net_device_stats, m)
1260
1261 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1262         { "rx_packets", DEV_STAT(rx_packets), -1 },
1263         { "tx_packets", DEV_STAT(tx_packets), -1 },
1264         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1265         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1266         { "rx_errors", DEV_STAT(rx_errors), -1 },
1267         { "tx_errors", DEV_STAT(tx_errors), -1 },
1268         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1269         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1270
1271         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1272         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1273         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1274         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1275         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1276         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1277         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1278         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1279         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1280         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1281         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1282         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1283         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1284         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1285         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1286         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1287         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1288         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1289         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1290         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1291         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1292
1293         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1294         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1295         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1296         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1297         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1298         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1299         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1300         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1301         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1302         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1303         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1304         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1305         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1306         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1307         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1308         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1309         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1310         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1311         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1312         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1313         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1314         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1315
1316 };
1317
1318 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1319
1320 static const u32 unused_mib_regs[] = {
1321         ETH_MIB_TX_ALL_OCTETS,
1322         ETH_MIB_TX_ALL_PKTS,
1323         ETH_MIB_RX_ALL_OCTETS,
1324         ETH_MIB_RX_ALL_PKTS,
1325 };
1326
1327
1328 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1329                                  struct ethtool_drvinfo *drvinfo)
1330 {
1331         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1332         strlcpy(drvinfo->version, bcm_enet_driver_version,
1333                 sizeof(drvinfo->version));
1334         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1335         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1336 }
1337
1338 static int bcm_enet_get_sset_count(struct net_device *netdev,
1339                                         int string_set)
1340 {
1341         switch (string_set) {
1342         case ETH_SS_STATS:
1343                 return BCM_ENET_STATS_LEN;
1344         default:
1345                 return -EINVAL;
1346         }
1347 }
1348
1349 static void bcm_enet_get_strings(struct net_device *netdev,
1350                                  u32 stringset, u8 *data)
1351 {
1352         int i;
1353
1354         switch (stringset) {
1355         case ETH_SS_STATS:
1356                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1357                         memcpy(data + i * ETH_GSTRING_LEN,
1358                                bcm_enet_gstrings_stats[i].stat_string,
1359                                ETH_GSTRING_LEN);
1360                 }
1361                 break;
1362         }
1363 }
1364
1365 static void update_mib_counters(struct bcm_enet_priv *priv)
1366 {
1367         int i;
1368
1369         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1370                 const struct bcm_enet_stats *s;
1371                 u32 val;
1372                 char *p;
1373
1374                 s = &bcm_enet_gstrings_stats[i];
1375                 if (s->mib_reg == -1)
1376                         continue;
1377
1378                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1379                 p = (char *)priv + s->stat_offset;
1380
1381                 if (s->sizeof_stat == sizeof(u64))
1382                         *(u64 *)p += val;
1383                 else
1384                         *(u32 *)p += val;
1385         }
1386
1387         /* also empty unused mib counters to make sure mib counter
1388          * overflow interrupt is cleared */
1389         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1390                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1391 }
1392
1393 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1394 {
1395         struct bcm_enet_priv *priv;
1396
1397         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1398         mutex_lock(&priv->mib_update_lock);
1399         update_mib_counters(priv);
1400         mutex_unlock(&priv->mib_update_lock);
1401
1402         /* reenable mib interrupt */
1403         if (netif_running(priv->net_dev))
1404                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1405 }
1406
1407 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1408                                        struct ethtool_stats *stats,
1409                                        u64 *data)
1410 {
1411         struct bcm_enet_priv *priv;
1412         int i;
1413
1414         priv = netdev_priv(netdev);
1415
1416         mutex_lock(&priv->mib_update_lock);
1417         update_mib_counters(priv);
1418
1419         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1420                 const struct bcm_enet_stats *s;
1421                 char *p;
1422
1423                 s = &bcm_enet_gstrings_stats[i];
1424                 if (s->mib_reg == -1)
1425                         p = (char *)&netdev->stats;
1426                 else
1427                         p = (char *)priv;
1428                 p += s->stat_offset;
1429                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1430                         *(u64 *)p : *(u32 *)p;
1431         }
1432         mutex_unlock(&priv->mib_update_lock);
1433 }
1434
1435 static int bcm_enet_nway_reset(struct net_device *dev)
1436 {
1437         struct bcm_enet_priv *priv;
1438
1439         priv = netdev_priv(dev);
1440         if (priv->has_phy)
1441                 return phy_ethtool_nway_reset(dev);
1442
1443         return -EOPNOTSUPP;
1444 }
1445
1446 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1447                                        struct ethtool_link_ksettings *cmd)
1448 {
1449         struct bcm_enet_priv *priv;
1450         u32 supported, advertising;
1451
1452         priv = netdev_priv(dev);
1453
1454         if (priv->has_phy) {
1455                 if (!dev->phydev)
1456                         return -ENODEV;
1457
1458                 phy_ethtool_ksettings_get(dev->phydev, cmd);
1459
1460                 return 0;
1461         } else {
1462                 cmd->base.autoneg = 0;
1463                 cmd->base.speed = (priv->force_speed_100) ?
1464                         SPEED_100 : SPEED_10;
1465                 cmd->base.duplex = (priv->force_duplex_full) ?
1466                         DUPLEX_FULL : DUPLEX_HALF;
1467                 supported = ADVERTISED_10baseT_Half |
1468                         ADVERTISED_10baseT_Full |
1469                         ADVERTISED_100baseT_Half |
1470                         ADVERTISED_100baseT_Full;
1471                 advertising = 0;
1472                 ethtool_convert_legacy_u32_to_link_mode(
1473                         cmd->link_modes.supported, supported);
1474                 ethtool_convert_legacy_u32_to_link_mode(
1475                         cmd->link_modes.advertising, advertising);
1476                 cmd->base.port = PORT_MII;
1477         }
1478         return 0;
1479 }
1480
1481 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1482                                        const struct ethtool_link_ksettings *cmd)
1483 {
1484         struct bcm_enet_priv *priv;
1485
1486         priv = netdev_priv(dev);
1487         if (priv->has_phy) {
1488                 if (!dev->phydev)
1489                         return -ENODEV;
1490                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1491         } else {
1492
1493                 if (cmd->base.autoneg ||
1494                     (cmd->base.speed != SPEED_100 &&
1495                      cmd->base.speed != SPEED_10) ||
1496                     cmd->base.port != PORT_MII)
1497                         return -EINVAL;
1498
1499                 priv->force_speed_100 =
1500                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1501                 priv->force_duplex_full =
1502                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1503
1504                 if (netif_running(dev))
1505                         bcm_enet_adjust_link(dev);
1506                 return 0;
1507         }
1508 }
1509
1510 static void bcm_enet_get_ringparam(struct net_device *dev,
1511                                    struct ethtool_ringparam *ering)
1512 {
1513         struct bcm_enet_priv *priv;
1514
1515         priv = netdev_priv(dev);
1516
1517         /* rx/tx ring is actually only limited by memory */
1518         ering->rx_max_pending = 8192;
1519         ering->tx_max_pending = 8192;
1520         ering->rx_pending = priv->rx_ring_size;
1521         ering->tx_pending = priv->tx_ring_size;
1522 }
1523
1524 static int bcm_enet_set_ringparam(struct net_device *dev,
1525                                   struct ethtool_ringparam *ering)
1526 {
1527         struct bcm_enet_priv *priv;
1528         int was_running;
1529
1530         priv = netdev_priv(dev);
1531
1532         was_running = 0;
1533         if (netif_running(dev)) {
1534                 bcm_enet_stop(dev);
1535                 was_running = 1;
1536         }
1537
1538         priv->rx_ring_size = ering->rx_pending;
1539         priv->tx_ring_size = ering->tx_pending;
1540
1541         if (was_running) {
1542                 int err;
1543
1544                 err = bcm_enet_open(dev);
1545                 if (err)
1546                         dev_close(dev);
1547                 else
1548                         bcm_enet_set_multicast_list(dev);
1549         }
1550         return 0;
1551 }
1552
1553 static void bcm_enet_get_pauseparam(struct net_device *dev,
1554                                     struct ethtool_pauseparam *ecmd)
1555 {
1556         struct bcm_enet_priv *priv;
1557
1558         priv = netdev_priv(dev);
1559         ecmd->autoneg = priv->pause_auto;
1560         ecmd->rx_pause = priv->pause_rx;
1561         ecmd->tx_pause = priv->pause_tx;
1562 }
1563
1564 static int bcm_enet_set_pauseparam(struct net_device *dev,
1565                                    struct ethtool_pauseparam *ecmd)
1566 {
1567         struct bcm_enet_priv *priv;
1568
1569         priv = netdev_priv(dev);
1570
1571         if (priv->has_phy) {
1572                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1573                         /* asymetric pause mode not supported,
1574                          * actually possible but integrated PHY has RO
1575                          * asym_pause bit */
1576                         return -EINVAL;
1577                 }
1578         } else {
1579                 /* no pause autoneg on direct mii connection */
1580                 if (ecmd->autoneg)
1581                         return -EINVAL;
1582         }
1583
1584         priv->pause_auto = ecmd->autoneg;
1585         priv->pause_rx = ecmd->rx_pause;
1586         priv->pause_tx = ecmd->tx_pause;
1587
1588         return 0;
1589 }
1590
1591 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1592         .get_strings            = bcm_enet_get_strings,
1593         .get_sset_count         = bcm_enet_get_sset_count,
1594         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1595         .nway_reset             = bcm_enet_nway_reset,
1596         .get_drvinfo            = bcm_enet_get_drvinfo,
1597         .get_link               = ethtool_op_get_link,
1598         .get_ringparam          = bcm_enet_get_ringparam,
1599         .set_ringparam          = bcm_enet_set_ringparam,
1600         .get_pauseparam         = bcm_enet_get_pauseparam,
1601         .set_pauseparam         = bcm_enet_set_pauseparam,
1602         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1603         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1604 };
1605
1606 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1607 {
1608         struct bcm_enet_priv *priv;
1609
1610         priv = netdev_priv(dev);
1611         if (priv->has_phy) {
1612                 if (!dev->phydev)
1613                         return -ENODEV;
1614                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1615         } else {
1616                 struct mii_if_info mii;
1617
1618                 mii.dev = dev;
1619                 mii.mdio_read = bcm_enet_mdio_read_mii;
1620                 mii.mdio_write = bcm_enet_mdio_write_mii;
1621                 mii.phy_id = 0;
1622                 mii.phy_id_mask = 0x3f;
1623                 mii.reg_num_mask = 0x1f;
1624                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1625         }
1626 }
1627
1628 /*
1629  * adjust mtu, can't be called while device is running
1630  */
1631 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1632 {
1633         struct bcm_enet_priv *priv = netdev_priv(dev);
1634         int actual_mtu = new_mtu;
1635
1636         if (netif_running(dev))
1637                 return -EBUSY;
1638
1639         /* add ethernet header + vlan tag size */
1640         actual_mtu += VLAN_ETH_HLEN;
1641
1642         /*
1643          * setup maximum size before we get overflow mark in
1644          * descriptor, note that this will not prevent reception of
1645          * big frames, they will be split into multiple buffers
1646          * anyway
1647          */
1648         priv->hw_mtu = actual_mtu;
1649
1650         /*
1651          * align rx buffer size to dma burst len, account FCS since
1652          * it's appended
1653          */
1654         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1655                                   priv->dma_maxburst * 4);
1656
1657         dev->mtu = new_mtu;
1658         return 0;
1659 }
1660
1661 /*
1662  * preinit hardware to allow mii operation while device is down
1663  */
1664 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1665 {
1666         u32 val;
1667         int limit;
1668
1669         /* make sure mac is disabled */
1670         bcm_enet_disable_mac(priv);
1671
1672         /* soft reset mac */
1673         val = ENET_CTL_SRESET_MASK;
1674         enet_writel(priv, val, ENET_CTL_REG);
1675         wmb();
1676
1677         limit = 1000;
1678         do {
1679                 val = enet_readl(priv, ENET_CTL_REG);
1680                 if (!(val & ENET_CTL_SRESET_MASK))
1681                         break;
1682                 udelay(1);
1683         } while (limit--);
1684
1685         /* select correct mii interface */
1686         val = enet_readl(priv, ENET_CTL_REG);
1687         if (priv->use_external_mii)
1688                 val |= ENET_CTL_EPHYSEL_MASK;
1689         else
1690                 val &= ~ENET_CTL_EPHYSEL_MASK;
1691         enet_writel(priv, val, ENET_CTL_REG);
1692
1693         /* turn on mdc clock */
1694         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1695                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1696
1697         /* set mib counters to self-clear when read */
1698         val = enet_readl(priv, ENET_MIBCTL_REG);
1699         val |= ENET_MIBCTL_RDCLEAR_MASK;
1700         enet_writel(priv, val, ENET_MIBCTL_REG);
1701 }
1702
1703 static const struct net_device_ops bcm_enet_ops = {
1704         .ndo_open               = bcm_enet_open,
1705         .ndo_stop               = bcm_enet_stop,
1706         .ndo_start_xmit         = bcm_enet_start_xmit,
1707         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1708         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1709         .ndo_do_ioctl           = bcm_enet_ioctl,
1710         .ndo_change_mtu         = bcm_enet_change_mtu,
1711 };
1712
1713 /*
1714  * allocate netdevice, request register memory and register device.
1715  */
1716 static int bcm_enet_probe(struct platform_device *pdev)
1717 {
1718         struct bcm_enet_priv *priv;
1719         struct net_device *dev;
1720         struct bcm63xx_enet_platform_data *pd;
1721         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1722         struct mii_bus *bus;
1723         const char *clk_name;
1724         int i, ret;
1725
1726         /* stop if shared driver failed, assume driver->probe will be
1727          * called in the same order we register devices (correct ?) */
1728         if (!bcm_enet_shared_base[0])
1729                 return -ENODEV;
1730
1731         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1732         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1733         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1734         if (!res_irq || !res_irq_rx || !res_irq_tx)
1735                 return -ENODEV;
1736
1737         ret = 0;
1738         dev = alloc_etherdev(sizeof(*priv));
1739         if (!dev)
1740                 return -ENOMEM;
1741         priv = netdev_priv(dev);
1742
1743         priv->enet_is_sw = false;
1744         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1745
1746         ret = bcm_enet_change_mtu(dev, dev->mtu);
1747         if (ret)
1748                 goto out;
1749
1750         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1751         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1752         if (IS_ERR(priv->base)) {
1753                 ret = PTR_ERR(priv->base);
1754                 goto out;
1755         }
1756
1757         dev->irq = priv->irq = res_irq->start;
1758         priv->irq_rx = res_irq_rx->start;
1759         priv->irq_tx = res_irq_tx->start;
1760         priv->mac_id = pdev->id;
1761
1762         /* get rx & tx dma channel id for this mac */
1763         if (priv->mac_id == 0) {
1764                 priv->rx_chan = 0;
1765                 priv->tx_chan = 1;
1766                 clk_name = "enet0";
1767         } else {
1768                 priv->rx_chan = 2;
1769                 priv->tx_chan = 3;
1770                 clk_name = "enet1";
1771         }
1772
1773         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1774         if (IS_ERR(priv->mac_clk)) {
1775                 ret = PTR_ERR(priv->mac_clk);
1776                 goto out;
1777         }
1778         ret = clk_prepare_enable(priv->mac_clk);
1779         if (ret)
1780                 goto out_put_clk_mac;
1781
1782         /* initialize default and fetch platform data */
1783         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1784         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1785
1786         pd = dev_get_platdata(&pdev->dev);
1787         if (pd) {
1788                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1789                 priv->has_phy = pd->has_phy;
1790                 priv->phy_id = pd->phy_id;
1791                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1792                 priv->phy_interrupt = pd->phy_interrupt;
1793                 priv->use_external_mii = !pd->use_internal_phy;
1794                 priv->pause_auto = pd->pause_auto;
1795                 priv->pause_rx = pd->pause_rx;
1796                 priv->pause_tx = pd->pause_tx;
1797                 priv->force_duplex_full = pd->force_duplex_full;
1798                 priv->force_speed_100 = pd->force_speed_100;
1799                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1800                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1801                 priv->dma_chan_width = pd->dma_chan_width;
1802                 priv->dma_has_sram = pd->dma_has_sram;
1803                 priv->dma_desc_shift = pd->dma_desc_shift;
1804         }
1805
1806         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1807                 /* using internal PHY, enable clock */
1808                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1809                 if (IS_ERR(priv->phy_clk)) {
1810                         ret = PTR_ERR(priv->phy_clk);
1811                         priv->phy_clk = NULL;
1812                         goto out_disable_clk_mac;
1813                 }
1814                 ret = clk_prepare_enable(priv->phy_clk);
1815                 if (ret)
1816                         goto out_put_clk_phy;
1817         }
1818
1819         /* do minimal hardware init to be able to probe mii bus */
1820         bcm_enet_hw_preinit(priv);
1821
1822         /* MII bus registration */
1823         if (priv->has_phy) {
1824
1825                 priv->mii_bus = mdiobus_alloc();
1826                 if (!priv->mii_bus) {
1827                         ret = -ENOMEM;
1828                         goto out_uninit_hw;
1829                 }
1830
1831                 bus = priv->mii_bus;
1832                 bus->name = "bcm63xx_enet MII bus";
1833                 bus->parent = &pdev->dev;
1834                 bus->priv = priv;
1835                 bus->read = bcm_enet_mdio_read_phylib;
1836                 bus->write = bcm_enet_mdio_write_phylib;
1837                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1838
1839                 /* only probe bus where we think the PHY is, because
1840                  * the mdio read operation return 0 instead of 0xffff
1841                  * if a slave is not present on hw */
1842                 bus->phy_mask = ~(1 << priv->phy_id);
1843
1844                 if (priv->has_phy_interrupt)
1845                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1846
1847                 ret = mdiobus_register(bus);
1848                 if (ret) {
1849                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1850                         goto out_free_mdio;
1851                 }
1852         } else {
1853
1854                 /* run platform code to initialize PHY device */
1855                 if (pd && pd->mii_config &&
1856                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1857                                    bcm_enet_mdio_write_mii)) {
1858                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1859                         goto out_uninit_hw;
1860                 }
1861         }
1862
1863         spin_lock_init(&priv->rx_lock);
1864
1865         /* init rx timeout (used for oom) */
1866         init_timer(&priv->rx_timeout);
1867         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1868         priv->rx_timeout.data = (unsigned long)dev;
1869
1870         /* init the mib update lock&work */
1871         mutex_init(&priv->mib_update_lock);
1872         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1873
1874         /* zero mib counters */
1875         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1876                 enet_writel(priv, 0, ENET_MIB_REG(i));
1877
1878         /* register netdevice */
1879         dev->netdev_ops = &bcm_enet_ops;
1880         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1881
1882         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1883         /* MTU range: 46 - 2028 */
1884         dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1885         dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1886         SET_NETDEV_DEV(dev, &pdev->dev);
1887
1888         ret = register_netdev(dev);
1889         if (ret)
1890                 goto out_unregister_mdio;
1891
1892         netif_carrier_off(dev);
1893         platform_set_drvdata(pdev, dev);
1894         priv->pdev = pdev;
1895         priv->net_dev = dev;
1896
1897         return 0;
1898
1899 out_unregister_mdio:
1900         if (priv->mii_bus)
1901                 mdiobus_unregister(priv->mii_bus);
1902
1903 out_free_mdio:
1904         if (priv->mii_bus)
1905                 mdiobus_free(priv->mii_bus);
1906
1907 out_uninit_hw:
1908         /* turn off mdc clock */
1909         enet_writel(priv, 0, ENET_MIISC_REG);
1910         if (priv->phy_clk)
1911                 clk_disable_unprepare(priv->phy_clk);
1912
1913 out_put_clk_phy:
1914         if (priv->phy_clk)
1915                 clk_put(priv->phy_clk);
1916
1917 out_disable_clk_mac:
1918         clk_disable_unprepare(priv->mac_clk);
1919 out_put_clk_mac:
1920         clk_put(priv->mac_clk);
1921 out:
1922         free_netdev(dev);
1923         return ret;
1924 }
1925
1926
1927 /*
1928  * exit func, stops hardware and unregisters netdevice
1929  */
1930 static int bcm_enet_remove(struct platform_device *pdev)
1931 {
1932         struct bcm_enet_priv *priv;
1933         struct net_device *dev;
1934
1935         /* stop netdevice */
1936         dev = platform_get_drvdata(pdev);
1937         priv = netdev_priv(dev);
1938         unregister_netdev(dev);
1939
1940         /* turn off mdc clock */
1941         enet_writel(priv, 0, ENET_MIISC_REG);
1942
1943         if (priv->has_phy) {
1944                 mdiobus_unregister(priv->mii_bus);
1945                 mdiobus_free(priv->mii_bus);
1946         } else {
1947                 struct bcm63xx_enet_platform_data *pd;
1948
1949                 pd = dev_get_platdata(&pdev->dev);
1950                 if (pd && pd->mii_config)
1951                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1952                                        bcm_enet_mdio_write_mii);
1953         }
1954
1955         /* disable hw block clocks */
1956         if (priv->phy_clk) {
1957                 clk_disable_unprepare(priv->phy_clk);
1958                 clk_put(priv->phy_clk);
1959         }
1960         clk_disable_unprepare(priv->mac_clk);
1961         clk_put(priv->mac_clk);
1962
1963         free_netdev(dev);
1964         return 0;
1965 }
1966
1967 struct platform_driver bcm63xx_enet_driver = {
1968         .probe  = bcm_enet_probe,
1969         .remove = bcm_enet_remove,
1970         .driver = {
1971                 .name   = "bcm63xx_enet",
1972                 .owner  = THIS_MODULE,
1973         },
1974 };
1975
1976 /*
1977  * switch mii access callbacks
1978  */
1979 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1980                                 int ext, int phy_id, int location)
1981 {
1982         u32 reg;
1983         int ret;
1984
1985         spin_lock_bh(&priv->enetsw_mdio_lock);
1986         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1987
1988         reg = ENETSW_MDIOC_RD_MASK |
1989                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1990                 (location << ENETSW_MDIOC_REG_SHIFT);
1991
1992         if (ext)
1993                 reg |= ENETSW_MDIOC_EXT_MASK;
1994
1995         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1996         udelay(50);
1997         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1998         spin_unlock_bh(&priv->enetsw_mdio_lock);
1999         return ret;
2000 }
2001
2002 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2003                                  int ext, int phy_id, int location,
2004                                  uint16_t data)
2005 {
2006         u32 reg;
2007
2008         spin_lock_bh(&priv->enetsw_mdio_lock);
2009         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2010
2011         reg = ENETSW_MDIOC_WR_MASK |
2012                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2013                 (location << ENETSW_MDIOC_REG_SHIFT);
2014
2015         if (ext)
2016                 reg |= ENETSW_MDIOC_EXT_MASK;
2017
2018         reg |= data;
2019
2020         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2021         udelay(50);
2022         spin_unlock_bh(&priv->enetsw_mdio_lock);
2023 }
2024
2025 static inline int bcm_enet_port_is_rgmii(int portid)
2026 {
2027         return portid >= ENETSW_RGMII_PORT0;
2028 }
2029
2030 /*
2031  * enet sw PHY polling
2032  */
2033 static void swphy_poll_timer(unsigned long data)
2034 {
2035         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2036         unsigned int i;
2037
2038         for (i = 0; i < priv->num_ports; i++) {
2039                 struct bcm63xx_enetsw_port *port;
2040                 int val, j, up, advertise, lpa, speed, duplex, media;
2041                 int external_phy = bcm_enet_port_is_rgmii(i);
2042                 u8 override;
2043
2044                 port = &priv->used_ports[i];
2045                 if (!port->used)
2046                         continue;
2047
2048                 if (port->bypass_link)
2049                         continue;
2050
2051                 /* dummy read to clear */
2052                 for (j = 0; j < 2; j++)
2053                         val = bcmenet_sw_mdio_read(priv, external_phy,
2054                                                    port->phy_id, MII_BMSR);
2055
2056                 if (val == 0xffff)
2057                         continue;
2058
2059                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2060                 if (!(up ^ priv->sw_port_link[i]))
2061                         continue;
2062
2063                 priv->sw_port_link[i] = up;
2064
2065                 /* link changed */
2066                 if (!up) {
2067                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2068                                  port->name);
2069                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2070                                       ENETSW_PORTOV_REG(i));
2071                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2072                                       ENETSW_PTCTRL_TXDIS_MASK,
2073                                       ENETSW_PTCTRL_REG(i));
2074                         continue;
2075                 }
2076
2077                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2078                                                  port->phy_id, MII_ADVERTISE);
2079
2080                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2081                                            MII_LPA);
2082
2083                 /* figure out media and duplex from advertise and LPA values */
2084                 media = mii_nway_result(lpa & advertise);
2085                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2086
2087                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2088                         speed = 100;
2089                 else
2090                         speed = 10;
2091
2092                 if (val & BMSR_ESTATEN) {
2093                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2094                                                 port->phy_id, MII_CTRL1000);
2095
2096                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2097                                                 port->phy_id, MII_STAT1000);
2098
2099                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2100                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2101                                 speed = 1000;
2102                                 duplex = (lpa & LPA_1000FULL);
2103                         }
2104                 }
2105
2106                 dev_info(&priv->pdev->dev,
2107                          "link UP on %s, %dMbps, %s-duplex\n",
2108                          port->name, speed, duplex ? "full" : "half");
2109
2110                 override = ENETSW_PORTOV_ENABLE_MASK |
2111                         ENETSW_PORTOV_LINKUP_MASK;
2112
2113                 if (speed == 1000)
2114                         override |= ENETSW_IMPOV_1000_MASK;
2115                 else if (speed == 100)
2116                         override |= ENETSW_IMPOV_100_MASK;
2117                 if (duplex)
2118                         override |= ENETSW_IMPOV_FDX_MASK;
2119
2120                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2121                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2122         }
2123
2124         priv->swphy_poll.expires = jiffies + HZ;
2125         add_timer(&priv->swphy_poll);
2126 }
2127
2128 /*
2129  * open callback, allocate dma rings & buffers and start rx operation
2130  */
2131 static int bcm_enetsw_open(struct net_device *dev)
2132 {
2133         struct bcm_enet_priv *priv;
2134         struct device *kdev;
2135         int i, ret;
2136         unsigned int size;
2137         void *p;
2138         u32 val;
2139
2140         priv = netdev_priv(dev);
2141         kdev = &priv->pdev->dev;
2142
2143         /* mask all interrupts and request them */
2144         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2145         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2146
2147         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2148                           0, dev->name, dev);
2149         if (ret)
2150                 goto out_freeirq;
2151
2152         if (priv->irq_tx != -1) {
2153                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2154                                   0, dev->name, dev);
2155                 if (ret)
2156                         goto out_freeirq_rx;
2157         }
2158
2159         /* allocate rx dma ring */
2160         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2161         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2162         if (!p) {
2163                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2164                 ret = -ENOMEM;
2165                 goto out_freeirq_tx;
2166         }
2167
2168         memset(p, 0, size);
2169         priv->rx_desc_alloc_size = size;
2170         priv->rx_desc_cpu = p;
2171
2172         /* allocate tx dma ring */
2173         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2174         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2175         if (!p) {
2176                 dev_err(kdev, "cannot allocate tx ring\n");
2177                 ret = -ENOMEM;
2178                 goto out_free_rx_ring;
2179         }
2180
2181         memset(p, 0, size);
2182         priv->tx_desc_alloc_size = size;
2183         priv->tx_desc_cpu = p;
2184
2185         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2186                                GFP_KERNEL);
2187         if (!priv->tx_skb) {
2188                 dev_err(kdev, "cannot allocate rx skb queue\n");
2189                 ret = -ENOMEM;
2190                 goto out_free_tx_ring;
2191         }
2192
2193         priv->tx_desc_count = priv->tx_ring_size;
2194         priv->tx_dirty_desc = 0;
2195         priv->tx_curr_desc = 0;
2196         spin_lock_init(&priv->tx_lock);
2197
2198         /* init & fill rx ring with skbs */
2199         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2200                                GFP_KERNEL);
2201         if (!priv->rx_skb) {
2202                 dev_err(kdev, "cannot allocate rx skb queue\n");
2203                 ret = -ENOMEM;
2204                 goto out_free_tx_skb;
2205         }
2206
2207         priv->rx_desc_count = 0;
2208         priv->rx_dirty_desc = 0;
2209         priv->rx_curr_desc = 0;
2210
2211         /* disable all ports */
2212         for (i = 0; i < priv->num_ports; i++) {
2213                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2214                               ENETSW_PORTOV_REG(i));
2215                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2216                               ENETSW_PTCTRL_TXDIS_MASK,
2217                               ENETSW_PTCTRL_REG(i));
2218
2219                 priv->sw_port_link[i] = 0;
2220         }
2221
2222         /* reset mib */
2223         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2224         val |= ENETSW_GMCR_RST_MIB_MASK;
2225         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2226         mdelay(1);
2227         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2228         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2229         mdelay(1);
2230
2231         /* force CPU port state */
2232         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2233         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2234         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2235
2236         /* enable switch forward engine */
2237         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2238         val |= ENETSW_SWMODE_FWD_EN_MASK;
2239         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2240
2241         /* enable jumbo on all ports */
2242         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2243         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2244
2245         /* initialize flow control buffer allocation */
2246         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2247                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2248
2249         if (bcm_enet_refill_rx(dev)) {
2250                 dev_err(kdev, "cannot allocate rx skb queue\n");
2251                 ret = -ENOMEM;
2252                 goto out;
2253         }
2254
2255         /* write rx & tx ring addresses */
2256         enet_dmas_writel(priv, priv->rx_desc_dma,
2257                          ENETDMAS_RSTART_REG, priv->rx_chan);
2258         enet_dmas_writel(priv, priv->tx_desc_dma,
2259                          ENETDMAS_RSTART_REG, priv->tx_chan);
2260
2261         /* clear remaining state ram for rx & tx channel */
2262         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2263         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2264         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2265         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2266         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2267         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2268
2269         /* set dma maximum burst len */
2270         enet_dmac_writel(priv, priv->dma_maxburst,
2271                          ENETDMAC_MAXBURST, priv->rx_chan);
2272         enet_dmac_writel(priv, priv->dma_maxburst,
2273                          ENETDMAC_MAXBURST, priv->tx_chan);
2274
2275         /* set flow control low/high threshold to 1/3 / 2/3 */
2276         val = priv->rx_ring_size / 3;
2277         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2278         val = (priv->rx_ring_size * 2) / 3;
2279         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2280
2281         /* all set, enable mac and interrupts, start dma engine and
2282          * kick rx dma channel
2283          */
2284         wmb();
2285         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2286         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2287                          ENETDMAC_CHANCFG, priv->rx_chan);
2288
2289         /* watch "packet transferred" interrupt in rx and tx */
2290         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2291                          ENETDMAC_IR, priv->rx_chan);
2292         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2293                          ENETDMAC_IR, priv->tx_chan);
2294
2295         /* make sure we enable napi before rx interrupt  */
2296         napi_enable(&priv->napi);
2297
2298         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2299                          ENETDMAC_IRMASK, priv->rx_chan);
2300         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2301                          ENETDMAC_IRMASK, priv->tx_chan);
2302
2303         netif_carrier_on(dev);
2304         netif_start_queue(dev);
2305
2306         /* apply override config for bypass_link ports here. */
2307         for (i = 0; i < priv->num_ports; i++) {
2308                 struct bcm63xx_enetsw_port *port;
2309                 u8 override;
2310                 port = &priv->used_ports[i];
2311                 if (!port->used)
2312                         continue;
2313
2314                 if (!port->bypass_link)
2315                         continue;
2316
2317                 override = ENETSW_PORTOV_ENABLE_MASK |
2318                         ENETSW_PORTOV_LINKUP_MASK;
2319
2320                 switch (port->force_speed) {
2321                 case 1000:
2322                         override |= ENETSW_IMPOV_1000_MASK;
2323                         break;
2324                 case 100:
2325                         override |= ENETSW_IMPOV_100_MASK;
2326                         break;
2327                 case 10:
2328                         break;
2329                 default:
2330                         pr_warn("invalid forced speed on port %s: assume 10\n",
2331                                port->name);
2332                         break;
2333                 }
2334
2335                 if (port->force_duplex_full)
2336                         override |= ENETSW_IMPOV_FDX_MASK;
2337
2338
2339                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2340                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2341         }
2342
2343         /* start phy polling timer */
2344         init_timer(&priv->swphy_poll);
2345         priv->swphy_poll.function = swphy_poll_timer;
2346         priv->swphy_poll.data = (unsigned long)priv;
2347         priv->swphy_poll.expires = jiffies;
2348         add_timer(&priv->swphy_poll);
2349         return 0;
2350
2351 out:
2352         for (i = 0; i < priv->rx_ring_size; i++) {
2353                 struct bcm_enet_desc *desc;
2354
2355                 if (!priv->rx_skb[i])
2356                         continue;
2357
2358                 desc = &priv->rx_desc_cpu[i];
2359                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2360                                  DMA_FROM_DEVICE);
2361                 kfree_skb(priv->rx_skb[i]);
2362         }
2363         kfree(priv->rx_skb);
2364
2365 out_free_tx_skb:
2366         kfree(priv->tx_skb);
2367
2368 out_free_tx_ring:
2369         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2370                           priv->tx_desc_cpu, priv->tx_desc_dma);
2371
2372 out_free_rx_ring:
2373         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2374                           priv->rx_desc_cpu, priv->rx_desc_dma);
2375
2376 out_freeirq_tx:
2377         if (priv->irq_tx != -1)
2378                 free_irq(priv->irq_tx, dev);
2379
2380 out_freeirq_rx:
2381         free_irq(priv->irq_rx, dev);
2382
2383 out_freeirq:
2384         return ret;
2385 }
2386
2387 /* stop callback */
2388 static int bcm_enetsw_stop(struct net_device *dev)
2389 {
2390         struct bcm_enet_priv *priv;
2391         struct device *kdev;
2392         int i;
2393
2394         priv = netdev_priv(dev);
2395         kdev = &priv->pdev->dev;
2396
2397         del_timer_sync(&priv->swphy_poll);
2398         netif_stop_queue(dev);
2399         napi_disable(&priv->napi);
2400         del_timer_sync(&priv->rx_timeout);
2401
2402         /* mask all interrupts */
2403         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2404         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2405
2406         /* disable dma & mac */
2407         bcm_enet_disable_dma(priv, priv->tx_chan);
2408         bcm_enet_disable_dma(priv, priv->rx_chan);
2409
2410         /* force reclaim of all tx buffers */
2411         bcm_enet_tx_reclaim(dev, 1);
2412
2413         /* free the rx skb ring */
2414         for (i = 0; i < priv->rx_ring_size; i++) {
2415                 struct bcm_enet_desc *desc;
2416
2417                 if (!priv->rx_skb[i])
2418                         continue;
2419
2420                 desc = &priv->rx_desc_cpu[i];
2421                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2422                                  DMA_FROM_DEVICE);
2423                 kfree_skb(priv->rx_skb[i]);
2424         }
2425
2426         /* free remaining allocated memory */
2427         kfree(priv->rx_skb);
2428         kfree(priv->tx_skb);
2429         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2430                           priv->rx_desc_cpu, priv->rx_desc_dma);
2431         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2432                           priv->tx_desc_cpu, priv->tx_desc_dma);
2433         if (priv->irq_tx != -1)
2434                 free_irq(priv->irq_tx, dev);
2435         free_irq(priv->irq_rx, dev);
2436
2437         return 0;
2438 }
2439
2440 /* try to sort out phy external status by walking the used_port field
2441  * in the bcm_enet_priv structure. in case the phy address is not
2442  * assigned to any physical port on the switch, assume it is external
2443  * (and yell at the user).
2444  */
2445 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2446 {
2447         int i;
2448
2449         for (i = 0; i < priv->num_ports; ++i) {
2450                 if (!priv->used_ports[i].used)
2451                         continue;
2452                 if (priv->used_ports[i].phy_id == phy_id)
2453                         return bcm_enet_port_is_rgmii(i);
2454         }
2455
2456         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2457                     phy_id);
2458         return 1;
2459 }
2460
2461 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2462  * external/internal status of the given phy_id first.
2463  */
2464 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2465                                     int location)
2466 {
2467         struct bcm_enet_priv *priv;
2468
2469         priv = netdev_priv(dev);
2470         return bcmenet_sw_mdio_read(priv,
2471                                     bcm_enetsw_phy_is_external(priv, phy_id),
2472                                     phy_id, location);
2473 }
2474
2475 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2476  * external/internal status of the given phy_id first.
2477  */
2478 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2479                                       int location,
2480                                       int val)
2481 {
2482         struct bcm_enet_priv *priv;
2483
2484         priv = netdev_priv(dev);
2485         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2486                               phy_id, location, val);
2487 }
2488
2489 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2490 {
2491         struct mii_if_info mii;
2492
2493         mii.dev = dev;
2494         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2495         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2496         mii.phy_id = 0;
2497         mii.phy_id_mask = 0x3f;
2498         mii.reg_num_mask = 0x1f;
2499         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2500
2501 }
2502
2503 static const struct net_device_ops bcm_enetsw_ops = {
2504         .ndo_open               = bcm_enetsw_open,
2505         .ndo_stop               = bcm_enetsw_stop,
2506         .ndo_start_xmit         = bcm_enet_start_xmit,
2507         .ndo_change_mtu         = bcm_enet_change_mtu,
2508         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2509 };
2510
2511
2512 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2513         { "rx_packets", DEV_STAT(rx_packets), -1 },
2514         { "tx_packets", DEV_STAT(tx_packets), -1 },
2515         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2516         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2517         { "rx_errors", DEV_STAT(rx_errors), -1 },
2518         { "tx_errors", DEV_STAT(tx_errors), -1 },
2519         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2520         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2521
2522         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2523         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2524         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2525         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2526         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2527         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2528         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2529         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2530         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2531         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2532           ETHSW_MIB_RX_1024_1522 },
2533         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2534           ETHSW_MIB_RX_1523_2047 },
2535         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2536           ETHSW_MIB_RX_2048_4095 },
2537         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2538           ETHSW_MIB_RX_4096_8191 },
2539         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2540           ETHSW_MIB_RX_8192_9728 },
2541         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2542         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2543         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2544         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2545         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2546
2547         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2548         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2549         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2550         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2551         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2552         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2553
2554 };
2555
2556 #define BCM_ENETSW_STATS_LEN    \
2557         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2558
2559 static void bcm_enetsw_get_strings(struct net_device *netdev,
2560                                    u32 stringset, u8 *data)
2561 {
2562         int i;
2563
2564         switch (stringset) {
2565         case ETH_SS_STATS:
2566                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2567                         memcpy(data + i * ETH_GSTRING_LEN,
2568                                bcm_enetsw_gstrings_stats[i].stat_string,
2569                                ETH_GSTRING_LEN);
2570                 }
2571                 break;
2572         }
2573 }
2574
2575 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2576                                      int string_set)
2577 {
2578         switch (string_set) {
2579         case ETH_SS_STATS:
2580                 return BCM_ENETSW_STATS_LEN;
2581         default:
2582                 return -EINVAL;
2583         }
2584 }
2585
2586 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2587                                    struct ethtool_drvinfo *drvinfo)
2588 {
2589         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2590         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2591         strncpy(drvinfo->fw_version, "N/A", 32);
2592         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2593 }
2594
2595 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2596                                          struct ethtool_stats *stats,
2597                                          u64 *data)
2598 {
2599         struct bcm_enet_priv *priv;
2600         int i;
2601
2602         priv = netdev_priv(netdev);
2603
2604         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2605                 const struct bcm_enet_stats *s;
2606                 u32 lo, hi;
2607                 char *p;
2608                 int reg;
2609
2610                 s = &bcm_enetsw_gstrings_stats[i];
2611
2612                 reg = s->mib_reg;
2613                 if (reg == -1)
2614                         continue;
2615
2616                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2617                 p = (char *)priv + s->stat_offset;
2618
2619                 if (s->sizeof_stat == sizeof(u64)) {
2620                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2621                         *(u64 *)p = ((u64)hi << 32 | lo);
2622                 } else {
2623                         *(u32 *)p = lo;
2624                 }
2625         }
2626
2627         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2628                 const struct bcm_enet_stats *s;
2629                 char *p;
2630
2631                 s = &bcm_enetsw_gstrings_stats[i];
2632
2633                 if (s->mib_reg == -1)
2634                         p = (char *)&netdev->stats + s->stat_offset;
2635                 else
2636                         p = (char *)priv + s->stat_offset;
2637
2638                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2639                         *(u64 *)p : *(u32 *)p;
2640         }
2641 }
2642
2643 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2644                                      struct ethtool_ringparam *ering)
2645 {
2646         struct bcm_enet_priv *priv;
2647
2648         priv = netdev_priv(dev);
2649
2650         /* rx/tx ring is actually only limited by memory */
2651         ering->rx_max_pending = 8192;
2652         ering->tx_max_pending = 8192;
2653         ering->rx_mini_max_pending = 0;
2654         ering->rx_jumbo_max_pending = 0;
2655         ering->rx_pending = priv->rx_ring_size;
2656         ering->tx_pending = priv->tx_ring_size;
2657 }
2658
2659 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2660                                     struct ethtool_ringparam *ering)
2661 {
2662         struct bcm_enet_priv *priv;
2663         int was_running;
2664
2665         priv = netdev_priv(dev);
2666
2667         was_running = 0;
2668         if (netif_running(dev)) {
2669                 bcm_enetsw_stop(dev);
2670                 was_running = 1;
2671         }
2672
2673         priv->rx_ring_size = ering->rx_pending;
2674         priv->tx_ring_size = ering->tx_pending;
2675
2676         if (was_running) {
2677                 int err;
2678
2679                 err = bcm_enetsw_open(dev);
2680                 if (err)
2681                         dev_close(dev);
2682         }
2683         return 0;
2684 }
2685
2686 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2687         .get_strings            = bcm_enetsw_get_strings,
2688         .get_sset_count         = bcm_enetsw_get_sset_count,
2689         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2690         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2691         .get_ringparam          = bcm_enetsw_get_ringparam,
2692         .set_ringparam          = bcm_enetsw_set_ringparam,
2693 };
2694
2695 /* allocate netdevice, request register memory and register device. */
2696 static int bcm_enetsw_probe(struct platform_device *pdev)
2697 {
2698         struct bcm_enet_priv *priv;
2699         struct net_device *dev;
2700         struct bcm63xx_enetsw_platform_data *pd;
2701         struct resource *res_mem;
2702         int ret, irq_rx, irq_tx;
2703
2704         /* stop if shared driver failed, assume driver->probe will be
2705          * called in the same order we register devices (correct ?)
2706          */
2707         if (!bcm_enet_shared_base[0])
2708                 return -ENODEV;
2709
2710         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2711         irq_rx = platform_get_irq(pdev, 0);
2712         irq_tx = platform_get_irq(pdev, 1);
2713         if (!res_mem || irq_rx < 0)
2714                 return -ENODEV;
2715
2716         ret = 0;
2717         dev = alloc_etherdev(sizeof(*priv));
2718         if (!dev)
2719                 return -ENOMEM;
2720         priv = netdev_priv(dev);
2721         memset(priv, 0, sizeof(*priv));
2722
2723         /* initialize default and fetch platform data */
2724         priv->enet_is_sw = true;
2725         priv->irq_rx = irq_rx;
2726         priv->irq_tx = irq_tx;
2727         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2728         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2729         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2730
2731         pd = dev_get_platdata(&pdev->dev);
2732         if (pd) {
2733                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2734                 memcpy(priv->used_ports, pd->used_ports,
2735                        sizeof(pd->used_ports));
2736                 priv->num_ports = pd->num_ports;
2737                 priv->dma_has_sram = pd->dma_has_sram;
2738                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2739                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2740                 priv->dma_chan_width = pd->dma_chan_width;
2741         }
2742
2743         ret = bcm_enet_change_mtu(dev, dev->mtu);
2744         if (ret)
2745                 goto out;
2746
2747         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2748                                 "bcm63xx_enetsw")) {
2749                 ret = -EBUSY;
2750                 goto out;
2751         }
2752
2753         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2754         if (priv->base == NULL) {
2755                 ret = -ENOMEM;
2756                 goto out_release_mem;
2757         }
2758
2759         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2760         if (IS_ERR(priv->mac_clk)) {
2761                 ret = PTR_ERR(priv->mac_clk);
2762                 goto out_unmap;
2763         }
2764         ret = clk_prepare_enable(priv->mac_clk);
2765         if (ret)
2766                 goto out_put_clk;
2767
2768         priv->rx_chan = 0;
2769         priv->tx_chan = 1;
2770         spin_lock_init(&priv->rx_lock);
2771
2772         /* init rx timeout (used for oom) */
2773         init_timer(&priv->rx_timeout);
2774         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2775         priv->rx_timeout.data = (unsigned long)dev;
2776
2777         /* register netdevice */
2778         dev->netdev_ops = &bcm_enetsw_ops;
2779         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2780         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2781         SET_NETDEV_DEV(dev, &pdev->dev);
2782
2783         spin_lock_init(&priv->enetsw_mdio_lock);
2784
2785         ret = register_netdev(dev);
2786         if (ret)
2787                 goto out_disable_clk;
2788
2789         netif_carrier_off(dev);
2790         platform_set_drvdata(pdev, dev);
2791         priv->pdev = pdev;
2792         priv->net_dev = dev;
2793
2794         return 0;
2795
2796 out_disable_clk:
2797         clk_disable_unprepare(priv->mac_clk);
2798
2799 out_put_clk:
2800         clk_put(priv->mac_clk);
2801
2802 out_unmap:
2803         iounmap(priv->base);
2804
2805 out_release_mem:
2806         release_mem_region(res_mem->start, resource_size(res_mem));
2807 out:
2808         free_netdev(dev);
2809         return ret;
2810 }
2811
2812
2813 /* exit func, stops hardware and unregisters netdevice */
2814 static int bcm_enetsw_remove(struct platform_device *pdev)
2815 {
2816         struct bcm_enet_priv *priv;
2817         struct net_device *dev;
2818         struct resource *res;
2819
2820         /* stop netdevice */
2821         dev = platform_get_drvdata(pdev);
2822         priv = netdev_priv(dev);
2823         unregister_netdev(dev);
2824
2825         /* release device resources */
2826         iounmap(priv->base);
2827         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2828         release_mem_region(res->start, resource_size(res));
2829
2830         clk_disable_unprepare(priv->mac_clk);
2831         clk_put(priv->mac_clk);
2832
2833         free_netdev(dev);
2834         return 0;
2835 }
2836
2837 struct platform_driver bcm63xx_enetsw_driver = {
2838         .probe  = bcm_enetsw_probe,
2839         .remove = bcm_enetsw_remove,
2840         .driver = {
2841                 .name   = "bcm63xx_enetsw",
2842                 .owner  = THIS_MODULE,
2843         },
2844 };
2845
2846 /* reserve & remap memory space shared between all macs */
2847 static int bcm_enet_shared_probe(struct platform_device *pdev)
2848 {
2849         struct resource *res;
2850         void __iomem *p[3];
2851         unsigned int i;
2852
2853         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2854
2855         for (i = 0; i < 3; i++) {
2856                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2857                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2858                 if (IS_ERR(p[i]))
2859                         return PTR_ERR(p[i]);
2860         }
2861
2862         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2863
2864         return 0;
2865 }
2866
2867 static int bcm_enet_shared_remove(struct platform_device *pdev)
2868 {
2869         return 0;
2870 }
2871
2872 /* this "shared" driver is needed because both macs share a single
2873  * address space
2874  */
2875 struct platform_driver bcm63xx_enet_shared_driver = {
2876         .probe  = bcm_enet_shared_probe,
2877         .remove = bcm_enet_shared_remove,
2878         .driver = {
2879                 .name   = "bcm63xx_enet_shared",
2880                 .owner  = THIS_MODULE,
2881         },
2882 };
2883
2884 static struct platform_driver * const drivers[] = {
2885         &bcm63xx_enet_shared_driver,
2886         &bcm63xx_enet_driver,
2887         &bcm63xx_enetsw_driver,
2888 };
2889
2890 /* entry point */
2891 static int __init bcm_enet_init(void)
2892 {
2893         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2894 }
2895
2896 static void __exit bcm_enet_exit(void)
2897 {
2898         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2899 }
2900
2901
2902 module_init(bcm_enet_init);
2903 module_exit(bcm_enet_exit);
2904
2905 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2906 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2907 MODULE_LICENSE("GPL");