1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <m@bues.ch>
9 * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
11 * Distribute under GPL.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/netdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/mii.h>
23 #include <linux/if_ether.h>
24 #include <linux/if_vlan.h>
25 #include <linux/etherdevice.h>
26 #include <linux/pci.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/ssb/ssb.h>
32 #include <linux/slab.h>
33 #include <linux/phy.h>
35 #include <linux/uaccess.h>
42 #define DRV_MODULE_NAME "b44"
43 #define DRV_DESCRIPTION "Broadcom 44xx/47xx 10/100 PCI ethernet driver"
45 #define B44_DEF_MSG_ENABLE \
55 /* length of time before we decide the hardware is borked,
56 * and dev->tx_timeout() should be called to fix the problem
58 #define B44_TX_TIMEOUT (5 * HZ)
60 /* hardware minimum and maximum for a single frame's data payload */
61 #define B44_MIN_MTU ETH_ZLEN
62 #define B44_MAX_MTU ETH_DATA_LEN
64 #define B44_RX_RING_SIZE 512
65 #define B44_DEF_RX_RING_PENDING 200
66 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
68 #define B44_TX_RING_SIZE 512
69 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
70 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
73 #define TX_RING_GAP(BP) \
74 (B44_TX_RING_SIZE - (BP)->tx_pending)
75 #define TX_BUFFS_AVAIL(BP) \
76 (((BP)->tx_cons <= (BP)->tx_prod) ? \
77 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
78 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
79 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
81 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
82 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
84 /* minimum number of free TX descriptors required to wake up TX process */
85 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
87 /* b44 internal pattern match filter info */
88 #define B44_PATTERN_BASE 0x400
89 #define B44_PATTERN_SIZE 0x80
90 #define B44_PMASK_BASE 0x600
91 #define B44_PMASK_SIZE 0x10
92 #define B44_MAX_PATTERNS 16
93 #define B44_ETHIPV6UDP_HLEN 62
94 #define B44_ETHIPV4UDP_HLEN 42
96 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
97 MODULE_DESCRIPTION(DRV_DESCRIPTION);
98 MODULE_LICENSE("GPL");
100 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
101 module_param(b44_debug, int, 0);
102 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
105 #ifdef CONFIG_B44_PCI
106 static const struct pci_device_id b44_pci_tbl[] = {
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
110 { 0 } /* terminate list with empty entry */
112 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
114 static struct pci_driver b44_pci_driver = {
115 .name = DRV_MODULE_NAME,
116 .id_table = b44_pci_tbl,
118 #endif /* CONFIG_B44_PCI */
120 static const struct ssb_device_id b44_ssb_tbl[] = {
121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
124 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
126 static void b44_halt(struct b44 *);
127 static void b44_init_rings(struct b44 *);
129 #define B44_FULL_RESET 1
130 #define B44_FULL_RESET_SKIP_PHY 2
131 #define B44_PARTIAL_RESET 3
132 #define B44_CHIP_RESET_FULL 4
133 #define B44_CHIP_RESET_PARTIAL 5
135 static void b44_init_hw(struct b44 *, int);
137 static int dma_desc_sync_size;
140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141 #define _B44(x...) # x,
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
148 unsigned long offset,
149 enum dma_data_direction dir)
151 dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
152 dma_desc_sync_size, dir);
155 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 unsigned long offset,
158 enum dma_data_direction dir)
160 dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
161 dma_desc_sync_size, dir);
164 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
166 return ssb_read32(bp->sdev, reg);
169 static inline void bw32(const struct b44 *bp,
170 unsigned long reg, unsigned long val)
172 ssb_write32(bp->sdev, reg, val);
175 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
176 u32 bit, unsigned long timeout, const int clear)
180 for (i = 0; i < timeout; i++) {
181 u32 val = br32(bp, reg);
183 if (clear && !(val & bit))
185 if (!clear && (val & bit))
191 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
192 bit, reg, clear ? "clear" : "set");
199 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
203 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
204 (index << CAM_CTRL_INDEX_SHIFT)));
206 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
208 val = br32(bp, B44_CAM_DATA_LO);
210 data[2] = (val >> 24) & 0xFF;
211 data[3] = (val >> 16) & 0xFF;
212 data[4] = (val >> 8) & 0xFF;
213 data[5] = (val >> 0) & 0xFF;
215 val = br32(bp, B44_CAM_DATA_HI);
217 data[0] = (val >> 8) & 0xFF;
218 data[1] = (val >> 0) & 0xFF;
221 static inline void __b44_cam_write(struct b44 *bp,
222 const unsigned char *data, int index)
226 val = ((u32) data[2]) << 24;
227 val |= ((u32) data[3]) << 16;
228 val |= ((u32) data[4]) << 8;
229 val |= ((u32) data[5]) << 0;
230 bw32(bp, B44_CAM_DATA_LO, val);
231 val = (CAM_DATA_HI_VALID |
232 (((u32) data[0]) << 8) |
233 (((u32) data[1]) << 0));
234 bw32(bp, B44_CAM_DATA_HI, val);
235 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
236 (index << CAM_CTRL_INDEX_SHIFT)));
237 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
240 static inline void __b44_disable_ints(struct b44 *bp)
242 bw32(bp, B44_IMASK, 0);
245 static void b44_disable_ints(struct b44 *bp)
247 __b44_disable_ints(bp);
249 /* Flush posted writes. */
253 static void b44_enable_ints(struct b44 *bp)
255 bw32(bp, B44_IMASK, bp->imask);
258 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
262 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
263 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
264 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
265 (phy_addr << MDIO_DATA_PMD_SHIFT) |
266 (reg << MDIO_DATA_RA_SHIFT) |
267 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
268 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
269 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
274 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
276 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
277 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
278 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
279 (phy_addr << MDIO_DATA_PMD_SHIFT) |
280 (reg << MDIO_DATA_RA_SHIFT) |
281 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
282 (val & MDIO_DATA_DATA)));
283 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
286 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
288 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
291 return __b44_readphy(bp, bp->phy_addr, reg, val);
294 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
296 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
299 return __b44_writephy(bp, bp->phy_addr, reg, val);
302 /* miilib interface */
303 static int b44_mdio_read_mii(struct net_device *dev, int phy_id, int location)
306 struct b44 *bp = netdev_priv(dev);
307 int rc = __b44_readphy(bp, phy_id, location, &val);
313 static void b44_mdio_write_mii(struct net_device *dev, int phy_id, int location,
316 struct b44 *bp = netdev_priv(dev);
317 __b44_writephy(bp, phy_id, location, val);
320 static int b44_mdio_read_phylib(struct mii_bus *bus, int phy_id, int location)
323 struct b44 *bp = bus->priv;
324 int rc = __b44_readphy(bp, phy_id, location, &val);
330 static int b44_mdio_write_phylib(struct mii_bus *bus, int phy_id, int location,
333 struct b44 *bp = bus->priv;
334 return __b44_writephy(bp, phy_id, location, val);
337 static int b44_phy_reset(struct b44 *bp)
342 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
344 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
348 err = b44_readphy(bp, MII_BMCR, &val);
350 if (val & BMCR_RESET) {
351 netdev_err(bp->dev, "PHY Reset would not complete\n");
359 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
363 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
364 bp->flags |= pause_flags;
366 val = br32(bp, B44_RXCONFIG);
367 if (pause_flags & B44_FLAG_RX_PAUSE)
368 val |= RXCONFIG_FLOW;
370 val &= ~RXCONFIG_FLOW;
371 bw32(bp, B44_RXCONFIG, val);
373 val = br32(bp, B44_MAC_FLOW);
374 if (pause_flags & B44_FLAG_TX_PAUSE)
375 val |= (MAC_FLOW_PAUSE_ENAB |
376 (0xc0 & MAC_FLOW_RX_HI_WATER));
378 val &= ~MAC_FLOW_PAUSE_ENAB;
379 bw32(bp, B44_MAC_FLOW, val);
382 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
386 /* The driver supports only rx pause by default because
387 the b44 mac tx pause mechanism generates excessive
389 Use ethtool to turn on b44 tx pause if necessary.
391 if ((local & ADVERTISE_PAUSE_CAP) &&
392 (local & ADVERTISE_PAUSE_ASYM)){
393 if ((remote & LPA_PAUSE_ASYM) &&
394 !(remote & LPA_PAUSE_CAP))
395 pause_enab |= B44_FLAG_RX_PAUSE;
398 __b44_set_flow_ctrl(bp, pause_enab);
401 #ifdef CONFIG_BCM47XX
402 #include <linux/bcm47xx_nvram.h>
403 static void b44_wap54g10_workaround(struct b44 *bp)
410 * workaround for bad hardware design in Linksys WAP54G v1.0
411 * see https://dev.openwrt.org/ticket/146
412 * check and reset bit "isolate"
414 if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
416 if (simple_strtoul(buf, NULL, 0) == 2) {
417 err = __b44_readphy(bp, 0, MII_BMCR, &val);
420 if (!(val & BMCR_ISOLATE))
422 val &= ~BMCR_ISOLATE;
423 err = __b44_writephy(bp, 0, MII_BMCR, val);
429 pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
432 static inline void b44_wap54g10_workaround(struct b44 *bp)
437 static int b44_setup_phy(struct b44 *bp)
442 b44_wap54g10_workaround(bp);
444 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
446 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
448 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
449 val & MII_ALEDCTRL_ALLMSK)) != 0)
451 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
453 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
454 val | MII_TLEDCTRL_ENABLE)) != 0)
457 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
458 u32 adv = ADVERTISE_CSMA;
460 if (bp->flags & B44_FLAG_ADV_10HALF)
461 adv |= ADVERTISE_10HALF;
462 if (bp->flags & B44_FLAG_ADV_10FULL)
463 adv |= ADVERTISE_10FULL;
464 if (bp->flags & B44_FLAG_ADV_100HALF)
465 adv |= ADVERTISE_100HALF;
466 if (bp->flags & B44_FLAG_ADV_100FULL)
467 adv |= ADVERTISE_100FULL;
469 if (bp->flags & B44_FLAG_PAUSE_AUTO)
470 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
472 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
474 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
475 BMCR_ANRESTART))) != 0)
480 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
482 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
483 if (bp->flags & B44_FLAG_100_BASE_T)
484 bmcr |= BMCR_SPEED100;
485 if (bp->flags & B44_FLAG_FULL_DUPLEX)
486 bmcr |= BMCR_FULLDPLX;
487 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
490 /* Since we will not be negotiating there is no safe way
491 * to determine if the link partner supports flow control
492 * or not. So just disable it completely in this case.
494 b44_set_flow_ctrl(bp, 0, 0);
501 static void b44_stats_update(struct b44 *bp)
506 val = &bp->hw_stats.tx_good_octets;
507 u64_stats_update_begin(&bp->hw_stats.syncp);
509 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
510 *val++ += br32(bp, reg);
513 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
514 *val++ += br32(bp, reg);
517 u64_stats_update_end(&bp->hw_stats.syncp);
520 static void b44_link_report(struct b44 *bp)
522 if (!netif_carrier_ok(bp->dev)) {
523 netdev_info(bp->dev, "Link is down\n");
525 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
526 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
527 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
529 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
530 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
531 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
535 static void b44_check_phy(struct b44 *bp)
539 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
540 bp->flags |= B44_FLAG_100_BASE_T;
541 if (!netif_carrier_ok(bp->dev)) {
542 u32 val = br32(bp, B44_TX_CTRL);
543 if (bp->flags & B44_FLAG_FULL_DUPLEX)
544 val |= TX_CTRL_DUPLEX;
546 val &= ~TX_CTRL_DUPLEX;
547 bw32(bp, B44_TX_CTRL, val);
548 netif_carrier_on(bp->dev);
554 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
555 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
557 if (aux & MII_AUXCTRL_SPEED)
558 bp->flags |= B44_FLAG_100_BASE_T;
560 bp->flags &= ~B44_FLAG_100_BASE_T;
561 if (aux & MII_AUXCTRL_DUPLEX)
562 bp->flags |= B44_FLAG_FULL_DUPLEX;
564 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
566 if (!netif_carrier_ok(bp->dev) &&
567 (bmsr & BMSR_LSTATUS)) {
568 u32 val = br32(bp, B44_TX_CTRL);
569 u32 local_adv, remote_adv;
571 if (bp->flags & B44_FLAG_FULL_DUPLEX)
572 val |= TX_CTRL_DUPLEX;
574 val &= ~TX_CTRL_DUPLEX;
575 bw32(bp, B44_TX_CTRL, val);
577 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
578 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
579 !b44_readphy(bp, MII_LPA, &remote_adv))
580 b44_set_flow_ctrl(bp, local_adv, remote_adv);
583 netif_carrier_on(bp->dev);
585 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
587 netif_carrier_off(bp->dev);
591 if (bmsr & BMSR_RFAULT)
592 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
594 netdev_warn(bp->dev, "Jabber detected in PHY\n");
598 static void b44_timer(struct timer_list *t)
600 struct b44 *bp = from_timer(bp, t, timer);
602 spin_lock_irq(&bp->lock);
606 b44_stats_update(bp);
608 spin_unlock_irq(&bp->lock);
610 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
613 static void b44_tx(struct b44 *bp)
616 unsigned bytes_compl = 0, pkts_compl = 0;
618 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
619 cur /= sizeof(struct dma_desc);
621 /* XXX needs updating when NETIF_F_SG is supported */
622 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
623 struct ring_info *rp = &bp->tx_buffers[cons];
624 struct sk_buff *skb = rp->skb;
628 dma_unmap_single(bp->sdev->dma_dev,
634 bytes_compl += skb->len;
637 dev_consume_skb_irq(skb);
640 netdev_completed_queue(bp->dev, pkts_compl, bytes_compl);
642 if (netif_queue_stopped(bp->dev) &&
643 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
644 netif_wake_queue(bp->dev);
646 bw32(bp, B44_GPTIMER, 0);
649 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
650 * before the DMA address you give it. So we allocate 30 more bytes
651 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
652 * point the chip at 30 bytes past where the rx_header will go.
654 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
657 struct ring_info *src_map, *map;
658 struct rx_header *rh;
666 src_map = &bp->rx_buffers[src_idx];
667 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
668 map = &bp->rx_buffers[dest_idx];
669 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
673 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
677 /* Hardware bug work-around, the chip is unable to do PCI DMA
678 to/from anything above 1GB :-( */
679 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
680 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
682 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
683 dma_unmap_single(bp->sdev->dma_dev, mapping,
684 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
685 dev_kfree_skb_any(skb);
686 skb = alloc_skb(RX_PKT_BUF_SZ, GFP_ATOMIC | GFP_DMA);
689 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
692 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
693 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
694 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
695 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
696 dev_kfree_skb_any(skb);
699 bp->force_copybreak = 1;
702 rh = (struct rx_header *) skb->data;
708 map->mapping = mapping;
713 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
714 if (dest_idx == (B44_RX_RING_SIZE - 1))
715 ctrl |= DESC_CTRL_EOT;
717 dp = &bp->rx_ring[dest_idx];
718 dp->ctrl = cpu_to_le32(ctrl);
719 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
721 if (bp->flags & B44_FLAG_RX_RING_HACK)
722 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
723 dest_idx * sizeof(*dp),
726 return RX_PKT_BUF_SZ;
729 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
731 struct dma_desc *src_desc, *dest_desc;
732 struct ring_info *src_map, *dest_map;
733 struct rx_header *rh;
737 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
738 dest_desc = &bp->rx_ring[dest_idx];
739 dest_map = &bp->rx_buffers[dest_idx];
740 src_desc = &bp->rx_ring[src_idx];
741 src_map = &bp->rx_buffers[src_idx];
743 dest_map->skb = src_map->skb;
744 rh = (struct rx_header *) src_map->skb->data;
747 dest_map->mapping = src_map->mapping;
749 if (bp->flags & B44_FLAG_RX_RING_HACK)
750 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
751 src_idx * sizeof(*src_desc),
754 ctrl = src_desc->ctrl;
755 if (dest_idx == (B44_RX_RING_SIZE - 1))
756 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
758 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
760 dest_desc->ctrl = ctrl;
761 dest_desc->addr = src_desc->addr;
765 if (bp->flags & B44_FLAG_RX_RING_HACK)
766 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
767 dest_idx * sizeof(*dest_desc),
770 dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
775 static int b44_rx(struct b44 *bp, int budget)
781 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
782 prod /= sizeof(struct dma_desc);
785 while (cons != prod && budget > 0) {
786 struct ring_info *rp = &bp->rx_buffers[cons];
787 struct sk_buff *skb = rp->skb;
788 dma_addr_t map = rp->mapping;
789 struct rx_header *rh;
792 dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
795 rh = (struct rx_header *) skb->data;
796 len = le16_to_cpu(rh->len);
797 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
798 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
800 b44_recycle_rx(bp, cons, bp->rx_prod);
802 bp->dev->stats.rx_dropped++;
812 len = le16_to_cpu(rh->len);
813 } while (len == 0 && i++ < 5);
821 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
823 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
826 dma_unmap_single(bp->sdev->dma_dev, map,
827 skb_size, DMA_FROM_DEVICE);
828 /* Leave out rx_header */
829 skb_put(skb, len + RX_PKT_OFFSET);
830 skb_pull(skb, RX_PKT_OFFSET);
832 struct sk_buff *copy_skb;
834 b44_recycle_rx(bp, cons, bp->rx_prod);
835 copy_skb = napi_alloc_skb(&bp->napi, len);
836 if (copy_skb == NULL)
837 goto drop_it_no_recycle;
839 skb_put(copy_skb, len);
840 /* DMA sync done above, copy just the actual packet */
841 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
842 copy_skb->data, len);
845 skb_checksum_none_assert(skb);
846 skb->protocol = eth_type_trans(skb, bp->dev);
847 netif_receive_skb(skb);
851 bp->rx_prod = (bp->rx_prod + 1) &
852 (B44_RX_RING_SIZE - 1);
853 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
857 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
862 static int b44_poll(struct napi_struct *napi, int budget)
864 struct b44 *bp = container_of(napi, struct b44, napi);
868 spin_lock_irqsave(&bp->lock, flags);
870 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
871 /* spin_lock(&bp->tx_lock); */
873 /* spin_unlock(&bp->tx_lock); */
875 if (bp->istat & ISTAT_RFO) { /* fast recovery, in ~20msec */
876 bp->istat &= ~ISTAT_RFO;
877 b44_disable_ints(bp);
878 ssb_device_enable(bp->sdev, 0); /* resets ISTAT_RFO */
880 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
881 netif_wake_queue(bp->dev);
884 spin_unlock_irqrestore(&bp->lock, flags);
887 if (bp->istat & ISTAT_RX)
888 work_done += b44_rx(bp, budget);
890 if (bp->istat & ISTAT_ERRORS) {
891 spin_lock_irqsave(&bp->lock, flags);
894 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
895 netif_wake_queue(bp->dev);
896 spin_unlock_irqrestore(&bp->lock, flags);
900 if (work_done < budget) {
901 napi_complete_done(napi, work_done);
908 static irqreturn_t b44_interrupt(int irq, void *dev_id)
910 struct net_device *dev = dev_id;
911 struct b44 *bp = netdev_priv(dev);
915 spin_lock(&bp->lock);
917 istat = br32(bp, B44_ISTAT);
918 imask = br32(bp, B44_IMASK);
920 /* The interrupt mask register controls which interrupt bits
921 * will actually raise an interrupt to the CPU when set by hw/firmware,
922 * but doesn't mask off the bits.
928 if (unlikely(!netif_running(dev))) {
929 netdev_info(dev, "late interrupt\n");
933 if (napi_schedule_prep(&bp->napi)) {
934 /* NOTE: These writes are posted by the readback of
935 * the ISTAT register below.
938 __b44_disable_ints(bp);
939 __napi_schedule(&bp->napi);
943 bw32(bp, B44_ISTAT, istat);
946 spin_unlock(&bp->lock);
947 return IRQ_RETVAL(handled);
950 static void b44_tx_timeout(struct net_device *dev, unsigned int txqueue)
952 struct b44 *bp = netdev_priv(dev);
954 netdev_err(dev, "transmit timed out, resetting\n");
956 spin_lock_irq(&bp->lock);
960 b44_init_hw(bp, B44_FULL_RESET);
962 spin_unlock_irq(&bp->lock);
966 netif_wake_queue(dev);
969 static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
971 struct b44 *bp = netdev_priv(dev);
972 int rc = NETDEV_TX_OK;
974 u32 len, entry, ctrl;
978 spin_lock_irqsave(&bp->lock, flags);
980 /* This is a hard error, log it. */
981 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
982 netif_stop_queue(dev);
983 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
987 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
988 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
989 struct sk_buff *bounce_skb;
991 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
992 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
993 dma_unmap_single(bp->sdev->dma_dev, mapping, len,
996 bounce_skb = alloc_skb(len, GFP_ATOMIC | GFP_DMA);
1000 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
1001 len, DMA_TO_DEVICE);
1002 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
1003 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
1004 dma_unmap_single(bp->sdev->dma_dev, mapping,
1005 len, DMA_TO_DEVICE);
1006 dev_kfree_skb_any(bounce_skb);
1010 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1011 dev_consume_skb_any(skb);
1015 entry = bp->tx_prod;
1016 bp->tx_buffers[entry].skb = skb;
1017 bp->tx_buffers[entry].mapping = mapping;
1019 ctrl = (len & DESC_CTRL_LEN);
1020 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1021 if (entry == (B44_TX_RING_SIZE - 1))
1022 ctrl |= DESC_CTRL_EOT;
1024 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1025 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1027 if (bp->flags & B44_FLAG_TX_RING_HACK)
1028 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1029 entry * sizeof(bp->tx_ring[0]),
1032 entry = NEXT_TX(entry);
1034 bp->tx_prod = entry;
1038 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1039 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1040 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1041 if (bp->flags & B44_FLAG_REORDER_BUG)
1042 br32(bp, B44_DMATX_PTR);
1044 netdev_sent_queue(dev, skb->len);
1046 if (TX_BUFFS_AVAIL(bp) < 1)
1047 netif_stop_queue(dev);
1050 spin_unlock_irqrestore(&bp->lock, flags);
1055 rc = NETDEV_TX_BUSY;
1059 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1061 struct b44 *bp = netdev_priv(dev);
1063 if (!netif_running(dev)) {
1064 /* We'll just catch it later when the
1071 spin_lock_irq(&bp->lock);
1075 b44_init_hw(bp, B44_FULL_RESET);
1076 spin_unlock_irq(&bp->lock);
1078 b44_enable_ints(bp);
1083 /* Free up pending packets in all rx/tx rings.
1085 * The chip has been shut down and the driver detached from
1086 * the networking, so no interrupts or new tx packets will
1087 * end up in the driver. bp->lock is not held and we are not
1088 * in an interrupt context and thus may sleep.
1090 static void b44_free_rings(struct b44 *bp)
1092 struct ring_info *rp;
1095 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1096 rp = &bp->rx_buffers[i];
1098 if (rp->skb == NULL)
1100 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
1102 dev_kfree_skb_any(rp->skb);
1106 /* XXX needs changes once NETIF_F_SG is set... */
1107 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1108 rp = &bp->tx_buffers[i];
1110 if (rp->skb == NULL)
1112 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
1114 dev_kfree_skb_any(rp->skb);
1119 /* Initialize tx/rx rings for packet processing.
1121 * The chip has been shut down and the driver detached from
1122 * the networking, so no interrupts or new tx packets will
1123 * end up in the driver.
1125 static void b44_init_rings(struct b44 *bp)
1131 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1132 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1134 if (bp->flags & B44_FLAG_RX_RING_HACK)
1135 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
1136 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1138 if (bp->flags & B44_FLAG_TX_RING_HACK)
1139 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
1140 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1142 for (i = 0; i < bp->rx_pending; i++) {
1143 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1149 * Must not be invoked with interrupt sources disabled and
1150 * the hardware shutdown down.
1152 static void b44_free_consistent(struct b44 *bp)
1154 kfree(bp->rx_buffers);
1155 bp->rx_buffers = NULL;
1156 kfree(bp->tx_buffers);
1157 bp->tx_buffers = NULL;
1159 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1160 dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
1161 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1164 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1165 bp->rx_ring, bp->rx_ring_dma);
1167 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1170 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1171 dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
1172 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1175 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1176 bp->tx_ring, bp->tx_ring_dma);
1178 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1183 * Must not be invoked with interrupt sources disabled and
1184 * the hardware shutdown down. Can sleep.
1186 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1190 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1191 bp->rx_buffers = kzalloc(size, gfp);
1192 if (!bp->rx_buffers)
1195 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1196 bp->tx_buffers = kzalloc(size, gfp);
1197 if (!bp->tx_buffers)
1200 size = DMA_TABLE_BYTES;
1201 bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1202 &bp->rx_ring_dma, gfp);
1204 /* Allocation may have failed due to dma_alloc_coherent
1205 insisting on use of GFP_DMA, which is more restrictive
1206 than necessary... */
1207 struct dma_desc *rx_ring;
1208 dma_addr_t rx_ring_dma;
1210 rx_ring = kzalloc(size, gfp);
1214 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
1218 if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
1219 rx_ring_dma + size > DMA_BIT_MASK(30)) {
1224 bp->rx_ring = rx_ring;
1225 bp->rx_ring_dma = rx_ring_dma;
1226 bp->flags |= B44_FLAG_RX_RING_HACK;
1229 bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1230 &bp->tx_ring_dma, gfp);
1232 /* Allocation may have failed due to ssb_dma_alloc_consistent
1233 insisting on use of GFP_DMA, which is more restrictive
1234 than necessary... */
1235 struct dma_desc *tx_ring;
1236 dma_addr_t tx_ring_dma;
1238 tx_ring = kzalloc(size, gfp);
1242 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
1246 if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
1247 tx_ring_dma + size > DMA_BIT_MASK(30)) {
1252 bp->tx_ring = tx_ring;
1253 bp->tx_ring_dma = tx_ring_dma;
1254 bp->flags |= B44_FLAG_TX_RING_HACK;
1260 b44_free_consistent(bp);
1264 /* bp->lock is held. */
1265 static void b44_clear_stats(struct b44 *bp)
1269 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1270 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1272 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1276 /* bp->lock is held. */
1277 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1279 struct ssb_device *sdev = bp->sdev;
1282 was_enabled = ssb_device_is_enabled(bp->sdev);
1284 ssb_device_enable(bp->sdev, 0);
1285 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1288 bw32(bp, B44_RCV_LAZY, 0);
1289 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1290 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1291 bw32(bp, B44_DMATX_CTRL, 0);
1292 bp->tx_prod = bp->tx_cons = 0;
1293 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1294 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1297 bw32(bp, B44_DMARX_CTRL, 0);
1298 bp->rx_prod = bp->rx_cons = 0;
1301 b44_clear_stats(bp);
1304 * Don't enable PHY if we are doing a partial reset
1305 * we are probably going to power down
1307 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1310 switch (sdev->bus->bustype) {
1311 case SSB_BUSTYPE_SSB:
1312 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1313 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1315 & MDIO_CTRL_MAXF_MASK)));
1317 case SSB_BUSTYPE_PCI:
1318 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1319 (0x0d & MDIO_CTRL_MAXF_MASK)));
1321 case SSB_BUSTYPE_PCMCIA:
1322 case SSB_BUSTYPE_SDIO:
1323 WARN_ON(1); /* A device with this bus does not exist. */
1327 br32(bp, B44_MDIO_CTRL);
1329 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1330 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1331 br32(bp, B44_ENET_CTRL);
1332 bp->flags |= B44_FLAG_EXTERNAL_PHY;
1334 u32 val = br32(bp, B44_DEVCTRL);
1336 if (val & DEVCTRL_EPR) {
1337 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1338 br32(bp, B44_DEVCTRL);
1341 bp->flags &= ~B44_FLAG_EXTERNAL_PHY;
1345 /* bp->lock is held. */
1346 static void b44_halt(struct b44 *bp)
1348 b44_disable_ints(bp);
1351 /* power down PHY */
1352 netdev_info(bp->dev, "powering down PHY\n");
1353 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1354 /* now reset the chip, but without enabling the MAC&PHY
1355 * part of it. This has to be done _after_ we shut down the PHY */
1356 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
1357 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1359 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1362 /* bp->lock is held. */
1363 static void __b44_set_mac_addr(struct b44 *bp)
1365 bw32(bp, B44_CAM_CTRL, 0);
1366 if (!(bp->dev->flags & IFF_PROMISC)) {
1369 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1370 val = br32(bp, B44_CAM_CTRL);
1371 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1375 static int b44_set_mac_addr(struct net_device *dev, void *p)
1377 struct b44 *bp = netdev_priv(dev);
1378 struct sockaddr *addr = p;
1381 if (netif_running(dev))
1384 if (!is_valid_ether_addr(addr->sa_data))
1387 eth_hw_addr_set(dev, addr->sa_data);
1389 spin_lock_irq(&bp->lock);
1391 val = br32(bp, B44_RXCONFIG);
1392 if (!(val & RXCONFIG_CAM_ABSENT))
1393 __b44_set_mac_addr(bp);
1395 spin_unlock_irq(&bp->lock);
1400 /* Called at device open time to get the chip ready for
1401 * packet processing. Invoked with bp->lock held.
1403 static void __b44_set_rx_mode(struct net_device *);
1404 static void b44_init_hw(struct b44 *bp, int reset_kind)
1408 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1409 if (reset_kind == B44_FULL_RESET) {
1414 /* Enable CRC32, set proper LED modes and power on PHY */
1415 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1416 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1418 /* This sets the MAC address too. */
1419 __b44_set_rx_mode(bp->dev);
1421 /* MTU + eth header + possible VLAN tag + struct rx_header */
1422 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1423 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1425 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1426 if (reset_kind == B44_PARTIAL_RESET) {
1427 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1428 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1430 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1431 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1432 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1433 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1434 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1436 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1437 bp->rx_prod = bp->rx_pending;
1439 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1442 val = br32(bp, B44_ENET_CTRL);
1443 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1445 netdev_reset_queue(bp->dev);
1448 static int b44_open(struct net_device *dev)
1450 struct b44 *bp = netdev_priv(dev);
1453 err = b44_alloc_consistent(bp, GFP_KERNEL);
1457 napi_enable(&bp->napi);
1460 b44_init_hw(bp, B44_FULL_RESET);
1464 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1465 if (unlikely(err < 0)) {
1466 napi_disable(&bp->napi);
1467 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1469 b44_free_consistent(bp);
1473 timer_setup(&bp->timer, b44_timer, 0);
1474 bp->timer.expires = jiffies + HZ;
1475 add_timer(&bp->timer);
1477 b44_enable_ints(bp);
1479 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
1480 phy_start(dev->phydev);
1482 netif_start_queue(dev);
1487 #ifdef CONFIG_NET_POLL_CONTROLLER
1489 * Polling receive - used by netconsole and other diagnostic tools
1490 * to allow network i/o with interrupts disabled.
1492 static void b44_poll_controller(struct net_device *dev)
1494 disable_irq(dev->irq);
1495 b44_interrupt(dev->irq, dev);
1496 enable_irq(dev->irq);
1500 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1503 u32 *pattern = (u32 *) pp;
1505 for (i = 0; i < bytes; i += sizeof(u32)) {
1506 bw32(bp, B44_FILT_ADDR, table_offset + i);
1507 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1511 static int b44_magic_pattern(const u8 *macaddr, u8 *ppattern, u8 *pmask,
1515 int k, j, len = offset;
1516 int ethaddr_bytes = ETH_ALEN;
1518 memset(ppattern + offset, 0xff, magicsync);
1519 for (j = 0; j < magicsync; j++) {
1520 pmask[len >> 3] |= BIT(len & 7);
1524 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1525 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1526 ethaddr_bytes = ETH_ALEN;
1528 ethaddr_bytes = B44_PATTERN_SIZE - len;
1529 if (ethaddr_bytes <=0)
1531 for (k = 0; k< ethaddr_bytes; k++) {
1532 ppattern[offset + magicsync +
1533 (j * ETH_ALEN) + k] = macaddr[k];
1534 pmask[len >> 3] |= BIT(len & 7);
1541 /* Setup magic packet patterns in the b44 WOL
1542 * pattern matching filter.
1544 static void b44_setup_pseudo_magicp(struct b44 *bp)
1548 int plen0, plen1, plen2;
1550 u8 pwol_mask[B44_PMASK_SIZE];
1552 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1556 /* Ipv4 magic packet pattern - pattern 0.*/
1557 memset(pwol_mask, 0, B44_PMASK_SIZE);
1558 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1559 B44_ETHIPV4UDP_HLEN);
1561 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1562 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1564 /* Raw ethernet II magic packet pattern - pattern 1 */
1565 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1566 memset(pwol_mask, 0, B44_PMASK_SIZE);
1567 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1570 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1571 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1572 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1573 B44_PMASK_BASE + B44_PMASK_SIZE);
1575 /* Ipv6 magic packet pattern - pattern 2 */
1576 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1577 memset(pwol_mask, 0, B44_PMASK_SIZE);
1578 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1579 B44_ETHIPV6UDP_HLEN);
1581 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1582 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1583 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1584 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1586 kfree(pwol_pattern);
1588 /* set these pattern's lengths: one less than each real length */
1589 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1590 bw32(bp, B44_WKUP_LEN, val);
1592 /* enable wakeup pattern matching */
1593 val = br32(bp, B44_DEVCTRL);
1594 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1598 #ifdef CONFIG_B44_PCI
1599 static void b44_setup_wol_pci(struct b44 *bp)
1603 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1604 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1605 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1606 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1610 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1611 #endif /* CONFIG_B44_PCI */
1613 static void b44_setup_wol(struct b44 *bp)
1617 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1619 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1621 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1623 val = bp->dev->dev_addr[2] << 24 |
1624 bp->dev->dev_addr[3] << 16 |
1625 bp->dev->dev_addr[4] << 8 |
1626 bp->dev->dev_addr[5];
1627 bw32(bp, B44_ADDR_LO, val);
1629 val = bp->dev->dev_addr[0] << 8 |
1630 bp->dev->dev_addr[1];
1631 bw32(bp, B44_ADDR_HI, val);
1633 val = br32(bp, B44_DEVCTRL);
1634 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1637 b44_setup_pseudo_magicp(bp);
1639 b44_setup_wol_pci(bp);
1642 static int b44_close(struct net_device *dev)
1644 struct b44 *bp = netdev_priv(dev);
1646 netif_stop_queue(dev);
1648 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
1649 phy_stop(dev->phydev);
1651 napi_disable(&bp->napi);
1653 del_timer_sync(&bp->timer);
1655 spin_lock_irq(&bp->lock);
1659 netif_carrier_off(dev);
1661 spin_unlock_irq(&bp->lock);
1663 free_irq(dev->irq, dev);
1665 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1666 b44_init_hw(bp, B44_PARTIAL_RESET);
1670 b44_free_consistent(bp);
1675 static void b44_get_stats64(struct net_device *dev,
1676 struct rtnl_link_stats64 *nstat)
1678 struct b44 *bp = netdev_priv(dev);
1679 struct b44_hw_stats *hwstat = &bp->hw_stats;
1683 start = u64_stats_fetch_begin_irq(&hwstat->syncp);
1685 /* Convert HW stats into rtnl_link_stats64 stats. */
1686 nstat->rx_packets = hwstat->rx_pkts;
1687 nstat->tx_packets = hwstat->tx_pkts;
1688 nstat->rx_bytes = hwstat->rx_octets;
1689 nstat->tx_bytes = hwstat->tx_octets;
1690 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1691 hwstat->tx_oversize_pkts +
1692 hwstat->tx_underruns +
1693 hwstat->tx_excessive_cols +
1694 hwstat->tx_late_cols);
1695 nstat->multicast = hwstat->rx_multicast_pkts;
1696 nstat->collisions = hwstat->tx_total_cols;
1698 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1699 hwstat->rx_undersize);
1700 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1701 nstat->rx_frame_errors = hwstat->rx_align_errs;
1702 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1703 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1704 hwstat->rx_oversize_pkts +
1705 hwstat->rx_missed_pkts +
1706 hwstat->rx_crc_align_errs +
1707 hwstat->rx_undersize +
1708 hwstat->rx_crc_errs +
1709 hwstat->rx_align_errs +
1710 hwstat->rx_symbol_errs);
1712 nstat->tx_aborted_errors = hwstat->tx_underruns;
1714 /* Carrier lost counter seems to be broken for some devices */
1715 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1717 } while (u64_stats_fetch_retry_irq(&hwstat->syncp, start));
1721 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1723 struct netdev_hw_addr *ha;
1726 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
1728 netdev_for_each_mc_addr(ha, dev) {
1731 __b44_cam_write(bp, ha->addr, i++ + 1);
1736 static void __b44_set_rx_mode(struct net_device *dev)
1738 struct b44 *bp = netdev_priv(dev);
1741 val = br32(bp, B44_RXCONFIG);
1742 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1743 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1744 val |= RXCONFIG_PROMISC;
1745 bw32(bp, B44_RXCONFIG, val);
1747 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1750 __b44_set_mac_addr(bp);
1752 if ((dev->flags & IFF_ALLMULTI) ||
1753 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1754 val |= RXCONFIG_ALLMULTI;
1756 i = __b44_load_mcast(bp, dev);
1759 __b44_cam_write(bp, zero, i);
1761 bw32(bp, B44_RXCONFIG, val);
1762 val = br32(bp, B44_CAM_CTRL);
1763 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1767 static void b44_set_rx_mode(struct net_device *dev)
1769 struct b44 *bp = netdev_priv(dev);
1771 spin_lock_irq(&bp->lock);
1772 __b44_set_rx_mode(dev);
1773 spin_unlock_irq(&bp->lock);
1776 static u32 b44_get_msglevel(struct net_device *dev)
1778 struct b44 *bp = netdev_priv(dev);
1779 return bp->msg_enable;
1782 static void b44_set_msglevel(struct net_device *dev, u32 value)
1784 struct b44 *bp = netdev_priv(dev);
1785 bp->msg_enable = value;
1788 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1790 struct b44 *bp = netdev_priv(dev);
1791 struct ssb_bus *bus = bp->sdev->bus;
1793 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1794 switch (bus->bustype) {
1795 case SSB_BUSTYPE_PCI:
1796 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1798 case SSB_BUSTYPE_SSB:
1799 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1801 case SSB_BUSTYPE_PCMCIA:
1802 case SSB_BUSTYPE_SDIO:
1803 WARN_ON(1); /* A device with this bus does not exist. */
1808 static int b44_nway_reset(struct net_device *dev)
1810 struct b44 *bp = netdev_priv(dev);
1814 spin_lock_irq(&bp->lock);
1815 b44_readphy(bp, MII_BMCR, &bmcr);
1816 b44_readphy(bp, MII_BMCR, &bmcr);
1818 if (bmcr & BMCR_ANENABLE) {
1819 b44_writephy(bp, MII_BMCR,
1820 bmcr | BMCR_ANRESTART);
1823 spin_unlock_irq(&bp->lock);
1828 static int b44_get_link_ksettings(struct net_device *dev,
1829 struct ethtool_link_ksettings *cmd)
1831 struct b44 *bp = netdev_priv(dev);
1832 u32 supported, advertising;
1834 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
1835 BUG_ON(!dev->phydev);
1836 phy_ethtool_ksettings_get(dev->phydev, cmd);
1841 supported = (SUPPORTED_Autoneg);
1842 supported |= (SUPPORTED_100baseT_Half |
1843 SUPPORTED_100baseT_Full |
1844 SUPPORTED_10baseT_Half |
1845 SUPPORTED_10baseT_Full |
1849 if (bp->flags & B44_FLAG_ADV_10HALF)
1850 advertising |= ADVERTISED_10baseT_Half;
1851 if (bp->flags & B44_FLAG_ADV_10FULL)
1852 advertising |= ADVERTISED_10baseT_Full;
1853 if (bp->flags & B44_FLAG_ADV_100HALF)
1854 advertising |= ADVERTISED_100baseT_Half;
1855 if (bp->flags & B44_FLAG_ADV_100FULL)
1856 advertising |= ADVERTISED_100baseT_Full;
1857 advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1858 cmd->base.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1859 SPEED_100 : SPEED_10;
1860 cmd->base.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1861 DUPLEX_FULL : DUPLEX_HALF;
1863 cmd->base.phy_address = bp->phy_addr;
1864 cmd->base.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1865 AUTONEG_DISABLE : AUTONEG_ENABLE;
1866 if (cmd->base.autoneg == AUTONEG_ENABLE)
1867 advertising |= ADVERTISED_Autoneg;
1869 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1871 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1874 if (!netif_running(dev)){
1875 cmd->base.speed = 0;
1876 cmd->base.duplex = 0xff;
1882 static int b44_set_link_ksettings(struct net_device *dev,
1883 const struct ethtool_link_ksettings *cmd)
1885 struct b44 *bp = netdev_priv(dev);
1890 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
1891 BUG_ON(!dev->phydev);
1892 spin_lock_irq(&bp->lock);
1893 if (netif_running(dev))
1896 ret = phy_ethtool_ksettings_set(dev->phydev, cmd);
1898 spin_unlock_irq(&bp->lock);
1903 speed = cmd->base.speed;
1905 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1906 cmd->link_modes.advertising);
1908 /* We do not support gigabit. */
1909 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1911 (ADVERTISED_1000baseT_Half |
1912 ADVERTISED_1000baseT_Full))
1914 } else if ((speed != SPEED_100 &&
1915 speed != SPEED_10) ||
1916 (cmd->base.duplex != DUPLEX_HALF &&
1917 cmd->base.duplex != DUPLEX_FULL)) {
1921 spin_lock_irq(&bp->lock);
1923 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1924 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1925 B44_FLAG_100_BASE_T |
1926 B44_FLAG_FULL_DUPLEX |
1927 B44_FLAG_ADV_10HALF |
1928 B44_FLAG_ADV_10FULL |
1929 B44_FLAG_ADV_100HALF |
1930 B44_FLAG_ADV_100FULL);
1931 if (advertising == 0) {
1932 bp->flags |= (B44_FLAG_ADV_10HALF |
1933 B44_FLAG_ADV_10FULL |
1934 B44_FLAG_ADV_100HALF |
1935 B44_FLAG_ADV_100FULL);
1937 if (advertising & ADVERTISED_10baseT_Half)
1938 bp->flags |= B44_FLAG_ADV_10HALF;
1939 if (advertising & ADVERTISED_10baseT_Full)
1940 bp->flags |= B44_FLAG_ADV_10FULL;
1941 if (advertising & ADVERTISED_100baseT_Half)
1942 bp->flags |= B44_FLAG_ADV_100HALF;
1943 if (advertising & ADVERTISED_100baseT_Full)
1944 bp->flags |= B44_FLAG_ADV_100FULL;
1947 bp->flags |= B44_FLAG_FORCE_LINK;
1948 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1949 if (speed == SPEED_100)
1950 bp->flags |= B44_FLAG_100_BASE_T;
1951 if (cmd->base.duplex == DUPLEX_FULL)
1952 bp->flags |= B44_FLAG_FULL_DUPLEX;
1955 if (netif_running(dev))
1958 spin_unlock_irq(&bp->lock);
1963 static void b44_get_ringparam(struct net_device *dev,
1964 struct ethtool_ringparam *ering,
1965 struct kernel_ethtool_ringparam *kernel_ering,
1966 struct netlink_ext_ack *extack)
1968 struct b44 *bp = netdev_priv(dev);
1970 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1971 ering->rx_pending = bp->rx_pending;
1973 /* XXX ethtool lacks a tx_max_pending, oops... */
1976 static int b44_set_ringparam(struct net_device *dev,
1977 struct ethtool_ringparam *ering,
1978 struct kernel_ethtool_ringparam *kernel_ering,
1979 struct netlink_ext_ack *extack)
1981 struct b44 *bp = netdev_priv(dev);
1983 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1984 (ering->rx_mini_pending != 0) ||
1985 (ering->rx_jumbo_pending != 0) ||
1986 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1989 spin_lock_irq(&bp->lock);
1991 bp->rx_pending = ering->rx_pending;
1992 bp->tx_pending = ering->tx_pending;
1996 b44_init_hw(bp, B44_FULL_RESET);
1997 netif_wake_queue(bp->dev);
1998 spin_unlock_irq(&bp->lock);
2000 b44_enable_ints(bp);
2005 static void b44_get_pauseparam(struct net_device *dev,
2006 struct ethtool_pauseparam *epause)
2008 struct b44 *bp = netdev_priv(dev);
2011 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
2013 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
2015 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
2018 static int b44_set_pauseparam(struct net_device *dev,
2019 struct ethtool_pauseparam *epause)
2021 struct b44 *bp = netdev_priv(dev);
2023 spin_lock_irq(&bp->lock);
2024 if (epause->autoneg)
2025 bp->flags |= B44_FLAG_PAUSE_AUTO;
2027 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
2028 if (epause->rx_pause)
2029 bp->flags |= B44_FLAG_RX_PAUSE;
2031 bp->flags &= ~B44_FLAG_RX_PAUSE;
2032 if (epause->tx_pause)
2033 bp->flags |= B44_FLAG_TX_PAUSE;
2035 bp->flags &= ~B44_FLAG_TX_PAUSE;
2036 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
2039 b44_init_hw(bp, B44_FULL_RESET);
2041 __b44_set_flow_ctrl(bp, bp->flags);
2043 spin_unlock_irq(&bp->lock);
2045 b44_enable_ints(bp);
2050 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2054 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
2059 static int b44_get_sset_count(struct net_device *dev, int sset)
2063 return ARRAY_SIZE(b44_gstrings);
2069 static void b44_get_ethtool_stats(struct net_device *dev,
2070 struct ethtool_stats *stats, u64 *data)
2072 struct b44 *bp = netdev_priv(dev);
2073 struct b44_hw_stats *hwstat = &bp->hw_stats;
2074 u64 *data_src, *data_dst;
2078 spin_lock_irq(&bp->lock);
2079 b44_stats_update(bp);
2080 spin_unlock_irq(&bp->lock);
2083 data_src = &hwstat->tx_good_octets;
2085 start = u64_stats_fetch_begin_irq(&hwstat->syncp);
2087 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2088 *data_dst++ = *data_src++;
2090 } while (u64_stats_fetch_retry_irq(&hwstat->syncp, start));
2093 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2095 struct b44 *bp = netdev_priv(dev);
2097 wol->supported = WAKE_MAGIC;
2098 if (bp->flags & B44_FLAG_WOL_ENABLE)
2099 wol->wolopts = WAKE_MAGIC;
2102 memset(&wol->sopass, 0, sizeof(wol->sopass));
2105 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2107 struct b44 *bp = netdev_priv(dev);
2109 spin_lock_irq(&bp->lock);
2110 if (wol->wolopts & WAKE_MAGIC)
2111 bp->flags |= B44_FLAG_WOL_ENABLE;
2113 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2114 spin_unlock_irq(&bp->lock);
2116 device_set_wakeup_enable(bp->sdev->dev, wol->wolopts & WAKE_MAGIC);
2120 static const struct ethtool_ops b44_ethtool_ops = {
2121 .get_drvinfo = b44_get_drvinfo,
2122 .nway_reset = b44_nway_reset,
2123 .get_link = ethtool_op_get_link,
2124 .get_wol = b44_get_wol,
2125 .set_wol = b44_set_wol,
2126 .get_ringparam = b44_get_ringparam,
2127 .set_ringparam = b44_set_ringparam,
2128 .get_pauseparam = b44_get_pauseparam,
2129 .set_pauseparam = b44_set_pauseparam,
2130 .get_msglevel = b44_get_msglevel,
2131 .set_msglevel = b44_set_msglevel,
2132 .get_strings = b44_get_strings,
2133 .get_sset_count = b44_get_sset_count,
2134 .get_ethtool_stats = b44_get_ethtool_stats,
2135 .get_link_ksettings = b44_get_link_ksettings,
2136 .set_link_ksettings = b44_set_link_ksettings,
2139 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2141 struct b44 *bp = netdev_priv(dev);
2144 if (!netif_running(dev))
2147 spin_lock_irq(&bp->lock);
2148 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
2149 BUG_ON(!dev->phydev);
2150 err = phy_mii_ioctl(dev->phydev, ifr, cmd);
2152 err = generic_mii_ioctl(&bp->mii_if, if_mii(ifr), cmd, NULL);
2154 spin_unlock_irq(&bp->lock);
2159 static int b44_get_invariants(struct b44 *bp)
2161 struct ssb_device *sdev = bp->sdev;
2165 bp->dma_offset = ssb_dma_translation(sdev);
2167 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2169 addr = sdev->bus->sprom.et1mac;
2170 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2172 addr = sdev->bus->sprom.et0mac;
2173 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2175 /* Some ROMs have buggy PHY addresses with the high
2176 * bits set (sign extension?). Truncate them to a
2177 * valid PHY address. */
2178 bp->phy_addr &= 0x1F;
2180 eth_hw_addr_set(bp->dev, addr);
2182 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2183 pr_err("Invalid MAC address found in EEPROM\n");
2187 bp->imask = IMASK_DEF;
2189 /* XXX - really required?
2190 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2193 if (bp->sdev->id.revision >= 7)
2194 bp->flags |= B44_FLAG_B0_ANDLATER;
2199 static const struct net_device_ops b44_netdev_ops = {
2200 .ndo_open = b44_open,
2201 .ndo_stop = b44_close,
2202 .ndo_start_xmit = b44_start_xmit,
2203 .ndo_get_stats64 = b44_get_stats64,
2204 .ndo_set_rx_mode = b44_set_rx_mode,
2205 .ndo_set_mac_address = b44_set_mac_addr,
2206 .ndo_validate_addr = eth_validate_addr,
2207 .ndo_eth_ioctl = b44_ioctl,
2208 .ndo_tx_timeout = b44_tx_timeout,
2209 .ndo_change_mtu = b44_change_mtu,
2210 #ifdef CONFIG_NET_POLL_CONTROLLER
2211 .ndo_poll_controller = b44_poll_controller,
2215 static void b44_adjust_link(struct net_device *dev)
2217 struct b44 *bp = netdev_priv(dev);
2218 struct phy_device *phydev = dev->phydev;
2219 bool status_changed = false;
2223 if (bp->old_link != phydev->link) {
2224 status_changed = true;
2225 bp->old_link = phydev->link;
2228 /* reflect duplex change */
2230 if ((phydev->duplex == DUPLEX_HALF) &&
2231 (bp->flags & B44_FLAG_FULL_DUPLEX)) {
2232 status_changed = true;
2233 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
2234 } else if ((phydev->duplex == DUPLEX_FULL) &&
2235 !(bp->flags & B44_FLAG_FULL_DUPLEX)) {
2236 status_changed = true;
2237 bp->flags |= B44_FLAG_FULL_DUPLEX;
2241 if (status_changed) {
2242 u32 val = br32(bp, B44_TX_CTRL);
2243 if (bp->flags & B44_FLAG_FULL_DUPLEX)
2244 val |= TX_CTRL_DUPLEX;
2246 val &= ~TX_CTRL_DUPLEX;
2247 bw32(bp, B44_TX_CTRL, val);
2248 phy_print_status(phydev);
2252 static int b44_register_phy_one(struct b44 *bp)
2254 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2255 struct mii_bus *mii_bus;
2256 struct ssb_device *sdev = bp->sdev;
2257 struct phy_device *phydev;
2258 char bus_id[MII_BUS_ID_SIZE + 3];
2259 struct ssb_sprom *sprom = &sdev->bus->sprom;
2262 mii_bus = mdiobus_alloc();
2264 dev_err(sdev->dev, "mdiobus_alloc() failed\n");
2270 mii_bus->read = b44_mdio_read_phylib;
2271 mii_bus->write = b44_mdio_write_phylib;
2272 mii_bus->name = "b44_eth_mii";
2273 mii_bus->parent = sdev->dev;
2274 mii_bus->phy_mask = ~(1 << bp->phy_addr);
2275 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%x", instance);
2277 bp->mii_bus = mii_bus;
2279 err = mdiobus_register(mii_bus);
2281 dev_err(sdev->dev, "failed to register MII bus\n");
2282 goto err_out_mdiobus;
2285 if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
2286 (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
2289 "could not find PHY at %i, use fixed one\n",
2293 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, "fixed-0",
2296 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
2300 phydev = phy_connect(bp->dev, bus_id, &b44_adjust_link,
2301 PHY_INTERFACE_MODE_MII);
2302 if (IS_ERR(phydev)) {
2303 dev_err(sdev->dev, "could not attach PHY at %i\n",
2305 err = PTR_ERR(phydev);
2306 goto err_out_mdiobus_unregister;
2309 /* mask with MAC supported features */
2310 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
2311 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
2312 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
2313 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
2314 linkmode_and(phydev->supported, phydev->supported, mask);
2315 linkmode_copy(phydev->advertising, phydev->supported);
2318 bp->phy_addr = phydev->mdio.addr;
2320 phy_attached_info(phydev);
2324 err_out_mdiobus_unregister:
2325 mdiobus_unregister(mii_bus);
2328 mdiobus_free(mii_bus);
2334 static void b44_unregister_phy_one(struct b44 *bp)
2336 struct net_device *dev = bp->dev;
2337 struct mii_bus *mii_bus = bp->mii_bus;
2339 phy_disconnect(dev->phydev);
2340 mdiobus_unregister(mii_bus);
2341 mdiobus_free(mii_bus);
2344 static int b44_init_one(struct ssb_device *sdev,
2345 const struct ssb_device_id *ent)
2347 struct net_device *dev;
2353 dev = alloc_etherdev(sizeof(*bp));
2359 SET_NETDEV_DEV(dev, sdev->dev);
2361 /* No interesting netdevice features in this card... */
2364 bp = netdev_priv(dev);
2367 bp->force_copybreak = 0;
2369 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2371 spin_lock_init(&bp->lock);
2372 u64_stats_init(&bp->hw_stats.syncp);
2374 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2375 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2377 dev->netdev_ops = &b44_netdev_ops;
2378 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2379 dev->watchdog_timeo = B44_TX_TIMEOUT;
2380 dev->min_mtu = B44_MIN_MTU;
2381 dev->max_mtu = B44_MAX_MTU;
2382 dev->irq = sdev->irq;
2383 dev->ethtool_ops = &b44_ethtool_ops;
2385 err = ssb_bus_powerup(sdev->bus, 0);
2388 "Failed to powerup the bus\n");
2389 goto err_out_free_dev;
2392 err = dma_set_mask_and_coherent(sdev->dma_dev, DMA_BIT_MASK(30));
2395 "Required 30BIT DMA mask unsupported by the system\n");
2396 goto err_out_powerdown;
2399 err = b44_get_invariants(bp);
2402 "Problem fetching invariants of chip, aborting\n");
2403 goto err_out_powerdown;
2406 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
2407 dev_err(sdev->dev, "No PHY present on this MAC, aborting\n");
2409 goto err_out_powerdown;
2412 bp->mii_if.dev = dev;
2413 bp->mii_if.mdio_read = b44_mdio_read_mii;
2414 bp->mii_if.mdio_write = b44_mdio_write_mii;
2415 bp->mii_if.phy_id = bp->phy_addr;
2416 bp->mii_if.phy_id_mask = 0x1f;
2417 bp->mii_if.reg_num_mask = 0x1f;
2419 /* By default, advertise all speed/duplex settings. */
2420 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2421 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2423 /* By default, auto-negotiate PAUSE. */
2424 bp->flags |= B44_FLAG_PAUSE_AUTO;
2426 err = register_netdev(dev);
2428 dev_err(sdev->dev, "Cannot register net device, aborting\n");
2429 goto err_out_powerdown;
2432 netif_carrier_off(dev);
2434 ssb_set_drvdata(sdev, dev);
2436 /* Chip reset provides power to the b44 MAC & PCI cores, which
2437 * is necessary for MAC register access.
2439 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2441 /* do a phy reset to test if there is an active phy */
2442 err = b44_phy_reset(bp);
2444 dev_err(sdev->dev, "phy reset failed\n");
2445 goto err_out_unregister_netdev;
2448 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
2449 err = b44_register_phy_one(bp);
2451 dev_err(sdev->dev, "Cannot register PHY, aborting\n");
2452 goto err_out_unregister_netdev;
2456 device_set_wakeup_capable(sdev->dev, true);
2457 netdev_info(dev, "%s %pM\n", DRV_DESCRIPTION, dev->dev_addr);
2461 err_out_unregister_netdev:
2462 unregister_netdev(dev);
2464 ssb_bus_may_powerdown(sdev->bus);
2467 netif_napi_del(&bp->napi);
2474 static void b44_remove_one(struct ssb_device *sdev)
2476 struct net_device *dev = ssb_get_drvdata(sdev);
2477 struct b44 *bp = netdev_priv(dev);
2479 unregister_netdev(dev);
2480 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
2481 b44_unregister_phy_one(bp);
2482 ssb_device_disable(sdev, 0);
2483 ssb_bus_may_powerdown(sdev->bus);
2484 netif_napi_del(&bp->napi);
2486 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2487 ssb_set_drvdata(sdev, NULL);
2490 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2492 struct net_device *dev = ssb_get_drvdata(sdev);
2493 struct b44 *bp = netdev_priv(dev);
2495 if (!netif_running(dev))
2498 del_timer_sync(&bp->timer);
2500 spin_lock_irq(&bp->lock);
2503 netif_carrier_off(bp->dev);
2504 netif_device_detach(bp->dev);
2507 spin_unlock_irq(&bp->lock);
2509 free_irq(dev->irq, dev);
2510 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2511 b44_init_hw(bp, B44_PARTIAL_RESET);
2515 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2519 static int b44_resume(struct ssb_device *sdev)
2521 struct net_device *dev = ssb_get_drvdata(sdev);
2522 struct b44 *bp = netdev_priv(dev);
2525 rc = ssb_bus_powerup(sdev->bus, 0);
2528 "Failed to powerup the bus\n");
2532 if (!netif_running(dev))
2535 spin_lock_irq(&bp->lock);
2537 b44_init_hw(bp, B44_FULL_RESET);
2538 spin_unlock_irq(&bp->lock);
2541 * As a shared interrupt, the handler can be called immediately. To be
2542 * able to check the interrupt status the hardware must already be
2543 * powered back on (b44_init_hw).
2545 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2547 netdev_err(dev, "request_irq failed\n");
2548 spin_lock_irq(&bp->lock);
2551 spin_unlock_irq(&bp->lock);
2555 netif_device_attach(bp->dev);
2557 b44_enable_ints(bp);
2558 netif_wake_queue(dev);
2560 mod_timer(&bp->timer, jiffies + 1);
2565 static struct ssb_driver b44_ssb_driver = {
2566 .name = DRV_MODULE_NAME,
2567 .id_table = b44_ssb_tbl,
2568 .probe = b44_init_one,
2569 .remove = b44_remove_one,
2570 .suspend = b44_suspend,
2571 .resume = b44_resume,
2574 static inline int __init b44_pci_init(void)
2577 #ifdef CONFIG_B44_PCI
2578 err = ssb_pcihost_register(&b44_pci_driver);
2583 static inline void b44_pci_exit(void)
2585 #ifdef CONFIG_B44_PCI
2586 ssb_pcihost_unregister(&b44_pci_driver);
2590 static int __init b44_init(void)
2592 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2595 /* Setup paramaters for syncing RX/TX DMA descriptors */
2596 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2598 err = b44_pci_init();
2601 err = ssb_driver_register(&b44_ssb_driver);
2607 static void __exit b44_cleanup(void)
2609 ssb_driver_unregister(&b44_ssb_driver);
2613 module_init(b44_init);
2614 module_exit(b44_cleanup);