1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <m@bues.ch>
9 * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
11 * Distribute under GPL.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/netdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/mii.h>
23 #include <linux/if_ether.h>
24 #include <linux/if_vlan.h>
25 #include <linux/etherdevice.h>
26 #include <linux/pci.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/ssb/ssb.h>
32 #include <linux/slab.h>
33 #include <linux/phy.h>
35 #include <linux/uaccess.h>
42 #define DRV_MODULE_NAME "b44"
43 #define DRV_MODULE_VERSION "2.0"
44 #define DRV_DESCRIPTION "Broadcom 44xx/47xx 10/100 PCI ethernet driver"
46 #define B44_DEF_MSG_ENABLE \
56 /* length of time before we decide the hardware is borked,
57 * and dev->tx_timeout() should be called to fix the problem
59 #define B44_TX_TIMEOUT (5 * HZ)
61 /* hardware minimum and maximum for a single frame's data payload */
62 #define B44_MIN_MTU ETH_ZLEN
63 #define B44_MAX_MTU ETH_DATA_LEN
65 #define B44_RX_RING_SIZE 512
66 #define B44_DEF_RX_RING_PENDING 200
67 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
69 #define B44_TX_RING_SIZE 512
70 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
71 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
74 #define TX_RING_GAP(BP) \
75 (B44_TX_RING_SIZE - (BP)->tx_pending)
76 #define TX_BUFFS_AVAIL(BP) \
77 (((BP)->tx_cons <= (BP)->tx_prod) ? \
78 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
79 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
80 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
82 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
83 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
85 /* minimum number of free TX descriptors required to wake up TX process */
86 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
88 /* b44 internal pattern match filter info */
89 #define B44_PATTERN_BASE 0x400
90 #define B44_PATTERN_SIZE 0x80
91 #define B44_PMASK_BASE 0x600
92 #define B44_PMASK_SIZE 0x10
93 #define B44_MAX_PATTERNS 16
94 #define B44_ETHIPV6UDP_HLEN 62
95 #define B44_ETHIPV4UDP_HLEN 42
97 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
98 MODULE_DESCRIPTION(DRV_DESCRIPTION);
99 MODULE_LICENSE("GPL");
100 MODULE_VERSION(DRV_MODULE_VERSION);
102 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
103 module_param(b44_debug, int, 0);
104 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
107 #ifdef CONFIG_B44_PCI
108 static const struct pci_device_id b44_pci_tbl[] = {
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
110 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
111 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
112 { 0 } /* terminate list with empty entry */
114 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
116 static struct pci_driver b44_pci_driver = {
117 .name = DRV_MODULE_NAME,
118 .id_table = b44_pci_tbl,
120 #endif /* CONFIG_B44_PCI */
122 static const struct ssb_device_id b44_ssb_tbl[] = {
123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
126 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
128 static void b44_halt(struct b44 *);
129 static void b44_init_rings(struct b44 *);
131 #define B44_FULL_RESET 1
132 #define B44_FULL_RESET_SKIP_PHY 2
133 #define B44_PARTIAL_RESET 3
134 #define B44_CHIP_RESET_FULL 4
135 #define B44_CHIP_RESET_PARTIAL 5
137 static void b44_init_hw(struct b44 *, int);
139 static int dma_desc_sync_size;
142 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
143 #define _B44(x...) # x,
148 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
150 unsigned long offset,
151 enum dma_data_direction dir)
153 dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
154 dma_desc_sync_size, dir);
157 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
159 unsigned long offset,
160 enum dma_data_direction dir)
162 dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
163 dma_desc_sync_size, dir);
166 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
168 return ssb_read32(bp->sdev, reg);
171 static inline void bw32(const struct b44 *bp,
172 unsigned long reg, unsigned long val)
174 ssb_write32(bp->sdev, reg, val);
177 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178 u32 bit, unsigned long timeout, const int clear)
182 for (i = 0; i < timeout; i++) {
183 u32 val = br32(bp, reg);
185 if (clear && !(val & bit))
187 if (!clear && (val & bit))
193 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
194 bit, reg, clear ? "clear" : "set");
201 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
205 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
206 (index << CAM_CTRL_INDEX_SHIFT)));
208 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
210 val = br32(bp, B44_CAM_DATA_LO);
212 data[2] = (val >> 24) & 0xFF;
213 data[3] = (val >> 16) & 0xFF;
214 data[4] = (val >> 8) & 0xFF;
215 data[5] = (val >> 0) & 0xFF;
217 val = br32(bp, B44_CAM_DATA_HI);
219 data[0] = (val >> 8) & 0xFF;
220 data[1] = (val >> 0) & 0xFF;
223 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
227 val = ((u32) data[2]) << 24;
228 val |= ((u32) data[3]) << 16;
229 val |= ((u32) data[4]) << 8;
230 val |= ((u32) data[5]) << 0;
231 bw32(bp, B44_CAM_DATA_LO, val);
232 val = (CAM_DATA_HI_VALID |
233 (((u32) data[0]) << 8) |
234 (((u32) data[1]) << 0));
235 bw32(bp, B44_CAM_DATA_HI, val);
236 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
237 (index << CAM_CTRL_INDEX_SHIFT)));
238 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
241 static inline void __b44_disable_ints(struct b44 *bp)
243 bw32(bp, B44_IMASK, 0);
246 static void b44_disable_ints(struct b44 *bp)
248 __b44_disable_ints(bp);
250 /* Flush posted writes. */
254 static void b44_enable_ints(struct b44 *bp)
256 bw32(bp, B44_IMASK, bp->imask);
259 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
263 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
264 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
265 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
266 (phy_addr << MDIO_DATA_PMD_SHIFT) |
267 (reg << MDIO_DATA_RA_SHIFT) |
268 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
269 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
270 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
275 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
277 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
278 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
279 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
280 (phy_addr << MDIO_DATA_PMD_SHIFT) |
281 (reg << MDIO_DATA_RA_SHIFT) |
282 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
283 (val & MDIO_DATA_DATA)));
284 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
287 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
289 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
292 return __b44_readphy(bp, bp->phy_addr, reg, val);
295 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
297 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
300 return __b44_writephy(bp, bp->phy_addr, reg, val);
303 /* miilib interface */
304 static int b44_mdio_read_mii(struct net_device *dev, int phy_id, int location)
307 struct b44 *bp = netdev_priv(dev);
308 int rc = __b44_readphy(bp, phy_id, location, &val);
314 static void b44_mdio_write_mii(struct net_device *dev, int phy_id, int location,
317 struct b44 *bp = netdev_priv(dev);
318 __b44_writephy(bp, phy_id, location, val);
321 static int b44_mdio_read_phylib(struct mii_bus *bus, int phy_id, int location)
324 struct b44 *bp = bus->priv;
325 int rc = __b44_readphy(bp, phy_id, location, &val);
331 static int b44_mdio_write_phylib(struct mii_bus *bus, int phy_id, int location,
334 struct b44 *bp = bus->priv;
335 return __b44_writephy(bp, phy_id, location, val);
338 static int b44_phy_reset(struct b44 *bp)
343 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
345 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
349 err = b44_readphy(bp, MII_BMCR, &val);
351 if (val & BMCR_RESET) {
352 netdev_err(bp->dev, "PHY Reset would not complete\n");
360 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
364 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
365 bp->flags |= pause_flags;
367 val = br32(bp, B44_RXCONFIG);
368 if (pause_flags & B44_FLAG_RX_PAUSE)
369 val |= RXCONFIG_FLOW;
371 val &= ~RXCONFIG_FLOW;
372 bw32(bp, B44_RXCONFIG, val);
374 val = br32(bp, B44_MAC_FLOW);
375 if (pause_flags & B44_FLAG_TX_PAUSE)
376 val |= (MAC_FLOW_PAUSE_ENAB |
377 (0xc0 & MAC_FLOW_RX_HI_WATER));
379 val &= ~MAC_FLOW_PAUSE_ENAB;
380 bw32(bp, B44_MAC_FLOW, val);
383 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
387 /* The driver supports only rx pause by default because
388 the b44 mac tx pause mechanism generates excessive
390 Use ethtool to turn on b44 tx pause if necessary.
392 if ((local & ADVERTISE_PAUSE_CAP) &&
393 (local & ADVERTISE_PAUSE_ASYM)){
394 if ((remote & LPA_PAUSE_ASYM) &&
395 !(remote & LPA_PAUSE_CAP))
396 pause_enab |= B44_FLAG_RX_PAUSE;
399 __b44_set_flow_ctrl(bp, pause_enab);
402 #ifdef CONFIG_BCM47XX
403 #include <linux/bcm47xx_nvram.h>
404 static void b44_wap54g10_workaround(struct b44 *bp)
411 * workaround for bad hardware design in Linksys WAP54G v1.0
412 * see https://dev.openwrt.org/ticket/146
413 * check and reset bit "isolate"
415 if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
417 if (simple_strtoul(buf, NULL, 0) == 2) {
418 err = __b44_readphy(bp, 0, MII_BMCR, &val);
421 if (!(val & BMCR_ISOLATE))
423 val &= ~BMCR_ISOLATE;
424 err = __b44_writephy(bp, 0, MII_BMCR, val);
430 pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
433 static inline void b44_wap54g10_workaround(struct b44 *bp)
438 static int b44_setup_phy(struct b44 *bp)
443 b44_wap54g10_workaround(bp);
445 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
447 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
449 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
450 val & MII_ALEDCTRL_ALLMSK)) != 0)
452 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
454 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
455 val | MII_TLEDCTRL_ENABLE)) != 0)
458 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
459 u32 adv = ADVERTISE_CSMA;
461 if (bp->flags & B44_FLAG_ADV_10HALF)
462 adv |= ADVERTISE_10HALF;
463 if (bp->flags & B44_FLAG_ADV_10FULL)
464 adv |= ADVERTISE_10FULL;
465 if (bp->flags & B44_FLAG_ADV_100HALF)
466 adv |= ADVERTISE_100HALF;
467 if (bp->flags & B44_FLAG_ADV_100FULL)
468 adv |= ADVERTISE_100FULL;
470 if (bp->flags & B44_FLAG_PAUSE_AUTO)
471 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
473 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
475 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
476 BMCR_ANRESTART))) != 0)
481 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
483 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
484 if (bp->flags & B44_FLAG_100_BASE_T)
485 bmcr |= BMCR_SPEED100;
486 if (bp->flags & B44_FLAG_FULL_DUPLEX)
487 bmcr |= BMCR_FULLDPLX;
488 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
491 /* Since we will not be negotiating there is no safe way
492 * to determine if the link partner supports flow control
493 * or not. So just disable it completely in this case.
495 b44_set_flow_ctrl(bp, 0, 0);
502 static void b44_stats_update(struct b44 *bp)
507 val = &bp->hw_stats.tx_good_octets;
508 u64_stats_update_begin(&bp->hw_stats.syncp);
510 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
511 *val++ += br32(bp, reg);
517 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
518 *val++ += br32(bp, reg);
521 u64_stats_update_end(&bp->hw_stats.syncp);
524 static void b44_link_report(struct b44 *bp)
526 if (!netif_carrier_ok(bp->dev)) {
527 netdev_info(bp->dev, "Link is down\n");
529 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
530 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
531 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
533 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
534 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
535 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
539 static void b44_check_phy(struct b44 *bp)
543 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
544 bp->flags |= B44_FLAG_100_BASE_T;
545 if (!netif_carrier_ok(bp->dev)) {
546 u32 val = br32(bp, B44_TX_CTRL);
547 if (bp->flags & B44_FLAG_FULL_DUPLEX)
548 val |= TX_CTRL_DUPLEX;
550 val &= ~TX_CTRL_DUPLEX;
551 bw32(bp, B44_TX_CTRL, val);
552 netif_carrier_on(bp->dev);
558 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
559 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
561 if (aux & MII_AUXCTRL_SPEED)
562 bp->flags |= B44_FLAG_100_BASE_T;
564 bp->flags &= ~B44_FLAG_100_BASE_T;
565 if (aux & MII_AUXCTRL_DUPLEX)
566 bp->flags |= B44_FLAG_FULL_DUPLEX;
568 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
570 if (!netif_carrier_ok(bp->dev) &&
571 (bmsr & BMSR_LSTATUS)) {
572 u32 val = br32(bp, B44_TX_CTRL);
573 u32 local_adv, remote_adv;
575 if (bp->flags & B44_FLAG_FULL_DUPLEX)
576 val |= TX_CTRL_DUPLEX;
578 val &= ~TX_CTRL_DUPLEX;
579 bw32(bp, B44_TX_CTRL, val);
581 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
582 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
583 !b44_readphy(bp, MII_LPA, &remote_adv))
584 b44_set_flow_ctrl(bp, local_adv, remote_adv);
587 netif_carrier_on(bp->dev);
589 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
591 netif_carrier_off(bp->dev);
595 if (bmsr & BMSR_RFAULT)
596 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
598 netdev_warn(bp->dev, "Jabber detected in PHY\n");
602 static void b44_timer(unsigned long __opaque)
604 struct b44 *bp = (struct b44 *) __opaque;
606 spin_lock_irq(&bp->lock);
610 b44_stats_update(bp);
612 spin_unlock_irq(&bp->lock);
614 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
617 static void b44_tx(struct b44 *bp)
620 unsigned bytes_compl = 0, pkts_compl = 0;
622 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
623 cur /= sizeof(struct dma_desc);
625 /* XXX needs updating when NETIF_F_SG is supported */
626 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
627 struct ring_info *rp = &bp->tx_buffers[cons];
628 struct sk_buff *skb = rp->skb;
632 dma_unmap_single(bp->sdev->dma_dev,
638 bytes_compl += skb->len;
641 dev_kfree_skb_irq(skb);
644 netdev_completed_queue(bp->dev, pkts_compl, bytes_compl);
646 if (netif_queue_stopped(bp->dev) &&
647 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
648 netif_wake_queue(bp->dev);
650 bw32(bp, B44_GPTIMER, 0);
653 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
654 * before the DMA address you give it. So we allocate 30 more bytes
655 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
656 * point the chip at 30 bytes past where the rx_header will go.
658 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
661 struct ring_info *src_map, *map;
662 struct rx_header *rh;
670 src_map = &bp->rx_buffers[src_idx];
671 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
672 map = &bp->rx_buffers[dest_idx];
673 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
677 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
681 /* Hardware bug work-around, the chip is unable to do PCI DMA
682 to/from anything above 1GB :-( */
683 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
684 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
686 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
687 dma_unmap_single(bp->sdev->dma_dev, mapping,
688 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
689 dev_kfree_skb_any(skb);
690 skb = alloc_skb(RX_PKT_BUF_SZ, GFP_ATOMIC | GFP_DMA);
693 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
696 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
697 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
698 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
699 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
700 dev_kfree_skb_any(skb);
703 bp->force_copybreak = 1;
706 rh = (struct rx_header *) skb->data;
712 map->mapping = mapping;
717 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
718 if (dest_idx == (B44_RX_RING_SIZE - 1))
719 ctrl |= DESC_CTRL_EOT;
721 dp = &bp->rx_ring[dest_idx];
722 dp->ctrl = cpu_to_le32(ctrl);
723 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
725 if (bp->flags & B44_FLAG_RX_RING_HACK)
726 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
727 dest_idx * sizeof(*dp),
730 return RX_PKT_BUF_SZ;
733 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
735 struct dma_desc *src_desc, *dest_desc;
736 struct ring_info *src_map, *dest_map;
737 struct rx_header *rh;
741 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
742 dest_desc = &bp->rx_ring[dest_idx];
743 dest_map = &bp->rx_buffers[dest_idx];
744 src_desc = &bp->rx_ring[src_idx];
745 src_map = &bp->rx_buffers[src_idx];
747 dest_map->skb = src_map->skb;
748 rh = (struct rx_header *) src_map->skb->data;
751 dest_map->mapping = src_map->mapping;
753 if (bp->flags & B44_FLAG_RX_RING_HACK)
754 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
755 src_idx * sizeof(*src_desc),
758 ctrl = src_desc->ctrl;
759 if (dest_idx == (B44_RX_RING_SIZE - 1))
760 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
762 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
764 dest_desc->ctrl = ctrl;
765 dest_desc->addr = src_desc->addr;
769 if (bp->flags & B44_FLAG_RX_RING_HACK)
770 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
771 dest_idx * sizeof(*dest_desc),
774 dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
779 static int b44_rx(struct b44 *bp, int budget)
785 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
786 prod /= sizeof(struct dma_desc);
789 while (cons != prod && budget > 0) {
790 struct ring_info *rp = &bp->rx_buffers[cons];
791 struct sk_buff *skb = rp->skb;
792 dma_addr_t map = rp->mapping;
793 struct rx_header *rh;
796 dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
799 rh = (struct rx_header *) skb->data;
800 len = le16_to_cpu(rh->len);
801 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
802 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
804 b44_recycle_rx(bp, cons, bp->rx_prod);
806 bp->dev->stats.rx_dropped++;
816 len = le16_to_cpu(rh->len);
817 } while (len == 0 && i++ < 5);
825 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
827 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
830 dma_unmap_single(bp->sdev->dma_dev, map,
831 skb_size, DMA_FROM_DEVICE);
832 /* Leave out rx_header */
833 skb_put(skb, len + RX_PKT_OFFSET);
834 skb_pull(skb, RX_PKT_OFFSET);
836 struct sk_buff *copy_skb;
838 b44_recycle_rx(bp, cons, bp->rx_prod);
839 copy_skb = napi_alloc_skb(&bp->napi, len);
840 if (copy_skb == NULL)
841 goto drop_it_no_recycle;
843 skb_put(copy_skb, len);
844 /* DMA sync done above, copy just the actual packet */
845 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
846 copy_skb->data, len);
849 skb_checksum_none_assert(skb);
850 skb->protocol = eth_type_trans(skb, bp->dev);
851 netif_receive_skb(skb);
855 bp->rx_prod = (bp->rx_prod + 1) &
856 (B44_RX_RING_SIZE - 1);
857 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
861 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
866 static int b44_poll(struct napi_struct *napi, int budget)
868 struct b44 *bp = container_of(napi, struct b44, napi);
872 spin_lock_irqsave(&bp->lock, flags);
874 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
875 /* spin_lock(&bp->tx_lock); */
877 /* spin_unlock(&bp->tx_lock); */
879 if (bp->istat & ISTAT_RFO) { /* fast recovery, in ~20msec */
880 bp->istat &= ~ISTAT_RFO;
881 b44_disable_ints(bp);
882 ssb_device_enable(bp->sdev, 0); /* resets ISTAT_RFO */
884 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
885 netif_wake_queue(bp->dev);
888 spin_unlock_irqrestore(&bp->lock, flags);
891 if (bp->istat & ISTAT_RX)
892 work_done += b44_rx(bp, budget);
894 if (bp->istat & ISTAT_ERRORS) {
895 spin_lock_irqsave(&bp->lock, flags);
898 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
899 netif_wake_queue(bp->dev);
900 spin_unlock_irqrestore(&bp->lock, flags);
904 if (work_done < budget) {
905 napi_complete_done(napi, work_done);
912 static irqreturn_t b44_interrupt(int irq, void *dev_id)
914 struct net_device *dev = dev_id;
915 struct b44 *bp = netdev_priv(dev);
919 spin_lock(&bp->lock);
921 istat = br32(bp, B44_ISTAT);
922 imask = br32(bp, B44_IMASK);
924 /* The interrupt mask register controls which interrupt bits
925 * will actually raise an interrupt to the CPU when set by hw/firmware,
926 * but doesn't mask off the bits.
932 if (unlikely(!netif_running(dev))) {
933 netdev_info(dev, "late interrupt\n");
937 if (napi_schedule_prep(&bp->napi)) {
938 /* NOTE: These writes are posted by the readback of
939 * the ISTAT register below.
942 __b44_disable_ints(bp);
943 __napi_schedule(&bp->napi);
947 bw32(bp, B44_ISTAT, istat);
950 spin_unlock(&bp->lock);
951 return IRQ_RETVAL(handled);
954 static void b44_tx_timeout(struct net_device *dev)
956 struct b44 *bp = netdev_priv(dev);
958 netdev_err(dev, "transmit timed out, resetting\n");
960 spin_lock_irq(&bp->lock);
964 b44_init_hw(bp, B44_FULL_RESET);
966 spin_unlock_irq(&bp->lock);
970 netif_wake_queue(dev);
973 static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
975 struct b44 *bp = netdev_priv(dev);
976 int rc = NETDEV_TX_OK;
978 u32 len, entry, ctrl;
982 spin_lock_irqsave(&bp->lock, flags);
984 /* This is a hard error, log it. */
985 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
986 netif_stop_queue(dev);
987 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
991 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
992 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
993 struct sk_buff *bounce_skb;
995 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
996 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
997 dma_unmap_single(bp->sdev->dma_dev, mapping, len,
1000 bounce_skb = alloc_skb(len, GFP_ATOMIC | GFP_DMA);
1004 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
1005 len, DMA_TO_DEVICE);
1006 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
1007 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
1008 dma_unmap_single(bp->sdev->dma_dev, mapping,
1009 len, DMA_TO_DEVICE);
1010 dev_kfree_skb_any(bounce_skb);
1014 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1015 dev_kfree_skb_any(skb);
1019 entry = bp->tx_prod;
1020 bp->tx_buffers[entry].skb = skb;
1021 bp->tx_buffers[entry].mapping = mapping;
1023 ctrl = (len & DESC_CTRL_LEN);
1024 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1025 if (entry == (B44_TX_RING_SIZE - 1))
1026 ctrl |= DESC_CTRL_EOT;
1028 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1029 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1031 if (bp->flags & B44_FLAG_TX_RING_HACK)
1032 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1033 entry * sizeof(bp->tx_ring[0]),
1036 entry = NEXT_TX(entry);
1038 bp->tx_prod = entry;
1042 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1043 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1044 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1045 if (bp->flags & B44_FLAG_REORDER_BUG)
1046 br32(bp, B44_DMATX_PTR);
1048 netdev_sent_queue(dev, skb->len);
1050 if (TX_BUFFS_AVAIL(bp) < 1)
1051 netif_stop_queue(dev);
1054 spin_unlock_irqrestore(&bp->lock, flags);
1059 rc = NETDEV_TX_BUSY;
1063 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1065 struct b44 *bp = netdev_priv(dev);
1067 if (!netif_running(dev)) {
1068 /* We'll just catch it later when the
1075 spin_lock_irq(&bp->lock);
1079 b44_init_hw(bp, B44_FULL_RESET);
1080 spin_unlock_irq(&bp->lock);
1082 b44_enable_ints(bp);
1087 /* Free up pending packets in all rx/tx rings.
1089 * The chip has been shut down and the driver detached from
1090 * the networking, so no interrupts or new tx packets will
1091 * end up in the driver. bp->lock is not held and we are not
1092 * in an interrupt context and thus may sleep.
1094 static void b44_free_rings(struct b44 *bp)
1096 struct ring_info *rp;
1099 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1100 rp = &bp->rx_buffers[i];
1102 if (rp->skb == NULL)
1104 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
1106 dev_kfree_skb_any(rp->skb);
1110 /* XXX needs changes once NETIF_F_SG is set... */
1111 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1112 rp = &bp->tx_buffers[i];
1114 if (rp->skb == NULL)
1116 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
1118 dev_kfree_skb_any(rp->skb);
1123 /* Initialize tx/rx rings for packet processing.
1125 * The chip has been shut down and the driver detached from
1126 * the networking, so no interrupts or new tx packets will
1127 * end up in the driver.
1129 static void b44_init_rings(struct b44 *bp)
1135 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1136 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1138 if (bp->flags & B44_FLAG_RX_RING_HACK)
1139 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
1140 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1142 if (bp->flags & B44_FLAG_TX_RING_HACK)
1143 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
1144 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1146 for (i = 0; i < bp->rx_pending; i++) {
1147 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1153 * Must not be invoked with interrupt sources disabled and
1154 * the hardware shutdown down.
1156 static void b44_free_consistent(struct b44 *bp)
1158 kfree(bp->rx_buffers);
1159 bp->rx_buffers = NULL;
1160 kfree(bp->tx_buffers);
1161 bp->tx_buffers = NULL;
1163 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1164 dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
1165 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1168 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1169 bp->rx_ring, bp->rx_ring_dma);
1171 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1174 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1175 dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
1176 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1179 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1180 bp->tx_ring, bp->tx_ring_dma);
1182 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1187 * Must not be invoked with interrupt sources disabled and
1188 * the hardware shutdown down. Can sleep.
1190 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1194 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1195 bp->rx_buffers = kzalloc(size, gfp);
1196 if (!bp->rx_buffers)
1199 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1200 bp->tx_buffers = kzalloc(size, gfp);
1201 if (!bp->tx_buffers)
1204 size = DMA_TABLE_BYTES;
1205 bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1206 &bp->rx_ring_dma, gfp);
1208 /* Allocation may have failed due to pci_alloc_consistent
1209 insisting on use of GFP_DMA, which is more restrictive
1210 than necessary... */
1211 struct dma_desc *rx_ring;
1212 dma_addr_t rx_ring_dma;
1214 rx_ring = kzalloc(size, gfp);
1218 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
1222 if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
1223 rx_ring_dma + size > DMA_BIT_MASK(30)) {
1228 bp->rx_ring = rx_ring;
1229 bp->rx_ring_dma = rx_ring_dma;
1230 bp->flags |= B44_FLAG_RX_RING_HACK;
1233 bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1234 &bp->tx_ring_dma, gfp);
1236 /* Allocation may have failed due to ssb_dma_alloc_consistent
1237 insisting on use of GFP_DMA, which is more restrictive
1238 than necessary... */
1239 struct dma_desc *tx_ring;
1240 dma_addr_t tx_ring_dma;
1242 tx_ring = kzalloc(size, gfp);
1246 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
1250 if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
1251 tx_ring_dma + size > DMA_BIT_MASK(30)) {
1256 bp->tx_ring = tx_ring;
1257 bp->tx_ring_dma = tx_ring_dma;
1258 bp->flags |= B44_FLAG_TX_RING_HACK;
1264 b44_free_consistent(bp);
1268 /* bp->lock is held. */
1269 static void b44_clear_stats(struct b44 *bp)
1273 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1274 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1276 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1280 /* bp->lock is held. */
1281 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1283 struct ssb_device *sdev = bp->sdev;
1286 was_enabled = ssb_device_is_enabled(bp->sdev);
1288 ssb_device_enable(bp->sdev, 0);
1289 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1292 bw32(bp, B44_RCV_LAZY, 0);
1293 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1294 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1295 bw32(bp, B44_DMATX_CTRL, 0);
1296 bp->tx_prod = bp->tx_cons = 0;
1297 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1298 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1301 bw32(bp, B44_DMARX_CTRL, 0);
1302 bp->rx_prod = bp->rx_cons = 0;
1305 b44_clear_stats(bp);
1308 * Don't enable PHY if we are doing a partial reset
1309 * we are probably going to power down
1311 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1314 switch (sdev->bus->bustype) {
1315 case SSB_BUSTYPE_SSB:
1316 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1317 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1319 & MDIO_CTRL_MAXF_MASK)));
1321 case SSB_BUSTYPE_PCI:
1322 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1323 (0x0d & MDIO_CTRL_MAXF_MASK)));
1325 case SSB_BUSTYPE_PCMCIA:
1326 case SSB_BUSTYPE_SDIO:
1327 WARN_ON(1); /* A device with this bus does not exist. */
1331 br32(bp, B44_MDIO_CTRL);
1333 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1334 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1335 br32(bp, B44_ENET_CTRL);
1336 bp->flags |= B44_FLAG_EXTERNAL_PHY;
1338 u32 val = br32(bp, B44_DEVCTRL);
1340 if (val & DEVCTRL_EPR) {
1341 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1342 br32(bp, B44_DEVCTRL);
1345 bp->flags &= ~B44_FLAG_EXTERNAL_PHY;
1349 /* bp->lock is held. */
1350 static void b44_halt(struct b44 *bp)
1352 b44_disable_ints(bp);
1355 /* power down PHY */
1356 netdev_info(bp->dev, "powering down PHY\n");
1357 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1358 /* now reset the chip, but without enabling the MAC&PHY
1359 * part of it. This has to be done _after_ we shut down the PHY */
1360 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
1361 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1363 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1366 /* bp->lock is held. */
1367 static void __b44_set_mac_addr(struct b44 *bp)
1369 bw32(bp, B44_CAM_CTRL, 0);
1370 if (!(bp->dev->flags & IFF_PROMISC)) {
1373 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1374 val = br32(bp, B44_CAM_CTRL);
1375 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1379 static int b44_set_mac_addr(struct net_device *dev, void *p)
1381 struct b44 *bp = netdev_priv(dev);
1382 struct sockaddr *addr = p;
1385 if (netif_running(dev))
1388 if (!is_valid_ether_addr(addr->sa_data))
1391 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1393 spin_lock_irq(&bp->lock);
1395 val = br32(bp, B44_RXCONFIG);
1396 if (!(val & RXCONFIG_CAM_ABSENT))
1397 __b44_set_mac_addr(bp);
1399 spin_unlock_irq(&bp->lock);
1404 /* Called at device open time to get the chip ready for
1405 * packet processing. Invoked with bp->lock held.
1407 static void __b44_set_rx_mode(struct net_device *);
1408 static void b44_init_hw(struct b44 *bp, int reset_kind)
1412 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1413 if (reset_kind == B44_FULL_RESET) {
1418 /* Enable CRC32, set proper LED modes and power on PHY */
1419 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1420 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1422 /* This sets the MAC address too. */
1423 __b44_set_rx_mode(bp->dev);
1425 /* MTU + eth header + possible VLAN tag + struct rx_header */
1426 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1427 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1429 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1430 if (reset_kind == B44_PARTIAL_RESET) {
1431 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1432 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1434 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1435 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1436 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1437 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1438 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1440 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1441 bp->rx_prod = bp->rx_pending;
1443 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1446 val = br32(bp, B44_ENET_CTRL);
1447 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1449 netdev_reset_queue(bp->dev);
1452 static int b44_open(struct net_device *dev)
1454 struct b44 *bp = netdev_priv(dev);
1457 err = b44_alloc_consistent(bp, GFP_KERNEL);
1461 napi_enable(&bp->napi);
1464 b44_init_hw(bp, B44_FULL_RESET);
1468 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1469 if (unlikely(err < 0)) {
1470 napi_disable(&bp->napi);
1471 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1473 b44_free_consistent(bp);
1477 init_timer(&bp->timer);
1478 bp->timer.expires = jiffies + HZ;
1479 bp->timer.data = (unsigned long) bp;
1480 bp->timer.function = b44_timer;
1481 add_timer(&bp->timer);
1483 b44_enable_ints(bp);
1485 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
1486 phy_start(dev->phydev);
1488 netif_start_queue(dev);
1493 #ifdef CONFIG_NET_POLL_CONTROLLER
1495 * Polling receive - used by netconsole and other diagnostic tools
1496 * to allow network i/o with interrupts disabled.
1498 static void b44_poll_controller(struct net_device *dev)
1500 disable_irq(dev->irq);
1501 b44_interrupt(dev->irq, dev);
1502 enable_irq(dev->irq);
1506 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1509 u32 *pattern = (u32 *) pp;
1511 for (i = 0; i < bytes; i += sizeof(u32)) {
1512 bw32(bp, B44_FILT_ADDR, table_offset + i);
1513 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1517 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1520 int k, j, len = offset;
1521 int ethaddr_bytes = ETH_ALEN;
1523 memset(ppattern + offset, 0xff, magicsync);
1524 for (j = 0; j < magicsync; j++) {
1525 pmask[len >> 3] |= BIT(len & 7);
1529 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1530 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1531 ethaddr_bytes = ETH_ALEN;
1533 ethaddr_bytes = B44_PATTERN_SIZE - len;
1534 if (ethaddr_bytes <=0)
1536 for (k = 0; k< ethaddr_bytes; k++) {
1537 ppattern[offset + magicsync +
1538 (j * ETH_ALEN) + k] = macaddr[k];
1539 pmask[len >> 3] |= BIT(len & 7);
1546 /* Setup magic packet patterns in the b44 WOL
1547 * pattern matching filter.
1549 static void b44_setup_pseudo_magicp(struct b44 *bp)
1553 int plen0, plen1, plen2;
1555 u8 pwol_mask[B44_PMASK_SIZE];
1557 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1561 /* Ipv4 magic packet pattern - pattern 0.*/
1562 memset(pwol_mask, 0, B44_PMASK_SIZE);
1563 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1564 B44_ETHIPV4UDP_HLEN);
1566 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1567 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1569 /* Raw ethernet II magic packet pattern - pattern 1 */
1570 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1571 memset(pwol_mask, 0, B44_PMASK_SIZE);
1572 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1575 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1576 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1577 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1578 B44_PMASK_BASE + B44_PMASK_SIZE);
1580 /* Ipv6 magic packet pattern - pattern 2 */
1581 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1582 memset(pwol_mask, 0, B44_PMASK_SIZE);
1583 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1584 B44_ETHIPV6UDP_HLEN);
1586 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1587 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1588 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1589 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1591 kfree(pwol_pattern);
1593 /* set these pattern's lengths: one less than each real length */
1594 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1595 bw32(bp, B44_WKUP_LEN, val);
1597 /* enable wakeup pattern matching */
1598 val = br32(bp, B44_DEVCTRL);
1599 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1603 #ifdef CONFIG_B44_PCI
1604 static void b44_setup_wol_pci(struct b44 *bp)
1608 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1609 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1610 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1611 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1615 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1616 #endif /* CONFIG_B44_PCI */
1618 static void b44_setup_wol(struct b44 *bp)
1622 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1624 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1626 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1628 val = bp->dev->dev_addr[2] << 24 |
1629 bp->dev->dev_addr[3] << 16 |
1630 bp->dev->dev_addr[4] << 8 |
1631 bp->dev->dev_addr[5];
1632 bw32(bp, B44_ADDR_LO, val);
1634 val = bp->dev->dev_addr[0] << 8 |
1635 bp->dev->dev_addr[1];
1636 bw32(bp, B44_ADDR_HI, val);
1638 val = br32(bp, B44_DEVCTRL);
1639 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1642 b44_setup_pseudo_magicp(bp);
1644 b44_setup_wol_pci(bp);
1647 static int b44_close(struct net_device *dev)
1649 struct b44 *bp = netdev_priv(dev);
1651 netif_stop_queue(dev);
1653 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
1654 phy_stop(dev->phydev);
1656 napi_disable(&bp->napi);
1658 del_timer_sync(&bp->timer);
1660 spin_lock_irq(&bp->lock);
1664 netif_carrier_off(dev);
1666 spin_unlock_irq(&bp->lock);
1668 free_irq(dev->irq, dev);
1670 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1671 b44_init_hw(bp, B44_PARTIAL_RESET);
1675 b44_free_consistent(bp);
1680 static void b44_get_stats64(struct net_device *dev,
1681 struct rtnl_link_stats64 *nstat)
1683 struct b44 *bp = netdev_priv(dev);
1684 struct b44_hw_stats *hwstat = &bp->hw_stats;
1688 start = u64_stats_fetch_begin_irq(&hwstat->syncp);
1690 /* Convert HW stats into rtnl_link_stats64 stats. */
1691 nstat->rx_packets = hwstat->rx_pkts;
1692 nstat->tx_packets = hwstat->tx_pkts;
1693 nstat->rx_bytes = hwstat->rx_octets;
1694 nstat->tx_bytes = hwstat->tx_octets;
1695 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1696 hwstat->tx_oversize_pkts +
1697 hwstat->tx_underruns +
1698 hwstat->tx_excessive_cols +
1699 hwstat->tx_late_cols);
1700 nstat->multicast = hwstat->rx_multicast_pkts;
1701 nstat->collisions = hwstat->tx_total_cols;
1703 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1704 hwstat->rx_undersize);
1705 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1706 nstat->rx_frame_errors = hwstat->rx_align_errs;
1707 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1708 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1709 hwstat->rx_oversize_pkts +
1710 hwstat->rx_missed_pkts +
1711 hwstat->rx_crc_align_errs +
1712 hwstat->rx_undersize +
1713 hwstat->rx_crc_errs +
1714 hwstat->rx_align_errs +
1715 hwstat->rx_symbol_errs);
1717 nstat->tx_aborted_errors = hwstat->tx_underruns;
1719 /* Carrier lost counter seems to be broken for some devices */
1720 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1722 } while (u64_stats_fetch_retry_irq(&hwstat->syncp, start));
1726 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1728 struct netdev_hw_addr *ha;
1731 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
1733 netdev_for_each_mc_addr(ha, dev) {
1736 __b44_cam_write(bp, ha->addr, i++ + 1);
1741 static void __b44_set_rx_mode(struct net_device *dev)
1743 struct b44 *bp = netdev_priv(dev);
1746 val = br32(bp, B44_RXCONFIG);
1747 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1748 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1749 val |= RXCONFIG_PROMISC;
1750 bw32(bp, B44_RXCONFIG, val);
1752 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1755 __b44_set_mac_addr(bp);
1757 if ((dev->flags & IFF_ALLMULTI) ||
1758 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1759 val |= RXCONFIG_ALLMULTI;
1761 i = __b44_load_mcast(bp, dev);
1764 __b44_cam_write(bp, zero, i);
1766 bw32(bp, B44_RXCONFIG, val);
1767 val = br32(bp, B44_CAM_CTRL);
1768 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1772 static void b44_set_rx_mode(struct net_device *dev)
1774 struct b44 *bp = netdev_priv(dev);
1776 spin_lock_irq(&bp->lock);
1777 __b44_set_rx_mode(dev);
1778 spin_unlock_irq(&bp->lock);
1781 static u32 b44_get_msglevel(struct net_device *dev)
1783 struct b44 *bp = netdev_priv(dev);
1784 return bp->msg_enable;
1787 static void b44_set_msglevel(struct net_device *dev, u32 value)
1789 struct b44 *bp = netdev_priv(dev);
1790 bp->msg_enable = value;
1793 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1795 struct b44 *bp = netdev_priv(dev);
1796 struct ssb_bus *bus = bp->sdev->bus;
1798 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1799 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1800 switch (bus->bustype) {
1801 case SSB_BUSTYPE_PCI:
1802 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1804 case SSB_BUSTYPE_SSB:
1805 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1807 case SSB_BUSTYPE_PCMCIA:
1808 case SSB_BUSTYPE_SDIO:
1809 WARN_ON(1); /* A device with this bus does not exist. */
1814 static int b44_nway_reset(struct net_device *dev)
1816 struct b44 *bp = netdev_priv(dev);
1820 spin_lock_irq(&bp->lock);
1821 b44_readphy(bp, MII_BMCR, &bmcr);
1822 b44_readphy(bp, MII_BMCR, &bmcr);
1824 if (bmcr & BMCR_ANENABLE) {
1825 b44_writephy(bp, MII_BMCR,
1826 bmcr | BMCR_ANRESTART);
1829 spin_unlock_irq(&bp->lock);
1834 static int b44_get_link_ksettings(struct net_device *dev,
1835 struct ethtool_link_ksettings *cmd)
1837 struct b44 *bp = netdev_priv(dev);
1838 u32 supported, advertising;
1840 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
1841 BUG_ON(!dev->phydev);
1842 phy_ethtool_ksettings_get(dev->phydev, cmd);
1847 supported = (SUPPORTED_Autoneg);
1848 supported |= (SUPPORTED_100baseT_Half |
1849 SUPPORTED_100baseT_Full |
1850 SUPPORTED_10baseT_Half |
1851 SUPPORTED_10baseT_Full |
1855 if (bp->flags & B44_FLAG_ADV_10HALF)
1856 advertising |= ADVERTISED_10baseT_Half;
1857 if (bp->flags & B44_FLAG_ADV_10FULL)
1858 advertising |= ADVERTISED_10baseT_Full;
1859 if (bp->flags & B44_FLAG_ADV_100HALF)
1860 advertising |= ADVERTISED_100baseT_Half;
1861 if (bp->flags & B44_FLAG_ADV_100FULL)
1862 advertising |= ADVERTISED_100baseT_Full;
1863 advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1864 cmd->base.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1865 SPEED_100 : SPEED_10;
1866 cmd->base.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1867 DUPLEX_FULL : DUPLEX_HALF;
1869 cmd->base.phy_address = bp->phy_addr;
1870 cmd->base.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1871 AUTONEG_DISABLE : AUTONEG_ENABLE;
1872 if (cmd->base.autoneg == AUTONEG_ENABLE)
1873 advertising |= ADVERTISED_Autoneg;
1875 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1877 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1880 if (!netif_running(dev)){
1881 cmd->base.speed = 0;
1882 cmd->base.duplex = 0xff;
1888 static int b44_set_link_ksettings(struct net_device *dev,
1889 const struct ethtool_link_ksettings *cmd)
1891 struct b44 *bp = netdev_priv(dev);
1896 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
1897 BUG_ON(!dev->phydev);
1898 spin_lock_irq(&bp->lock);
1899 if (netif_running(dev))
1902 ret = phy_ethtool_ksettings_set(dev->phydev, cmd);
1904 spin_unlock_irq(&bp->lock);
1909 speed = cmd->base.speed;
1911 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1912 cmd->link_modes.advertising);
1914 /* We do not support gigabit. */
1915 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1917 (ADVERTISED_1000baseT_Half |
1918 ADVERTISED_1000baseT_Full))
1920 } else if ((speed != SPEED_100 &&
1921 speed != SPEED_10) ||
1922 (cmd->base.duplex != DUPLEX_HALF &&
1923 cmd->base.duplex != DUPLEX_FULL)) {
1927 spin_lock_irq(&bp->lock);
1929 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1930 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1931 B44_FLAG_100_BASE_T |
1932 B44_FLAG_FULL_DUPLEX |
1933 B44_FLAG_ADV_10HALF |
1934 B44_FLAG_ADV_10FULL |
1935 B44_FLAG_ADV_100HALF |
1936 B44_FLAG_ADV_100FULL);
1937 if (advertising == 0) {
1938 bp->flags |= (B44_FLAG_ADV_10HALF |
1939 B44_FLAG_ADV_10FULL |
1940 B44_FLAG_ADV_100HALF |
1941 B44_FLAG_ADV_100FULL);
1943 if (advertising & ADVERTISED_10baseT_Half)
1944 bp->flags |= B44_FLAG_ADV_10HALF;
1945 if (advertising & ADVERTISED_10baseT_Full)
1946 bp->flags |= B44_FLAG_ADV_10FULL;
1947 if (advertising & ADVERTISED_100baseT_Half)
1948 bp->flags |= B44_FLAG_ADV_100HALF;
1949 if (advertising & ADVERTISED_100baseT_Full)
1950 bp->flags |= B44_FLAG_ADV_100FULL;
1953 bp->flags |= B44_FLAG_FORCE_LINK;
1954 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1955 if (speed == SPEED_100)
1956 bp->flags |= B44_FLAG_100_BASE_T;
1957 if (cmd->base.duplex == DUPLEX_FULL)
1958 bp->flags |= B44_FLAG_FULL_DUPLEX;
1961 if (netif_running(dev))
1964 spin_unlock_irq(&bp->lock);
1969 static void b44_get_ringparam(struct net_device *dev,
1970 struct ethtool_ringparam *ering)
1972 struct b44 *bp = netdev_priv(dev);
1974 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1975 ering->rx_pending = bp->rx_pending;
1977 /* XXX ethtool lacks a tx_max_pending, oops... */
1980 static int b44_set_ringparam(struct net_device *dev,
1981 struct ethtool_ringparam *ering)
1983 struct b44 *bp = netdev_priv(dev);
1985 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1986 (ering->rx_mini_pending != 0) ||
1987 (ering->rx_jumbo_pending != 0) ||
1988 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1991 spin_lock_irq(&bp->lock);
1993 bp->rx_pending = ering->rx_pending;
1994 bp->tx_pending = ering->tx_pending;
1998 b44_init_hw(bp, B44_FULL_RESET);
1999 netif_wake_queue(bp->dev);
2000 spin_unlock_irq(&bp->lock);
2002 b44_enable_ints(bp);
2007 static void b44_get_pauseparam(struct net_device *dev,
2008 struct ethtool_pauseparam *epause)
2010 struct b44 *bp = netdev_priv(dev);
2013 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
2015 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
2017 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
2020 static int b44_set_pauseparam(struct net_device *dev,
2021 struct ethtool_pauseparam *epause)
2023 struct b44 *bp = netdev_priv(dev);
2025 spin_lock_irq(&bp->lock);
2026 if (epause->autoneg)
2027 bp->flags |= B44_FLAG_PAUSE_AUTO;
2029 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
2030 if (epause->rx_pause)
2031 bp->flags |= B44_FLAG_RX_PAUSE;
2033 bp->flags &= ~B44_FLAG_RX_PAUSE;
2034 if (epause->tx_pause)
2035 bp->flags |= B44_FLAG_TX_PAUSE;
2037 bp->flags &= ~B44_FLAG_TX_PAUSE;
2038 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
2041 b44_init_hw(bp, B44_FULL_RESET);
2043 __b44_set_flow_ctrl(bp, bp->flags);
2045 spin_unlock_irq(&bp->lock);
2047 b44_enable_ints(bp);
2052 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2056 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
2061 static int b44_get_sset_count(struct net_device *dev, int sset)
2065 return ARRAY_SIZE(b44_gstrings);
2071 static void b44_get_ethtool_stats(struct net_device *dev,
2072 struct ethtool_stats *stats, u64 *data)
2074 struct b44 *bp = netdev_priv(dev);
2075 struct b44_hw_stats *hwstat = &bp->hw_stats;
2076 u64 *data_src, *data_dst;
2080 spin_lock_irq(&bp->lock);
2081 b44_stats_update(bp);
2082 spin_unlock_irq(&bp->lock);
2085 data_src = &hwstat->tx_good_octets;
2087 start = u64_stats_fetch_begin_irq(&hwstat->syncp);
2089 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2090 *data_dst++ = *data_src++;
2092 } while (u64_stats_fetch_retry_irq(&hwstat->syncp, start));
2095 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2097 struct b44 *bp = netdev_priv(dev);
2099 wol->supported = WAKE_MAGIC;
2100 if (bp->flags & B44_FLAG_WOL_ENABLE)
2101 wol->wolopts = WAKE_MAGIC;
2104 memset(&wol->sopass, 0, sizeof(wol->sopass));
2107 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2109 struct b44 *bp = netdev_priv(dev);
2111 spin_lock_irq(&bp->lock);
2112 if (wol->wolopts & WAKE_MAGIC)
2113 bp->flags |= B44_FLAG_WOL_ENABLE;
2115 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2116 spin_unlock_irq(&bp->lock);
2118 device_set_wakeup_enable(bp->sdev->dev, wol->wolopts & WAKE_MAGIC);
2122 static const struct ethtool_ops b44_ethtool_ops = {
2123 .get_drvinfo = b44_get_drvinfo,
2124 .nway_reset = b44_nway_reset,
2125 .get_link = ethtool_op_get_link,
2126 .get_wol = b44_get_wol,
2127 .set_wol = b44_set_wol,
2128 .get_ringparam = b44_get_ringparam,
2129 .set_ringparam = b44_set_ringparam,
2130 .get_pauseparam = b44_get_pauseparam,
2131 .set_pauseparam = b44_set_pauseparam,
2132 .get_msglevel = b44_get_msglevel,
2133 .set_msglevel = b44_set_msglevel,
2134 .get_strings = b44_get_strings,
2135 .get_sset_count = b44_get_sset_count,
2136 .get_ethtool_stats = b44_get_ethtool_stats,
2137 .get_link_ksettings = b44_get_link_ksettings,
2138 .set_link_ksettings = b44_set_link_ksettings,
2141 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2143 struct b44 *bp = netdev_priv(dev);
2146 if (!netif_running(dev))
2149 spin_lock_irq(&bp->lock);
2150 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
2151 BUG_ON(!dev->phydev);
2152 err = phy_mii_ioctl(dev->phydev, ifr, cmd);
2154 err = generic_mii_ioctl(&bp->mii_if, if_mii(ifr), cmd, NULL);
2156 spin_unlock_irq(&bp->lock);
2161 static int b44_get_invariants(struct b44 *bp)
2163 struct ssb_device *sdev = bp->sdev;
2167 bp->dma_offset = ssb_dma_translation(sdev);
2169 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2171 addr = sdev->bus->sprom.et1mac;
2172 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2174 addr = sdev->bus->sprom.et0mac;
2175 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2177 /* Some ROMs have buggy PHY addresses with the high
2178 * bits set (sign extension?). Truncate them to a
2179 * valid PHY address. */
2180 bp->phy_addr &= 0x1F;
2182 memcpy(bp->dev->dev_addr, addr, ETH_ALEN);
2184 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2185 pr_err("Invalid MAC address found in EEPROM\n");
2189 bp->imask = IMASK_DEF;
2191 /* XXX - really required?
2192 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2195 if (bp->sdev->id.revision >= 7)
2196 bp->flags |= B44_FLAG_B0_ANDLATER;
2201 static const struct net_device_ops b44_netdev_ops = {
2202 .ndo_open = b44_open,
2203 .ndo_stop = b44_close,
2204 .ndo_start_xmit = b44_start_xmit,
2205 .ndo_get_stats64 = b44_get_stats64,
2206 .ndo_set_rx_mode = b44_set_rx_mode,
2207 .ndo_set_mac_address = b44_set_mac_addr,
2208 .ndo_validate_addr = eth_validate_addr,
2209 .ndo_do_ioctl = b44_ioctl,
2210 .ndo_tx_timeout = b44_tx_timeout,
2211 .ndo_change_mtu = b44_change_mtu,
2212 #ifdef CONFIG_NET_POLL_CONTROLLER
2213 .ndo_poll_controller = b44_poll_controller,
2217 static void b44_adjust_link(struct net_device *dev)
2219 struct b44 *bp = netdev_priv(dev);
2220 struct phy_device *phydev = dev->phydev;
2221 bool status_changed = 0;
2225 if (bp->old_link != phydev->link) {
2227 bp->old_link = phydev->link;
2230 /* reflect duplex change */
2232 if ((phydev->duplex == DUPLEX_HALF) &&
2233 (bp->flags & B44_FLAG_FULL_DUPLEX)) {
2235 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
2236 } else if ((phydev->duplex == DUPLEX_FULL) &&
2237 !(bp->flags & B44_FLAG_FULL_DUPLEX)) {
2239 bp->flags |= B44_FLAG_FULL_DUPLEX;
2243 if (status_changed) {
2244 u32 val = br32(bp, B44_TX_CTRL);
2245 if (bp->flags & B44_FLAG_FULL_DUPLEX)
2246 val |= TX_CTRL_DUPLEX;
2248 val &= ~TX_CTRL_DUPLEX;
2249 bw32(bp, B44_TX_CTRL, val);
2250 phy_print_status(phydev);
2254 static int b44_register_phy_one(struct b44 *bp)
2256 struct mii_bus *mii_bus;
2257 struct ssb_device *sdev = bp->sdev;
2258 struct phy_device *phydev;
2259 char bus_id[MII_BUS_ID_SIZE + 3];
2260 struct ssb_sprom *sprom = &sdev->bus->sprom;
2263 mii_bus = mdiobus_alloc();
2265 dev_err(sdev->dev, "mdiobus_alloc() failed\n");
2271 mii_bus->read = b44_mdio_read_phylib;
2272 mii_bus->write = b44_mdio_write_phylib;
2273 mii_bus->name = "b44_eth_mii";
2274 mii_bus->parent = sdev->dev;
2275 mii_bus->phy_mask = ~(1 << bp->phy_addr);
2276 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%x", instance);
2278 bp->mii_bus = mii_bus;
2280 err = mdiobus_register(mii_bus);
2282 dev_err(sdev->dev, "failed to register MII bus\n");
2283 goto err_out_mdiobus;
2286 if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
2287 (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
2290 "could not find PHY at %i, use fixed one\n",
2294 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, "fixed-0",
2297 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
2301 phydev = phy_connect(bp->dev, bus_id, &b44_adjust_link,
2302 PHY_INTERFACE_MODE_MII);
2303 if (IS_ERR(phydev)) {
2304 dev_err(sdev->dev, "could not attach PHY at %i\n",
2306 err = PTR_ERR(phydev);
2307 goto err_out_mdiobus_unregister;
2310 /* mask with MAC supported features */
2311 phydev->supported &= (SUPPORTED_100baseT_Half |
2312 SUPPORTED_100baseT_Full |
2315 phydev->advertising = phydev->supported;
2318 bp->phy_addr = phydev->mdio.addr;
2320 phy_attached_info(phydev);
2324 err_out_mdiobus_unregister:
2325 mdiobus_unregister(mii_bus);
2328 mdiobus_free(mii_bus);
2334 static void b44_unregister_phy_one(struct b44 *bp)
2336 struct net_device *dev = bp->dev;
2337 struct mii_bus *mii_bus = bp->mii_bus;
2339 phy_disconnect(dev->phydev);
2340 mdiobus_unregister(mii_bus);
2341 mdiobus_free(mii_bus);
2344 static int b44_init_one(struct ssb_device *sdev,
2345 const struct ssb_device_id *ent)
2347 struct net_device *dev;
2353 pr_info_once("%s version %s\n", DRV_DESCRIPTION, DRV_MODULE_VERSION);
2355 dev = alloc_etherdev(sizeof(*bp));
2361 SET_NETDEV_DEV(dev, sdev->dev);
2363 /* No interesting netdevice features in this card... */
2366 bp = netdev_priv(dev);
2369 bp->force_copybreak = 0;
2371 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2373 spin_lock_init(&bp->lock);
2374 u64_stats_init(&bp->hw_stats.syncp);
2376 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2377 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2379 dev->netdev_ops = &b44_netdev_ops;
2380 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2381 dev->watchdog_timeo = B44_TX_TIMEOUT;
2382 dev->min_mtu = B44_MIN_MTU;
2383 dev->max_mtu = B44_MAX_MTU;
2384 dev->irq = sdev->irq;
2385 dev->ethtool_ops = &b44_ethtool_ops;
2387 err = ssb_bus_powerup(sdev->bus, 0);
2390 "Failed to powerup the bus\n");
2391 goto err_out_free_dev;
2394 err = dma_set_mask_and_coherent(sdev->dma_dev, DMA_BIT_MASK(30));
2397 "Required 30BIT DMA mask unsupported by the system\n");
2398 goto err_out_powerdown;
2401 err = b44_get_invariants(bp);
2404 "Problem fetching invariants of chip, aborting\n");
2405 goto err_out_powerdown;
2408 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
2409 dev_err(sdev->dev, "No PHY present on this MAC, aborting\n");
2411 goto err_out_powerdown;
2414 bp->mii_if.dev = dev;
2415 bp->mii_if.mdio_read = b44_mdio_read_mii;
2416 bp->mii_if.mdio_write = b44_mdio_write_mii;
2417 bp->mii_if.phy_id = bp->phy_addr;
2418 bp->mii_if.phy_id_mask = 0x1f;
2419 bp->mii_if.reg_num_mask = 0x1f;
2421 /* By default, advertise all speed/duplex settings. */
2422 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2423 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2425 /* By default, auto-negotiate PAUSE. */
2426 bp->flags |= B44_FLAG_PAUSE_AUTO;
2428 err = register_netdev(dev);
2430 dev_err(sdev->dev, "Cannot register net device, aborting\n");
2431 goto err_out_powerdown;
2434 netif_carrier_off(dev);
2436 ssb_set_drvdata(sdev, dev);
2438 /* Chip reset provides power to the b44 MAC & PCI cores, which
2439 * is necessary for MAC register access.
2441 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2443 /* do a phy reset to test if there is an active phy */
2444 err = b44_phy_reset(bp);
2446 dev_err(sdev->dev, "phy reset failed\n");
2447 goto err_out_unregister_netdev;
2450 if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
2451 err = b44_register_phy_one(bp);
2453 dev_err(sdev->dev, "Cannot register PHY, aborting\n");
2454 goto err_out_unregister_netdev;
2458 device_set_wakeup_capable(sdev->dev, true);
2459 netdev_info(dev, "%s %pM\n", DRV_DESCRIPTION, dev->dev_addr);
2463 err_out_unregister_netdev:
2464 unregister_netdev(dev);
2466 ssb_bus_may_powerdown(sdev->bus);
2469 netif_napi_del(&bp->napi);
2476 static void b44_remove_one(struct ssb_device *sdev)
2478 struct net_device *dev = ssb_get_drvdata(sdev);
2479 struct b44 *bp = netdev_priv(dev);
2481 unregister_netdev(dev);
2482 if (bp->flags & B44_FLAG_EXTERNAL_PHY)
2483 b44_unregister_phy_one(bp);
2484 ssb_device_disable(sdev, 0);
2485 ssb_bus_may_powerdown(sdev->bus);
2486 netif_napi_del(&bp->napi);
2488 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2489 ssb_set_drvdata(sdev, NULL);
2492 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2494 struct net_device *dev = ssb_get_drvdata(sdev);
2495 struct b44 *bp = netdev_priv(dev);
2497 if (!netif_running(dev))
2500 del_timer_sync(&bp->timer);
2502 spin_lock_irq(&bp->lock);
2505 netif_carrier_off(bp->dev);
2506 netif_device_detach(bp->dev);
2509 spin_unlock_irq(&bp->lock);
2511 free_irq(dev->irq, dev);
2512 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2513 b44_init_hw(bp, B44_PARTIAL_RESET);
2517 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2521 static int b44_resume(struct ssb_device *sdev)
2523 struct net_device *dev = ssb_get_drvdata(sdev);
2524 struct b44 *bp = netdev_priv(dev);
2527 rc = ssb_bus_powerup(sdev->bus, 0);
2530 "Failed to powerup the bus\n");
2534 if (!netif_running(dev))
2537 spin_lock_irq(&bp->lock);
2539 b44_init_hw(bp, B44_FULL_RESET);
2540 spin_unlock_irq(&bp->lock);
2543 * As a shared interrupt, the handler can be called immediately. To be
2544 * able to check the interrupt status the hardware must already be
2545 * powered back on (b44_init_hw).
2547 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2549 netdev_err(dev, "request_irq failed\n");
2550 spin_lock_irq(&bp->lock);
2553 spin_unlock_irq(&bp->lock);
2557 netif_device_attach(bp->dev);
2559 b44_enable_ints(bp);
2560 netif_wake_queue(dev);
2562 mod_timer(&bp->timer, jiffies + 1);
2567 static struct ssb_driver b44_ssb_driver = {
2568 .name = DRV_MODULE_NAME,
2569 .id_table = b44_ssb_tbl,
2570 .probe = b44_init_one,
2571 .remove = b44_remove_one,
2572 .suspend = b44_suspend,
2573 .resume = b44_resume,
2576 static inline int __init b44_pci_init(void)
2579 #ifdef CONFIG_B44_PCI
2580 err = ssb_pcihost_register(&b44_pci_driver);
2585 static inline void b44_pci_exit(void)
2587 #ifdef CONFIG_B44_PCI
2588 ssb_pcihost_unregister(&b44_pci_driver);
2592 static int __init b44_init(void)
2594 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2597 /* Setup paramaters for syncing RX/TX DMA descriptors */
2598 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2600 err = b44_pci_init();
2603 err = ssb_driver_register(&b44_ssb_driver);
2609 static void __exit b44_cleanup(void)
2611 ssb_driver_unregister(&b44_ssb_driver);
2615 module_init(b44_init);
2616 module_exit(b44_cleanup);