2 * Copyright (c) 2013, 2021 Johannes Berg <johannes@sipsolutions.net>
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 * This file incorporates work covered by the following copyright and
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
39 #include <linux/ipv6.h>
40 #include <linux/if_vlan.h>
41 #include <linux/mdio.h>
42 #include <linux/bitops.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/crc32.h>
51 static const char alx_drv_name[] = "alx";
53 static void alx_free_txbuf(struct alx_tx_queue *txq, int entry)
55 struct alx_buffer *txb = &txq->bufs[entry];
57 if (dma_unmap_len(txb, size)) {
58 dma_unmap_single(txq->dev,
59 dma_unmap_addr(txb, dma),
60 dma_unmap_len(txb, size),
62 dma_unmap_len_set(txb, size, 0);
66 dev_kfree_skb_any(txb->skb);
71 static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
73 struct alx_rx_queue *rxq = alx->qnapi[0]->rxq;
75 struct alx_buffer *cur_buf;
77 u16 cur, next, count = 0;
79 next = cur = rxq->write_idx;
80 if (++next == alx->rx_ringsz)
82 cur_buf = &rxq->bufs[cur];
84 while (!cur_buf->skb && next != rxq->read_idx) {
85 struct alx_rfd *rfd = &rxq->rfd[cur];
88 * When DMA RX address is set to something like
89 * 0x....fc0, it will be very likely to cause DMA
92 * To work around it, we apply rx skb with 64 bytes
93 * longer space, and offset the address whenever
94 * 0x....fc0 is detected.
96 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size + 64, gfp);
100 if (((unsigned long)skb->data & 0xfff) == 0xfc0)
101 skb_reserve(skb, 64);
103 dma = dma_map_single(&alx->hw.pdev->dev,
104 skb->data, alx->rxbuf_size,
106 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
111 /* Unfortunately, RX descriptor buffers must be 4-byte
112 * aligned, so we can't use IP alignment.
114 if (WARN_ON(dma & 3)) {
120 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
121 dma_unmap_addr_set(cur_buf, dma, dma);
122 rfd->addr = cpu_to_le64(dma);
125 if (++next == alx->rx_ringsz)
127 cur_buf = &rxq->bufs[cur];
132 /* flush all updates before updating hardware */
134 rxq->write_idx = cur;
135 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
141 static struct alx_tx_queue *alx_tx_queue_mapping(struct alx_priv *alx,
144 unsigned int r_idx = skb->queue_mapping;
146 if (r_idx >= alx->num_txq)
147 r_idx = r_idx % alx->num_txq;
149 return alx->qnapi[r_idx]->txq;
152 static struct netdev_queue *alx_get_tx_queue(const struct alx_tx_queue *txq)
154 return netdev_get_tx_queue(txq->netdev, txq->queue_idx);
157 static inline int alx_tpd_avail(struct alx_tx_queue *txq)
159 if (txq->write_idx >= txq->read_idx)
160 return txq->count + txq->read_idx - txq->write_idx - 1;
161 return txq->read_idx - txq->write_idx - 1;
164 static bool alx_clean_tx_irq(struct alx_tx_queue *txq)
166 struct alx_priv *alx;
167 struct netdev_queue *tx_queue;
168 u16 hw_read_idx, sw_read_idx;
169 unsigned int total_bytes = 0, total_packets = 0;
170 int budget = ALX_DEFAULT_TX_WORK;
172 alx = netdev_priv(txq->netdev);
173 tx_queue = alx_get_tx_queue(txq);
175 sw_read_idx = txq->read_idx;
176 hw_read_idx = alx_read_mem16(&alx->hw, txq->c_reg);
178 if (sw_read_idx != hw_read_idx) {
179 while (sw_read_idx != hw_read_idx && budget > 0) {
182 skb = txq->bufs[sw_read_idx].skb;
184 total_bytes += skb->len;
189 alx_free_txbuf(txq, sw_read_idx);
191 if (++sw_read_idx == txq->count)
194 txq->read_idx = sw_read_idx;
196 netdev_tx_completed_queue(tx_queue, total_packets, total_bytes);
199 if (netif_tx_queue_stopped(tx_queue) && netif_carrier_ok(alx->dev) &&
200 alx_tpd_avail(txq) > txq->count / 4)
201 netif_tx_wake_queue(tx_queue);
203 return sw_read_idx == hw_read_idx;
206 static void alx_schedule_link_check(struct alx_priv *alx)
208 schedule_work(&alx->link_check_wk);
211 static void alx_schedule_reset(struct alx_priv *alx)
213 schedule_work(&alx->reset_wk);
216 static int alx_clean_rx_irq(struct alx_rx_queue *rxq, int budget)
218 struct alx_priv *alx;
220 struct alx_buffer *rxb;
222 u16 length, rfd_cleaned = 0;
225 alx = netdev_priv(rxq->netdev);
227 while (work < budget) {
228 rrd = &rxq->rrd[rxq->rrd_read_idx];
229 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
231 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
233 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
234 RRD_SI) != rxq->read_idx ||
235 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
237 alx_schedule_reset(alx);
241 rxb = &rxq->bufs[rxq->read_idx];
242 dma_unmap_single(rxq->dev,
243 dma_unmap_addr(rxb, dma),
244 dma_unmap_len(rxb, size),
246 dma_unmap_len_set(rxb, size, 0);
250 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
251 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
253 dev_kfree_skb_any(skb);
257 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
258 RRD_PKTLEN) - ETH_FCS_LEN;
259 skb_put(skb, length);
260 skb->protocol = eth_type_trans(skb, rxq->netdev);
262 skb_checksum_none_assert(skb);
263 if (alx->dev->features & NETIF_F_RXCSUM &&
264 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
265 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
266 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
268 case RRD_PID_IPV6UDP:
269 case RRD_PID_IPV4UDP:
270 case RRD_PID_IPV4TCP:
271 case RRD_PID_IPV6TCP:
272 skb->ip_summed = CHECKSUM_UNNECESSARY;
277 napi_gro_receive(&rxq->np->napi, skb);
281 if (++rxq->read_idx == rxq->count)
283 if (++rxq->rrd_read_idx == rxq->count)
284 rxq->rrd_read_idx = 0;
286 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
287 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
291 alx_refill_rx_ring(alx, GFP_ATOMIC);
296 static int alx_poll(struct napi_struct *napi, int budget)
298 struct alx_napi *np = container_of(napi, struct alx_napi, napi);
299 struct alx_priv *alx = np->alx;
300 struct alx_hw *hw = &alx->hw;
302 bool tx_complete = true;
306 tx_complete = alx_clean_tx_irq(np->txq);
308 work = alx_clean_rx_irq(np->rxq, budget);
310 if (!tx_complete || work == budget)
313 napi_complete_done(&np->napi, work);
315 /* enable interrupt */
316 if (alx->hw.pdev->msix_enabled) {
317 alx_mask_msix(hw, np->vec_idx, false);
319 spin_lock_irqsave(&alx->irq_lock, flags);
320 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
321 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
322 spin_unlock_irqrestore(&alx->irq_lock, flags);
330 static bool alx_intr_handle_misc(struct alx_priv *alx, u32 intr)
332 struct alx_hw *hw = &alx->hw;
334 if (intr & ALX_ISR_FATAL) {
335 netif_warn(alx, hw, alx->dev,
336 "fatal interrupt 0x%x, resetting\n", intr);
337 alx_schedule_reset(alx);
341 if (intr & ALX_ISR_ALERT)
342 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
344 if (intr & ALX_ISR_PHY) {
345 /* suppress PHY interrupt, because the source
346 * is from PHY internal. only the internal status
347 * is cleared, the interrupt status could be cleared.
349 alx->int_mask &= ~ALX_ISR_PHY;
350 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
351 alx_schedule_link_check(alx);
357 static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
359 struct alx_hw *hw = &alx->hw;
361 spin_lock(&alx->irq_lock);
364 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
365 intr &= alx->int_mask;
367 if (alx_intr_handle_misc(alx, intr))
370 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
371 napi_schedule(&alx->qnapi[0]->napi);
372 /* mask rx/tx interrupt, enable them when napi complete */
373 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
374 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
377 alx_write_mem32(hw, ALX_ISR, 0);
380 spin_unlock(&alx->irq_lock);
384 static irqreturn_t alx_intr_msix_ring(int irq, void *data)
386 struct alx_napi *np = data;
387 struct alx_hw *hw = &np->alx->hw;
389 /* mask interrupt to ACK chip */
390 alx_mask_msix(hw, np->vec_idx, true);
391 /* clear interrupt status */
392 alx_write_mem32(hw, ALX_ISR, np->vec_mask);
394 napi_schedule(&np->napi);
399 static irqreturn_t alx_intr_msix_misc(int irq, void *data)
401 struct alx_priv *alx = data;
402 struct alx_hw *hw = &alx->hw;
405 /* mask interrupt to ACK chip */
406 alx_mask_msix(hw, 0, true);
408 /* read interrupt status */
409 intr = alx_read_mem32(hw, ALX_ISR);
410 intr &= (alx->int_mask & ~ALX_ISR_ALL_QUEUES);
412 if (alx_intr_handle_misc(alx, intr))
415 /* clear interrupt status */
416 alx_write_mem32(hw, ALX_ISR, intr);
418 /* enable interrupt again */
419 alx_mask_msix(hw, 0, false);
424 static irqreturn_t alx_intr_msi(int irq, void *data)
426 struct alx_priv *alx = data;
428 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
431 static irqreturn_t alx_intr_legacy(int irq, void *data)
433 struct alx_priv *alx = data;
434 struct alx_hw *hw = &alx->hw;
437 intr = alx_read_mem32(hw, ALX_ISR);
439 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
442 return alx_intr_handle(alx, intr);
445 static const u16 txring_header_reg[] = {ALX_TPD_PRI0_ADDR_LO,
446 ALX_TPD_PRI1_ADDR_LO,
447 ALX_TPD_PRI2_ADDR_LO,
448 ALX_TPD_PRI3_ADDR_LO};
450 static void alx_init_ring_ptrs(struct alx_priv *alx)
452 struct alx_hw *hw = &alx->hw;
453 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
457 for (i = 0; i < alx->num_napi; i++) {
460 np->txq->read_idx = 0;
461 np->txq->write_idx = 0;
463 txring_header_reg[np->txq->queue_idx],
468 np->rxq->read_idx = 0;
469 np->rxq->write_idx = 0;
470 np->rxq->rrd_read_idx = 0;
471 alx_write_mem32(hw, ALX_RRD_ADDR_LO, np->rxq->rrd_dma);
472 alx_write_mem32(hw, ALX_RFD_ADDR_LO, np->rxq->rfd_dma);
476 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
477 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
479 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
480 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
481 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
482 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
484 /* load these pointers into the chip */
485 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
488 static void alx_free_txring_buf(struct alx_tx_queue *txq)
495 for (i = 0; i < txq->count; i++)
496 alx_free_txbuf(txq, i);
498 memset(txq->bufs, 0, txq->count * sizeof(struct alx_buffer));
499 memset(txq->tpd, 0, txq->count * sizeof(struct alx_txd));
503 netdev_tx_reset_queue(alx_get_tx_queue(txq));
506 static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
508 struct alx_buffer *cur_buf;
514 for (i = 0; i < rxq->count; i++) {
515 cur_buf = rxq->bufs + i;
517 dma_unmap_single(rxq->dev,
518 dma_unmap_addr(cur_buf, dma),
519 dma_unmap_len(cur_buf, size),
521 dev_kfree_skb(cur_buf->skb);
523 dma_unmap_len_set(cur_buf, size, 0);
524 dma_unmap_addr_set(cur_buf, dma, 0);
530 rxq->rrd_read_idx = 0;
533 static void alx_free_buffers(struct alx_priv *alx)
537 for (i = 0; i < alx->num_txq; i++)
538 if (alx->qnapi[i] && alx->qnapi[i]->txq)
539 alx_free_txring_buf(alx->qnapi[i]->txq);
541 if (alx->qnapi[0] && alx->qnapi[0]->rxq)
542 alx_free_rxring_buf(alx->qnapi[0]->rxq);
545 static int alx_reinit_rings(struct alx_priv *alx)
547 alx_free_buffers(alx);
549 alx_init_ring_ptrs(alx);
551 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
557 static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
561 crc32 = ether_crc(ETH_ALEN, addr);
562 reg = (crc32 >> 31) & 0x1;
563 bit = (crc32 >> 26) & 0x1F;
565 mc_hash[reg] |= BIT(bit);
568 static void __alx_set_rx_mode(struct net_device *netdev)
570 struct alx_priv *alx = netdev_priv(netdev);
571 struct alx_hw *hw = &alx->hw;
572 struct netdev_hw_addr *ha;
575 if (!(netdev->flags & IFF_ALLMULTI)) {
576 netdev_for_each_mc_addr(ha, netdev)
577 alx_add_mc_addr(hw, ha->addr, mc_hash);
579 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
580 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
583 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
584 if (netdev->flags & IFF_PROMISC)
585 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
586 if (netdev->flags & IFF_ALLMULTI)
587 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
589 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
592 static void alx_set_rx_mode(struct net_device *netdev)
594 __alx_set_rx_mode(netdev);
597 static int alx_set_mac_address(struct net_device *netdev, void *data)
599 struct alx_priv *alx = netdev_priv(netdev);
600 struct alx_hw *hw = &alx->hw;
601 struct sockaddr *addr = data;
603 if (!is_valid_ether_addr(addr->sa_data))
604 return -EADDRNOTAVAIL;
606 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
607 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
609 eth_hw_addr_set(netdev, addr->sa_data);
610 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
611 alx_set_macaddr(hw, hw->mac_addr);
616 static int alx_alloc_tx_ring(struct alx_priv *alx, struct alx_tx_queue *txq,
619 txq->bufs = kcalloc(txq->count, sizeof(struct alx_buffer), GFP_KERNEL);
623 txq->tpd = alx->descmem.virt + offset;
624 txq->tpd_dma = alx->descmem.dma + offset;
625 offset += sizeof(struct alx_txd) * txq->count;
630 static int alx_alloc_rx_ring(struct alx_priv *alx, struct alx_rx_queue *rxq,
633 rxq->bufs = kcalloc(rxq->count, sizeof(struct alx_buffer), GFP_KERNEL);
637 rxq->rrd = alx->descmem.virt + offset;
638 rxq->rrd_dma = alx->descmem.dma + offset;
639 offset += sizeof(struct alx_rrd) * rxq->count;
641 rxq->rfd = alx->descmem.virt + offset;
642 rxq->rfd_dma = alx->descmem.dma + offset;
643 offset += sizeof(struct alx_rfd) * rxq->count;
648 static int alx_alloc_rings(struct alx_priv *alx)
652 /* physical tx/rx ring descriptors
654 * Allocate them as a single chunk because they must not cross a
655 * 4G boundary (hardware has a single register for high 32 bits
658 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz *
660 sizeof(struct alx_rrd) * alx->rx_ringsz +
661 sizeof(struct alx_rfd) * alx->rx_ringsz;
662 alx->descmem.virt = dma_alloc_coherent(&alx->hw.pdev->dev,
664 &alx->descmem.dma, GFP_KERNEL);
665 if (!alx->descmem.virt)
668 /* alignment requirements */
669 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
670 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
672 for (i = 0; i < alx->num_txq; i++) {
673 offset = alx_alloc_tx_ring(alx, alx->qnapi[i]->txq, offset);
675 netdev_err(alx->dev, "Allocation of tx buffer failed!\n");
680 offset = alx_alloc_rx_ring(alx, alx->qnapi[0]->rxq, offset);
682 netdev_err(alx->dev, "Allocation of rx buffer failed!\n");
689 static void alx_free_rings(struct alx_priv *alx)
693 alx_free_buffers(alx);
695 for (i = 0; i < alx->num_txq; i++)
696 if (alx->qnapi[i] && alx->qnapi[i]->txq)
697 kfree(alx->qnapi[i]->txq->bufs);
699 if (alx->qnapi[0] && alx->qnapi[0]->rxq)
700 kfree(alx->qnapi[0]->rxq->bufs);
702 if (alx->descmem.virt)
703 dma_free_coherent(&alx->hw.pdev->dev,
709 static void alx_free_napis(struct alx_priv *alx)
714 for (i = 0; i < alx->num_napi; i++) {
719 netif_napi_del(&np->napi);
723 alx->qnapi[i] = NULL;
727 static const u16 tx_pidx_reg[] = {ALX_TPD_PRI0_PIDX, ALX_TPD_PRI1_PIDX,
728 ALX_TPD_PRI2_PIDX, ALX_TPD_PRI3_PIDX};
729 static const u16 tx_cidx_reg[] = {ALX_TPD_PRI0_CIDX, ALX_TPD_PRI1_CIDX,
730 ALX_TPD_PRI2_CIDX, ALX_TPD_PRI3_CIDX};
731 static const u32 tx_vect_mask[] = {ALX_ISR_TX_Q0, ALX_ISR_TX_Q1,
732 ALX_ISR_TX_Q2, ALX_ISR_TX_Q3};
733 static const u32 rx_vect_mask[] = {ALX_ISR_RX_Q0, ALX_ISR_RX_Q1,
734 ALX_ISR_RX_Q2, ALX_ISR_RX_Q3,
735 ALX_ISR_RX_Q4, ALX_ISR_RX_Q5,
736 ALX_ISR_RX_Q6, ALX_ISR_RX_Q7};
738 static int alx_alloc_napis(struct alx_priv *alx)
741 struct alx_rx_queue *rxq;
742 struct alx_tx_queue *txq;
745 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
747 /* allocate alx_napi structures */
748 for (i = 0; i < alx->num_napi; i++) {
749 np = kzalloc(sizeof(struct alx_napi), GFP_KERNEL);
754 netif_napi_add(alx->dev, &np->napi, alx_poll);
758 /* allocate tx queues */
759 for (i = 0; i < alx->num_txq; i++) {
761 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
766 txq->p_reg = tx_pidx_reg[i];
767 txq->c_reg = tx_cidx_reg[i];
769 txq->count = alx->tx_ringsz;
770 txq->netdev = alx->dev;
771 txq->dev = &alx->hw.pdev->dev;
772 np->vec_mask |= tx_vect_mask[i];
773 alx->int_mask |= tx_vect_mask[i];
776 /* allocate rx queues */
778 rxq = kzalloc(sizeof(*rxq), GFP_KERNEL);
783 rxq->np = alx->qnapi[0];
785 rxq->count = alx->rx_ringsz;
786 rxq->netdev = alx->dev;
787 rxq->dev = &alx->hw.pdev->dev;
788 np->vec_mask |= rx_vect_mask[0];
789 alx->int_mask |= rx_vect_mask[0];
794 netdev_err(alx->dev, "error allocating internal structures\n");
799 static const int txq_vec_mapping_shift[] = {
800 0, ALX_MSI_MAP_TBL1_TXQ0_SHIFT,
801 0, ALX_MSI_MAP_TBL1_TXQ1_SHIFT,
802 1, ALX_MSI_MAP_TBL2_TXQ2_SHIFT,
803 1, ALX_MSI_MAP_TBL2_TXQ3_SHIFT,
806 static void alx_config_vector_mapping(struct alx_priv *alx)
808 struct alx_hw *hw = &alx->hw;
810 int i, vector, idx, shift;
812 if (alx->hw.pdev->msix_enabled) {
814 for (i = 0, vector = 1; i < alx->num_txq; i++, vector++) {
815 idx = txq_vec_mapping_shift[i * 2];
816 shift = txq_vec_mapping_shift[i * 2 + 1];
817 tbl[idx] |= vector << shift;
821 tbl[0] |= 1 << ALX_MSI_MAP_TBL1_RXQ0_SHIFT;
824 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, tbl[0]);
825 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, tbl[1]);
826 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
829 static int alx_enable_msix(struct alx_priv *alx)
831 int err, num_vec, num_txq, num_rxq;
833 num_txq = min_t(int, num_online_cpus(), ALX_MAX_TX_QUEUES);
835 num_vec = max_t(int, num_txq, num_rxq) + 1;
837 err = pci_alloc_irq_vectors(alx->hw.pdev, num_vec, num_vec,
840 netdev_warn(alx->dev, "Enabling MSI-X interrupts failed!\n");
844 alx->num_vec = num_vec;
845 alx->num_napi = num_vec - 1;
846 alx->num_txq = num_txq;
847 alx->num_rxq = num_rxq;
852 static int alx_request_msix(struct alx_priv *alx)
854 struct net_device *netdev = alx->dev;
855 int i, err, vector = 0, free_vector = 0;
857 err = request_irq(pci_irq_vector(alx->hw.pdev, 0), alx_intr_msix_misc,
858 0, netdev->name, alx);
862 for (i = 0; i < alx->num_napi; i++) {
863 struct alx_napi *np = alx->qnapi[i];
867 if (np->txq && np->rxq)
868 sprintf(np->irq_lbl, "%s-TxRx-%u", netdev->name,
871 sprintf(np->irq_lbl, "%s-tx-%u", netdev->name,
874 sprintf(np->irq_lbl, "%s-rx-%u", netdev->name,
877 sprintf(np->irq_lbl, "%s-unused", netdev->name);
879 np->vec_idx = vector;
880 err = request_irq(pci_irq_vector(alx->hw.pdev, vector),
881 alx_intr_msix_ring, 0, np->irq_lbl, np);
888 free_irq(pci_irq_vector(alx->hw.pdev, free_vector++), alx);
891 for (i = 0; i < vector; i++)
892 free_irq(pci_irq_vector(alx->hw.pdev,free_vector++),
899 static int alx_init_intr(struct alx_priv *alx)
903 ret = pci_alloc_irq_vectors(alx->hw.pdev, 1, 1,
904 PCI_IRQ_MSI | PCI_IRQ_LEGACY);
915 static void alx_irq_enable(struct alx_priv *alx)
917 struct alx_hw *hw = &alx->hw;
920 /* level-1 interrupt switch */
921 alx_write_mem32(hw, ALX_ISR, 0);
922 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
925 if (alx->hw.pdev->msix_enabled) {
926 /* enable all msix irqs */
927 for (i = 0; i < alx->num_vec; i++)
928 alx_mask_msix(hw, i, false);
932 static void alx_irq_disable(struct alx_priv *alx)
934 struct alx_hw *hw = &alx->hw;
937 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
938 alx_write_mem32(hw, ALX_IMR, 0);
941 if (alx->hw.pdev->msix_enabled) {
942 for (i = 0; i < alx->num_vec; i++) {
943 alx_mask_msix(hw, i, true);
944 synchronize_irq(pci_irq_vector(alx->hw.pdev, i));
947 synchronize_irq(pci_irq_vector(alx->hw.pdev, 0));
951 static int alx_realloc_resources(struct alx_priv *alx)
957 pci_free_irq_vectors(alx->hw.pdev);
959 err = alx_init_intr(alx);
963 err = alx_alloc_napis(alx);
967 err = alx_alloc_rings(alx);
974 static int alx_request_irq(struct alx_priv *alx)
976 struct pci_dev *pdev = alx->hw.pdev;
977 struct alx_hw *hw = &alx->hw;
981 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
983 if (alx->hw.pdev->msix_enabled) {
984 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, msi_ctrl);
985 err = alx_request_msix(alx);
989 /* msix request failed, realloc resources */
990 err = alx_realloc_resources(alx);
995 if (alx->hw.pdev->msi_enabled) {
996 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
997 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
998 err = request_irq(pci_irq_vector(pdev, 0), alx_intr_msi, 0,
999 alx->dev->name, alx);
1003 /* fall back to legacy interrupt */
1004 pci_free_irq_vectors(alx->hw.pdev);
1007 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
1008 err = request_irq(pci_irq_vector(pdev, 0), alx_intr_legacy, IRQF_SHARED,
1009 alx->dev->name, alx);
1012 alx_config_vector_mapping(alx);
1014 netdev_err(alx->dev, "IRQ registration failed!\n");
1018 static void alx_free_irq(struct alx_priv *alx)
1020 struct pci_dev *pdev = alx->hw.pdev;
1023 free_irq(pci_irq_vector(pdev, 0), alx);
1024 if (alx->hw.pdev->msix_enabled) {
1025 for (i = 0; i < alx->num_napi; i++)
1026 free_irq(pci_irq_vector(pdev, i + 1), alx->qnapi[i]);
1029 pci_free_irq_vectors(pdev);
1032 static int alx_identify_hw(struct alx_priv *alx)
1034 struct alx_hw *hw = &alx->hw;
1035 int rev = alx_hw_revision(hw);
1037 if (rev > ALX_REV_C0)
1040 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
1045 static int alx_init_sw(struct alx_priv *alx)
1047 struct pci_dev *pdev = alx->hw.pdev;
1048 struct alx_hw *hw = &alx->hw;
1051 err = alx_identify_hw(alx);
1053 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
1058 pdev->device == ALX_DEV_ID_AR8161 &&
1059 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
1060 pdev->subsystem_device == 0x0091 &&
1061 pdev->revision == 0;
1063 hw->smb_timer = 400;
1064 hw->mtu = alx->dev->mtu;
1065 alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu);
1066 /* MTU range: 34 - 9256 */
1067 alx->dev->min_mtu = 34;
1068 alx->dev->max_mtu = ALX_MAX_FRAME_LEN(ALX_MAX_FRAME_SIZE);
1069 alx->tx_ringsz = 256;
1070 alx->rx_ringsz = 512;
1072 alx->int_mask = ALX_ISR_MISC;
1073 hw->dma_chnl = hw->max_dma_chnl;
1074 hw->ith_tpd = alx->tx_ringsz / 3;
1075 hw->link_speed = SPEED_UNKNOWN;
1076 hw->duplex = DUPLEX_UNKNOWN;
1077 hw->adv_cfg = ADVERTISED_Autoneg |
1078 ADVERTISED_10baseT_Half |
1079 ADVERTISED_10baseT_Full |
1080 ADVERTISED_100baseT_Full |
1081 ADVERTISED_100baseT_Half |
1082 ADVERTISED_1000baseT_Full;
1083 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
1085 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
1086 ALX_MAC_CTRL_MHASH_ALG_HI5B |
1087 ALX_MAC_CTRL_BRD_EN |
1088 ALX_MAC_CTRL_PCRCE |
1090 ALX_MAC_CTRL_RXFC_EN |
1091 ALX_MAC_CTRL_TXFC_EN |
1092 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
1093 mutex_init(&alx->mtx);
1099 static netdev_features_t alx_fix_features(struct net_device *netdev,
1100 netdev_features_t features)
1102 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
1103 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1108 static void alx_netif_stop(struct alx_priv *alx)
1112 netif_trans_update(alx->dev);
1113 if (netif_carrier_ok(alx->dev)) {
1114 netif_carrier_off(alx->dev);
1115 netif_tx_disable(alx->dev);
1116 for (i = 0; i < alx->num_napi; i++)
1117 napi_disable(&alx->qnapi[i]->napi);
1121 static void alx_halt(struct alx_priv *alx)
1123 struct alx_hw *hw = &alx->hw;
1125 lockdep_assert_held(&alx->mtx);
1127 alx_netif_stop(alx);
1128 hw->link_speed = SPEED_UNKNOWN;
1129 hw->duplex = DUPLEX_UNKNOWN;
1133 /* disable l0s/l1 */
1134 alx_enable_aspm(hw, false, false);
1135 alx_irq_disable(alx);
1136 alx_free_buffers(alx);
1139 static void alx_configure(struct alx_priv *alx)
1141 struct alx_hw *hw = &alx->hw;
1143 alx_configure_basic(hw);
1144 alx_disable_rss(hw);
1145 __alx_set_rx_mode(alx->dev);
1147 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
1150 static void alx_activate(struct alx_priv *alx)
1152 lockdep_assert_held(&alx->mtx);
1154 /* hardware setting lost, restore it */
1155 alx_reinit_rings(alx);
1158 /* clear old interrupts */
1159 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
1161 alx_irq_enable(alx);
1163 alx_schedule_link_check(alx);
1166 static void alx_reinit(struct alx_priv *alx)
1168 lockdep_assert_held(&alx->mtx);
1174 static int alx_change_mtu(struct net_device *netdev, int mtu)
1176 struct alx_priv *alx = netdev_priv(netdev);
1177 int max_frame = ALX_MAX_FRAME_LEN(mtu);
1181 alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE);
1182 netdev_update_features(netdev);
1183 if (netif_running(netdev)) {
1184 mutex_lock(&alx->mtx);
1186 mutex_unlock(&alx->mtx);
1191 static void alx_netif_start(struct alx_priv *alx)
1195 netif_tx_wake_all_queues(alx->dev);
1196 for (i = 0; i < alx->num_napi; i++)
1197 napi_enable(&alx->qnapi[i]->napi);
1198 netif_carrier_on(alx->dev);
1201 static int __alx_open(struct alx_priv *alx, bool resume)
1205 err = alx_enable_msix(alx);
1207 err = alx_init_intr(alx);
1213 netif_carrier_off(alx->dev);
1215 err = alx_alloc_napis(alx);
1217 goto out_disable_adv_intr;
1219 err = alx_alloc_rings(alx);
1221 goto out_free_rings;
1225 err = alx_request_irq(alx);
1227 goto out_free_rings;
1229 /* must be called after alx_request_irq because the chip stops working
1230 * if we copy the dma addresses in alx_init_ring_ptrs twice when
1231 * requesting msi-x interrupts failed
1233 alx_reinit_rings(alx);
1235 netif_set_real_num_tx_queues(alx->dev, alx->num_txq);
1236 netif_set_real_num_rx_queues(alx->dev, alx->num_rxq);
1238 /* clear old interrupts */
1239 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
1241 alx_irq_enable(alx);
1244 netif_tx_start_all_queues(alx->dev);
1246 alx_schedule_link_check(alx);
1250 alx_free_rings(alx);
1251 alx_free_napis(alx);
1252 out_disable_adv_intr:
1253 pci_free_irq_vectors(alx->hw.pdev);
1257 static void __alx_stop(struct alx_priv *alx)
1259 lockdep_assert_held(&alx->mtx);
1263 cancel_work_sync(&alx->link_check_wk);
1264 cancel_work_sync(&alx->reset_wk);
1267 alx_free_rings(alx);
1268 alx_free_napis(alx);
1271 static const char *alx_speed_desc(struct alx_hw *hw)
1273 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) {
1274 case ADVERTISED_1000baseT_Full:
1275 return "1 Gbps Full";
1276 case ADVERTISED_100baseT_Full:
1277 return "100 Mbps Full";
1278 case ADVERTISED_100baseT_Half:
1279 return "100 Mbps Half";
1280 case ADVERTISED_10baseT_Full:
1281 return "10 Mbps Full";
1282 case ADVERTISED_10baseT_Half:
1283 return "10 Mbps Half";
1285 return "Unknown speed";
1289 static void alx_check_link(struct alx_priv *alx)
1291 struct alx_hw *hw = &alx->hw;
1292 unsigned long flags;
1296 lockdep_assert_held(&alx->mtx);
1298 /* clear PHY internal interrupt status, otherwise the main
1299 * interrupt status will be asserted forever
1301 alx_clear_phy_intr(hw);
1303 old_speed = hw->link_speed;
1304 err = alx_read_phy_link(hw);
1308 spin_lock_irqsave(&alx->irq_lock, flags);
1309 alx->int_mask |= ALX_ISR_PHY;
1310 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
1311 spin_unlock_irqrestore(&alx->irq_lock, flags);
1313 if (old_speed == hw->link_speed)
1316 if (hw->link_speed != SPEED_UNKNOWN) {
1317 netif_info(alx, link, alx->dev,
1318 "NIC Up: %s\n", alx_speed_desc(hw));
1319 alx_post_phy_link(hw);
1320 alx_enable_aspm(hw, true, true);
1323 if (old_speed == SPEED_UNKNOWN)
1324 alx_netif_start(alx);
1326 /* link is now down */
1327 alx_netif_stop(alx);
1328 netif_info(alx, link, alx->dev, "Link Down\n");
1329 err = alx_reset_mac(hw);
1332 alx_irq_disable(alx);
1334 /* MAC reset causes all HW settings to be lost, restore all */
1335 err = alx_reinit_rings(alx);
1339 alx_enable_aspm(hw, false, true);
1340 alx_post_phy_link(hw);
1341 alx_irq_enable(alx);
1347 alx_schedule_reset(alx);
1350 static int alx_open(struct net_device *netdev)
1352 struct alx_priv *alx = netdev_priv(netdev);
1355 mutex_lock(&alx->mtx);
1356 ret = __alx_open(alx, false);
1357 mutex_unlock(&alx->mtx);
1362 static int alx_stop(struct net_device *netdev)
1364 struct alx_priv *alx = netdev_priv(netdev);
1366 mutex_lock(&alx->mtx);
1368 mutex_unlock(&alx->mtx);
1373 static void alx_link_check(struct work_struct *work)
1375 struct alx_priv *alx;
1377 alx = container_of(work, struct alx_priv, link_check_wk);
1379 mutex_lock(&alx->mtx);
1380 alx_check_link(alx);
1381 mutex_unlock(&alx->mtx);
1384 static void alx_reset(struct work_struct *work)
1386 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
1388 mutex_lock(&alx->mtx);
1390 mutex_unlock(&alx->mtx);
1393 static int alx_tpd_req(struct sk_buff *skb)
1397 num = skb_shinfo(skb)->nr_frags + 1;
1398 /* we need one extra descriptor for LSOv2 */
1399 if (skb_is_gso(skb) && skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
1405 static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
1409 if (skb->ip_summed != CHECKSUM_PARTIAL)
1412 cso = skb_checksum_start_offset(skb);
1416 css = cso + skb->csum_offset;
1417 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
1418 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
1419 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1424 static int alx_tso(struct sk_buff *skb, struct alx_txd *first)
1428 if (skb->ip_summed != CHECKSUM_PARTIAL)
1431 if (!skb_is_gso(skb))
1434 err = skb_cow_head(skb, 0);
1438 if (skb->protocol == htons(ETH_P_IP)) {
1439 struct iphdr *iph = ip_hdr(skb);
1442 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1444 first->word1 |= 1 << TPD_IPV4_SHIFT;
1445 } else if (skb_is_gso_v6(skb)) {
1446 tcp_v6_gso_csum_prep(skb);
1447 /* LSOv2: the first TPD only provides the packet length */
1448 first->adrl.l.pkt_len = skb->len;
1449 first->word1 |= 1 << TPD_LSO_V2_SHIFT;
1452 first->word1 |= 1 << TPD_LSO_EN_SHIFT;
1453 first->word1 |= (skb_transport_offset(skb) &
1454 TPD_L4HDROFFSET_MASK) << TPD_L4HDROFFSET_SHIFT;
1455 first->word1 |= (skb_shinfo(skb)->gso_size &
1456 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1460 static int alx_map_tx_skb(struct alx_tx_queue *txq, struct sk_buff *skb)
1462 struct alx_txd *tpd, *first_tpd;
1464 int maplen, f, first_idx = txq->write_idx;
1466 first_tpd = &txq->tpd[txq->write_idx];
1469 if (tpd->word1 & (1 << TPD_LSO_V2_SHIFT)) {
1470 if (++txq->write_idx == txq->count)
1473 tpd = &txq->tpd[txq->write_idx];
1474 tpd->len = first_tpd->len;
1475 tpd->vlan_tag = first_tpd->vlan_tag;
1476 tpd->word1 = first_tpd->word1;
1479 maplen = skb_headlen(skb);
1480 dma = dma_map_single(txq->dev, skb->data, maplen,
1482 if (dma_mapping_error(txq->dev, dma))
1485 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1486 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1488 tpd->adrl.addr = cpu_to_le64(dma);
1489 tpd->len = cpu_to_le16(maplen);
1491 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1492 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1494 if (++txq->write_idx == txq->count)
1496 tpd = &txq->tpd[txq->write_idx];
1498 tpd->word1 = first_tpd->word1;
1500 maplen = skb_frag_size(frag);
1501 dma = skb_frag_dma_map(txq->dev, frag, 0,
1502 maplen, DMA_TO_DEVICE);
1503 if (dma_mapping_error(txq->dev, dma))
1505 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1506 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1508 tpd->adrl.addr = cpu_to_le64(dma);
1509 tpd->len = cpu_to_le16(maplen);
1512 /* last TPD, set EOP flag and store skb */
1513 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1514 txq->bufs[txq->write_idx].skb = skb;
1516 if (++txq->write_idx == txq->count)
1523 while (f != txq->write_idx) {
1524 alx_free_txbuf(txq, f);
1525 if (++f == txq->count)
1531 static netdev_tx_t alx_start_xmit_ring(struct sk_buff *skb,
1532 struct alx_tx_queue *txq)
1534 struct alx_priv *alx;
1535 struct alx_txd *first;
1538 alx = netdev_priv(txq->netdev);
1540 if (alx_tpd_avail(txq) < alx_tpd_req(skb)) {
1541 netif_tx_stop_queue(alx_get_tx_queue(txq));
1545 first = &txq->tpd[txq->write_idx];
1546 memset(first, 0, sizeof(*first));
1548 tso = alx_tso(skb, first);
1551 else if (!tso && alx_tx_csum(skb, first))
1554 if (alx_map_tx_skb(txq, skb) < 0)
1557 netdev_tx_sent_queue(alx_get_tx_queue(txq), skb->len);
1559 /* flush updates before updating hardware */
1561 alx_write_mem16(&alx->hw, txq->p_reg, txq->write_idx);
1563 if (alx_tpd_avail(txq) < txq->count / 8)
1564 netif_tx_stop_queue(alx_get_tx_queue(txq));
1566 return NETDEV_TX_OK;
1569 dev_kfree_skb_any(skb);
1570 return NETDEV_TX_OK;
1573 static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1574 struct net_device *netdev)
1576 struct alx_priv *alx = netdev_priv(netdev);
1577 return alx_start_xmit_ring(skb, alx_tx_queue_mapping(alx, skb));
1580 static void alx_tx_timeout(struct net_device *dev, unsigned int txqueue)
1582 struct alx_priv *alx = netdev_priv(dev);
1584 alx_schedule_reset(alx);
1587 static int alx_mdio_read(struct net_device *netdev,
1588 int prtad, int devad, u16 addr)
1590 struct alx_priv *alx = netdev_priv(netdev);
1591 struct alx_hw *hw = &alx->hw;
1595 if (prtad != hw->mdio.prtad)
1598 if (devad == MDIO_DEVAD_NONE)
1599 err = alx_read_phy_reg(hw, addr, &val);
1601 err = alx_read_phy_ext(hw, devad, addr, &val);
1608 static int alx_mdio_write(struct net_device *netdev,
1609 int prtad, int devad, u16 addr, u16 val)
1611 struct alx_priv *alx = netdev_priv(netdev);
1612 struct alx_hw *hw = &alx->hw;
1614 if (prtad != hw->mdio.prtad)
1617 if (devad == MDIO_DEVAD_NONE)
1618 return alx_write_phy_reg(hw, addr, val);
1620 return alx_write_phy_ext(hw, devad, addr, val);
1623 static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1625 struct alx_priv *alx = netdev_priv(netdev);
1627 if (!netif_running(netdev))
1630 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1633 #ifdef CONFIG_NET_POLL_CONTROLLER
1634 static void alx_poll_controller(struct net_device *netdev)
1636 struct alx_priv *alx = netdev_priv(netdev);
1639 if (alx->hw.pdev->msix_enabled) {
1640 alx_intr_msix_misc(0, alx);
1641 for (i = 0; i < alx->num_txq; i++)
1642 alx_intr_msix_ring(0, alx->qnapi[i]);
1643 } else if (alx->hw.pdev->msi_enabled)
1644 alx_intr_msi(0, alx);
1646 alx_intr_legacy(0, alx);
1650 static void alx_get_stats64(struct net_device *dev,
1651 struct rtnl_link_stats64 *net_stats)
1653 struct alx_priv *alx = netdev_priv(dev);
1654 struct alx_hw_stats *hw_stats = &alx->hw.stats;
1656 spin_lock(&alx->stats_lock);
1658 alx_update_hw_stats(&alx->hw);
1660 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1661 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1662 net_stats->multicast = hw_stats->rx_mcast;
1663 net_stats->collisions = hw_stats->tx_single_col +
1664 hw_stats->tx_multi_col +
1665 hw_stats->tx_late_col +
1666 hw_stats->tx_abort_col;
1668 net_stats->rx_errors = hw_stats->rx_frag +
1669 hw_stats->rx_fcs_err +
1670 hw_stats->rx_len_err +
1671 hw_stats->rx_ov_sz +
1672 hw_stats->rx_ov_rrd +
1673 hw_stats->rx_align_err +
1674 hw_stats->rx_ov_rxf;
1676 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
1677 net_stats->rx_length_errors = hw_stats->rx_len_err;
1678 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1679 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1680 net_stats->rx_dropped = hw_stats->rx_ov_rrd;
1682 net_stats->tx_errors = hw_stats->tx_late_col +
1683 hw_stats->tx_abort_col +
1684 hw_stats->tx_underrun +
1687 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1688 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1689 net_stats->tx_window_errors = hw_stats->tx_late_col;
1691 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1692 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1694 spin_unlock(&alx->stats_lock);
1697 static const struct net_device_ops alx_netdev_ops = {
1698 .ndo_open = alx_open,
1699 .ndo_stop = alx_stop,
1700 .ndo_start_xmit = alx_start_xmit,
1701 .ndo_get_stats64 = alx_get_stats64,
1702 .ndo_set_rx_mode = alx_set_rx_mode,
1703 .ndo_validate_addr = eth_validate_addr,
1704 .ndo_set_mac_address = alx_set_mac_address,
1705 .ndo_change_mtu = alx_change_mtu,
1706 .ndo_eth_ioctl = alx_ioctl,
1707 .ndo_tx_timeout = alx_tx_timeout,
1708 .ndo_fix_features = alx_fix_features,
1709 #ifdef CONFIG_NET_POLL_CONTROLLER
1710 .ndo_poll_controller = alx_poll_controller,
1714 static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1716 struct net_device *netdev;
1717 struct alx_priv *alx;
1719 bool phy_configured;
1722 err = pci_enable_device_mem(pdev);
1726 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1727 * shared register for the high 32 bits, so only a single, aligned,
1728 * 4 GB physical address range can be used for descriptors.
1730 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
1731 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1733 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1735 dev_err(&pdev->dev, "No usable DMA config, aborting\n");
1736 goto out_pci_disable;
1740 err = pci_request_mem_regions(pdev, alx_drv_name);
1743 "pci_request_mem_regions failed\n");
1744 goto out_pci_disable;
1747 pci_set_master(pdev);
1749 if (!pdev->pm_cap) {
1751 "Can't find power management capability, aborting\n");
1753 goto out_pci_release;
1756 netdev = alloc_etherdev_mqs(sizeof(*alx),
1757 ALX_MAX_TX_QUEUES, 1);
1760 goto out_pci_release;
1763 SET_NETDEV_DEV(netdev, &pdev->dev);
1764 alx = netdev_priv(netdev);
1765 spin_lock_init(&alx->hw.mdio_lock);
1766 spin_lock_init(&alx->irq_lock);
1767 spin_lock_init(&alx->stats_lock);
1769 alx->hw.pdev = pdev;
1770 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1771 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1773 pci_set_drvdata(pdev, alx);
1775 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1777 dev_err(&pdev->dev, "cannot map device registers\n");
1779 goto out_free_netdev;
1782 netdev->netdev_ops = &alx_netdev_ops;
1783 netdev->ethtool_ops = &alx_ethtool_ops;
1784 netdev->irq = pci_irq_vector(pdev, 0);
1785 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1787 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1788 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1790 err = alx_init_sw(alx);
1792 dev_err(&pdev->dev, "net device private data init failed\n");
1796 mutex_lock(&alx->mtx);
1800 phy_configured = alx_phy_configured(hw);
1802 if (!phy_configured)
1805 err = alx_reset_mac(hw);
1807 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1811 /* setup link to put it in a known good starting state */
1812 if (!phy_configured) {
1813 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1816 "failed to configure PHY speed/duplex (err=%d)\n",
1822 netdev->hw_features = NETIF_F_SG |
1828 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1829 dev_warn(&pdev->dev,
1830 "Invalid permanent address programmed, using random one\n");
1831 eth_hw_addr_random(netdev);
1832 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1835 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1836 eth_hw_addr_set(netdev, hw->mac_addr);
1837 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1841 hw->mdio.dev = netdev;
1842 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1845 hw->mdio.mdio_read = alx_mdio_read;
1846 hw->mdio.mdio_write = alx_mdio_write;
1848 if (!alx_get_phy_info(hw)) {
1849 dev_err(&pdev->dev, "failed to identify PHY\n");
1854 mutex_unlock(&alx->mtx);
1856 INIT_WORK(&alx->link_check_wk, alx_link_check);
1857 INIT_WORK(&alx->reset_wk, alx_reset);
1858 netif_carrier_off(netdev);
1860 err = register_netdev(netdev);
1862 dev_err(&pdev->dev, "register netdevice failed\n");
1867 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1873 mutex_unlock(&alx->mtx);
1875 iounmap(hw->hw_addr);
1877 free_netdev(netdev);
1879 pci_release_mem_regions(pdev);
1881 pci_disable_device(pdev);
1885 static void alx_remove(struct pci_dev *pdev)
1887 struct alx_priv *alx = pci_get_drvdata(pdev);
1888 struct alx_hw *hw = &alx->hw;
1890 /* restore permanent mac address */
1891 alx_set_macaddr(hw, hw->perm_addr);
1893 unregister_netdev(alx->dev);
1894 iounmap(hw->hw_addr);
1895 pci_release_mem_regions(pdev);
1897 pci_disable_device(pdev);
1899 mutex_destroy(&alx->mtx);
1901 free_netdev(alx->dev);
1904 static int alx_suspend(struct device *dev)
1906 struct alx_priv *alx = dev_get_drvdata(dev);
1908 if (!netif_running(alx->dev))
1912 netif_device_detach(alx->dev);
1914 mutex_lock(&alx->mtx);
1916 mutex_unlock(&alx->mtx);
1922 static int alx_resume(struct device *dev)
1924 struct alx_priv *alx = dev_get_drvdata(dev);
1925 struct alx_hw *hw = &alx->hw;
1929 mutex_lock(&alx->mtx);
1932 if (!netif_running(alx->dev)) {
1937 err = __alx_open(alx, true);
1941 netif_device_attach(alx->dev);
1944 mutex_unlock(&alx->mtx);
1949 static DEFINE_SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1951 static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1952 pci_channel_state_t state)
1954 struct alx_priv *alx = pci_get_drvdata(pdev);
1955 struct net_device *netdev = alx->dev;
1956 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1958 dev_info(&pdev->dev, "pci error detected\n");
1960 mutex_lock(&alx->mtx);
1962 if (netif_running(netdev)) {
1963 netif_device_detach(netdev);
1967 if (state == pci_channel_io_perm_failure)
1968 rc = PCI_ERS_RESULT_DISCONNECT;
1970 pci_disable_device(pdev);
1972 mutex_unlock(&alx->mtx);
1977 static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1979 struct alx_priv *alx = pci_get_drvdata(pdev);
1980 struct alx_hw *hw = &alx->hw;
1981 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1983 dev_info(&pdev->dev, "pci error slot reset\n");
1985 mutex_lock(&alx->mtx);
1987 if (pci_enable_device(pdev)) {
1988 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1992 pci_set_master(pdev);
1995 if (!alx_reset_mac(hw))
1996 rc = PCI_ERS_RESULT_RECOVERED;
1998 mutex_unlock(&alx->mtx);
2003 static void alx_pci_error_resume(struct pci_dev *pdev)
2005 struct alx_priv *alx = pci_get_drvdata(pdev);
2006 struct net_device *netdev = alx->dev;
2008 dev_info(&pdev->dev, "pci error resume\n");
2010 mutex_lock(&alx->mtx);
2012 if (netif_running(netdev)) {
2014 netif_device_attach(netdev);
2017 mutex_unlock(&alx->mtx);
2020 static const struct pci_error_handlers alx_err_handlers = {
2021 .error_detected = alx_pci_error_detected,
2022 .slot_reset = alx_pci_error_slot_reset,
2023 .resume = alx_pci_error_resume,
2026 static const struct pci_device_id alx_pci_tbl[] = {
2027 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
2028 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2029 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
2030 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2031 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400),
2032 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2033 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2500),
2034 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2035 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
2036 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2037 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
2038 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
2042 static struct pci_driver alx_driver = {
2043 .name = alx_drv_name,
2044 .id_table = alx_pci_tbl,
2046 .remove = alx_remove,
2047 .err_handler = &alx_err_handlers,
2048 .driver.pm = pm_sleep_ptr(&alx_pm_ops),
2051 module_pci_driver(alx_driver);
2052 MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
2053 MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
2054 MODULE_AUTHOR("Qualcomm Corporation");
2056 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
2057 MODULE_LICENSE("GPL");