2 * emac-rockchip.c - Rockchip EMAC specific glue layer
4 * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/etherdevice.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/of_net.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
27 #define DRV_NAME "rockchip_emac"
28 #define DRV_VERSION "1.0"
30 #define GRF_MODE_MII (1UL << 0)
31 #define GRF_MODE_RMII (0UL << 0)
32 #define GRF_SPEED_10M (0UL << 1)
33 #define GRF_SPEED_100M (1UL << 1)
34 #define GRF_SPEED_ENABLE_BIT (1UL << 17)
35 #define GRF_MODE_ENABLE_BIT (1UL << 16)
37 struct emac_rockchip_soc_data {
41 struct rockchip_priv_data {
42 struct arc_emac_priv emac;
44 const struct emac_rockchip_soc_data *soc_data;
45 struct regulator *regulator;
49 static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
51 struct rockchip_priv_data *emac = priv;
55 /* write-enable bits */
56 data = GRF_SPEED_ENABLE_BIT;
60 data |= GRF_SPEED_10M;
63 data |= GRF_SPEED_100M;
66 pr_err("speed %u not supported\n", speed);
70 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
72 pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
75 static const struct emac_rockchip_soc_data emac_rockchip_dt_data[] = {
76 { .grf_offset = 0x154 }, /* rk3066 */
77 { .grf_offset = 0x0a4 }, /* rk3188 */
80 static const struct of_device_id emac_rockchip_dt_ids[] = {
81 { .compatible = "rockchip,rk3066-emac", .data = &emac_rockchip_dt_data[0] },
82 { .compatible = "rockchip,rk3188-emac", .data = &emac_rockchip_dt_data[1] },
86 MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
88 static int emac_rockchip_probe(struct platform_device *pdev)
90 struct device *dev = &pdev->dev;
91 struct net_device *ndev;
92 struct rockchip_priv_data *priv;
93 const struct of_device_id *match;
97 if (!pdev->dev.of_node)
100 ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
103 platform_set_drvdata(pdev, ndev);
104 SET_NETDEV_DEV(ndev, dev);
106 priv = netdev_priv(ndev);
107 priv->emac.drv_name = DRV_NAME;
108 priv->emac.drv_version = DRV_VERSION;
109 priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
111 interface = of_get_phy_mode(dev->of_node);
113 /* RK3066 and RK3188 SoCs only support RMII */
114 if (interface != PHY_INTERFACE_MODE_RMII) {
115 dev_err(dev, "unsupported phy interface mode %d\n", interface);
120 priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
121 if (IS_ERR(priv->grf)) {
122 dev_err(dev, "failed to retrieve global register file (%ld)\n", PTR_ERR(priv->grf));
123 err = PTR_ERR(priv->grf);
127 match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
128 priv->soc_data = match->data;
130 priv->emac.clk = devm_clk_get(dev, "hclk");
131 if (IS_ERR(priv->emac.clk)) {
132 dev_err(dev, "failed to retrieve host clock (%ld)\n", PTR_ERR(priv->emac.clk));
133 err = PTR_ERR(priv->emac.clk);
137 priv->refclk = devm_clk_get(dev, "macref");
138 if (IS_ERR(priv->refclk)) {
139 dev_err(dev, "failed to retrieve reference clock (%ld)\n", PTR_ERR(priv->refclk));
140 err = PTR_ERR(priv->refclk);
144 err = clk_prepare_enable(priv->refclk);
146 dev_err(dev, "failed to enable reference clock (%d)\n", err);
150 /* Optional regulator for PHY */
151 priv->regulator = devm_regulator_get_optional(dev, "phy");
152 if (IS_ERR(priv->regulator)) {
153 if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
155 goto out_clk_disable;
157 dev_err(dev, "no regulator found\n");
158 priv->regulator = NULL;
161 if (priv->regulator) {
162 err = regulator_enable(priv->regulator);
164 dev_err(dev, "failed to enable phy-supply (%d)\n", err);
165 goto out_clk_disable;
169 err = arc_emac_probe(ndev, interface);
171 goto out_regulator_disable;
173 /* write-enable bits */
174 data = GRF_MODE_ENABLE_BIT | GRF_SPEED_ENABLE_BIT;
176 data |= GRF_SPEED_100M;
177 data |= GRF_MODE_RMII;
179 err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
181 dev_err(dev, "unable to apply initial settings to grf (%d)\n", err);
182 goto out_regulator_disable;
185 /* RMII interface needs always a rate of 50MHz */
186 err = clk_set_rate(priv->refclk, 50000000);
188 dev_err(dev, "failed to change reference clock rate (%d)\n", err);
191 out_regulator_disable:
193 regulator_disable(priv->regulator);
195 clk_disable_unprepare(priv->refclk);
201 static int emac_rockchip_remove(struct platform_device *pdev)
203 struct net_device *ndev = platform_get_drvdata(pdev);
204 struct rockchip_priv_data *priv = netdev_priv(ndev);
207 err = arc_emac_remove(ndev);
209 clk_disable_unprepare(priv->refclk);
212 regulator_disable(priv->regulator);
218 static struct platform_driver emac_rockchip_driver = {
219 .probe = emac_rockchip_probe,
220 .remove = emac_rockchip_remove,
223 .of_match_table = emac_rockchip_dt_ids,
227 module_platform_driver(emac_rockchip_driver);
229 MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
230 MODULE_DESCRIPTION("Rockchip EMAC platform driver");
231 MODULE_LICENSE("GPL");