2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "hw_atl_a0.h"
16 #include "hw_atl_utils.h"
17 #include "hw_atl_llh.h"
18 #include "hw_atl_a0_internal.h"
20 static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
21 struct aq_hw_caps_s *aq_hw_caps,
22 unsigned short device,
23 unsigned short subsystem_device)
25 memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps));
27 if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001)
28 aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_10G;
30 if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) {
31 aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_10G;
32 aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_5G;
38 static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
40 struct aq_hw_ops *ops)
42 struct hw_atl_s *self = NULL;
44 self = kzalloc(sizeof(*self), GFP_KERNEL);
48 self->base.aq_pci_func = aq_pci_func;
50 self->base.not_ff_addr = 0x10U;
53 return (struct aq_hw_s *)self;
56 static void hw_atl_a0_destroy(struct aq_hw_s *self)
61 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
65 glb_glb_reg_res_dis_set(self, 1U);
66 pci_pci_reg_res_dis_set(self, 0U);
67 rx_rx_reg_res_dis_set(self, 0U);
68 tx_tx_reg_res_dis_set(self, 0U);
71 glb_soft_res_set(self, 1);
73 /* check 10 times by 1ms */
74 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
78 itr_irq_reg_res_dis_set(self, 0U);
79 itr_res_irq_set(self, 1U);
81 /* check 10 times by 1ms */
82 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
86 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
88 err = aq_hw_err_from_flags(self);
94 static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
98 unsigned int i_priority = 0U;
99 bool is_rx_flow_control = false;
101 /* TPS Descriptor rate init */
102 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
103 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
106 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
108 /* TPS TC credits init */
109 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
110 tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
112 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
113 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
114 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
115 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
118 buff_size = HW_ATL_A0_TXBUF_MAX;
120 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
121 tpb_tx_buff_hi_threshold_per_tc_set(self,
122 (buff_size * (1024 / 32U) * 66U) /
124 tpb_tx_buff_lo_threshold_per_tc_set(self,
125 (buff_size * (1024 / 32U) * 50U) /
128 /* QoS Rx buf size per TC */
130 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
131 buff_size = HW_ATL_A0_RXBUF_MAX;
133 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
134 rpb_rx_buff_hi_threshold_per_tc_set(self,
136 (1024U / 32U) * 66U) /
138 rpb_rx_buff_lo_threshold_per_tc_set(self,
140 (1024U / 32U) * 50U) /
142 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
144 /* QoS 802.1p priority -> TC mapping */
145 for (i_priority = 8U; i_priority--;)
146 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
148 return aq_hw_err_from_flags(self);
151 static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
152 struct aq_rss_parameters *rss_params)
154 struct aq_nic_cfg_s *cfg = NULL;
157 unsigned int addr = 0U;
159 cfg = self->aq_nic_cfg;
161 for (i = 10, addr = 0U; i--; ++addr) {
162 u32 key_data = cfg->is_rss ?
163 __swab32(rss_params->hash_secret_key[i]) : 0U;
164 rpf_rss_key_wr_data_set(self, key_data);
165 rpf_rss_key_addr_set(self, addr);
166 rpf_rss_key_wr_en_set(self, 1U);
167 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
172 err = aq_hw_err_from_flags(self);
178 static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
179 struct aq_rss_parameters *rss_params)
181 u8 *indirection_table = rss_params->indirection_table;
183 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
185 u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX *
186 HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
188 memset(bitary, 0, sizeof(bitary));
190 for (i = HW_ATL_A0_RSS_REDIRECTION_MAX; i--; ) {
191 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
192 ((indirection_table[i] % num_rss_queues) <<
196 for (i = AQ_DIMOF(bitary); i--;) {
197 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
198 rpf_rss_redir_tbl_addr_set(self, i);
199 rpf_rss_redir_wr_en_set(self, 1U);
200 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
205 err = aq_hw_err_from_flags(self);
211 static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
212 struct aq_nic_cfg_s *aq_nic_cfg)
214 /* TX checksums offloads*/
215 tpo_ipv4header_crc_offload_en_set(self, 1);
216 tpo_tcp_udp_crc_offload_en_set(self, 1);
218 /* RX checksums offloads*/
219 rpo_ipv4header_crc_offload_en_set(self, 1);
220 rpo_tcp_udp_crc_offload_en_set(self, 1);
223 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
225 return aq_hw_err_from_flags(self);
228 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
230 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
231 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
232 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
235 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
238 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
239 0x00010000U : 0x00000000U);
240 tdm_tx_dca_en_set(self, 0U);
241 tdm_tx_dca_mode_set(self, 0U);
243 tpb_tx_path_scp_ins_en_set(self, 1U);
245 return aq_hw_err_from_flags(self);
248 static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
250 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
253 /* Rx TC/RSS number config */
254 rpb_rpf_rx_traf_class_mode_set(self, 1U);
256 /* Rx flow control */
257 rpb_rx_flow_ctl_mode_set(self, 1U);
259 /* RSS Ring selection */
260 reg_rx_flr_rss_control1set(self, cfg->is_rss ?
261 0xB3333333U : 0x00000000U);
263 /* Multicast filters */
264 for (i = HW_ATL_A0_MAC_MAX; i--;) {
265 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
266 rpfl2unicast_flr_act_set(self, 1U, i);
269 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
270 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
273 rpf_vlan_outer_etht_set(self, 0x88A8U);
274 rpf_vlan_inner_etht_set(self, 0x8100U);
275 rpf_vlan_prom_mode_en_set(self, 1);
278 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
281 rpfl2broadcast_flr_act_set(self, 1U);
282 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
284 rdm_rx_dca_en_set(self, 0U);
285 rdm_rx_dca_mode_set(self, 0U);
287 return aq_hw_err_from_flags(self);
290 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
300 h = (mac_addr[0] << 8) | (mac_addr[1]);
301 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
302 (mac_addr[4] << 8) | mac_addr[5];
304 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
305 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
306 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
307 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
309 err = aq_hw_err_from_flags(self);
315 static int hw_atl_a0_hw_init(struct aq_hw_s *self,
316 struct aq_nic_cfg_s *aq_nic_cfg,
319 static u32 aq_hw_atl_igcr_table_[4][2] = {
320 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
321 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
322 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
323 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
328 self->aq_nic_cfg = aq_nic_cfg;
330 hw_atl_utils_hw_chip_features_init(self,
331 &PHAL_ATLANTIC_A0->chip_features);
333 hw_atl_a0_hw_init_tx_path(self);
334 hw_atl_a0_hw_init_rx_path(self);
336 hw_atl_a0_hw_mac_addr_set(self, mac_addr);
338 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
340 reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
341 reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
343 hw_atl_a0_hw_qos_set(self);
344 hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
345 hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
347 err = aq_hw_err_from_flags(self);
352 reg_irq_glb_ctl_set(self,
353 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
354 [(aq_nic_cfg->vecs > 1U) ?
357 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
360 reg_gen_irq_map_set(self,
361 ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
362 ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
363 ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
364 ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
366 hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
372 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
373 struct aq_ring_s *ring)
375 tdm_tx_desc_en_set(self, 1, ring->idx);
376 return aq_hw_err_from_flags(self);
379 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
380 struct aq_ring_s *ring)
382 rdm_rx_desc_en_set(self, 1, ring->idx);
383 return aq_hw_err_from_flags(self);
386 static int hw_atl_a0_hw_start(struct aq_hw_s *self)
388 tpb_tx_buff_en_set(self, 1);
389 rpb_rx_buff_en_set(self, 1);
390 return aq_hw_err_from_flags(self);
393 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
394 struct aq_ring_s *ring)
396 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
400 static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s *self,
401 struct aq_ring_s *ring,
404 struct aq_ring_buff_s *buff = NULL;
405 struct hw_atl_txd_s *txd = NULL;
406 unsigned int buff_pa_len = 0U;
407 unsigned int pkt_len = 0U;
408 unsigned int frag_count = 0U;
411 buff = &ring->buff_ring[ring->sw_tail];
412 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
414 for (frag_count = 0; frag_count < frags; frag_count++) {
415 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
421 buff = &ring->buff_ring[ring->sw_tail];
424 txd->ctl |= (buff->len_l3 << 31) |
425 (buff->len_l2 << 24) |
426 HW_ATL_A0_TXD_CTL_CMD_TCP |
427 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC;
428 txd->ctl2 |= (buff->mss << 16) |
429 (buff->len_l4 << 8) |
432 pkt_len -= (buff->len_l4 +
438 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPV6;
440 buff_pa_len = buff->len;
442 txd->buf_addr = buff->pa;
443 txd->ctl |= (HW_ATL_A0_TXD_CTL_BLEN &
444 ((u32)buff_pa_len << 4));
445 txd->ctl |= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD;
447 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14);
450 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_LSO;
451 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN;
454 /* Tx checksum offloads */
456 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPCSO;
458 if (buff->is_udp_cso || buff->is_tcp_cso)
459 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_TUCSO;
461 if (unlikely(buff->is_eop)) {
462 txd->ctl |= HW_ATL_A0_TXD_CTL_EOP;
463 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_WB;
468 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
471 hw_atl_a0_hw_tx_ring_tail_update(self, ring);
472 return aq_hw_err_from_flags(self);
475 static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
476 struct aq_ring_s *aq_ring,
477 struct aq_ring_param_s *aq_ring_param)
479 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
480 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
482 rdm_rx_desc_en_set(self, false, aq_ring->idx);
484 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
486 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
489 reg_rx_dma_desc_base_addressmswset(self,
490 dma_desc_addr_msw, aq_ring->idx);
492 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
494 rdm_rx_desc_data_buff_size_set(self,
495 AQ_CFG_RX_FRAME_MAX / 1024U,
498 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
499 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
500 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
502 /* Rx ring set mode */
504 /* Mapping interrupt vector */
505 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
506 itr_irq_map_en_rx_set(self, true, aq_ring->idx);
508 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
509 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
510 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
511 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
513 return aq_hw_err_from_flags(self);
516 static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
517 struct aq_ring_s *aq_ring,
518 struct aq_ring_param_s *aq_ring_param)
520 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
521 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
523 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
526 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
529 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
531 hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
533 /* Set Tx threshold */
534 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
536 /* Mapping interrupt vector */
537 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
538 itr_irq_map_en_tx_set(self, true, aq_ring->idx);
540 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
541 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
543 return aq_hw_err_from_flags(self);
546 static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
547 struct aq_ring_s *ring,
548 unsigned int sw_tail_old)
550 for (; sw_tail_old != ring->sw_tail;
551 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
552 struct hw_atl_rxd_s *rxd =
553 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
556 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
558 rxd->buf_addr = buff->pa;
562 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
564 return aq_hw_err_from_flags(self);
567 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
568 struct aq_ring_s *ring)
571 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
573 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
577 ring->hw_head = hw_head_;
578 err = aq_hw_err_from_flags(self);
584 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
585 struct aq_ring_s *ring)
587 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
589 for (; ring->hw_head != ring->sw_tail;
590 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
591 struct aq_ring_buff_s *buff = NULL;
592 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
593 &ring->dx_ring[ring->hw_head * HW_ATL_A0_RXD_SIZE];
595 unsigned int is_err = 1U;
596 unsigned int is_rx_check_sum_enabled = 0U;
597 unsigned int pkt_type = 0U;
599 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
601 reg_rx_dma_desc_status_get(self, ring->idx)) {
602 rdm_rx_desc_en_set(self, false, ring->idx);
603 rdm_rx_desc_res_set(self, true, ring->idx);
604 rdm_rx_desc_res_set(self, false, ring->idx);
605 rdm_rx_desc_en_set(self, true, ring->idx);
609 (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) {
611 } else if (!(rxd_wb->status & 0x1U)) {
612 struct hw_atl_rxd_wb_s *rxd_wb1 =
613 (struct hw_atl_rxd_wb_s *)
614 (&ring->dx_ring[(1U) *
615 HW_ATL_A0_RXD_SIZE]);
617 if ((rxd_wb1->status & 0x1U)) {
618 rxd_wb->pkt_len = 1514U;
626 buff = &ring->buff_ring[ring->hw_head];
628 if (0x3U != (rxd_wb->status & 0x3U))
631 is_err = (0x0000001CU & rxd_wb->status);
632 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
633 pkt_type = 0xFFU & (rxd_wb->type >> 4);
635 if (is_rx_check_sum_enabled) {
636 if (0x0U == (pkt_type & 0x3U))
637 buff->is_ip_cso = (is_err & 0x08U) ? 0 : 1;
639 if (0x4U == (pkt_type & 0x1CU))
640 buff->is_udp_cso = (is_err & 0x10U) ? 0 : 1;
641 else if (0x0U == (pkt_type & 0x1CU))
642 buff->is_tcp_cso = (is_err & 0x10U) ? 0 : 1;
644 /* Checksum offload workaround for small packets */
645 if (rxd_wb->pkt_len <= 60) {
646 buff->is_ip_cso = 0U;
647 buff->is_cso_err = 0U;
654 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
656 if (is_err || rxd_wb->type & 0x1000U) {
657 /* status error or DMA error */
660 if (self->aq_nic_cfg->is_rss) {
662 u16 rss_type = rxd_wb->type & 0xFU;
664 if (rss_type && rss_type < 0x8U) {
665 buff->is_hash_l4 = (rss_type == 0x4 ||
667 buff->rss_hash = rxd_wb->rss_hash;
671 if (HW_ATL_A0_RXD_WB_STAT2_EOP & rxd_wb->status) {
672 buff->len = rxd_wb->pkt_len %
674 buff->len = buff->len ?
675 buff->len : AQ_CFG_RX_FRAME_MAX;
680 buff->next = aq_ring_next_dx(ring,
682 ++ring->stats.rx.jumbo_packets;
687 return aq_hw_err_from_flags(self);
690 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
692 itr_irq_msk_setlsw_set(self, LODWORD(mask) |
693 (1U << HW_ATL_A0_ERR_INT));
694 return aq_hw_err_from_flags(self);
697 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
699 itr_irq_msk_clearlsw_set(self, LODWORD(mask));
700 itr_irq_status_clearlsw_set(self, LODWORD(mask));
702 if ((1U << 16) & reg_gen_irq_status_get(self))
704 atomic_inc(&PHAL_ATLANTIC_A0->dpc);
706 return aq_hw_err_from_flags(self);
709 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
711 *mask = itr_irq_statuslsw_get(self);
712 return aq_hw_err_from_flags(self);
715 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
717 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
718 unsigned int packet_filter)
722 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
723 rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0);
724 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
726 self->aq_nic_cfg->is_mc_list_enabled =
727 IS_FILTER_ENABLED(IFF_MULTICAST);
729 for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
730 rpfl2_uc_flr_en_set(self,
731 (self->aq_nic_cfg->is_mc_list_enabled &&
732 (i <= self->aq_nic_cfg->mc_list_count)) ?
735 return aq_hw_err_from_flags(self);
738 #undef IS_FILTER_ENABLED
740 static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
742 [AQ_CFG_MULTICAST_ADDRESS_MAX]
748 if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
752 for (self->aq_nic_cfg->mc_list_count = 0U;
753 self->aq_nic_cfg->mc_list_count < count;
754 ++self->aq_nic_cfg->mc_list_count) {
755 u32 i = self->aq_nic_cfg->mc_list_count;
756 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
757 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
758 (ar_mac[i][4] << 8) | ar_mac[i][5];
760 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
762 rpfl2unicast_dest_addresslsw_set(self,
763 l, HW_ATL_A0_MAC_MIN + i);
765 rpfl2unicast_dest_addressmsw_set(self,
766 h, HW_ATL_A0_MAC_MIN + i);
768 rpfl2_uc_flr_en_set(self,
769 (self->aq_nic_cfg->is_mc_list_enabled),
770 HW_ATL_A0_MAC_MIN + i);
773 err = aq_hw_err_from_flags(self);
779 static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self)
784 if (self->aq_nic_cfg->itr) {
785 if (self->aq_nic_cfg->itr != AQ_CFG_INTERRUPT_MODERATION_AUTO) {
786 u32 itr_ = (self->aq_nic_cfg->itr >> 1);
788 itr_ = min(AQ_CFG_IRQ_MASK, itr_);
790 itr_rx = 0x80000000U | (itr_ << 0x10);
792 u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
794 if (n < self->aq_link_status.mbps) {
797 static unsigned int hw_timers_tbl_[] = {
800 0x039U, /* 5Gbit 5GS */
801 0x073U, /* 2.5Gbit */
803 0x1FFU, /* 100Mbit */
806 unsigned int speed_index =
807 hw_atl_utils_mbps_2_speed_index(
808 self->aq_link_status.mbps);
810 itr_rx = 0x80000000U |
811 (hw_timers_tbl_[speed_index] << 0x10U);
814 aq_hw_write_reg(self, 0x00002A00U, 0x40000000U);
815 aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
821 for (i = HW_ATL_A0_RINGS_MAX; i--;)
822 reg_irq_thr_set(self, itr_rx, i);
824 return aq_hw_err_from_flags(self);
827 static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
829 hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
830 return aq_hw_err_from_flags(self);
833 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
834 struct aq_ring_s *ring)
836 tdm_tx_desc_en_set(self, 0U, ring->idx);
837 return aq_hw_err_from_flags(self);
840 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
841 struct aq_ring_s *ring)
843 rdm_rx_desc_en_set(self, 0U, ring->idx);
844 return aq_hw_err_from_flags(self);
847 static int hw_atl_a0_hw_set_speed(struct aq_hw_s *self, u32 speed)
851 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
859 static struct aq_hw_ops hw_atl_ops_ = {
860 .create = hw_atl_a0_create,
861 .destroy = hw_atl_a0_destroy,
862 .get_hw_caps = hw_atl_a0_get_hw_caps,
864 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
865 .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
866 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
867 .hw_set_link_speed = hw_atl_a0_hw_set_speed,
868 .hw_init = hw_atl_a0_hw_init,
869 .hw_deinit = hw_atl_utils_hw_deinit,
870 .hw_set_power = hw_atl_utils_hw_set_power,
871 .hw_reset = hw_atl_a0_hw_reset,
872 .hw_start = hw_atl_a0_hw_start,
873 .hw_ring_tx_start = hw_atl_a0_hw_ring_tx_start,
874 .hw_ring_tx_stop = hw_atl_a0_hw_ring_tx_stop,
875 .hw_ring_rx_start = hw_atl_a0_hw_ring_rx_start,
876 .hw_ring_rx_stop = hw_atl_a0_hw_ring_rx_stop,
877 .hw_stop = hw_atl_a0_hw_stop,
879 .hw_ring_tx_xmit = hw_atl_a0_hw_ring_tx_xmit,
880 .hw_ring_tx_head_update = hw_atl_a0_hw_ring_tx_head_update,
882 .hw_ring_rx_receive = hw_atl_a0_hw_ring_rx_receive,
883 .hw_ring_rx_fill = hw_atl_a0_hw_ring_rx_fill,
885 .hw_irq_enable = hw_atl_a0_hw_irq_enable,
886 .hw_irq_disable = hw_atl_a0_hw_irq_disable,
887 .hw_irq_read = hw_atl_a0_hw_irq_read,
889 .hw_ring_rx_init = hw_atl_a0_hw_ring_rx_init,
890 .hw_ring_tx_init = hw_atl_a0_hw_ring_tx_init,
891 .hw_packet_filter_set = hw_atl_a0_hw_packet_filter_set,
892 .hw_multicast_list_set = hw_atl_a0_hw_multicast_list_set,
893 .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
894 .hw_rss_set = hw_atl_a0_hw_rss_set,
895 .hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set,
896 .hw_get_regs = hw_atl_utils_hw_get_regs,
897 .hw_update_stats = hw_atl_utils_update_stats,
898 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
899 .hw_get_fw_version = hw_atl_utils_get_fw_version,
902 struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
904 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
905 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
906 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
907 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
908 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
909 (pdev->device == HW_ATL_DEVICE_ID_D109));
911 bool is_rev_ok = (pdev->revision == 1U);
913 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;