1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Atlantic Network Driver
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
8 /* File aq_hw_utils.c: Definitions of helper functions used across
12 #include "aq_hw_utils.h"
14 #include <linux/io-64-nonatomic-lo-hi.h>
19 void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
25 reg_old = aq_hw_read_reg(aq_hw, addr);
26 reg_new = (reg_old & (~msk)) | (val << shift);
28 if (reg_old != reg_new)
29 aq_hw_write_reg(aq_hw, addr, reg_new);
31 aq_hw_write_reg(aq_hw, addr, val);
35 u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift)
37 return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift);
40 u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)
42 u32 value = readl(hw->mmio + reg);
44 if (value == U32_MAX &&
45 readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX)
46 aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
51 void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)
53 writel(value, hw->mmio + reg);
56 /* Most of 64-bit registers are in LSW, MSW form.
57 Counters are normally implemented by HW as latched pairs:
58 reading LSW first locks MSW, to overcome LSW overflow
60 u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg)
64 if (hw->aq_nic_cfg->aq_hw_caps->op64bit)
65 value = readq(hw->mmio + reg);
67 value = lo_hi_readq(hw->mmio + reg);
69 if (value == U64_MAX &&
70 readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX)
71 aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
76 void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value)
78 if (hw->aq_nic_cfg->aq_hw_caps->op64bit)
79 writeq(value, hw->mmio + reg);
81 lo_hi_writeq(value, hw->mmio + reg);
84 int aq_hw_err_from_flags(struct aq_hw_s *hw)
88 if (aq_utils_obj_test(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
92 if (aq_utils_obj_test(&hw->flags, AQ_HW_FLAG_ERR_HW)) {
101 int aq_hw_num_tcs(struct aq_hw_s *hw)
103 switch (hw->aq_nic_cfg->tc_mode) {
104 case AQ_TC_MODE_8TCS:
106 case AQ_TC_MODE_4TCS:
115 int aq_hw_q_per_tc(struct aq_hw_s *hw)
117 switch (hw->aq_nic_cfg->tc_mode) {
118 case AQ_TC_MODE_8TCS:
120 case AQ_TC_MODE_4TCS: