1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __XGENE_ENET_HW_H__
23 #define __XGENE_ENET_HW_H__
25 #include "xgene_enet_main.h"
27 struct xgene_enet_pdata;
28 struct xgene_enet_stats;
29 struct xgene_enet_desc_ring;
31 /* clears and then set bits */
32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
34 u32 end = start + len - 1;
35 u32 mask = GENMASK(end, start);
38 *dst |= (val << start) & mask;
41 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
43 return (val & GENMASK(end, start)) >> start;
52 #define CSR_RING_ID 0x0008
53 #define OVERWRITE BIT(31)
54 #define IS_BUFFER_POOL BIT(20)
55 #define PREFETCH_BUF_EN BIT(21)
56 #define CSR_RING_ID_BUF 0x000c
57 #define CSR_PBM_COAL 0x0014
58 #define CSR_PBM_CTICK0 0x0018
59 #define CSR_PBM_CTICK1 0x001c
60 #define CSR_PBM_CTICK2 0x0020
61 #define CSR_PBM_CTICK3 0x0024
62 #define CSR_THRESHOLD0_SET1 0x0030
63 #define CSR_THRESHOLD1_SET1 0x0034
64 #define CSR_RING_NE_INT_MODE 0x017c
65 #define CSR_RING_CONFIG 0x006c
66 #define CSR_RING_WR_BASE 0x0070
67 #define NUM_RING_CONFIG 5
68 #define BUFPOOL_MODE 3
69 #define INC_DEC_CMD_ADDR 0x002c
70 #define UDP_HDR_SIZE 2
71 #define BUF_LEN_CODE_2K 0x5000
73 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
74 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
76 /* Empty slot soft signature */
77 #define EMPTY_SLOT_INDEX 1
78 #define EMPTY_SLOT ~0ULL
80 #define WORK_DESC_SIZE 32
81 #define BUFPOOL_DESC_SIZE 16
83 #define RING_OWNER_MASK GENMASK(9, 6)
84 #define RING_BUFNUM_MASK GENMASK(5, 0)
86 #define SELTHRSH_POS 3
87 #define SELTHRSH_LEN 3
88 #define RINGADDRL_POS 5
89 #define RINGADDRL_LEN 27
90 #define RINGADDRH_POS 0
91 #define RINGADDRH_LEN 7
92 #define RINGSIZE_POS 23
93 #define RINGSIZE_LEN 3
94 #define RINGTYPE_POS 19
95 #define RINGTYPE_LEN 2
96 #define RINGMODE_POS 20
97 #define RINGMODE_LEN 3
98 #define RECOMTIMEOUTL_POS 28
99 #define RECOMTIMEOUTL_LEN 4
100 #define RECOMTIMEOUTH_POS 0
101 #define RECOMTIMEOUTH_LEN 3
102 #define NUMMSGSINQ_POS 1
103 #define NUMMSGSINQ_LEN 16
104 #define ACCEPTLERR BIT(19)
105 #define QCOHERENT BIT(4)
106 #define RECOMBBUF BIT(27)
108 #define MAC_OFFSET 0x30
109 #define OFFSET_4 0x04
110 #define OFFSET_8 0x08
112 #define BLOCK_ETH_CSR_OFFSET 0x2000
113 #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000
114 #define BLOCK_ETH_RING_IF_OFFSET 0x9000
115 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000
116 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
117 #define BLOCK_ETH_MAC_OFFSET 0x0000
118 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
120 #define CLKEN_ADDR 0xc208
121 #define SRST_ADDR 0xc200
123 #define MAC_ADDR_REG_OFFSET 0x00
124 #define MAC_COMMAND_REG_OFFSET 0x04
125 #define MAC_WRITE_REG_OFFSET 0x08
126 #define MAC_READ_REG_OFFSET 0x0c
127 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
129 #define PCS_ADDR_REG_OFFSET 0x00
130 #define PCS_COMMAND_REG_OFFSET 0x04
131 #define PCS_WRITE_REG_OFFSET 0x08
132 #define PCS_READ_REG_OFFSET 0x0c
133 #define PCS_COMMAND_DONE_REG_OFFSET 0x10
135 #define MII_MGMT_CONFIG_ADDR 0x20
136 #define MII_MGMT_COMMAND_ADDR 0x24
137 #define MII_MGMT_ADDRESS_ADDR 0x28
138 #define MII_MGMT_CONTROL_ADDR 0x2c
139 #define MII_MGMT_STATUS_ADDR 0x30
140 #define MII_MGMT_INDICATORS_ADDR 0x34
142 #define BUSY_MASK BIT(0)
143 #define READ_CYCLE_MASK BIT(0)
144 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
146 #define ENET_SPARE_CFG_REG_ADDR 0x0750
147 #define RSIF_CONFIG_REG_ADDR 0x0010
148 #define RSIF_RAM_DBG_REG0_ADDR 0x0048
149 #define RGMII_REG_0_ADDR 0x07e0
150 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
151 #define DEBUG_REG_ADDR 0x0700
152 #define CFG_BYPASS_ADDR 0x0294
153 #define CLE_BYPASS_REG0_0_ADDR 0x0490
154 #define CLE_BYPASS_REG1_0_ADDR 0x0494
155 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
156 #define RESUME_TX BIT(0)
157 #define CFG_SPEED_1250 BIT(24)
158 #define TX_PORT0 BIT(0)
159 #define CFG_BYPASS_UNISEC_TX BIT(2)
160 #define CFG_BYPASS_UNISEC_RX BIT(1)
161 #define CFG_CLE_BYPASS_EN0 BIT(31)
162 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
163 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)
165 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
166 #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
167 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
168 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
169 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
170 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
171 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0))
172 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16))
173 #define ICM_CONFIG0_REG_0_ADDR 0x0400
174 #define ICM_CONFIG2_REG_0_ADDR 0x0410
175 #define RX_DV_GATE_REG_0_ADDR 0x05fc
176 #define TX_DV_GATE_EN0 BIT(2)
177 #define RX_DV_GATE_EN0 BIT(1)
178 #define RESUME_RX0 BIT(0)
179 #define ENET_CFGSSQMIFPRESET_ADDR 0x14
180 #define ENET_CFGSSQMIWQRESET_ADDR 0x1c
181 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
182 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
183 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
184 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
185 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
186 #define ENET_BLOCK_MEM_RDY_ADDR 0x74
187 #define MAC_CONFIG_1_ADDR 0x00
188 #define MAC_CONFIG_2_ADDR 0x04
189 #define MAX_FRAME_LEN_ADDR 0x10
190 #define INTERFACE_CONTROL_ADDR 0x38
191 #define STATION_ADDR0_ADDR 0x40
192 #define STATION_ADDR1_ADDR 0x44
193 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
194 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
195 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
196 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
197 #define SOFT_RESET1 BIT(31)
200 #define ENET_LHD_MODE BIT(25)
201 #define ENET_GHD_MODE BIT(26)
202 #define FULL_DUPLEX2 BIT(0)
203 #define PAD_CRC BIT(2)
204 #define SCAN_AUTO_INCR BIT(5)
205 #define TBYT_ADDR 0x38
206 #define TPKT_ADDR 0x39
207 #define TDRP_ADDR 0x45
208 #define TFCS_ADDR 0x47
209 #define TUND_ADDR 0x4a
211 #define TSO_IPPROTO_TCP 1
213 #define USERINFO_POS 0
214 #define USERINFO_LEN 32
215 #define FPQNUM_POS 32
216 #define FPQNUM_LEN 12
227 #define BUFDATALEN_POS 48
228 #define BUFDATALEN_LEN 15
229 #define DATAADDR_POS 0
230 #define DATAADDR_LEN 42
231 #define COHERENT_POS 63
232 #define HENQNUM_POS 48
233 #define HENQNUM_LEN 12
234 #define TYPESEL_POS 44
235 #define TYPESEL_LEN 4
236 #define ETHHDR_POS 12
238 #define IC_POS 35 /* Insert CRC */
245 #define EC_POS 22 /* Enable checksum */
247 #define ET_POS 23 /* Enable TSO */
248 #define IS_POS 24 /* IP protocol select */
250 #define TYPE_ETH_WORK_MESSAGE_POS 44
251 #define LL_BYTES_MSB_POS 56
252 #define LL_BYTES_MSB_LEN 8
253 #define LL_BYTES_LSB_POS 48
254 #define LL_BYTES_LSB_LEN 12
255 #define LL_LEN_POS 48
257 #define DATALEN_MASK GENMASK(11, 0)
259 #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)
261 #define TSO_MSS0_POS 0
262 #define TSO_MSS0_LEN 14
263 #define TSO_MSS1_POS 16
264 #define TSO_MSS1_LEN 14
266 struct xgene_enet_raw_desc {
273 struct xgene_enet_raw_desc16 {
278 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
280 __le64 *desc_slot = desc_slot_ptr;
282 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
285 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
287 __le64 *desc_slot = desc_slot_ptr;
289 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
292 enum xgene_enet_ring_cfgsize {
301 enum xgene_enet_ring_type {
307 enum xgene_ring_owner {
314 enum xgene_enet_ring_bufnum {
315 RING_BUFNUM_REGULAR = 0x0,
316 RING_BUFNUM_BUFPOOL = 0x20,
320 enum xgene_enet_err_code {
324 BUFPOOL_TIMEOUT = 15,
326 INGRESS_CHECKSUM = 17,
327 INGRESS_TRUNC_FRAME = 18,
328 INGRESS_PKT_LEN = 19,
329 INGRESS_PKT_UNDER = 20,
330 INGRESS_FIFO_OVERRUN = 21,
331 INGRESS_CHECKSUM_COMPUTE = 26,
335 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
337 return (id & RING_OWNER_MASK) >> 6;
340 static inline u8 xgene_enet_ring_bufnum(u16 id)
342 return id & RING_BUFNUM_MASK;
345 static inline bool xgene_enet_is_bufpool(u16 id)
347 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
350 static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
352 bool is_bufpool = xgene_enet_is_bufpool(id);
354 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
355 size / WORK_DESC_SIZE;
358 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
359 struct xgene_enet_pdata *pdata,
360 enum xgene_enet_err_code status);
362 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
363 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
364 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p);
365 int xgene_enet_phy_connect(struct net_device *ndev);
366 void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata);
368 extern const struct xgene_mac_ops xgene_gmac_ops;
369 extern const struct xgene_port_ops xgene_gport_ops;
370 extern struct xgene_ring_ops xgene_ring1_ops;
372 #endif /* __XGENE_ENET_HW_H__ */