1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "xgene_enet_main.h"
23 #include "xgene_enet_hw.h"
25 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
27 u32 *ring_cfg = ring->state;
29 enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
31 ring_cfg[4] |= (1 << SELTHRSH_POS) &
32 CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
33 ring_cfg[3] |= ACCEPTLERR;
34 ring_cfg[2] |= QCOHERENT;
37 ring_cfg[2] |= (addr << RINGADDRL_POS) &
38 CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
39 addr >>= RINGADDRL_LEN;
40 ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
41 ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
42 CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
45 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
47 u32 *ring_cfg = ring->state;
51 is_bufpool = xgene_enet_is_bufpool(ring->id);
52 val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
53 ring_cfg[4] |= (val << RINGTYPE_POS) &
54 CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
57 ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
58 CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
62 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
64 u32 *ring_cfg = ring->state;
66 ring_cfg[3] |= RECOMBBUF;
67 ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
68 CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
69 ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
72 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
75 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
77 iowrite32(data, pdata->ring_csr_addr + offset);
80 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
81 u32 offset, u32 *data)
83 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
85 *data = ioread32(pdata->ring_csr_addr + offset);
88 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
90 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
93 xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
94 for (i = 0; i < pdata->ring_ops->num_ring_config; i++) {
95 xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
100 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
102 memset(ring->state, 0, sizeof(ring->state));
103 xgene_enet_write_ring_state(ring);
106 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
108 xgene_enet_ring_set_type(ring);
110 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||
111 xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)
112 xgene_enet_ring_set_recombbuf(ring);
114 xgene_enet_ring_init(ring);
115 xgene_enet_write_ring_state(ring);
118 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
120 u32 ring_id_val, ring_id_buf;
123 is_bufpool = xgene_enet_is_bufpool(ring->id);
125 ring_id_val = ring->id & GENMASK(9, 0);
126 ring_id_val |= OVERWRITE;
128 ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
129 ring_id_buf |= PREFETCH_BUF_EN;
131 ring_id_buf |= IS_BUFFER_POOL;
133 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
134 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
137 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
141 ring_id = ring->id | OVERWRITE;
142 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
143 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
146 static struct xgene_enet_desc_ring *xgene_enet_setup_ring(
147 struct xgene_enet_desc_ring *ring)
149 u32 size = ring->size;
153 xgene_enet_clr_ring_state(ring);
154 xgene_enet_set_ring_state(ring);
155 xgene_enet_set_ring_id(ring);
157 ring->slots = xgene_enet_get_numslots(ring->id, size);
159 is_bufpool = xgene_enet_is_bufpool(ring->id);
160 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
163 for (i = 0; i < ring->slots; i++)
164 xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
166 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
167 data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
168 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
173 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
178 is_bufpool = xgene_enet_is_bufpool(ring->id);
179 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
182 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
183 data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
184 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
187 xgene_enet_clr_desc_ring_id(ring);
188 xgene_enet_clr_ring_state(ring);
191 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
193 iowrite32(count, ring->cmd);
196 static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
198 u32 __iomem *cmd_base = ring->cmd_base;
199 u32 ring_state, num_msgs;
201 ring_state = ioread32(&cmd_base[1]);
202 num_msgs = GET_VAL(NUMMSGSINQ, ring_state);
207 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
208 struct xgene_enet_pdata *pdata,
209 enum xgene_enet_err_code status)
213 ring->rx_crc_errors++;
216 case INGRESS_CHECKSUM:
217 case INGRESS_CHECKSUM_COMPUTE:
221 case INGRESS_TRUNC_FRAME:
222 ring->rx_frame_errors++;
225 case INGRESS_PKT_LEN:
226 ring->rx_length_errors++;
229 case INGRESS_PKT_UNDER:
230 ring->rx_frame_errors++;
233 case INGRESS_FIFO_OVERRUN:
234 ring->rx_fifo_errors++;
241 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
244 void __iomem *addr = pdata->eth_csr_addr + offset;
246 iowrite32(val, addr);
249 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
252 void __iomem *addr = pdata->eth_ring_if_addr + offset;
254 iowrite32(val, addr);
257 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
260 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
262 iowrite32(val, addr);
265 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
268 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
270 iowrite32(val, addr);
273 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
274 void __iomem *cmd, void __iomem *cmd_done,
275 u32 wr_addr, u32 wr_data)
280 iowrite32(wr_addr, addr);
281 iowrite32(wr_data, wr);
282 iowrite32(XGENE_ENET_WR_CMD, cmd);
284 /* wait for write command to complete */
285 while (!(done = ioread32(cmd_done)) && wait--)
296 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata,
297 u32 wr_addr, u32 wr_data)
299 void __iomem *addr, *wr, *cmd, *cmd_done;
301 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
302 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
303 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
304 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
306 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
307 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
311 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
312 u32 offset, u32 *val)
314 void __iomem *addr = pdata->eth_csr_addr + offset;
316 *val = ioread32(addr);
319 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
320 u32 offset, u32 *val)
322 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
324 *val = ioread32(addr);
327 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
328 u32 offset, u32 *val)
330 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
332 *val = ioread32(addr);
335 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
336 void __iomem *cmd, void __iomem *cmd_done,
337 u32 rd_addr, u32 *rd_data)
342 iowrite32(rd_addr, addr);
343 iowrite32(XGENE_ENET_RD_CMD, cmd);
345 /* wait for read command to complete */
346 while (!(done = ioread32(cmd_done)) && wait--)
352 *rd_data = ioread32(rd);
358 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata,
359 u32 rd_addr, u32 *rd_data)
361 void __iomem *addr, *rd, *cmd, *cmd_done;
363 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
364 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
365 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
366 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
368 if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
369 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
373 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
376 u8 *dev_addr = pdata->ndev->dev_addr;
378 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
379 (dev_addr[1] << 8) | dev_addr[0];
380 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
382 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0);
383 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1);
386 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
388 struct net_device *ndev = pdata->ndev;
392 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
394 usleep_range(100, 110);
395 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
396 } while ((data != 0xffffffff) && wait--);
398 if (data != 0xffffffff) {
399 netdev_err(ndev, "Failed to release memory from shutdown\n");
406 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
408 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
409 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0);
412 static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
414 struct device *dev = &pdata->pdev->dev;
417 struct clk *parent = clk_get_parent(pdata->clk);
419 switch (pdata->phy_speed) {
421 clk_set_rate(parent, 2500000);
424 clk_set_rate(parent, 25000000);
427 clk_set_rate(parent, 125000000);
433 switch (pdata->phy_speed) {
435 acpi_evaluate_object(ACPI_HANDLE(dev),
439 acpi_evaluate_object(ACPI_HANDLE(dev),
443 acpi_evaluate_object(ACPI_HANDLE(dev),
451 static void xgene_gmac_set_speed(struct xgene_enet_pdata *pdata)
453 struct device *dev = &pdata->pdev->dev;
455 u32 intf_ctl, rgmii, value;
457 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
458 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
459 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2);
460 xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl);
461 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
463 switch (pdata->phy_speed) {
465 ENET_INTERFACE_MODE2_SET(&mc2, 1);
466 intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
467 CFG_MACMODE_SET(&icm0, 0);
468 CFG_WAITASYNCRD_SET(&icm2, 500);
469 rgmii &= ~CFG_SPEED_1250;
472 ENET_INTERFACE_MODE2_SET(&mc2, 1);
473 intf_ctl &= ~ENET_GHD_MODE;
474 intf_ctl |= ENET_LHD_MODE;
475 CFG_MACMODE_SET(&icm0, 1);
476 CFG_WAITASYNCRD_SET(&icm2, 80);
477 rgmii &= ~CFG_SPEED_1250;
480 ENET_INTERFACE_MODE2_SET(&mc2, 2);
481 intf_ctl &= ~ENET_LHD_MODE;
482 intf_ctl |= ENET_GHD_MODE;
483 CFG_MACMODE_SET(&icm0, 2);
484 CFG_WAITASYNCRD_SET(&icm2, 0);
486 CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
487 CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
489 rgmii |= CFG_SPEED_1250;
491 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
492 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
493 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
497 mc2 |= FULL_DUPLEX2 | PAD_CRC;
498 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
499 xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
500 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
501 xgene_enet_configure_clock(pdata);
503 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
504 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
507 static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
511 if (!pdata->mdio_driver)
512 xgene_gmac_reset(pdata);
514 xgene_gmac_set_speed(pdata);
515 xgene_gmac_set_mac_addr(pdata);
517 /* Adjust MDC clock frequency */
518 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value);
519 MGMT_CLOCK_SEL_SET(&value, 7);
520 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
522 /* Enable drop if bufpool not available */
523 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
524 value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
525 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
527 /* Rtype should be copied from FP */
528 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
530 /* Rx-Tx traffic resume */
531 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
533 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
534 value &= ~TX_DV_GATE_EN0;
535 value &= ~RX_DV_GATE_EN0;
537 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
539 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
542 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
544 u32 val = 0xffffffff;
546 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
547 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
548 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
549 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
552 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
553 u32 dst_ring_num, u16 bufpool_id)
558 fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
560 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
561 cb |= CFG_CLE_BYPASS_EN0;
562 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
563 CFG_CLE_IP_HDR_LEN_SET(&cb, 0);
564 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
566 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
567 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
568 CFG_CLE_FPSEL0_SET(&cb, fpsel);
569 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
572 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
576 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
577 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
580 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
584 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
585 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
588 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
592 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
593 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
596 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
600 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
601 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
604 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
606 if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
609 if (ioread32(p->ring_csr_addr + SRST_ADDR))
615 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
617 struct device *dev = &pdata->pdev->dev;
619 if (!xgene_ring_mgr_init(pdata))
622 if (pdata->mdio_driver) {
623 xgene_enet_config_ring_if_assoc(pdata);
628 clk_prepare_enable(pdata->clk);
630 clk_disable_unprepare(pdata->clk);
632 clk_prepare_enable(pdata->clk);
636 if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) {
637 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
639 } else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev),
641 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
647 xgene_enet_ecc_init(pdata);
648 xgene_enet_config_ring_if_assoc(pdata);
653 static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
654 struct xgene_enet_desc_ring *ring)
658 val = xgene_enet_ring_bufnum(ring->id);
660 if (xgene_enet_is_bufpool(ring->id)) {
661 addr = ENET_CFGSSQMIFPRESET_ADDR;
662 data = BIT(val - 0x20);
664 addr = ENET_CFGSSQMIWQRESET_ADDR;
668 xgene_enet_wr_ring_if(pdata, addr, data);
671 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
673 struct device *dev = &pdata->pdev->dev;
674 struct xgene_enet_desc_ring *ring;
679 for (i = 0; i < pdata->rxq_cnt; i++) {
680 ring = pdata->rx_ring[i]->buf_pool;
682 val = xgene_enet_ring_bufnum(ring->id);
683 pb |= BIT(val - 0x20);
685 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);
688 for (i = 0; i < pdata->txq_cnt; i++) {
689 ring = pdata->tx_ring[i];
691 val = xgene_enet_ring_bufnum(ring->id);
694 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb);
697 if (!IS_ERR(pdata->clk))
698 clk_disable_unprepare(pdata->clk);
702 static void xgene_enet_adjust_link(struct net_device *ndev)
704 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
705 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
706 struct phy_device *phydev = ndev->phydev;
709 if (pdata->phy_speed != phydev->speed) {
710 pdata->phy_speed = phydev->speed;
711 mac_ops->set_speed(pdata);
712 mac_ops->rx_enable(pdata);
713 mac_ops->tx_enable(pdata);
714 phy_print_status(phydev);
717 mac_ops->rx_disable(pdata);
718 mac_ops->tx_disable(pdata);
719 pdata->phy_speed = SPEED_UNKNOWN;
720 phy_print_status(phydev);
725 static struct acpi_device *acpi_phy_find_device(struct device *dev)
727 struct acpi_reference_args args;
728 struct fwnode_handle *fw_node;
731 fw_node = acpi_fwnode_handle(ACPI_COMPANION(dev));
732 status = acpi_node_get_property_reference(fw_node, "phy-handle", 0,
734 if (ACPI_FAILURE(status)) {
735 dev_dbg(dev, "No matching phy in ACPI table\n");
743 int xgene_enet_phy_connect(struct net_device *ndev)
745 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
746 struct device_node *np;
747 struct phy_device *phy_dev;
748 struct device *dev = &pdata->pdev->dev;
752 for (i = 0 ; i < 2; i++) {
753 np = of_parse_phandle(dev->of_node, "phy-handle", i);
754 phy_dev = of_phy_connect(ndev, np,
755 &xgene_enet_adjust_link,
763 netdev_err(ndev, "Could not connect to PHY\n");
768 struct acpi_device *adev = acpi_phy_find_device(dev);
770 phy_dev = adev->driver_data;
775 phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
777 netdev_err(ndev, "Could not connect to PHY\n");
785 pdata->phy_speed = SPEED_UNKNOWN;
786 phy_dev->supported &= ~SUPPORTED_10baseT_Half &
787 ~SUPPORTED_100baseT_Half &
788 ~SUPPORTED_1000baseT_Half;
789 phy_dev->advertising = phy_dev->supported;
794 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata,
795 struct mii_bus *mdio)
797 struct device *dev = &pdata->pdev->dev;
798 struct net_device *ndev = pdata->ndev;
799 struct phy_device *phy;
800 struct device_node *child_np;
801 struct device_node *mdio_np = NULL;
806 for_each_child_of_node(dev->of_node, child_np) {
807 if (of_device_is_compatible(child_np,
815 netdev_dbg(ndev, "No mdio node in the dts\n");
819 return of_mdiobus_register(mdio, mdio_np);
822 /* Mask out all PHYs from auto probing. */
825 /* Register the MDIO bus */
826 ret = mdiobus_register(mdio);
830 ret = device_property_read_u32(dev, "phy-channel", &phy_addr);
832 ret = device_property_read_u32(dev, "phy-addr", &phy_addr);
836 phy = xgene_enet_phy_register(mdio, phy_addr);
843 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
845 struct net_device *ndev = pdata->ndev;
846 struct mii_bus *mdio_bus;
849 mdio_bus = mdiobus_alloc();
853 mdio_bus->name = "APM X-Gene MDIO bus";
854 mdio_bus->read = xgene_mdio_rgmii_read;
855 mdio_bus->write = xgene_mdio_rgmii_write;
856 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
859 mdio_bus->priv = (void __force *)pdata->mcx_mac_addr;
860 mdio_bus->parent = &pdata->pdev->dev;
862 ret = xgene_mdiobus_register(pdata, mdio_bus);
864 netdev_err(ndev, "Failed to register MDIO bus\n");
865 mdiobus_free(mdio_bus);
868 pdata->mdio_bus = mdio_bus;
870 ret = xgene_enet_phy_connect(ndev);
872 xgene_enet_mdio_remove(pdata);
877 void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata)
879 struct net_device *ndev = pdata->ndev;
882 phy_disconnect(ndev->phydev);
885 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
887 struct net_device *ndev = pdata->ndev;
890 phy_disconnect(ndev->phydev);
892 mdiobus_unregister(pdata->mdio_bus);
893 mdiobus_free(pdata->mdio_bus);
894 pdata->mdio_bus = NULL;
897 const struct xgene_mac_ops xgene_gmac_ops = {
898 .init = xgene_gmac_init,
899 .reset = xgene_gmac_reset,
900 .rx_enable = xgene_gmac_rx_enable,
901 .tx_enable = xgene_gmac_tx_enable,
902 .rx_disable = xgene_gmac_rx_disable,
903 .tx_disable = xgene_gmac_tx_disable,
904 .set_speed = xgene_gmac_set_speed,
905 .set_mac_addr = xgene_gmac_set_mac_addr,
908 const struct xgene_port_ops xgene_gport_ops = {
909 .reset = xgene_enet_reset,
910 .clear = xgene_enet_clear,
911 .cle_bypass = xgene_enet_cle_bypass,
912 .shutdown = xgene_gport_shutdown,
915 struct xgene_ring_ops xgene_ring1_ops = {
916 .num_ring_config = NUM_RING_CONFIG,
917 .num_ring_id_shift = 6,
918 .setup = xgene_enet_setup_ring,
919 .clear = xgene_enet_clear_ring,
920 .wr_cmd = xgene_enet_wr_cmd,
921 .len = xgene_enet_ring_len,