2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
125 #include "xgbe-common.h"
127 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
132 #define XGBE_MUTEX_RELEASE 0x80000000
134 #define XGBE_SFP_DIRECT 7
136 /* I2C target addresses */
137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139 #define XGBE_SFP_PHY_ADDRESS 0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
142 /* SFP sideband signal indicators */
143 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146 #define XGBE_GPIO_NO_RX_LOS BIT(3)
148 /* Rate-change complete wait/retry count */
149 #define XGBE_RATECHANGE_COUNT 500
151 /* CDR delay values for KR support (in usec) */
152 #define XGBE_CDR_DELAY_INIT 10000
153 #define XGBE_CDR_DELAY_INC 10000
154 #define XGBE_CDR_DELAY_MAX 100000
156 /* RRC frequency during link status check */
157 #define XGBE_RRC_FREQUENCY 10
159 enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
172 enum xgbe_conn_type {
173 XGBE_CONN_TYPE_NONE = 0,
176 XGBE_CONN_TYPE_RSVD1,
177 XGBE_CONN_TYPE_BACKPLANE,
181 /* SFP/SFP+ related definitions */
183 XGBE_SFP_COMM_DIRECT = 0,
184 XGBE_SFP_COMM_PCA9545,
187 enum xgbe_sfp_cable {
188 XGBE_SFP_CABLE_UNKNOWN = 0,
189 XGBE_SFP_CABLE_ACTIVE,
190 XGBE_SFP_CABLE_PASSIVE,
191 XGBE_SFP_CABLE_FIBER,
195 XGBE_SFP_BASE_UNKNOWN = 0,
196 XGBE_SFP_BASE_1000_T,
197 XGBE_SFP_BASE_1000_SX,
198 XGBE_SFP_BASE_1000_LX,
199 XGBE_SFP_BASE_1000_CX,
200 XGBE_SFP_BASE_10000_SR,
201 XGBE_SFP_BASE_10000_LR,
202 XGBE_SFP_BASE_10000_LRM,
203 XGBE_SFP_BASE_10000_ER,
204 XGBE_SFP_BASE_10000_CR,
207 enum xgbe_sfp_speed {
208 XGBE_SFP_SPEED_UNKNOWN = 0,
209 XGBE_SFP_SPEED_100_1000,
211 XGBE_SFP_SPEED_10000,
214 /* SFP Serial ID Base ID values relative to an offset of 0 */
215 #define XGBE_SFP_BASE_ID 0
216 #define XGBE_SFP_ID_SFP 0x03
218 #define XGBE_SFP_BASE_EXT_ID 1
219 #define XGBE_SFP_EXT_ID_SFP 0x04
221 #define XGBE_SFP_BASE_10GBE_CC 3
222 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
223 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
224 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
225 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
227 #define XGBE_SFP_BASE_1GBE_CC 6
228 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
229 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
230 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
231 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
233 #define XGBE_SFP_BASE_CABLE 8
234 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
235 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
237 #define XGBE_SFP_BASE_BR 12
238 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
239 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
241 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
243 #define XGBE_SFP_BASE_VENDOR_NAME 20
244 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
245 #define XGBE_SFP_BASE_VENDOR_PN 40
246 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
247 #define XGBE_SFP_BASE_VENDOR_REV 56
248 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
250 #define XGBE_SFP_BASE_CC 63
252 /* SFP Serial ID Extended ID values relative to an offset of 64 */
253 #define XGBE_SFP_BASE_VENDOR_SN 4
254 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
256 #define XGBE_SFP_EXTD_OPT1 1
257 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
258 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
260 #define XGBE_SFP_EXTD_DIAG 28
261 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
263 #define XGBE_SFP_EXTD_SFF_8472 30
265 #define XGBE_SFP_EXTD_CC 31
267 struct xgbe_sfp_eeprom {
273 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
274 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
275 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
277 #define XGBE_SFP_EEPROM_BASE_LEN 256
278 #define XGBE_SFP_EEPROM_DIAG_LEN 256
279 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
280 XGBE_SFP_EEPROM_DIAG_LEN)
282 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
283 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
285 #define XGBE_MOLEX_VENDOR "Molex Inc. "
287 struct xgbe_sfp_ascii {
289 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
290 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
291 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
292 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
296 /* MDIO PHY reset types */
297 enum xgbe_mdio_reset {
298 XGBE_MDIO_RESET_NONE = 0,
299 XGBE_MDIO_RESET_I2C_GPIO,
300 XGBE_MDIO_RESET_INT_GPIO,
304 /* Re-driver related definitions */
305 enum xgbe_phy_redrv_if {
306 XGBE_PHY_REDRV_IF_MDIO = 0,
307 XGBE_PHY_REDRV_IF_I2C,
308 XGBE_PHY_REDRV_IF_MAX,
311 enum xgbe_phy_redrv_model {
312 XGBE_PHY_REDRV_MODEL_4223 = 0,
313 XGBE_PHY_REDRV_MODEL_4227,
314 XGBE_PHY_REDRV_MODEL_MAX,
317 enum xgbe_phy_redrv_mode {
318 XGBE_PHY_REDRV_MODE_CX = 5,
319 XGBE_PHY_REDRV_MODE_SR = 9,
322 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
324 /* PHY related configuration information */
325 struct xgbe_phy_data {
326 enum xgbe_port_mode port_mode;
328 unsigned int port_id;
330 unsigned int port_speeds;
332 enum xgbe_conn_type conn_type;
334 enum xgbe_mode cur_mode;
335 enum xgbe_mode start_mode;
337 unsigned int rrc_count;
339 unsigned int mdio_addr;
342 enum xgbe_sfp_comm sfp_comm;
343 unsigned int sfp_mux_address;
344 unsigned int sfp_mux_channel;
346 unsigned int sfp_gpio_address;
347 unsigned int sfp_gpio_mask;
348 unsigned int sfp_gpio_inputs;
349 unsigned int sfp_gpio_rx_los;
350 unsigned int sfp_gpio_tx_fault;
351 unsigned int sfp_gpio_mod_absent;
352 unsigned int sfp_gpio_rate_select;
354 unsigned int sfp_rx_los;
355 unsigned int sfp_tx_fault;
356 unsigned int sfp_mod_absent;
357 unsigned int sfp_changed;
358 unsigned int sfp_phy_avail;
359 unsigned int sfp_cable_len;
360 enum xgbe_sfp_base sfp_base;
361 enum xgbe_sfp_cable sfp_cable;
362 enum xgbe_sfp_speed sfp_speed;
363 struct xgbe_sfp_eeprom sfp_eeprom;
365 /* External PHY support */
366 enum xgbe_mdio_mode phydev_mode;
368 struct phy_device *phydev;
369 enum xgbe_mdio_reset mdio_reset;
370 unsigned int mdio_reset_addr;
371 unsigned int mdio_reset_gpio;
373 /* Re-driver support */
375 unsigned int redrv_if;
376 unsigned int redrv_addr;
377 unsigned int redrv_lane;
378 unsigned int redrv_model;
381 unsigned int phy_cdr_notrack;
382 unsigned int phy_cdr_delay;
385 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
386 static DEFINE_MUTEX(xgbe_phy_comm_lock);
388 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
390 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
391 struct xgbe_i2c_op *i2c_op)
393 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
396 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
399 struct xgbe_phy_data *phy_data = pdata->phy_data;
400 struct xgbe_i2c_op i2c_op;
402 u8 redrv_data[5], csum;
403 unsigned int i, retry;
406 /* High byte of register contains read/write indicator */
407 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
408 redrv_data[1] = reg & 0xff;
409 redrv_val = (__be16 *)&redrv_data[2];
410 *redrv_val = cpu_to_be16(val);
412 /* Calculate 1 byte checksum */
414 for (i = 0; i < 4; i++) {
415 csum += redrv_data[i];
416 if (redrv_data[i] > csum)
419 redrv_data[4] = ~csum;
423 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
424 i2c_op.target = phy_data->redrv_addr;
425 i2c_op.len = sizeof(redrv_data);
426 i2c_op.buf = redrv_data;
427 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
429 if ((ret == -EAGAIN) && retry--)
437 i2c_op.cmd = XGBE_I2C_CMD_READ;
438 i2c_op.target = phy_data->redrv_addr;
440 i2c_op.buf = redrv_data;
441 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
443 if ((ret == -EAGAIN) && retry--)
449 if (redrv_data[0] != 0xff) {
450 netif_dbg(pdata, drv, pdata->netdev,
451 "Redriver write checksum error\n");
458 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
459 void *val, unsigned int val_len)
461 struct xgbe_i2c_op i2c_op;
466 /* Write the specfied register */
467 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
468 i2c_op.target = target;
469 i2c_op.len = val_len;
471 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
472 if ((ret == -EAGAIN) && retry--)
478 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
479 void *reg, unsigned int reg_len,
480 void *val, unsigned int val_len)
482 struct xgbe_i2c_op i2c_op;
487 /* Set the specified register to read */
488 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
489 i2c_op.target = target;
490 i2c_op.len = reg_len;
492 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
494 if ((ret == -EAGAIN) && retry--)
502 /* Read the specfied register */
503 i2c_op.cmd = XGBE_I2C_CMD_READ;
504 i2c_op.target = target;
505 i2c_op.len = val_len;
507 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
508 if ((ret == -EAGAIN) && retry--)
514 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
516 struct xgbe_phy_data *phy_data = pdata->phy_data;
517 struct xgbe_i2c_op i2c_op;
520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
523 /* Select no mux channels */
525 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
526 i2c_op.target = phy_data->sfp_mux_address;
527 i2c_op.len = sizeof(mux_channel);
528 i2c_op.buf = &mux_channel;
530 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
533 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
535 struct xgbe_phy_data *phy_data = pdata->phy_data;
536 struct xgbe_i2c_op i2c_op;
539 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
542 /* Select desired mux channel */
543 mux_channel = 1 << phy_data->sfp_mux_channel;
544 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
545 i2c_op.target = phy_data->sfp_mux_address;
546 i2c_op.len = sizeof(mux_channel);
547 i2c_op.buf = &mux_channel;
549 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
552 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
554 mutex_unlock(&xgbe_phy_comm_lock);
557 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
559 struct xgbe_phy_data *phy_data = pdata->phy_data;
560 unsigned long timeout;
561 unsigned int mutex_id;
563 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
564 * the driver needs to take the software mutex and then the hardware
565 * mutexes before being able to use the busses.
567 mutex_lock(&xgbe_phy_comm_lock);
569 /* Clear the mutexes */
570 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
571 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
573 /* Mutex formats are the same for I2C and MDIO/GPIO */
575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
576 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
578 timeout = jiffies + (5 * HZ);
579 while (time_before(jiffies, timeout)) {
580 /* Must be all zeroes in order to obtain the mutex */
581 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
582 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
583 usleep_range(100, 200);
587 /* Obtain the mutex */
588 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
589 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
594 mutex_unlock(&xgbe_phy_comm_lock);
596 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
601 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
606 if (reg & MII_ADDR_C45) {
607 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
610 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
614 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
617 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
623 ret = xgbe_phy_sfp_get_mux(pdata);
627 mii_data[0] = reg & 0xff;
628 mii_val = (__be16 *)&mii_data[1];
629 *mii_val = cpu_to_be16(val);
631 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
632 mii_data, sizeof(mii_data));
634 xgbe_phy_sfp_put_mux(pdata);
639 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
641 struct xgbe_prv_data *pdata = mii->priv;
642 struct xgbe_phy_data *phy_data = pdata->phy_data;
645 ret = xgbe_phy_get_comm_ownership(pdata);
649 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
650 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
651 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
652 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
656 xgbe_phy_put_comm_ownership(pdata);
661 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
664 struct xgbe_phy_data *phy_data = pdata->phy_data;
666 if (reg & MII_ADDR_C45) {
667 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
670 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
674 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
677 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
683 ret = xgbe_phy_sfp_get_mux(pdata);
688 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
689 &mii_reg, sizeof(mii_reg),
690 &mii_val, sizeof(mii_val));
692 ret = be16_to_cpu(mii_val);
694 xgbe_phy_sfp_put_mux(pdata);
699 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
701 struct xgbe_prv_data *pdata = mii->priv;
702 struct xgbe_phy_data *phy_data = pdata->phy_data;
705 ret = xgbe_phy_get_comm_ownership(pdata);
709 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
710 ret = xgbe_phy_i2c_mii_read(pdata, reg);
711 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
712 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
716 xgbe_phy_put_comm_ownership(pdata);
721 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
723 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
724 struct xgbe_phy_data *phy_data = pdata->phy_data;
726 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
731 if (phy_data->sfp_mod_absent) {
732 pdata->phy.speed = SPEED_UNKNOWN;
733 pdata->phy.duplex = DUPLEX_UNKNOWN;
734 pdata->phy.autoneg = AUTONEG_ENABLE;
735 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
737 XGBE_SET_SUP(lks, Autoneg);
738 XGBE_SET_SUP(lks, Pause);
739 XGBE_SET_SUP(lks, Asym_Pause);
740 XGBE_SET_SUP(lks, TP);
741 XGBE_SET_SUP(lks, FIBRE);
743 XGBE_LM_COPY(lks, advertising, lks, supported);
748 switch (phy_data->sfp_base) {
749 case XGBE_SFP_BASE_1000_T:
750 case XGBE_SFP_BASE_1000_SX:
751 case XGBE_SFP_BASE_1000_LX:
752 case XGBE_SFP_BASE_1000_CX:
753 pdata->phy.speed = SPEED_UNKNOWN;
754 pdata->phy.duplex = DUPLEX_UNKNOWN;
755 pdata->phy.autoneg = AUTONEG_ENABLE;
756 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
757 XGBE_SET_SUP(lks, Autoneg);
758 XGBE_SET_SUP(lks, Pause);
759 XGBE_SET_SUP(lks, Asym_Pause);
760 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
761 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
762 XGBE_SET_SUP(lks, 100baseT_Full);
763 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
764 XGBE_SET_SUP(lks, 1000baseT_Full);
766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
767 XGBE_SET_SUP(lks, 1000baseX_Full);
770 case XGBE_SFP_BASE_10000_SR:
771 case XGBE_SFP_BASE_10000_LR:
772 case XGBE_SFP_BASE_10000_LRM:
773 case XGBE_SFP_BASE_10000_ER:
774 case XGBE_SFP_BASE_10000_CR:
775 pdata->phy.speed = SPEED_10000;
776 pdata->phy.duplex = DUPLEX_FULL;
777 pdata->phy.autoneg = AUTONEG_DISABLE;
778 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
779 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
780 switch (phy_data->sfp_base) {
781 case XGBE_SFP_BASE_10000_SR:
782 XGBE_SET_SUP(lks, 10000baseSR_Full);
784 case XGBE_SFP_BASE_10000_LR:
785 XGBE_SET_SUP(lks, 10000baseLR_Full);
787 case XGBE_SFP_BASE_10000_LRM:
788 XGBE_SET_SUP(lks, 10000baseLRM_Full);
790 case XGBE_SFP_BASE_10000_ER:
791 XGBE_SET_SUP(lks, 10000baseER_Full);
793 case XGBE_SFP_BASE_10000_CR:
794 XGBE_SET_SUP(lks, 10000baseCR_Full);
802 pdata->phy.speed = SPEED_UNKNOWN;
803 pdata->phy.duplex = DUPLEX_UNKNOWN;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
809 switch (phy_data->sfp_base) {
810 case XGBE_SFP_BASE_1000_T:
811 case XGBE_SFP_BASE_1000_CX:
812 case XGBE_SFP_BASE_10000_CR:
813 XGBE_SET_SUP(lks, TP);
816 XGBE_SET_SUP(lks, FIBRE);
820 XGBE_LM_COPY(lks, advertising, lks, supported);
823 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
824 enum xgbe_sfp_speed sfp_speed)
828 sfp_base = sfp_eeprom->base;
831 case XGBE_SFP_SPEED_1000:
832 min = XGBE_SFP_BASE_BR_1GBE_MIN;
834 case XGBE_SFP_SPEED_10000:
835 min = XGBE_SFP_BASE_BR_10GBE_MIN;
841 return sfp_base[XGBE_SFP_BASE_BR] >= min;
844 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
846 struct xgbe_phy_data *phy_data = pdata->phy_data;
848 if (phy_data->phydev) {
849 phy_detach(phy_data->phydev);
850 phy_device_remove(phy_data->phydev);
851 phy_device_free(phy_data->phydev);
852 phy_data->phydev = NULL;
856 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
858 struct xgbe_phy_data *phy_data = pdata->phy_data;
859 unsigned int phy_id = phy_data->phydev->phy_id;
861 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
864 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
867 /* Enable Base-T AN */
868 phy_write(phy_data->phydev, 0x16, 0x0001);
869 phy_write(phy_data->phydev, 0x00, 0x9140);
870 phy_write(phy_data->phydev, 0x16, 0x0000);
872 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
873 phy_write(phy_data->phydev, 0x1b, 0x9084);
874 phy_write(phy_data->phydev, 0x09, 0x0e00);
875 phy_write(phy_data->phydev, 0x00, 0x8140);
876 phy_write(phy_data->phydev, 0x04, 0x0d01);
877 phy_write(phy_data->phydev, 0x00, 0x9140);
879 phy_data->phydev->supported = PHY_GBIT_FEATURES;
880 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
881 phy_data->phydev->advertising = phy_data->phydev->supported;
883 netif_dbg(pdata, drv, pdata->netdev,
884 "Finisar PHY quirk in place\n");
889 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
891 struct xgbe_phy_data *phy_data = pdata->phy_data;
892 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
893 unsigned int phy_id = phy_data->phydev->phy_id;
896 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
899 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
900 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
903 /* For Bel-Fuse, use the extra AN flag */
906 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
907 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
910 if ((phy_id & 0xfffffff0) != 0x03625d10)
913 /* Reset PHY - wait for self-clearing reset bit to clear */
914 genphy_soft_reset(phy_data->phydev);
916 /* Disable RGMII mode */
917 phy_write(phy_data->phydev, 0x18, 0x7007);
918 reg = phy_read(phy_data->phydev, 0x18);
919 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
921 /* Enable fiber register bank */
922 phy_write(phy_data->phydev, 0x1c, 0x7c00);
923 reg = phy_read(phy_data->phydev, 0x1c);
926 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
928 /* Power down SerDes */
929 reg = phy_read(phy_data->phydev, 0x00);
930 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
932 /* Configure SGMII-to-Copper mode */
933 phy_write(phy_data->phydev, 0x1c, 0x7c00);
934 reg = phy_read(phy_data->phydev, 0x1c);
937 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
939 /* Power up SerDes */
940 reg = phy_read(phy_data->phydev, 0x00);
941 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
943 /* Enable copper register bank */
944 phy_write(phy_data->phydev, 0x1c, 0x7c00);
945 reg = phy_read(phy_data->phydev, 0x1c);
948 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
950 /* Power up SerDes */
951 reg = phy_read(phy_data->phydev, 0x00);
952 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
954 phy_data->phydev->supported = PHY_GBIT_FEATURES;
955 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
956 phy_data->phydev->advertising = phy_data->phydev->supported;
958 netif_dbg(pdata, drv, pdata->netdev,
959 "BelFuse PHY quirk in place\n");
964 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
966 if (xgbe_phy_belfuse_phy_quirks(pdata))
969 if (xgbe_phy_finisar_phy_quirks(pdata))
973 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
975 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
976 struct xgbe_phy_data *phy_data = pdata->phy_data;
977 struct phy_device *phydev;
981 /* If we already have a PHY, just return */
982 if (phy_data->phydev)
985 /* Clear the extra AN flag */
988 /* Check for the use of an external PHY */
989 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
992 /* For SFP, only use an external PHY if available */
993 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
994 !phy_data->sfp_phy_avail)
997 /* Set the proper MDIO mode for the PHY */
998 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
999 phy_data->phydev_mode);
1001 netdev_err(pdata->netdev,
1002 "mdio port/clause not compatible (%u/%u)\n",
1003 phy_data->mdio_addr, phy_data->phydev_mode);
1007 /* Create and connect to the PHY device */
1008 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1009 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1010 if (IS_ERR(phydev)) {
1011 netdev_err(pdata->netdev, "get_phy_device failed\n");
1014 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1017 /*TODO: If c45, add request_module based on one of the MMD ids? */
1019 ret = phy_device_register(phydev);
1021 netdev_err(pdata->netdev, "phy_device_register failed\n");
1022 phy_device_free(phydev);
1026 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1027 PHY_INTERFACE_MODE_SGMII);
1029 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1030 phy_device_remove(phydev);
1031 phy_device_free(phydev);
1034 phy_data->phydev = phydev;
1036 xgbe_phy_external_phy_quirks(pdata);
1038 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1039 lks->link_modes.advertising);
1040 phydev->advertising &= advertising;
1042 phy_start_aneg(phy_data->phydev);
1047 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1049 struct xgbe_phy_data *phy_data = pdata->phy_data;
1052 if (!phy_data->sfp_changed)
1055 phy_data->sfp_phy_avail = 0;
1057 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1060 /* Check access to the PHY by reading CTRL1 */
1061 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1065 /* Successfully accessed the PHY */
1066 phy_data->sfp_phy_avail = 1;
1069 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1071 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1073 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1076 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1079 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1085 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1087 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1089 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1092 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1095 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1101 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1103 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1106 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1112 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1114 struct xgbe_phy_data *phy_data = pdata->phy_data;
1115 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1118 sfp_base = sfp_eeprom->base;
1120 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1123 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1126 /* Update transceiver signals (eeprom extd/options) */
1127 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1128 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1130 /* Assume FIBER cable unless told otherwise */
1131 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1132 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1133 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1134 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) {
1135 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1137 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER;
1140 /* Determine the type of SFP */
1141 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER &&
1142 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1143 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1144 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1145 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1146 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1147 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1148 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1149 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1150 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1151 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1152 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1153 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1154 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1155 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1156 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1157 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1158 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1159 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1161 switch (phy_data->sfp_base) {
1162 case XGBE_SFP_BASE_1000_T:
1163 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1165 case XGBE_SFP_BASE_1000_SX:
1166 case XGBE_SFP_BASE_1000_LX:
1167 case XGBE_SFP_BASE_1000_CX:
1168 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1170 case XGBE_SFP_BASE_10000_SR:
1171 case XGBE_SFP_BASE_10000_LR:
1172 case XGBE_SFP_BASE_10000_LRM:
1173 case XGBE_SFP_BASE_10000_ER:
1174 case XGBE_SFP_BASE_10000_CR:
1175 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1182 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1183 struct xgbe_sfp_eeprom *sfp_eeprom)
1185 struct xgbe_sfp_ascii sfp_ascii;
1186 char *sfp_data = (char *)&sfp_ascii;
1188 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1189 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1190 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1191 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1192 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1195 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1196 XGBE_SFP_BASE_VENDOR_PN_LEN);
1197 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1198 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1201 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1202 XGBE_SFP_BASE_VENDOR_REV_LEN);
1203 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1204 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1207 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1208 XGBE_SFP_BASE_VENDOR_SN_LEN);
1209 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1210 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1214 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1218 for (cc = 0; len; buf++, len--)
1221 return (cc == cc_in) ? true : false;
1224 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1226 struct xgbe_phy_data *phy_data = pdata->phy_data;
1227 struct xgbe_sfp_eeprom sfp_eeprom;
1231 ret = xgbe_phy_sfp_get_mux(pdata);
1233 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1234 netdev_name(pdata->netdev));
1238 /* Read the SFP serial ID eeprom */
1240 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1241 &eeprom_addr, sizeof(eeprom_addr),
1242 &sfp_eeprom, sizeof(sfp_eeprom));
1244 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1245 netdev_name(pdata->netdev));
1249 /* Validate the contents read */
1250 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1252 sizeof(sfp_eeprom.base) - 1)) {
1257 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1259 sizeof(sfp_eeprom.extd) - 1)) {
1264 /* Check for an added or changed SFP */
1265 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1266 phy_data->sfp_changed = 1;
1268 if (netif_msg_drv(pdata))
1269 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1271 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1273 xgbe_phy_free_phy_device(pdata);
1275 phy_data->sfp_changed = 0;
1279 xgbe_phy_sfp_put_mux(pdata);
1284 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1286 struct xgbe_phy_data *phy_data = pdata->phy_data;
1287 u8 gpio_reg, gpio_ports[2];
1290 /* Read the input port registers */
1292 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1293 &gpio_reg, sizeof(gpio_reg),
1294 gpio_ports, sizeof(gpio_ports));
1296 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1297 netdev_name(pdata->netdev));
1301 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1303 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1306 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1308 struct xgbe_phy_data *phy_data = pdata->phy_data;
1310 xgbe_phy_free_phy_device(pdata);
1312 phy_data->sfp_mod_absent = 1;
1313 phy_data->sfp_phy_avail = 0;
1314 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1317 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1319 phy_data->sfp_rx_los = 0;
1320 phy_data->sfp_tx_fault = 0;
1321 phy_data->sfp_mod_absent = 1;
1322 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1323 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1324 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1327 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1329 struct xgbe_phy_data *phy_data = pdata->phy_data;
1332 /* Reset the SFP signals and info */
1333 xgbe_phy_sfp_reset(phy_data);
1335 ret = xgbe_phy_get_comm_ownership(pdata);
1339 /* Read the SFP signals and check for module presence */
1340 xgbe_phy_sfp_signals(pdata);
1341 if (phy_data->sfp_mod_absent) {
1342 xgbe_phy_sfp_mod_absent(pdata);
1346 ret = xgbe_phy_sfp_read_eeprom(pdata);
1348 /* Treat any error as if there isn't an SFP plugged in */
1349 xgbe_phy_sfp_reset(phy_data);
1350 xgbe_phy_sfp_mod_absent(pdata);
1354 xgbe_phy_sfp_parse_eeprom(pdata);
1356 xgbe_phy_sfp_external_phy(pdata);
1359 xgbe_phy_sfp_phy_settings(pdata);
1361 xgbe_phy_put_comm_ownership(pdata);
1364 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1365 struct ethtool_eeprom *eeprom, u8 *data)
1367 struct xgbe_phy_data *phy_data = pdata->phy_data;
1368 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1369 struct xgbe_sfp_eeprom *sfp_eeprom;
1370 unsigned int i, j, rem;
1380 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1385 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1390 if (!netif_running(pdata->netdev)) {
1395 if (phy_data->sfp_mod_absent) {
1400 ret = xgbe_phy_get_comm_ownership(pdata);
1406 ret = xgbe_phy_sfp_get_mux(pdata);
1408 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1413 /* Read the SFP serial ID eeprom */
1415 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1416 &eeprom_addr, sizeof(eeprom_addr),
1417 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1419 netdev_err(pdata->netdev,
1420 "I2C error reading SFP EEPROM\n");
1425 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1427 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1428 /* Read the SFP diagnostic eeprom */
1430 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1431 &eeprom_addr, sizeof(eeprom_addr),
1432 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1433 XGBE_SFP_EEPROM_DIAG_LEN);
1435 netdev_err(pdata->netdev,
1436 "I2C error reading SFP DIAGS\n");
1442 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1443 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1444 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1447 data[i] = eeprom_data[j];
1452 xgbe_phy_sfp_put_mux(pdata);
1455 xgbe_phy_put_comm_ownership(pdata);
1463 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1464 struct ethtool_modinfo *modinfo)
1466 struct xgbe_phy_data *phy_data = pdata->phy_data;
1468 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1471 if (!netif_running(pdata->netdev))
1474 if (phy_data->sfp_mod_absent)
1477 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1478 modinfo->type = ETH_MODULE_SFF_8472;
1479 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1481 modinfo->type = ETH_MODULE_SFF_8079;
1482 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1488 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1490 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1491 struct xgbe_phy_data *phy_data = pdata->phy_data;
1492 u16 lcl_adv = 0, rmt_adv = 0;
1495 pdata->phy.tx_pause = 0;
1496 pdata->phy.rx_pause = 0;
1498 if (!phy_data->phydev)
1501 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1502 lcl_adv |= ADVERTISE_PAUSE_CAP;
1503 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1504 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1506 if (phy_data->phydev->pause) {
1507 XGBE_SET_LP_ADV(lks, Pause);
1508 rmt_adv |= LPA_PAUSE_CAP;
1510 if (phy_data->phydev->asym_pause) {
1511 XGBE_SET_LP_ADV(lks, Asym_Pause);
1512 rmt_adv |= LPA_PAUSE_ASYM;
1515 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1516 if (fc & FLOW_CTRL_TX)
1517 pdata->phy.tx_pause = 1;
1518 if (fc & FLOW_CTRL_RX)
1519 pdata->phy.rx_pause = 1;
1522 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1524 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1525 enum xgbe_mode mode;
1527 XGBE_SET_LP_ADV(lks, Autoneg);
1528 XGBE_SET_LP_ADV(lks, TP);
1530 /* Use external PHY to determine flow control */
1531 if (pdata->phy.pause_autoneg)
1532 xgbe_phy_phydev_flowctrl(pdata);
1534 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1535 case XGBE_SGMII_AN_LINK_SPEED_100:
1536 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1537 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1538 mode = XGBE_MODE_SGMII_100;
1540 /* Half-duplex not supported */
1541 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1542 mode = XGBE_MODE_UNKNOWN;
1545 case XGBE_SGMII_AN_LINK_SPEED_1000:
1546 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1547 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1548 mode = XGBE_MODE_SGMII_1000;
1550 /* Half-duplex not supported */
1551 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1552 mode = XGBE_MODE_UNKNOWN;
1556 mode = XGBE_MODE_UNKNOWN;
1562 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1564 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1565 enum xgbe_mode mode;
1566 unsigned int ad_reg, lp_reg;
1568 XGBE_SET_LP_ADV(lks, Autoneg);
1569 XGBE_SET_LP_ADV(lks, FIBRE);
1571 /* Compare Advertisement and Link Partner register */
1572 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1573 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1575 XGBE_SET_LP_ADV(lks, Pause);
1577 XGBE_SET_LP_ADV(lks, Asym_Pause);
1579 if (pdata->phy.pause_autoneg) {
1580 /* Set flow control based on auto-negotiation result */
1581 pdata->phy.tx_pause = 0;
1582 pdata->phy.rx_pause = 0;
1584 if (ad_reg & lp_reg & 0x100) {
1585 pdata->phy.tx_pause = 1;
1586 pdata->phy.rx_pause = 1;
1587 } else if (ad_reg & lp_reg & 0x80) {
1589 pdata->phy.rx_pause = 1;
1590 else if (lp_reg & 0x100)
1591 pdata->phy.tx_pause = 1;
1596 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1598 /* Half duplex is not supported */
1600 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1605 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1607 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1608 struct xgbe_phy_data *phy_data = pdata->phy_data;
1609 enum xgbe_mode mode;
1610 unsigned int ad_reg, lp_reg;
1612 XGBE_SET_LP_ADV(lks, Autoneg);
1613 XGBE_SET_LP_ADV(lks, Backplane);
1615 /* Use external PHY to determine flow control */
1616 if (pdata->phy.pause_autoneg)
1617 xgbe_phy_phydev_flowctrl(pdata);
1619 /* Compare Advertisement and Link Partner register 2 */
1620 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1621 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1623 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1625 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1628 if (ad_reg & 0x80) {
1629 switch (phy_data->port_mode) {
1630 case XGBE_PORT_MODE_BACKPLANE:
1631 mode = XGBE_MODE_KR;
1634 mode = XGBE_MODE_SFI;
1637 } else if (ad_reg & 0x20) {
1638 switch (phy_data->port_mode) {
1639 case XGBE_PORT_MODE_BACKPLANE:
1640 mode = XGBE_MODE_KX_1000;
1642 case XGBE_PORT_MODE_1000BASE_X:
1645 case XGBE_PORT_MODE_SFP:
1646 switch (phy_data->sfp_base) {
1647 case XGBE_SFP_BASE_1000_T:
1648 if (phy_data->phydev &&
1649 (phy_data->phydev->speed == SPEED_100))
1650 mode = XGBE_MODE_SGMII_100;
1652 mode = XGBE_MODE_SGMII_1000;
1654 case XGBE_SFP_BASE_1000_SX:
1655 case XGBE_SFP_BASE_1000_LX:
1656 case XGBE_SFP_BASE_1000_CX:
1663 if (phy_data->phydev &&
1664 (phy_data->phydev->speed == SPEED_100))
1665 mode = XGBE_MODE_SGMII_100;
1667 mode = XGBE_MODE_SGMII_1000;
1671 mode = XGBE_MODE_UNKNOWN;
1674 /* Compare Advertisement and Link Partner register 3 */
1675 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1676 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1677 if (lp_reg & 0xc000)
1678 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1683 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1685 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1686 enum xgbe_mode mode;
1687 unsigned int ad_reg, lp_reg;
1689 XGBE_SET_LP_ADV(lks, Autoneg);
1690 XGBE_SET_LP_ADV(lks, Backplane);
1692 /* Compare Advertisement and Link Partner register 1 */
1693 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1694 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1696 XGBE_SET_LP_ADV(lks, Pause);
1698 XGBE_SET_LP_ADV(lks, Asym_Pause);
1700 if (pdata->phy.pause_autoneg) {
1701 /* Set flow control based on auto-negotiation result */
1702 pdata->phy.tx_pause = 0;
1703 pdata->phy.rx_pause = 0;
1705 if (ad_reg & lp_reg & 0x400) {
1706 pdata->phy.tx_pause = 1;
1707 pdata->phy.rx_pause = 1;
1708 } else if (ad_reg & lp_reg & 0x800) {
1710 pdata->phy.rx_pause = 1;
1711 else if (lp_reg & 0x400)
1712 pdata->phy.tx_pause = 1;
1716 /* Compare Advertisement and Link Partner register 2 */
1717 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1718 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1720 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1722 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1726 mode = XGBE_MODE_KR;
1727 else if (ad_reg & 0x20)
1728 mode = XGBE_MODE_KX_1000;
1730 mode = XGBE_MODE_UNKNOWN;
1732 /* Compare Advertisement and Link Partner register 3 */
1733 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1734 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1735 if (lp_reg & 0xc000)
1736 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1741 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1743 switch (pdata->an_mode) {
1744 case XGBE_AN_MODE_CL73:
1745 return xgbe_phy_an73_outcome(pdata);
1746 case XGBE_AN_MODE_CL73_REDRV:
1747 return xgbe_phy_an73_redrv_outcome(pdata);
1748 case XGBE_AN_MODE_CL37:
1749 return xgbe_phy_an37_outcome(pdata);
1750 case XGBE_AN_MODE_CL37_SGMII:
1751 return xgbe_phy_an37_sgmii_outcome(pdata);
1753 return XGBE_MODE_UNKNOWN;
1757 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1758 struct ethtool_link_ksettings *dlks)
1760 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1761 struct xgbe_phy_data *phy_data = pdata->phy_data;
1763 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1765 /* Without a re-driver, just return current advertising */
1766 if (!phy_data->redrv)
1769 /* With the KR re-driver we need to advertise a single speed */
1770 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1771 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1773 /* Advertise FEC support is present */
1774 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1775 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1777 switch (phy_data->port_mode) {
1778 case XGBE_PORT_MODE_BACKPLANE:
1779 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1781 case XGBE_PORT_MODE_BACKPLANE_2500:
1782 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1784 case XGBE_PORT_MODE_1000BASE_T:
1785 case XGBE_PORT_MODE_1000BASE_X:
1786 case XGBE_PORT_MODE_NBASE_T:
1787 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1789 case XGBE_PORT_MODE_10GBASE_T:
1790 if (phy_data->phydev &&
1791 (phy_data->phydev->speed == SPEED_10000))
1792 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1794 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1796 case XGBE_PORT_MODE_10GBASE_R:
1797 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1799 case XGBE_PORT_MODE_SFP:
1800 switch (phy_data->sfp_base) {
1801 case XGBE_SFP_BASE_1000_T:
1802 case XGBE_SFP_BASE_1000_SX:
1803 case XGBE_SFP_BASE_1000_LX:
1804 case XGBE_SFP_BASE_1000_CX:
1805 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1808 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1813 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1818 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1820 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1821 struct xgbe_phy_data *phy_data = pdata->phy_data;
1825 ret = xgbe_phy_find_phy_device(pdata);
1829 if (!phy_data->phydev)
1832 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1833 lks->link_modes.advertising);
1835 phy_data->phydev->autoneg = pdata->phy.autoneg;
1836 phy_data->phydev->advertising = phy_data->phydev->supported &
1839 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1840 phy_data->phydev->speed = pdata->phy.speed;
1841 phy_data->phydev->duplex = pdata->phy.duplex;
1844 ret = phy_start_aneg(phy_data->phydev);
1849 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1851 switch (phy_data->sfp_base) {
1852 case XGBE_SFP_BASE_1000_T:
1853 return XGBE_AN_MODE_CL37_SGMII;
1854 case XGBE_SFP_BASE_1000_SX:
1855 case XGBE_SFP_BASE_1000_LX:
1856 case XGBE_SFP_BASE_1000_CX:
1857 return XGBE_AN_MODE_CL37;
1859 return XGBE_AN_MODE_NONE;
1863 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1865 struct xgbe_phy_data *phy_data = pdata->phy_data;
1867 /* A KR re-driver will always require CL73 AN */
1868 if (phy_data->redrv)
1869 return XGBE_AN_MODE_CL73_REDRV;
1871 switch (phy_data->port_mode) {
1872 case XGBE_PORT_MODE_BACKPLANE:
1873 return XGBE_AN_MODE_CL73;
1874 case XGBE_PORT_MODE_BACKPLANE_2500:
1875 return XGBE_AN_MODE_NONE;
1876 case XGBE_PORT_MODE_1000BASE_T:
1877 return XGBE_AN_MODE_CL37_SGMII;
1878 case XGBE_PORT_MODE_1000BASE_X:
1879 return XGBE_AN_MODE_CL37;
1880 case XGBE_PORT_MODE_NBASE_T:
1881 return XGBE_AN_MODE_CL37_SGMII;
1882 case XGBE_PORT_MODE_10GBASE_T:
1883 return XGBE_AN_MODE_CL73;
1884 case XGBE_PORT_MODE_10GBASE_R:
1885 return XGBE_AN_MODE_NONE;
1886 case XGBE_PORT_MODE_SFP:
1887 return xgbe_phy_an_sfp_mode(phy_data);
1889 return XGBE_AN_MODE_NONE;
1893 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1894 enum xgbe_phy_redrv_mode mode)
1896 struct xgbe_phy_data *phy_data = pdata->phy_data;
1897 u16 redrv_reg, redrv_val;
1899 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1900 redrv_val = (u16)mode;
1902 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1903 redrv_reg, redrv_val);
1906 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1907 enum xgbe_phy_redrv_mode mode)
1909 struct xgbe_phy_data *phy_data = pdata->phy_data;
1910 unsigned int redrv_reg;
1913 /* Calculate the register to write */
1914 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1916 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1921 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1923 struct xgbe_phy_data *phy_data = pdata->phy_data;
1924 enum xgbe_phy_redrv_mode mode;
1927 if (!phy_data->redrv)
1930 mode = XGBE_PHY_REDRV_MODE_CX;
1931 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1932 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1933 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1934 mode = XGBE_PHY_REDRV_MODE_SR;
1936 ret = xgbe_phy_get_comm_ownership(pdata);
1940 if (phy_data->redrv_if)
1941 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1943 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1945 xgbe_phy_put_comm_ownership(pdata);
1948 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1952 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1953 XGBE_PCS_PSEQ_STATE_MASK);
1954 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1955 /* Mailbox command timed out, reset of RX block is required.
1956 * This can be done by asseting the reset bit and wait for
1959 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1960 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1962 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1963 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1964 usleep_range(40, 50);
1965 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1969 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
1971 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1972 XGBE_PMA_PLL_CTRL_MASK,
1973 enable ? XGBE_PMA_PLL_CTRL_ENABLE
1974 : XGBE_PMA_PLL_CTRL_DISABLE);
1976 /* Wait for command to complete */
1977 usleep_range(100, 200);
1980 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1981 unsigned int cmd, unsigned int sub_cmd)
1983 unsigned int s0 = 0;
1986 /* Disable PLL re-initialization during FW command processing */
1987 xgbe_phy_pll_ctrl(pdata, false);
1989 /* Log if a previous command did not complete */
1990 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1991 netif_dbg(pdata, link, pdata->netdev,
1992 "firmware mailbox not ready for command\n");
1993 xgbe_phy_rx_reset(pdata);
1996 /* Construct the command */
1997 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1998 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2000 /* Issue the command */
2001 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2002 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2003 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2005 /* Wait for command to complete */
2006 wait = XGBE_RATECHANGE_COUNT;
2008 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2011 usleep_range(1000, 2000);
2014 netif_dbg(pdata, link, pdata->netdev,
2015 "firmware mailbox command did not complete\n");
2017 /* Reset on error */
2018 xgbe_phy_rx_reset(pdata);
2021 /* Enable PLL re-initialization */
2022 xgbe_phy_pll_ctrl(pdata, true);
2025 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2027 /* Receiver Reset Cycle */
2028 xgbe_phy_perform_ratechange(pdata, 5, 0);
2030 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2033 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2035 struct xgbe_phy_data *phy_data = pdata->phy_data;
2038 xgbe_phy_perform_ratechange(pdata, 0, 0);
2040 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2042 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2045 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2047 struct xgbe_phy_data *phy_data = pdata->phy_data;
2049 xgbe_phy_set_redrv_mode(pdata);
2052 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2053 xgbe_phy_perform_ratechange(pdata, 3, 0);
2055 if (phy_data->sfp_cable_len <= 1)
2056 xgbe_phy_perform_ratechange(pdata, 3, 1);
2057 else if (phy_data->sfp_cable_len <= 3)
2058 xgbe_phy_perform_ratechange(pdata, 3, 2);
2060 xgbe_phy_perform_ratechange(pdata, 3, 3);
2063 phy_data->cur_mode = XGBE_MODE_SFI;
2065 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2068 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2070 struct xgbe_phy_data *phy_data = pdata->phy_data;
2072 xgbe_phy_set_redrv_mode(pdata);
2075 xgbe_phy_perform_ratechange(pdata, 1, 3);
2077 phy_data->cur_mode = XGBE_MODE_X;
2079 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2082 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2084 struct xgbe_phy_data *phy_data = pdata->phy_data;
2086 xgbe_phy_set_redrv_mode(pdata);
2089 xgbe_phy_perform_ratechange(pdata, 1, 2);
2091 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2093 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2096 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2098 struct xgbe_phy_data *phy_data = pdata->phy_data;
2100 xgbe_phy_set_redrv_mode(pdata);
2103 xgbe_phy_perform_ratechange(pdata, 1, 1);
2105 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2107 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2110 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2112 struct xgbe_phy_data *phy_data = pdata->phy_data;
2114 xgbe_phy_set_redrv_mode(pdata);
2117 xgbe_phy_perform_ratechange(pdata, 4, 0);
2119 phy_data->cur_mode = XGBE_MODE_KR;
2121 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2124 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2126 struct xgbe_phy_data *phy_data = pdata->phy_data;
2128 xgbe_phy_set_redrv_mode(pdata);
2131 xgbe_phy_perform_ratechange(pdata, 2, 0);
2133 phy_data->cur_mode = XGBE_MODE_KX_2500;
2135 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2138 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2140 struct xgbe_phy_data *phy_data = pdata->phy_data;
2142 xgbe_phy_set_redrv_mode(pdata);
2145 xgbe_phy_perform_ratechange(pdata, 1, 3);
2147 phy_data->cur_mode = XGBE_MODE_KX_1000;
2149 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2152 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2154 struct xgbe_phy_data *phy_data = pdata->phy_data;
2156 return phy_data->cur_mode;
2159 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2161 struct xgbe_phy_data *phy_data = pdata->phy_data;
2163 /* No switching if not 10GBase-T */
2164 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2165 return xgbe_phy_cur_mode(pdata);
2167 switch (xgbe_phy_cur_mode(pdata)) {
2168 case XGBE_MODE_SGMII_100:
2169 case XGBE_MODE_SGMII_1000:
2170 return XGBE_MODE_KR;
2173 return XGBE_MODE_SGMII_1000;
2177 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2179 return XGBE_MODE_KX_2500;
2182 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2184 /* If we are in KR switch to KX, and vice-versa */
2185 switch (xgbe_phy_cur_mode(pdata)) {
2186 case XGBE_MODE_KX_1000:
2187 return XGBE_MODE_KR;
2190 return XGBE_MODE_KX_1000;
2194 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2196 struct xgbe_phy_data *phy_data = pdata->phy_data;
2198 switch (phy_data->port_mode) {
2199 case XGBE_PORT_MODE_BACKPLANE:
2200 return xgbe_phy_switch_bp_mode(pdata);
2201 case XGBE_PORT_MODE_BACKPLANE_2500:
2202 return xgbe_phy_switch_bp_2500_mode(pdata);
2203 case XGBE_PORT_MODE_1000BASE_T:
2204 case XGBE_PORT_MODE_NBASE_T:
2205 case XGBE_PORT_MODE_10GBASE_T:
2206 return xgbe_phy_switch_baset_mode(pdata);
2207 case XGBE_PORT_MODE_1000BASE_X:
2208 case XGBE_PORT_MODE_10GBASE_R:
2209 case XGBE_PORT_MODE_SFP:
2210 /* No switching, so just return current mode */
2211 return xgbe_phy_cur_mode(pdata);
2213 return XGBE_MODE_UNKNOWN;
2217 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2224 return XGBE_MODE_KR;
2226 return XGBE_MODE_UNKNOWN;
2230 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2235 return XGBE_MODE_SGMII_100;
2237 return XGBE_MODE_SGMII_1000;
2239 return XGBE_MODE_KX_2500;
2241 return XGBE_MODE_KR;
2243 return XGBE_MODE_UNKNOWN;
2247 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2252 return XGBE_MODE_SGMII_100;
2254 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2255 return XGBE_MODE_SGMII_1000;
2260 return XGBE_MODE_SFI;
2262 return XGBE_MODE_UNKNOWN;
2266 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2270 return XGBE_MODE_KX_2500;
2272 return XGBE_MODE_UNKNOWN;
2276 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2280 return XGBE_MODE_KX_1000;
2282 return XGBE_MODE_KR;
2284 return XGBE_MODE_UNKNOWN;
2288 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2291 struct xgbe_phy_data *phy_data = pdata->phy_data;
2293 switch (phy_data->port_mode) {
2294 case XGBE_PORT_MODE_BACKPLANE:
2295 return xgbe_phy_get_bp_mode(speed);
2296 case XGBE_PORT_MODE_BACKPLANE_2500:
2297 return xgbe_phy_get_bp_2500_mode(speed);
2298 case XGBE_PORT_MODE_1000BASE_T:
2299 case XGBE_PORT_MODE_NBASE_T:
2300 case XGBE_PORT_MODE_10GBASE_T:
2301 return xgbe_phy_get_baset_mode(phy_data, speed);
2302 case XGBE_PORT_MODE_1000BASE_X:
2303 case XGBE_PORT_MODE_10GBASE_R:
2304 return xgbe_phy_get_basex_mode(phy_data, speed);
2305 case XGBE_PORT_MODE_SFP:
2306 return xgbe_phy_get_sfp_mode(phy_data, speed);
2308 return XGBE_MODE_UNKNOWN;
2312 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2315 case XGBE_MODE_KX_1000:
2316 xgbe_phy_kx_1000_mode(pdata);
2318 case XGBE_MODE_KX_2500:
2319 xgbe_phy_kx_2500_mode(pdata);
2322 xgbe_phy_kr_mode(pdata);
2324 case XGBE_MODE_SGMII_100:
2325 xgbe_phy_sgmii_100_mode(pdata);
2327 case XGBE_MODE_SGMII_1000:
2328 xgbe_phy_sgmii_1000_mode(pdata);
2331 xgbe_phy_x_mode(pdata);
2334 xgbe_phy_sfi_mode(pdata);
2341 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2342 enum xgbe_mode mode, bool advert)
2344 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2347 enum xgbe_mode cur_mode;
2349 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2350 if (cur_mode == mode)
2357 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2358 enum xgbe_mode mode)
2360 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2364 return xgbe_phy_check_mode(pdata, mode,
2365 XGBE_ADV(lks, 1000baseX_Full));
2367 return xgbe_phy_check_mode(pdata, mode,
2368 XGBE_ADV(lks, 10000baseKR_Full));
2374 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2375 enum xgbe_mode mode)
2377 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2380 case XGBE_MODE_SGMII_100:
2381 return xgbe_phy_check_mode(pdata, mode,
2382 XGBE_ADV(lks, 100baseT_Full));
2383 case XGBE_MODE_SGMII_1000:
2384 return xgbe_phy_check_mode(pdata, mode,
2385 XGBE_ADV(lks, 1000baseT_Full));
2386 case XGBE_MODE_KX_2500:
2387 return xgbe_phy_check_mode(pdata, mode,
2388 XGBE_ADV(lks, 2500baseT_Full));
2390 return xgbe_phy_check_mode(pdata, mode,
2391 XGBE_ADV(lks, 10000baseT_Full));
2397 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2398 enum xgbe_mode mode)
2400 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2401 struct xgbe_phy_data *phy_data = pdata->phy_data;
2405 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2407 return xgbe_phy_check_mode(pdata, mode,
2408 XGBE_ADV(lks, 1000baseX_Full));
2409 case XGBE_MODE_SGMII_100:
2410 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2412 return xgbe_phy_check_mode(pdata, mode,
2413 XGBE_ADV(lks, 100baseT_Full));
2414 case XGBE_MODE_SGMII_1000:
2415 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2417 return xgbe_phy_check_mode(pdata, mode,
2418 XGBE_ADV(lks, 1000baseT_Full));
2420 if (phy_data->sfp_mod_absent)
2422 return xgbe_phy_check_mode(pdata, mode,
2423 XGBE_ADV(lks, 10000baseSR_Full) ||
2424 XGBE_ADV(lks, 10000baseLR_Full) ||
2425 XGBE_ADV(lks, 10000baseLRM_Full) ||
2426 XGBE_ADV(lks, 10000baseER_Full) ||
2427 XGBE_ADV(lks, 10000baseCR_Full));
2433 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2434 enum xgbe_mode mode)
2436 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2439 case XGBE_MODE_KX_2500:
2440 return xgbe_phy_check_mode(pdata, mode,
2441 XGBE_ADV(lks, 2500baseX_Full));
2447 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2448 enum xgbe_mode mode)
2450 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2453 case XGBE_MODE_KX_1000:
2454 return xgbe_phy_check_mode(pdata, mode,
2455 XGBE_ADV(lks, 1000baseKX_Full));
2457 return xgbe_phy_check_mode(pdata, mode,
2458 XGBE_ADV(lks, 10000baseKR_Full));
2464 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2466 struct xgbe_phy_data *phy_data = pdata->phy_data;
2468 switch (phy_data->port_mode) {
2469 case XGBE_PORT_MODE_BACKPLANE:
2470 return xgbe_phy_use_bp_mode(pdata, mode);
2471 case XGBE_PORT_MODE_BACKPLANE_2500:
2472 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2473 case XGBE_PORT_MODE_1000BASE_T:
2474 case XGBE_PORT_MODE_NBASE_T:
2475 case XGBE_PORT_MODE_10GBASE_T:
2476 return xgbe_phy_use_baset_mode(pdata, mode);
2477 case XGBE_PORT_MODE_1000BASE_X:
2478 case XGBE_PORT_MODE_10GBASE_R:
2479 return xgbe_phy_use_basex_mode(pdata, mode);
2480 case XGBE_PORT_MODE_SFP:
2481 return xgbe_phy_use_sfp_mode(pdata, mode);
2487 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2492 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2494 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2500 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2508 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2510 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2516 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2521 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2523 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2524 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2526 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2532 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2542 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2553 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2555 struct xgbe_phy_data *phy_data = pdata->phy_data;
2557 switch (phy_data->port_mode) {
2558 case XGBE_PORT_MODE_BACKPLANE:
2559 return xgbe_phy_valid_speed_bp_mode(speed);
2560 case XGBE_PORT_MODE_BACKPLANE_2500:
2561 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2562 case XGBE_PORT_MODE_1000BASE_T:
2563 case XGBE_PORT_MODE_NBASE_T:
2564 case XGBE_PORT_MODE_10GBASE_T:
2565 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2566 case XGBE_PORT_MODE_1000BASE_X:
2567 case XGBE_PORT_MODE_10GBASE_R:
2568 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2569 case XGBE_PORT_MODE_SFP:
2570 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2576 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2578 struct xgbe_phy_data *phy_data = pdata->phy_data;
2584 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2585 /* Check SFP signals */
2586 xgbe_phy_sfp_detect(pdata);
2588 if (phy_data->sfp_changed) {
2593 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2597 if (phy_data->phydev) {
2598 /* Check external PHY */
2599 ret = phy_read_status(phy_data->phydev);
2603 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2604 !phy_aneg_done(phy_data->phydev))
2607 if (!phy_data->phydev->link)
2611 /* Link status is latched low, so read once to clear
2612 * and then read again to get current state
2614 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2615 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2616 if (reg & MDIO_STAT1_LSTATUS)
2619 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2620 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2621 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2622 netif_carrier_off(pdata->netdev);
2627 /* No link, attempt a receiver reset cycle */
2628 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2629 phy_data->rrc_count = 0;
2630 xgbe_phy_rrc(pdata);
2636 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2638 struct xgbe_phy_data *phy_data = pdata->phy_data;
2640 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2641 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2644 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2647 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2649 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2651 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2653 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2656 if (netif_msg_probe(pdata)) {
2657 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2658 phy_data->sfp_gpio_address);
2659 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2660 phy_data->sfp_gpio_mask);
2661 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2662 phy_data->sfp_gpio_rx_los);
2663 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2664 phy_data->sfp_gpio_tx_fault);
2665 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2666 phy_data->sfp_gpio_mod_absent);
2667 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2668 phy_data->sfp_gpio_rate_select);
2672 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2674 struct xgbe_phy_data *phy_data = pdata->phy_data;
2675 unsigned int mux_addr_hi, mux_addr_lo;
2677 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2678 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2679 if (mux_addr_lo == XGBE_SFP_DIRECT)
2682 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2683 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2684 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2687 if (netif_msg_probe(pdata)) {
2688 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2689 phy_data->sfp_mux_address);
2690 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2691 phy_data->sfp_mux_channel);
2695 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2697 xgbe_phy_sfp_comm_setup(pdata);
2698 xgbe_phy_sfp_gpio_setup(pdata);
2701 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2703 struct xgbe_phy_data *phy_data = pdata->phy_data;
2706 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2710 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2715 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2717 struct xgbe_phy_data *phy_data = pdata->phy_data;
2718 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2721 /* Read the output port registers */
2723 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2724 &gpio_reg, sizeof(gpio_reg),
2725 gpio_ports, sizeof(gpio_ports));
2729 /* Prepare to write the GPIO data */
2731 gpio_data[1] = gpio_ports[0];
2732 gpio_data[2] = gpio_ports[1];
2734 /* Set the GPIO pin */
2735 if (phy_data->mdio_reset_gpio < 8)
2736 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2738 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2740 /* Write the output port registers */
2741 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2742 gpio_data, sizeof(gpio_data));
2746 /* Clear the GPIO pin */
2747 if (phy_data->mdio_reset_gpio < 8)
2748 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2750 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2752 /* Write the output port registers */
2753 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2754 gpio_data, sizeof(gpio_data));
2759 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2761 struct xgbe_phy_data *phy_data = pdata->phy_data;
2764 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2767 ret = xgbe_phy_get_comm_ownership(pdata);
2771 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2772 ret = xgbe_phy_i2c_mdio_reset(pdata);
2773 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2774 ret = xgbe_phy_int_mdio_reset(pdata);
2776 xgbe_phy_put_comm_ownership(pdata);
2781 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2783 if (!phy_data->redrv)
2786 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2789 switch (phy_data->redrv_model) {
2790 case XGBE_PHY_REDRV_MODEL_4223:
2791 if (phy_data->redrv_lane > 3)
2794 case XGBE_PHY_REDRV_MODEL_4227:
2795 if (phy_data->redrv_lane > 1)
2805 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2807 struct xgbe_phy_data *phy_data = pdata->phy_data;
2809 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2812 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2813 switch (phy_data->mdio_reset) {
2814 case XGBE_MDIO_RESET_NONE:
2815 case XGBE_MDIO_RESET_I2C_GPIO:
2816 case XGBE_MDIO_RESET_INT_GPIO:
2819 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2820 phy_data->mdio_reset);
2824 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2825 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2826 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2827 MDIO_RESET_I2C_ADDR);
2828 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2829 MDIO_RESET_I2C_GPIO);
2830 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2831 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2832 MDIO_RESET_INT_GPIO);
2838 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2840 struct xgbe_phy_data *phy_data = pdata->phy_data;
2842 switch (phy_data->port_mode) {
2843 case XGBE_PORT_MODE_BACKPLANE:
2844 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2845 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2848 case XGBE_PORT_MODE_BACKPLANE_2500:
2849 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2852 case XGBE_PORT_MODE_1000BASE_T:
2853 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2854 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2857 case XGBE_PORT_MODE_1000BASE_X:
2858 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2861 case XGBE_PORT_MODE_NBASE_T:
2862 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2863 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2864 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2867 case XGBE_PORT_MODE_10GBASE_T:
2868 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2869 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2870 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2873 case XGBE_PORT_MODE_10GBASE_R:
2874 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2877 case XGBE_PORT_MODE_SFP:
2878 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2879 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2880 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2890 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2892 struct xgbe_phy_data *phy_data = pdata->phy_data;
2894 switch (phy_data->port_mode) {
2895 case XGBE_PORT_MODE_BACKPLANE:
2896 case XGBE_PORT_MODE_BACKPLANE_2500:
2897 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2900 case XGBE_PORT_MODE_1000BASE_T:
2901 case XGBE_PORT_MODE_1000BASE_X:
2902 case XGBE_PORT_MODE_NBASE_T:
2903 case XGBE_PORT_MODE_10GBASE_T:
2904 case XGBE_PORT_MODE_10GBASE_R:
2905 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2908 case XGBE_PORT_MODE_SFP:
2909 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2919 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2921 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2923 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2929 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2931 struct xgbe_phy_data *phy_data = pdata->phy_data;
2933 if (!pdata->debugfs_an_cdr_workaround)
2936 if (!phy_data->phy_cdr_notrack)
2939 usleep_range(phy_data->phy_cdr_delay,
2940 phy_data->phy_cdr_delay + 500);
2942 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2943 XGBE_PMA_CDR_TRACK_EN_MASK,
2944 XGBE_PMA_CDR_TRACK_EN_ON);
2946 phy_data->phy_cdr_notrack = 0;
2949 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2951 struct xgbe_phy_data *phy_data = pdata->phy_data;
2953 if (!pdata->debugfs_an_cdr_workaround)
2956 if (phy_data->phy_cdr_notrack)
2959 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2960 XGBE_PMA_CDR_TRACK_EN_MASK,
2961 XGBE_PMA_CDR_TRACK_EN_OFF);
2963 xgbe_phy_rrc(pdata);
2965 phy_data->phy_cdr_notrack = 1;
2968 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2970 if (!pdata->debugfs_an_cdr_track_early)
2971 xgbe_phy_cdr_track(pdata);
2974 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2976 if (pdata->debugfs_an_cdr_track_early)
2977 xgbe_phy_cdr_track(pdata);
2980 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2982 struct xgbe_phy_data *phy_data = pdata->phy_data;
2984 switch (pdata->an_mode) {
2985 case XGBE_AN_MODE_CL73:
2986 case XGBE_AN_MODE_CL73_REDRV:
2987 if (phy_data->cur_mode != XGBE_MODE_KR)
2990 xgbe_phy_cdr_track(pdata);
2992 switch (pdata->an_result) {
2994 case XGBE_AN_COMPLETE:
2997 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2998 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3000 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3009 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3011 struct xgbe_phy_data *phy_data = pdata->phy_data;
3013 switch (pdata->an_mode) {
3014 case XGBE_AN_MODE_CL73:
3015 case XGBE_AN_MODE_CL73_REDRV:
3016 if (phy_data->cur_mode != XGBE_MODE_KR)
3019 xgbe_phy_cdr_notrack(pdata);
3026 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3028 struct xgbe_phy_data *phy_data = pdata->phy_data;
3030 /* If we have an external PHY, free it */
3031 xgbe_phy_free_phy_device(pdata);
3033 /* Reset SFP data */
3034 xgbe_phy_sfp_reset(phy_data);
3035 xgbe_phy_sfp_mod_absent(pdata);
3037 /* Reset CDR support */
3038 xgbe_phy_cdr_track(pdata);
3040 /* Power off the PHY */
3041 xgbe_phy_power_off(pdata);
3043 /* Stop the I2C controller */
3044 pdata->i2c_if.i2c_stop(pdata);
3047 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3049 struct xgbe_phy_data *phy_data = pdata->phy_data;
3052 /* Start the I2C controller */
3053 ret = pdata->i2c_if.i2c_start(pdata);
3057 /* Set the proper MDIO mode for the re-driver */
3058 if (phy_data->redrv && !phy_data->redrv_if) {
3059 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3060 XGBE_MDIO_MODE_CL22);
3062 netdev_err(pdata->netdev,
3063 "redriver mdio port not compatible (%u)\n",
3064 phy_data->redrv_addr);
3069 /* Start in highest supported mode */
3070 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3072 /* Reset CDR support */
3073 xgbe_phy_cdr_track(pdata);
3075 /* After starting the I2C controller, we can check for an SFP */
3076 switch (phy_data->port_mode) {
3077 case XGBE_PORT_MODE_SFP:
3078 xgbe_phy_sfp_detect(pdata);
3084 /* If we have an external PHY, start it */
3085 ret = xgbe_phy_find_phy_device(pdata);
3092 pdata->i2c_if.i2c_stop(pdata);
3097 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3099 struct xgbe_phy_data *phy_data = pdata->phy_data;
3100 enum xgbe_mode cur_mode;
3103 /* Reset by power cycling the PHY */
3104 cur_mode = phy_data->cur_mode;
3105 xgbe_phy_power_off(pdata);
3106 xgbe_phy_set_mode(pdata, cur_mode);
3108 if (!phy_data->phydev)
3111 /* Reset the external PHY */
3112 ret = xgbe_phy_mdio_reset(pdata);
3116 return phy_init_hw(phy_data->phydev);
3119 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3121 struct xgbe_phy_data *phy_data = pdata->phy_data;
3123 /* Unregister for driving external PHYs */
3124 mdiobus_unregister(phy_data->mii);
3127 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3129 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3130 struct xgbe_phy_data *phy_data;
3131 struct mii_bus *mii;
3134 /* Check if enabled */
3135 if (!xgbe_phy_port_enabled(pdata)) {
3136 dev_info(pdata->dev, "device is not enabled\n");
3140 /* Initialize the I2C controller */
3141 ret = pdata->i2c_if.i2c_init(pdata);
3145 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3148 pdata->phy_data = phy_data;
3150 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3151 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3152 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3153 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3154 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3155 if (netif_msg_probe(pdata)) {
3156 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3157 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3158 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3159 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3160 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3163 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3164 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3165 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3166 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3167 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3168 if (phy_data->redrv && netif_msg_probe(pdata)) {
3169 dev_dbg(pdata->dev, "redrv present\n");
3170 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3171 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3172 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3173 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3176 /* Validate the connection requested */
3177 if (xgbe_phy_conn_type_mismatch(pdata)) {
3178 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3179 phy_data->port_mode, phy_data->conn_type);
3183 /* Validate the mode requested */
3184 if (xgbe_phy_port_mode_mismatch(pdata)) {
3185 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3186 phy_data->port_mode, phy_data->port_speeds);
3190 /* Check for and validate MDIO reset support */
3191 ret = xgbe_phy_mdio_reset_setup(pdata);
3195 /* Validate the re-driver information */
3196 if (xgbe_phy_redrv_error(phy_data)) {
3197 dev_err(pdata->dev, "phy re-driver settings error\n");
3200 pdata->kr_redrv = phy_data->redrv;
3202 /* Indicate current mode is unknown */
3203 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3205 /* Initialize supported features */
3208 switch (phy_data->port_mode) {
3209 /* Backplane support */
3210 case XGBE_PORT_MODE_BACKPLANE:
3211 XGBE_SET_SUP(lks, Autoneg);
3212 XGBE_SET_SUP(lks, Pause);
3213 XGBE_SET_SUP(lks, Asym_Pause);
3214 XGBE_SET_SUP(lks, Backplane);
3215 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3216 XGBE_SET_SUP(lks, 1000baseKX_Full);
3217 phy_data->start_mode = XGBE_MODE_KX_1000;
3219 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3220 XGBE_SET_SUP(lks, 10000baseKR_Full);
3221 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3222 XGBE_SET_SUP(lks, 10000baseR_FEC);
3223 phy_data->start_mode = XGBE_MODE_KR;
3226 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3228 case XGBE_PORT_MODE_BACKPLANE_2500:
3229 XGBE_SET_SUP(lks, Pause);
3230 XGBE_SET_SUP(lks, Asym_Pause);
3231 XGBE_SET_SUP(lks, Backplane);
3232 XGBE_SET_SUP(lks, 2500baseX_Full);
3233 phy_data->start_mode = XGBE_MODE_KX_2500;
3235 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3238 /* MDIO 1GBase-T support */
3239 case XGBE_PORT_MODE_1000BASE_T:
3240 XGBE_SET_SUP(lks, Autoneg);
3241 XGBE_SET_SUP(lks, Pause);
3242 XGBE_SET_SUP(lks, Asym_Pause);
3243 XGBE_SET_SUP(lks, TP);
3244 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3245 XGBE_SET_SUP(lks, 100baseT_Full);
3246 phy_data->start_mode = XGBE_MODE_SGMII_100;
3248 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3249 XGBE_SET_SUP(lks, 1000baseT_Full);
3250 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3253 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3256 /* MDIO Base-X support */
3257 case XGBE_PORT_MODE_1000BASE_X:
3258 XGBE_SET_SUP(lks, Autoneg);
3259 XGBE_SET_SUP(lks, Pause);
3260 XGBE_SET_SUP(lks, Asym_Pause);
3261 XGBE_SET_SUP(lks, FIBRE);
3262 XGBE_SET_SUP(lks, 1000baseX_Full);
3263 phy_data->start_mode = XGBE_MODE_X;
3265 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3268 /* MDIO NBase-T support */
3269 case XGBE_PORT_MODE_NBASE_T:
3270 XGBE_SET_SUP(lks, Autoneg);
3271 XGBE_SET_SUP(lks, Pause);
3272 XGBE_SET_SUP(lks, Asym_Pause);
3273 XGBE_SET_SUP(lks, TP);
3274 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3275 XGBE_SET_SUP(lks, 100baseT_Full);
3276 phy_data->start_mode = XGBE_MODE_SGMII_100;
3278 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3279 XGBE_SET_SUP(lks, 1000baseT_Full);
3280 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3282 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3283 XGBE_SET_SUP(lks, 2500baseT_Full);
3284 phy_data->start_mode = XGBE_MODE_KX_2500;
3287 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3290 /* 10GBase-T support */
3291 case XGBE_PORT_MODE_10GBASE_T:
3292 XGBE_SET_SUP(lks, Autoneg);
3293 XGBE_SET_SUP(lks, Pause);
3294 XGBE_SET_SUP(lks, Asym_Pause);
3295 XGBE_SET_SUP(lks, TP);
3296 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3297 XGBE_SET_SUP(lks, 100baseT_Full);
3298 phy_data->start_mode = XGBE_MODE_SGMII_100;
3300 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3301 XGBE_SET_SUP(lks, 1000baseT_Full);
3302 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3304 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3305 XGBE_SET_SUP(lks, 10000baseT_Full);
3306 phy_data->start_mode = XGBE_MODE_KR;
3309 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3312 /* 10GBase-R support */
3313 case XGBE_PORT_MODE_10GBASE_R:
3314 XGBE_SET_SUP(lks, Autoneg);
3315 XGBE_SET_SUP(lks, Pause);
3316 XGBE_SET_SUP(lks, Asym_Pause);
3317 XGBE_SET_SUP(lks, FIBRE);
3318 XGBE_SET_SUP(lks, 10000baseSR_Full);
3319 XGBE_SET_SUP(lks, 10000baseLR_Full);
3320 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3321 XGBE_SET_SUP(lks, 10000baseER_Full);
3322 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3323 XGBE_SET_SUP(lks, 10000baseR_FEC);
3324 phy_data->start_mode = XGBE_MODE_SFI;
3326 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3330 case XGBE_PORT_MODE_SFP:
3331 XGBE_SET_SUP(lks, Autoneg);
3332 XGBE_SET_SUP(lks, Pause);
3333 XGBE_SET_SUP(lks, Asym_Pause);
3334 XGBE_SET_SUP(lks, TP);
3335 XGBE_SET_SUP(lks, FIBRE);
3336 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3337 phy_data->start_mode = XGBE_MODE_SGMII_100;
3338 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3339 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3340 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3341 phy_data->start_mode = XGBE_MODE_SFI;
3343 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3345 xgbe_phy_sfp_setup(pdata);
3351 if (netif_msg_probe(pdata))
3352 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3353 __ETHTOOL_LINK_MODE_MASK_NBITS,
3354 lks->link_modes.supported);
3356 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3357 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3358 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3359 phy_data->phydev_mode);
3362 "mdio port/clause not compatible (%d/%u)\n",
3363 phy_data->mdio_addr, phy_data->phydev_mode);
3368 if (phy_data->redrv && !phy_data->redrv_if) {
3369 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3370 XGBE_MDIO_MODE_CL22);
3373 "redriver mdio port not compatible (%u)\n",
3374 phy_data->redrv_addr);
3379 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3381 /* Register for driving external PHYs */
3382 mii = devm_mdiobus_alloc(pdata->dev);
3384 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3389 mii->name = "amd-xgbe-mii";
3390 mii->read = xgbe_phy_mii_read;
3391 mii->write = xgbe_phy_mii_write;
3392 mii->parent = pdata->dev;
3394 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3395 ret = mdiobus_register(mii);
3397 dev_err(pdata->dev, "mdiobus_register failed\n");
3400 phy_data->mii = mii;
3405 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3407 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3409 phy_impl->init = xgbe_phy_init;
3410 phy_impl->exit = xgbe_phy_exit;
3412 phy_impl->reset = xgbe_phy_reset;
3413 phy_impl->start = xgbe_phy_start;
3414 phy_impl->stop = xgbe_phy_stop;
3416 phy_impl->link_status = xgbe_phy_link_status;
3418 phy_impl->valid_speed = xgbe_phy_valid_speed;
3420 phy_impl->use_mode = xgbe_phy_use_mode;
3421 phy_impl->set_mode = xgbe_phy_set_mode;
3422 phy_impl->get_mode = xgbe_phy_get_mode;
3423 phy_impl->switch_mode = xgbe_phy_switch_mode;
3424 phy_impl->cur_mode = xgbe_phy_cur_mode;
3426 phy_impl->an_mode = xgbe_phy_an_mode;
3428 phy_impl->an_config = xgbe_phy_an_config;
3430 phy_impl->an_advertising = xgbe_phy_an_advertising;
3432 phy_impl->an_outcome = xgbe_phy_an_outcome;
3434 phy_impl->an_pre = xgbe_phy_an_pre;
3435 phy_impl->an_post = xgbe_phy_an_post;
3437 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3438 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3440 phy_impl->module_info = xgbe_phy_module_info;
3441 phy_impl->module_eeprom = xgbe_phy_module_eeprom;