2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
124 #include "xgbe-common.h"
126 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
131 #define XGBE_MUTEX_RELEASE 0x80000000
133 #define XGBE_SFP_DIRECT 7
135 /* I2C target addresses */
136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
138 #define XGBE_SFP_PHY_ADDRESS 0x56
139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
141 /* SFP sideband signal indicators */
142 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
145 #define XGBE_GPIO_NO_RX_LOS BIT(3)
147 /* Rate-change complete wait/retry count */
148 #define XGBE_RATECHANGE_COUNT 500
150 /* CDR delay values for KR support (in usec) */
151 #define XGBE_CDR_DELAY_INIT 10000
152 #define XGBE_CDR_DELAY_INC 10000
153 #define XGBE_CDR_DELAY_MAX 100000
155 /* RRC frequency during link status check */
156 #define XGBE_RRC_FREQUENCY 10
158 enum xgbe_port_mode {
159 XGBE_PORT_MODE_RSVD = 0,
160 XGBE_PORT_MODE_BACKPLANE,
161 XGBE_PORT_MODE_BACKPLANE_2500,
162 XGBE_PORT_MODE_1000BASE_T,
163 XGBE_PORT_MODE_1000BASE_X,
164 XGBE_PORT_MODE_NBASE_T,
165 XGBE_PORT_MODE_10GBASE_T,
166 XGBE_PORT_MODE_10GBASE_R,
171 enum xgbe_conn_type {
172 XGBE_CONN_TYPE_NONE = 0,
175 XGBE_CONN_TYPE_RSVD1,
176 XGBE_CONN_TYPE_BACKPLANE,
180 /* SFP/SFP+ related definitions */
182 XGBE_SFP_COMM_DIRECT = 0,
183 XGBE_SFP_COMM_PCA9545,
186 enum xgbe_sfp_cable {
187 XGBE_SFP_CABLE_UNKNOWN = 0,
188 XGBE_SFP_CABLE_ACTIVE,
189 XGBE_SFP_CABLE_PASSIVE,
193 XGBE_SFP_BASE_UNKNOWN = 0,
194 XGBE_SFP_BASE_1000_T,
195 XGBE_SFP_BASE_1000_SX,
196 XGBE_SFP_BASE_1000_LX,
197 XGBE_SFP_BASE_1000_CX,
198 XGBE_SFP_BASE_10000_SR,
199 XGBE_SFP_BASE_10000_LR,
200 XGBE_SFP_BASE_10000_LRM,
201 XGBE_SFP_BASE_10000_ER,
202 XGBE_SFP_BASE_10000_CR,
205 enum xgbe_sfp_speed {
206 XGBE_SFP_SPEED_UNKNOWN = 0,
207 XGBE_SFP_SPEED_100_1000,
209 XGBE_SFP_SPEED_10000,
212 /* SFP Serial ID Base ID values relative to an offset of 0 */
213 #define XGBE_SFP_BASE_ID 0
214 #define XGBE_SFP_ID_SFP 0x03
216 #define XGBE_SFP_BASE_EXT_ID 1
217 #define XGBE_SFP_EXT_ID_SFP 0x04
219 #define XGBE_SFP_BASE_10GBE_CC 3
220 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
221 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
222 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
223 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
225 #define XGBE_SFP_BASE_1GBE_CC 6
226 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
227 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
228 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
229 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
231 #define XGBE_SFP_BASE_CABLE 8
232 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
233 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
235 #define XGBE_SFP_BASE_BR 12
236 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
237 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
239 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
241 #define XGBE_SFP_BASE_VENDOR_NAME 20
242 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
243 #define XGBE_SFP_BASE_VENDOR_PN 40
244 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
245 #define XGBE_SFP_BASE_VENDOR_REV 56
246 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
248 #define XGBE_SFP_BASE_CC 63
250 /* SFP Serial ID Extended ID values relative to an offset of 64 */
251 #define XGBE_SFP_BASE_VENDOR_SN 4
252 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
254 #define XGBE_SFP_EXTD_OPT1 1
255 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
256 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
258 #define XGBE_SFP_EXTD_DIAG 28
259 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
261 #define XGBE_SFP_EXTD_SFF_8472 30
263 #define XGBE_SFP_EXTD_CC 31
265 struct xgbe_sfp_eeprom {
271 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
272 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
274 #define XGBE_MOLEX_VENDOR "Molex Inc. "
276 struct xgbe_sfp_ascii {
278 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
279 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
280 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
281 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
285 /* MDIO PHY reset types */
286 enum xgbe_mdio_reset {
287 XGBE_MDIO_RESET_NONE = 0,
288 XGBE_MDIO_RESET_I2C_GPIO,
289 XGBE_MDIO_RESET_INT_GPIO,
293 /* Re-driver related definitions */
294 enum xgbe_phy_redrv_if {
295 XGBE_PHY_REDRV_IF_MDIO = 0,
296 XGBE_PHY_REDRV_IF_I2C,
297 XGBE_PHY_REDRV_IF_MAX,
300 enum xgbe_phy_redrv_model {
301 XGBE_PHY_REDRV_MODEL_4223 = 0,
302 XGBE_PHY_REDRV_MODEL_4227,
303 XGBE_PHY_REDRV_MODEL_MAX,
306 enum xgbe_phy_redrv_mode {
307 XGBE_PHY_REDRV_MODE_CX = 5,
308 XGBE_PHY_REDRV_MODE_SR = 9,
311 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
313 /* PHY related configuration information */
314 struct xgbe_phy_data {
315 enum xgbe_port_mode port_mode;
317 unsigned int port_id;
319 unsigned int port_speeds;
321 enum xgbe_conn_type conn_type;
323 enum xgbe_mode cur_mode;
324 enum xgbe_mode start_mode;
326 unsigned int rrc_count;
328 unsigned int mdio_addr;
330 unsigned int comm_owned;
333 enum xgbe_sfp_comm sfp_comm;
334 unsigned int sfp_mux_address;
335 unsigned int sfp_mux_channel;
337 unsigned int sfp_gpio_address;
338 unsigned int sfp_gpio_mask;
339 unsigned int sfp_gpio_inputs;
340 unsigned int sfp_gpio_rx_los;
341 unsigned int sfp_gpio_tx_fault;
342 unsigned int sfp_gpio_mod_absent;
343 unsigned int sfp_gpio_rate_select;
345 unsigned int sfp_rx_los;
346 unsigned int sfp_tx_fault;
347 unsigned int sfp_mod_absent;
348 unsigned int sfp_diags;
349 unsigned int sfp_changed;
350 unsigned int sfp_phy_avail;
351 unsigned int sfp_cable_len;
352 enum xgbe_sfp_base sfp_base;
353 enum xgbe_sfp_cable sfp_cable;
354 enum xgbe_sfp_speed sfp_speed;
355 struct xgbe_sfp_eeprom sfp_eeprom;
357 /* External PHY support */
358 enum xgbe_mdio_mode phydev_mode;
360 struct phy_device *phydev;
361 enum xgbe_mdio_reset mdio_reset;
362 unsigned int mdio_reset_addr;
363 unsigned int mdio_reset_gpio;
365 /* Re-driver support */
367 unsigned int redrv_if;
368 unsigned int redrv_addr;
369 unsigned int redrv_lane;
370 unsigned int redrv_model;
373 unsigned int phy_cdr_notrack;
374 unsigned int phy_cdr_delay;
377 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
378 static DEFINE_MUTEX(xgbe_phy_comm_lock);
380 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
382 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
383 struct xgbe_i2c_op *i2c_op)
385 struct xgbe_phy_data *phy_data = pdata->phy_data;
387 /* Be sure we own the bus */
388 if (WARN_ON(!phy_data->comm_owned))
391 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
394 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
397 struct xgbe_phy_data *phy_data = pdata->phy_data;
398 struct xgbe_i2c_op i2c_op;
400 u8 redrv_data[5], csum;
401 unsigned int i, retry;
404 /* High byte of register contains read/write indicator */
405 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
406 redrv_data[1] = reg & 0xff;
407 redrv_val = (__be16 *)&redrv_data[2];
408 *redrv_val = cpu_to_be16(val);
410 /* Calculate 1 byte checksum */
412 for (i = 0; i < 4; i++) {
413 csum += redrv_data[i];
414 if (redrv_data[i] > csum)
417 redrv_data[4] = ~csum;
421 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
422 i2c_op.target = phy_data->redrv_addr;
423 i2c_op.len = sizeof(redrv_data);
424 i2c_op.buf = redrv_data;
425 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
427 if ((ret == -EAGAIN) && retry--)
435 i2c_op.cmd = XGBE_I2C_CMD_READ;
436 i2c_op.target = phy_data->redrv_addr;
438 i2c_op.buf = redrv_data;
439 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
441 if ((ret == -EAGAIN) && retry--)
447 if (redrv_data[0] != 0xff) {
448 netif_dbg(pdata, drv, pdata->netdev,
449 "Redriver write checksum error\n");
456 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
457 void *val, unsigned int val_len)
459 struct xgbe_i2c_op i2c_op;
464 /* Write the specfied register */
465 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
466 i2c_op.target = target;
467 i2c_op.len = val_len;
469 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
470 if ((ret == -EAGAIN) && retry--)
476 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
477 void *reg, unsigned int reg_len,
478 void *val, unsigned int val_len)
480 struct xgbe_i2c_op i2c_op;
485 /* Set the specified register to read */
486 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
487 i2c_op.target = target;
488 i2c_op.len = reg_len;
490 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
492 if ((ret == -EAGAIN) && retry--)
500 /* Read the specfied register */
501 i2c_op.cmd = XGBE_I2C_CMD_READ;
502 i2c_op.target = target;
503 i2c_op.len = val_len;
505 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
506 if ((ret == -EAGAIN) && retry--)
512 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
514 struct xgbe_phy_data *phy_data = pdata->phy_data;
515 struct xgbe_i2c_op i2c_op;
518 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
521 /* Select no mux channels */
523 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
524 i2c_op.target = phy_data->sfp_mux_address;
525 i2c_op.len = sizeof(mux_channel);
526 i2c_op.buf = &mux_channel;
528 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
531 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
533 struct xgbe_phy_data *phy_data = pdata->phy_data;
534 struct xgbe_i2c_op i2c_op;
537 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
540 /* Select desired mux channel */
541 mux_channel = 1 << phy_data->sfp_mux_channel;
542 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
543 i2c_op.target = phy_data->sfp_mux_address;
544 i2c_op.len = sizeof(mux_channel);
545 i2c_op.buf = &mux_channel;
547 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
550 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
552 struct xgbe_phy_data *phy_data = pdata->phy_data;
554 phy_data->comm_owned = 0;
556 mutex_unlock(&xgbe_phy_comm_lock);
559 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
561 struct xgbe_phy_data *phy_data = pdata->phy_data;
562 unsigned long timeout;
563 unsigned int mutex_id;
565 if (phy_data->comm_owned)
568 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
569 * the driver needs to take the software mutex and then the hardware
570 * mutexes before being able to use the busses.
572 mutex_lock(&xgbe_phy_comm_lock);
574 /* Clear the mutexes */
575 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
576 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
578 /* Mutex formats are the same for I2C and MDIO/GPIO */
580 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
581 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
583 timeout = jiffies + (5 * HZ);
584 while (time_before(jiffies, timeout)) {
585 /* Must be all zeroes in order to obtain the mutex */
586 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
587 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
588 usleep_range(100, 200);
592 /* Obtain the mutex */
593 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
594 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
596 phy_data->comm_owned = 1;
600 mutex_unlock(&xgbe_phy_comm_lock);
602 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
607 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
610 struct xgbe_phy_data *phy_data = pdata->phy_data;
612 if (reg & MII_ADDR_C45) {
613 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
616 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
620 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
623 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
629 ret = xgbe_phy_sfp_get_mux(pdata);
633 mii_data[0] = reg & 0xff;
634 mii_val = (__be16 *)&mii_data[1];
635 *mii_val = cpu_to_be16(val);
637 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
638 mii_data, sizeof(mii_data));
640 xgbe_phy_sfp_put_mux(pdata);
645 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
647 struct xgbe_prv_data *pdata = mii->priv;
648 struct xgbe_phy_data *phy_data = pdata->phy_data;
651 ret = xgbe_phy_get_comm_ownership(pdata);
655 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
656 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
657 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
658 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
662 xgbe_phy_put_comm_ownership(pdata);
667 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
670 struct xgbe_phy_data *phy_data = pdata->phy_data;
672 if (reg & MII_ADDR_C45) {
673 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
676 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
680 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
683 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
689 ret = xgbe_phy_sfp_get_mux(pdata);
694 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
695 &mii_reg, sizeof(mii_reg),
696 &mii_val, sizeof(mii_val));
698 ret = be16_to_cpu(mii_val);
700 xgbe_phy_sfp_put_mux(pdata);
705 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
707 struct xgbe_prv_data *pdata = mii->priv;
708 struct xgbe_phy_data *phy_data = pdata->phy_data;
711 ret = xgbe_phy_get_comm_ownership(pdata);
715 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
716 ret = xgbe_phy_i2c_mii_read(pdata, reg);
717 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
718 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
722 xgbe_phy_put_comm_ownership(pdata);
727 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
729 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
730 struct xgbe_phy_data *phy_data = pdata->phy_data;
732 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
737 if (phy_data->sfp_mod_absent) {
738 pdata->phy.speed = SPEED_UNKNOWN;
739 pdata->phy.duplex = DUPLEX_UNKNOWN;
740 pdata->phy.autoneg = AUTONEG_ENABLE;
741 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
743 XGBE_SET_SUP(lks, Autoneg);
744 XGBE_SET_SUP(lks, Pause);
745 XGBE_SET_SUP(lks, Asym_Pause);
746 XGBE_SET_SUP(lks, TP);
747 XGBE_SET_SUP(lks, FIBRE);
749 XGBE_LM_COPY(lks, advertising, lks, supported);
754 switch (phy_data->sfp_base) {
755 case XGBE_SFP_BASE_1000_T:
756 case XGBE_SFP_BASE_1000_SX:
757 case XGBE_SFP_BASE_1000_LX:
758 case XGBE_SFP_BASE_1000_CX:
759 pdata->phy.speed = SPEED_UNKNOWN;
760 pdata->phy.duplex = DUPLEX_UNKNOWN;
761 pdata->phy.autoneg = AUTONEG_ENABLE;
762 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
763 XGBE_SET_SUP(lks, Autoneg);
764 XGBE_SET_SUP(lks, Pause);
765 XGBE_SET_SUP(lks, Asym_Pause);
766 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
767 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
768 XGBE_SET_SUP(lks, 100baseT_Full);
769 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
770 XGBE_SET_SUP(lks, 1000baseT_Full);
772 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
773 XGBE_SET_SUP(lks, 1000baseX_Full);
776 case XGBE_SFP_BASE_10000_SR:
777 case XGBE_SFP_BASE_10000_LR:
778 case XGBE_SFP_BASE_10000_LRM:
779 case XGBE_SFP_BASE_10000_ER:
780 case XGBE_SFP_BASE_10000_CR:
781 pdata->phy.speed = SPEED_10000;
782 pdata->phy.duplex = DUPLEX_FULL;
783 pdata->phy.autoneg = AUTONEG_DISABLE;
784 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
785 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
786 switch (phy_data->sfp_base) {
787 case XGBE_SFP_BASE_10000_SR:
788 XGBE_SET_SUP(lks, 10000baseSR_Full);
790 case XGBE_SFP_BASE_10000_LR:
791 XGBE_SET_SUP(lks, 10000baseLR_Full);
793 case XGBE_SFP_BASE_10000_LRM:
794 XGBE_SET_SUP(lks, 10000baseLRM_Full);
796 case XGBE_SFP_BASE_10000_ER:
797 XGBE_SET_SUP(lks, 10000baseER_Full);
799 case XGBE_SFP_BASE_10000_CR:
800 XGBE_SET_SUP(lks, 10000baseCR_Full);
808 pdata->phy.speed = SPEED_UNKNOWN;
809 pdata->phy.duplex = DUPLEX_UNKNOWN;
810 pdata->phy.autoneg = AUTONEG_DISABLE;
811 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
815 switch (phy_data->sfp_base) {
816 case XGBE_SFP_BASE_1000_T:
817 case XGBE_SFP_BASE_1000_CX:
818 case XGBE_SFP_BASE_10000_CR:
819 XGBE_SET_SUP(lks, TP);
822 XGBE_SET_SUP(lks, FIBRE);
826 XGBE_LM_COPY(lks, advertising, lks, supported);
829 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
830 enum xgbe_sfp_speed sfp_speed)
834 sfp_base = sfp_eeprom->base;
837 case XGBE_SFP_SPEED_1000:
838 min = XGBE_SFP_BASE_BR_1GBE_MIN;
840 case XGBE_SFP_SPEED_10000:
841 min = XGBE_SFP_BASE_BR_10GBE_MIN;
847 return sfp_base[XGBE_SFP_BASE_BR] >= min;
850 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
852 struct xgbe_phy_data *phy_data = pdata->phy_data;
854 if (phy_data->phydev) {
855 phy_detach(phy_data->phydev);
856 phy_device_remove(phy_data->phydev);
857 phy_device_free(phy_data->phydev);
858 phy_data->phydev = NULL;
862 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
864 struct xgbe_phy_data *phy_data = pdata->phy_data;
865 unsigned int phy_id = phy_data->phydev->phy_id;
867 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
870 /* Enable Base-T AN */
871 phy_write(phy_data->phydev, 0x16, 0x0001);
872 phy_write(phy_data->phydev, 0x00, 0x9140);
873 phy_write(phy_data->phydev, 0x16, 0x0000);
875 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
876 phy_write(phy_data->phydev, 0x1b, 0x9084);
877 phy_write(phy_data->phydev, 0x09, 0x0e00);
878 phy_write(phy_data->phydev, 0x00, 0x8140);
879 phy_write(phy_data->phydev, 0x04, 0x0d01);
880 phy_write(phy_data->phydev, 0x00, 0x9140);
882 phy_data->phydev->supported = PHY_GBIT_FEATURES;
883 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
884 phy_data->phydev->advertising = phy_data->phydev->supported;
886 netif_dbg(pdata, drv, pdata->netdev,
887 "Finisar PHY quirk in place\n");
892 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
894 if (xgbe_phy_finisar_phy_quirks(pdata))
898 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
900 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
901 struct xgbe_phy_data *phy_data = pdata->phy_data;
902 struct phy_device *phydev;
906 /* If we already have a PHY, just return */
907 if (phy_data->phydev)
910 /* Check for the use of an external PHY */
911 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
914 /* For SFP, only use an external PHY if available */
915 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
916 !phy_data->sfp_phy_avail)
919 /* Set the proper MDIO mode for the PHY */
920 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
921 phy_data->phydev_mode);
923 netdev_err(pdata->netdev,
924 "mdio port/clause not compatible (%u/%u)\n",
925 phy_data->mdio_addr, phy_data->phydev_mode);
929 /* Create and connect to the PHY device */
930 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
931 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
932 if (IS_ERR(phydev)) {
933 netdev_err(pdata->netdev, "get_phy_device failed\n");
936 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
939 /*TODO: If c45, add request_module based on one of the MMD ids? */
941 ret = phy_device_register(phydev);
943 netdev_err(pdata->netdev, "phy_device_register failed\n");
944 phy_device_free(phydev);
948 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
949 PHY_INTERFACE_MODE_SGMII);
951 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
952 phy_device_remove(phydev);
953 phy_device_free(phydev);
956 phy_data->phydev = phydev;
958 xgbe_phy_external_phy_quirks(pdata);
960 ethtool_convert_link_mode_to_legacy_u32(&advertising,
961 lks->link_modes.advertising);
962 phydev->advertising &= advertising;
964 phy_start_aneg(phy_data->phydev);
969 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
971 struct xgbe_phy_data *phy_data = pdata->phy_data;
974 if (!phy_data->sfp_changed)
977 phy_data->sfp_phy_avail = 0;
979 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
982 /* Check access to the PHY by reading CTRL1 */
983 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
987 /* Successfully accessed the PHY */
988 phy_data->sfp_phy_avail = 1;
991 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
993 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
995 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
998 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1001 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1007 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1009 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1011 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1014 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1017 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1023 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1025 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1028 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1034 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata)
1036 struct xgbe_phy_data *phy_data = pdata->phy_data;
1037 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1039 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1040 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
1043 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1044 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) {
1045 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1046 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1047 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1048 if (phy_data->sfp_changed)
1049 netif_dbg(pdata, drv, pdata->netdev,
1050 "Bel-Fuse SFP quirk in place\n");
1057 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata)
1059 if (xgbe_phy_belfuse_parse_quirks(pdata))
1065 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1067 struct xgbe_phy_data *phy_data = pdata->phy_data;
1068 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1071 sfp_base = sfp_eeprom->base;
1073 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1076 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1079 /* Update transceiver signals (eeprom extd/options) */
1080 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1081 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1083 if (xgbe_phy_sfp_parse_quirks(pdata))
1086 /* Assume ACTIVE cable unless told it is PASSIVE */
1087 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1088 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1089 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1091 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1094 /* Determine the type of SFP */
1095 if (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE &&
1096 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1097 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1098 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1099 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1100 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1101 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1102 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1103 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1104 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1105 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1106 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1107 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1108 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1109 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1110 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1111 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1112 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1113 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1115 switch (phy_data->sfp_base) {
1116 case XGBE_SFP_BASE_1000_T:
1117 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1119 case XGBE_SFP_BASE_1000_SX:
1120 case XGBE_SFP_BASE_1000_LX:
1121 case XGBE_SFP_BASE_1000_CX:
1122 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1124 case XGBE_SFP_BASE_10000_SR:
1125 case XGBE_SFP_BASE_10000_LR:
1126 case XGBE_SFP_BASE_10000_LRM:
1127 case XGBE_SFP_BASE_10000_ER:
1128 case XGBE_SFP_BASE_10000_CR:
1129 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1136 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1137 struct xgbe_sfp_eeprom *sfp_eeprom)
1139 struct xgbe_sfp_ascii sfp_ascii;
1140 char *sfp_data = (char *)&sfp_ascii;
1142 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1143 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1144 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1145 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1146 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1149 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1150 XGBE_SFP_BASE_VENDOR_PN_LEN);
1151 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1152 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1155 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1156 XGBE_SFP_BASE_VENDOR_REV_LEN);
1157 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1158 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1161 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1162 XGBE_SFP_BASE_VENDOR_SN_LEN);
1163 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1164 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1168 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1172 for (cc = 0; len; buf++, len--)
1175 return (cc == cc_in) ? true : false;
1178 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1180 struct xgbe_phy_data *phy_data = pdata->phy_data;
1181 struct xgbe_sfp_eeprom sfp_eeprom;
1185 ret = xgbe_phy_sfp_get_mux(pdata);
1187 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1188 netdev_name(pdata->netdev));
1192 /* Read the SFP serial ID eeprom */
1194 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1195 &eeprom_addr, sizeof(eeprom_addr),
1196 &sfp_eeprom, sizeof(sfp_eeprom));
1198 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1199 netdev_name(pdata->netdev));
1203 /* Validate the contents read */
1204 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1206 sizeof(sfp_eeprom.base) - 1)) {
1211 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1213 sizeof(sfp_eeprom.extd) - 1)) {
1218 /* Check for an added or changed SFP */
1219 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1220 phy_data->sfp_changed = 1;
1222 if (netif_msg_drv(pdata))
1223 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1225 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1227 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) {
1228 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG];
1230 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
1231 phy_data->sfp_diags = 1;
1234 xgbe_phy_free_phy_device(pdata);
1236 phy_data->sfp_changed = 0;
1240 xgbe_phy_sfp_put_mux(pdata);
1245 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1247 struct xgbe_phy_data *phy_data = pdata->phy_data;
1248 u8 gpio_reg, gpio_ports[2];
1251 /* Read the input port registers */
1253 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1254 &gpio_reg, sizeof(gpio_reg),
1255 gpio_ports, sizeof(gpio_ports));
1257 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1258 netdev_name(pdata->netdev));
1262 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1264 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1267 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1269 struct xgbe_phy_data *phy_data = pdata->phy_data;
1271 xgbe_phy_free_phy_device(pdata);
1273 phy_data->sfp_mod_absent = 1;
1274 phy_data->sfp_phy_avail = 0;
1275 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1278 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1280 phy_data->sfp_rx_los = 0;
1281 phy_data->sfp_tx_fault = 0;
1282 phy_data->sfp_mod_absent = 1;
1283 phy_data->sfp_diags = 0;
1284 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1285 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1286 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1289 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1291 struct xgbe_phy_data *phy_data = pdata->phy_data;
1294 /* Reset the SFP signals and info */
1295 xgbe_phy_sfp_reset(phy_data);
1297 ret = xgbe_phy_get_comm_ownership(pdata);
1301 /* Read the SFP signals and check for module presence */
1302 xgbe_phy_sfp_signals(pdata);
1303 if (phy_data->sfp_mod_absent) {
1304 xgbe_phy_sfp_mod_absent(pdata);
1308 ret = xgbe_phy_sfp_read_eeprom(pdata);
1310 /* Treat any error as if there isn't an SFP plugged in */
1311 xgbe_phy_sfp_reset(phy_data);
1312 xgbe_phy_sfp_mod_absent(pdata);
1316 xgbe_phy_sfp_parse_eeprom(pdata);
1318 xgbe_phy_sfp_external_phy(pdata);
1321 xgbe_phy_sfp_phy_settings(pdata);
1323 xgbe_phy_put_comm_ownership(pdata);
1326 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1328 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1329 struct xgbe_phy_data *phy_data = pdata->phy_data;
1330 u16 lcl_adv = 0, rmt_adv = 0;
1333 pdata->phy.tx_pause = 0;
1334 pdata->phy.rx_pause = 0;
1336 if (!phy_data->phydev)
1339 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1340 lcl_adv |= ADVERTISE_PAUSE_CAP;
1341 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1342 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1344 if (phy_data->phydev->pause) {
1345 XGBE_SET_LP_ADV(lks, Pause);
1346 rmt_adv |= LPA_PAUSE_CAP;
1348 if (phy_data->phydev->asym_pause) {
1349 XGBE_SET_LP_ADV(lks, Asym_Pause);
1350 rmt_adv |= LPA_PAUSE_ASYM;
1353 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1354 if (fc & FLOW_CTRL_TX)
1355 pdata->phy.tx_pause = 1;
1356 if (fc & FLOW_CTRL_RX)
1357 pdata->phy.rx_pause = 1;
1360 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1362 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1363 enum xgbe_mode mode;
1365 XGBE_SET_LP_ADV(lks, Autoneg);
1366 XGBE_SET_LP_ADV(lks, TP);
1368 /* Use external PHY to determine flow control */
1369 if (pdata->phy.pause_autoneg)
1370 xgbe_phy_phydev_flowctrl(pdata);
1372 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1373 case XGBE_SGMII_AN_LINK_SPEED_100:
1374 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1375 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1376 mode = XGBE_MODE_SGMII_100;
1378 /* Half-duplex not supported */
1379 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1380 mode = XGBE_MODE_UNKNOWN;
1383 case XGBE_SGMII_AN_LINK_SPEED_1000:
1384 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1385 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1386 mode = XGBE_MODE_SGMII_1000;
1388 /* Half-duplex not supported */
1389 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1390 mode = XGBE_MODE_UNKNOWN;
1394 mode = XGBE_MODE_UNKNOWN;
1400 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1402 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1403 enum xgbe_mode mode;
1404 unsigned int ad_reg, lp_reg;
1406 XGBE_SET_LP_ADV(lks, Autoneg);
1407 XGBE_SET_LP_ADV(lks, FIBRE);
1409 /* Compare Advertisement and Link Partner register */
1410 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1411 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1413 XGBE_SET_LP_ADV(lks, Pause);
1415 XGBE_SET_LP_ADV(lks, Asym_Pause);
1417 if (pdata->phy.pause_autoneg) {
1418 /* Set flow control based on auto-negotiation result */
1419 pdata->phy.tx_pause = 0;
1420 pdata->phy.rx_pause = 0;
1422 if (ad_reg & lp_reg & 0x100) {
1423 pdata->phy.tx_pause = 1;
1424 pdata->phy.rx_pause = 1;
1425 } else if (ad_reg & lp_reg & 0x80) {
1427 pdata->phy.rx_pause = 1;
1428 else if (lp_reg & 0x100)
1429 pdata->phy.tx_pause = 1;
1434 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1436 /* Half duplex is not supported */
1438 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1443 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1445 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1446 struct xgbe_phy_data *phy_data = pdata->phy_data;
1447 enum xgbe_mode mode;
1448 unsigned int ad_reg, lp_reg;
1450 XGBE_SET_LP_ADV(lks, Autoneg);
1451 XGBE_SET_LP_ADV(lks, Backplane);
1453 /* Use external PHY to determine flow control */
1454 if (pdata->phy.pause_autoneg)
1455 xgbe_phy_phydev_flowctrl(pdata);
1457 /* Compare Advertisement and Link Partner register 2 */
1458 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1459 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1461 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1463 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1466 if (ad_reg & 0x80) {
1467 switch (phy_data->port_mode) {
1468 case XGBE_PORT_MODE_BACKPLANE:
1469 mode = XGBE_MODE_KR;
1472 mode = XGBE_MODE_SFI;
1475 } else if (ad_reg & 0x20) {
1476 switch (phy_data->port_mode) {
1477 case XGBE_PORT_MODE_BACKPLANE:
1478 mode = XGBE_MODE_KX_1000;
1480 case XGBE_PORT_MODE_1000BASE_X:
1483 case XGBE_PORT_MODE_SFP:
1484 switch (phy_data->sfp_base) {
1485 case XGBE_SFP_BASE_1000_T:
1486 if (phy_data->phydev &&
1487 (phy_data->phydev->speed == SPEED_100))
1488 mode = XGBE_MODE_SGMII_100;
1490 mode = XGBE_MODE_SGMII_1000;
1492 case XGBE_SFP_BASE_1000_SX:
1493 case XGBE_SFP_BASE_1000_LX:
1494 case XGBE_SFP_BASE_1000_CX:
1501 if (phy_data->phydev &&
1502 (phy_data->phydev->speed == SPEED_100))
1503 mode = XGBE_MODE_SGMII_100;
1505 mode = XGBE_MODE_SGMII_1000;
1509 mode = XGBE_MODE_UNKNOWN;
1512 /* Compare Advertisement and Link Partner register 3 */
1513 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1514 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1515 if (lp_reg & 0xc000)
1516 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1521 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1523 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1524 enum xgbe_mode mode;
1525 unsigned int ad_reg, lp_reg;
1527 XGBE_SET_LP_ADV(lks, Autoneg);
1528 XGBE_SET_LP_ADV(lks, Backplane);
1530 /* Compare Advertisement and Link Partner register 1 */
1531 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1532 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1534 XGBE_SET_LP_ADV(lks, Pause);
1536 XGBE_SET_LP_ADV(lks, Asym_Pause);
1538 if (pdata->phy.pause_autoneg) {
1539 /* Set flow control based on auto-negotiation result */
1540 pdata->phy.tx_pause = 0;
1541 pdata->phy.rx_pause = 0;
1543 if (ad_reg & lp_reg & 0x400) {
1544 pdata->phy.tx_pause = 1;
1545 pdata->phy.rx_pause = 1;
1546 } else if (ad_reg & lp_reg & 0x800) {
1548 pdata->phy.rx_pause = 1;
1549 else if (lp_reg & 0x400)
1550 pdata->phy.tx_pause = 1;
1554 /* Compare Advertisement and Link Partner register 2 */
1555 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1556 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1558 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1560 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1564 mode = XGBE_MODE_KR;
1565 else if (ad_reg & 0x20)
1566 mode = XGBE_MODE_KX_1000;
1568 mode = XGBE_MODE_UNKNOWN;
1570 /* Compare Advertisement and Link Partner register 3 */
1571 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1572 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1573 if (lp_reg & 0xc000)
1574 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1579 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1581 switch (pdata->an_mode) {
1582 case XGBE_AN_MODE_CL73:
1583 return xgbe_phy_an73_outcome(pdata);
1584 case XGBE_AN_MODE_CL73_REDRV:
1585 return xgbe_phy_an73_redrv_outcome(pdata);
1586 case XGBE_AN_MODE_CL37:
1587 return xgbe_phy_an37_outcome(pdata);
1588 case XGBE_AN_MODE_CL37_SGMII:
1589 return xgbe_phy_an37_sgmii_outcome(pdata);
1591 return XGBE_MODE_UNKNOWN;
1595 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1596 struct ethtool_link_ksettings *dlks)
1598 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1599 struct xgbe_phy_data *phy_data = pdata->phy_data;
1601 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1603 /* Without a re-driver, just return current advertising */
1604 if (!phy_data->redrv)
1607 /* With the KR re-driver we need to advertise a single speed */
1608 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1609 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1611 switch (phy_data->port_mode) {
1612 case XGBE_PORT_MODE_BACKPLANE:
1613 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1615 case XGBE_PORT_MODE_BACKPLANE_2500:
1616 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1618 case XGBE_PORT_MODE_1000BASE_T:
1619 case XGBE_PORT_MODE_1000BASE_X:
1620 case XGBE_PORT_MODE_NBASE_T:
1621 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1623 case XGBE_PORT_MODE_10GBASE_T:
1624 if (phy_data->phydev &&
1625 (phy_data->phydev->speed == SPEED_10000))
1626 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1628 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1630 case XGBE_PORT_MODE_10GBASE_R:
1631 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1633 case XGBE_PORT_MODE_SFP:
1634 switch (phy_data->sfp_base) {
1635 case XGBE_SFP_BASE_1000_T:
1636 case XGBE_SFP_BASE_1000_SX:
1637 case XGBE_SFP_BASE_1000_LX:
1638 case XGBE_SFP_BASE_1000_CX:
1639 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1642 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1647 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1652 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1654 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1655 struct xgbe_phy_data *phy_data = pdata->phy_data;
1659 ret = xgbe_phy_find_phy_device(pdata);
1663 if (!phy_data->phydev)
1666 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1667 lks->link_modes.advertising);
1669 phy_data->phydev->autoneg = pdata->phy.autoneg;
1670 phy_data->phydev->advertising = phy_data->phydev->supported &
1673 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1674 phy_data->phydev->speed = pdata->phy.speed;
1675 phy_data->phydev->duplex = pdata->phy.duplex;
1678 ret = phy_start_aneg(phy_data->phydev);
1683 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1685 switch (phy_data->sfp_base) {
1686 case XGBE_SFP_BASE_1000_T:
1687 return XGBE_AN_MODE_CL37_SGMII;
1688 case XGBE_SFP_BASE_1000_SX:
1689 case XGBE_SFP_BASE_1000_LX:
1690 case XGBE_SFP_BASE_1000_CX:
1691 return XGBE_AN_MODE_CL37;
1693 return XGBE_AN_MODE_NONE;
1697 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1699 struct xgbe_phy_data *phy_data = pdata->phy_data;
1701 /* A KR re-driver will always require CL73 AN */
1702 if (phy_data->redrv)
1703 return XGBE_AN_MODE_CL73_REDRV;
1705 switch (phy_data->port_mode) {
1706 case XGBE_PORT_MODE_BACKPLANE:
1707 return XGBE_AN_MODE_CL73;
1708 case XGBE_PORT_MODE_BACKPLANE_2500:
1709 return XGBE_AN_MODE_NONE;
1710 case XGBE_PORT_MODE_1000BASE_T:
1711 return XGBE_AN_MODE_CL37_SGMII;
1712 case XGBE_PORT_MODE_1000BASE_X:
1713 return XGBE_AN_MODE_CL37;
1714 case XGBE_PORT_MODE_NBASE_T:
1715 return XGBE_AN_MODE_CL37_SGMII;
1716 case XGBE_PORT_MODE_10GBASE_T:
1717 return XGBE_AN_MODE_CL73;
1718 case XGBE_PORT_MODE_10GBASE_R:
1719 return XGBE_AN_MODE_NONE;
1720 case XGBE_PORT_MODE_SFP:
1721 return xgbe_phy_an_sfp_mode(phy_data);
1723 return XGBE_AN_MODE_NONE;
1727 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1728 enum xgbe_phy_redrv_mode mode)
1730 struct xgbe_phy_data *phy_data = pdata->phy_data;
1731 u16 redrv_reg, redrv_val;
1733 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1734 redrv_val = (u16)mode;
1736 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1737 redrv_reg, redrv_val);
1740 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1741 enum xgbe_phy_redrv_mode mode)
1743 struct xgbe_phy_data *phy_data = pdata->phy_data;
1744 unsigned int redrv_reg;
1747 /* Calculate the register to write */
1748 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1750 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1755 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1757 struct xgbe_phy_data *phy_data = pdata->phy_data;
1758 enum xgbe_phy_redrv_mode mode;
1761 if (!phy_data->redrv)
1764 mode = XGBE_PHY_REDRV_MODE_CX;
1765 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1766 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1767 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1768 mode = XGBE_PHY_REDRV_MODE_SR;
1770 ret = xgbe_phy_get_comm_ownership(pdata);
1774 if (phy_data->redrv_if)
1775 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1777 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1779 xgbe_phy_put_comm_ownership(pdata);
1782 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1786 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1787 XGBE_PCS_PSEQ_STATE_MASK);
1788 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1789 /* Mailbox command timed out, reset of RX block is required.
1790 * This can be done by asseting the reset bit and wait for
1793 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1794 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1796 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1797 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1798 usleep_range(40, 50);
1799 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1803 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
1805 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1806 XGBE_PMA_PLL_CTRL_MASK,
1807 enable ? XGBE_PMA_PLL_CTRL_ENABLE
1808 : XGBE_PMA_PLL_CTRL_DISABLE);
1810 /* Wait for command to complete */
1811 usleep_range(100, 200);
1814 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1815 unsigned int cmd, unsigned int sub_cmd)
1817 unsigned int s0 = 0;
1820 /* Disable PLL re-initialization during FW command processing */
1821 xgbe_phy_pll_ctrl(pdata, false);
1823 /* Log if a previous command did not complete */
1824 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1825 netif_dbg(pdata, link, pdata->netdev,
1826 "firmware mailbox not ready for command\n");
1827 xgbe_phy_rx_reset(pdata);
1830 /* Construct the command */
1831 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1832 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1834 /* Issue the command */
1835 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1836 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1837 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1839 /* Wait for command to complete */
1840 wait = XGBE_RATECHANGE_COUNT;
1842 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1845 usleep_range(1000, 2000);
1848 netif_dbg(pdata, link, pdata->netdev,
1849 "firmware mailbox command did not complete\n");
1851 /* Reset on error */
1852 xgbe_phy_rx_reset(pdata);
1855 /* Enable PLL re-initialization */
1856 xgbe_phy_pll_ctrl(pdata, true);
1859 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1861 /* Receiver Reset Cycle */
1862 xgbe_phy_perform_ratechange(pdata, 5, 0);
1864 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1867 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1869 struct xgbe_phy_data *phy_data = pdata->phy_data;
1872 xgbe_phy_perform_ratechange(pdata, 0, 0);
1874 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
1876 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
1879 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
1881 struct xgbe_phy_data *phy_data = pdata->phy_data;
1883 xgbe_phy_set_redrv_mode(pdata);
1886 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
1887 xgbe_phy_perform_ratechange(pdata, 3, 0);
1889 if (phy_data->sfp_cable_len <= 1)
1890 xgbe_phy_perform_ratechange(pdata, 3, 1);
1891 else if (phy_data->sfp_cable_len <= 3)
1892 xgbe_phy_perform_ratechange(pdata, 3, 2);
1894 xgbe_phy_perform_ratechange(pdata, 3, 3);
1897 phy_data->cur_mode = XGBE_MODE_SFI;
1899 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
1902 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
1904 struct xgbe_phy_data *phy_data = pdata->phy_data;
1906 xgbe_phy_set_redrv_mode(pdata);
1909 xgbe_phy_perform_ratechange(pdata, 1, 3);
1911 phy_data->cur_mode = XGBE_MODE_X;
1913 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
1916 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
1918 struct xgbe_phy_data *phy_data = pdata->phy_data;
1920 xgbe_phy_set_redrv_mode(pdata);
1923 xgbe_phy_perform_ratechange(pdata, 1, 2);
1925 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
1927 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
1930 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
1932 struct xgbe_phy_data *phy_data = pdata->phy_data;
1934 xgbe_phy_set_redrv_mode(pdata);
1937 xgbe_phy_perform_ratechange(pdata, 1, 1);
1939 phy_data->cur_mode = XGBE_MODE_SGMII_100;
1941 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
1944 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
1946 struct xgbe_phy_data *phy_data = pdata->phy_data;
1948 xgbe_phy_set_redrv_mode(pdata);
1951 xgbe_phy_perform_ratechange(pdata, 4, 0);
1953 phy_data->cur_mode = XGBE_MODE_KR;
1955 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
1958 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
1960 struct xgbe_phy_data *phy_data = pdata->phy_data;
1962 xgbe_phy_set_redrv_mode(pdata);
1965 xgbe_phy_perform_ratechange(pdata, 2, 0);
1967 phy_data->cur_mode = XGBE_MODE_KX_2500;
1969 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
1972 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
1974 struct xgbe_phy_data *phy_data = pdata->phy_data;
1976 xgbe_phy_set_redrv_mode(pdata);
1979 xgbe_phy_perform_ratechange(pdata, 1, 3);
1981 phy_data->cur_mode = XGBE_MODE_KX_1000;
1983 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
1986 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
1988 struct xgbe_phy_data *phy_data = pdata->phy_data;
1990 return phy_data->cur_mode;
1993 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
1995 struct xgbe_phy_data *phy_data = pdata->phy_data;
1997 /* No switching if not 10GBase-T */
1998 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
1999 return xgbe_phy_cur_mode(pdata);
2001 switch (xgbe_phy_cur_mode(pdata)) {
2002 case XGBE_MODE_SGMII_100:
2003 case XGBE_MODE_SGMII_1000:
2004 return XGBE_MODE_KR;
2007 return XGBE_MODE_SGMII_1000;
2011 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2013 return XGBE_MODE_KX_2500;
2016 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2018 /* If we are in KR switch to KX, and vice-versa */
2019 switch (xgbe_phy_cur_mode(pdata)) {
2020 case XGBE_MODE_KX_1000:
2021 return XGBE_MODE_KR;
2024 return XGBE_MODE_KX_1000;
2028 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2030 struct xgbe_phy_data *phy_data = pdata->phy_data;
2032 switch (phy_data->port_mode) {
2033 case XGBE_PORT_MODE_BACKPLANE:
2034 return xgbe_phy_switch_bp_mode(pdata);
2035 case XGBE_PORT_MODE_BACKPLANE_2500:
2036 return xgbe_phy_switch_bp_2500_mode(pdata);
2037 case XGBE_PORT_MODE_1000BASE_T:
2038 case XGBE_PORT_MODE_NBASE_T:
2039 case XGBE_PORT_MODE_10GBASE_T:
2040 return xgbe_phy_switch_baset_mode(pdata);
2041 case XGBE_PORT_MODE_1000BASE_X:
2042 case XGBE_PORT_MODE_10GBASE_R:
2043 case XGBE_PORT_MODE_SFP:
2044 /* No switching, so just return current mode */
2045 return xgbe_phy_cur_mode(pdata);
2047 return XGBE_MODE_UNKNOWN;
2051 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2058 return XGBE_MODE_KR;
2060 return XGBE_MODE_UNKNOWN;
2064 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2069 return XGBE_MODE_SGMII_100;
2071 return XGBE_MODE_SGMII_1000;
2073 return XGBE_MODE_KX_2500;
2075 return XGBE_MODE_KR;
2077 return XGBE_MODE_UNKNOWN;
2081 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2086 return XGBE_MODE_SGMII_100;
2088 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2089 return XGBE_MODE_SGMII_1000;
2094 return XGBE_MODE_SFI;
2096 return XGBE_MODE_UNKNOWN;
2100 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2104 return XGBE_MODE_KX_2500;
2106 return XGBE_MODE_UNKNOWN;
2110 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2114 return XGBE_MODE_KX_1000;
2116 return XGBE_MODE_KR;
2118 return XGBE_MODE_UNKNOWN;
2122 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2125 struct xgbe_phy_data *phy_data = pdata->phy_data;
2127 switch (phy_data->port_mode) {
2128 case XGBE_PORT_MODE_BACKPLANE:
2129 return xgbe_phy_get_bp_mode(speed);
2130 case XGBE_PORT_MODE_BACKPLANE_2500:
2131 return xgbe_phy_get_bp_2500_mode(speed);
2132 case XGBE_PORT_MODE_1000BASE_T:
2133 case XGBE_PORT_MODE_NBASE_T:
2134 case XGBE_PORT_MODE_10GBASE_T:
2135 return xgbe_phy_get_baset_mode(phy_data, speed);
2136 case XGBE_PORT_MODE_1000BASE_X:
2137 case XGBE_PORT_MODE_10GBASE_R:
2138 return xgbe_phy_get_basex_mode(phy_data, speed);
2139 case XGBE_PORT_MODE_SFP:
2140 return xgbe_phy_get_sfp_mode(phy_data, speed);
2142 return XGBE_MODE_UNKNOWN;
2146 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2149 case XGBE_MODE_KX_1000:
2150 xgbe_phy_kx_1000_mode(pdata);
2152 case XGBE_MODE_KX_2500:
2153 xgbe_phy_kx_2500_mode(pdata);
2156 xgbe_phy_kr_mode(pdata);
2158 case XGBE_MODE_SGMII_100:
2159 xgbe_phy_sgmii_100_mode(pdata);
2161 case XGBE_MODE_SGMII_1000:
2162 xgbe_phy_sgmii_1000_mode(pdata);
2165 xgbe_phy_x_mode(pdata);
2168 xgbe_phy_sfi_mode(pdata);
2175 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2176 enum xgbe_mode mode, bool advert)
2178 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2181 enum xgbe_mode cur_mode;
2183 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2184 if (cur_mode == mode)
2191 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2192 enum xgbe_mode mode)
2194 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2198 return xgbe_phy_check_mode(pdata, mode,
2199 XGBE_ADV(lks, 1000baseX_Full));
2201 return xgbe_phy_check_mode(pdata, mode,
2202 XGBE_ADV(lks, 10000baseKR_Full));
2208 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2209 enum xgbe_mode mode)
2211 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2214 case XGBE_MODE_SGMII_100:
2215 return xgbe_phy_check_mode(pdata, mode,
2216 XGBE_ADV(lks, 100baseT_Full));
2217 case XGBE_MODE_SGMII_1000:
2218 return xgbe_phy_check_mode(pdata, mode,
2219 XGBE_ADV(lks, 1000baseT_Full));
2220 case XGBE_MODE_KX_2500:
2221 return xgbe_phy_check_mode(pdata, mode,
2222 XGBE_ADV(lks, 2500baseT_Full));
2224 return xgbe_phy_check_mode(pdata, mode,
2225 XGBE_ADV(lks, 10000baseT_Full));
2231 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2232 enum xgbe_mode mode)
2234 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2235 struct xgbe_phy_data *phy_data = pdata->phy_data;
2239 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2241 return xgbe_phy_check_mode(pdata, mode,
2242 XGBE_ADV(lks, 1000baseX_Full));
2243 case XGBE_MODE_SGMII_100:
2244 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2246 return xgbe_phy_check_mode(pdata, mode,
2247 XGBE_ADV(lks, 100baseT_Full));
2248 case XGBE_MODE_SGMII_1000:
2249 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2251 return xgbe_phy_check_mode(pdata, mode,
2252 XGBE_ADV(lks, 1000baseT_Full));
2254 if (phy_data->sfp_mod_absent)
2256 return xgbe_phy_check_mode(pdata, mode,
2257 XGBE_ADV(lks, 10000baseSR_Full) ||
2258 XGBE_ADV(lks, 10000baseLR_Full) ||
2259 XGBE_ADV(lks, 10000baseLRM_Full) ||
2260 XGBE_ADV(lks, 10000baseER_Full) ||
2261 XGBE_ADV(lks, 10000baseCR_Full));
2267 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2268 enum xgbe_mode mode)
2270 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2273 case XGBE_MODE_KX_2500:
2274 return xgbe_phy_check_mode(pdata, mode,
2275 XGBE_ADV(lks, 2500baseX_Full));
2281 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2282 enum xgbe_mode mode)
2284 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2287 case XGBE_MODE_KX_1000:
2288 return xgbe_phy_check_mode(pdata, mode,
2289 XGBE_ADV(lks, 1000baseKX_Full));
2291 return xgbe_phy_check_mode(pdata, mode,
2292 XGBE_ADV(lks, 10000baseKR_Full));
2298 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2300 struct xgbe_phy_data *phy_data = pdata->phy_data;
2302 switch (phy_data->port_mode) {
2303 case XGBE_PORT_MODE_BACKPLANE:
2304 return xgbe_phy_use_bp_mode(pdata, mode);
2305 case XGBE_PORT_MODE_BACKPLANE_2500:
2306 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2307 case XGBE_PORT_MODE_1000BASE_T:
2308 case XGBE_PORT_MODE_NBASE_T:
2309 case XGBE_PORT_MODE_10GBASE_T:
2310 return xgbe_phy_use_baset_mode(pdata, mode);
2311 case XGBE_PORT_MODE_1000BASE_X:
2312 case XGBE_PORT_MODE_10GBASE_R:
2313 return xgbe_phy_use_basex_mode(pdata, mode);
2314 case XGBE_PORT_MODE_SFP:
2315 return xgbe_phy_use_sfp_mode(pdata, mode);
2321 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2326 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2328 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2334 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2342 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2344 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2350 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2355 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2357 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2358 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2360 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2366 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2376 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2387 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2389 struct xgbe_phy_data *phy_data = pdata->phy_data;
2391 switch (phy_data->port_mode) {
2392 case XGBE_PORT_MODE_BACKPLANE:
2393 return xgbe_phy_valid_speed_bp_mode(speed);
2394 case XGBE_PORT_MODE_BACKPLANE_2500:
2395 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2396 case XGBE_PORT_MODE_1000BASE_T:
2397 case XGBE_PORT_MODE_NBASE_T:
2398 case XGBE_PORT_MODE_10GBASE_T:
2399 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2400 case XGBE_PORT_MODE_1000BASE_X:
2401 case XGBE_PORT_MODE_10GBASE_R:
2402 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2403 case XGBE_PORT_MODE_SFP:
2404 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2410 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2412 struct xgbe_phy_data *phy_data = pdata->phy_data;
2418 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2419 /* Check SFP signals */
2420 xgbe_phy_sfp_detect(pdata);
2422 if (phy_data->sfp_changed) {
2427 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2431 if (phy_data->phydev) {
2432 /* Check external PHY */
2433 ret = phy_read_status(phy_data->phydev);
2437 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2438 !phy_aneg_done(phy_data->phydev))
2441 if (!phy_data->phydev->link)
2445 /* Link status is latched low, so read once to clear
2446 * and then read again to get current state
2448 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2449 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2450 if (reg & MDIO_STAT1_LSTATUS)
2453 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2454 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2455 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2456 netif_carrier_off(pdata->netdev);
2461 /* No link, attempt a receiver reset cycle */
2462 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2463 phy_data->rrc_count = 0;
2464 xgbe_phy_rrc(pdata);
2470 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2472 struct xgbe_phy_data *phy_data = pdata->phy_data;
2475 reg = XP_IOREAD(pdata, XP_PROP_3);
2477 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2478 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
2480 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
2482 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
2484 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
2486 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
2488 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
2491 if (netif_msg_probe(pdata)) {
2492 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2493 phy_data->sfp_gpio_address);
2494 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2495 phy_data->sfp_gpio_mask);
2496 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2497 phy_data->sfp_gpio_rx_los);
2498 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2499 phy_data->sfp_gpio_tx_fault);
2500 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2501 phy_data->sfp_gpio_mod_absent);
2502 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2503 phy_data->sfp_gpio_rate_select);
2507 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2509 struct xgbe_phy_data *phy_data = pdata->phy_data;
2510 unsigned int reg, mux_addr_hi, mux_addr_lo;
2512 reg = XP_IOREAD(pdata, XP_PROP_4);
2514 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
2515 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
2516 if (mux_addr_lo == XGBE_SFP_DIRECT)
2519 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2520 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2521 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
2523 if (netif_msg_probe(pdata)) {
2524 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2525 phy_data->sfp_mux_address);
2526 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2527 phy_data->sfp_mux_channel);
2531 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2533 xgbe_phy_sfp_comm_setup(pdata);
2534 xgbe_phy_sfp_gpio_setup(pdata);
2537 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2539 struct xgbe_phy_data *phy_data = pdata->phy_data;
2542 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2546 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2551 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2553 struct xgbe_phy_data *phy_data = pdata->phy_data;
2554 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2557 /* Read the output port registers */
2559 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2560 &gpio_reg, sizeof(gpio_reg),
2561 gpio_ports, sizeof(gpio_ports));
2565 /* Prepare to write the GPIO data */
2567 gpio_data[1] = gpio_ports[0];
2568 gpio_data[2] = gpio_ports[1];
2570 /* Set the GPIO pin */
2571 if (phy_data->mdio_reset_gpio < 8)
2572 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2574 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2576 /* Write the output port registers */
2577 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2578 gpio_data, sizeof(gpio_data));
2582 /* Clear the GPIO pin */
2583 if (phy_data->mdio_reset_gpio < 8)
2584 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2586 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2588 /* Write the output port registers */
2589 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2590 gpio_data, sizeof(gpio_data));
2595 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2597 struct xgbe_phy_data *phy_data = pdata->phy_data;
2600 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2603 ret = xgbe_phy_get_comm_ownership(pdata);
2607 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2608 ret = xgbe_phy_i2c_mdio_reset(pdata);
2609 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2610 ret = xgbe_phy_int_mdio_reset(pdata);
2612 xgbe_phy_put_comm_ownership(pdata);
2617 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2619 if (!phy_data->redrv)
2622 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2625 switch (phy_data->redrv_model) {
2626 case XGBE_PHY_REDRV_MODEL_4223:
2627 if (phy_data->redrv_lane > 3)
2630 case XGBE_PHY_REDRV_MODEL_4227:
2631 if (phy_data->redrv_lane > 1)
2641 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2643 struct xgbe_phy_data *phy_data = pdata->phy_data;
2646 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2649 reg = XP_IOREAD(pdata, XP_PROP_3);
2650 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
2651 switch (phy_data->mdio_reset) {
2652 case XGBE_MDIO_RESET_NONE:
2653 case XGBE_MDIO_RESET_I2C_GPIO:
2654 case XGBE_MDIO_RESET_INT_GPIO:
2657 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2658 phy_data->mdio_reset);
2662 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2663 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2664 XP_GET_BITS(reg, XP_PROP_3,
2665 MDIO_RESET_I2C_ADDR);
2666 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2667 MDIO_RESET_I2C_GPIO);
2668 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2669 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2670 MDIO_RESET_INT_GPIO);
2676 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2678 struct xgbe_phy_data *phy_data = pdata->phy_data;
2680 switch (phy_data->port_mode) {
2681 case XGBE_PORT_MODE_BACKPLANE:
2682 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2683 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2686 case XGBE_PORT_MODE_BACKPLANE_2500:
2687 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2690 case XGBE_PORT_MODE_1000BASE_T:
2691 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2692 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2695 case XGBE_PORT_MODE_1000BASE_X:
2696 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2699 case XGBE_PORT_MODE_NBASE_T:
2700 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2701 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2702 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2705 case XGBE_PORT_MODE_10GBASE_T:
2706 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2707 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2708 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2711 case XGBE_PORT_MODE_10GBASE_R:
2712 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2715 case XGBE_PORT_MODE_SFP:
2716 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2717 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2718 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2728 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2730 struct xgbe_phy_data *phy_data = pdata->phy_data;
2732 switch (phy_data->port_mode) {
2733 case XGBE_PORT_MODE_BACKPLANE:
2734 case XGBE_PORT_MODE_BACKPLANE_2500:
2735 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2738 case XGBE_PORT_MODE_1000BASE_T:
2739 case XGBE_PORT_MODE_1000BASE_X:
2740 case XGBE_PORT_MODE_NBASE_T:
2741 case XGBE_PORT_MODE_10GBASE_T:
2742 case XGBE_PORT_MODE_10GBASE_R:
2743 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2746 case XGBE_PORT_MODE_SFP:
2747 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2757 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2761 reg = XP_IOREAD(pdata, XP_PROP_0);
2762 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
2764 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
2770 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2772 struct xgbe_phy_data *phy_data = pdata->phy_data;
2774 if (!pdata->debugfs_an_cdr_workaround)
2777 if (!phy_data->phy_cdr_notrack)
2780 usleep_range(phy_data->phy_cdr_delay,
2781 phy_data->phy_cdr_delay + 500);
2783 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2784 XGBE_PMA_CDR_TRACK_EN_MASK,
2785 XGBE_PMA_CDR_TRACK_EN_ON);
2787 phy_data->phy_cdr_notrack = 0;
2790 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2792 struct xgbe_phy_data *phy_data = pdata->phy_data;
2794 if (!pdata->debugfs_an_cdr_workaround)
2797 if (phy_data->phy_cdr_notrack)
2800 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2801 XGBE_PMA_CDR_TRACK_EN_MASK,
2802 XGBE_PMA_CDR_TRACK_EN_OFF);
2804 xgbe_phy_rrc(pdata);
2806 phy_data->phy_cdr_notrack = 1;
2809 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2811 if (!pdata->debugfs_an_cdr_track_early)
2812 xgbe_phy_cdr_track(pdata);
2815 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2817 if (pdata->debugfs_an_cdr_track_early)
2818 xgbe_phy_cdr_track(pdata);
2821 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2823 struct xgbe_phy_data *phy_data = pdata->phy_data;
2825 switch (pdata->an_mode) {
2826 case XGBE_AN_MODE_CL73:
2827 case XGBE_AN_MODE_CL73_REDRV:
2828 if (phy_data->cur_mode != XGBE_MODE_KR)
2831 xgbe_phy_cdr_track(pdata);
2833 switch (pdata->an_result) {
2835 case XGBE_AN_COMPLETE:
2838 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2839 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2841 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
2850 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
2852 struct xgbe_phy_data *phy_data = pdata->phy_data;
2854 switch (pdata->an_mode) {
2855 case XGBE_AN_MODE_CL73:
2856 case XGBE_AN_MODE_CL73_REDRV:
2857 if (phy_data->cur_mode != XGBE_MODE_KR)
2860 xgbe_phy_cdr_notrack(pdata);
2867 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2869 struct xgbe_phy_data *phy_data = pdata->phy_data;
2871 /* If we have an external PHY, free it */
2872 xgbe_phy_free_phy_device(pdata);
2874 /* Reset SFP data */
2875 xgbe_phy_sfp_reset(phy_data);
2876 xgbe_phy_sfp_mod_absent(pdata);
2878 /* Reset CDR support */
2879 xgbe_phy_cdr_track(pdata);
2881 /* Power off the PHY */
2882 xgbe_phy_power_off(pdata);
2884 /* Stop the I2C controller */
2885 pdata->i2c_if.i2c_stop(pdata);
2888 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
2890 struct xgbe_phy_data *phy_data = pdata->phy_data;
2893 /* Start the I2C controller */
2894 ret = pdata->i2c_if.i2c_start(pdata);
2898 /* Set the proper MDIO mode for the re-driver */
2899 if (phy_data->redrv && !phy_data->redrv_if) {
2900 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2901 XGBE_MDIO_MODE_CL22);
2903 netdev_err(pdata->netdev,
2904 "redriver mdio port not compatible (%u)\n",
2905 phy_data->redrv_addr);
2910 /* Start in highest supported mode */
2911 xgbe_phy_set_mode(pdata, phy_data->start_mode);
2913 /* Reset CDR support */
2914 xgbe_phy_cdr_track(pdata);
2916 /* After starting the I2C controller, we can check for an SFP */
2917 switch (phy_data->port_mode) {
2918 case XGBE_PORT_MODE_SFP:
2919 xgbe_phy_sfp_detect(pdata);
2925 /* If we have an external PHY, start it */
2926 ret = xgbe_phy_find_phy_device(pdata);
2933 pdata->i2c_if.i2c_stop(pdata);
2938 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
2940 struct xgbe_phy_data *phy_data = pdata->phy_data;
2941 enum xgbe_mode cur_mode;
2944 /* Reset by power cycling the PHY */
2945 cur_mode = phy_data->cur_mode;
2946 xgbe_phy_power_off(pdata);
2947 xgbe_phy_set_mode(pdata, cur_mode);
2949 if (!phy_data->phydev)
2952 /* Reset the external PHY */
2953 ret = xgbe_phy_mdio_reset(pdata);
2957 return phy_init_hw(phy_data->phydev);
2960 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
2962 struct xgbe_phy_data *phy_data = pdata->phy_data;
2964 /* Unregister for driving external PHYs */
2965 mdiobus_unregister(phy_data->mii);
2968 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
2970 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2971 struct xgbe_phy_data *phy_data;
2972 struct mii_bus *mii;
2976 /* Check if enabled */
2977 if (!xgbe_phy_port_enabled(pdata)) {
2978 dev_info(pdata->dev, "device is not enabled\n");
2982 /* Initialize the I2C controller */
2983 ret = pdata->i2c_if.i2c_init(pdata);
2987 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
2990 pdata->phy_data = phy_data;
2992 reg = XP_IOREAD(pdata, XP_PROP_0);
2993 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2994 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2995 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2996 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2997 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2998 if (netif_msg_probe(pdata)) {
2999 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3000 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3001 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3002 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3003 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3006 reg = XP_IOREAD(pdata, XP_PROP_4);
3007 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
3008 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
3009 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
3010 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
3011 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
3012 if (phy_data->redrv && netif_msg_probe(pdata)) {
3013 dev_dbg(pdata->dev, "redrv present\n");
3014 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3015 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3016 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3017 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3020 /* Validate the connection requested */
3021 if (xgbe_phy_conn_type_mismatch(pdata)) {
3022 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3023 phy_data->port_mode, phy_data->conn_type);
3027 /* Validate the mode requested */
3028 if (xgbe_phy_port_mode_mismatch(pdata)) {
3029 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3030 phy_data->port_mode, phy_data->port_speeds);
3034 /* Check for and validate MDIO reset support */
3035 ret = xgbe_phy_mdio_reset_setup(pdata);
3039 /* Validate the re-driver information */
3040 if (xgbe_phy_redrv_error(phy_data)) {
3041 dev_err(pdata->dev, "phy re-driver settings error\n");
3044 pdata->kr_redrv = phy_data->redrv;
3046 /* Indicate current mode is unknown */
3047 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3049 /* Initialize supported features */
3052 switch (phy_data->port_mode) {
3053 /* Backplane support */
3054 case XGBE_PORT_MODE_BACKPLANE:
3055 XGBE_SET_SUP(lks, Autoneg);
3056 XGBE_SET_SUP(lks, Pause);
3057 XGBE_SET_SUP(lks, Asym_Pause);
3058 XGBE_SET_SUP(lks, Backplane);
3059 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3060 XGBE_SET_SUP(lks, 1000baseKX_Full);
3061 phy_data->start_mode = XGBE_MODE_KX_1000;
3063 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3064 XGBE_SET_SUP(lks, 10000baseKR_Full);
3065 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3066 XGBE_SET_SUP(lks, 10000baseR_FEC);
3067 phy_data->start_mode = XGBE_MODE_KR;
3070 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3072 case XGBE_PORT_MODE_BACKPLANE_2500:
3073 XGBE_SET_SUP(lks, Pause);
3074 XGBE_SET_SUP(lks, Asym_Pause);
3075 XGBE_SET_SUP(lks, Backplane);
3076 XGBE_SET_SUP(lks, 2500baseX_Full);
3077 phy_data->start_mode = XGBE_MODE_KX_2500;
3079 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3082 /* MDIO 1GBase-T support */
3083 case XGBE_PORT_MODE_1000BASE_T:
3084 XGBE_SET_SUP(lks, Autoneg);
3085 XGBE_SET_SUP(lks, Pause);
3086 XGBE_SET_SUP(lks, Asym_Pause);
3087 XGBE_SET_SUP(lks, TP);
3088 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3089 XGBE_SET_SUP(lks, 100baseT_Full);
3090 phy_data->start_mode = XGBE_MODE_SGMII_100;
3092 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3093 XGBE_SET_SUP(lks, 1000baseT_Full);
3094 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3097 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3100 /* MDIO Base-X support */
3101 case XGBE_PORT_MODE_1000BASE_X:
3102 XGBE_SET_SUP(lks, Autoneg);
3103 XGBE_SET_SUP(lks, Pause);
3104 XGBE_SET_SUP(lks, Asym_Pause);
3105 XGBE_SET_SUP(lks, FIBRE);
3106 XGBE_SET_SUP(lks, 1000baseX_Full);
3107 phy_data->start_mode = XGBE_MODE_X;
3109 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3112 /* MDIO NBase-T support */
3113 case XGBE_PORT_MODE_NBASE_T:
3114 XGBE_SET_SUP(lks, Autoneg);
3115 XGBE_SET_SUP(lks, Pause);
3116 XGBE_SET_SUP(lks, Asym_Pause);
3117 XGBE_SET_SUP(lks, TP);
3118 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3119 XGBE_SET_SUP(lks, 100baseT_Full);
3120 phy_data->start_mode = XGBE_MODE_SGMII_100;
3122 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3123 XGBE_SET_SUP(lks, 1000baseT_Full);
3124 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3126 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3127 XGBE_SET_SUP(lks, 2500baseT_Full);
3128 phy_data->start_mode = XGBE_MODE_KX_2500;
3131 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3134 /* 10GBase-T support */
3135 case XGBE_PORT_MODE_10GBASE_T:
3136 XGBE_SET_SUP(lks, Autoneg);
3137 XGBE_SET_SUP(lks, Pause);
3138 XGBE_SET_SUP(lks, Asym_Pause);
3139 XGBE_SET_SUP(lks, TP);
3140 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3141 XGBE_SET_SUP(lks, 100baseT_Full);
3142 phy_data->start_mode = XGBE_MODE_SGMII_100;
3144 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3145 XGBE_SET_SUP(lks, 1000baseT_Full);
3146 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3148 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3149 XGBE_SET_SUP(lks, 10000baseT_Full);
3150 phy_data->start_mode = XGBE_MODE_KR;
3153 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3156 /* 10GBase-R support */
3157 case XGBE_PORT_MODE_10GBASE_R:
3158 XGBE_SET_SUP(lks, Autoneg);
3159 XGBE_SET_SUP(lks, Pause);
3160 XGBE_SET_SUP(lks, Asym_Pause);
3161 XGBE_SET_SUP(lks, FIBRE);
3162 XGBE_SET_SUP(lks, 10000baseSR_Full);
3163 XGBE_SET_SUP(lks, 10000baseLR_Full);
3164 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3165 XGBE_SET_SUP(lks, 10000baseER_Full);
3166 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3167 XGBE_SET_SUP(lks, 10000baseR_FEC);
3168 phy_data->start_mode = XGBE_MODE_SFI;
3170 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3174 case XGBE_PORT_MODE_SFP:
3175 XGBE_SET_SUP(lks, Autoneg);
3176 XGBE_SET_SUP(lks, Pause);
3177 XGBE_SET_SUP(lks, Asym_Pause);
3178 XGBE_SET_SUP(lks, TP);
3179 XGBE_SET_SUP(lks, FIBRE);
3180 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3181 phy_data->start_mode = XGBE_MODE_SGMII_100;
3182 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3183 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3184 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3185 phy_data->start_mode = XGBE_MODE_SFI;
3187 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3189 xgbe_phy_sfp_setup(pdata);
3195 if (netif_msg_probe(pdata))
3196 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3197 __ETHTOOL_LINK_MODE_MASK_NBITS,
3198 lks->link_modes.supported);
3200 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3201 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3202 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3203 phy_data->phydev_mode);
3206 "mdio port/clause not compatible (%d/%u)\n",
3207 phy_data->mdio_addr, phy_data->phydev_mode);
3212 if (phy_data->redrv && !phy_data->redrv_if) {
3213 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3214 XGBE_MDIO_MODE_CL22);
3217 "redriver mdio port not compatible (%u)\n",
3218 phy_data->redrv_addr);
3223 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3225 /* Register for driving external PHYs */
3226 mii = devm_mdiobus_alloc(pdata->dev);
3228 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3233 mii->name = "amd-xgbe-mii";
3234 mii->read = xgbe_phy_mii_read;
3235 mii->write = xgbe_phy_mii_write;
3236 mii->parent = pdata->dev;
3238 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3239 ret = mdiobus_register(mii);
3241 dev_err(pdata->dev, "mdiobus_register failed\n");
3244 phy_data->mii = mii;
3249 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3251 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3253 phy_impl->init = xgbe_phy_init;
3254 phy_impl->exit = xgbe_phy_exit;
3256 phy_impl->reset = xgbe_phy_reset;
3257 phy_impl->start = xgbe_phy_start;
3258 phy_impl->stop = xgbe_phy_stop;
3260 phy_impl->link_status = xgbe_phy_link_status;
3262 phy_impl->valid_speed = xgbe_phy_valid_speed;
3264 phy_impl->use_mode = xgbe_phy_use_mode;
3265 phy_impl->set_mode = xgbe_phy_set_mode;
3266 phy_impl->get_mode = xgbe_phy_get_mode;
3267 phy_impl->switch_mode = xgbe_phy_switch_mode;
3268 phy_impl->cur_mode = xgbe_phy_cur_mode;
3270 phy_impl->an_mode = xgbe_phy_an_mode;
3272 phy_impl->an_config = xgbe_phy_an_config;
3274 phy_impl->an_advertising = xgbe_phy_an_advertising;
3276 phy_impl->an_outcome = xgbe_phy_an_outcome;
3278 phy_impl->an_pre = xgbe_phy_an_pre;
3279 phy_impl->an_post = xgbe_phy_an_post;
3281 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3282 phy_impl->kr_training_post = xgbe_phy_kr_training_post;