drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <linux/interrupt.h>
 122 #include <net/busy_poll.h>
 123 #include <linux/clk.h>
 124 #include <linux/if_ether.h>
 125 #include <linux/net_tstamp.h>
 126 #include <linux/phy.h>
 127 #include <net/vxlan.h>
 128
 129 #include "xgbe.h"
 130 #include "xgbe-common.h"
 131
 132 static unsigned int ecc_sec_info_threshold = 10;
 133 static unsigned int ecc_sec_warn_threshold = 10000;
 134 static unsigned int ecc_sec_period = 600;
 135 static unsigned int ecc_ded_threshold = 2;
 136 static unsigned int ecc_ded_period = 600;
 137
 138 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
 139 /* Only expose the ECC parameters if supported */
 140 module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO);
 141 MODULE_PARM_DESC(ecc_sec_info_threshold,
 142                  " ECC corrected error informational threshold setting");
 143
 144 module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO);
 145 MODULE_PARM_DESC(ecc_sec_warn_threshold,
 146                  " ECC corrected error warning threshold setting");
 147
 148 module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO);
 149 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
 150
 151 module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO);
 152 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
 153
 154 module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO);
 155 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
 156 #endif
 157
 158 static int xgbe_one_poll(struct napi_struct *, int);
 159 static int xgbe_all_poll(struct napi_struct *, int);
 160 static void xgbe_stop(struct xgbe_prv_data *);
 161
 162 static void *xgbe_alloc_node(size_t size, int node)
 163 {
 164         void *mem;
 165
 166         mem = kzalloc_node(size, GFP_KERNEL, node);
 167         if (!mem)
 168                 mem = kzalloc(size, GFP_KERNEL);
 169
 170         return mem;
 171 }
 172
 173 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 174 {
 175         unsigned int i;
 176
 177         for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
 178                 if (!pdata->channel[i])
 179                         continue;
 180
 181                 kfree(pdata->channel[i]->rx_ring);
 182                 kfree(pdata->channel[i]->tx_ring);
 183                 kfree(pdata->channel[i]);
 184
 185                 pdata->channel[i] = NULL;
 186         }
 187
 188         pdata->channel_count = 0;
 189 }
 190
 191 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 192 {
 193         struct xgbe_channel *channel;
 194         struct xgbe_ring *ring;
 195         unsigned int count, i;
 196         unsigned int cpu;
 197         int node;
 198
 199         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 200         for (i = 0; i < count; i++) {
 201                 /* Attempt to use a CPU on the node the device is on */
 202                 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
 203
 204                 /* Set the allocation node based on the returned CPU */
 205                 node = cpu_to_node(cpu);
 206
 207                 channel = xgbe_alloc_node(sizeof(*channel), node);
 208                 if (!channel)
 209                         goto err_mem;
 210                 pdata->channel[i] = channel;
 211
 212                 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
 213                 channel->pdata = pdata;
 214                 channel->queue_index = i;
 215                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 216                                     (DMA_CH_INC * i);
 217                 channel->node = node;
 218                 cpumask_set_cpu(cpu, &channel->affinity_mask);
 219
 220                 if (pdata->per_channel_irq)
 221                         channel->dma_irq = pdata->channel_irq[i];
 222
 223                 if (i < pdata->tx_ring_count) {
 224                         ring = xgbe_alloc_node(sizeof(*ring), node);
 225                         if (!ring)
 226                                 goto err_mem;
 227
 228                         spin_lock_init(&ring->lock);
 229                         ring->node = node;
 230
 231                         channel->tx_ring = ring;
 232                 }
 233
 234                 if (i < pdata->rx_ring_count) {
 235                         ring = xgbe_alloc_node(sizeof(*ring), node);
 236                         if (!ring)
 237                                 goto err_mem;
 238
 239                         spin_lock_init(&ring->lock);
 240                         ring->node = node;
 241
 242                         channel->rx_ring = ring;
 243                 }
 244
 245                 netif_dbg(pdata, drv, pdata->netdev,
 246                           "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
 247
 248                 netif_dbg(pdata, drv, pdata->netdev,
 249                           "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 250                           channel->name, channel->dma_regs, channel->dma_irq,
 251                           channel->tx_ring, channel->rx_ring);
 252         }
 253
 254         pdata->channel_count = count;
 255
 256         return 0;
 257
 258 err_mem:
 259         xgbe_free_channels(pdata);
 260
 261         return -ENOMEM;
 262 }
 263
 264 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 265 {
 266         return (ring->rdesc_count - (ring->cur - ring->dirty));
 267 }
 268
 269 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
 270 {
 271         return (ring->cur - ring->dirty);
 272 }
 273
 274 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
 275                                     struct xgbe_ring *ring, unsigned int count)
 276 {
 277         struct xgbe_prv_data *pdata = channel->pdata;
 278
 279         if (count > xgbe_tx_avail_desc(ring)) {
 280                 netif_info(pdata, drv, pdata->netdev,
 281                            "Tx queue stopped, not enough descriptors available\n");
 282                 netif_stop_subqueue(pdata->netdev, channel->queue_index);
 283                 ring->tx.queue_stopped = 1;
 284
 285                 /* If we haven't notified the hardware because of xmit_more
 286                  * support, tell it now
 287                  */
 288                 if (ring->tx.xmit_more)
 289                         pdata->hw_if.tx_start_xmit(channel, ring);
 290
 291                 return NETDEV_TX_BUSY;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 298 {
 299         unsigned int rx_buf_size;
 300
 301         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 302         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 303
 304         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 305                       ~(XGBE_RX_BUF_ALIGN - 1);
 306
 307         return rx_buf_size;
 308 }
 309
 310 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
 311                                   struct xgbe_channel *channel)
 312 {
 313         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 314         enum xgbe_int int_id;
 315
 316         if (channel->tx_ring && channel->rx_ring)
 317                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 318         else if (channel->tx_ring)
 319                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 320         else if (channel->rx_ring)
 321                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 322         else
 323                 return;
 324
 325         hw_if->enable_int(channel, int_id);
 326 }
 327
 328 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 329 {
 330         unsigned int i;
 331
 332         for (i = 0; i < pdata->channel_count; i++)
 333                 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
 334 }
 335
 336 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
 337                                    struct xgbe_channel *channel)
 338 {
 339         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 340         enum xgbe_int int_id;
 341
 342         if (channel->tx_ring && channel->rx_ring)
 343                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 344         else if (channel->tx_ring)
 345                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 346         else if (channel->rx_ring)
 347                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 348         else
 349                 return;
 350
 351         hw_if->disable_int(channel, int_id);
 352 }
 353
 354 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 355 {
 356         unsigned int i;
 357
 358         for (i = 0; i < pdata->channel_count; i++)
 359                 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
 360 }
 361
 362 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
 363                          unsigned int *count, const char *area)
 364 {
 365         if (time_before(jiffies, *period)) {
 366                 (*count)++;
 367         } else {
 368                 *period = jiffies + (ecc_sec_period * HZ);
 369                 *count = 1;
 370         }
 371
 372         if (*count > ecc_sec_info_threshold)
 373                 dev_warn_once(pdata->dev,
 374                               "%s ECC corrected errors exceed informational threshold\n",
 375                               area);
 376
 377         if (*count > ecc_sec_warn_threshold) {
 378                 dev_warn_once(pdata->dev,
 379                               "%s ECC corrected errors exceed warning threshold\n",
 380                               area);
 381                 return true;
 382         }
 383
 384         return false;
 385 }
 386
 387 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
 388                          unsigned int *count, const char *area)
 389 {
 390         if (time_before(jiffies, *period)) {
 391                 (*count)++;
 392         } else {
 393                 *period = jiffies + (ecc_ded_period * HZ);
 394                 *count = 1;
 395         }
 396
 397         if (*count > ecc_ded_threshold) {
 398                 netdev_alert(pdata->netdev,
 399                              "%s ECC detected errors exceed threshold\n",
 400                              area);
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 static void xgbe_ecc_isr_task(unsigned long data)
 408 {
 409         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 410         unsigned int ecc_isr;
 411         bool stop = false;
 412
 413         /* Mask status with only the interrupts we care about */
 414         ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
 415         ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
 416         netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
 417
 418         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
 419                 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
 420                                      &pdata->tx_ded_count, "TX fifo");
 421         }
 422
 423         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
 424                 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
 425                                      &pdata->rx_ded_count, "RX fifo");
 426         }
 427
 428         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
 429                 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
 430                                      &pdata->desc_ded_count,
 431                                      "descriptor cache");
 432         }
 433
 434         if (stop) {
 435                 pdata->hw_if.disable_ecc_ded(pdata);
 436                 schedule_work(&pdata->stopdev_work);
 437                 goto out;
 438         }
 439
 440         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
 441                 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
 442                                  &pdata->tx_sec_count, "TX fifo"))
 443                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
 444         }
 445
 446         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
 447                 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
 448                                  &pdata->rx_sec_count, "RX fifo"))
 449                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
 450
 451         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
 452                 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
 453                                  &pdata->desc_sec_count, "descriptor cache"))
 454                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
 455
 456 out:
 457         /* Clear all ECC interrupts */
 458         XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
 459
 460         /* Reissue interrupt if status is not clear */
 461         if (pdata->vdata->irq_reissue_support)
 462                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
 463 }
 464
 465 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
 466 {
 467         struct xgbe_prv_data *pdata = data;
 468
 469         if (pdata->isr_as_tasklet)
 470                 tasklet_schedule(&pdata->tasklet_ecc);
 471         else
 472                 xgbe_ecc_isr_task((unsigned long)pdata);
 473
 474         return IRQ_HANDLED;
 475 }
 476
 477 static void xgbe_isr_task(unsigned long data)
 478 {
 479         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 480         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 481         struct xgbe_channel *channel;
 482         unsigned int dma_isr, dma_ch_isr;
 483         unsigned int mac_isr, mac_tssr, mac_mdioisr;
 484         unsigned int i;
 485
 486         /* The DMA interrupt status register also reports MAC and MTL
 487          * interrupts. So for polling mode, we just need to check for
 488          * this register to be non-zero
 489          */
 490         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 491         if (!dma_isr)
 492                 goto isr_done;
 493
 494         netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
 495
 496         for (i = 0; i < pdata->channel_count; i++) {
 497                 if (!(dma_isr & (1 << i)))
 498                         continue;
 499
 500                 channel = pdata->channel[i];
 501
 502                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 503                 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
 504                           i, dma_ch_isr);
 505
 506                 /* The TI or RI interrupt bits may still be set even if using
 507                  * per channel DMA interrupts. Check to be sure those are not
 508                  * enabled before using the private data napi structure.
 509                  */
 510                 if (!pdata->per_channel_irq &&
 511                     (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 512                      XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
 513                         if (napi_schedule_prep(&pdata->napi)) {
 514                                 /* Disable Tx and Rx interrupts */
 515                                 xgbe_disable_rx_tx_ints(pdata);
 516
 517                                 /* Turn on polling */
 518                                 __napi_schedule(&pdata->napi);
 519                         }
 520                 } else {
 521                         /* Don't clear Rx/Tx status if doing per channel DMA
 522                          * interrupts, these will be cleared by the ISR for
 523                          * per channel DMA interrupts.
 524                          */
 525                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
 526                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
 527                 }
 528
 529                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
 530                         pdata->ext_stats.rx_buffer_unavailable++;
 531
 532                 /* Restart the device on a Fatal Bus Error */
 533                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 534                         schedule_work(&pdata->restart_work);
 535
 536                 /* Clear interrupt signals */
 537                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 538         }
 539
 540         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 541                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 542
 543                 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
 544                           mac_isr);
 545
 546                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 547                         hw_if->tx_mmc_int(pdata);
 548
 549                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 550                         hw_if->rx_mmc_int(pdata);
 551
 552                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 553                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 554
 555                         netif_dbg(pdata, intr, pdata->netdev,
 556                                   "MAC_TSSR=%#010x\n", mac_tssr);
 557
 558                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 559                                 /* Read Tx Timestamp to clear interrupt */
 560                                 pdata->tx_tstamp =
 561                                         hw_if->get_tx_tstamp(pdata);
 562                                 queue_work(pdata->dev_workqueue,
 563                                            &pdata->tx_tstamp_work);
 564                         }
 565                 }
 566
 567                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
 568                         mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
 569
 570                         netif_dbg(pdata, intr, pdata->netdev,
 571                                   "MAC_MDIOISR=%#010x\n", mac_mdioisr);
 572
 573                         if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
 574                                            SNGLCOMPINT))
 575                                 complete(&pdata->mdio_complete);
 576                 }
 577         }
 578
 579 isr_done:
 580         /* If there is not a separate AN irq, handle it here */
 581         if (pdata->dev_irq == pdata->an_irq)
 582                 pdata->phy_if.an_isr(pdata);
 583
 584         /* If there is not a separate ECC irq, handle it here */
 585         if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
 586                 xgbe_ecc_isr_task((unsigned long)pdata);
 587
 588         /* If there is not a separate I2C irq, handle it here */
 589         if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
 590                 pdata->i2c_if.i2c_isr(pdata);
 591
 592         /* Reissue interrupt if status is not clear */
 593         if (pdata->vdata->irq_reissue_support) {
 594                 unsigned int reissue_mask;
 595
 596                 reissue_mask = 1 << 0;
 597                 if (!pdata->per_channel_irq)
 598                         reissue_mask |= 0xffff << 4;
 599
 600                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
 601         }
 602 }
 603
 604 static irqreturn_t xgbe_isr(int irq, void *data)
 605 {
 606         struct xgbe_prv_data *pdata = data;
 607
 608         if (pdata->isr_as_tasklet)
 609                 tasklet_schedule(&pdata->tasklet_dev);
 610         else
 611                 xgbe_isr_task((unsigned long)pdata);
 612
 613         return IRQ_HANDLED;
 614 }
 615
 616 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 617 {
 618         struct xgbe_channel *channel = data;
 619         struct xgbe_prv_data *pdata = channel->pdata;
 620         unsigned int dma_status;
 621
 622         /* Per channel DMA interrupts are enabled, so we use the per
 623          * channel napi structure and not the private data napi structure
 624          */
 625         if (napi_schedule_prep(&channel->napi)) {
 626                 /* Disable Tx and Rx interrupts */
 627                 if (pdata->channel_irq_mode)
 628                         xgbe_disable_rx_tx_int(pdata, channel);
 629                 else
 630                         disable_irq_nosync(channel->dma_irq);
 631
 632                 /* Turn on polling */
 633                 __napi_schedule_irqoff(&channel->napi);
 634         }
 635
 636         /* Clear Tx/Rx signals */
 637         dma_status = 0;
 638         XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
 639         XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
 640         XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
 641
 642         return IRQ_HANDLED;
 643 }
 644
 645 static void xgbe_tx_timer(unsigned long data)
 646 {
 647         struct xgbe_channel *channel = (struct xgbe_channel *)data;
 648         struct xgbe_prv_data *pdata = channel->pdata;
 649         struct napi_struct *napi;
 650
 651         DBGPR("-->xgbe_tx_timer\n");
 652
 653         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 654
 655         if (napi_schedule_prep(napi)) {
 656                 /* Disable Tx and Rx interrupts */
 657                 if (pdata->per_channel_irq)
 658                         if (pdata->channel_irq_mode)
 659                                 xgbe_disable_rx_tx_int(pdata, channel);
 660                         else
 661                                 disable_irq_nosync(channel->dma_irq);
 662                 else
 663                         xgbe_disable_rx_tx_ints(pdata);
 664
 665                 /* Turn on polling */
 666                 __napi_schedule(napi);
 667         }
 668
 669         channel->tx_timer_active = 0;
 670
 671         DBGPR("<--xgbe_tx_timer\n");
 672 }
 673
 674 static void xgbe_service(struct work_struct *work)
 675 {
 676         struct xgbe_prv_data *pdata = container_of(work,
 677                                                    struct xgbe_prv_data,
 678                                                    service_work);
 679
 680         pdata->phy_if.phy_status(pdata);
 681 }
 682
 683 static void xgbe_service_timer(unsigned long data)
 684 {
 685         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 686
 687         queue_work(pdata->dev_workqueue, &pdata->service_work);
 688
 689         mod_timer(&pdata->service_timer, jiffies + HZ);
 690 }
 691
 692 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
 693 {
 694         struct xgbe_channel *channel;
 695         unsigned int i;
 696
 697         setup_timer(&pdata->service_timer, xgbe_service_timer,
 698                     (unsigned long)pdata);
 699
 700         for (i = 0; i < pdata->channel_count; i++) {
 701                 channel = pdata->channel[i];
 702                 if (!channel->tx_ring)
 703                         break;
 704
 705                 setup_timer(&channel->tx_timer, xgbe_tx_timer,
 706                             (unsigned long)channel);
 707         }
 708 }
 709
 710 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
 711 {
 712         mod_timer(&pdata->service_timer, jiffies + HZ);
 713 }
 714
 715 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
 716 {
 717         struct xgbe_channel *channel;
 718         unsigned int i;
 719
 720         del_timer_sync(&pdata->service_timer);
 721
 722         for (i = 0; i < pdata->channel_count; i++) {
 723                 channel = pdata->channel[i];
 724                 if (!channel->tx_ring)
 725                         break;
 726
 727                 /* Deactivate the Tx timer */
 728                 del_timer_sync(&channel->tx_timer);
 729                 channel->tx_timer_active = 0;
 730         }
 731 }
 732
 733 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 734 {
 735         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 736         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 737
 738         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 739         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 740         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 741
 742         memset(hw_feat, 0, sizeof(*hw_feat));
 743
 744         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 745
 746         /* Hardware feature register 0 */
 747         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 748         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 749         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 750         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 751         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 752         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 753         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 754         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 755         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 756         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 757         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 758         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 759                                               ADDMACADRSEL);
 760         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 761         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 762         hw_feat->vxn         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
 763
 764         /* Hardware feature register 1 */
 765         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 766                                                 RXFIFOSIZE);
 767         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 768                                                 TXFIFOSIZE);
 769         hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
 770         hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
 771         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 772         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 773         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 774         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 775         hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
 776         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 777         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 778                                                   HASHTBLSZ);
 779         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 780                                                   L3L4FNUM);
 781
 782         /* Hardware feature register 2 */
 783         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 784         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 785         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 786         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 787         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 788         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 789
 790         /* Translate the Hash Table size into actual number */
 791         switch (hw_feat->hash_table_size) {
 792         case 0:
 793                 break;
 794         case 1:
 795                 hw_feat->hash_table_size = 64;
 796                 break;
 797         case 2:
 798                 hw_feat->hash_table_size = 128;
 799                 break;
 800         case 3:
 801                 hw_feat->hash_table_size = 256;
 802                 break;
 803         }
 804
 805         /* Translate the address width setting into actual number */
 806         switch (hw_feat->dma_width) {
 807         case 0:
 808                 hw_feat->dma_width = 32;
 809                 break;
 810         case 1:
 811                 hw_feat->dma_width = 40;
 812                 break;
 813         case 2:
 814                 hw_feat->dma_width = 48;
 815                 break;
 816         default:
 817                 hw_feat->dma_width = 32;
 818         }
 819
 820         /* The Queue, Channel and TC counts are zero based so increment them
 821          * to get the actual number
 822          */
 823         hw_feat->rx_q_cnt++;
 824         hw_feat->tx_q_cnt++;
 825         hw_feat->rx_ch_cnt++;
 826         hw_feat->tx_ch_cnt++;
 827         hw_feat->tc_cnt++;
 828
 829         /* Translate the fifo sizes into actual numbers */
 830         hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
 831         hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
 832
 833         if (netif_msg_probe(pdata)) {
 834                 dev_dbg(pdata->dev, "Hardware features:\n");
 835
 836                 /* Hardware feature register 0 */
 837                 dev_dbg(pdata->dev, "  1GbE support              : %s\n",
 838                         hw_feat->gmii ? "yes" : "no");
 839                 dev_dbg(pdata->dev, "  VLAN hash filter          : %s\n",
 840                         hw_feat->vlhash ? "yes" : "no");
 841                 dev_dbg(pdata->dev, "  MDIO interface            : %s\n",
 842                         hw_feat->sma ? "yes" : "no");
 843                 dev_dbg(pdata->dev, "  Wake-up packet support    : %s\n",
 844                         hw_feat->rwk ? "yes" : "no");
 845                 dev_dbg(pdata->dev, "  Magic packet support      : %s\n",
 846                         hw_feat->mgk ? "yes" : "no");
 847                 dev_dbg(pdata->dev, "  Management counters       : %s\n",
 848                         hw_feat->mmc ? "yes" : "no");
 849                 dev_dbg(pdata->dev, "  ARP offload               : %s\n",
 850                         hw_feat->aoe ? "yes" : "no");
 851                 dev_dbg(pdata->dev, "  IEEE 1588-2008 Timestamp  : %s\n",
 852                         hw_feat->ts ? "yes" : "no");
 853                 dev_dbg(pdata->dev, "  Energy Efficient Ethernet : %s\n",
 854                         hw_feat->eee ? "yes" : "no");
 855                 dev_dbg(pdata->dev, "  TX checksum offload       : %s\n",
 856                         hw_feat->tx_coe ? "yes" : "no");
 857                 dev_dbg(pdata->dev, "  RX checksum offload       : %s\n",
 858                         hw_feat->rx_coe ? "yes" : "no");
 859                 dev_dbg(pdata->dev, "  Additional MAC addresses  : %u\n",
 860                         hw_feat->addn_mac);
 861                 dev_dbg(pdata->dev, "  Timestamp source          : %s\n",
 862                         (hw_feat->ts_src == 1) ? "internal" :
 863                         (hw_feat->ts_src == 2) ? "external" :
 864                         (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
 865                 dev_dbg(pdata->dev, "  SA/VLAN insertion         : %s\n",
 866                         hw_feat->sa_vlan_ins ? "yes" : "no");
 867                 dev_dbg(pdata->dev, "  VXLAN/NVGRE support       : %s\n",
 868                         hw_feat->vxn ? "yes" : "no");
 869
 870                 /* Hardware feature register 1 */
 871                 dev_dbg(pdata->dev, "  RX fifo size              : %u\n",
 872                         hw_feat->rx_fifo_size);
 873                 dev_dbg(pdata->dev, "  TX fifo size              : %u\n",
 874                         hw_feat->tx_fifo_size);
 875                 dev_dbg(pdata->dev, "  IEEE 1588 high word       : %s\n",
 876                         hw_feat->adv_ts_hi ? "yes" : "no");
 877                 dev_dbg(pdata->dev, "  DMA width                 : %u\n",
 878                         hw_feat->dma_width);
 879                 dev_dbg(pdata->dev, "  Data Center Bridging      : %s\n",
 880                         hw_feat->dcb ? "yes" : "no");
 881                 dev_dbg(pdata->dev, "  Split header              : %s\n",
 882                         hw_feat->sph ? "yes" : "no");
 883                 dev_dbg(pdata->dev, "  TCP Segmentation Offload  : %s\n",
 884                         hw_feat->tso ? "yes" : "no");
 885                 dev_dbg(pdata->dev, "  Debug memory interface    : %s\n",
 886                         hw_feat->dma_debug ? "yes" : "no");
 887                 dev_dbg(pdata->dev, "  Receive Side Scaling      : %s\n",
 888                         hw_feat->rss ? "yes" : "no");
 889                 dev_dbg(pdata->dev, "  Traffic Class count       : %u\n",
 890                         hw_feat->tc_cnt);
 891                 dev_dbg(pdata->dev, "  Hash table size           : %u\n",
 892                         hw_feat->hash_table_size);
 893                 dev_dbg(pdata->dev, "  L3/L4 Filters             : %u\n",
 894                         hw_feat->l3l4_filter_num);
 895
 896                 /* Hardware feature register 2 */
 897                 dev_dbg(pdata->dev, "  RX queue count            : %u\n",
 898                         hw_feat->rx_q_cnt);
 899                 dev_dbg(pdata->dev, "  TX queue count            : %u\n",
 900                         hw_feat->tx_q_cnt);
 901                 dev_dbg(pdata->dev, "  RX DMA channel count      : %u\n",
 902                         hw_feat->rx_ch_cnt);
 903                 dev_dbg(pdata->dev, "  TX DMA channel count      : %u\n",
 904                         hw_feat->rx_ch_cnt);
 905                 dev_dbg(pdata->dev, "  PPS outputs               : %u\n",
 906                         hw_feat->pps_out_num);
 907                 dev_dbg(pdata->dev, "  Auxiliary snapshot inputs : %u\n",
 908                         hw_feat->aux_snap_num);
 909         }
 910 }
 911
 912 static void xgbe_disable_vxlan_offloads(struct xgbe_prv_data *pdata)
 913 {
 914         struct net_device *netdev = pdata->netdev;
 915
 916         if (!pdata->vxlan_offloads_set)
 917                 return;
 918
 919         netdev_info(netdev, "disabling VXLAN offloads\n");
 920
 921         netdev->hw_enc_features &= ~(NETIF_F_SG |
 922                                      NETIF_F_IP_CSUM |
 923                                      NETIF_F_IPV6_CSUM |
 924                                      NETIF_F_RXCSUM |
 925                                      NETIF_F_TSO |
 926                                      NETIF_F_TSO6 |
 927                                      NETIF_F_GRO |
 928                                      NETIF_F_GSO_UDP_TUNNEL |
 929                                      NETIF_F_GSO_UDP_TUNNEL_CSUM);
 930
 931         netdev->features &= ~(NETIF_F_GSO_UDP_TUNNEL |
 932                               NETIF_F_GSO_UDP_TUNNEL_CSUM);
 933
 934         pdata->vxlan_offloads_set = 0;
 935 }
 936
 937 static void xgbe_disable_vxlan_hw(struct xgbe_prv_data *pdata)
 938 {
 939         if (!pdata->vxlan_port_set)
 940                 return;
 941
 942         pdata->hw_if.disable_vxlan(pdata);
 943
 944         pdata->vxlan_port_set = 0;
 945         pdata->vxlan_port = 0;
 946 }
 947
 948 static void xgbe_disable_vxlan_accel(struct xgbe_prv_data *pdata)
 949 {
 950         xgbe_disable_vxlan_offloads(pdata);
 951
 952         xgbe_disable_vxlan_hw(pdata);
 953 }
 954
 955 static void xgbe_enable_vxlan_offloads(struct xgbe_prv_data *pdata)
 956 {
 957         struct net_device *netdev = pdata->netdev;
 958
 959         if (pdata->vxlan_offloads_set)
 960                 return;
 961
 962         netdev_info(netdev, "enabling VXLAN offloads\n");
 963
 964         netdev->hw_enc_features |= NETIF_F_SG |
 965                                    NETIF_F_IP_CSUM |
 966                                    NETIF_F_IPV6_CSUM |
 967                                    NETIF_F_RXCSUM |
 968                                    NETIF_F_TSO |
 969                                    NETIF_F_TSO6 |
 970                                    NETIF_F_GRO |
 971                                    pdata->vxlan_features;
 972
 973         netdev->features |= pdata->vxlan_features;
 974
 975         pdata->vxlan_offloads_set = 1;
 976 }
 977
 978 static void xgbe_enable_vxlan_hw(struct xgbe_prv_data *pdata)
 979 {
 980         struct xgbe_vxlan_data *vdata;
 981
 982         if (pdata->vxlan_port_set)
 983                 return;
 984
 985         if (list_empty(&pdata->vxlan_ports))
 986                 return;
 987
 988         vdata = list_first_entry(&pdata->vxlan_ports,
 989                                  struct xgbe_vxlan_data, list);
 990
 991         pdata->vxlan_port_set = 1;
 992         pdata->vxlan_port = be16_to_cpu(vdata->port);
 993
 994         pdata->hw_if.enable_vxlan(pdata);
 995 }
 996
 997 static void xgbe_enable_vxlan_accel(struct xgbe_prv_data *pdata)
 998 {
 999         /* VXLAN acceleration desired? */
1000         if (!pdata->vxlan_features)
1001                 return;
1002
1003         /* VXLAN acceleration possible? */
1004         if (pdata->vxlan_force_disable)
1005                 return;
1006
1007         xgbe_enable_vxlan_hw(pdata);
1008
1009         xgbe_enable_vxlan_offloads(pdata);
1010 }
1011
1012 static void xgbe_reset_vxlan_accel(struct xgbe_prv_data *pdata)
1013 {
1014         xgbe_disable_vxlan_hw(pdata);
1015
1016         if (pdata->vxlan_features)
1017                 xgbe_enable_vxlan_offloads(pdata);
1018
1019         pdata->vxlan_force_disable = 0;
1020 }
1021
1022 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
1023 {
1024         struct xgbe_channel *channel;
1025         unsigned int i;
1026
1027         if (pdata->per_channel_irq) {
1028                 for (i = 0; i < pdata->channel_count; i++) {
1029                         channel = pdata->channel[i];
1030                         if (add)
1031                                 netif_napi_add(pdata->netdev, &channel->napi,
1032                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
1033
1034                         napi_enable(&channel->napi);
1035                 }
1036         } else {
1037                 if (add)
1038                         netif_napi_add(pdata->netdev, &pdata->napi,
1039                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
1040
1041                 napi_enable(&pdata->napi);
1042         }
1043 }
1044
1045 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
1046 {
1047         struct xgbe_channel *channel;
1048         unsigned int i;
1049
1050         if (pdata->per_channel_irq) {
1051                 for (i = 0; i < pdata->channel_count; i++) {
1052                         channel = pdata->channel[i];
1053                         napi_disable(&channel->napi);
1054
1055                         if (del)
1056                                 netif_napi_del(&channel->napi);
1057                 }
1058         } else {
1059                 napi_disable(&pdata->napi);
1060
1061                 if (del)
1062                         netif_napi_del(&pdata->napi);
1063         }
1064 }
1065
1066 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1067 {
1068         struct xgbe_channel *channel;
1069         struct net_device *netdev = pdata->netdev;
1070         unsigned int i;
1071         int ret;
1072
1073         tasklet_init(&pdata->tasklet_dev, xgbe_isr_task, (unsigned long)pdata);
1074         tasklet_init(&pdata->tasklet_ecc, xgbe_ecc_isr_task,
1075                      (unsigned long)pdata);
1076
1077         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1078                                netdev_name(netdev), pdata);
1079         if (ret) {
1080                 netdev_alert(netdev, "error requesting irq %d\n",
1081                              pdata->dev_irq);
1082                 return ret;
1083         }
1084
1085         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1086                 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1087                                        0, pdata->ecc_name, pdata);
1088                 if (ret) {
1089                         netdev_alert(netdev, "error requesting ecc irq %d\n",
1090                                      pdata->ecc_irq);
1091                         goto err_dev_irq;
1092                 }
1093         }
1094
1095         if (!pdata->per_channel_irq)
1096                 return 0;
1097
1098         for (i = 0; i < pdata->channel_count; i++) {
1099                 channel = pdata->channel[i];
1100                 snprintf(channel->dma_irq_name,
1101                          sizeof(channel->dma_irq_name) - 1,
1102                          "%s-TxRx-%u", netdev_name(netdev),
1103                          channel->queue_index);
1104
1105                 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1106                                        xgbe_dma_isr, 0,
1107                                        channel->dma_irq_name, channel);
1108                 if (ret) {
1109                         netdev_alert(netdev, "error requesting irq %d\n",
1110                                      channel->dma_irq);
1111                         goto err_dma_irq;
1112                 }
1113
1114                 irq_set_affinity_hint(channel->dma_irq,
1115                                       &channel->affinity_mask);
1116         }
1117
1118         return 0;
1119
1120 err_dma_irq:
1121         /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1122         for (i--; i < pdata->channel_count; i--) {
1123                 channel = pdata->channel[i];
1124
1125                 irq_set_affinity_hint(channel->dma_irq, NULL);
1126                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1127         }
1128
1129         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1130                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1131
1132 err_dev_irq:
1133         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1134
1135         return ret;
1136 }
1137
1138 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1139 {
1140         struct xgbe_channel *channel;
1141         unsigned int i;
1142
1143         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1144
1145         tasklet_kill(&pdata->tasklet_dev);
1146         tasklet_kill(&pdata->tasklet_ecc);
1147
1148         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1149                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1150
1151         if (!pdata->per_channel_irq)
1152                 return;
1153
1154         for (i = 0; i < pdata->channel_count; i++) {
1155                 channel = pdata->channel[i];
1156
1157                 irq_set_affinity_hint(channel->dma_irq, NULL);
1158                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1159         }
1160 }
1161
1162 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1163 {
1164         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1165
1166         DBGPR("-->xgbe_init_tx_coalesce\n");
1167
1168         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1169         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1170
1171         hw_if->config_tx_coalesce(pdata);
1172
1173         DBGPR("<--xgbe_init_tx_coalesce\n");
1174 }
1175
1176 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1177 {
1178         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1179
1180         DBGPR("-->xgbe_init_rx_coalesce\n");
1181
1182         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1183         pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1184         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1185
1186         hw_if->config_rx_coalesce(pdata);
1187
1188         DBGPR("<--xgbe_init_rx_coalesce\n");
1189 }
1190
1191 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1192 {
1193         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1194         struct xgbe_ring *ring;
1195         struct xgbe_ring_data *rdata;
1196         unsigned int i, j;
1197
1198         DBGPR("-->xgbe_free_tx_data\n");
1199
1200         for (i = 0; i < pdata->channel_count; i++) {
1201                 ring = pdata->channel[i]->tx_ring;
1202                 if (!ring)
1203                         break;
1204
1205                 for (j = 0; j < ring->rdesc_count; j++) {
1206                         rdata = XGBE_GET_DESC_DATA(ring, j);
1207                         desc_if->unmap_rdata(pdata, rdata);
1208                 }
1209         }
1210
1211         DBGPR("<--xgbe_free_tx_data\n");
1212 }
1213
1214 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1215 {
1216         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1217         struct xgbe_ring *ring;
1218         struct xgbe_ring_data *rdata;
1219         unsigned int i, j;
1220
1221         DBGPR("-->xgbe_free_rx_data\n");
1222
1223         for (i = 0; i < pdata->channel_count; i++) {
1224                 ring = pdata->channel[i]->rx_ring;
1225                 if (!ring)
1226                         break;
1227
1228                 for (j = 0; j < ring->rdesc_count; j++) {
1229                         rdata = XGBE_GET_DESC_DATA(ring, j);
1230                         desc_if->unmap_rdata(pdata, rdata);
1231                 }
1232         }
1233
1234         DBGPR("<--xgbe_free_rx_data\n");
1235 }
1236
1237 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1238 {
1239         pdata->phy_link = -1;
1240         pdata->phy_speed = SPEED_UNKNOWN;
1241
1242         return pdata->phy_if.phy_reset(pdata);
1243 }
1244
1245 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1246 {
1247         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1248         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1249         unsigned long flags;
1250
1251         DBGPR("-->xgbe_powerdown\n");
1252
1253         if (!netif_running(netdev) ||
1254             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1255                 netdev_alert(netdev, "Device is already powered down\n");
1256                 DBGPR("<--xgbe_powerdown\n");
1257                 return -EINVAL;
1258         }
1259
1260         spin_lock_irqsave(&pdata->lock, flags);
1261
1262         if (caller == XGMAC_DRIVER_CONTEXT)
1263                 netif_device_detach(netdev);
1264
1265         netif_tx_stop_all_queues(netdev);
1266
1267         xgbe_stop_timers(pdata);
1268         flush_workqueue(pdata->dev_workqueue);
1269
1270         hw_if->powerdown_tx(pdata);
1271         hw_if->powerdown_rx(pdata);
1272
1273         xgbe_napi_disable(pdata, 0);
1274
1275         pdata->power_down = 1;
1276
1277         spin_unlock_irqrestore(&pdata->lock, flags);
1278
1279         DBGPR("<--xgbe_powerdown\n");
1280
1281         return 0;
1282 }
1283
1284 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1285 {
1286         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1287         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1288         unsigned long flags;
1289
1290         DBGPR("-->xgbe_powerup\n");
1291
1292         if (!netif_running(netdev) ||
1293             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1294                 netdev_alert(netdev, "Device is already powered up\n");
1295                 DBGPR("<--xgbe_powerup\n");
1296                 return -EINVAL;
1297         }
1298
1299         spin_lock_irqsave(&pdata->lock, flags);
1300
1301         pdata->power_down = 0;
1302
1303         xgbe_napi_enable(pdata, 0);
1304
1305         hw_if->powerup_tx(pdata);
1306         hw_if->powerup_rx(pdata);
1307
1308         if (caller == XGMAC_DRIVER_CONTEXT)
1309                 netif_device_attach(netdev);
1310
1311         netif_tx_start_all_queues(netdev);
1312
1313         xgbe_start_timers(pdata);
1314
1315         spin_unlock_irqrestore(&pdata->lock, flags);
1316
1317         DBGPR("<--xgbe_powerup\n");
1318
1319         return 0;
1320 }
1321
1322 static int xgbe_start(struct xgbe_prv_data *pdata)
1323 {
1324         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1325         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1326         struct net_device *netdev = pdata->netdev;
1327         int ret;
1328
1329         DBGPR("-->xgbe_start\n");
1330
1331         ret = hw_if->init(pdata);
1332         if (ret)
1333                 return ret;
1334
1335         xgbe_napi_enable(pdata, 1);
1336
1337         ret = xgbe_request_irqs(pdata);
1338         if (ret)
1339                 goto err_napi;
1340
1341         ret = phy_if->phy_start(pdata);
1342         if (ret)
1343                 goto err_irqs;
1344
1345         hw_if->enable_tx(pdata);
1346         hw_if->enable_rx(pdata);
1347
1348         udp_tunnel_get_rx_info(netdev);
1349
1350         netif_tx_start_all_queues(netdev);
1351
1352         xgbe_start_timers(pdata);
1353         queue_work(pdata->dev_workqueue, &pdata->service_work);
1354
1355         clear_bit(XGBE_STOPPED, &pdata->dev_state);
1356
1357         DBGPR("<--xgbe_start\n");
1358
1359         return 0;
1360
1361 err_irqs:
1362         xgbe_free_irqs(pdata);
1363
1364 err_napi:
1365         xgbe_napi_disable(pdata, 1);
1366
1367         hw_if->exit(pdata);
1368
1369         return ret;
1370 }
1371
1372 static void xgbe_stop(struct xgbe_prv_data *pdata)
1373 {
1374         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1375         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1376         struct xgbe_channel *channel;
1377         struct net_device *netdev = pdata->netdev;
1378         struct netdev_queue *txq;
1379         unsigned int i;
1380
1381         DBGPR("-->xgbe_stop\n");
1382
1383         if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1384                 return;
1385
1386         netif_tx_stop_all_queues(netdev);
1387
1388         xgbe_stop_timers(pdata);
1389         flush_workqueue(pdata->dev_workqueue);
1390
1391         xgbe_reset_vxlan_accel(pdata);
1392
1393         hw_if->disable_tx(pdata);
1394         hw_if->disable_rx(pdata);
1395
1396         phy_if->phy_stop(pdata);
1397
1398         xgbe_free_irqs(pdata);
1399
1400         xgbe_napi_disable(pdata, 1);
1401
1402         hw_if->exit(pdata);
1403
1404         for (i = 0; i < pdata->channel_count; i++) {
1405                 channel = pdata->channel[i];
1406                 if (!channel->tx_ring)
1407                         continue;
1408
1409                 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1410                 netdev_tx_reset_queue(txq);
1411         }
1412
1413         set_bit(XGBE_STOPPED, &pdata->dev_state);
1414
1415         DBGPR("<--xgbe_stop\n");
1416 }
1417
1418 static void xgbe_stopdev(struct work_struct *work)
1419 {
1420         struct xgbe_prv_data *pdata = container_of(work,
1421                                                    struct xgbe_prv_data,
1422                                                    stopdev_work);
1423
1424         rtnl_lock();
1425
1426         xgbe_stop(pdata);
1427
1428         xgbe_free_tx_data(pdata);
1429         xgbe_free_rx_data(pdata);
1430
1431         rtnl_unlock();
1432
1433         netdev_alert(pdata->netdev, "device stopped\n");
1434 }
1435
1436 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1437 {
1438         DBGPR("-->xgbe_restart_dev\n");
1439
1440         /* If not running, "restart" will happen on open */
1441         if (!netif_running(pdata->netdev))
1442                 return;
1443
1444         xgbe_stop(pdata);
1445
1446         xgbe_free_tx_data(pdata);
1447         xgbe_free_rx_data(pdata);
1448
1449         xgbe_start(pdata);
1450
1451         DBGPR("<--xgbe_restart_dev\n");
1452 }
1453
1454 static void xgbe_restart(struct work_struct *work)
1455 {
1456         struct xgbe_prv_data *pdata = container_of(work,
1457                                                    struct xgbe_prv_data,
1458                                                    restart_work);
1459
1460         rtnl_lock();
1461
1462         xgbe_restart_dev(pdata);
1463
1464         rtnl_unlock();
1465 }
1466
1467 static void xgbe_tx_tstamp(struct work_struct *work)
1468 {
1469         struct xgbe_prv_data *pdata = container_of(work,
1470                                                    struct xgbe_prv_data,
1471                                                    tx_tstamp_work);
1472         struct skb_shared_hwtstamps hwtstamps;
1473         u64 nsec;
1474         unsigned long flags;
1475
1476         spin_lock_irqsave(&pdata->tstamp_lock, flags);
1477         if (!pdata->tx_tstamp_skb)
1478                 goto unlock;
1479
1480         if (pdata->tx_tstamp) {
1481                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1482                                             pdata->tx_tstamp);
1483
1484                 memset(&hwtstamps, 0, sizeof(hwtstamps));
1485                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1486                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1487         }
1488
1489         dev_kfree_skb_any(pdata->tx_tstamp_skb);
1490
1491         pdata->tx_tstamp_skb = NULL;
1492
1493 unlock:
1494         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1495 }
1496
1497 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1498                                       struct ifreq *ifreq)
1499 {
1500         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1501                          sizeof(pdata->tstamp_config)))
1502                 return -EFAULT;
1503
1504         return 0;
1505 }
1506
1507 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1508                                       struct ifreq *ifreq)
1509 {
1510         struct hwtstamp_config config;
1511         unsigned int mac_tscr;
1512
1513         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1514                 return -EFAULT;
1515
1516         if (config.flags)
1517                 return -EINVAL;
1518
1519         mac_tscr = 0;
1520
1521         switch (config.tx_type) {
1522         case HWTSTAMP_TX_OFF:
1523                 break;
1524
1525         case HWTSTAMP_TX_ON:
1526                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1527                 break;
1528
1529         default:
1530                 return -ERANGE;
1531         }
1532
1533         switch (config.rx_filter) {
1534         case HWTSTAMP_FILTER_NONE:
1535                 break;
1536
1537         case HWTSTAMP_FILTER_NTP_ALL:
1538         case HWTSTAMP_FILTER_ALL:
1539                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1540                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1541                 break;
1542
1543         /* PTP v2, UDP, any kind of event packet */
1544         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1545                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1546         /* PTP v1, UDP, any kind of event packet */
1547         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1548                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1549                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1550                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1551                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1552                 break;
1553
1554         /* PTP v2, UDP, Sync packet */
1555         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1556                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1557         /* PTP v1, UDP, Sync packet */
1558         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1559                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1560                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1561                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1562                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1563                 break;
1564
1565         /* PTP v2, UDP, Delay_req packet */
1566         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1567                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1568         /* PTP v1, UDP, Delay_req packet */
1569         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1570                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1571                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1572                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1573                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1574                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1575                 break;
1576
1577         /* 802.AS1, Ethernet, any kind of event packet */
1578         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1579                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1580                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1581                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1582                 break;
1583
1584         /* 802.AS1, Ethernet, Sync packet */
1585         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1586                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1587                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1588                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1589                 break;
1590
1591         /* 802.AS1, Ethernet, Delay_req packet */
1592         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1593                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1594                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1595                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1596                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1597                 break;
1598
1599         /* PTP v2/802.AS1, any layer, any kind of event packet */
1600         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1601                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1602                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1603                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1604                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1605                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1606                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1607                 break;
1608
1609         /* PTP v2/802.AS1, any layer, Sync packet */
1610         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1611                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1612                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1613                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1614                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1615                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1616                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1617                 break;
1618
1619         /* PTP v2/802.AS1, any layer, Delay_req packet */
1620         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1621                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1622                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1623                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1624                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1625                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1626                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1627                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1628                 break;
1629
1630         default:
1631                 return -ERANGE;
1632         }
1633
1634         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1635
1636         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1637
1638         return 0;
1639 }
1640
1641 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1642                                 struct sk_buff *skb,
1643                                 struct xgbe_packet_data *packet)
1644 {
1645         unsigned long flags;
1646
1647         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1648                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1649                 if (pdata->tx_tstamp_skb) {
1650                         /* Another timestamp in progress, ignore this one */
1651                         XGMAC_SET_BITS(packet->attributes,
1652                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1653                 } else {
1654                         pdata->tx_tstamp_skb = skb_get(skb);
1655                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1656                 }
1657                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1658         }
1659
1660         skb_tx_timestamp(skb);
1661 }
1662
1663 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1664 {
1665         if (skb_vlan_tag_present(skb))
1666                 packet->vlan_ctag = skb_vlan_tag_get(skb);
1667 }
1668
1669 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1670 {
1671         int ret;
1672
1673         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1674                             TSO_ENABLE))
1675                 return 0;
1676
1677         ret = skb_cow_head(skb, 0);
1678         if (ret)
1679                 return ret;
1680
1681         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1682                 packet->header_len = skb_inner_transport_offset(skb) +
1683                                      inner_tcp_hdrlen(skb);
1684                 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1685         } else {
1686                 packet->header_len = skb_transport_offset(skb) +
1687                                      tcp_hdrlen(skb);
1688                 packet->tcp_header_len = tcp_hdrlen(skb);
1689         }
1690         packet->tcp_payload_len = skb->len - packet->header_len;
1691         packet->mss = skb_shinfo(skb)->gso_size;
1692
1693         DBGPR("  packet->header_len=%u\n", packet->header_len);
1694         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1695               packet->tcp_header_len, packet->tcp_payload_len);
1696         DBGPR("  packet->mss=%u\n", packet->mss);
1697
1698         /* Update the number of packets that will ultimately be transmitted
1699          * along with the extra bytes for each extra packet
1700          */
1701         packet->tx_packets = skb_shinfo(skb)->gso_segs;
1702         packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1703
1704         return 0;
1705 }
1706
1707 static bool xgbe_is_vxlan(struct xgbe_prv_data *pdata, struct sk_buff *skb)
1708 {
1709         struct xgbe_vxlan_data *vdata;
1710
1711         if (pdata->vxlan_force_disable)
1712                 return false;
1713
1714         if (!skb->encapsulation)
1715                 return false;
1716
1717         if (skb->ip_summed != CHECKSUM_PARTIAL)
1718                 return false;
1719
1720         switch (skb->protocol) {
1721         case htons(ETH_P_IP):
1722                 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1723                         return false;
1724                 break;
1725
1726         case htons(ETH_P_IPV6):
1727                 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1728                         return false;
1729                 break;
1730
1731         default:
1732                 return false;
1733         }
1734
1735         /* See if we have the UDP port in our list */
1736         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
1737                 if ((skb->protocol == htons(ETH_P_IP)) &&
1738                     (vdata->sa_family == AF_INET) &&
1739                     (vdata->port == udp_hdr(skb)->dest))
1740                         return true;
1741                 else if ((skb->protocol == htons(ETH_P_IPV6)) &&
1742                          (vdata->sa_family == AF_INET6) &&
1743                          (vdata->port == udp_hdr(skb)->dest))
1744                         return true;
1745         }
1746
1747         return false;
1748 }
1749
1750 static int xgbe_is_tso(struct sk_buff *skb)
1751 {
1752         if (skb->ip_summed != CHECKSUM_PARTIAL)
1753                 return 0;
1754
1755         if (!skb_is_gso(skb))
1756                 return 0;
1757
1758         DBGPR("  TSO packet to be processed\n");
1759
1760         return 1;
1761 }
1762
1763 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1764                              struct xgbe_ring *ring, struct sk_buff *skb,
1765                              struct xgbe_packet_data *packet)
1766 {
1767         struct skb_frag_struct *frag;
1768         unsigned int context_desc;
1769         unsigned int len;
1770         unsigned int i;
1771
1772         packet->skb = skb;
1773
1774         context_desc = 0;
1775         packet->rdesc_count = 0;
1776
1777         packet->tx_packets = 1;
1778         packet->tx_bytes = skb->len;
1779
1780         if (xgbe_is_tso(skb)) {
1781                 /* TSO requires an extra descriptor if mss is different */
1782                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1783                         context_desc = 1;
1784                         packet->rdesc_count++;
1785                 }
1786
1787                 /* TSO requires an extra descriptor for TSO header */
1788                 packet->rdesc_count++;
1789
1790                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1791                                TSO_ENABLE, 1);
1792                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1793                                CSUM_ENABLE, 1);
1794         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1795                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1796                                CSUM_ENABLE, 1);
1797
1798         if (xgbe_is_vxlan(pdata, skb))
1799                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1800                                VXLAN, 1);
1801
1802         if (skb_vlan_tag_present(skb)) {
1803                 /* VLAN requires an extra descriptor if tag is different */
1804                 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1805                         /* We can share with the TSO context descriptor */
1806                         if (!context_desc) {
1807                                 context_desc = 1;
1808                                 packet->rdesc_count++;
1809                         }
1810
1811                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1812                                VLAN_CTAG, 1);
1813         }
1814
1815         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1816             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1817                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1818                                PTP, 1);
1819
1820         for (len = skb_headlen(skb); len;) {
1821                 packet->rdesc_count++;
1822                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1823         }
1824
1825         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1826                 frag = &skb_shinfo(skb)->frags[i];
1827                 for (len = skb_frag_size(frag); len; ) {
1828                         packet->rdesc_count++;
1829                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1830                 }
1831         }
1832 }
1833
1834 static int xgbe_open(struct net_device *netdev)
1835 {
1836         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1837         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1838         int ret;
1839
1840         DBGPR("-->xgbe_open\n");
1841
1842         /* Create the various names based on netdev name */
1843         snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1844                  netdev_name(netdev));
1845
1846         snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1847                  netdev_name(netdev));
1848
1849         snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1850                  netdev_name(netdev));
1851
1852         /* Create workqueues */
1853         pdata->dev_workqueue =
1854                 create_singlethread_workqueue(netdev_name(netdev));
1855         if (!pdata->dev_workqueue) {
1856                 netdev_err(netdev, "device workqueue creation failed\n");
1857                 return -ENOMEM;
1858         }
1859
1860         pdata->an_workqueue =
1861                 create_singlethread_workqueue(pdata->an_name);
1862         if (!pdata->an_workqueue) {
1863                 netdev_err(netdev, "phy workqueue creation failed\n");
1864                 ret = -ENOMEM;
1865                 goto err_dev_wq;
1866         }
1867
1868         /* Reset the phy settings */
1869         ret = xgbe_phy_reset(pdata);
1870         if (ret)
1871                 goto err_an_wq;
1872
1873         /* Enable the clocks */
1874         ret = clk_prepare_enable(pdata->sysclk);
1875         if (ret) {
1876                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1877                 goto err_an_wq;
1878         }
1879
1880         ret = clk_prepare_enable(pdata->ptpclk);
1881         if (ret) {
1882                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1883                 goto err_sysclk;
1884         }
1885
1886         /* Calculate the Rx buffer size before allocating rings */
1887         ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1888         if (ret < 0)
1889                 goto err_ptpclk;
1890         pdata->rx_buf_size = ret;
1891
1892         /* Allocate the channel and ring structures */
1893         ret = xgbe_alloc_channels(pdata);
1894         if (ret)
1895                 goto err_ptpclk;
1896
1897         /* Allocate the ring descriptors and buffers */
1898         ret = desc_if->alloc_ring_resources(pdata);
1899         if (ret)
1900                 goto err_channels;
1901
1902         INIT_WORK(&pdata->service_work, xgbe_service);
1903         INIT_WORK(&pdata->restart_work, xgbe_restart);
1904         INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1905         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1906         xgbe_init_timers(pdata);
1907
1908         ret = xgbe_start(pdata);
1909         if (ret)
1910                 goto err_rings;
1911
1912         clear_bit(XGBE_DOWN, &pdata->dev_state);
1913
1914         DBGPR("<--xgbe_open\n");
1915
1916         return 0;
1917
1918 err_rings:
1919         desc_if->free_ring_resources(pdata);
1920
1921 err_channels:
1922         xgbe_free_channels(pdata);
1923
1924 err_ptpclk:
1925         clk_disable_unprepare(pdata->ptpclk);
1926
1927 err_sysclk:
1928         clk_disable_unprepare(pdata->sysclk);
1929
1930 err_an_wq:
1931         destroy_workqueue(pdata->an_workqueue);
1932
1933 err_dev_wq:
1934         destroy_workqueue(pdata->dev_workqueue);
1935
1936         return ret;
1937 }
1938
1939 static int xgbe_close(struct net_device *netdev)
1940 {
1941         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1942         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1943
1944         DBGPR("-->xgbe_close\n");
1945
1946         /* Stop the device */
1947         xgbe_stop(pdata);
1948
1949         /* Free the ring descriptors and buffers */
1950         desc_if->free_ring_resources(pdata);
1951
1952         /* Free the channel and ring structures */
1953         xgbe_free_channels(pdata);
1954
1955         /* Disable the clocks */
1956         clk_disable_unprepare(pdata->ptpclk);
1957         clk_disable_unprepare(pdata->sysclk);
1958
1959         flush_workqueue(pdata->an_workqueue);
1960         destroy_workqueue(pdata->an_workqueue);
1961
1962         flush_workqueue(pdata->dev_workqueue);
1963         destroy_workqueue(pdata->dev_workqueue);
1964
1965         set_bit(XGBE_DOWN, &pdata->dev_state);
1966
1967         DBGPR("<--xgbe_close\n");
1968
1969         return 0;
1970 }
1971
1972 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1973 {
1974         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1975         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1976         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1977         struct xgbe_channel *channel;
1978         struct xgbe_ring *ring;
1979         struct xgbe_packet_data *packet;
1980         struct netdev_queue *txq;
1981         netdev_tx_t ret;
1982
1983         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1984
1985         channel = pdata->channel[skb->queue_mapping];
1986         txq = netdev_get_tx_queue(netdev, channel->queue_index);
1987         ring = channel->tx_ring;
1988         packet = &ring->packet_data;
1989
1990         ret = NETDEV_TX_OK;
1991
1992         if (skb->len == 0) {
1993                 netif_err(pdata, tx_err, netdev,
1994                           "empty skb received from stack\n");
1995                 dev_kfree_skb_any(skb);
1996                 goto tx_netdev_return;
1997         }
1998
1999         /* Calculate preliminary packet info */
2000         memset(packet, 0, sizeof(*packet));
2001         xgbe_packet_info(pdata, ring, skb, packet);
2002
2003         /* Check that there are enough descriptors available */
2004         ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
2005         if (ret)
2006                 goto tx_netdev_return;
2007
2008         ret = xgbe_prep_tso(skb, packet);
2009         if (ret) {
2010                 netif_err(pdata, tx_err, netdev,
2011                           "error processing TSO packet\n");
2012                 dev_kfree_skb_any(skb);
2013                 goto tx_netdev_return;
2014         }
2015         xgbe_prep_vlan(skb, packet);
2016
2017         if (!desc_if->map_tx_skb(channel, skb)) {
2018                 dev_kfree_skb_any(skb);
2019                 goto tx_netdev_return;
2020         }
2021
2022         xgbe_prep_tx_tstamp(pdata, skb, packet);
2023
2024         /* Report on the actual number of bytes (to be) sent */
2025         netdev_tx_sent_queue(txq, packet->tx_bytes);
2026
2027         /* Configure required descriptor fields for transmission */
2028         hw_if->dev_xmit(channel);
2029
2030         if (netif_msg_pktdata(pdata))
2031                 xgbe_print_pkt(netdev, skb, true);
2032
2033         /* Stop the queue in advance if there may not be enough descriptors */
2034         xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2035
2036         ret = NETDEV_TX_OK;
2037
2038 tx_netdev_return:
2039         return ret;
2040 }
2041
2042 static void xgbe_set_rx_mode(struct net_device *netdev)
2043 {
2044         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2045         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2046
2047         DBGPR("-->xgbe_set_rx_mode\n");
2048
2049         hw_if->config_rx_mode(pdata);
2050
2051         DBGPR("<--xgbe_set_rx_mode\n");
2052 }
2053
2054 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2055 {
2056         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2057         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2058         struct sockaddr *saddr = addr;
2059
2060         DBGPR("-->xgbe_set_mac_address\n");
2061
2062         if (!is_valid_ether_addr(saddr->sa_data))
2063                 return -EADDRNOTAVAIL;
2064
2065         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2066
2067         hw_if->set_mac_address(pdata, netdev->dev_addr);
2068
2069         DBGPR("<--xgbe_set_mac_address\n");
2070
2071         return 0;
2072 }
2073
2074 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2075 {
2076         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2077         int ret;
2078
2079         switch (cmd) {
2080         case SIOCGHWTSTAMP:
2081                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2082                 break;
2083
2084         case SIOCSHWTSTAMP:
2085                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2086                 break;
2087
2088         default:
2089                 ret = -EOPNOTSUPP;
2090         }
2091
2092         return ret;
2093 }
2094
2095 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2096 {
2097         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2098         int ret;
2099
2100         DBGPR("-->xgbe_change_mtu\n");
2101
2102         ret = xgbe_calc_rx_buf_size(netdev, mtu);
2103         if (ret < 0)
2104                 return ret;
2105
2106         pdata->rx_buf_size = ret;
2107         netdev->mtu = mtu;
2108
2109         xgbe_restart_dev(pdata);
2110
2111         DBGPR("<--xgbe_change_mtu\n");
2112
2113         return 0;
2114 }
2115
2116 static void xgbe_tx_timeout(struct net_device *netdev)
2117 {
2118         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2119
2120         netdev_warn(netdev, "tx timeout, device restarting\n");
2121         schedule_work(&pdata->restart_work);
2122 }
2123
2124 static void xgbe_get_stats64(struct net_device *netdev,
2125                              struct rtnl_link_stats64 *s)
2126 {
2127         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2128         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2129
2130         DBGPR("-->%s\n", __func__);
2131
2132         pdata->hw_if.read_mmc_stats(pdata);
2133
2134         s->rx_packets = pstats->rxframecount_gb;
2135         s->rx_bytes = pstats->rxoctetcount_gb;
2136         s->rx_errors = pstats->rxframecount_gb -
2137                        pstats->rxbroadcastframes_g -
2138                        pstats->rxmulticastframes_g -
2139                        pstats->rxunicastframes_g;
2140         s->multicast = pstats->rxmulticastframes_g;
2141         s->rx_length_errors = pstats->rxlengtherror;
2142         s->rx_crc_errors = pstats->rxcrcerror;
2143         s->rx_fifo_errors = pstats->rxfifooverflow;
2144
2145         s->tx_packets = pstats->txframecount_gb;
2146         s->tx_bytes = pstats->txoctetcount_gb;
2147         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2148         s->tx_dropped = netdev->stats.tx_dropped;
2149
2150         DBGPR("<--%s\n", __func__);
2151 }
2152
2153 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2154                                 u16 vid)
2155 {
2156         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2157         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2158
2159         DBGPR("-->%s\n", __func__);
2160
2161         set_bit(vid, pdata->active_vlans);
2162         hw_if->update_vlan_hash_table(pdata);
2163
2164         DBGPR("<--%s\n", __func__);
2165
2166         return 0;
2167 }
2168
2169 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2170                                  u16 vid)
2171 {
2172         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2173         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2174
2175         DBGPR("-->%s\n", __func__);
2176
2177         clear_bit(vid, pdata->active_vlans);
2178         hw_if->update_vlan_hash_table(pdata);
2179
2180         DBGPR("<--%s\n", __func__);
2181
2182         return 0;
2183 }
2184
2185 #ifdef CONFIG_NET_POLL_CONTROLLER
2186 static void xgbe_poll_controller(struct net_device *netdev)
2187 {
2188         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2189         struct xgbe_channel *channel;
2190         unsigned int i;
2191
2192         DBGPR("-->xgbe_poll_controller\n");
2193
2194         if (pdata->per_channel_irq) {
2195                 for (i = 0; i < pdata->channel_count; i++) {
2196                         channel = pdata->channel[i];
2197                         xgbe_dma_isr(channel->dma_irq, channel);
2198                 }
2199         } else {
2200                 disable_irq(pdata->dev_irq);
2201                 xgbe_isr(pdata->dev_irq, pdata);
2202                 enable_irq(pdata->dev_irq);
2203         }
2204
2205         DBGPR("<--xgbe_poll_controller\n");
2206 }
2207 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2208
2209 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2210                          void *type_data)
2211 {
2212         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2213         struct tc_mqprio_qopt *mqprio = type_data;
2214         u8 tc;
2215
2216         if (type != TC_SETUP_MQPRIO)
2217                 return -EOPNOTSUPP;
2218
2219         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2220         tc = mqprio->num_tc;
2221
2222         if (tc > pdata->hw_feat.tc_cnt)
2223                 return -EINVAL;
2224
2225         pdata->num_tcs = tc;
2226         pdata->hw_if.config_tc(pdata);
2227
2228         return 0;
2229 }
2230
2231 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2232                                            netdev_features_t features)
2233 {
2234         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2235         netdev_features_t vxlan_base, vxlan_mask;
2236
2237         vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2238         vxlan_mask = vxlan_base | NETIF_F_GSO_UDP_TUNNEL_CSUM;
2239
2240         pdata->vxlan_features = features & vxlan_mask;
2241
2242         /* Only fix VXLAN-related features */
2243         if (!pdata->vxlan_features)
2244                 return features;
2245
2246         /* If VXLAN isn't supported then clear any features:
2247          *   This is needed because NETIF_F_RX_UDP_TUNNEL_PORT gets
2248          *   automatically set if ndo_udp_tunnel_add is set.
2249          */
2250         if (!pdata->hw_feat.vxn)
2251                 return features & ~vxlan_mask;
2252
2253         /* VXLAN CSUM requires VXLAN base */
2254         if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2255             !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2256                 netdev_notice(netdev,
2257                               "forcing tx udp tunnel support\n");
2258                 features |= NETIF_F_GSO_UDP_TUNNEL;
2259         }
2260
2261         /* Can't do one without doing the other */
2262         if ((features & vxlan_base) != vxlan_base) {
2263                 netdev_notice(netdev,
2264                               "forcing both tx and rx udp tunnel support\n");
2265                 features |= vxlan_base;
2266         }
2267
2268         if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2269                 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2270                         netdev_notice(netdev,
2271                                       "forcing tx udp tunnel checksumming on\n");
2272                         features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2273                 }
2274         } else {
2275                 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2276                         netdev_notice(netdev,
2277                                       "forcing tx udp tunnel checksumming off\n");
2278                         features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2279                 }
2280         }
2281
2282         pdata->vxlan_features = features & vxlan_mask;
2283
2284         /* Adjust UDP Tunnel based on current state */
2285         if (pdata->vxlan_force_disable) {
2286                 netdev_notice(netdev,
2287                               "VXLAN acceleration disabled, turning off udp tunnel features\n");
2288                 features &= ~vxlan_mask;
2289         }
2290
2291         return features;
2292 }
2293
2294 static int xgbe_set_features(struct net_device *netdev,
2295                              netdev_features_t features)
2296 {
2297         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2298         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2299         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2300         netdev_features_t udp_tunnel;
2301         int ret = 0;
2302
2303         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2304         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2305         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2306         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2307         udp_tunnel = pdata->netdev_features & NETIF_F_GSO_UDP_TUNNEL;
2308
2309         if ((features & NETIF_F_RXHASH) && !rxhash)
2310                 ret = hw_if->enable_rss(pdata);
2311         else if (!(features & NETIF_F_RXHASH) && rxhash)
2312                 ret = hw_if->disable_rss(pdata);
2313         if (ret)
2314                 return ret;
2315
2316         if ((features & NETIF_F_RXCSUM) && !rxcsum)
2317                 hw_if->enable_rx_csum(pdata);
2318         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2319                 hw_if->disable_rx_csum(pdata);
2320
2321         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2322                 hw_if->enable_rx_vlan_stripping(pdata);
2323         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2324                 hw_if->disable_rx_vlan_stripping(pdata);
2325
2326         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2327                 hw_if->enable_rx_vlan_filtering(pdata);
2328         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2329                 hw_if->disable_rx_vlan_filtering(pdata);
2330
2331         if ((features & NETIF_F_GSO_UDP_TUNNEL) && !udp_tunnel)
2332                 xgbe_enable_vxlan_accel(pdata);
2333         else if (!(features & NETIF_F_GSO_UDP_TUNNEL) && udp_tunnel)
2334                 xgbe_disable_vxlan_accel(pdata);
2335
2336         pdata->netdev_features = features;
2337
2338         DBGPR("<--xgbe_set_features\n");
2339
2340         return 0;
2341 }
2342
2343 static void xgbe_udp_tunnel_add(struct net_device *netdev,
2344                                 struct udp_tunnel_info *ti)
2345 {
2346         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2347         struct xgbe_vxlan_data *vdata;
2348
2349         if (!pdata->hw_feat.vxn)
2350                 return;
2351
2352         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2353                 return;
2354
2355         pdata->vxlan_port_count++;
2356
2357         netif_dbg(pdata, drv, netdev,
2358                   "adding VXLAN tunnel, family=%hx/port=%hx\n",
2359                   ti->sa_family, be16_to_cpu(ti->port));
2360
2361         if (pdata->vxlan_force_disable)
2362                 return;
2363
2364         vdata = kzalloc(sizeof(*vdata), GFP_ATOMIC);
2365         if (!vdata) {
2366                 /* Can no longer properly track VXLAN ports */
2367                 pdata->vxlan_force_disable = 1;
2368                 netif_dbg(pdata, drv, netdev,
2369                           "internal error, disabling VXLAN accelerations\n");
2370
2371                 xgbe_disable_vxlan_accel(pdata);
2372
2373                 return;
2374         }
2375         vdata->sa_family = ti->sa_family;
2376         vdata->port = ti->port;
2377
2378         list_add_tail(&vdata->list, &pdata->vxlan_ports);
2379
2380         /* First port added? */
2381         if (pdata->vxlan_port_count == 1) {
2382                 xgbe_enable_vxlan_accel(pdata);
2383
2384                 return;
2385         }
2386 }
2387
2388 static void xgbe_udp_tunnel_del(struct net_device *netdev,
2389                                 struct udp_tunnel_info *ti)
2390 {
2391         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2392         struct xgbe_vxlan_data *vdata;
2393
2394         if (!pdata->hw_feat.vxn)
2395                 return;
2396
2397         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2398                 return;
2399
2400         netif_dbg(pdata, drv, netdev,
2401                   "deleting VXLAN tunnel, family=%hx/port=%hx\n",
2402                   ti->sa_family, be16_to_cpu(ti->port));
2403
2404         /* Don't need safe version since loop terminates with deletion */
2405         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
2406                 if (vdata->sa_family != ti->sa_family)
2407                         continue;
2408
2409                 if (vdata->port != ti->port)
2410                         continue;
2411
2412                 list_del(&vdata->list);
2413                 kfree(vdata);
2414
2415                 break;
2416         }
2417
2418         pdata->vxlan_port_count--;
2419         if (!pdata->vxlan_port_count) {
2420                 xgbe_reset_vxlan_accel(pdata);
2421
2422                 return;
2423         }
2424
2425         if (pdata->vxlan_force_disable)
2426                 return;
2427
2428         /* See if VXLAN tunnel id needs to be changed */
2429         vdata = list_first_entry(&pdata->vxlan_ports,
2430                                  struct xgbe_vxlan_data, list);
2431         if (pdata->vxlan_port == be16_to_cpu(vdata->port))
2432                 return;
2433
2434         pdata->vxlan_port = be16_to_cpu(vdata->port);
2435         pdata->hw_if.set_vxlan_id(pdata);
2436 }
2437
2438 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2439                                              struct net_device *netdev,
2440                                              netdev_features_t features)
2441 {
2442         features = vlan_features_check(skb, features);
2443         features = vxlan_features_check(skb, features);
2444
2445         return features;
2446 }
2447
2448 static const struct net_device_ops xgbe_netdev_ops = {
2449         .ndo_open               = xgbe_open,
2450         .ndo_stop               = xgbe_close,
2451         .ndo_start_xmit         = xgbe_xmit,
2452         .ndo_set_rx_mode        = xgbe_set_rx_mode,
2453         .ndo_set_mac_address    = xgbe_set_mac_address,
2454         .ndo_validate_addr      = eth_validate_addr,
2455         .ndo_do_ioctl           = xgbe_ioctl,
2456         .ndo_change_mtu         = xgbe_change_mtu,
2457         .ndo_tx_timeout         = xgbe_tx_timeout,
2458         .ndo_get_stats64        = xgbe_get_stats64,
2459         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
2460         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
2461 #ifdef CONFIG_NET_POLL_CONTROLLER
2462         .ndo_poll_controller    = xgbe_poll_controller,
2463 #endif
2464         .ndo_setup_tc           = xgbe_setup_tc,
2465         .ndo_fix_features       = xgbe_fix_features,
2466         .ndo_set_features       = xgbe_set_features,
2467         .ndo_udp_tunnel_add     = xgbe_udp_tunnel_add,
2468         .ndo_udp_tunnel_del     = xgbe_udp_tunnel_del,
2469         .ndo_features_check     = xgbe_features_check,
2470 };
2471
2472 const struct net_device_ops *xgbe_get_netdev_ops(void)
2473 {
2474         return &xgbe_netdev_ops;
2475 }
2476
2477 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2478 {
2479         struct xgbe_prv_data *pdata = channel->pdata;
2480         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2481         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2482         struct xgbe_ring *ring = channel->rx_ring;
2483         struct xgbe_ring_data *rdata;
2484
2485         while (ring->dirty != ring->cur) {
2486                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2487
2488                 /* Reset rdata values */
2489                 desc_if->unmap_rdata(pdata, rdata);
2490
2491                 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2492                         break;
2493
2494                 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2495
2496                 ring->dirty++;
2497         }
2498
2499         /* Make sure everything is written before the register write */
2500         wmb();
2501
2502         /* Update the Rx Tail Pointer Register with address of
2503          * the last cleaned entry */
2504         rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2505         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2506                           lower_32_bits(rdata->rdesc_dma));
2507 }
2508
2509 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2510                                        struct napi_struct *napi,
2511                                        struct xgbe_ring_data *rdata,
2512                                        unsigned int len)
2513 {
2514         struct sk_buff *skb;
2515         u8 *packet;
2516
2517         skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2518         if (!skb)
2519                 return NULL;
2520
2521         /* Pull in the header buffer which may contain just the header
2522          * or the header plus data
2523          */
2524         dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2525                                       rdata->rx.hdr.dma_off,
2526                                       rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2527
2528         packet = page_address(rdata->rx.hdr.pa.pages) +
2529                  rdata->rx.hdr.pa.pages_offset;
2530         skb_copy_to_linear_data(skb, packet, len);
2531         skb_put(skb, len);
2532
2533         return skb;
2534 }
2535
2536 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2537                                      struct xgbe_packet_data *packet)
2538 {
2539         /* Always zero if not the first descriptor */
2540         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2541                 return 0;
2542
2543         /* First descriptor with split header, return header length */
2544         if (rdata->rx.hdr_len)
2545                 return rdata->rx.hdr_len;
2546
2547         /* First descriptor but not the last descriptor and no split header,
2548          * so the full buffer was used
2549          */
2550         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2551                 return rdata->rx.hdr.dma_len;
2552
2553         /* First descriptor and last descriptor and no split header, so
2554          * calculate how much of the buffer was used
2555          */
2556         return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2557 }
2558
2559 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2560                                      struct xgbe_packet_data *packet,
2561                                      unsigned int len)
2562 {
2563         /* Always the full buffer if not the last descriptor */
2564         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2565                 return rdata->rx.buf.dma_len;
2566
2567         /* Last descriptor so calculate how much of the buffer was used
2568          * for the last bit of data
2569          */
2570         return rdata->rx.len - len;
2571 }
2572
2573 static int xgbe_tx_poll(struct xgbe_channel *channel)
2574 {
2575         struct xgbe_prv_data *pdata = channel->pdata;
2576         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2577         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2578         struct xgbe_ring *ring = channel->tx_ring;
2579         struct xgbe_ring_data *rdata;
2580         struct xgbe_ring_desc *rdesc;
2581         struct net_device *netdev = pdata->netdev;
2582         struct netdev_queue *txq;
2583         int processed = 0;
2584         unsigned int tx_packets = 0, tx_bytes = 0;
2585         unsigned int cur;
2586
2587         DBGPR("-->xgbe_tx_poll\n");
2588
2589         /* Nothing to do if there isn't a Tx ring for this channel */
2590         if (!ring)
2591                 return 0;
2592
2593         cur = ring->cur;
2594
2595         /* Be sure we get ring->cur before accessing descriptor data */
2596         smp_rmb();
2597
2598         txq = netdev_get_tx_queue(netdev, channel->queue_index);
2599
2600         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2601                (ring->dirty != cur)) {
2602                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2603                 rdesc = rdata->rdesc;
2604
2605                 if (!hw_if->tx_complete(rdesc))
2606                         break;
2607
2608                 /* Make sure descriptor fields are read after reading the OWN
2609                  * bit */
2610                 dma_rmb();
2611
2612                 if (netif_msg_tx_done(pdata))
2613                         xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2614
2615                 if (hw_if->is_last_desc(rdesc)) {
2616                         tx_packets += rdata->tx.packets;
2617                         tx_bytes += rdata->tx.bytes;
2618                 }
2619
2620                 /* Free the SKB and reset the descriptor for re-use */
2621                 desc_if->unmap_rdata(pdata, rdata);
2622                 hw_if->tx_desc_reset(rdata);
2623
2624                 processed++;
2625                 ring->dirty++;
2626         }
2627
2628         if (!processed)
2629                 return 0;
2630
2631         netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2632
2633         if ((ring->tx.queue_stopped == 1) &&
2634             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2635                 ring->tx.queue_stopped = 0;
2636                 netif_tx_wake_queue(txq);
2637         }
2638
2639         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2640
2641         return processed;
2642 }
2643
2644 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2645 {
2646         struct xgbe_prv_data *pdata = channel->pdata;
2647         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2648         struct xgbe_ring *ring = channel->rx_ring;
2649         struct xgbe_ring_data *rdata;
2650         struct xgbe_packet_data *packet;
2651         struct net_device *netdev = pdata->netdev;
2652         struct napi_struct *napi;
2653         struct sk_buff *skb;
2654         struct skb_shared_hwtstamps *hwtstamps;
2655         unsigned int last, error, context_next, context;
2656         unsigned int len, buf1_len, buf2_len, max_len;
2657         unsigned int received = 0;
2658         int packet_count = 0;
2659
2660         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2661
2662         /* Nothing to do if there isn't a Rx ring for this channel */
2663         if (!ring)
2664                 return 0;
2665
2666         last = 0;
2667         context_next = 0;
2668
2669         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2670
2671         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2672         packet = &ring->packet_data;
2673         while (packet_count < budget) {
2674                 DBGPR("  cur = %d\n", ring->cur);
2675
2676                 /* First time in loop see if we need to restore state */
2677                 if (!received && rdata->state_saved) {
2678                         skb = rdata->state.skb;
2679                         error = rdata->state.error;
2680                         len = rdata->state.len;
2681                 } else {
2682                         memset(packet, 0, sizeof(*packet));
2683                         skb = NULL;
2684                         error = 0;
2685                         len = 0;
2686                 }
2687
2688 read_again:
2689                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2690
2691                 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2692                         xgbe_rx_refresh(channel);
2693
2694                 if (hw_if->dev_read(channel))
2695                         break;
2696
2697                 received++;
2698                 ring->cur++;
2699
2700                 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2701                                       LAST);
2702                 context_next = XGMAC_GET_BITS(packet->attributes,
2703                                               RX_PACKET_ATTRIBUTES,
2704                                               CONTEXT_NEXT);
2705                 context = XGMAC_GET_BITS(packet->attributes,
2706                                          RX_PACKET_ATTRIBUTES,
2707                                          CONTEXT);
2708
2709                 /* Earlier error, just drain the remaining data */
2710                 if ((!last || context_next) && error)
2711                         goto read_again;
2712
2713                 if (error || packet->errors) {
2714                         if (packet->errors)
2715                                 netif_err(pdata, rx_err, netdev,
2716                                           "error in received packet\n");
2717                         dev_kfree_skb(skb);
2718                         goto next_packet;
2719                 }
2720
2721                 if (!context) {
2722                         /* Get the data length in the descriptor buffers */
2723                         buf1_len = xgbe_rx_buf1_len(rdata, packet);
2724                         len += buf1_len;
2725                         buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2726                         len += buf2_len;
2727
2728                         if (buf2_len > rdata->rx.buf.dma_len) {
2729                                 /* Hardware inconsistency within the descriptors
2730                                  * that has resulted in a length underflow.
2731                                  */
2732                                 error = 1;
2733                                 goto skip_data;
2734                         }
2735
2736                         if (!skb) {
2737                                 skb = xgbe_create_skb(pdata, napi, rdata,
2738                                                       buf1_len);
2739                                 if (!skb) {
2740                                         error = 1;
2741                                         goto skip_data;
2742                                 }
2743                         }
2744
2745                         if (buf2_len) {
2746                                 dma_sync_single_range_for_cpu(pdata->dev,
2747                                                         rdata->rx.buf.dma_base,
2748                                                         rdata->rx.buf.dma_off,
2749                                                         rdata->rx.buf.dma_len,
2750                                                         DMA_FROM_DEVICE);
2751
2752                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2753                                                 rdata->rx.buf.pa.pages,
2754                                                 rdata->rx.buf.pa.pages_offset,
2755                                                 buf2_len,
2756                                                 rdata->rx.buf.dma_len);
2757                                 rdata->rx.buf.pa.pages = NULL;
2758                         }
2759                 }
2760
2761 skip_data:
2762                 if (!last || context_next)
2763                         goto read_again;
2764
2765                 if (!skb || error) {
2766                         dev_kfree_skb(skb);
2767                         goto next_packet;
2768                 }
2769
2770                 /* Be sure we don't exceed the configured MTU */
2771                 max_len = netdev->mtu + ETH_HLEN;
2772                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2773                     (skb->protocol == htons(ETH_P_8021Q)))
2774                         max_len += VLAN_HLEN;
2775
2776                 if (skb->len > max_len) {
2777                         netif_err(pdata, rx_err, netdev,
2778                                   "packet length exceeds configured MTU\n");
2779                         dev_kfree_skb(skb);
2780                         goto next_packet;
2781                 }
2782
2783                 if (netif_msg_pktdata(pdata))
2784                         xgbe_print_pkt(netdev, skb, false);
2785
2786                 skb_checksum_none_assert(skb);
2787                 if (XGMAC_GET_BITS(packet->attributes,
2788                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
2789                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2790
2791                 if (XGMAC_GET_BITS(packet->attributes,
2792                                    RX_PACKET_ATTRIBUTES, TNP)) {
2793                         skb->encapsulation = 1;
2794
2795                         if (XGMAC_GET_BITS(packet->attributes,
2796                                            RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2797                                 skb->csum_level = 1;
2798                 }
2799
2800                 if (XGMAC_GET_BITS(packet->attributes,
2801                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2802                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2803                                                packet->vlan_ctag);
2804
2805                 if (XGMAC_GET_BITS(packet->attributes,
2806                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2807                         u64 nsec;
2808
2809                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2810                                                     packet->rx_tstamp);
2811                         hwtstamps = skb_hwtstamps(skb);
2812                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
2813                 }
2814
2815                 if (XGMAC_GET_BITS(packet->attributes,
2816                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
2817                         skb_set_hash(skb, packet->rss_hash,
2818                                      packet->rss_hash_type);
2819
2820                 skb->dev = netdev;
2821                 skb->protocol = eth_type_trans(skb, netdev);
2822                 skb_record_rx_queue(skb, channel->queue_index);
2823
2824                 napi_gro_receive(napi, skb);
2825
2826 next_packet:
2827                 packet_count++;
2828         }
2829
2830         /* Check if we need to save state before leaving */
2831         if (received && (!last || context_next)) {
2832                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2833                 rdata->state_saved = 1;
2834                 rdata->state.skb = skb;
2835                 rdata->state.len = len;
2836                 rdata->state.error = error;
2837         }
2838
2839         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2840
2841         return packet_count;
2842 }
2843
2844 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2845 {
2846         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2847                                                     napi);
2848         struct xgbe_prv_data *pdata = channel->pdata;
2849         int processed = 0;
2850
2851         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2852
2853         /* Cleanup Tx ring first */
2854         xgbe_tx_poll(channel);
2855
2856         /* Process Rx ring next */
2857         processed = xgbe_rx_poll(channel, budget);
2858
2859         /* If we processed everything, we are done */
2860         if ((processed < budget) && napi_complete_done(napi, processed)) {
2861                 /* Enable Tx and Rx interrupts */
2862                 if (pdata->channel_irq_mode)
2863                         xgbe_enable_rx_tx_int(pdata, channel);
2864                 else
2865                         enable_irq(channel->dma_irq);
2866         }
2867
2868         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2869
2870         return processed;
2871 }
2872
2873 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2874 {
2875         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2876                                                    napi);
2877         struct xgbe_channel *channel;
2878         int ring_budget;
2879         int processed, last_processed;
2880         unsigned int i;
2881
2882         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2883
2884         processed = 0;
2885         ring_budget = budget / pdata->rx_ring_count;
2886         do {
2887                 last_processed = processed;
2888
2889                 for (i = 0; i < pdata->channel_count; i++) {
2890                         channel = pdata->channel[i];
2891
2892                         /* Cleanup Tx ring first */
2893                         xgbe_tx_poll(channel);
2894
2895                         /* Process Rx ring next */
2896                         if (ring_budget > (budget - processed))
2897                                 ring_budget = budget - processed;
2898                         processed += xgbe_rx_poll(channel, ring_budget);
2899                 }
2900         } while ((processed < budget) && (processed != last_processed));
2901
2902         /* If we processed everything, we are done */
2903         if ((processed < budget) && napi_complete_done(napi, processed)) {
2904                 /* Enable Tx and Rx interrupts */
2905                 xgbe_enable_rx_tx_ints(pdata);
2906         }
2907
2908         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2909
2910         return processed;
2911 }
2912
2913 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2914                        unsigned int idx, unsigned int count, unsigned int flag)
2915 {
2916         struct xgbe_ring_data *rdata;
2917         struct xgbe_ring_desc *rdesc;
2918
2919         while (count--) {
2920                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2921                 rdesc = rdata->rdesc;
2922                 netdev_dbg(pdata->netdev,
2923                            "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2924                            (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2925                            le32_to_cpu(rdesc->desc0),
2926                            le32_to_cpu(rdesc->desc1),
2927                            le32_to_cpu(rdesc->desc2),
2928                            le32_to_cpu(rdesc->desc3));
2929                 idx++;
2930         }
2931 }
2932
2933 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2934                        unsigned int idx)
2935 {
2936         struct xgbe_ring_data *rdata;
2937         struct xgbe_ring_desc *rdesc;
2938
2939         rdata = XGBE_GET_DESC_DATA(ring, idx);
2940         rdesc = rdata->rdesc;
2941         netdev_dbg(pdata->netdev,
2942                    "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2943                    idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2944                    le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2945 }
2946
2947 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2948 {
2949         struct ethhdr *eth = (struct ethhdr *)skb->data;
2950         unsigned char *buf = skb->data;
2951         unsigned char buffer[128];
2952         unsigned int i, j;
2953
2954         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2955
2956         netdev_dbg(netdev, "%s packet of %d bytes\n",
2957                    (tx_rx ? "TX" : "RX"), skb->len);
2958
2959         netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2960         netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2961         netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2962
2963         for (i = 0, j = 0; i < skb->len;) {
2964                 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2965                               buf[i++]);
2966
2967                 if ((i % 32) == 0) {
2968                         netdev_dbg(netdev, "  %#06x: %s\n", i - 32, buffer);
2969                         j = 0;
2970                 } else if ((i % 16) == 0) {
2971                         buffer[j++] = ' ';
2972                         buffer[j++] = ' ';
2973                 } else if ((i % 4) == 0) {
2974                         buffer[j++] = ' ';
2975                 }
2976         }
2977         if (i % 32)
2978                 netdev_dbg(netdev, "  %#06x: %s\n", i - (i % 32), buffer);
2979
2980         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2981 }