drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <linux/interrupt.h>
 122 #include <net/busy_poll.h>
 123 #include <linux/clk.h>
 124 #include <linux/if_ether.h>
 125 #include <linux/net_tstamp.h>
 126 #include <linux/phy.h>
 127 #include <net/vxlan.h>
 128
 129 #include "xgbe.h"
 130 #include "xgbe-common.h"
 131
 132 static unsigned int ecc_sec_info_threshold = 10;
 133 static unsigned int ecc_sec_warn_threshold = 10000;
 134 static unsigned int ecc_sec_period = 600;
 135 static unsigned int ecc_ded_threshold = 2;
 136 static unsigned int ecc_ded_period = 600;
 137
 138 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
 139 /* Only expose the ECC parameters if supported */
 140 module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO);
 141 MODULE_PARM_DESC(ecc_sec_info_threshold,
 142                  " ECC corrected error informational threshold setting");
 143
 144 module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO);
 145 MODULE_PARM_DESC(ecc_sec_warn_threshold,
 146                  " ECC corrected error warning threshold setting");
 147
 148 module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO);
 149 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
 150
 151 module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO);
 152 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
 153
 154 module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO);
 155 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
 156 #endif
 157
 158 static int xgbe_one_poll(struct napi_struct *, int);
 159 static int xgbe_all_poll(struct napi_struct *, int);
 160 static void xgbe_stop(struct xgbe_prv_data *);
 161
 162 static void *xgbe_alloc_node(size_t size, int node)
 163 {
 164         void *mem;
 165
 166         mem = kzalloc_node(size, GFP_KERNEL, node);
 167         if (!mem)
 168                 mem = kzalloc(size, GFP_KERNEL);
 169
 170         return mem;
 171 }
 172
 173 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 174 {
 175         unsigned int i;
 176
 177         for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
 178                 if (!pdata->channel[i])
 179                         continue;
 180
 181                 kfree(pdata->channel[i]->rx_ring);
 182                 kfree(pdata->channel[i]->tx_ring);
 183                 kfree(pdata->channel[i]);
 184
 185                 pdata->channel[i] = NULL;
 186         }
 187
 188         pdata->channel_count = 0;
 189 }
 190
 191 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 192 {
 193         struct xgbe_channel *channel;
 194         struct xgbe_ring *ring;
 195         unsigned int count, i;
 196         unsigned int cpu;
 197         int node;
 198
 199         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 200         for (i = 0; i < count; i++) {
 201                 /* Attempt to use a CPU on the node the device is on */
 202                 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
 203
 204                 /* Set the allocation node based on the returned CPU */
 205                 node = cpu_to_node(cpu);
 206
 207                 channel = xgbe_alloc_node(sizeof(*channel), node);
 208                 if (!channel)
 209                         goto err_mem;
 210                 pdata->channel[i] = channel;
 211
 212                 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
 213                 channel->pdata = pdata;
 214                 channel->queue_index = i;
 215                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 216                                     (DMA_CH_INC * i);
 217                 channel->node = node;
 218                 cpumask_set_cpu(cpu, &channel->affinity_mask);
 219
 220                 if (pdata->per_channel_irq)
 221                         channel->dma_irq = pdata->channel_irq[i];
 222
 223                 if (i < pdata->tx_ring_count) {
 224                         ring = xgbe_alloc_node(sizeof(*ring), node);
 225                         if (!ring)
 226                                 goto err_mem;
 227
 228                         spin_lock_init(&ring->lock);
 229                         ring->node = node;
 230
 231                         channel->tx_ring = ring;
 232                 }
 233
 234                 if (i < pdata->rx_ring_count) {
 235                         ring = xgbe_alloc_node(sizeof(*ring), node);
 236                         if (!ring)
 237                                 goto err_mem;
 238
 239                         spin_lock_init(&ring->lock);
 240                         ring->node = node;
 241
 242                         channel->rx_ring = ring;
 243                 }
 244
 245                 netif_dbg(pdata, drv, pdata->netdev,
 246                           "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
 247
 248                 netif_dbg(pdata, drv, pdata->netdev,
 249                           "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 250                           channel->name, channel->dma_regs, channel->dma_irq,
 251                           channel->tx_ring, channel->rx_ring);
 252         }
 253
 254         pdata->channel_count = count;
 255
 256         return 0;
 257
 258 err_mem:
 259         xgbe_free_channels(pdata);
 260
 261         return -ENOMEM;
 262 }
 263
 264 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 265 {
 266         return (ring->rdesc_count - (ring->cur - ring->dirty));
 267 }
 268
 269 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
 270 {
 271         return (ring->cur - ring->dirty);
 272 }
 273
 274 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
 275                                     struct xgbe_ring *ring, unsigned int count)
 276 {
 277         struct xgbe_prv_data *pdata = channel->pdata;
 278
 279         if (count > xgbe_tx_avail_desc(ring)) {
 280                 netif_info(pdata, drv, pdata->netdev,
 281                            "Tx queue stopped, not enough descriptors available\n");
 282                 netif_stop_subqueue(pdata->netdev, channel->queue_index);
 283                 ring->tx.queue_stopped = 1;
 284
 285                 /* If we haven't notified the hardware because of xmit_more
 286                  * support, tell it now
 287                  */
 288                 if (ring->tx.xmit_more)
 289                         pdata->hw_if.tx_start_xmit(channel, ring);
 290
 291                 return NETDEV_TX_BUSY;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 298 {
 299         unsigned int rx_buf_size;
 300
 301         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 302         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 303
 304         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 305                       ~(XGBE_RX_BUF_ALIGN - 1);
 306
 307         return rx_buf_size;
 308 }
 309
 310 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
 311                                   struct xgbe_channel *channel)
 312 {
 313         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 314         enum xgbe_int int_id;
 315
 316         if (channel->tx_ring && channel->rx_ring)
 317                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 318         else if (channel->tx_ring)
 319                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 320         else if (channel->rx_ring)
 321                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 322         else
 323                 return;
 324
 325         hw_if->enable_int(channel, int_id);
 326 }
 327
 328 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 329 {
 330         unsigned int i;
 331
 332         for (i = 0; i < pdata->channel_count; i++)
 333                 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
 334 }
 335
 336 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
 337                                    struct xgbe_channel *channel)
 338 {
 339         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 340         enum xgbe_int int_id;
 341
 342         if (channel->tx_ring && channel->rx_ring)
 343                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 344         else if (channel->tx_ring)
 345                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 346         else if (channel->rx_ring)
 347                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 348         else
 349                 return;
 350
 351         hw_if->disable_int(channel, int_id);
 352 }
 353
 354 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 355 {
 356         unsigned int i;
 357
 358         for (i = 0; i < pdata->channel_count; i++)
 359                 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
 360 }
 361
 362 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
 363                          unsigned int *count, const char *area)
 364 {
 365         if (time_before(jiffies, *period)) {
 366                 (*count)++;
 367         } else {
 368                 *period = jiffies + (ecc_sec_period * HZ);
 369                 *count = 1;
 370         }
 371
 372         if (*count > ecc_sec_info_threshold)
 373                 dev_warn_once(pdata->dev,
 374                               "%s ECC corrected errors exceed informational threshold\n",
 375                               area);
 376
 377         if (*count > ecc_sec_warn_threshold) {
 378                 dev_warn_once(pdata->dev,
 379                               "%s ECC corrected errors exceed warning threshold\n",
 380                               area);
 381                 return true;
 382         }
 383
 384         return false;
 385 }
 386
 387 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
 388                          unsigned int *count, const char *area)
 389 {
 390         if (time_before(jiffies, *period)) {
 391                 (*count)++;
 392         } else {
 393                 *period = jiffies + (ecc_ded_period * HZ);
 394                 *count = 1;
 395         }
 396
 397         if (*count > ecc_ded_threshold) {
 398                 netdev_alert(pdata->netdev,
 399                              "%s ECC detected errors exceed threshold\n",
 400                              area);
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 static void xgbe_ecc_isr_task(unsigned long data)
 408 {
 409         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 410         unsigned int ecc_isr;
 411         bool stop = false;
 412
 413         /* Mask status with only the interrupts we care about */
 414         ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
 415         ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
 416         netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
 417
 418         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
 419                 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
 420                                      &pdata->tx_ded_count, "TX fifo");
 421         }
 422
 423         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
 424                 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
 425                                      &pdata->rx_ded_count, "RX fifo");
 426         }
 427
 428         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
 429                 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
 430                                      &pdata->desc_ded_count,
 431                                      "descriptor cache");
 432         }
 433
 434         if (stop) {
 435                 pdata->hw_if.disable_ecc_ded(pdata);
 436                 schedule_work(&pdata->stopdev_work);
 437                 goto out;
 438         }
 439
 440         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
 441                 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
 442                                  &pdata->tx_sec_count, "TX fifo"))
 443                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
 444         }
 445
 446         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
 447                 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
 448                                  &pdata->rx_sec_count, "RX fifo"))
 449                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
 450
 451         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
 452                 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
 453                                  &pdata->desc_sec_count, "descriptor cache"))
 454                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
 455
 456 out:
 457         /* Clear all ECC interrupts */
 458         XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
 459
 460         /* Reissue interrupt if status is not clear */
 461         if (pdata->vdata->irq_reissue_support)
 462                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
 463 }
 464
 465 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
 466 {
 467         struct xgbe_prv_data *pdata = data;
 468
 469         if (pdata->isr_as_tasklet)
 470                 tasklet_schedule(&pdata->tasklet_ecc);
 471         else
 472                 xgbe_ecc_isr_task((unsigned long)pdata);
 473
 474         return IRQ_HANDLED;
 475 }
 476
 477 static void xgbe_isr_task(unsigned long data)
 478 {
 479         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 480         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 481         struct xgbe_channel *channel;
 482         unsigned int dma_isr, dma_ch_isr;
 483         unsigned int mac_isr, mac_tssr, mac_mdioisr;
 484         unsigned int i;
 485
 486         /* The DMA interrupt status register also reports MAC and MTL
 487          * interrupts. So for polling mode, we just need to check for
 488          * this register to be non-zero
 489          */
 490         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 491         if (!dma_isr)
 492                 goto isr_done;
 493
 494         netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
 495
 496         for (i = 0; i < pdata->channel_count; i++) {
 497                 if (!(dma_isr & (1 << i)))
 498                         continue;
 499
 500                 channel = pdata->channel[i];
 501
 502                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 503                 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
 504                           i, dma_ch_isr);
 505
 506                 /* The TI or RI interrupt bits may still be set even if using
 507                  * per channel DMA interrupts. Check to be sure those are not
 508                  * enabled before using the private data napi structure.
 509                  */
 510                 if (!pdata->per_channel_irq &&
 511                     (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 512                      XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
 513                         if (napi_schedule_prep(&pdata->napi)) {
 514                                 /* Disable Tx and Rx interrupts */
 515                                 xgbe_disable_rx_tx_ints(pdata);
 516
 517                                 /* Turn on polling */
 518                                 __napi_schedule(&pdata->napi);
 519                         }
 520                 } else {
 521                         /* Don't clear Rx/Tx status if doing per channel DMA
 522                          * interrupts, these will be cleared by the ISR for
 523                          * per channel DMA interrupts.
 524                          */
 525                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
 526                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
 527                 }
 528
 529                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
 530                         pdata->ext_stats.rx_buffer_unavailable++;
 531
 532                 /* Restart the device on a Fatal Bus Error */
 533                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 534                         schedule_work(&pdata->restart_work);
 535
 536                 /* Clear interrupt signals */
 537                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 538         }
 539
 540         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 541                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 542
 543                 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
 544                           mac_isr);
 545
 546                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 547                         hw_if->tx_mmc_int(pdata);
 548
 549                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 550                         hw_if->rx_mmc_int(pdata);
 551
 552                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 553                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 554
 555                         netif_dbg(pdata, intr, pdata->netdev,
 556                                   "MAC_TSSR=%#010x\n", mac_tssr);
 557
 558                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 559                                 /* Read Tx Timestamp to clear interrupt */
 560                                 pdata->tx_tstamp =
 561                                         hw_if->get_tx_tstamp(pdata);
 562                                 queue_work(pdata->dev_workqueue,
 563                                            &pdata->tx_tstamp_work);
 564                         }
 565                 }
 566
 567                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
 568                         mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
 569
 570                         netif_dbg(pdata, intr, pdata->netdev,
 571                                   "MAC_MDIOISR=%#010x\n", mac_mdioisr);
 572
 573                         if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
 574                                            SNGLCOMPINT))
 575                                 complete(&pdata->mdio_complete);
 576                 }
 577         }
 578
 579 isr_done:
 580         /* If there is not a separate AN irq, handle it here */
 581         if (pdata->dev_irq == pdata->an_irq)
 582                 pdata->phy_if.an_isr(pdata);
 583
 584         /* If there is not a separate ECC irq, handle it here */
 585         if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
 586                 xgbe_ecc_isr_task((unsigned long)pdata);
 587
 588         /* If there is not a separate I2C irq, handle it here */
 589         if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
 590                 pdata->i2c_if.i2c_isr(pdata);
 591
 592         /* Reissue interrupt if status is not clear */
 593         if (pdata->vdata->irq_reissue_support) {
 594                 unsigned int reissue_mask;
 595
 596                 reissue_mask = 1 << 0;
 597                 if (!pdata->per_channel_irq)
 598                         reissue_mask |= 0xffff << 4;
 599
 600                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
 601         }
 602 }
 603
 604 static irqreturn_t xgbe_isr(int irq, void *data)
 605 {
 606         struct xgbe_prv_data *pdata = data;
 607
 608         if (pdata->isr_as_tasklet)
 609                 tasklet_schedule(&pdata->tasklet_dev);
 610         else
 611                 xgbe_isr_task((unsigned long)pdata);
 612
 613         return IRQ_HANDLED;
 614 }
 615
 616 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 617 {
 618         struct xgbe_channel *channel = data;
 619         struct xgbe_prv_data *pdata = channel->pdata;
 620         unsigned int dma_status;
 621
 622         /* Per channel DMA interrupts are enabled, so we use the per
 623          * channel napi structure and not the private data napi structure
 624          */
 625         if (napi_schedule_prep(&channel->napi)) {
 626                 /* Disable Tx and Rx interrupts */
 627                 if (pdata->channel_irq_mode)
 628                         xgbe_disable_rx_tx_int(pdata, channel);
 629                 else
 630                         disable_irq_nosync(channel->dma_irq);
 631
 632                 /* Turn on polling */
 633                 __napi_schedule_irqoff(&channel->napi);
 634         }
 635
 636         /* Clear Tx/Rx signals */
 637         dma_status = 0;
 638         XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
 639         XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
 640         XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
 641
 642         return IRQ_HANDLED;
 643 }
 644
 645 static void xgbe_tx_timer(unsigned long data)
 646 {
 647         struct xgbe_channel *channel = (struct xgbe_channel *)data;
 648         struct xgbe_prv_data *pdata = channel->pdata;
 649         struct napi_struct *napi;
 650
 651         DBGPR("-->xgbe_tx_timer\n");
 652
 653         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 654
 655         if (napi_schedule_prep(napi)) {
 656                 /* Disable Tx and Rx interrupts */
 657                 if (pdata->per_channel_irq)
 658                         if (pdata->channel_irq_mode)
 659                                 xgbe_disable_rx_tx_int(pdata, channel);
 660                         else
 661                                 disable_irq_nosync(channel->dma_irq);
 662                 else
 663                         xgbe_disable_rx_tx_ints(pdata);
 664
 665                 /* Turn on polling */
 666                 __napi_schedule(napi);
 667         }
 668
 669         channel->tx_timer_active = 0;
 670
 671         DBGPR("<--xgbe_tx_timer\n");
 672 }
 673
 674 static void xgbe_service(struct work_struct *work)
 675 {
 676         struct xgbe_prv_data *pdata = container_of(work,
 677                                                    struct xgbe_prv_data,
 678                                                    service_work);
 679
 680         pdata->phy_if.phy_status(pdata);
 681 }
 682
 683 static void xgbe_service_timer(unsigned long data)
 684 {
 685         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 686
 687         queue_work(pdata->dev_workqueue, &pdata->service_work);
 688
 689         mod_timer(&pdata->service_timer, jiffies + HZ);
 690 }
 691
 692 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
 693 {
 694         struct xgbe_channel *channel;
 695         unsigned int i;
 696
 697         setup_timer(&pdata->service_timer, xgbe_service_timer,
 698                     (unsigned long)pdata);
 699
 700         for (i = 0; i < pdata->channel_count; i++) {
 701                 channel = pdata->channel[i];
 702                 if (!channel->tx_ring)
 703                         break;
 704
 705                 setup_timer(&channel->tx_timer, xgbe_tx_timer,
 706                             (unsigned long)channel);
 707         }
 708 }
 709
 710 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
 711 {
 712         mod_timer(&pdata->service_timer, jiffies + HZ);
 713 }
 714
 715 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
 716 {
 717         struct xgbe_channel *channel;
 718         unsigned int i;
 719
 720         del_timer_sync(&pdata->service_timer);
 721
 722         for (i = 0; i < pdata->channel_count; i++) {
 723                 channel = pdata->channel[i];
 724                 if (!channel->tx_ring)
 725                         break;
 726
 727                 del_timer_sync(&channel->tx_timer);
 728         }
 729 }
 730
 731 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 732 {
 733         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 734         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 735
 736         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 737         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 738         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 739
 740         memset(hw_feat, 0, sizeof(*hw_feat));
 741
 742         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 743
 744         /* Hardware feature register 0 */
 745         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 746         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 747         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 748         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 749         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 750         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 751         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 752         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 753         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 754         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 755         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 756         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 757                                               ADDMACADRSEL);
 758         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 759         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 760         hw_feat->vxn         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
 761
 762         /* Hardware feature register 1 */
 763         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 764                                                 RXFIFOSIZE);
 765         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 766                                                 TXFIFOSIZE);
 767         hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
 768         hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
 769         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 770         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 771         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 772         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 773         hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
 774         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 775         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 776                                                   HASHTBLSZ);
 777         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 778                                                   L3L4FNUM);
 779
 780         /* Hardware feature register 2 */
 781         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 782         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 783         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 784         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 785         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 786         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 787
 788         /* Translate the Hash Table size into actual number */
 789         switch (hw_feat->hash_table_size) {
 790         case 0:
 791                 break;
 792         case 1:
 793                 hw_feat->hash_table_size = 64;
 794                 break;
 795         case 2:
 796                 hw_feat->hash_table_size = 128;
 797                 break;
 798         case 3:
 799                 hw_feat->hash_table_size = 256;
 800                 break;
 801         }
 802
 803         /* Translate the address width setting into actual number */
 804         switch (hw_feat->dma_width) {
 805         case 0:
 806                 hw_feat->dma_width = 32;
 807                 break;
 808         case 1:
 809                 hw_feat->dma_width = 40;
 810                 break;
 811         case 2:
 812                 hw_feat->dma_width = 48;
 813                 break;
 814         default:
 815                 hw_feat->dma_width = 32;
 816         }
 817
 818         /* The Queue, Channel and TC counts are zero based so increment them
 819          * to get the actual number
 820          */
 821         hw_feat->rx_q_cnt++;
 822         hw_feat->tx_q_cnt++;
 823         hw_feat->rx_ch_cnt++;
 824         hw_feat->tx_ch_cnt++;
 825         hw_feat->tc_cnt++;
 826
 827         /* Translate the fifo sizes into actual numbers */
 828         hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
 829         hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
 830
 831         if (netif_msg_probe(pdata)) {
 832                 dev_dbg(pdata->dev, "Hardware features:\n");
 833
 834                 /* Hardware feature register 0 */
 835                 dev_dbg(pdata->dev, "  1GbE support              : %s\n",
 836                         hw_feat->gmii ? "yes" : "no");
 837                 dev_dbg(pdata->dev, "  VLAN hash filter          : %s\n",
 838                         hw_feat->vlhash ? "yes" : "no");
 839                 dev_dbg(pdata->dev, "  MDIO interface            : %s\n",
 840                         hw_feat->sma ? "yes" : "no");
 841                 dev_dbg(pdata->dev, "  Wake-up packet support    : %s\n",
 842                         hw_feat->rwk ? "yes" : "no");
 843                 dev_dbg(pdata->dev, "  Magic packet support      : %s\n",
 844                         hw_feat->mgk ? "yes" : "no");
 845                 dev_dbg(pdata->dev, "  Management counters       : %s\n",
 846                         hw_feat->mmc ? "yes" : "no");
 847                 dev_dbg(pdata->dev, "  ARP offload               : %s\n",
 848                         hw_feat->aoe ? "yes" : "no");
 849                 dev_dbg(pdata->dev, "  IEEE 1588-2008 Timestamp  : %s\n",
 850                         hw_feat->ts ? "yes" : "no");
 851                 dev_dbg(pdata->dev, "  Energy Efficient Ethernet : %s\n",
 852                         hw_feat->eee ? "yes" : "no");
 853                 dev_dbg(pdata->dev, "  TX checksum offload       : %s\n",
 854                         hw_feat->tx_coe ? "yes" : "no");
 855                 dev_dbg(pdata->dev, "  RX checksum offload       : %s\n",
 856                         hw_feat->rx_coe ? "yes" : "no");
 857                 dev_dbg(pdata->dev, "  Additional MAC addresses  : %u\n",
 858                         hw_feat->addn_mac);
 859                 dev_dbg(pdata->dev, "  Timestamp source          : %s\n",
 860                         (hw_feat->ts_src == 1) ? "internal" :
 861                         (hw_feat->ts_src == 2) ? "external" :
 862                         (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
 863                 dev_dbg(pdata->dev, "  SA/VLAN insertion         : %s\n",
 864                         hw_feat->sa_vlan_ins ? "yes" : "no");
 865                 dev_dbg(pdata->dev, "  VXLAN/NVGRE support       : %s\n",
 866                         hw_feat->vxn ? "yes" : "no");
 867
 868                 /* Hardware feature register 1 */
 869                 dev_dbg(pdata->dev, "  RX fifo size              : %u\n",
 870                         hw_feat->rx_fifo_size);
 871                 dev_dbg(pdata->dev, "  TX fifo size              : %u\n",
 872                         hw_feat->tx_fifo_size);
 873                 dev_dbg(pdata->dev, "  IEEE 1588 high word       : %s\n",
 874                         hw_feat->adv_ts_hi ? "yes" : "no");
 875                 dev_dbg(pdata->dev, "  DMA width                 : %u\n",
 876                         hw_feat->dma_width);
 877                 dev_dbg(pdata->dev, "  Data Center Bridging      : %s\n",
 878                         hw_feat->dcb ? "yes" : "no");
 879                 dev_dbg(pdata->dev, "  Split header              : %s\n",
 880                         hw_feat->sph ? "yes" : "no");
 881                 dev_dbg(pdata->dev, "  TCP Segmentation Offload  : %s\n",
 882                         hw_feat->tso ? "yes" : "no");
 883                 dev_dbg(pdata->dev, "  Debug memory interface    : %s\n",
 884                         hw_feat->dma_debug ? "yes" : "no");
 885                 dev_dbg(pdata->dev, "  Receive Side Scaling      : %s\n",
 886                         hw_feat->rss ? "yes" : "no");
 887                 dev_dbg(pdata->dev, "  Traffic Class count       : %u\n",
 888                         hw_feat->tc_cnt);
 889                 dev_dbg(pdata->dev, "  Hash table size           : %u\n",
 890                         hw_feat->hash_table_size);
 891                 dev_dbg(pdata->dev, "  L3/L4 Filters             : %u\n",
 892                         hw_feat->l3l4_filter_num);
 893
 894                 /* Hardware feature register 2 */
 895                 dev_dbg(pdata->dev, "  RX queue count            : %u\n",
 896                         hw_feat->rx_q_cnt);
 897                 dev_dbg(pdata->dev, "  TX queue count            : %u\n",
 898                         hw_feat->tx_q_cnt);
 899                 dev_dbg(pdata->dev, "  RX DMA channel count      : %u\n",
 900                         hw_feat->rx_ch_cnt);
 901                 dev_dbg(pdata->dev, "  TX DMA channel count      : %u\n",
 902                         hw_feat->rx_ch_cnt);
 903                 dev_dbg(pdata->dev, "  PPS outputs               : %u\n",
 904                         hw_feat->pps_out_num);
 905                 dev_dbg(pdata->dev, "  Auxiliary snapshot inputs : %u\n",
 906                         hw_feat->aux_snap_num);
 907         }
 908 }
 909
 910 static void xgbe_disable_vxlan_offloads(struct xgbe_prv_data *pdata)
 911 {
 912         struct net_device *netdev = pdata->netdev;
 913
 914         if (!pdata->vxlan_offloads_set)
 915                 return;
 916
 917         netdev_info(netdev, "disabling VXLAN offloads\n");
 918
 919         netdev->hw_enc_features &= ~(NETIF_F_SG |
 920                                      NETIF_F_IP_CSUM |
 921                                      NETIF_F_IPV6_CSUM |
 922                                      NETIF_F_RXCSUM |
 923                                      NETIF_F_TSO |
 924                                      NETIF_F_TSO6 |
 925                                      NETIF_F_GRO |
 926                                      NETIF_F_GSO_UDP_TUNNEL |
 927                                      NETIF_F_GSO_UDP_TUNNEL_CSUM);
 928
 929         netdev->features &= ~(NETIF_F_GSO_UDP_TUNNEL |
 930                               NETIF_F_GSO_UDP_TUNNEL_CSUM);
 931
 932         pdata->vxlan_offloads_set = 0;
 933 }
 934
 935 static void xgbe_disable_vxlan_hw(struct xgbe_prv_data *pdata)
 936 {
 937         if (!pdata->vxlan_port_set)
 938                 return;
 939
 940         pdata->hw_if.disable_vxlan(pdata);
 941
 942         pdata->vxlan_port_set = 0;
 943         pdata->vxlan_port = 0;
 944 }
 945
 946 static void xgbe_disable_vxlan_accel(struct xgbe_prv_data *pdata)
 947 {
 948         xgbe_disable_vxlan_offloads(pdata);
 949
 950         xgbe_disable_vxlan_hw(pdata);
 951 }
 952
 953 static void xgbe_enable_vxlan_offloads(struct xgbe_prv_data *pdata)
 954 {
 955         struct net_device *netdev = pdata->netdev;
 956
 957         if (pdata->vxlan_offloads_set)
 958                 return;
 959
 960         netdev_info(netdev, "enabling VXLAN offloads\n");
 961
 962         netdev->hw_enc_features |= NETIF_F_SG |
 963                                    NETIF_F_IP_CSUM |
 964                                    NETIF_F_IPV6_CSUM |
 965                                    NETIF_F_RXCSUM |
 966                                    NETIF_F_TSO |
 967                                    NETIF_F_TSO6 |
 968                                    NETIF_F_GRO |
 969                                    pdata->vxlan_features;
 970
 971         netdev->features |= pdata->vxlan_features;
 972
 973         pdata->vxlan_offloads_set = 1;
 974 }
 975
 976 static void xgbe_enable_vxlan_hw(struct xgbe_prv_data *pdata)
 977 {
 978         struct xgbe_vxlan_data *vdata;
 979
 980         if (pdata->vxlan_port_set)
 981                 return;
 982
 983         if (list_empty(&pdata->vxlan_ports))
 984                 return;
 985
 986         vdata = list_first_entry(&pdata->vxlan_ports,
 987                                  struct xgbe_vxlan_data, list);
 988
 989         pdata->vxlan_port_set = 1;
 990         pdata->vxlan_port = be16_to_cpu(vdata->port);
 991
 992         pdata->hw_if.enable_vxlan(pdata);
 993 }
 994
 995 static void xgbe_enable_vxlan_accel(struct xgbe_prv_data *pdata)
 996 {
 997         /* VXLAN acceleration desired? */
 998         if (!pdata->vxlan_features)
 999                 return;
1000
1001         /* VXLAN acceleration possible? */
1002         if (pdata->vxlan_force_disable)
1003                 return;
1004
1005         xgbe_enable_vxlan_hw(pdata);
1006
1007         xgbe_enable_vxlan_offloads(pdata);
1008 }
1009
1010 static void xgbe_reset_vxlan_accel(struct xgbe_prv_data *pdata)
1011 {
1012         xgbe_disable_vxlan_hw(pdata);
1013
1014         if (pdata->vxlan_features)
1015                 xgbe_enable_vxlan_offloads(pdata);
1016
1017         pdata->vxlan_force_disable = 0;
1018 }
1019
1020 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
1021 {
1022         struct xgbe_channel *channel;
1023         unsigned int i;
1024
1025         if (pdata->per_channel_irq) {
1026                 for (i = 0; i < pdata->channel_count; i++) {
1027                         channel = pdata->channel[i];
1028                         if (add)
1029                                 netif_napi_add(pdata->netdev, &channel->napi,
1030                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
1031
1032                         napi_enable(&channel->napi);
1033                 }
1034         } else {
1035                 if (add)
1036                         netif_napi_add(pdata->netdev, &pdata->napi,
1037                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
1038
1039                 napi_enable(&pdata->napi);
1040         }
1041 }
1042
1043 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
1044 {
1045         struct xgbe_channel *channel;
1046         unsigned int i;
1047
1048         if (pdata->per_channel_irq) {
1049                 for (i = 0; i < pdata->channel_count; i++) {
1050                         channel = pdata->channel[i];
1051                         napi_disable(&channel->napi);
1052
1053                         if (del)
1054                                 netif_napi_del(&channel->napi);
1055                 }
1056         } else {
1057                 napi_disable(&pdata->napi);
1058
1059                 if (del)
1060                         netif_napi_del(&pdata->napi);
1061         }
1062 }
1063
1064 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1065 {
1066         struct xgbe_channel *channel;
1067         struct net_device *netdev = pdata->netdev;
1068         unsigned int i;
1069         int ret;
1070
1071         tasklet_init(&pdata->tasklet_dev, xgbe_isr_task, (unsigned long)pdata);
1072         tasklet_init(&pdata->tasklet_ecc, xgbe_ecc_isr_task,
1073                      (unsigned long)pdata);
1074
1075         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1076                                netdev_name(netdev), pdata);
1077         if (ret) {
1078                 netdev_alert(netdev, "error requesting irq %d\n",
1079                              pdata->dev_irq);
1080                 return ret;
1081         }
1082
1083         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1084                 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1085                                        0, pdata->ecc_name, pdata);
1086                 if (ret) {
1087                         netdev_alert(netdev, "error requesting ecc irq %d\n",
1088                                      pdata->ecc_irq);
1089                         goto err_dev_irq;
1090                 }
1091         }
1092
1093         if (!pdata->per_channel_irq)
1094                 return 0;
1095
1096         for (i = 0; i < pdata->channel_count; i++) {
1097                 channel = pdata->channel[i];
1098                 snprintf(channel->dma_irq_name,
1099                          sizeof(channel->dma_irq_name) - 1,
1100                          "%s-TxRx-%u", netdev_name(netdev),
1101                          channel->queue_index);
1102
1103                 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1104                                        xgbe_dma_isr, 0,
1105                                        channel->dma_irq_name, channel);
1106                 if (ret) {
1107                         netdev_alert(netdev, "error requesting irq %d\n",
1108                                      channel->dma_irq);
1109                         goto err_dma_irq;
1110                 }
1111
1112                 irq_set_affinity_hint(channel->dma_irq,
1113                                       &channel->affinity_mask);
1114         }
1115
1116         return 0;
1117
1118 err_dma_irq:
1119         /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1120         for (i--; i < pdata->channel_count; i--) {
1121                 channel = pdata->channel[i];
1122
1123                 irq_set_affinity_hint(channel->dma_irq, NULL);
1124                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1125         }
1126
1127         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1128                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1129
1130 err_dev_irq:
1131         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1132
1133         return ret;
1134 }
1135
1136 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1137 {
1138         struct xgbe_channel *channel;
1139         unsigned int i;
1140
1141         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1142
1143         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1144                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1145
1146         if (!pdata->per_channel_irq)
1147                 return;
1148
1149         for (i = 0; i < pdata->channel_count; i++) {
1150                 channel = pdata->channel[i];
1151
1152                 irq_set_affinity_hint(channel->dma_irq, NULL);
1153                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1154         }
1155 }
1156
1157 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1158 {
1159         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1160
1161         DBGPR("-->xgbe_init_tx_coalesce\n");
1162
1163         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1164         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1165
1166         hw_if->config_tx_coalesce(pdata);
1167
1168         DBGPR("<--xgbe_init_tx_coalesce\n");
1169 }
1170
1171 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1172 {
1173         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1174
1175         DBGPR("-->xgbe_init_rx_coalesce\n");
1176
1177         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1178         pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1179         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1180
1181         hw_if->config_rx_coalesce(pdata);
1182
1183         DBGPR("<--xgbe_init_rx_coalesce\n");
1184 }
1185
1186 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1187 {
1188         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1189         struct xgbe_ring *ring;
1190         struct xgbe_ring_data *rdata;
1191         unsigned int i, j;
1192
1193         DBGPR("-->xgbe_free_tx_data\n");
1194
1195         for (i = 0; i < pdata->channel_count; i++) {
1196                 ring = pdata->channel[i]->tx_ring;
1197                 if (!ring)
1198                         break;
1199
1200                 for (j = 0; j < ring->rdesc_count; j++) {
1201                         rdata = XGBE_GET_DESC_DATA(ring, j);
1202                         desc_if->unmap_rdata(pdata, rdata);
1203                 }
1204         }
1205
1206         DBGPR("<--xgbe_free_tx_data\n");
1207 }
1208
1209 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1210 {
1211         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1212         struct xgbe_ring *ring;
1213         struct xgbe_ring_data *rdata;
1214         unsigned int i, j;
1215
1216         DBGPR("-->xgbe_free_rx_data\n");
1217
1218         for (i = 0; i < pdata->channel_count; i++) {
1219                 ring = pdata->channel[i]->rx_ring;
1220                 if (!ring)
1221                         break;
1222
1223                 for (j = 0; j < ring->rdesc_count; j++) {
1224                         rdata = XGBE_GET_DESC_DATA(ring, j);
1225                         desc_if->unmap_rdata(pdata, rdata);
1226                 }
1227         }
1228
1229         DBGPR("<--xgbe_free_rx_data\n");
1230 }
1231
1232 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1233 {
1234         pdata->phy_link = -1;
1235         pdata->phy_speed = SPEED_UNKNOWN;
1236
1237         return pdata->phy_if.phy_reset(pdata);
1238 }
1239
1240 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1241 {
1242         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1243         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1244         unsigned long flags;
1245
1246         DBGPR("-->xgbe_powerdown\n");
1247
1248         if (!netif_running(netdev) ||
1249             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1250                 netdev_alert(netdev, "Device is already powered down\n");
1251                 DBGPR("<--xgbe_powerdown\n");
1252                 return -EINVAL;
1253         }
1254
1255         spin_lock_irqsave(&pdata->lock, flags);
1256
1257         if (caller == XGMAC_DRIVER_CONTEXT)
1258                 netif_device_detach(netdev);
1259
1260         netif_tx_stop_all_queues(netdev);
1261
1262         xgbe_stop_timers(pdata);
1263         flush_workqueue(pdata->dev_workqueue);
1264
1265         hw_if->powerdown_tx(pdata);
1266         hw_if->powerdown_rx(pdata);
1267
1268         xgbe_napi_disable(pdata, 0);
1269
1270         pdata->power_down = 1;
1271
1272         spin_unlock_irqrestore(&pdata->lock, flags);
1273
1274         DBGPR("<--xgbe_powerdown\n");
1275
1276         return 0;
1277 }
1278
1279 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1280 {
1281         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1282         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1283         unsigned long flags;
1284
1285         DBGPR("-->xgbe_powerup\n");
1286
1287         if (!netif_running(netdev) ||
1288             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1289                 netdev_alert(netdev, "Device is already powered up\n");
1290                 DBGPR("<--xgbe_powerup\n");
1291                 return -EINVAL;
1292         }
1293
1294         spin_lock_irqsave(&pdata->lock, flags);
1295
1296         pdata->power_down = 0;
1297
1298         xgbe_napi_enable(pdata, 0);
1299
1300         hw_if->powerup_tx(pdata);
1301         hw_if->powerup_rx(pdata);
1302
1303         if (caller == XGMAC_DRIVER_CONTEXT)
1304                 netif_device_attach(netdev);
1305
1306         netif_tx_start_all_queues(netdev);
1307
1308         xgbe_start_timers(pdata);
1309
1310         spin_unlock_irqrestore(&pdata->lock, flags);
1311
1312         DBGPR("<--xgbe_powerup\n");
1313
1314         return 0;
1315 }
1316
1317 static int xgbe_start(struct xgbe_prv_data *pdata)
1318 {
1319         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1320         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1321         struct net_device *netdev = pdata->netdev;
1322         int ret;
1323
1324         DBGPR("-->xgbe_start\n");
1325
1326         ret = hw_if->init(pdata);
1327         if (ret)
1328                 return ret;
1329
1330         xgbe_napi_enable(pdata, 1);
1331
1332         ret = xgbe_request_irqs(pdata);
1333         if (ret)
1334                 goto err_napi;
1335
1336         ret = phy_if->phy_start(pdata);
1337         if (ret)
1338                 goto err_irqs;
1339
1340         hw_if->enable_tx(pdata);
1341         hw_if->enable_rx(pdata);
1342
1343         udp_tunnel_get_rx_info(netdev);
1344
1345         netif_tx_start_all_queues(netdev);
1346
1347         xgbe_start_timers(pdata);
1348         queue_work(pdata->dev_workqueue, &pdata->service_work);
1349
1350         clear_bit(XGBE_STOPPED, &pdata->dev_state);
1351
1352         DBGPR("<--xgbe_start\n");
1353
1354         return 0;
1355
1356 err_irqs:
1357         xgbe_free_irqs(pdata);
1358
1359 err_napi:
1360         xgbe_napi_disable(pdata, 1);
1361
1362         hw_if->exit(pdata);
1363
1364         return ret;
1365 }
1366
1367 static void xgbe_stop(struct xgbe_prv_data *pdata)
1368 {
1369         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1370         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1371         struct xgbe_channel *channel;
1372         struct net_device *netdev = pdata->netdev;
1373         struct netdev_queue *txq;
1374         unsigned int i;
1375
1376         DBGPR("-->xgbe_stop\n");
1377
1378         if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1379                 return;
1380
1381         netif_tx_stop_all_queues(netdev);
1382
1383         xgbe_stop_timers(pdata);
1384         flush_workqueue(pdata->dev_workqueue);
1385
1386         xgbe_reset_vxlan_accel(pdata);
1387
1388         hw_if->disable_tx(pdata);
1389         hw_if->disable_rx(pdata);
1390
1391         phy_if->phy_stop(pdata);
1392
1393         xgbe_free_irqs(pdata);
1394
1395         xgbe_napi_disable(pdata, 1);
1396
1397         hw_if->exit(pdata);
1398
1399         for (i = 0; i < pdata->channel_count; i++) {
1400                 channel = pdata->channel[i];
1401                 if (!channel->tx_ring)
1402                         continue;
1403
1404                 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1405                 netdev_tx_reset_queue(txq);
1406         }
1407
1408         set_bit(XGBE_STOPPED, &pdata->dev_state);
1409
1410         DBGPR("<--xgbe_stop\n");
1411 }
1412
1413 static void xgbe_stopdev(struct work_struct *work)
1414 {
1415         struct xgbe_prv_data *pdata = container_of(work,
1416                                                    struct xgbe_prv_data,
1417                                                    stopdev_work);
1418
1419         rtnl_lock();
1420
1421         xgbe_stop(pdata);
1422
1423         xgbe_free_tx_data(pdata);
1424         xgbe_free_rx_data(pdata);
1425
1426         rtnl_unlock();
1427
1428         netdev_alert(pdata->netdev, "device stopped\n");
1429 }
1430
1431 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1432 {
1433         DBGPR("-->xgbe_restart_dev\n");
1434
1435         /* If not running, "restart" will happen on open */
1436         if (!netif_running(pdata->netdev))
1437                 return;
1438
1439         xgbe_stop(pdata);
1440
1441         xgbe_free_tx_data(pdata);
1442         xgbe_free_rx_data(pdata);
1443
1444         xgbe_start(pdata);
1445
1446         DBGPR("<--xgbe_restart_dev\n");
1447 }
1448
1449 static void xgbe_restart(struct work_struct *work)
1450 {
1451         struct xgbe_prv_data *pdata = container_of(work,
1452                                                    struct xgbe_prv_data,
1453                                                    restart_work);
1454
1455         rtnl_lock();
1456
1457         xgbe_restart_dev(pdata);
1458
1459         rtnl_unlock();
1460 }
1461
1462 static void xgbe_tx_tstamp(struct work_struct *work)
1463 {
1464         struct xgbe_prv_data *pdata = container_of(work,
1465                                                    struct xgbe_prv_data,
1466                                                    tx_tstamp_work);
1467         struct skb_shared_hwtstamps hwtstamps;
1468         u64 nsec;
1469         unsigned long flags;
1470
1471         spin_lock_irqsave(&pdata->tstamp_lock, flags);
1472         if (!pdata->tx_tstamp_skb)
1473                 goto unlock;
1474
1475         if (pdata->tx_tstamp) {
1476                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1477                                             pdata->tx_tstamp);
1478
1479                 memset(&hwtstamps, 0, sizeof(hwtstamps));
1480                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1481                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1482         }
1483
1484         dev_kfree_skb_any(pdata->tx_tstamp_skb);
1485
1486         pdata->tx_tstamp_skb = NULL;
1487
1488 unlock:
1489         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1490 }
1491
1492 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1493                                       struct ifreq *ifreq)
1494 {
1495         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1496                          sizeof(pdata->tstamp_config)))
1497                 return -EFAULT;
1498
1499         return 0;
1500 }
1501
1502 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1503                                       struct ifreq *ifreq)
1504 {
1505         struct hwtstamp_config config;
1506         unsigned int mac_tscr;
1507
1508         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1509                 return -EFAULT;
1510
1511         if (config.flags)
1512                 return -EINVAL;
1513
1514         mac_tscr = 0;
1515
1516         switch (config.tx_type) {
1517         case HWTSTAMP_TX_OFF:
1518                 break;
1519
1520         case HWTSTAMP_TX_ON:
1521                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1522                 break;
1523
1524         default:
1525                 return -ERANGE;
1526         }
1527
1528         switch (config.rx_filter) {
1529         case HWTSTAMP_FILTER_NONE:
1530                 break;
1531
1532         case HWTSTAMP_FILTER_NTP_ALL:
1533         case HWTSTAMP_FILTER_ALL:
1534                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1535                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1536                 break;
1537
1538         /* PTP v2, UDP, any kind of event packet */
1539         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1540                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1541         /* PTP v1, UDP, any kind of event packet */
1542         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1543                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1544                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1545                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1546                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1547                 break;
1548
1549         /* PTP v2, UDP, Sync packet */
1550         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1551                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1552         /* PTP v1, UDP, Sync packet */
1553         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1554                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1555                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1556                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1557                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1558                 break;
1559
1560         /* PTP v2, UDP, Delay_req packet */
1561         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1562                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1563         /* PTP v1, UDP, Delay_req packet */
1564         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1565                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1566                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1567                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1568                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1569                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1570                 break;
1571
1572         /* 802.AS1, Ethernet, any kind of event packet */
1573         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1574                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1575                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1576                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1577                 break;
1578
1579         /* 802.AS1, Ethernet, Sync packet */
1580         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1581                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1582                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1583                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1584                 break;
1585
1586         /* 802.AS1, Ethernet, Delay_req packet */
1587         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1588                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1589                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1590                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1591                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1592                 break;
1593
1594         /* PTP v2/802.AS1, any layer, any kind of event packet */
1595         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1596                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1597                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1598                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1599                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1600                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1601                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1602                 break;
1603
1604         /* PTP v2/802.AS1, any layer, Sync packet */
1605         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1606                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1607                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1608                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1609                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1610                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1611                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1612                 break;
1613
1614         /* PTP v2/802.AS1, any layer, Delay_req packet */
1615         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1616                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1617                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1618                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1619                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1620                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1621                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1622                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1623                 break;
1624
1625         default:
1626                 return -ERANGE;
1627         }
1628
1629         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1630
1631         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1632
1633         return 0;
1634 }
1635
1636 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1637                                 struct sk_buff *skb,
1638                                 struct xgbe_packet_data *packet)
1639 {
1640         unsigned long flags;
1641
1642         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1643                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1644                 if (pdata->tx_tstamp_skb) {
1645                         /* Another timestamp in progress, ignore this one */
1646                         XGMAC_SET_BITS(packet->attributes,
1647                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1648                 } else {
1649                         pdata->tx_tstamp_skb = skb_get(skb);
1650                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1651                 }
1652                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1653         }
1654
1655         skb_tx_timestamp(skb);
1656 }
1657
1658 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1659 {
1660         if (skb_vlan_tag_present(skb))
1661                 packet->vlan_ctag = skb_vlan_tag_get(skb);
1662 }
1663
1664 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1665 {
1666         int ret;
1667
1668         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1669                             TSO_ENABLE))
1670                 return 0;
1671
1672         ret = skb_cow_head(skb, 0);
1673         if (ret)
1674                 return ret;
1675
1676         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1677                 packet->header_len = skb_inner_transport_offset(skb) +
1678                                      inner_tcp_hdrlen(skb);
1679                 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1680         } else {
1681                 packet->header_len = skb_transport_offset(skb) +
1682                                      tcp_hdrlen(skb);
1683                 packet->tcp_header_len = tcp_hdrlen(skb);
1684         }
1685         packet->tcp_payload_len = skb->len - packet->header_len;
1686         packet->mss = skb_shinfo(skb)->gso_size;
1687
1688         DBGPR("  packet->header_len=%u\n", packet->header_len);
1689         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1690               packet->tcp_header_len, packet->tcp_payload_len);
1691         DBGPR("  packet->mss=%u\n", packet->mss);
1692
1693         /* Update the number of packets that will ultimately be transmitted
1694          * along with the extra bytes for each extra packet
1695          */
1696         packet->tx_packets = skb_shinfo(skb)->gso_segs;
1697         packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1698
1699         return 0;
1700 }
1701
1702 static bool xgbe_is_vxlan(struct xgbe_prv_data *pdata, struct sk_buff *skb)
1703 {
1704         struct xgbe_vxlan_data *vdata;
1705
1706         if (pdata->vxlan_force_disable)
1707                 return false;
1708
1709         if (!skb->encapsulation)
1710                 return false;
1711
1712         if (skb->ip_summed != CHECKSUM_PARTIAL)
1713                 return false;
1714
1715         switch (skb->protocol) {
1716         case htons(ETH_P_IP):
1717                 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1718                         return false;
1719                 break;
1720
1721         case htons(ETH_P_IPV6):
1722                 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1723                         return false;
1724                 break;
1725
1726         default:
1727                 return false;
1728         }
1729
1730         /* See if we have the UDP port in our list */
1731         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
1732                 if ((skb->protocol == htons(ETH_P_IP)) &&
1733                     (vdata->sa_family == AF_INET) &&
1734                     (vdata->port == udp_hdr(skb)->dest))
1735                         return true;
1736                 else if ((skb->protocol == htons(ETH_P_IPV6)) &&
1737                          (vdata->sa_family == AF_INET6) &&
1738                          (vdata->port == udp_hdr(skb)->dest))
1739                         return true;
1740         }
1741
1742         return false;
1743 }
1744
1745 static int xgbe_is_tso(struct sk_buff *skb)
1746 {
1747         if (skb->ip_summed != CHECKSUM_PARTIAL)
1748                 return 0;
1749
1750         if (!skb_is_gso(skb))
1751                 return 0;
1752
1753         DBGPR("  TSO packet to be processed\n");
1754
1755         return 1;
1756 }
1757
1758 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1759                              struct xgbe_ring *ring, struct sk_buff *skb,
1760                              struct xgbe_packet_data *packet)
1761 {
1762         struct skb_frag_struct *frag;
1763         unsigned int context_desc;
1764         unsigned int len;
1765         unsigned int i;
1766
1767         packet->skb = skb;
1768
1769         context_desc = 0;
1770         packet->rdesc_count = 0;
1771
1772         packet->tx_packets = 1;
1773         packet->tx_bytes = skb->len;
1774
1775         if (xgbe_is_tso(skb)) {
1776                 /* TSO requires an extra descriptor if mss is different */
1777                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1778                         context_desc = 1;
1779                         packet->rdesc_count++;
1780                 }
1781
1782                 /* TSO requires an extra descriptor for TSO header */
1783                 packet->rdesc_count++;
1784
1785                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1786                                TSO_ENABLE, 1);
1787                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1788                                CSUM_ENABLE, 1);
1789         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1790                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1791                                CSUM_ENABLE, 1);
1792
1793         if (xgbe_is_vxlan(pdata, skb))
1794                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1795                                VXLAN, 1);
1796
1797         if (skb_vlan_tag_present(skb)) {
1798                 /* VLAN requires an extra descriptor if tag is different */
1799                 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1800                         /* We can share with the TSO context descriptor */
1801                         if (!context_desc) {
1802                                 context_desc = 1;
1803                                 packet->rdesc_count++;
1804                         }
1805
1806                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1807                                VLAN_CTAG, 1);
1808         }
1809
1810         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1811             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1812                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1813                                PTP, 1);
1814
1815         for (len = skb_headlen(skb); len;) {
1816                 packet->rdesc_count++;
1817                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1818         }
1819
1820         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1821                 frag = &skb_shinfo(skb)->frags[i];
1822                 for (len = skb_frag_size(frag); len; ) {
1823                         packet->rdesc_count++;
1824                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1825                 }
1826         }
1827 }
1828
1829 static int xgbe_open(struct net_device *netdev)
1830 {
1831         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1832         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1833         int ret;
1834
1835         DBGPR("-->xgbe_open\n");
1836
1837         /* Create the various names based on netdev name */
1838         snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1839                  netdev_name(netdev));
1840
1841         snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1842                  netdev_name(netdev));
1843
1844         snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1845                  netdev_name(netdev));
1846
1847         /* Create workqueues */
1848         pdata->dev_workqueue =
1849                 create_singlethread_workqueue(netdev_name(netdev));
1850         if (!pdata->dev_workqueue) {
1851                 netdev_err(netdev, "device workqueue creation failed\n");
1852                 return -ENOMEM;
1853         }
1854
1855         pdata->an_workqueue =
1856                 create_singlethread_workqueue(pdata->an_name);
1857         if (!pdata->an_workqueue) {
1858                 netdev_err(netdev, "phy workqueue creation failed\n");
1859                 ret = -ENOMEM;
1860                 goto err_dev_wq;
1861         }
1862
1863         /* Reset the phy settings */
1864         ret = xgbe_phy_reset(pdata);
1865         if (ret)
1866                 goto err_an_wq;
1867
1868         /* Enable the clocks */
1869         ret = clk_prepare_enable(pdata->sysclk);
1870         if (ret) {
1871                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1872                 goto err_an_wq;
1873         }
1874
1875         ret = clk_prepare_enable(pdata->ptpclk);
1876         if (ret) {
1877                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1878                 goto err_sysclk;
1879         }
1880
1881         /* Calculate the Rx buffer size before allocating rings */
1882         ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1883         if (ret < 0)
1884                 goto err_ptpclk;
1885         pdata->rx_buf_size = ret;
1886
1887         /* Allocate the channel and ring structures */
1888         ret = xgbe_alloc_channels(pdata);
1889         if (ret)
1890                 goto err_ptpclk;
1891
1892         /* Allocate the ring descriptors and buffers */
1893         ret = desc_if->alloc_ring_resources(pdata);
1894         if (ret)
1895                 goto err_channels;
1896
1897         INIT_WORK(&pdata->service_work, xgbe_service);
1898         INIT_WORK(&pdata->restart_work, xgbe_restart);
1899         INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1900         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1901         xgbe_init_timers(pdata);
1902
1903         ret = xgbe_start(pdata);
1904         if (ret)
1905                 goto err_rings;
1906
1907         clear_bit(XGBE_DOWN, &pdata->dev_state);
1908
1909         DBGPR("<--xgbe_open\n");
1910
1911         return 0;
1912
1913 err_rings:
1914         desc_if->free_ring_resources(pdata);
1915
1916 err_channels:
1917         xgbe_free_channels(pdata);
1918
1919 err_ptpclk:
1920         clk_disable_unprepare(pdata->ptpclk);
1921
1922 err_sysclk:
1923         clk_disable_unprepare(pdata->sysclk);
1924
1925 err_an_wq:
1926         destroy_workqueue(pdata->an_workqueue);
1927
1928 err_dev_wq:
1929         destroy_workqueue(pdata->dev_workqueue);
1930
1931         return ret;
1932 }
1933
1934 static int xgbe_close(struct net_device *netdev)
1935 {
1936         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1937         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1938
1939         DBGPR("-->xgbe_close\n");
1940
1941         /* Stop the device */
1942         xgbe_stop(pdata);
1943
1944         /* Free the ring descriptors and buffers */
1945         desc_if->free_ring_resources(pdata);
1946
1947         /* Free the channel and ring structures */
1948         xgbe_free_channels(pdata);
1949
1950         /* Disable the clocks */
1951         clk_disable_unprepare(pdata->ptpclk);
1952         clk_disable_unprepare(pdata->sysclk);
1953
1954         flush_workqueue(pdata->an_workqueue);
1955         destroy_workqueue(pdata->an_workqueue);
1956
1957         flush_workqueue(pdata->dev_workqueue);
1958         destroy_workqueue(pdata->dev_workqueue);
1959
1960         set_bit(XGBE_DOWN, &pdata->dev_state);
1961
1962         DBGPR("<--xgbe_close\n");
1963
1964         return 0;
1965 }
1966
1967 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1968 {
1969         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1970         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1971         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1972         struct xgbe_channel *channel;
1973         struct xgbe_ring *ring;
1974         struct xgbe_packet_data *packet;
1975         struct netdev_queue *txq;
1976         netdev_tx_t ret;
1977
1978         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1979
1980         channel = pdata->channel[skb->queue_mapping];
1981         txq = netdev_get_tx_queue(netdev, channel->queue_index);
1982         ring = channel->tx_ring;
1983         packet = &ring->packet_data;
1984
1985         ret = NETDEV_TX_OK;
1986
1987         if (skb->len == 0) {
1988                 netif_err(pdata, tx_err, netdev,
1989                           "empty skb received from stack\n");
1990                 dev_kfree_skb_any(skb);
1991                 goto tx_netdev_return;
1992         }
1993
1994         /* Calculate preliminary packet info */
1995         memset(packet, 0, sizeof(*packet));
1996         xgbe_packet_info(pdata, ring, skb, packet);
1997
1998         /* Check that there are enough descriptors available */
1999         ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
2000         if (ret)
2001                 goto tx_netdev_return;
2002
2003         ret = xgbe_prep_tso(skb, packet);
2004         if (ret) {
2005                 netif_err(pdata, tx_err, netdev,
2006                           "error processing TSO packet\n");
2007                 dev_kfree_skb_any(skb);
2008                 goto tx_netdev_return;
2009         }
2010         xgbe_prep_vlan(skb, packet);
2011
2012         if (!desc_if->map_tx_skb(channel, skb)) {
2013                 dev_kfree_skb_any(skb);
2014                 goto tx_netdev_return;
2015         }
2016
2017         xgbe_prep_tx_tstamp(pdata, skb, packet);
2018
2019         /* Report on the actual number of bytes (to be) sent */
2020         netdev_tx_sent_queue(txq, packet->tx_bytes);
2021
2022         /* Configure required descriptor fields for transmission */
2023         hw_if->dev_xmit(channel);
2024
2025         if (netif_msg_pktdata(pdata))
2026                 xgbe_print_pkt(netdev, skb, true);
2027
2028         /* Stop the queue in advance if there may not be enough descriptors */
2029         xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2030
2031         ret = NETDEV_TX_OK;
2032
2033 tx_netdev_return:
2034         return ret;
2035 }
2036
2037 static void xgbe_set_rx_mode(struct net_device *netdev)
2038 {
2039         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2040         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2041
2042         DBGPR("-->xgbe_set_rx_mode\n");
2043
2044         hw_if->config_rx_mode(pdata);
2045
2046         DBGPR("<--xgbe_set_rx_mode\n");
2047 }
2048
2049 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2050 {
2051         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2052         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2053         struct sockaddr *saddr = addr;
2054
2055         DBGPR("-->xgbe_set_mac_address\n");
2056
2057         if (!is_valid_ether_addr(saddr->sa_data))
2058                 return -EADDRNOTAVAIL;
2059
2060         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2061
2062         hw_if->set_mac_address(pdata, netdev->dev_addr);
2063
2064         DBGPR("<--xgbe_set_mac_address\n");
2065
2066         return 0;
2067 }
2068
2069 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2070 {
2071         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2072         int ret;
2073
2074         switch (cmd) {
2075         case SIOCGHWTSTAMP:
2076                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2077                 break;
2078
2079         case SIOCSHWTSTAMP:
2080                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2081                 break;
2082
2083         default:
2084                 ret = -EOPNOTSUPP;
2085         }
2086
2087         return ret;
2088 }
2089
2090 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2091 {
2092         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2093         int ret;
2094
2095         DBGPR("-->xgbe_change_mtu\n");
2096
2097         ret = xgbe_calc_rx_buf_size(netdev, mtu);
2098         if (ret < 0)
2099                 return ret;
2100
2101         pdata->rx_buf_size = ret;
2102         netdev->mtu = mtu;
2103
2104         xgbe_restart_dev(pdata);
2105
2106         DBGPR("<--xgbe_change_mtu\n");
2107
2108         return 0;
2109 }
2110
2111 static void xgbe_tx_timeout(struct net_device *netdev)
2112 {
2113         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2114
2115         netdev_warn(netdev, "tx timeout, device restarting\n");
2116         schedule_work(&pdata->restart_work);
2117 }
2118
2119 static void xgbe_get_stats64(struct net_device *netdev,
2120                              struct rtnl_link_stats64 *s)
2121 {
2122         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2123         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2124
2125         DBGPR("-->%s\n", __func__);
2126
2127         pdata->hw_if.read_mmc_stats(pdata);
2128
2129         s->rx_packets = pstats->rxframecount_gb;
2130         s->rx_bytes = pstats->rxoctetcount_gb;
2131         s->rx_errors = pstats->rxframecount_gb -
2132                        pstats->rxbroadcastframes_g -
2133                        pstats->rxmulticastframes_g -
2134                        pstats->rxunicastframes_g;
2135         s->multicast = pstats->rxmulticastframes_g;
2136         s->rx_length_errors = pstats->rxlengtherror;
2137         s->rx_crc_errors = pstats->rxcrcerror;
2138         s->rx_fifo_errors = pstats->rxfifooverflow;
2139
2140         s->tx_packets = pstats->txframecount_gb;
2141         s->tx_bytes = pstats->txoctetcount_gb;
2142         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2143         s->tx_dropped = netdev->stats.tx_dropped;
2144
2145         DBGPR("<--%s\n", __func__);
2146 }
2147
2148 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2149                                 u16 vid)
2150 {
2151         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2152         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2153
2154         DBGPR("-->%s\n", __func__);
2155
2156         set_bit(vid, pdata->active_vlans);
2157         hw_if->update_vlan_hash_table(pdata);
2158
2159         DBGPR("<--%s\n", __func__);
2160
2161         return 0;
2162 }
2163
2164 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2165                                  u16 vid)
2166 {
2167         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2168         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2169
2170         DBGPR("-->%s\n", __func__);
2171
2172         clear_bit(vid, pdata->active_vlans);
2173         hw_if->update_vlan_hash_table(pdata);
2174
2175         DBGPR("<--%s\n", __func__);
2176
2177         return 0;
2178 }
2179
2180 #ifdef CONFIG_NET_POLL_CONTROLLER
2181 static void xgbe_poll_controller(struct net_device *netdev)
2182 {
2183         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2184         struct xgbe_channel *channel;
2185         unsigned int i;
2186
2187         DBGPR("-->xgbe_poll_controller\n");
2188
2189         if (pdata->per_channel_irq) {
2190                 for (i = 0; i < pdata->channel_count; i++) {
2191                         channel = pdata->channel[i];
2192                         xgbe_dma_isr(channel->dma_irq, channel);
2193                 }
2194         } else {
2195                 disable_irq(pdata->dev_irq);
2196                 xgbe_isr(pdata->dev_irq, pdata);
2197                 enable_irq(pdata->dev_irq);
2198         }
2199
2200         DBGPR("<--xgbe_poll_controller\n");
2201 }
2202 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2203
2204 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2205                          void *type_data)
2206 {
2207         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2208         struct tc_mqprio_qopt *mqprio = type_data;
2209         u8 tc;
2210
2211         if (type != TC_SETUP_MQPRIO)
2212                 return -EOPNOTSUPP;
2213
2214         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2215         tc = mqprio->num_tc;
2216
2217         if (tc > pdata->hw_feat.tc_cnt)
2218                 return -EINVAL;
2219
2220         pdata->num_tcs = tc;
2221         pdata->hw_if.config_tc(pdata);
2222
2223         return 0;
2224 }
2225
2226 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2227                                            netdev_features_t features)
2228 {
2229         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2230         netdev_features_t vxlan_base, vxlan_mask;
2231
2232         vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2233         vxlan_mask = vxlan_base | NETIF_F_GSO_UDP_TUNNEL_CSUM;
2234
2235         pdata->vxlan_features = features & vxlan_mask;
2236
2237         /* Only fix VXLAN-related features */
2238         if (!pdata->vxlan_features)
2239                 return features;
2240
2241         /* If VXLAN isn't supported then clear any features:
2242          *   This is needed because NETIF_F_RX_UDP_TUNNEL_PORT gets
2243          *   automatically set if ndo_udp_tunnel_add is set.
2244          */
2245         if (!pdata->hw_feat.vxn)
2246                 return features & ~vxlan_mask;
2247
2248         /* VXLAN CSUM requires VXLAN base */
2249         if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2250             !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2251                 netdev_notice(netdev,
2252                               "forcing tx udp tunnel support\n");
2253                 features |= NETIF_F_GSO_UDP_TUNNEL;
2254         }
2255
2256         /* Can't do one without doing the other */
2257         if ((features & vxlan_base) != vxlan_base) {
2258                 netdev_notice(netdev,
2259                               "forcing both tx and rx udp tunnel support\n");
2260                 features |= vxlan_base;
2261         }
2262
2263         if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2264                 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2265                         netdev_notice(netdev,
2266                                       "forcing tx udp tunnel checksumming on\n");
2267                         features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2268                 }
2269         } else {
2270                 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2271                         netdev_notice(netdev,
2272                                       "forcing tx udp tunnel checksumming off\n");
2273                         features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2274                 }
2275         }
2276
2277         pdata->vxlan_features = features & vxlan_mask;
2278
2279         /* Adjust UDP Tunnel based on current state */
2280         if (pdata->vxlan_force_disable) {
2281                 netdev_notice(netdev,
2282                               "VXLAN acceleration disabled, turning off udp tunnel features\n");
2283                 features &= ~vxlan_mask;
2284         }
2285
2286         return features;
2287 }
2288
2289 static int xgbe_set_features(struct net_device *netdev,
2290                              netdev_features_t features)
2291 {
2292         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2293         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2294         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2295         netdev_features_t udp_tunnel;
2296         int ret = 0;
2297
2298         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2299         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2300         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2301         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2302         udp_tunnel = pdata->netdev_features & NETIF_F_GSO_UDP_TUNNEL;
2303
2304         if ((features & NETIF_F_RXHASH) && !rxhash)
2305                 ret = hw_if->enable_rss(pdata);
2306         else if (!(features & NETIF_F_RXHASH) && rxhash)
2307                 ret = hw_if->disable_rss(pdata);
2308         if (ret)
2309                 return ret;
2310
2311         if ((features & NETIF_F_RXCSUM) && !rxcsum)
2312                 hw_if->enable_rx_csum(pdata);
2313         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2314                 hw_if->disable_rx_csum(pdata);
2315
2316         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2317                 hw_if->enable_rx_vlan_stripping(pdata);
2318         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2319                 hw_if->disable_rx_vlan_stripping(pdata);
2320
2321         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2322                 hw_if->enable_rx_vlan_filtering(pdata);
2323         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2324                 hw_if->disable_rx_vlan_filtering(pdata);
2325
2326         if ((features & NETIF_F_GSO_UDP_TUNNEL) && !udp_tunnel)
2327                 xgbe_enable_vxlan_accel(pdata);
2328         else if (!(features & NETIF_F_GSO_UDP_TUNNEL) && udp_tunnel)
2329                 xgbe_disable_vxlan_accel(pdata);
2330
2331         pdata->netdev_features = features;
2332
2333         DBGPR("<--xgbe_set_features\n");
2334
2335         return 0;
2336 }
2337
2338 static void xgbe_udp_tunnel_add(struct net_device *netdev,
2339                                 struct udp_tunnel_info *ti)
2340 {
2341         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2342         struct xgbe_vxlan_data *vdata;
2343
2344         if (!pdata->hw_feat.vxn)
2345                 return;
2346
2347         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2348                 return;
2349
2350         pdata->vxlan_port_count++;
2351
2352         netif_dbg(pdata, drv, netdev,
2353                   "adding VXLAN tunnel, family=%hx/port=%hx\n",
2354                   ti->sa_family, be16_to_cpu(ti->port));
2355
2356         if (pdata->vxlan_force_disable)
2357                 return;
2358
2359         vdata = kzalloc(sizeof(*vdata), GFP_ATOMIC);
2360         if (!vdata) {
2361                 /* Can no longer properly track VXLAN ports */
2362                 pdata->vxlan_force_disable = 1;
2363                 netif_dbg(pdata, drv, netdev,
2364                           "internal error, disabling VXLAN accelerations\n");
2365
2366                 xgbe_disable_vxlan_accel(pdata);
2367
2368                 return;
2369         }
2370         vdata->sa_family = ti->sa_family;
2371         vdata->port = ti->port;
2372
2373         list_add_tail(&vdata->list, &pdata->vxlan_ports);
2374
2375         /* First port added? */
2376         if (pdata->vxlan_port_count == 1) {
2377                 xgbe_enable_vxlan_accel(pdata);
2378
2379                 return;
2380         }
2381 }
2382
2383 static void xgbe_udp_tunnel_del(struct net_device *netdev,
2384                                 struct udp_tunnel_info *ti)
2385 {
2386         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2387         struct xgbe_vxlan_data *vdata;
2388
2389         if (!pdata->hw_feat.vxn)
2390                 return;
2391
2392         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2393                 return;
2394
2395         netif_dbg(pdata, drv, netdev,
2396                   "deleting VXLAN tunnel, family=%hx/port=%hx\n",
2397                   ti->sa_family, be16_to_cpu(ti->port));
2398
2399         /* Don't need safe version since loop terminates with deletion */
2400         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
2401                 if (vdata->sa_family != ti->sa_family)
2402                         continue;
2403
2404                 if (vdata->port != ti->port)
2405                         continue;
2406
2407                 list_del(&vdata->list);
2408                 kfree(vdata);
2409
2410                 break;
2411         }
2412
2413         pdata->vxlan_port_count--;
2414         if (!pdata->vxlan_port_count) {
2415                 xgbe_reset_vxlan_accel(pdata);
2416
2417                 return;
2418         }
2419
2420         if (pdata->vxlan_force_disable)
2421                 return;
2422
2423         /* See if VXLAN tunnel id needs to be changed */
2424         vdata = list_first_entry(&pdata->vxlan_ports,
2425                                  struct xgbe_vxlan_data, list);
2426         if (pdata->vxlan_port == be16_to_cpu(vdata->port))
2427                 return;
2428
2429         pdata->vxlan_port = be16_to_cpu(vdata->port);
2430         pdata->hw_if.set_vxlan_id(pdata);
2431 }
2432
2433 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2434                                              struct net_device *netdev,
2435                                              netdev_features_t features)
2436 {
2437         features = vlan_features_check(skb, features);
2438         features = vxlan_features_check(skb, features);
2439
2440         return features;
2441 }
2442
2443 static const struct net_device_ops xgbe_netdev_ops = {
2444         .ndo_open               = xgbe_open,
2445         .ndo_stop               = xgbe_close,
2446         .ndo_start_xmit         = xgbe_xmit,
2447         .ndo_set_rx_mode        = xgbe_set_rx_mode,
2448         .ndo_set_mac_address    = xgbe_set_mac_address,
2449         .ndo_validate_addr      = eth_validate_addr,
2450         .ndo_do_ioctl           = xgbe_ioctl,
2451         .ndo_change_mtu         = xgbe_change_mtu,
2452         .ndo_tx_timeout         = xgbe_tx_timeout,
2453         .ndo_get_stats64        = xgbe_get_stats64,
2454         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
2455         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
2456 #ifdef CONFIG_NET_POLL_CONTROLLER
2457         .ndo_poll_controller    = xgbe_poll_controller,
2458 #endif
2459         .ndo_setup_tc           = xgbe_setup_tc,
2460         .ndo_fix_features       = xgbe_fix_features,
2461         .ndo_set_features       = xgbe_set_features,
2462         .ndo_udp_tunnel_add     = xgbe_udp_tunnel_add,
2463         .ndo_udp_tunnel_del     = xgbe_udp_tunnel_del,
2464         .ndo_features_check     = xgbe_features_check,
2465 };
2466
2467 const struct net_device_ops *xgbe_get_netdev_ops(void)
2468 {
2469         return &xgbe_netdev_ops;
2470 }
2471
2472 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2473 {
2474         struct xgbe_prv_data *pdata = channel->pdata;
2475         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2476         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2477         struct xgbe_ring *ring = channel->rx_ring;
2478         struct xgbe_ring_data *rdata;
2479
2480         while (ring->dirty != ring->cur) {
2481                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2482
2483                 /* Reset rdata values */
2484                 desc_if->unmap_rdata(pdata, rdata);
2485
2486                 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2487                         break;
2488
2489                 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2490
2491                 ring->dirty++;
2492         }
2493
2494         /* Make sure everything is written before the register write */
2495         wmb();
2496
2497         /* Update the Rx Tail Pointer Register with address of
2498          * the last cleaned entry */
2499         rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2500         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2501                           lower_32_bits(rdata->rdesc_dma));
2502 }
2503
2504 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2505                                        struct napi_struct *napi,
2506                                        struct xgbe_ring_data *rdata,
2507                                        unsigned int len)
2508 {
2509         struct sk_buff *skb;
2510         u8 *packet;
2511
2512         skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2513         if (!skb)
2514                 return NULL;
2515
2516         /* Pull in the header buffer which may contain just the header
2517          * or the header plus data
2518          */
2519         dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2520                                       rdata->rx.hdr.dma_off,
2521                                       rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2522
2523         packet = page_address(rdata->rx.hdr.pa.pages) +
2524                  rdata->rx.hdr.pa.pages_offset;
2525         skb_copy_to_linear_data(skb, packet, len);
2526         skb_put(skb, len);
2527
2528         return skb;
2529 }
2530
2531 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2532                                      struct xgbe_packet_data *packet)
2533 {
2534         /* Always zero if not the first descriptor */
2535         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2536                 return 0;
2537
2538         /* First descriptor with split header, return header length */
2539         if (rdata->rx.hdr_len)
2540                 return rdata->rx.hdr_len;
2541
2542         /* First descriptor but not the last descriptor and no split header,
2543          * so the full buffer was used
2544          */
2545         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2546                 return rdata->rx.hdr.dma_len;
2547
2548         /* First descriptor and last descriptor and no split header, so
2549          * calculate how much of the buffer was used
2550          */
2551         return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2552 }
2553
2554 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2555                                      struct xgbe_packet_data *packet,
2556                                      unsigned int len)
2557 {
2558         /* Always the full buffer if not the last descriptor */
2559         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2560                 return rdata->rx.buf.dma_len;
2561
2562         /* Last descriptor so calculate how much of the buffer was used
2563          * for the last bit of data
2564          */
2565         return rdata->rx.len - len;
2566 }
2567
2568 static int xgbe_tx_poll(struct xgbe_channel *channel)
2569 {
2570         struct xgbe_prv_data *pdata = channel->pdata;
2571         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2572         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2573         struct xgbe_ring *ring = channel->tx_ring;
2574         struct xgbe_ring_data *rdata;
2575         struct xgbe_ring_desc *rdesc;
2576         struct net_device *netdev = pdata->netdev;
2577         struct netdev_queue *txq;
2578         int processed = 0;
2579         unsigned int tx_packets = 0, tx_bytes = 0;
2580         unsigned int cur;
2581
2582         DBGPR("-->xgbe_tx_poll\n");
2583
2584         /* Nothing to do if there isn't a Tx ring for this channel */
2585         if (!ring)
2586                 return 0;
2587
2588         cur = ring->cur;
2589
2590         /* Be sure we get ring->cur before accessing descriptor data */
2591         smp_rmb();
2592
2593         txq = netdev_get_tx_queue(netdev, channel->queue_index);
2594
2595         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2596                (ring->dirty != cur)) {
2597                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2598                 rdesc = rdata->rdesc;
2599
2600                 if (!hw_if->tx_complete(rdesc))
2601                         break;
2602
2603                 /* Make sure descriptor fields are read after reading the OWN
2604                  * bit */
2605                 dma_rmb();
2606
2607                 if (netif_msg_tx_done(pdata))
2608                         xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2609
2610                 if (hw_if->is_last_desc(rdesc)) {
2611                         tx_packets += rdata->tx.packets;
2612                         tx_bytes += rdata->tx.bytes;
2613                 }
2614
2615                 /* Free the SKB and reset the descriptor for re-use */
2616                 desc_if->unmap_rdata(pdata, rdata);
2617                 hw_if->tx_desc_reset(rdata);
2618
2619                 processed++;
2620                 ring->dirty++;
2621         }
2622
2623         if (!processed)
2624                 return 0;
2625
2626         netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2627
2628         if ((ring->tx.queue_stopped == 1) &&
2629             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2630                 ring->tx.queue_stopped = 0;
2631                 netif_tx_wake_queue(txq);
2632         }
2633
2634         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2635
2636         return processed;
2637 }
2638
2639 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2640 {
2641         struct xgbe_prv_data *pdata = channel->pdata;
2642         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2643         struct xgbe_ring *ring = channel->rx_ring;
2644         struct xgbe_ring_data *rdata;
2645         struct xgbe_packet_data *packet;
2646         struct net_device *netdev = pdata->netdev;
2647         struct napi_struct *napi;
2648         struct sk_buff *skb;
2649         struct skb_shared_hwtstamps *hwtstamps;
2650         unsigned int last, error, context_next, context;
2651         unsigned int len, buf1_len, buf2_len, max_len;
2652         unsigned int received = 0;
2653         int packet_count = 0;
2654
2655         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2656
2657         /* Nothing to do if there isn't a Rx ring for this channel */
2658         if (!ring)
2659                 return 0;
2660
2661         last = 0;
2662         context_next = 0;
2663
2664         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2665
2666         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2667         packet = &ring->packet_data;
2668         while (packet_count < budget) {
2669                 DBGPR("  cur = %d\n", ring->cur);
2670
2671                 /* First time in loop see if we need to restore state */
2672                 if (!received && rdata->state_saved) {
2673                         skb = rdata->state.skb;
2674                         error = rdata->state.error;
2675                         len = rdata->state.len;
2676                 } else {
2677                         memset(packet, 0, sizeof(*packet));
2678                         skb = NULL;
2679                         error = 0;
2680                         len = 0;
2681                 }
2682
2683 read_again:
2684                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2685
2686                 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2687                         xgbe_rx_refresh(channel);
2688
2689                 if (hw_if->dev_read(channel))
2690                         break;
2691
2692                 received++;
2693                 ring->cur++;
2694
2695                 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2696                                       LAST);
2697                 context_next = XGMAC_GET_BITS(packet->attributes,
2698                                               RX_PACKET_ATTRIBUTES,
2699                                               CONTEXT_NEXT);
2700                 context = XGMAC_GET_BITS(packet->attributes,
2701                                          RX_PACKET_ATTRIBUTES,
2702                                          CONTEXT);
2703
2704                 /* Earlier error, just drain the remaining data */
2705                 if ((!last || context_next) && error)
2706                         goto read_again;
2707
2708                 if (error || packet->errors) {
2709                         if (packet->errors)
2710                                 netif_err(pdata, rx_err, netdev,
2711                                           "error in received packet\n");
2712                         dev_kfree_skb(skb);
2713                         goto next_packet;
2714                 }
2715
2716                 if (!context) {
2717                         /* Get the data length in the descriptor buffers */
2718                         buf1_len = xgbe_rx_buf1_len(rdata, packet);
2719                         len += buf1_len;
2720                         buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2721                         len += buf2_len;
2722
2723                         if (!skb) {
2724                                 skb = xgbe_create_skb(pdata, napi, rdata,
2725                                                       buf1_len);
2726                                 if (!skb) {
2727                                         error = 1;
2728                                         goto skip_data;
2729                                 }
2730                         }
2731
2732                         if (buf2_len) {
2733                                 dma_sync_single_range_for_cpu(pdata->dev,
2734                                                         rdata->rx.buf.dma_base,
2735                                                         rdata->rx.buf.dma_off,
2736                                                         rdata->rx.buf.dma_len,
2737                                                         DMA_FROM_DEVICE);
2738
2739                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2740                                                 rdata->rx.buf.pa.pages,
2741                                                 rdata->rx.buf.pa.pages_offset,
2742                                                 buf2_len,
2743                                                 rdata->rx.buf.dma_len);
2744                                 rdata->rx.buf.pa.pages = NULL;
2745                         }
2746                 }
2747
2748 skip_data:
2749                 if (!last || context_next)
2750                         goto read_again;
2751
2752                 if (!skb)
2753                         goto next_packet;
2754
2755                 /* Be sure we don't exceed the configured MTU */
2756                 max_len = netdev->mtu + ETH_HLEN;
2757                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2758                     (skb->protocol == htons(ETH_P_8021Q)))
2759                         max_len += VLAN_HLEN;
2760
2761                 if (skb->len > max_len) {
2762                         netif_err(pdata, rx_err, netdev,
2763                                   "packet length exceeds configured MTU\n");
2764                         dev_kfree_skb(skb);
2765                         goto next_packet;
2766                 }
2767
2768                 if (netif_msg_pktdata(pdata))
2769                         xgbe_print_pkt(netdev, skb, false);
2770
2771                 skb_checksum_none_assert(skb);
2772                 if (XGMAC_GET_BITS(packet->attributes,
2773                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
2774                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2775
2776                 if (XGMAC_GET_BITS(packet->attributes,
2777                                    RX_PACKET_ATTRIBUTES, TNP)) {
2778                         skb->encapsulation = 1;
2779
2780                         if (XGMAC_GET_BITS(packet->attributes,
2781                                            RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2782                                 skb->csum_level = 1;
2783                 }
2784
2785                 if (XGMAC_GET_BITS(packet->attributes,
2786                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2787                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2788                                                packet->vlan_ctag);
2789
2790                 if (XGMAC_GET_BITS(packet->attributes,
2791                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2792                         u64 nsec;
2793
2794                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2795                                                     packet->rx_tstamp);
2796                         hwtstamps = skb_hwtstamps(skb);
2797                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
2798                 }
2799
2800                 if (XGMAC_GET_BITS(packet->attributes,
2801                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
2802                         skb_set_hash(skb, packet->rss_hash,
2803                                      packet->rss_hash_type);
2804
2805                 skb->dev = netdev;
2806                 skb->protocol = eth_type_trans(skb, netdev);
2807                 skb_record_rx_queue(skb, channel->queue_index);
2808
2809                 napi_gro_receive(napi, skb);
2810
2811 next_packet:
2812                 packet_count++;
2813         }
2814
2815         /* Check if we need to save state before leaving */
2816         if (received && (!last || context_next)) {
2817                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2818                 rdata->state_saved = 1;
2819                 rdata->state.skb = skb;
2820                 rdata->state.len = len;
2821                 rdata->state.error = error;
2822         }
2823
2824         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2825
2826         return packet_count;
2827 }
2828
2829 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2830 {
2831         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2832                                                     napi);
2833         struct xgbe_prv_data *pdata = channel->pdata;
2834         int processed = 0;
2835
2836         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2837
2838         /* Cleanup Tx ring first */
2839         xgbe_tx_poll(channel);
2840
2841         /* Process Rx ring next */
2842         processed = xgbe_rx_poll(channel, budget);
2843
2844         /* If we processed everything, we are done */
2845         if ((processed < budget) && napi_complete_done(napi, processed)) {
2846                 /* Enable Tx and Rx interrupts */
2847                 if (pdata->channel_irq_mode)
2848                         xgbe_enable_rx_tx_int(pdata, channel);
2849                 else
2850                         enable_irq(channel->dma_irq);
2851         }
2852
2853         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2854
2855         return processed;
2856 }
2857
2858 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2859 {
2860         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2861                                                    napi);
2862         struct xgbe_channel *channel;
2863         int ring_budget;
2864         int processed, last_processed;
2865         unsigned int i;
2866
2867         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2868
2869         processed = 0;
2870         ring_budget = budget / pdata->rx_ring_count;
2871         do {
2872                 last_processed = processed;
2873
2874                 for (i = 0; i < pdata->channel_count; i++) {
2875                         channel = pdata->channel[i];
2876
2877                         /* Cleanup Tx ring first */
2878                         xgbe_tx_poll(channel);
2879
2880                         /* Process Rx ring next */
2881                         if (ring_budget > (budget - processed))
2882                                 ring_budget = budget - processed;
2883                         processed += xgbe_rx_poll(channel, ring_budget);
2884                 }
2885         } while ((processed < budget) && (processed != last_processed));
2886
2887         /* If we processed everything, we are done */
2888         if ((processed < budget) && napi_complete_done(napi, processed)) {
2889                 /* Enable Tx and Rx interrupts */
2890                 xgbe_enable_rx_tx_ints(pdata);
2891         }
2892
2893         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2894
2895         return processed;
2896 }
2897
2898 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2899                        unsigned int idx, unsigned int count, unsigned int flag)
2900 {
2901         struct xgbe_ring_data *rdata;
2902         struct xgbe_ring_desc *rdesc;
2903
2904         while (count--) {
2905                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2906                 rdesc = rdata->rdesc;
2907                 netdev_dbg(pdata->netdev,
2908                            "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2909                            (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2910                            le32_to_cpu(rdesc->desc0),
2911                            le32_to_cpu(rdesc->desc1),
2912                            le32_to_cpu(rdesc->desc2),
2913                            le32_to_cpu(rdesc->desc3));
2914                 idx++;
2915         }
2916 }
2917
2918 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2919                        unsigned int idx)
2920 {
2921         struct xgbe_ring_data *rdata;
2922         struct xgbe_ring_desc *rdesc;
2923
2924         rdata = XGBE_GET_DESC_DATA(ring, idx);
2925         rdesc = rdata->rdesc;
2926         netdev_dbg(pdata->netdev,
2927                    "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2928                    idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2929                    le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2930 }
2931
2932 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2933 {
2934         struct ethhdr *eth = (struct ethhdr *)skb->data;
2935         unsigned char *buf = skb->data;
2936         unsigned char buffer[128];
2937         unsigned int i, j;
2938
2939         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2940
2941         netdev_dbg(netdev, "%s packet of %d bytes\n",
2942                    (tx_rx ? "TX" : "RX"), skb->len);
2943
2944         netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2945         netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2946         netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2947
2948         for (i = 0, j = 0; i < skb->len;) {
2949                 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2950                               buf[i++]);
2951
2952                 if ((i % 32) == 0) {
2953                         netdev_dbg(netdev, "  %#06x: %s\n", i - 32, buffer);
2954                         j = 0;
2955                 } else if ((i % 16) == 0) {
2956                         buffer[j++] = ' ';
2957                         buffer[j++] = ' ';
2958                 } else if ((i % 4) == 0) {
2959                         buffer[j++] = ' ';
2960                 }
2961         }
2962         if (i % 32)
2963                 netdev_dbg(netdev, "  %#06x: %s\n", i - (i % 32), buffer);
2964
2965         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2966 }