1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #define DRV_NAME "pcnet32"
27 #define DRV_VERSION "1.35"
28 #define DRV_RELDATE "21.Apr.2008"
29 #define PFX DRV_NAME ": "
31 static const char *const version =
32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/sched.h>
37 #include <linux/string.h>
38 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/ethtool.h>
46 #include <linux/mii.h>
47 #include <linux/crc32.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/if_ether.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
56 #include <linux/uaccess.h>
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
64 static const struct pci_device_id pcnet32_pci_tbl[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
75 { } /* terminate list */
78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
80 static int cards_found;
85 static unsigned int pcnet32_portlist[] =
86 { 0x300, 0x320, 0x340, 0x360, 0 };
88 static int pcnet32_debug;
89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb; /* check for VLB cards ? */
92 static struct net_device *pcnet32_dev;
94 static int max_interrupt_work = 2;
95 static int rx_copybreak = 200;
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
107 #define PCNET32_DMA_MASK 0xffffffff
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
113 * table to translate option values from tulip
114 * to internal options
116 static const unsigned char options_mapping[] = {
117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Loopback test (offline)"
140 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
142 #define PCNET32_NUM_REGS 136
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options[MAX_UNITS];
146 static int full_duplex[MAX_UNITS];
147 static int homepna[MAX_UNITS];
150 * Theory of Operation
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
177 #define PKT_BUF_SKB 1544
178 /* actual buffer length after being aligned */
179 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
180 /* chip wants twos complement of the (aligned) buffer length */
181 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
183 /* Offsets from base I/O address. */
184 #define PCNET32_WIO_RDP 0x10
185 #define PCNET32_WIO_RAP 0x12
186 #define PCNET32_WIO_RESET 0x14
187 #define PCNET32_WIO_BDP 0x16
189 #define PCNET32_DWIO_RDP 0x10
190 #define PCNET32_DWIO_RAP 0x14
191 #define PCNET32_DWIO_RESET 0x18
192 #define PCNET32_DWIO_BDP 0x1C
194 #define PCNET32_TOTAL_SIZE 0x20
197 #define CSR0_INIT 0x1
198 #define CSR0_START 0x2
199 #define CSR0_STOP 0x4
200 #define CSR0_TXPOLL 0x8
201 #define CSR0_INTEN 0x40
202 #define CSR0_IDON 0x0100
203 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
204 #define PCNET32_INIT_LOW 1
205 #define PCNET32_INIT_HIGH 2
209 #define CSR5_SUSPEND 0x0001
211 #define PCNET32_MC_FILTER 8
213 #define PCNET32_79C970A 0x2621
215 /* The PCNET32 Rx and Tx ring descriptors. */
216 struct pcnet32_rx_head {
218 __le16 buf_length; /* two`s complement of length */
224 struct pcnet32_tx_head {
226 __le16 length; /* two`s complement of length */
232 /* The PCNET32 32-Bit initialization block, described in databook. */
233 struct pcnet32_init_block {
239 /* Receive and transmit ring base, along with extra bits. */
244 /* PCnet32 access functions */
245 struct pcnet32_access {
246 u16 (*read_csr) (unsigned long, int);
247 void (*write_csr) (unsigned long, int, u16);
248 u16 (*read_bcr) (unsigned long, int);
249 void (*write_bcr) (unsigned long, int, u16);
250 u16 (*read_rap) (unsigned long);
251 void (*write_rap) (unsigned long, u16);
252 void (*reset) (unsigned long);
256 * The first field of pcnet32_private is read by the ethernet device
257 * so the structure should be allocated using pci_alloc_consistent().
259 struct pcnet32_private {
260 struct pcnet32_init_block *init_block;
261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
262 struct pcnet32_rx_head *rx_ring;
263 struct pcnet32_tx_head *tx_ring;
264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
265 returned by pci_alloc_consistent */
266 struct pci_dev *pci_dev;
268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
269 struct sk_buff **tx_skbuff;
270 struct sk_buff **rx_skbuff;
271 dma_addr_t *tx_dma_addr;
272 dma_addr_t *rx_dma_addr;
273 const struct pcnet32_access *a;
274 spinlock_t lock; /* Guard lock */
275 unsigned int cur_rx, cur_tx; /* The next free ring entry */
276 unsigned int rx_ring_size; /* current rx ring size */
277 unsigned int tx_ring_size; /* current tx ring size */
278 unsigned int rx_mod_mask; /* rx ring modular mask */
279 unsigned int tx_mod_mask; /* tx ring modular mask */
280 unsigned short rx_len_bits;
281 unsigned short tx_len_bits;
282 dma_addr_t rx_ring_dma_addr;
283 dma_addr_t tx_ring_dma_addr;
284 unsigned int dirty_rx, /* ring entries to be freed. */
287 struct net_device *dev;
288 struct napi_struct napi;
290 char phycount; /* number of phys found */
292 unsigned int shared_irq:1, /* shared irq possible */
293 dxsuflo:1, /* disable transmit stop on uflo */
294 mii:1; /* mii port available */
295 struct net_device *next;
296 struct mii_if_info mii_if;
297 struct timer_list watchdog_timer;
298 u32 msg_enable; /* debug message level */
300 /* each bit indicates an available PHY */
302 unsigned short chip_version; /* which variant this is */
304 /* saved registers during ethtool blink */
308 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
309 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
310 static int pcnet32_open(struct net_device *);
311 static int pcnet32_init_ring(struct net_device *);
312 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
313 struct net_device *);
314 static void pcnet32_tx_timeout(struct net_device *dev);
315 static irqreturn_t pcnet32_interrupt(int, void *);
316 static int pcnet32_close(struct net_device *);
317 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
318 static void pcnet32_load_multicast(struct net_device *dev);
319 static void pcnet32_set_multicast_list(struct net_device *);
320 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
321 static void pcnet32_watchdog(struct net_device *);
322 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
323 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
325 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
326 static void pcnet32_ethtool_test(struct net_device *dev,
327 struct ethtool_test *eth_test, u64 * data);
328 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
329 static int pcnet32_get_regs_len(struct net_device *dev);
330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
332 static void pcnet32_purge_tx_ring(struct net_device *dev);
333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
334 static void pcnet32_free_ring(struct net_device *dev);
335 static void pcnet32_check_media(struct net_device *dev, int verbose);
337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
339 outw(index, addr + PCNET32_WIO_RAP);
340 return inw(addr + PCNET32_WIO_RDP);
343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
345 outw(index, addr + PCNET32_WIO_RAP);
346 outw(val, addr + PCNET32_WIO_RDP);
349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
351 outw(index, addr + PCNET32_WIO_RAP);
352 return inw(addr + PCNET32_WIO_BDP);
355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
357 outw(index, addr + PCNET32_WIO_RAP);
358 outw(val, addr + PCNET32_WIO_BDP);
361 static u16 pcnet32_wio_read_rap(unsigned long addr)
363 return inw(addr + PCNET32_WIO_RAP);
366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
368 outw(val, addr + PCNET32_WIO_RAP);
371 static void pcnet32_wio_reset(unsigned long addr)
373 inw(addr + PCNET32_WIO_RESET);
376 static int pcnet32_wio_check(unsigned long addr)
378 outw(88, addr + PCNET32_WIO_RAP);
379 return inw(addr + PCNET32_WIO_RAP) == 88;
382 static const struct pcnet32_access pcnet32_wio = {
383 .read_csr = pcnet32_wio_read_csr,
384 .write_csr = pcnet32_wio_write_csr,
385 .read_bcr = pcnet32_wio_read_bcr,
386 .write_bcr = pcnet32_wio_write_bcr,
387 .read_rap = pcnet32_wio_read_rap,
388 .write_rap = pcnet32_wio_write_rap,
389 .reset = pcnet32_wio_reset
392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
394 outl(index, addr + PCNET32_DWIO_RAP);
395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
400 outl(index, addr + PCNET32_DWIO_RAP);
401 outl(val, addr + PCNET32_DWIO_RDP);
404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
406 outl(index, addr + PCNET32_DWIO_RAP);
407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
412 outl(index, addr + PCNET32_DWIO_RAP);
413 outl(val, addr + PCNET32_DWIO_BDP);
416 static u16 pcnet32_dwio_read_rap(unsigned long addr)
418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
423 outl(val, addr + PCNET32_DWIO_RAP);
426 static void pcnet32_dwio_reset(unsigned long addr)
428 inl(addr + PCNET32_DWIO_RESET);
431 static int pcnet32_dwio_check(unsigned long addr)
433 outl(88, addr + PCNET32_DWIO_RAP);
434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
437 static const struct pcnet32_access pcnet32_dwio = {
438 .read_csr = pcnet32_dwio_read_csr,
439 .write_csr = pcnet32_dwio_write_csr,
440 .read_bcr = pcnet32_dwio_read_bcr,
441 .write_bcr = pcnet32_dwio_write_bcr,
442 .read_rap = pcnet32_dwio_read_rap,
443 .write_rap = pcnet32_dwio_write_rap,
444 .reset = pcnet32_dwio_reset
447 static void pcnet32_netif_stop(struct net_device *dev)
449 struct pcnet32_private *lp = netdev_priv(dev);
451 netif_trans_update(dev); /* prevent tx timeout */
452 napi_disable(&lp->napi);
453 netif_tx_disable(dev);
456 static void pcnet32_netif_start(struct net_device *dev)
458 struct pcnet32_private *lp = netdev_priv(dev);
459 ulong ioaddr = dev->base_addr;
462 netif_wake_queue(dev);
463 val = lp->a->read_csr(ioaddr, CSR3);
465 lp->a->write_csr(ioaddr, CSR3, val);
466 napi_enable(&lp->napi);
470 * Allocate space for the new sized tx ring.
472 * Save new resources.
473 * Any failure keeps old resources.
474 * Must be called with lp->lock held.
476 static void pcnet32_realloc_tx_ring(struct net_device *dev,
477 struct pcnet32_private *lp,
480 dma_addr_t new_ring_dma_addr;
481 dma_addr_t *new_dma_addr_list;
482 struct pcnet32_tx_head *new_tx_ring;
483 struct sk_buff **new_skb_list;
484 unsigned int entries = BIT(size);
486 pcnet32_purge_tx_ring(dev);
489 pci_zalloc_consistent(lp->pci_dev,
490 sizeof(struct pcnet32_tx_head) * entries,
492 if (new_tx_ring == NULL)
495 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
496 if (!new_dma_addr_list)
497 goto free_new_tx_ring;
499 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
503 kfree(lp->tx_skbuff);
504 kfree(lp->tx_dma_addr);
505 pci_free_consistent(lp->pci_dev,
506 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
507 lp->tx_ring, lp->tx_ring_dma_addr);
509 lp->tx_ring_size = entries;
510 lp->tx_mod_mask = lp->tx_ring_size - 1;
511 lp->tx_len_bits = (size << 12);
512 lp->tx_ring = new_tx_ring;
513 lp->tx_ring_dma_addr = new_ring_dma_addr;
514 lp->tx_dma_addr = new_dma_addr_list;
515 lp->tx_skbuff = new_skb_list;
519 kfree(new_dma_addr_list);
521 pci_free_consistent(lp->pci_dev,
522 sizeof(struct pcnet32_tx_head) * entries,
528 * Allocate space for the new sized rx ring.
529 * Re-use old receive buffers.
530 * alloc extra buffers
531 * free unneeded buffers
532 * free unneeded buffers
533 * Save new resources.
534 * Any failure keeps old resources.
535 * Must be called with lp->lock held.
537 static void pcnet32_realloc_rx_ring(struct net_device *dev,
538 struct pcnet32_private *lp,
541 dma_addr_t new_ring_dma_addr;
542 dma_addr_t *new_dma_addr_list;
543 struct pcnet32_rx_head *new_rx_ring;
544 struct sk_buff **new_skb_list;
546 unsigned int entries = BIT(size);
549 pci_zalloc_consistent(lp->pci_dev,
550 sizeof(struct pcnet32_rx_head) * entries,
552 if (new_rx_ring == NULL)
555 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
556 if (!new_dma_addr_list)
557 goto free_new_rx_ring;
559 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
563 /* first copy the current receive buffers */
564 overlap = min(entries, lp->rx_ring_size);
565 for (new = 0; new < overlap; new++) {
566 new_rx_ring[new] = lp->rx_ring[new];
567 new_dma_addr_list[new] = lp->rx_dma_addr[new];
568 new_skb_list[new] = lp->rx_skbuff[new];
570 /* now allocate any new buffers needed */
571 for (; new < entries; new++) {
572 struct sk_buff *rx_skbuff;
573 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
574 rx_skbuff = new_skb_list[new];
576 /* keep the original lists and buffers */
577 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
581 skb_reserve(rx_skbuff, NET_IP_ALIGN);
583 new_dma_addr_list[new] =
584 pci_map_single(lp->pci_dev, rx_skbuff->data,
585 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
586 if (pci_dma_mapping_error(lp->pci_dev,
587 new_dma_addr_list[new])) {
588 netif_err(lp, drv, dev, "%s dma mapping failed\n",
590 dev_kfree_skb(new_skb_list[new]);
593 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
594 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
595 new_rx_ring[new].status = cpu_to_le16(0x8000);
597 /* and free any unneeded buffers */
598 for (; new < lp->rx_ring_size; new++) {
599 if (lp->rx_skbuff[new]) {
600 if (!pci_dma_mapping_error(lp->pci_dev,
601 lp->rx_dma_addr[new]))
602 pci_unmap_single(lp->pci_dev,
603 lp->rx_dma_addr[new],
606 dev_kfree_skb(lp->rx_skbuff[new]);
610 kfree(lp->rx_skbuff);
611 kfree(lp->rx_dma_addr);
612 pci_free_consistent(lp->pci_dev,
613 sizeof(struct pcnet32_rx_head) *
614 lp->rx_ring_size, lp->rx_ring,
615 lp->rx_ring_dma_addr);
617 lp->rx_ring_size = entries;
618 lp->rx_mod_mask = lp->rx_ring_size - 1;
619 lp->rx_len_bits = (size << 4);
620 lp->rx_ring = new_rx_ring;
621 lp->rx_ring_dma_addr = new_ring_dma_addr;
622 lp->rx_dma_addr = new_dma_addr_list;
623 lp->rx_skbuff = new_skb_list;
627 while (--new >= lp->rx_ring_size) {
628 if (new_skb_list[new]) {
629 if (!pci_dma_mapping_error(lp->pci_dev,
630 new_dma_addr_list[new]))
631 pci_unmap_single(lp->pci_dev,
632 new_dma_addr_list[new],
635 dev_kfree_skb(new_skb_list[new]);
640 kfree(new_dma_addr_list);
642 pci_free_consistent(lp->pci_dev,
643 sizeof(struct pcnet32_rx_head) * entries,
648 static void pcnet32_purge_rx_ring(struct net_device *dev)
650 struct pcnet32_private *lp = netdev_priv(dev);
653 /* free all allocated skbuffs */
654 for (i = 0; i < lp->rx_ring_size; i++) {
655 lp->rx_ring[i].status = 0; /* CPU owns buffer */
656 wmb(); /* Make sure adapter sees owner change */
657 if (lp->rx_skbuff[i]) {
658 if (!pci_dma_mapping_error(lp->pci_dev,
660 pci_unmap_single(lp->pci_dev,
664 dev_kfree_skb_any(lp->rx_skbuff[i]);
666 lp->rx_skbuff[i] = NULL;
667 lp->rx_dma_addr[i] = 0;
671 #ifdef CONFIG_NET_POLL_CONTROLLER
672 static void pcnet32_poll_controller(struct net_device *dev)
674 disable_irq(dev->irq);
675 pcnet32_interrupt(0, dev);
676 enable_irq(dev->irq);
680 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
682 struct pcnet32_private *lp = netdev_priv(dev);
687 spin_lock_irqsave(&lp->lock, flags);
688 mii_ethtool_gset(&lp->mii_if, cmd);
689 spin_unlock_irqrestore(&lp->lock, flags);
695 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
697 struct pcnet32_private *lp = netdev_priv(dev);
702 spin_lock_irqsave(&lp->lock, flags);
703 r = mii_ethtool_sset(&lp->mii_if, cmd);
704 spin_unlock_irqrestore(&lp->lock, flags);
709 static void pcnet32_get_drvinfo(struct net_device *dev,
710 struct ethtool_drvinfo *info)
712 struct pcnet32_private *lp = netdev_priv(dev);
714 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
715 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
717 strlcpy(info->bus_info, pci_name(lp->pci_dev),
718 sizeof(info->bus_info));
720 snprintf(info->bus_info, sizeof(info->bus_info),
721 "VLB 0x%lx", dev->base_addr);
724 static u32 pcnet32_get_link(struct net_device *dev)
726 struct pcnet32_private *lp = netdev_priv(dev);
730 spin_lock_irqsave(&lp->lock, flags);
732 r = mii_link_ok(&lp->mii_if);
733 } else if (lp->chip_version >= PCNET32_79C970A) {
734 ulong ioaddr = dev->base_addr; /* card base I/O address */
735 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
736 } else { /* can not detect link on really old chips */
739 spin_unlock_irqrestore(&lp->lock, flags);
744 static u32 pcnet32_get_msglevel(struct net_device *dev)
746 struct pcnet32_private *lp = netdev_priv(dev);
747 return lp->msg_enable;
750 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
752 struct pcnet32_private *lp = netdev_priv(dev);
753 lp->msg_enable = value;
756 static int pcnet32_nway_reset(struct net_device *dev)
758 struct pcnet32_private *lp = netdev_priv(dev);
763 spin_lock_irqsave(&lp->lock, flags);
764 r = mii_nway_restart(&lp->mii_if);
765 spin_unlock_irqrestore(&lp->lock, flags);
770 static void pcnet32_get_ringparam(struct net_device *dev,
771 struct ethtool_ringparam *ering)
773 struct pcnet32_private *lp = netdev_priv(dev);
775 ering->tx_max_pending = TX_MAX_RING_SIZE;
776 ering->tx_pending = lp->tx_ring_size;
777 ering->rx_max_pending = RX_MAX_RING_SIZE;
778 ering->rx_pending = lp->rx_ring_size;
781 static int pcnet32_set_ringparam(struct net_device *dev,
782 struct ethtool_ringparam *ering)
784 struct pcnet32_private *lp = netdev_priv(dev);
787 ulong ioaddr = dev->base_addr;
790 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
793 if (netif_running(dev))
794 pcnet32_netif_stop(dev);
796 spin_lock_irqsave(&lp->lock, flags);
797 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
799 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
801 /* set the minimum ring size to 4, to allow the loopback test to work
804 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
805 if (size <= (1 << i))
808 if ((1 << i) != lp->tx_ring_size)
809 pcnet32_realloc_tx_ring(dev, lp, i);
811 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
812 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
813 if (size <= (1 << i))
816 if ((1 << i) != lp->rx_ring_size)
817 pcnet32_realloc_rx_ring(dev, lp, i);
819 lp->napi.weight = lp->rx_ring_size / 2;
821 if (netif_running(dev)) {
822 pcnet32_netif_start(dev);
823 pcnet32_restart(dev, CSR0_NORMAL);
826 spin_unlock_irqrestore(&lp->lock, flags);
828 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
829 lp->rx_ring_size, lp->tx_ring_size);
834 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
837 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
840 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
844 return PCNET32_TEST_LEN;
850 static void pcnet32_ethtool_test(struct net_device *dev,
851 struct ethtool_test *test, u64 * data)
853 struct pcnet32_private *lp = netdev_priv(dev);
856 if (test->flags == ETH_TEST_FL_OFFLINE) {
857 rc = pcnet32_loopback_test(dev, data);
859 netif_printk(lp, hw, KERN_DEBUG, dev,
860 "Loopback test failed\n");
861 test->flags |= ETH_TEST_FL_FAILED;
863 netif_printk(lp, hw, KERN_DEBUG, dev,
864 "Loopback test passed\n");
866 netif_printk(lp, hw, KERN_DEBUG, dev,
867 "No tests to run (specify 'Offline' on ethtool)\n");
868 } /* end pcnet32_ethtool_test */
870 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
872 struct pcnet32_private *lp = netdev_priv(dev);
873 const struct pcnet32_access *a = lp->a; /* access to registers */
874 ulong ioaddr = dev->base_addr; /* card base I/O address */
875 struct sk_buff *skb; /* sk buff */
876 int x, i; /* counters */
877 int numbuffs = 4; /* number of TX/RX buffers and descs */
878 u16 status = 0x8300; /* TX ring status */
879 __le16 teststatus; /* test of ring status */
880 int rc; /* return code */
881 int size; /* size of packets */
882 unsigned char *packet; /* source packet data */
883 static const int data_len = 60; /* length of source packets */
887 rc = 1; /* default to fail */
889 if (netif_running(dev))
890 pcnet32_netif_stop(dev);
892 spin_lock_irqsave(&lp->lock, flags);
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
895 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
897 /* Reset the PCNET32 */
898 lp->a->reset(ioaddr);
899 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
901 /* switch pcnet32 to 32bit mode */
902 lp->a->write_bcr(ioaddr, 20, 2);
904 /* purge & init rings but don't actually restart */
905 pcnet32_restart(dev, 0x0000);
907 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
909 /* Initialize Transmit buffers. */
910 size = data_len + 15;
911 for (x = 0; x < numbuffs; x++) {
912 skb = netdev_alloc_skb(dev, size);
914 netif_printk(lp, hw, KERN_DEBUG, dev,
915 "Cannot allocate skb at line: %d!\n",
920 skb_put(skb, size); /* create space for data */
921 lp->tx_skbuff[x] = skb;
922 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
923 lp->tx_ring[x].misc = 0;
925 /* put DA and SA into the skb */
926 for (i = 0; i < 6; i++)
927 *packet++ = dev->dev_addr[i];
928 for (i = 0; i < 6; i++)
929 *packet++ = dev->dev_addr[i];
935 /* fill packet with data */
936 for (i = 0; i < data_len; i++)
940 pci_map_single(lp->pci_dev, skb->data, skb->len,
942 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[x])) {
943 netif_printk(lp, hw, KERN_DEBUG, dev,
944 "DMA mapping error at line: %d!\n",
948 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
949 wmb(); /* Make sure owner changes after all others are visible */
950 lp->tx_ring[x].status = cpu_to_le16(status);
953 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
954 a->write_bcr(ioaddr, 32, x | 0x0002);
956 /* set int loopback in CSR15 */
957 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
958 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
960 teststatus = cpu_to_le16(0x8000);
961 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
963 /* Check status of descriptors */
964 for (x = 0; x < numbuffs; x++) {
967 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
968 spin_unlock_irqrestore(&lp->lock, flags);
970 spin_lock_irqsave(&lp->lock, flags);
975 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
980 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
982 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
983 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
985 for (x = 0; x < numbuffs; x++) {
986 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
987 skb = lp->rx_skbuff[x];
988 for (i = 0; i < size; i++)
989 pr_cont(" %02x", *(skb->data + i));
996 while (x < numbuffs && !rc) {
997 skb = lp->rx_skbuff[x];
998 packet = lp->tx_skbuff[x]->data;
999 for (i = 0; i < size; i++) {
1000 if (*(skb->data + i) != packet[i]) {
1001 netif_printk(lp, hw, KERN_DEBUG, dev,
1002 "Error in compare! %2x - %02x %02x\n",
1003 i, *(skb->data + i), packet[i]);
1013 pcnet32_purge_tx_ring(dev);
1015 x = a->read_csr(ioaddr, CSR15);
1016 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1018 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1019 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1021 if (netif_running(dev)) {
1022 pcnet32_netif_start(dev);
1023 pcnet32_restart(dev, CSR0_NORMAL);
1025 pcnet32_purge_rx_ring(dev);
1026 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1028 spin_unlock_irqrestore(&lp->lock, flags);
1031 } /* end pcnet32_loopback_test */
1033 static int pcnet32_set_phys_id(struct net_device *dev,
1034 enum ethtool_phys_id_state state)
1036 struct pcnet32_private *lp = netdev_priv(dev);
1037 const struct pcnet32_access *a = lp->a;
1038 ulong ioaddr = dev->base_addr;
1039 unsigned long flags;
1043 case ETHTOOL_ID_ACTIVE:
1044 /* Save the current value of the bcrs */
1045 spin_lock_irqsave(&lp->lock, flags);
1046 for (i = 4; i < 8; i++)
1047 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1048 spin_unlock_irqrestore(&lp->lock, flags);
1049 return 2; /* cycle on/off twice per second */
1052 case ETHTOOL_ID_OFF:
1054 spin_lock_irqsave(&lp->lock, flags);
1055 for (i = 4; i < 8; i++)
1056 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1057 spin_unlock_irqrestore(&lp->lock, flags);
1060 case ETHTOOL_ID_INACTIVE:
1061 /* Restore the original value of the bcrs */
1062 spin_lock_irqsave(&lp->lock, flags);
1063 for (i = 4; i < 8; i++)
1064 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1065 spin_unlock_irqrestore(&lp->lock, flags);
1071 * lp->lock must be held.
1073 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1077 struct pcnet32_private *lp = netdev_priv(dev);
1078 const struct pcnet32_access *a = lp->a;
1079 ulong ioaddr = dev->base_addr;
1082 /* really old chips have to be stopped. */
1083 if (lp->chip_version < PCNET32_79C970A)
1086 /* set SUSPEND (SPND) - CSR5 bit 0 */
1087 csr5 = a->read_csr(ioaddr, CSR5);
1088 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1090 /* poll waiting for bit to be set */
1092 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1093 spin_unlock_irqrestore(&lp->lock, *flags);
1098 spin_lock_irqsave(&lp->lock, *flags);
1101 netif_printk(lp, hw, KERN_DEBUG, dev,
1102 "Error getting into suspend!\n");
1110 * process one receive descriptor entry
1113 static void pcnet32_rx_entry(struct net_device *dev,
1114 struct pcnet32_private *lp,
1115 struct pcnet32_rx_head *rxp,
1118 int status = (short)le16_to_cpu(rxp->status) >> 8;
1119 int rx_in_place = 0;
1120 struct sk_buff *skb;
1123 if (status != 0x03) { /* There was an error. */
1125 * There is a tricky error noted by John Murphy,
1126 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1127 * buffers it's possible for a jabber packet to use two
1128 * buffers, with only the last correctly noting the error.
1130 if (status & 0x01) /* Only count a general error at the */
1131 dev->stats.rx_errors++; /* end of a packet. */
1133 dev->stats.rx_frame_errors++;
1135 dev->stats.rx_over_errors++;
1137 dev->stats.rx_crc_errors++;
1139 dev->stats.rx_fifo_errors++;
1143 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1145 /* Discard oversize frames. */
1146 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1147 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1149 dev->stats.rx_errors++;
1153 netif_err(lp, rx_err, dev, "Runt packet!\n");
1154 dev->stats.rx_errors++;
1158 if (pkt_len > rx_copybreak) {
1159 struct sk_buff *newskb;
1160 dma_addr_t new_dma_addr;
1162 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1164 * map the new buffer, if mapping fails, drop the packet and
1165 * reuse the old buffer
1168 skb_reserve(newskb, NET_IP_ALIGN);
1169 new_dma_addr = pci_map_single(lp->pci_dev,
1172 PCI_DMA_FROMDEVICE);
1173 if (pci_dma_mapping_error(lp->pci_dev, new_dma_addr)) {
1174 netif_err(lp, rx_err, dev,
1175 "DMA mapping error.\n");
1176 dev_kfree_skb(newskb);
1179 skb = lp->rx_skbuff[entry];
1180 pci_unmap_single(lp->pci_dev,
1181 lp->rx_dma_addr[entry],
1183 PCI_DMA_FROMDEVICE);
1184 skb_put(skb, pkt_len);
1185 lp->rx_skbuff[entry] = newskb;
1186 lp->rx_dma_addr[entry] = new_dma_addr;
1187 rxp->base = cpu_to_le32(new_dma_addr);
1193 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1196 dev->stats.rx_dropped++;
1200 skb_reserve(skb, NET_IP_ALIGN);
1201 skb_put(skb, pkt_len); /* Make room */
1202 pci_dma_sync_single_for_cpu(lp->pci_dev,
1203 lp->rx_dma_addr[entry],
1205 PCI_DMA_FROMDEVICE);
1206 skb_copy_to_linear_data(skb,
1207 (unsigned char *)(lp->rx_skbuff[entry]->data),
1209 pci_dma_sync_single_for_device(lp->pci_dev,
1210 lp->rx_dma_addr[entry],
1212 PCI_DMA_FROMDEVICE);
1214 dev->stats.rx_bytes += skb->len;
1215 skb->protocol = eth_type_trans(skb, dev);
1216 netif_receive_skb(skb);
1217 dev->stats.rx_packets++;
1220 static int pcnet32_rx(struct net_device *dev, int budget)
1222 struct pcnet32_private *lp = netdev_priv(dev);
1223 int entry = lp->cur_rx & lp->rx_mod_mask;
1224 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1227 /* If we own the next entry, it's a new packet. Send it up. */
1228 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1229 pcnet32_rx_entry(dev, lp, rxp, entry);
1232 * The docs say that the buffer length isn't touched, but Andrew
1233 * Boyd of QNX reports that some revs of the 79C965 clear it.
1235 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1236 wmb(); /* Make sure owner changes after others are visible */
1237 rxp->status = cpu_to_le16(0x8000);
1238 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1239 rxp = &lp->rx_ring[entry];
1245 static int pcnet32_tx(struct net_device *dev)
1247 struct pcnet32_private *lp = netdev_priv(dev);
1248 unsigned int dirty_tx = lp->dirty_tx;
1250 int must_restart = 0;
1252 while (dirty_tx != lp->cur_tx) {
1253 int entry = dirty_tx & lp->tx_mod_mask;
1254 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1257 break; /* It still hasn't been Txed */
1259 lp->tx_ring[entry].base = 0;
1261 if (status & 0x4000) {
1262 /* There was a major error, log it. */
1263 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1264 dev->stats.tx_errors++;
1265 netif_err(lp, tx_err, dev,
1266 "Tx error status=%04x err_status=%08x\n",
1267 status, err_status);
1268 if (err_status & 0x04000000)
1269 dev->stats.tx_aborted_errors++;
1270 if (err_status & 0x08000000)
1271 dev->stats.tx_carrier_errors++;
1272 if (err_status & 0x10000000)
1273 dev->stats.tx_window_errors++;
1275 if (err_status & 0x40000000) {
1276 dev->stats.tx_fifo_errors++;
1277 /* Ackk! On FIFO errors the Tx unit is turned off! */
1278 /* Remove this verbosity later! */
1279 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1283 if (err_status & 0x40000000) {
1284 dev->stats.tx_fifo_errors++;
1285 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1286 /* Ackk! On FIFO errors the Tx unit is turned off! */
1287 /* Remove this verbosity later! */
1288 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1294 if (status & 0x1800)
1295 dev->stats.collisions++;
1296 dev->stats.tx_packets++;
1299 /* We must free the original skb */
1300 if (lp->tx_skbuff[entry]) {
1301 pci_unmap_single(lp->pci_dev,
1302 lp->tx_dma_addr[entry],
1303 lp->tx_skbuff[entry]->
1304 len, PCI_DMA_TODEVICE);
1305 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1306 lp->tx_skbuff[entry] = NULL;
1307 lp->tx_dma_addr[entry] = 0;
1312 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1313 if (delta > lp->tx_ring_size) {
1314 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1315 dirty_tx, lp->cur_tx, lp->tx_full);
1316 dirty_tx += lp->tx_ring_size;
1317 delta -= lp->tx_ring_size;
1321 netif_queue_stopped(dev) &&
1322 delta < lp->tx_ring_size - 2) {
1323 /* The ring is no longer full, clear tbusy. */
1325 netif_wake_queue(dev);
1327 lp->dirty_tx = dirty_tx;
1329 return must_restart;
1332 static int pcnet32_poll(struct napi_struct *napi, int budget)
1334 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1335 struct net_device *dev = lp->dev;
1336 unsigned long ioaddr = dev->base_addr;
1337 unsigned long flags;
1341 work_done = pcnet32_rx(dev, budget);
1343 spin_lock_irqsave(&lp->lock, flags);
1344 if (pcnet32_tx(dev)) {
1345 /* reset the chip to clear the error condition, then restart */
1346 lp->a->reset(ioaddr);
1347 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1348 pcnet32_restart(dev, CSR0_START);
1349 netif_wake_queue(dev);
1351 spin_unlock_irqrestore(&lp->lock, flags);
1353 if (work_done < budget) {
1354 spin_lock_irqsave(&lp->lock, flags);
1356 __napi_complete(napi);
1358 /* clear interrupt masks */
1359 val = lp->a->read_csr(ioaddr, CSR3);
1361 lp->a->write_csr(ioaddr, CSR3, val);
1363 /* Set interrupt enable. */
1364 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1366 spin_unlock_irqrestore(&lp->lock, flags);
1371 #define PCNET32_REGS_PER_PHY 32
1372 #define PCNET32_MAX_PHYS 32
1373 static int pcnet32_get_regs_len(struct net_device *dev)
1375 struct pcnet32_private *lp = netdev_priv(dev);
1376 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1378 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1381 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1386 struct pcnet32_private *lp = netdev_priv(dev);
1387 const struct pcnet32_access *a = lp->a;
1388 ulong ioaddr = dev->base_addr;
1389 unsigned long flags;
1391 spin_lock_irqsave(&lp->lock, flags);
1393 csr0 = a->read_csr(ioaddr, CSR0);
1394 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1395 pcnet32_suspend(dev, &flags, 1);
1397 /* read address PROM */
1398 for (i = 0; i < 16; i += 2)
1399 *buff++ = inw(ioaddr + i);
1401 /* read control and status registers */
1402 for (i = 0; i < 90; i++)
1403 *buff++ = a->read_csr(ioaddr, i);
1405 *buff++ = a->read_csr(ioaddr, 112);
1406 *buff++ = a->read_csr(ioaddr, 114);
1408 /* read bus configuration registers */
1409 for (i = 0; i < 30; i++)
1410 *buff++ = a->read_bcr(ioaddr, i);
1412 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1414 for (i = 31; i < 36; i++)
1415 *buff++ = a->read_bcr(ioaddr, i);
1417 /* read mii phy registers */
1420 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1421 if (lp->phymask & (1 << j)) {
1422 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1423 lp->a->write_bcr(ioaddr, 33,
1425 *buff++ = lp->a->read_bcr(ioaddr, 34);
1431 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1434 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1435 csr5 = a->read_csr(ioaddr, CSR5);
1436 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1439 spin_unlock_irqrestore(&lp->lock, flags);
1442 static const struct ethtool_ops pcnet32_ethtool_ops = {
1443 .get_settings = pcnet32_get_settings,
1444 .set_settings = pcnet32_set_settings,
1445 .get_drvinfo = pcnet32_get_drvinfo,
1446 .get_msglevel = pcnet32_get_msglevel,
1447 .set_msglevel = pcnet32_set_msglevel,
1448 .nway_reset = pcnet32_nway_reset,
1449 .get_link = pcnet32_get_link,
1450 .get_ringparam = pcnet32_get_ringparam,
1451 .set_ringparam = pcnet32_set_ringparam,
1452 .get_strings = pcnet32_get_strings,
1453 .self_test = pcnet32_ethtool_test,
1454 .set_phys_id = pcnet32_set_phys_id,
1455 .get_regs_len = pcnet32_get_regs_len,
1456 .get_regs = pcnet32_get_regs,
1457 .get_sset_count = pcnet32_get_sset_count,
1460 /* only probes for non-PCI devices, the rest are handled by
1461 * pci_register_driver via pcnet32_probe_pci */
1463 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1465 unsigned int *port, ioaddr;
1467 /* search for PCnet32 VLB cards at known addresses */
1468 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1470 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1471 /* check if there is really a pcnet chip on that ioaddr */
1472 if ((inb(ioaddr + 14) == 0x57) &&
1473 (inb(ioaddr + 15) == 0x57)) {
1474 pcnet32_probe1(ioaddr, 0, NULL);
1476 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1483 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1485 unsigned long ioaddr;
1488 err = pci_enable_device(pdev);
1490 if (pcnet32_debug & NETIF_MSG_PROBE)
1491 pr_err("failed to enable device -- err=%d\n", err);
1494 pci_set_master(pdev);
1496 if (!pci_resource_len(pdev, 0)) {
1497 if (pcnet32_debug & NETIF_MSG_PROBE)
1498 pr_err("card has no PCI IO resources, aborting\n");
1502 err = pci_set_dma_mask(pdev, PCNET32_DMA_MASK);
1504 if (pcnet32_debug & NETIF_MSG_PROBE)
1505 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1509 ioaddr = pci_resource_start(pdev, 0);
1510 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1511 if (pcnet32_debug & NETIF_MSG_PROBE)
1512 pr_err("io address range already allocated\n");
1516 err = pcnet32_probe1(ioaddr, 1, pdev);
1518 pci_disable_device(pdev);
1523 static const struct net_device_ops pcnet32_netdev_ops = {
1524 .ndo_open = pcnet32_open,
1525 .ndo_stop = pcnet32_close,
1526 .ndo_start_xmit = pcnet32_start_xmit,
1527 .ndo_tx_timeout = pcnet32_tx_timeout,
1528 .ndo_get_stats = pcnet32_get_stats,
1529 .ndo_set_rx_mode = pcnet32_set_multicast_list,
1530 .ndo_do_ioctl = pcnet32_ioctl,
1531 .ndo_change_mtu = eth_change_mtu,
1532 .ndo_set_mac_address = eth_mac_addr,
1533 .ndo_validate_addr = eth_validate_addr,
1534 #ifdef CONFIG_NET_POLL_CONTROLLER
1535 .ndo_poll_controller = pcnet32_poll_controller,
1540 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1541 * pdev will be NULL when called from pcnet32_probe_vlbus.
1544 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1546 struct pcnet32_private *lp;
1548 int fdx, mii, fset, dxsuflo, sram;
1551 struct net_device *dev;
1552 const struct pcnet32_access *a = NULL;
1553 u8 promaddr[ETH_ALEN];
1556 /* reset the chip */
1557 pcnet32_wio_reset(ioaddr);
1559 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1560 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1563 pcnet32_dwio_reset(ioaddr);
1564 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1565 pcnet32_dwio_check(ioaddr)) {
1568 if (pcnet32_debug & NETIF_MSG_PROBE)
1569 pr_err("No access methods\n");
1570 goto err_release_region;
1575 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1576 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1577 pr_info(" PCnet chip version is %#x\n", chip_version);
1578 if ((chip_version & 0xfff) != 0x003) {
1579 if (pcnet32_debug & NETIF_MSG_PROBE)
1580 pr_info("Unsupported chip version\n");
1581 goto err_release_region;
1584 /* initialize variables */
1585 fdx = mii = fset = dxsuflo = sram = 0;
1586 chip_version = (chip_version >> 12) & 0xffff;
1588 switch (chip_version) {
1590 chipname = "PCnet/PCI 79C970"; /* PCI */
1594 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1596 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1599 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1603 chipname = "PCnet/FAST 79C971"; /* PCI */
1609 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1615 chipname = "PCnet/FAST III 79C973"; /* PCI */
1621 chipname = "PCnet/Home 79C978"; /* PCI */
1624 * This is based on specs published at www.amd.com. This section
1625 * assumes that a card with a 79C978 wants to go into standard
1626 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1627 * and the module option homepna=1 can select this instead.
1629 media = a->read_bcr(ioaddr, 49);
1630 media &= ~3; /* default to 10Mb ethernet */
1631 if (cards_found < MAX_UNITS && homepna[cards_found])
1632 media |= 1; /* switch to home wiring mode */
1633 if (pcnet32_debug & NETIF_MSG_PROBE)
1634 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1635 (media & 1) ? "1" : "10");
1636 a->write_bcr(ioaddr, 49, media);
1639 chipname = "PCnet/FAST III 79C975"; /* PCI */
1645 chipname = "PCnet/PRO 79C976";
1650 if (pcnet32_debug & NETIF_MSG_PROBE)
1651 pr_info("PCnet version %#x, no PCnet32 chip\n",
1653 goto err_release_region;
1657 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1658 * starting until the packet is loaded. Strike one for reliability, lose
1659 * one for latency - although on PCI this isn't a big loss. Older chips
1660 * have FIFO's smaller than a packet, so you can't do this.
1661 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1665 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1666 a->write_csr(ioaddr, 80,
1667 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1672 * The Am79C973/Am79C975 controllers come with 12K of SRAM
1673 * which we can use for the Tx/Rx buffers but most importantly,
1674 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1675 * Tx fifo underflows.
1679 * The SRAM is being configured in two steps. First we
1680 * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1681 * to the datasheet, each bit corresponds to a 512-byte
1682 * page so we can have at most 24 pages. The SRAM_SIZE
1683 * holds the value of the upper 8 bits of the 16-bit SRAM size.
1684 * The low 8-bits start at 0x00 and end at 0xff. So the
1685 * address range is from 0x0000 up to 0x17ff. Therefore,
1686 * the SRAM_SIZE is set to 0x17. The next step is to set
1687 * the BCR26:SRAM_BND midway through so the Tx and Rx
1688 * buffers can share the SRAM equally.
1690 a->write_bcr(ioaddr, 25, 0x17);
1691 a->write_bcr(ioaddr, 26, 0xc);
1692 /* And finally enable the NOUFLO bit */
1693 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1696 dev = alloc_etherdev(sizeof(*lp));
1699 goto err_release_region;
1703 SET_NETDEV_DEV(dev, &pdev->dev);
1705 if (pcnet32_debug & NETIF_MSG_PROBE)
1706 pr_info("%s at %#3lx,", chipname, ioaddr);
1708 /* In most chips, after a chip reset, the ethernet address is read from the
1709 * station address PROM at the base address and programmed into the
1710 * "Physical Address Registers" CSR12-14.
1711 * As a precautionary measure, we read the PROM values and complain if
1712 * they disagree with the CSRs. If they miscompare, and the PROM addr
1713 * is valid, then the PROM addr is used.
1715 for (i = 0; i < 3; i++) {
1717 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1718 /* There may be endianness issues here. */
1719 dev->dev_addr[2 * i] = val & 0x0ff;
1720 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1723 /* read PROM address and compare with CSR address */
1724 for (i = 0; i < ETH_ALEN; i++)
1725 promaddr[i] = inb(ioaddr + i);
1727 if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1728 !is_valid_ether_addr(dev->dev_addr)) {
1729 if (is_valid_ether_addr(promaddr)) {
1730 if (pcnet32_debug & NETIF_MSG_PROBE) {
1731 pr_cont(" warning: CSR address invalid,\n");
1732 pr_info(" using instead PROM address of");
1734 memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1738 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1739 if (!is_valid_ether_addr(dev->dev_addr))
1740 eth_zero_addr(dev->dev_addr);
1742 if (pcnet32_debug & NETIF_MSG_PROBE) {
1743 pr_cont(" %pM", dev->dev_addr);
1745 /* Version 0x2623 and 0x2624 */
1746 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1747 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1748 pr_info(" tx_start_pt(0x%04x):", i);
1751 pr_cont(" 20 bytes,");
1754 pr_cont(" 64 bytes,");
1757 pr_cont(" 128 bytes,");
1760 pr_cont("~220 bytes,");
1763 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1764 pr_cont(" BCR18(%x):", i & 0xffff);
1766 pr_cont("BurstWrEn ");
1768 pr_cont("BurstRdEn ");
1770 pr_cont("DWordIO ");
1772 pr_cont("NoUFlow ");
1773 i = a->read_bcr(ioaddr, 25);
1774 pr_info(" SRAMSIZE=0x%04x,", i << 8);
1775 i = a->read_bcr(ioaddr, 26);
1776 pr_cont(" SRAM_BND=0x%04x,", i << 8);
1777 i = a->read_bcr(ioaddr, 27);
1779 pr_cont("LowLatRx");
1783 dev->base_addr = ioaddr;
1784 lp = netdev_priv(dev);
1785 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1786 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1787 &lp->init_dma_addr);
1788 if (!lp->init_block) {
1789 if (pcnet32_debug & NETIF_MSG_PROBE)
1790 pr_err("Consistent memory allocation failed\n");
1792 goto err_free_netdev;
1798 spin_lock_init(&lp->lock);
1800 lp->name = chipname;
1801 lp->shared_irq = shared;
1802 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1803 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1804 lp->tx_mod_mask = lp->tx_ring_size - 1;
1805 lp->rx_mod_mask = lp->rx_ring_size - 1;
1806 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1807 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1808 lp->mii_if.full_duplex = fdx;
1809 lp->mii_if.phy_id_mask = 0x1f;
1810 lp->mii_if.reg_num_mask = 0x1f;
1811 lp->dxsuflo = dxsuflo;
1813 lp->chip_version = chip_version;
1814 lp->msg_enable = pcnet32_debug;
1815 if ((cards_found >= MAX_UNITS) ||
1816 (options[cards_found] >= sizeof(options_mapping)))
1817 lp->options = PCNET32_PORT_ASEL;
1819 lp->options = options_mapping[options[cards_found]];
1820 lp->mii_if.dev = dev;
1821 lp->mii_if.mdio_read = mdio_read;
1822 lp->mii_if.mdio_write = mdio_write;
1824 /* napi.weight is used in both the napi and non-napi cases */
1825 lp->napi.weight = lp->rx_ring_size / 2;
1827 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1829 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1830 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1831 lp->options |= PCNET32_PORT_FD;
1835 /* prior to register_netdev, dev->name is not yet correct */
1836 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1840 /* detect special T1/E1 WAN card by checking for MAC address */
1841 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1842 dev->dev_addr[2] == 0x75)
1843 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1845 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1846 lp->init_block->tlen_rlen =
1847 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1848 for (i = 0; i < 6; i++)
1849 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1850 lp->init_block->filter[0] = 0x00000000;
1851 lp->init_block->filter[1] = 0x00000000;
1852 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1853 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1855 /* switch pcnet32 to 32bit mode */
1856 a->write_bcr(ioaddr, 20, 2);
1858 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1859 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1861 if (pdev) { /* use the IRQ provided by PCI */
1862 dev->irq = pdev->irq;
1863 if (pcnet32_debug & NETIF_MSG_PROBE)
1864 pr_cont(" assigned IRQ %d\n", dev->irq);
1866 unsigned long irq_mask = probe_irq_on();
1869 * To auto-IRQ we enable the initialization-done and DMA error
1870 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1873 /* Trigger an initialization just for the interrupt. */
1874 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1877 dev->irq = probe_irq_off(irq_mask);
1879 if (pcnet32_debug & NETIF_MSG_PROBE)
1880 pr_cont(", failed to detect IRQ line\n");
1884 if (pcnet32_debug & NETIF_MSG_PROBE)
1885 pr_cont(", probed IRQ %d\n", dev->irq);
1888 /* Set the mii phy_id so that we can query the link state */
1890 /* lp->phycount and lp->phymask are set to 0 by memset above */
1892 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1894 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1895 unsigned short id1, id2;
1897 id1 = mdio_read(dev, i, MII_PHYSID1);
1900 id2 = mdio_read(dev, i, MII_PHYSID2);
1903 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1904 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1906 lp->phymask |= (1 << i);
1907 lp->mii_if.phy_id = i;
1908 if (pcnet32_debug & NETIF_MSG_PROBE)
1909 pr_info("Found PHY %04x:%04x at address %d\n",
1912 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1913 if (lp->phycount > 1)
1914 lp->options |= PCNET32_PORT_MII;
1917 init_timer(&lp->watchdog_timer);
1918 lp->watchdog_timer.data = (unsigned long)dev;
1919 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1921 /* The PCNET32-specific entries in the device structure. */
1922 dev->netdev_ops = &pcnet32_netdev_ops;
1923 dev->ethtool_ops = &pcnet32_ethtool_ops;
1924 dev->watchdog_timeo = (5 * HZ);
1926 /* Fill in the generic fields of the device structure. */
1927 if (register_netdev(dev))
1931 pci_set_drvdata(pdev, dev);
1933 lp->next = pcnet32_dev;
1937 if (pcnet32_debug & NETIF_MSG_PROBE)
1938 pr_info("%s: registered as %s\n", dev->name, lp->name);
1941 /* enable LED writes */
1942 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1947 pcnet32_free_ring(dev);
1948 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1949 lp->init_block, lp->init_dma_addr);
1953 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1957 /* if any allocation fails, caller must also call pcnet32_free_ring */
1958 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1960 struct pcnet32_private *lp = netdev_priv(dev);
1962 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1963 sizeof(struct pcnet32_tx_head) *
1965 &lp->tx_ring_dma_addr);
1966 if (lp->tx_ring == NULL) {
1967 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1971 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1972 sizeof(struct pcnet32_rx_head) *
1974 &lp->rx_ring_dma_addr);
1975 if (lp->rx_ring == NULL) {
1976 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1980 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1982 if (!lp->tx_dma_addr)
1985 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1987 if (!lp->rx_dma_addr)
1990 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1995 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2003 static void pcnet32_free_ring(struct net_device *dev)
2005 struct pcnet32_private *lp = netdev_priv(dev);
2007 kfree(lp->tx_skbuff);
2008 lp->tx_skbuff = NULL;
2010 kfree(lp->rx_skbuff);
2011 lp->rx_skbuff = NULL;
2013 kfree(lp->tx_dma_addr);
2014 lp->tx_dma_addr = NULL;
2016 kfree(lp->rx_dma_addr);
2017 lp->rx_dma_addr = NULL;
2020 pci_free_consistent(lp->pci_dev,
2021 sizeof(struct pcnet32_tx_head) *
2022 lp->tx_ring_size, lp->tx_ring,
2023 lp->tx_ring_dma_addr);
2028 pci_free_consistent(lp->pci_dev,
2029 sizeof(struct pcnet32_rx_head) *
2030 lp->rx_ring_size, lp->rx_ring,
2031 lp->rx_ring_dma_addr);
2036 static int pcnet32_open(struct net_device *dev)
2038 struct pcnet32_private *lp = netdev_priv(dev);
2039 struct pci_dev *pdev = lp->pci_dev;
2040 unsigned long ioaddr = dev->base_addr;
2044 unsigned long flags;
2046 if (request_irq(dev->irq, pcnet32_interrupt,
2047 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2052 spin_lock_irqsave(&lp->lock, flags);
2053 /* Check for a valid station address */
2054 if (!is_valid_ether_addr(dev->dev_addr)) {
2059 /* Reset the PCNET32 */
2060 lp->a->reset(ioaddr);
2062 /* switch pcnet32 to 32bit mode */
2063 lp->a->write_bcr(ioaddr, 20, 2);
2065 netif_printk(lp, ifup, KERN_DEBUG, dev,
2066 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2067 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2068 (u32) (lp->rx_ring_dma_addr),
2069 (u32) (lp->init_dma_addr));
2071 /* set/reset autoselect bit */
2072 val = lp->a->read_bcr(ioaddr, 2) & ~2;
2073 if (lp->options & PCNET32_PORT_ASEL)
2075 lp->a->write_bcr(ioaddr, 2, val);
2077 /* handle full duplex setting */
2078 if (lp->mii_if.full_duplex) {
2079 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2080 if (lp->options & PCNET32_PORT_FD) {
2082 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2084 } else if (lp->options & PCNET32_PORT_ASEL) {
2085 /* workaround of xSeries250, turn on for 79C975 only */
2086 if (lp->chip_version == 0x2627)
2089 lp->a->write_bcr(ioaddr, 9, val);
2092 /* set/reset GPSI bit in test register */
2093 val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2094 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2096 lp->a->write_csr(ioaddr, 124, val);
2098 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2099 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2100 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2101 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2102 if (lp->options & PCNET32_PORT_ASEL) {
2103 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2104 netif_printk(lp, link, KERN_DEBUG, dev,
2105 "Setting 100Mb-Full Duplex\n");
2108 if (lp->phycount < 2) {
2110 * 24 Jun 2004 according AMD, in order to change the PHY,
2111 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2112 * duplex, and/or enable auto negotiation, and clear DANAS
2114 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2115 lp->a->write_bcr(ioaddr, 32,
2116 lp->a->read_bcr(ioaddr, 32) | 0x0080);
2117 /* disable Auto Negotiation, set 10Mpbs, HD */
2118 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2119 if (lp->options & PCNET32_PORT_FD)
2121 if (lp->options & PCNET32_PORT_100)
2123 lp->a->write_bcr(ioaddr, 32, val);
2125 if (lp->options & PCNET32_PORT_ASEL) {
2126 lp->a->write_bcr(ioaddr, 32,
2127 lp->a->read_bcr(ioaddr,
2129 /* enable auto negotiate, setup, disable fd */
2130 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2132 lp->a->write_bcr(ioaddr, 32, val);
2139 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2142 * There is really no good other way to handle multiple PHYs
2143 * other than turning off all automatics
2145 val = lp->a->read_bcr(ioaddr, 2);
2146 lp->a->write_bcr(ioaddr, 2, val & ~2);
2147 val = lp->a->read_bcr(ioaddr, 32);
2148 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2150 if (!(lp->options & PCNET32_PORT_ASEL)) {
2152 ecmd.port = PORT_MII;
2153 ecmd.transceiver = XCVR_INTERNAL;
2154 ecmd.autoneg = AUTONEG_DISABLE;
2155 ethtool_cmd_speed_set(&ecmd,
2156 (lp->options & PCNET32_PORT_100) ?
2157 SPEED_100 : SPEED_10);
2158 bcr9 = lp->a->read_bcr(ioaddr, 9);
2160 if (lp->options & PCNET32_PORT_FD) {
2161 ecmd.duplex = DUPLEX_FULL;
2164 ecmd.duplex = DUPLEX_HALF;
2167 lp->a->write_bcr(ioaddr, 9, bcr9);
2170 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2171 if (lp->phymask & (1 << i)) {
2172 /* isolate all but the first PHY */
2173 bmcr = mdio_read(dev, i, MII_BMCR);
2174 if (first_phy == -1) {
2176 mdio_write(dev, i, MII_BMCR,
2177 bmcr & ~BMCR_ISOLATE);
2179 mdio_write(dev, i, MII_BMCR,
2180 bmcr | BMCR_ISOLATE);
2182 /* use mii_ethtool_sset to setup PHY */
2183 lp->mii_if.phy_id = i;
2184 ecmd.phy_address = i;
2185 if (lp->options & PCNET32_PORT_ASEL) {
2186 mii_ethtool_gset(&lp->mii_if, &ecmd);
2187 ecmd.autoneg = AUTONEG_ENABLE;
2189 mii_ethtool_sset(&lp->mii_if, &ecmd);
2192 lp->mii_if.phy_id = first_phy;
2193 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2197 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2198 val = lp->a->read_csr(ioaddr, CSR3);
2200 lp->a->write_csr(ioaddr, CSR3, val);
2204 lp->init_block->mode =
2205 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2206 pcnet32_load_multicast(dev);
2208 if (pcnet32_init_ring(dev)) {
2213 napi_enable(&lp->napi);
2215 /* Re-initialize the PCNET32, and start it when done. */
2216 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2217 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2219 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2220 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2222 netif_start_queue(dev);
2224 if (lp->chip_version >= PCNET32_79C970A) {
2225 /* Print the link status and start the watchdog */
2226 pcnet32_check_media(dev, 1);
2227 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2232 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2235 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2236 * reports that doing so triggers a bug in the '974.
2238 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2240 netif_printk(lp, ifup, KERN_DEBUG, dev,
2241 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2243 (u32) (lp->init_dma_addr),
2244 lp->a->read_csr(ioaddr, CSR0));
2246 spin_unlock_irqrestore(&lp->lock, flags);
2248 return 0; /* Always succeed */
2251 /* free any allocated skbuffs */
2252 pcnet32_purge_rx_ring(dev);
2255 * Switch back to 16bit mode to avoid problems with dumb
2256 * DOS packet driver after a warm reboot
2258 lp->a->write_bcr(ioaddr, 20, 4);
2261 spin_unlock_irqrestore(&lp->lock, flags);
2262 free_irq(dev->irq, dev);
2267 * The LANCE has been halted for one reason or another (busmaster memory
2268 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2269 * etc.). Modern LANCE variants always reload their ring-buffer
2270 * configuration when restarted, so we must reinitialize our ring
2271 * context before restarting. As part of this reinitialization,
2272 * find all packets still on the Tx ring and pretend that they had been
2273 * sent (in effect, drop the packets on the floor) - the higher-level
2274 * protocols will time out and retransmit. It'd be better to shuffle
2275 * these skbs to a temp list and then actually re-Tx them after
2276 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2279 static void pcnet32_purge_tx_ring(struct net_device *dev)
2281 struct pcnet32_private *lp = netdev_priv(dev);
2284 for (i = 0; i < lp->tx_ring_size; i++) {
2285 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2286 wmb(); /* Make sure adapter sees owner change */
2287 if (lp->tx_skbuff[i]) {
2288 if (!pci_dma_mapping_error(lp->pci_dev,
2289 lp->tx_dma_addr[i]))
2290 pci_unmap_single(lp->pci_dev,
2292 lp->tx_skbuff[i]->len,
2294 dev_kfree_skb_any(lp->tx_skbuff[i]);
2296 lp->tx_skbuff[i] = NULL;
2297 lp->tx_dma_addr[i] = 0;
2301 /* Initialize the PCNET32 Rx and Tx rings. */
2302 static int pcnet32_init_ring(struct net_device *dev)
2304 struct pcnet32_private *lp = netdev_priv(dev);
2308 lp->cur_rx = lp->cur_tx = 0;
2309 lp->dirty_rx = lp->dirty_tx = 0;
2311 for (i = 0; i < lp->rx_ring_size; i++) {
2312 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2313 if (rx_skbuff == NULL) {
2314 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2315 rx_skbuff = lp->rx_skbuff[i];
2317 /* there is not much we can do at this point */
2318 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2322 skb_reserve(rx_skbuff, NET_IP_ALIGN);
2326 if (lp->rx_dma_addr[i] == 0) {
2327 lp->rx_dma_addr[i] =
2328 pci_map_single(lp->pci_dev, rx_skbuff->data,
2329 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2330 if (pci_dma_mapping_error(lp->pci_dev,
2331 lp->rx_dma_addr[i])) {
2332 /* there is not much we can do at this point */
2333 netif_err(lp, drv, dev,
2334 "%s pci dma mapping error\n",
2339 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2340 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2341 wmb(); /* Make sure owner changes after all others are visible */
2342 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2344 /* The Tx buffer address is filled in as needed, but we do need to clear
2345 * the upper ownership bit. */
2346 for (i = 0; i < lp->tx_ring_size; i++) {
2347 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2348 wmb(); /* Make sure adapter sees owner change */
2349 lp->tx_ring[i].base = 0;
2350 lp->tx_dma_addr[i] = 0;
2353 lp->init_block->tlen_rlen =
2354 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2355 for (i = 0; i < 6; i++)
2356 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2357 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2358 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2359 wmb(); /* Make sure all changes are visible */
2363 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2364 * then flush the pending transmit operations, re-initialize the ring,
2365 * and tell the chip to initialize.
2367 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2369 struct pcnet32_private *lp = netdev_priv(dev);
2370 unsigned long ioaddr = dev->base_addr;
2374 for (i = 0; i < 100; i++)
2375 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2379 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2382 pcnet32_purge_tx_ring(dev);
2383 if (pcnet32_init_ring(dev))
2387 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2390 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2393 lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2396 static void pcnet32_tx_timeout(struct net_device *dev)
2398 struct pcnet32_private *lp = netdev_priv(dev);
2399 unsigned long ioaddr = dev->base_addr, flags;
2401 spin_lock_irqsave(&lp->lock, flags);
2402 /* Transmitter timeout, serious problems. */
2403 if (pcnet32_debug & NETIF_MSG_DRV)
2404 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2405 dev->name, lp->a->read_csr(ioaddr, CSR0));
2406 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2407 dev->stats.tx_errors++;
2408 if (netif_msg_tx_err(lp)) {
2411 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2412 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2414 for (i = 0; i < lp->rx_ring_size; i++)
2415 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2416 le32_to_cpu(lp->rx_ring[i].base),
2417 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2418 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2419 le16_to_cpu(lp->rx_ring[i].status));
2420 for (i = 0; i < lp->tx_ring_size; i++)
2421 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2422 le32_to_cpu(lp->tx_ring[i].base),
2423 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2424 le32_to_cpu(lp->tx_ring[i].misc),
2425 le16_to_cpu(lp->tx_ring[i].status));
2428 pcnet32_restart(dev, CSR0_NORMAL);
2430 netif_trans_update(dev); /* prevent tx timeout */
2431 netif_wake_queue(dev);
2433 spin_unlock_irqrestore(&lp->lock, flags);
2436 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2437 struct net_device *dev)
2439 struct pcnet32_private *lp = netdev_priv(dev);
2440 unsigned long ioaddr = dev->base_addr;
2443 unsigned long flags;
2445 spin_lock_irqsave(&lp->lock, flags);
2447 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2448 "%s() called, csr0 %4.4x\n",
2449 __func__, lp->a->read_csr(ioaddr, CSR0));
2451 /* Default status -- will not enable Successful-TxDone
2452 * interrupt when that option is available to us.
2456 /* Fill in a Tx ring entry */
2458 /* Mask to ring buffer boundary. */
2459 entry = lp->cur_tx & lp->tx_mod_mask;
2461 /* Caution: the write order is important here, set the status
2462 * with the "ownership" bits last. */
2464 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2466 lp->tx_ring[entry].misc = 0x00000000;
2468 lp->tx_dma_addr[entry] =
2469 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2470 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[entry])) {
2471 dev_kfree_skb_any(skb);
2472 dev->stats.tx_dropped++;
2475 lp->tx_skbuff[entry] = skb;
2476 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2477 wmb(); /* Make sure owner changes after all others are visible */
2478 lp->tx_ring[entry].status = cpu_to_le16(status);
2481 dev->stats.tx_bytes += skb->len;
2483 /* Trigger an immediate send poll. */
2484 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2486 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2488 netif_stop_queue(dev);
2491 spin_unlock_irqrestore(&lp->lock, flags);
2492 return NETDEV_TX_OK;
2495 /* The PCNET32 interrupt handler. */
2497 pcnet32_interrupt(int irq, void *dev_id)
2499 struct net_device *dev = dev_id;
2500 struct pcnet32_private *lp;
2501 unsigned long ioaddr;
2503 int boguscnt = max_interrupt_work;
2505 ioaddr = dev->base_addr;
2506 lp = netdev_priv(dev);
2508 spin_lock(&lp->lock);
2510 csr0 = lp->a->read_csr(ioaddr, CSR0);
2511 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2513 break; /* PCMCIA remove happened */
2514 /* Acknowledge all of the current interrupt sources ASAP. */
2515 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2517 netif_printk(lp, intr, KERN_DEBUG, dev,
2518 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
2519 csr0, lp->a->read_csr(ioaddr, CSR0));
2521 /* Log misc errors. */
2523 dev->stats.tx_errors++; /* Tx babble. */
2524 if (csr0 & 0x1000) {
2526 * This happens when our receive ring is full. This
2527 * shouldn't be a problem as we will see normal rx
2528 * interrupts for the frames in the receive ring. But
2529 * there are some PCI chipsets (I can reproduce this
2530 * on SP3G with Intel saturn chipset) which have
2531 * sometimes problems and will fill up the receive
2532 * ring with error descriptors. In this situation we
2533 * don't get a rx interrupt, but a missed frame
2534 * interrupt sooner or later.
2536 dev->stats.rx_errors++; /* Missed a Rx frame. */
2538 if (csr0 & 0x0800) {
2539 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2541 /* unlike for the lance, there is no restart needed */
2543 if (napi_schedule_prep(&lp->napi)) {
2545 /* set interrupt masks */
2546 val = lp->a->read_csr(ioaddr, CSR3);
2548 lp->a->write_csr(ioaddr, CSR3, val);
2550 __napi_schedule(&lp->napi);
2553 csr0 = lp->a->read_csr(ioaddr, CSR0);
2556 netif_printk(lp, intr, KERN_DEBUG, dev,
2557 "exiting interrupt, csr0=%#4.4x\n",
2558 lp->a->read_csr(ioaddr, CSR0));
2560 spin_unlock(&lp->lock);
2565 static int pcnet32_close(struct net_device *dev)
2567 unsigned long ioaddr = dev->base_addr;
2568 struct pcnet32_private *lp = netdev_priv(dev);
2569 unsigned long flags;
2571 del_timer_sync(&lp->watchdog_timer);
2573 netif_stop_queue(dev);
2574 napi_disable(&lp->napi);
2576 spin_lock_irqsave(&lp->lock, flags);
2578 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2580 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2581 "Shutting down ethercard, status was %2.2x\n",
2582 lp->a->read_csr(ioaddr, CSR0));
2584 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2585 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2588 * Switch back to 16bit mode to avoid problems with dumb
2589 * DOS packet driver after a warm reboot
2591 lp->a->write_bcr(ioaddr, 20, 4);
2593 spin_unlock_irqrestore(&lp->lock, flags);
2595 free_irq(dev->irq, dev);
2597 spin_lock_irqsave(&lp->lock, flags);
2599 pcnet32_purge_rx_ring(dev);
2600 pcnet32_purge_tx_ring(dev);
2602 spin_unlock_irqrestore(&lp->lock, flags);
2607 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2609 struct pcnet32_private *lp = netdev_priv(dev);
2610 unsigned long ioaddr = dev->base_addr;
2611 unsigned long flags;
2613 spin_lock_irqsave(&lp->lock, flags);
2614 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2615 spin_unlock_irqrestore(&lp->lock, flags);
2620 /* taken from the sunlance driver, which it took from the depca driver */
2621 static void pcnet32_load_multicast(struct net_device *dev)
2623 struct pcnet32_private *lp = netdev_priv(dev);
2624 volatile struct pcnet32_init_block *ib = lp->init_block;
2625 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2626 struct netdev_hw_addr *ha;
2627 unsigned long ioaddr = dev->base_addr;
2631 /* set all multicast bits */
2632 if (dev->flags & IFF_ALLMULTI) {
2633 ib->filter[0] = cpu_to_le32(~0U);
2634 ib->filter[1] = cpu_to_le32(~0U);
2635 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2636 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2637 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2638 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2641 /* clear the multicast filter */
2646 netdev_for_each_mc_addr(ha, dev) {
2647 crc = ether_crc_le(6, ha->addr);
2649 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2651 for (i = 0; i < 4; i++)
2652 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2653 le16_to_cpu(mcast_table[i]));
2657 * Set or clear the multicast filter for this adaptor.
2659 static void pcnet32_set_multicast_list(struct net_device *dev)
2661 unsigned long ioaddr = dev->base_addr, flags;
2662 struct pcnet32_private *lp = netdev_priv(dev);
2663 int csr15, suspended;
2665 spin_lock_irqsave(&lp->lock, flags);
2666 suspended = pcnet32_suspend(dev, &flags, 0);
2667 csr15 = lp->a->read_csr(ioaddr, CSR15);
2668 if (dev->flags & IFF_PROMISC) {
2669 /* Log any net taps. */
2670 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2671 lp->init_block->mode =
2672 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2674 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2676 lp->init_block->mode =
2677 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2678 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2679 pcnet32_load_multicast(dev);
2684 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2685 csr5 = lp->a->read_csr(ioaddr, CSR5);
2686 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2688 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2689 pcnet32_restart(dev, CSR0_NORMAL);
2690 netif_wake_queue(dev);
2693 spin_unlock_irqrestore(&lp->lock, flags);
2696 /* This routine assumes that the lp->lock is held */
2697 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2699 struct pcnet32_private *lp = netdev_priv(dev);
2700 unsigned long ioaddr = dev->base_addr;
2706 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2707 val_out = lp->a->read_bcr(ioaddr, 34);
2712 /* This routine assumes that the lp->lock is held */
2713 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2715 struct pcnet32_private *lp = netdev_priv(dev);
2716 unsigned long ioaddr = dev->base_addr;
2721 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2722 lp->a->write_bcr(ioaddr, 34, val);
2725 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2727 struct pcnet32_private *lp = netdev_priv(dev);
2729 unsigned long flags;
2731 /* SIOC[GS]MIIxxx ioctls */
2733 spin_lock_irqsave(&lp->lock, flags);
2734 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2735 spin_unlock_irqrestore(&lp->lock, flags);
2743 static int pcnet32_check_otherphy(struct net_device *dev)
2745 struct pcnet32_private *lp = netdev_priv(dev);
2746 struct mii_if_info mii = lp->mii_if;
2750 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2751 if (i == lp->mii_if.phy_id)
2752 continue; /* skip active phy */
2753 if (lp->phymask & (1 << i)) {
2755 if (mii_link_ok(&mii)) {
2756 /* found PHY with active link */
2757 netif_info(lp, link, dev, "Using PHY number %d\n",
2760 /* isolate inactive phy */
2762 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2763 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2764 bmcr | BMCR_ISOLATE);
2766 /* de-isolate new phy */
2767 bmcr = mdio_read(dev, i, MII_BMCR);
2768 mdio_write(dev, i, MII_BMCR,
2769 bmcr & ~BMCR_ISOLATE);
2771 /* set new phy address */
2772 lp->mii_if.phy_id = i;
2781 * Show the status of the media. Similar to mii_check_media however it
2782 * correctly shows the link speed for all (tested) pcnet32 variants.
2783 * Devices with no mii just report link state without speed.
2785 * Caller is assumed to hold and release the lp->lock.
2788 static void pcnet32_check_media(struct net_device *dev, int verbose)
2790 struct pcnet32_private *lp = netdev_priv(dev);
2792 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2796 curr_link = mii_link_ok(&lp->mii_if);
2798 ulong ioaddr = dev->base_addr; /* card base I/O address */
2799 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2802 if (prev_link || verbose) {
2803 netif_carrier_off(dev);
2804 netif_info(lp, link, dev, "link down\n");
2806 if (lp->phycount > 1) {
2807 curr_link = pcnet32_check_otherphy(dev);
2810 } else if (verbose || !prev_link) {
2811 netif_carrier_on(dev);
2813 if (netif_msg_link(lp)) {
2814 struct ethtool_cmd ecmd = {
2815 .cmd = ETHTOOL_GSET };
2816 mii_ethtool_gset(&lp->mii_if, &ecmd);
2817 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2818 ethtool_cmd_speed(&ecmd),
2819 (ecmd.duplex == DUPLEX_FULL)
2822 bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2823 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2824 if (lp->mii_if.full_duplex)
2828 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2831 netif_info(lp, link, dev, "link up\n");
2837 * Check for loss of link and link establishment.
2838 * Could possibly be changed to use mii_check_media instead.
2841 static void pcnet32_watchdog(struct net_device *dev)
2843 struct pcnet32_private *lp = netdev_priv(dev);
2844 unsigned long flags;
2846 /* Print the link status if it has changed */
2847 spin_lock_irqsave(&lp->lock, flags);
2848 pcnet32_check_media(dev, 0);
2849 spin_unlock_irqrestore(&lp->lock, flags);
2851 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2854 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2856 struct net_device *dev = pci_get_drvdata(pdev);
2858 if (netif_running(dev)) {
2859 netif_device_detach(dev);
2862 pci_save_state(pdev);
2863 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2867 static int pcnet32_pm_resume(struct pci_dev *pdev)
2869 struct net_device *dev = pci_get_drvdata(pdev);
2871 pci_set_power_state(pdev, PCI_D0);
2872 pci_restore_state(pdev);
2874 if (netif_running(dev)) {
2876 netif_device_attach(dev);
2881 static void pcnet32_remove_one(struct pci_dev *pdev)
2883 struct net_device *dev = pci_get_drvdata(pdev);
2886 struct pcnet32_private *lp = netdev_priv(dev);
2888 unregister_netdev(dev);
2889 pcnet32_free_ring(dev);
2890 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2891 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2892 lp->init_block, lp->init_dma_addr);
2894 pci_disable_device(pdev);
2898 static struct pci_driver pcnet32_driver = {
2900 .probe = pcnet32_probe_pci,
2901 .remove = pcnet32_remove_one,
2902 .id_table = pcnet32_pci_tbl,
2903 .suspend = pcnet32_pm_suspend,
2904 .resume = pcnet32_pm_resume,
2907 /* An additional parameter that may be passed in... */
2908 static int debug = -1;
2909 static int tx_start_pt = -1;
2910 static int pcnet32_have_pci;
2912 module_param(debug, int, 0);
2913 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2914 module_param(max_interrupt_work, int, 0);
2915 MODULE_PARM_DESC(max_interrupt_work,
2916 DRV_NAME " maximum events handled per interrupt");
2917 module_param(rx_copybreak, int, 0);
2918 MODULE_PARM_DESC(rx_copybreak,
2919 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2920 module_param(tx_start_pt, int, 0);
2921 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2922 module_param(pcnet32vlb, int, 0);
2923 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2924 module_param_array(options, int, NULL, 0);
2925 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2926 module_param_array(full_duplex, int, NULL, 0);
2927 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2928 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2929 module_param_array(homepna, int, NULL, 0);
2930 MODULE_PARM_DESC(homepna,
2932 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2934 MODULE_AUTHOR("Thomas Bogendoerfer");
2935 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2936 MODULE_LICENSE("GPL");
2938 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2940 static int __init pcnet32_init_module(void)
2942 pr_info("%s", version);
2944 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2946 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2947 tx_start = tx_start_pt;
2949 /* find the PCI devices */
2950 if (!pci_register_driver(&pcnet32_driver))
2951 pcnet32_have_pci = 1;
2953 /* should we find any remaining VLbus devices ? */
2955 pcnet32_probe_vlbus(pcnet32_portlist);
2957 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2958 pr_info("%d cards_found\n", cards_found);
2960 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2963 static void __exit pcnet32_cleanup_module(void)
2965 struct net_device *next_dev;
2967 while (pcnet32_dev) {
2968 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
2969 next_dev = lp->next;
2970 unregister_netdev(pcnet32_dev);
2971 pcnet32_free_ring(pcnet32_dev);
2972 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2973 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2974 lp->init_block, lp->init_dma_addr);
2975 free_netdev(pcnet32_dev);
2976 pcnet32_dev = next_dev;
2979 if (pcnet32_have_pci)
2980 pci_unregister_driver(&pcnet32_driver);
2983 module_init(pcnet32_init_module);
2984 module_exit(pcnet32_cleanup_module);