drivers/net/ethernet/amd/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #define DRV_NAME        "pcnet32"
  27 #define DRV_VERSION     "1.35"
  28 #define DRV_RELDATE     "21.Apr.2008"
  29 #define PFX             DRV_NAME ": "
  30
  31 static const char *const version =
  32     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/sched.h>
  37 #include <linux/string.h>
  38 #include <linux/errno.h>
  39 #include <linux/ioport.h>
  40 #include <linux/slab.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/delay.h>
  44 #include <linux/init.h>
  45 #include <linux/ethtool.h>
  46 #include <linux/mii.h>
  47 #include <linux/crc32.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/if_ether.h>
  51 #include <linux/skbuff.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/bitops.h>
  55 #include <linux/io.h>
  56 #include <linux/uaccess.h>
  57
  58 #include <asm/dma.h>
  59 #include <asm/irq.h>
  60
  61 /*
  62  * PCI device identifiers for "new style" Linux PCI Device Drivers
  63  */
  64 static const struct pci_device_id pcnet32_pci_tbl[] = {
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  67
  68         /*
  69          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  70          * the incorrect vendor id.
  71          */
  72         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  73           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  74
  75         { }     /* terminate list */
  76 };
  77
  78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  79
  80 static int cards_found;
  81
  82 /*
  83  * VLB I/O addresses
  84  */
  85 static unsigned int pcnet32_portlist[] =
  86     { 0x300, 0x320, 0x340, 0x360, 0 };
  87
  88 static int pcnet32_debug;
  89 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  90 static int pcnet32vlb;          /* check for VLB cards ? */
  91
  92 static struct net_device *pcnet32_dev;
  93
  94 static int max_interrupt_work = 2;
  95 static int rx_copybreak = 200;
  96
  97 #define PCNET32_PORT_AUI      0x00
  98 #define PCNET32_PORT_10BT     0x01
  99 #define PCNET32_PORT_GPSI     0x02
 100 #define PCNET32_PORT_MII      0x03
 101
 102 #define PCNET32_PORT_PORTSEL  0x03
 103 #define PCNET32_PORT_ASEL     0x04
 104 #define PCNET32_PORT_100      0x40
 105 #define PCNET32_PORT_FD       0x80
 106
 107 #define PCNET32_DMA_MASK 0xffffffff
 108
 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 110 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 111
 112 /*
 113  * table to translate option values from tulip
 114  * to internal options
 115  */
 116 static const unsigned char options_mapping[] = {
 117         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 118         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 119         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 120         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 121         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 122         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 123         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 124         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 125         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 126         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 127         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 128         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 129         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 130         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 131                                                 /* 14 MII 100BaseTx-FD */
 132         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 133         PCNET32_PORT_ASEL                       /* 15 not supported    */
 134 };
 135
 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 137         "Loopback test  (offline)"
 138 };
 139
 140 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 141
 142 #define PCNET32_NUM_REGS 136
 143
 144 #define MAX_UNITS 8             /* More are supported, limit only on options */
 145 static int options[MAX_UNITS];
 146 static int full_duplex[MAX_UNITS];
 147 static int homepna[MAX_UNITS];
 148
 149 /*
 150  *                              Theory of Operation
 151  *
 152  * This driver uses the same software structure as the normal lance
 153  * driver. So look for a verbose description in lance.c. The differences
 154  * to the normal lance driver is the use of the 32bit mode of PCnet32
 155  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 156  * 16MB limitation and we don't need bounce buffers.
 157  */
 158
 159 /*
 160  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 161  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 162  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 163  */
 164 #ifndef PCNET32_LOG_TX_BUFFERS
 165 #define PCNET32_LOG_TX_BUFFERS          4
 166 #define PCNET32_LOG_RX_BUFFERS          5
 167 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 168 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 169 #endif
 170
 171 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 172 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 173
 174 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 175 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 176
 177 #define PKT_BUF_SKB             1544
 178 /* actual buffer length after being aligned */
 179 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 180 /* chip wants twos complement of the (aligned) buffer length */
 181 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 182
 183 /* Offsets from base I/O address. */
 184 #define PCNET32_WIO_RDP         0x10
 185 #define PCNET32_WIO_RAP         0x12
 186 #define PCNET32_WIO_RESET       0x14
 187 #define PCNET32_WIO_BDP         0x16
 188
 189 #define PCNET32_DWIO_RDP        0x10
 190 #define PCNET32_DWIO_RAP        0x14
 191 #define PCNET32_DWIO_RESET      0x18
 192 #define PCNET32_DWIO_BDP        0x1C
 193
 194 #define PCNET32_TOTAL_SIZE      0x20
 195
 196 #define CSR0            0
 197 #define CSR0_INIT       0x1
 198 #define CSR0_START      0x2
 199 #define CSR0_STOP       0x4
 200 #define CSR0_TXPOLL     0x8
 201 #define CSR0_INTEN      0x40
 202 #define CSR0_IDON       0x0100
 203 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 204 #define PCNET32_INIT_LOW        1
 205 #define PCNET32_INIT_HIGH       2
 206 #define CSR3            3
 207 #define CSR4            4
 208 #define CSR5            5
 209 #define CSR5_SUSPEND    0x0001
 210 #define CSR15           15
 211 #define PCNET32_MC_FILTER       8
 212
 213 #define PCNET32_79C970A 0x2621
 214
 215 /* The PCNET32 Rx and Tx ring descriptors. */
 216 struct pcnet32_rx_head {
 217         __le32  base;
 218         __le16  buf_length;     /* two`s complement of length */
 219         __le16  status;
 220         __le32  msg_length;
 221         __le32  reserved;
 222 };
 223
 224 struct pcnet32_tx_head {
 225         __le32  base;
 226         __le16  length;         /* two`s complement of length */
 227         __le16  status;
 228         __le32  misc;
 229         __le32  reserved;
 230 };
 231
 232 /* The PCNET32 32-Bit initialization block, described in databook. */
 233 struct pcnet32_init_block {
 234         __le16  mode;
 235         __le16  tlen_rlen;
 236         u8      phys_addr[6];
 237         __le16  reserved;
 238         __le32  filter[2];
 239         /* Receive and transmit ring base, along with extra bits. */
 240         __le32  rx_ring;
 241         __le32  tx_ring;
 242 };
 243
 244 /* PCnet32 access functions */
 245 struct pcnet32_access {
 246         u16     (*read_csr) (unsigned long, int);
 247         void    (*write_csr) (unsigned long, int, u16);
 248         u16     (*read_bcr) (unsigned long, int);
 249         void    (*write_bcr) (unsigned long, int, u16);
 250         u16     (*read_rap) (unsigned long);
 251         void    (*write_rap) (unsigned long, u16);
 252         void    (*reset) (unsigned long);
 253 };
 254
 255 /*
 256  * The first field of pcnet32_private is read by the ethernet device
 257  * so the structure should be allocated using pci_alloc_consistent().
 258  */
 259 struct pcnet32_private {
 260         struct pcnet32_init_block *init_block;
 261         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 262         struct pcnet32_rx_head  *rx_ring;
 263         struct pcnet32_tx_head  *tx_ring;
 264         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 265                                    returned by pci_alloc_consistent */
 266         struct pci_dev          *pci_dev;
 267         const char              *name;
 268         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 269         struct sk_buff          **tx_skbuff;
 270         struct sk_buff          **rx_skbuff;
 271         dma_addr_t              *tx_dma_addr;
 272         dma_addr_t              *rx_dma_addr;
 273         const struct pcnet32_access *a;
 274         spinlock_t              lock;           /* Guard lock */
 275         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 276         unsigned int            rx_ring_size;   /* current rx ring size */
 277         unsigned int            tx_ring_size;   /* current tx ring size */
 278         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 279         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 280         unsigned short          rx_len_bits;
 281         unsigned short          tx_len_bits;
 282         dma_addr_t              rx_ring_dma_addr;
 283         dma_addr_t              tx_ring_dma_addr;
 284         unsigned int            dirty_rx,       /* ring entries to be freed. */
 285                                 dirty_tx;
 286
 287         struct net_device       *dev;
 288         struct napi_struct      napi;
 289         char                    tx_full;
 290         char                    phycount;       /* number of phys found */
 291         int                     options;
 292         unsigned int            shared_irq:1,   /* shared irq possible */
 293                                 dxsuflo:1,   /* disable transmit stop on uflo */
 294                                 mii:1,          /* mii port available */
 295                                 autoneg:1,      /* autoneg enabled */
 296                                 port_tp:1,      /* port set to TP */
 297                                 fdx:1;          /* full duplex enabled */
 298         struct net_device       *next;
 299         struct mii_if_info      mii_if;
 300         struct timer_list       watchdog_timer;
 301         u32                     msg_enable;     /* debug message level */
 302
 303         /* each bit indicates an available PHY */
 304         u32                     phymask;
 305         unsigned short          chip_version;   /* which variant this is */
 306
 307         /* saved registers during ethtool blink */
 308         u16                     save_regs[4];
 309 };
 310
 311 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 312 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 313 static int pcnet32_open(struct net_device *);
 314 static int pcnet32_init_ring(struct net_device *);
 315 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
 316                                       struct net_device *);
 317 static void pcnet32_tx_timeout(struct net_device *dev);
 318 static irqreturn_t pcnet32_interrupt(int, void *);
 319 static int pcnet32_close(struct net_device *);
 320 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 321 static void pcnet32_load_multicast(struct net_device *dev);
 322 static void pcnet32_set_multicast_list(struct net_device *);
 323 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 324 static void pcnet32_watchdog(struct net_device *);
 325 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 326 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 327                        int val);
 328 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 329 static void pcnet32_ethtool_test(struct net_device *dev,
 330                                  struct ethtool_test *eth_test, u64 * data);
 331 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 332 static int pcnet32_get_regs_len(struct net_device *dev);
 333 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 334                              void *ptr);
 335 static void pcnet32_purge_tx_ring(struct net_device *dev);
 336 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 337 static void pcnet32_free_ring(struct net_device *dev);
 338 static void pcnet32_check_media(struct net_device *dev, int verbose);
 339
 340 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 341 {
 342         outw(index, addr + PCNET32_WIO_RAP);
 343         return inw(addr + PCNET32_WIO_RDP);
 344 }
 345
 346 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 347 {
 348         outw(index, addr + PCNET32_WIO_RAP);
 349         outw(val, addr + PCNET32_WIO_RDP);
 350 }
 351
 352 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 353 {
 354         outw(index, addr + PCNET32_WIO_RAP);
 355         return inw(addr + PCNET32_WIO_BDP);
 356 }
 357
 358 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 359 {
 360         outw(index, addr + PCNET32_WIO_RAP);
 361         outw(val, addr + PCNET32_WIO_BDP);
 362 }
 363
 364 static u16 pcnet32_wio_read_rap(unsigned long addr)
 365 {
 366         return inw(addr + PCNET32_WIO_RAP);
 367 }
 368
 369 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 370 {
 371         outw(val, addr + PCNET32_WIO_RAP);
 372 }
 373
 374 static void pcnet32_wio_reset(unsigned long addr)
 375 {
 376         inw(addr + PCNET32_WIO_RESET);
 377 }
 378
 379 static int pcnet32_wio_check(unsigned long addr)
 380 {
 381         outw(88, addr + PCNET32_WIO_RAP);
 382         return inw(addr + PCNET32_WIO_RAP) == 88;
 383 }
 384
 385 static const struct pcnet32_access pcnet32_wio = {
 386         .read_csr = pcnet32_wio_read_csr,
 387         .write_csr = pcnet32_wio_write_csr,
 388         .read_bcr = pcnet32_wio_read_bcr,
 389         .write_bcr = pcnet32_wio_write_bcr,
 390         .read_rap = pcnet32_wio_read_rap,
 391         .write_rap = pcnet32_wio_write_rap,
 392         .reset = pcnet32_wio_reset
 393 };
 394
 395 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 396 {
 397         outl(index, addr + PCNET32_DWIO_RAP);
 398         return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
 399 }
 400
 401 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 402 {
 403         outl(index, addr + PCNET32_DWIO_RAP);
 404         outl(val, addr + PCNET32_DWIO_RDP);
 405 }
 406
 407 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 408 {
 409         outl(index, addr + PCNET32_DWIO_RAP);
 410         return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
 411 }
 412
 413 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 414 {
 415         outl(index, addr + PCNET32_DWIO_RAP);
 416         outl(val, addr + PCNET32_DWIO_BDP);
 417 }
 418
 419 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 420 {
 421         return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
 422 }
 423
 424 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 425 {
 426         outl(val, addr + PCNET32_DWIO_RAP);
 427 }
 428
 429 static void pcnet32_dwio_reset(unsigned long addr)
 430 {
 431         inl(addr + PCNET32_DWIO_RESET);
 432 }
 433
 434 static int pcnet32_dwio_check(unsigned long addr)
 435 {
 436         outl(88, addr + PCNET32_DWIO_RAP);
 437         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
 438 }
 439
 440 static const struct pcnet32_access pcnet32_dwio = {
 441         .read_csr = pcnet32_dwio_read_csr,
 442         .write_csr = pcnet32_dwio_write_csr,
 443         .read_bcr = pcnet32_dwio_read_bcr,
 444         .write_bcr = pcnet32_dwio_write_bcr,
 445         .read_rap = pcnet32_dwio_read_rap,
 446         .write_rap = pcnet32_dwio_write_rap,
 447         .reset = pcnet32_dwio_reset
 448 };
 449
 450 static void pcnet32_netif_stop(struct net_device *dev)
 451 {
 452         struct pcnet32_private *lp = netdev_priv(dev);
 453
 454         netif_trans_update(dev); /* prevent tx timeout */
 455         napi_disable(&lp->napi);
 456         netif_tx_disable(dev);
 457 }
 458
 459 static void pcnet32_netif_start(struct net_device *dev)
 460 {
 461         struct pcnet32_private *lp = netdev_priv(dev);
 462         ulong ioaddr = dev->base_addr;
 463         u16 val;
 464
 465         netif_wake_queue(dev);
 466         val = lp->a->read_csr(ioaddr, CSR3);
 467         val &= 0x00ff;
 468         lp->a->write_csr(ioaddr, CSR3, val);
 469         napi_enable(&lp->napi);
 470 }
 471
 472 /*
 473  * Allocate space for the new sized tx ring.
 474  * Free old resources
 475  * Save new resources.
 476  * Any failure keeps old resources.
 477  * Must be called with lp->lock held.
 478  */
 479 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 480                                     struct pcnet32_private *lp,
 481                                     unsigned int size)
 482 {
 483         dma_addr_t new_ring_dma_addr;
 484         dma_addr_t *new_dma_addr_list;
 485         struct pcnet32_tx_head *new_tx_ring;
 486         struct sk_buff **new_skb_list;
 487         unsigned int entries = BIT(size);
 488
 489         pcnet32_purge_tx_ring(dev);
 490
 491         new_tx_ring =
 492                 pci_zalloc_consistent(lp->pci_dev,
 493                                       sizeof(struct pcnet32_tx_head) * entries,
 494                                       &new_ring_dma_addr);
 495         if (new_tx_ring == NULL)
 496                 return;
 497
 498         new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
 499         if (!new_dma_addr_list)
 500                 goto free_new_tx_ring;
 501
 502         new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
 503         if (!new_skb_list)
 504                 goto free_new_lists;
 505
 506         kfree(lp->tx_skbuff);
 507         kfree(lp->tx_dma_addr);
 508         pci_free_consistent(lp->pci_dev,
 509                             sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
 510                             lp->tx_ring, lp->tx_ring_dma_addr);
 511
 512         lp->tx_ring_size = entries;
 513         lp->tx_mod_mask = lp->tx_ring_size - 1;
 514         lp->tx_len_bits = (size << 12);
 515         lp->tx_ring = new_tx_ring;
 516         lp->tx_ring_dma_addr = new_ring_dma_addr;
 517         lp->tx_dma_addr = new_dma_addr_list;
 518         lp->tx_skbuff = new_skb_list;
 519         return;
 520
 521 free_new_lists:
 522         kfree(new_dma_addr_list);
 523 free_new_tx_ring:
 524         pci_free_consistent(lp->pci_dev,
 525                             sizeof(struct pcnet32_tx_head) * entries,
 526                             new_tx_ring,
 527                             new_ring_dma_addr);
 528 }
 529
 530 /*
 531  * Allocate space for the new sized rx ring.
 532  * Re-use old receive buffers.
 533  *   alloc extra buffers
 534  *   free unneeded buffers
 535  *   free unneeded buffers
 536  * Save new resources.
 537  * Any failure keeps old resources.
 538  * Must be called with lp->lock held.
 539  */
 540 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 541                                     struct pcnet32_private *lp,
 542                                     unsigned int size)
 543 {
 544         dma_addr_t new_ring_dma_addr;
 545         dma_addr_t *new_dma_addr_list;
 546         struct pcnet32_rx_head *new_rx_ring;
 547         struct sk_buff **new_skb_list;
 548         int new, overlap;
 549         unsigned int entries = BIT(size);
 550
 551         new_rx_ring =
 552                 pci_zalloc_consistent(lp->pci_dev,
 553                                       sizeof(struct pcnet32_rx_head) * entries,
 554                                       &new_ring_dma_addr);
 555         if (new_rx_ring == NULL)
 556                 return;
 557
 558         new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
 559         if (!new_dma_addr_list)
 560                 goto free_new_rx_ring;
 561
 562         new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
 563         if (!new_skb_list)
 564                 goto free_new_lists;
 565
 566         /* first copy the current receive buffers */
 567         overlap = min(entries, lp->rx_ring_size);
 568         for (new = 0; new < overlap; new++) {
 569                 new_rx_ring[new] = lp->rx_ring[new];
 570                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 571                 new_skb_list[new] = lp->rx_skbuff[new];
 572         }
 573         /* now allocate any new buffers needed */
 574         for (; new < entries; new++) {
 575                 struct sk_buff *rx_skbuff;
 576                 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
 577                 rx_skbuff = new_skb_list[new];
 578                 if (!rx_skbuff) {
 579                         /* keep the original lists and buffers */
 580                         netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
 581                                   __func__);
 582                         goto free_all_new;
 583                 }
 584                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 585
 586                 new_dma_addr_list[new] =
 587                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 588                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 589                 if (pci_dma_mapping_error(lp->pci_dev,
 590                                           new_dma_addr_list[new])) {
 591                         netif_err(lp, drv, dev, "%s dma mapping failed\n",
 592                                   __func__);
 593                         dev_kfree_skb(new_skb_list[new]);
 594                         goto free_all_new;
 595                 }
 596                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 597                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 598                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 599         }
 600         /* and free any unneeded buffers */
 601         for (; new < lp->rx_ring_size; new++) {
 602                 if (lp->rx_skbuff[new]) {
 603                         if (!pci_dma_mapping_error(lp->pci_dev,
 604                                                    lp->rx_dma_addr[new]))
 605                                 pci_unmap_single(lp->pci_dev,
 606                                                  lp->rx_dma_addr[new],
 607                                                  PKT_BUF_SIZE,
 608                                                  PCI_DMA_FROMDEVICE);
 609                         dev_kfree_skb(lp->rx_skbuff[new]);
 610                 }
 611         }
 612
 613         kfree(lp->rx_skbuff);
 614         kfree(lp->rx_dma_addr);
 615         pci_free_consistent(lp->pci_dev,
 616                             sizeof(struct pcnet32_rx_head) *
 617                             lp->rx_ring_size, lp->rx_ring,
 618                             lp->rx_ring_dma_addr);
 619
 620         lp->rx_ring_size = entries;
 621         lp->rx_mod_mask = lp->rx_ring_size - 1;
 622         lp->rx_len_bits = (size << 4);
 623         lp->rx_ring = new_rx_ring;
 624         lp->rx_ring_dma_addr = new_ring_dma_addr;
 625         lp->rx_dma_addr = new_dma_addr_list;
 626         lp->rx_skbuff = new_skb_list;
 627         return;
 628
 629 free_all_new:
 630         while (--new >= lp->rx_ring_size) {
 631                 if (new_skb_list[new]) {
 632                         if (!pci_dma_mapping_error(lp->pci_dev,
 633                                                    new_dma_addr_list[new]))
 634                                 pci_unmap_single(lp->pci_dev,
 635                                                  new_dma_addr_list[new],
 636                                                  PKT_BUF_SIZE,
 637                                                  PCI_DMA_FROMDEVICE);
 638                         dev_kfree_skb(new_skb_list[new]);
 639                 }
 640         }
 641         kfree(new_skb_list);
 642 free_new_lists:
 643         kfree(new_dma_addr_list);
 644 free_new_rx_ring:
 645         pci_free_consistent(lp->pci_dev,
 646                             sizeof(struct pcnet32_rx_head) * entries,
 647                             new_rx_ring,
 648                             new_ring_dma_addr);
 649 }
 650
 651 static void pcnet32_purge_rx_ring(struct net_device *dev)
 652 {
 653         struct pcnet32_private *lp = netdev_priv(dev);
 654         int i;
 655
 656         /* free all allocated skbuffs */
 657         for (i = 0; i < lp->rx_ring_size; i++) {
 658                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 659                 wmb();          /* Make sure adapter sees owner change */
 660                 if (lp->rx_skbuff[i]) {
 661                         if (!pci_dma_mapping_error(lp->pci_dev,
 662                                                    lp->rx_dma_addr[i]))
 663                                 pci_unmap_single(lp->pci_dev,
 664                                                  lp->rx_dma_addr[i],
 665                                                  PKT_BUF_SIZE,
 666                                                  PCI_DMA_FROMDEVICE);
 667                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 668                 }
 669                 lp->rx_skbuff[i] = NULL;
 670                 lp->rx_dma_addr[i] = 0;
 671         }
 672 }
 673
 674 #ifdef CONFIG_NET_POLL_CONTROLLER
 675 static void pcnet32_poll_controller(struct net_device *dev)
 676 {
 677         disable_irq(dev->irq);
 678         pcnet32_interrupt(0, dev);
 679         enable_irq(dev->irq);
 680 }
 681 #endif
 682
 683 /*
 684  * lp->lock must be held.
 685  */
 686 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
 687                            int can_sleep)
 688 {
 689         int csr5;
 690         struct pcnet32_private *lp = netdev_priv(dev);
 691         const struct pcnet32_access *a = lp->a;
 692         ulong ioaddr = dev->base_addr;
 693         int ticks;
 694
 695         /* really old chips have to be stopped. */
 696         if (lp->chip_version < PCNET32_79C970A)
 697                 return 0;
 698
 699         /* set SUSPEND (SPND) - CSR5 bit 0 */
 700         csr5 = a->read_csr(ioaddr, CSR5);
 701         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
 702
 703         /* poll waiting for bit to be set */
 704         ticks = 0;
 705         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
 706                 spin_unlock_irqrestore(&lp->lock, *flags);
 707                 if (can_sleep)
 708                         msleep(1);
 709                 else
 710                         mdelay(1);
 711                 spin_lock_irqsave(&lp->lock, *flags);
 712                 ticks++;
 713                 if (ticks > 200) {
 714                         netif_printk(lp, hw, KERN_DEBUG, dev,
 715                                      "Error getting into suspend!\n");
 716                         return 0;
 717                 }
 718         }
 719         return 1;
 720 }
 721
 722 static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr)
 723 {
 724         int csr5 = lp->a->read_csr(ioaddr, CSR5);
 725         /* clear SUSPEND (SPND) - CSR5 bit 0 */
 726         lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
 727 }
 728
 729 static int pcnet32_get_link_ksettings(struct net_device *dev,
 730                                       struct ethtool_link_ksettings *cmd)
 731 {
 732         struct pcnet32_private *lp = netdev_priv(dev);
 733         unsigned long flags;
 734
 735         spin_lock_irqsave(&lp->lock, flags);
 736         if (lp->mii) {
 737                 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
 738         } else if (lp->chip_version == PCNET32_79C970A) {
 739                 if (lp->autoneg) {
 740                         cmd->base.autoneg = AUTONEG_ENABLE;
 741                         if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0)
 742                                 cmd->base.port = PORT_AUI;
 743                         else
 744                                 cmd->base.port = PORT_TP;
 745                 } else {
 746                         cmd->base.autoneg = AUTONEG_DISABLE;
 747                         cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI;
 748                 }
 749                 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF;
 750                 cmd->base.speed = SPEED_10;
 751                 ethtool_convert_legacy_u32_to_link_mode(
 752                                                 cmd->link_modes.supported,
 753                                                 SUPPORTED_TP | SUPPORTED_AUI);
 754         }
 755         spin_unlock_irqrestore(&lp->lock, flags);
 756         return 0;
 757 }
 758
 759 static int pcnet32_set_link_ksettings(struct net_device *dev,
 760                                       const struct ethtool_link_ksettings *cmd)
 761 {
 762         struct pcnet32_private *lp = netdev_priv(dev);
 763         ulong ioaddr = dev->base_addr;
 764         unsigned long flags;
 765         int r = -EOPNOTSUPP;
 766         int suspended, bcr2, bcr9, csr15;
 767
 768         spin_lock_irqsave(&lp->lock, flags);
 769         if (lp->mii) {
 770                 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
 771         } else if (lp->chip_version == PCNET32_79C970A) {
 772                 suspended = pcnet32_suspend(dev, &flags, 0);
 773                 if (!suspended)
 774                         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
 775
 776                 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
 777                 bcr2 = lp->a->read_bcr(ioaddr, 2);
 778                 if (cmd->base.autoneg == AUTONEG_ENABLE) {
 779                         lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002);
 780                 } else {
 781                         lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002);
 782
 783                         lp->port_tp = cmd->base.port == PORT_TP;
 784                         csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;
 785                         if (cmd->base.port == PORT_TP)
 786                                 csr15 |= 0x0080;
 787                         lp->a->write_csr(ioaddr, CSR15, csr15);
 788                         lp->init_block->mode = cpu_to_le16(csr15);
 789
 790                         lp->fdx = cmd->base.duplex == DUPLEX_FULL;
 791                         bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003;
 792                         if (cmd->base.duplex == DUPLEX_FULL)
 793                                 bcr9 |= 0x0003;
 794                         lp->a->write_bcr(ioaddr, 9, bcr9);
 795                 }
 796                 if (suspended)
 797                         pcnet32_clr_suspend(lp, ioaddr);
 798                 else if (netif_running(dev))
 799                         pcnet32_restart(dev, CSR0_NORMAL);
 800                 r = 0;
 801         }
 802         spin_unlock_irqrestore(&lp->lock, flags);
 803         return r;
 804 }
 805
 806 static void pcnet32_get_drvinfo(struct net_device *dev,
 807                                 struct ethtool_drvinfo *info)
 808 {
 809         struct pcnet32_private *lp = netdev_priv(dev);
 810
 811         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 812         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 813         if (lp->pci_dev)
 814                 strlcpy(info->bus_info, pci_name(lp->pci_dev),
 815                         sizeof(info->bus_info));
 816         else
 817                 snprintf(info->bus_info, sizeof(info->bus_info),
 818                         "VLB 0x%lx", dev->base_addr);
 819 }
 820
 821 static u32 pcnet32_get_link(struct net_device *dev)
 822 {
 823         struct pcnet32_private *lp = netdev_priv(dev);
 824         unsigned long flags;
 825         int r;
 826
 827         spin_lock_irqsave(&lp->lock, flags);
 828         if (lp->mii) {
 829                 r = mii_link_ok(&lp->mii_if);
 830         } else if (lp->chip_version == PCNET32_79C970A) {
 831                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 832                 /* only read link if port is set to TP */
 833                 if (!lp->autoneg && lp->port_tp)
 834                         r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
 835                 else /* link always up for AUI port or port auto select */
 836                         r = 1;
 837         } else if (lp->chip_version > PCNET32_79C970A) {
 838                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 839                 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
 840         } else {        /* can not detect link on really old chips */
 841                 r = 1;
 842         }
 843         spin_unlock_irqrestore(&lp->lock, flags);
 844
 845         return r;
 846 }
 847
 848 static u32 pcnet32_get_msglevel(struct net_device *dev)
 849 {
 850         struct pcnet32_private *lp = netdev_priv(dev);
 851         return lp->msg_enable;
 852 }
 853
 854 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 855 {
 856         struct pcnet32_private *lp = netdev_priv(dev);
 857         lp->msg_enable = value;
 858 }
 859
 860 static int pcnet32_nway_reset(struct net_device *dev)
 861 {
 862         struct pcnet32_private *lp = netdev_priv(dev);
 863         unsigned long flags;
 864         int r = -EOPNOTSUPP;
 865
 866         if (lp->mii) {
 867                 spin_lock_irqsave(&lp->lock, flags);
 868                 r = mii_nway_restart(&lp->mii_if);
 869                 spin_unlock_irqrestore(&lp->lock, flags);
 870         }
 871         return r;
 872 }
 873
 874 static void pcnet32_get_ringparam(struct net_device *dev,
 875                                   struct ethtool_ringparam *ering)
 876 {
 877         struct pcnet32_private *lp = netdev_priv(dev);
 878
 879         ering->tx_max_pending = TX_MAX_RING_SIZE;
 880         ering->tx_pending = lp->tx_ring_size;
 881         ering->rx_max_pending = RX_MAX_RING_SIZE;
 882         ering->rx_pending = lp->rx_ring_size;
 883 }
 884
 885 static int pcnet32_set_ringparam(struct net_device *dev,
 886                                  struct ethtool_ringparam *ering)
 887 {
 888         struct pcnet32_private *lp = netdev_priv(dev);
 889         unsigned long flags;
 890         unsigned int size;
 891         ulong ioaddr = dev->base_addr;
 892         int i;
 893
 894         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 895                 return -EINVAL;
 896
 897         if (netif_running(dev))
 898                 pcnet32_netif_stop(dev);
 899
 900         spin_lock_irqsave(&lp->lock, flags);
 901         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 902
 903         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 904
 905         /* set the minimum ring size to 4, to allow the loopback test to work
 906          * unchanged.
 907          */
 908         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 909                 if (size <= (1 << i))
 910                         break;
 911         }
 912         if ((1 << i) != lp->tx_ring_size)
 913                 pcnet32_realloc_tx_ring(dev, lp, i);
 914
 915         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 916         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 917                 if (size <= (1 << i))
 918                         break;
 919         }
 920         if ((1 << i) != lp->rx_ring_size)
 921                 pcnet32_realloc_rx_ring(dev, lp, i);
 922
 923         lp->napi.weight = lp->rx_ring_size / 2;
 924
 925         if (netif_running(dev)) {
 926                 pcnet32_netif_start(dev);
 927                 pcnet32_restart(dev, CSR0_NORMAL);
 928         }
 929
 930         spin_unlock_irqrestore(&lp->lock, flags);
 931
 932         netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
 933                    lp->rx_ring_size, lp->tx_ring_size);
 934
 935         return 0;
 936 }
 937
 938 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 939                                 u8 *data)
 940 {
 941         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 942 }
 943
 944 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 945 {
 946         switch (sset) {
 947         case ETH_SS_TEST:
 948                 return PCNET32_TEST_LEN;
 949         default:
 950                 return -EOPNOTSUPP;
 951         }
 952 }
 953
 954 static void pcnet32_ethtool_test(struct net_device *dev,
 955                                  struct ethtool_test *test, u64 * data)
 956 {
 957         struct pcnet32_private *lp = netdev_priv(dev);
 958         int rc;
 959
 960         if (test->flags == ETH_TEST_FL_OFFLINE) {
 961                 rc = pcnet32_loopback_test(dev, data);
 962                 if (rc) {
 963                         netif_printk(lp, hw, KERN_DEBUG, dev,
 964                                      "Loopback test failed\n");
 965                         test->flags |= ETH_TEST_FL_FAILED;
 966                 } else
 967                         netif_printk(lp, hw, KERN_DEBUG, dev,
 968                                      "Loopback test passed\n");
 969         } else
 970                 netif_printk(lp, hw, KERN_DEBUG, dev,
 971                              "No tests to run (specify 'Offline' on ethtool)\n");
 972 }                               /* end pcnet32_ethtool_test */
 973
 974 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 975 {
 976         struct pcnet32_private *lp = netdev_priv(dev);
 977         const struct pcnet32_access *a = lp->a; /* access to registers */
 978         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 979         struct sk_buff *skb;    /* sk buff */
 980         int x, i;               /* counters */
 981         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 982         u16 status = 0x8300;    /* TX ring status */
 983         __le16 teststatus;      /* test of ring status */
 984         int rc;                 /* return code */
 985         int size;               /* size of packets */
 986         unsigned char *packet;  /* source packet data */
 987         static const int data_len = 60; /* length of source packets */
 988         unsigned long flags;
 989         unsigned long ticks;
 990
 991         rc = 1;                 /* default to fail */
 992
 993         if (netif_running(dev))
 994                 pcnet32_netif_stop(dev);
 995
 996         spin_lock_irqsave(&lp->lock, flags);
 997         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 998
 999         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
1000
1001         /* Reset the PCNET32 */
1002         lp->a->reset(ioaddr);
1003         lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1004
1005         /* switch pcnet32 to 32bit mode */
1006         lp->a->write_bcr(ioaddr, 20, 2);
1007
1008         /* purge & init rings but don't actually restart */
1009         pcnet32_restart(dev, 0x0000);
1010
1011         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
1012
1013         /* Initialize Transmit buffers. */
1014         size = data_len + 15;
1015         for (x = 0; x < numbuffs; x++) {
1016                 skb = netdev_alloc_skb(dev, size);
1017                 if (!skb) {
1018                         netif_printk(lp, hw, KERN_DEBUG, dev,
1019                                      "Cannot allocate skb at line: %d!\n",
1020                                      __LINE__);
1021                         goto clean_up;
1022                 }
1023                 packet = skb->data;
1024                 skb_put(skb, size);     /* create space for data */
1025                 lp->tx_skbuff[x] = skb;
1026                 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
1027                 lp->tx_ring[x].misc = 0;
1028
1029                 /* put DA and SA into the skb */
1030                 for (i = 0; i < 6; i++)
1031                         *packet++ = dev->dev_addr[i];
1032                 for (i = 0; i < 6; i++)
1033                         *packet++ = dev->dev_addr[i];
1034                 /* type */
1035                 *packet++ = 0x08;
1036                 *packet++ = 0x06;
1037                 /* packet number */
1038                 *packet++ = x;
1039                 /* fill packet with data */
1040                 for (i = 0; i < data_len; i++)
1041                         *packet++ = i;
1042
1043                 lp->tx_dma_addr[x] =
1044                         pci_map_single(lp->pci_dev, skb->data, skb->len,
1045                                        PCI_DMA_TODEVICE);
1046                 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[x])) {
1047                         netif_printk(lp, hw, KERN_DEBUG, dev,
1048                                      "DMA mapping error at line: %d!\n",
1049                                      __LINE__);
1050                         goto clean_up;
1051                 }
1052                 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
1053                 wmb();  /* Make sure owner changes after all others are visible */
1054                 lp->tx_ring[x].status = cpu_to_le16(status);
1055         }
1056
1057         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
1058         a->write_bcr(ioaddr, 32, x | 0x0002);
1059
1060         /* set int loopback in CSR15 */
1061         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1062         lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1063
1064         teststatus = cpu_to_le16(0x8000);
1065         lp->a->write_csr(ioaddr, CSR0, CSR0_START);     /* Set STRT bit */
1066
1067         /* Check status of descriptors */
1068         for (x = 0; x < numbuffs; x++) {
1069                 ticks = 0;
1070                 rmb();
1071                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
1072                         spin_unlock_irqrestore(&lp->lock, flags);
1073                         msleep(1);
1074                         spin_lock_irqsave(&lp->lock, flags);
1075                         rmb();
1076                         ticks++;
1077                 }
1078                 if (ticks == 200) {
1079                         netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
1080                         break;
1081                 }
1082         }
1083
1084         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
1085         wmb();
1086         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1087                 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
1088
1089                 for (x = 0; x < numbuffs; x++) {
1090                         netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
1091                         skb = lp->rx_skbuff[x];
1092                         for (i = 0; i < size; i++)
1093                                 pr_cont(" %02x", *(skb->data + i));
1094                         pr_cont("\n");
1095                 }
1096         }
1097
1098         x = 0;
1099         rc = 0;
1100         while (x < numbuffs && !rc) {
1101                 skb = lp->rx_skbuff[x];
1102                 packet = lp->tx_skbuff[x]->data;
1103                 for (i = 0; i < size; i++) {
1104                         if (*(skb->data + i) != packet[i]) {
1105                                 netif_printk(lp, hw, KERN_DEBUG, dev,
1106                                              "Error in compare! %2x - %02x %02x\n",
1107                                              i, *(skb->data + i), packet[i]);
1108                                 rc = 1;
1109                                 break;
1110                         }
1111                 }
1112                 x++;
1113         }
1114
1115 clean_up:
1116         *data1 = rc;
1117         pcnet32_purge_tx_ring(dev);
1118
1119         x = a->read_csr(ioaddr, CSR15);
1120         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1121
1122         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1123         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1124
1125         if (netif_running(dev)) {
1126                 pcnet32_netif_start(dev);
1127                 pcnet32_restart(dev, CSR0_NORMAL);
1128         } else {
1129                 pcnet32_purge_rx_ring(dev);
1130                 lp->a->write_bcr(ioaddr, 20, 4);        /* return to 16bit mode */
1131         }
1132         spin_unlock_irqrestore(&lp->lock, flags);
1133
1134         return rc;
1135 }                               /* end pcnet32_loopback_test  */
1136
1137 static int pcnet32_set_phys_id(struct net_device *dev,
1138                                enum ethtool_phys_id_state state)
1139 {
1140         struct pcnet32_private *lp = netdev_priv(dev);
1141         const struct pcnet32_access *a = lp->a;
1142         ulong ioaddr = dev->base_addr;
1143         unsigned long flags;
1144         int i;
1145
1146         switch (state) {
1147         case ETHTOOL_ID_ACTIVE:
1148                 /* Save the current value of the bcrs */
1149                 spin_lock_irqsave(&lp->lock, flags);
1150                 for (i = 4; i < 8; i++)
1151                         lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1152                 spin_unlock_irqrestore(&lp->lock, flags);
1153                 return 2;       /* cycle on/off twice per second */
1154
1155         case ETHTOOL_ID_ON:
1156         case ETHTOOL_ID_OFF:
1157                 /* Blink the led */
1158                 spin_lock_irqsave(&lp->lock, flags);
1159                 for (i = 4; i < 8; i++)
1160                         a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1161                 spin_unlock_irqrestore(&lp->lock, flags);
1162                 break;
1163
1164         case ETHTOOL_ID_INACTIVE:
1165                 /* Restore the original value of the bcrs */
1166                 spin_lock_irqsave(&lp->lock, flags);
1167                 for (i = 4; i < 8; i++)
1168                         a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1169                 spin_unlock_irqrestore(&lp->lock, flags);
1170         }
1171         return 0;
1172 }
1173
1174 /*
1175  * process one receive descriptor entry
1176  */
1177
1178 static void pcnet32_rx_entry(struct net_device *dev,
1179                              struct pcnet32_private *lp,
1180                              struct pcnet32_rx_head *rxp,
1181                              int entry)
1182 {
1183         int status = (short)le16_to_cpu(rxp->status) >> 8;
1184         int rx_in_place = 0;
1185         struct sk_buff *skb;
1186         short pkt_len;
1187
1188         if (status != 0x03) {   /* There was an error. */
1189                 /*
1190                  * There is a tricky error noted by John Murphy,
1191                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1192                  * buffers it's possible for a jabber packet to use two
1193                  * buffers, with only the last correctly noting the error.
1194                  */
1195                 if (status & 0x01)      /* Only count a general error at the */
1196                         dev->stats.rx_errors++; /* end of a packet. */
1197                 if (status & 0x20)
1198                         dev->stats.rx_frame_errors++;
1199                 if (status & 0x10)
1200                         dev->stats.rx_over_errors++;
1201                 if (status & 0x08)
1202                         dev->stats.rx_crc_errors++;
1203                 if (status & 0x04)
1204                         dev->stats.rx_fifo_errors++;
1205                 return;
1206         }
1207
1208         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1209
1210         /* Discard oversize frames. */
1211         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1212                 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1213                           pkt_len);
1214                 dev->stats.rx_errors++;
1215                 return;
1216         }
1217         if (pkt_len < 60) {
1218                 netif_err(lp, rx_err, dev, "Runt packet!\n");
1219                 dev->stats.rx_errors++;
1220                 return;
1221         }
1222
1223         if (pkt_len > rx_copybreak) {
1224                 struct sk_buff *newskb;
1225                 dma_addr_t new_dma_addr;
1226
1227                 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1228                 /*
1229                  * map the new buffer, if mapping fails, drop the packet and
1230                  * reuse the old buffer
1231                  */
1232                 if (newskb) {
1233                         skb_reserve(newskb, NET_IP_ALIGN);
1234                         new_dma_addr = pci_map_single(lp->pci_dev,
1235                                                       newskb->data,
1236                                                       PKT_BUF_SIZE,
1237                                                       PCI_DMA_FROMDEVICE);
1238                         if (pci_dma_mapping_error(lp->pci_dev, new_dma_addr)) {
1239                                 netif_err(lp, rx_err, dev,
1240                                           "DMA mapping error.\n");
1241                                 dev_kfree_skb(newskb);
1242                                 skb = NULL;
1243                         } else {
1244                                 skb = lp->rx_skbuff[entry];
1245                                 pci_unmap_single(lp->pci_dev,
1246                                                  lp->rx_dma_addr[entry],
1247                                                  PKT_BUF_SIZE,
1248                                                  PCI_DMA_FROMDEVICE);
1249                                 skb_put(skb, pkt_len);
1250                                 lp->rx_skbuff[entry] = newskb;
1251                                 lp->rx_dma_addr[entry] = new_dma_addr;
1252                                 rxp->base = cpu_to_le32(new_dma_addr);
1253                                 rx_in_place = 1;
1254                         }
1255                 } else
1256                         skb = NULL;
1257         } else
1258                 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1259
1260         if (skb == NULL) {
1261                 dev->stats.rx_dropped++;
1262                 return;
1263         }
1264         if (!rx_in_place) {
1265                 skb_reserve(skb, NET_IP_ALIGN);
1266                 skb_put(skb, pkt_len);  /* Make room */
1267                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1268                                             lp->rx_dma_addr[entry],
1269                                             pkt_len,
1270                                             PCI_DMA_FROMDEVICE);
1271                 skb_copy_to_linear_data(skb,
1272                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1273                                  pkt_len);
1274                 pci_dma_sync_single_for_device(lp->pci_dev,
1275                                                lp->rx_dma_addr[entry],
1276                                                pkt_len,
1277                                                PCI_DMA_FROMDEVICE);
1278         }
1279         dev->stats.rx_bytes += skb->len;
1280         skb->protocol = eth_type_trans(skb, dev);
1281         netif_receive_skb(skb);
1282         dev->stats.rx_packets++;
1283 }
1284
1285 static int pcnet32_rx(struct net_device *dev, int budget)
1286 {
1287         struct pcnet32_private *lp = netdev_priv(dev);
1288         int entry = lp->cur_rx & lp->rx_mod_mask;
1289         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1290         int npackets = 0;
1291
1292         /* If we own the next entry, it's a new packet. Send it up. */
1293         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1294                 pcnet32_rx_entry(dev, lp, rxp, entry);
1295                 npackets += 1;
1296                 /*
1297                  * The docs say that the buffer length isn't touched, but Andrew
1298                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1299                  */
1300                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1301                 wmb();  /* Make sure owner changes after others are visible */
1302                 rxp->status = cpu_to_le16(0x8000);
1303                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1304                 rxp = &lp->rx_ring[entry];
1305         }
1306
1307         return npackets;
1308 }
1309
1310 static int pcnet32_tx(struct net_device *dev)
1311 {
1312         struct pcnet32_private *lp = netdev_priv(dev);
1313         unsigned int dirty_tx = lp->dirty_tx;
1314         int delta;
1315         int must_restart = 0;
1316
1317         while (dirty_tx != lp->cur_tx) {
1318                 int entry = dirty_tx & lp->tx_mod_mask;
1319                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1320
1321                 if (status < 0)
1322                         break;  /* It still hasn't been Txed */
1323
1324                 lp->tx_ring[entry].base = 0;
1325
1326                 if (status & 0x4000) {
1327                         /* There was a major error, log it. */
1328                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1329                         dev->stats.tx_errors++;
1330                         netif_err(lp, tx_err, dev,
1331                                   "Tx error status=%04x err_status=%08x\n",
1332                                   status, err_status);
1333                         if (err_status & 0x04000000)
1334                                 dev->stats.tx_aborted_errors++;
1335                         if (err_status & 0x08000000)
1336                                 dev->stats.tx_carrier_errors++;
1337                         if (err_status & 0x10000000)
1338                                 dev->stats.tx_window_errors++;
1339 #ifndef DO_DXSUFLO
1340                         if (err_status & 0x40000000) {
1341                                 dev->stats.tx_fifo_errors++;
1342                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1343                                 /* Remove this verbosity later! */
1344                                 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1345                                 must_restart = 1;
1346                         }
1347 #else
1348                         if (err_status & 0x40000000) {
1349                                 dev->stats.tx_fifo_errors++;
1350                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1351                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1352                                         /* Remove this verbosity later! */
1353                                         netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1354                                         must_restart = 1;
1355                                 }
1356                         }
1357 #endif
1358                 } else {
1359                         if (status & 0x1800)
1360                                 dev->stats.collisions++;
1361                         dev->stats.tx_packets++;
1362                 }
1363
1364                 /* We must free the original skb */
1365                 if (lp->tx_skbuff[entry]) {
1366                         pci_unmap_single(lp->pci_dev,
1367                                          lp->tx_dma_addr[entry],
1368                                          lp->tx_skbuff[entry]->
1369                                          len, PCI_DMA_TODEVICE);
1370                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1371                         lp->tx_skbuff[entry] = NULL;
1372                         lp->tx_dma_addr[entry] = 0;
1373                 }
1374                 dirty_tx++;
1375         }
1376
1377         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1378         if (delta > lp->tx_ring_size) {
1379                 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1380                           dirty_tx, lp->cur_tx, lp->tx_full);
1381                 dirty_tx += lp->tx_ring_size;
1382                 delta -= lp->tx_ring_size;
1383         }
1384
1385         if (lp->tx_full &&
1386             netif_queue_stopped(dev) &&
1387             delta < lp->tx_ring_size - 2) {
1388                 /* The ring is no longer full, clear tbusy. */
1389                 lp->tx_full = 0;
1390                 netif_wake_queue(dev);
1391         }
1392         lp->dirty_tx = dirty_tx;
1393
1394         return must_restart;
1395 }
1396
1397 static int pcnet32_poll(struct napi_struct *napi, int budget)
1398 {
1399         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1400         struct net_device *dev = lp->dev;
1401         unsigned long ioaddr = dev->base_addr;
1402         unsigned long flags;
1403         int work_done;
1404         u16 val;
1405
1406         work_done = pcnet32_rx(dev, budget);
1407
1408         spin_lock_irqsave(&lp->lock, flags);
1409         if (pcnet32_tx(dev)) {
1410                 /* reset the chip to clear the error condition, then restart */
1411                 lp->a->reset(ioaddr);
1412                 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1413                 pcnet32_restart(dev, CSR0_START);
1414                 netif_wake_queue(dev);
1415         }
1416
1417         if (work_done < budget && napi_complete_done(napi, work_done)) {
1418                 /* clear interrupt masks */
1419                 val = lp->a->read_csr(ioaddr, CSR3);
1420                 val &= 0x00ff;
1421                 lp->a->write_csr(ioaddr, CSR3, val);
1422
1423                 /* Set interrupt enable. */
1424                 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1425         }
1426
1427         spin_unlock_irqrestore(&lp->lock, flags);
1428         return work_done;
1429 }
1430
1431 #define PCNET32_REGS_PER_PHY    32
1432 #define PCNET32_MAX_PHYS        32
1433 static int pcnet32_get_regs_len(struct net_device *dev)
1434 {
1435         struct pcnet32_private *lp = netdev_priv(dev);
1436         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1437
1438         return (PCNET32_NUM_REGS + j) * sizeof(u16);
1439 }
1440
1441 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1442                              void *ptr)
1443 {
1444         int i, csr0;
1445         u16 *buff = ptr;
1446         struct pcnet32_private *lp = netdev_priv(dev);
1447         const struct pcnet32_access *a = lp->a;
1448         ulong ioaddr = dev->base_addr;
1449         unsigned long flags;
1450
1451         spin_lock_irqsave(&lp->lock, flags);
1452
1453         csr0 = a->read_csr(ioaddr, CSR0);
1454         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1455                 pcnet32_suspend(dev, &flags, 1);
1456
1457         /* read address PROM */
1458         for (i = 0; i < 16; i += 2)
1459                 *buff++ = inw(ioaddr + i);
1460
1461         /* read control and status registers */
1462         for (i = 0; i < 90; i++)
1463                 *buff++ = a->read_csr(ioaddr, i);
1464
1465         *buff++ = a->read_csr(ioaddr, 112);
1466         *buff++ = a->read_csr(ioaddr, 114);
1467
1468         /* read bus configuration registers */
1469         for (i = 0; i < 30; i++)
1470                 *buff++ = a->read_bcr(ioaddr, i);
1471
1472         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1473
1474         for (i = 31; i < 36; i++)
1475                 *buff++ = a->read_bcr(ioaddr, i);
1476
1477         /* read mii phy registers */
1478         if (lp->mii) {
1479                 int j;
1480                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1481                         if (lp->phymask & (1 << j)) {
1482                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1483                                         lp->a->write_bcr(ioaddr, 33,
1484                                                         (j << 5) | i);
1485                                         *buff++ = lp->a->read_bcr(ioaddr, 34);
1486                                 }
1487                         }
1488                 }
1489         }
1490
1491         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1492                 pcnet32_clr_suspend(lp, ioaddr);
1493
1494         spin_unlock_irqrestore(&lp->lock, flags);
1495 }
1496
1497 static const struct ethtool_ops pcnet32_ethtool_ops = {
1498         .get_drvinfo            = pcnet32_get_drvinfo,
1499         .get_msglevel           = pcnet32_get_msglevel,
1500         .set_msglevel           = pcnet32_set_msglevel,
1501         .nway_reset             = pcnet32_nway_reset,
1502         .get_link               = pcnet32_get_link,
1503         .get_ringparam          = pcnet32_get_ringparam,
1504         .set_ringparam          = pcnet32_set_ringparam,
1505         .get_strings            = pcnet32_get_strings,
1506         .self_test              = pcnet32_ethtool_test,
1507         .set_phys_id            = pcnet32_set_phys_id,
1508         .get_regs_len           = pcnet32_get_regs_len,
1509         .get_regs               = pcnet32_get_regs,
1510         .get_sset_count         = pcnet32_get_sset_count,
1511         .get_link_ksettings     = pcnet32_get_link_ksettings,
1512         .set_link_ksettings     = pcnet32_set_link_ksettings,
1513 };
1514
1515 /* only probes for non-PCI devices, the rest are handled by
1516  * pci_register_driver via pcnet32_probe_pci */
1517
1518 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1519 {
1520         unsigned int *port, ioaddr;
1521
1522         /* search for PCnet32 VLB cards at known addresses */
1523         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1524                 if (request_region
1525                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1526                         /* check if there is really a pcnet chip on that ioaddr */
1527                         if ((inb(ioaddr + 14) == 0x57) &&
1528                             (inb(ioaddr + 15) == 0x57)) {
1529                                 pcnet32_probe1(ioaddr, 0, NULL);
1530                         } else {
1531                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1532                         }
1533                 }
1534         }
1535 }
1536
1537 static int
1538 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1539 {
1540         unsigned long ioaddr;
1541         int err;
1542
1543         err = pci_enable_device(pdev);
1544         if (err < 0) {
1545                 if (pcnet32_debug & NETIF_MSG_PROBE)
1546                         pr_err("failed to enable device -- err=%d\n", err);
1547                 return err;
1548         }
1549         pci_set_master(pdev);
1550
1551         if (!pci_resource_len(pdev, 0)) {
1552                 if (pcnet32_debug & NETIF_MSG_PROBE)
1553                         pr_err("card has no PCI IO resources, aborting\n");
1554                 return -ENODEV;
1555         }
1556
1557         err = pci_set_dma_mask(pdev, PCNET32_DMA_MASK);
1558         if (err) {
1559                 if (pcnet32_debug & NETIF_MSG_PROBE)
1560                         pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1561                 return err;
1562         }
1563
1564         ioaddr = pci_resource_start(pdev, 0);
1565         if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1566                 if (pcnet32_debug & NETIF_MSG_PROBE)
1567                         pr_err("io address range already allocated\n");
1568                 return -EBUSY;
1569         }
1570
1571         err = pcnet32_probe1(ioaddr, 1, pdev);
1572         if (err < 0)
1573                 pci_disable_device(pdev);
1574
1575         return err;
1576 }
1577
1578 static const struct net_device_ops pcnet32_netdev_ops = {
1579         .ndo_open               = pcnet32_open,
1580         .ndo_stop               = pcnet32_close,
1581         .ndo_start_xmit         = pcnet32_start_xmit,
1582         .ndo_tx_timeout         = pcnet32_tx_timeout,
1583         .ndo_get_stats          = pcnet32_get_stats,
1584         .ndo_set_rx_mode        = pcnet32_set_multicast_list,
1585         .ndo_do_ioctl           = pcnet32_ioctl,
1586         .ndo_set_mac_address    = eth_mac_addr,
1587         .ndo_validate_addr      = eth_validate_addr,
1588 #ifdef CONFIG_NET_POLL_CONTROLLER
1589         .ndo_poll_controller    = pcnet32_poll_controller,
1590 #endif
1591 };
1592
1593 /* pcnet32_probe1
1594  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1595  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1596  */
1597 static int
1598 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1599 {
1600         struct pcnet32_private *lp;
1601         int i, media;
1602         int fdx, mii, fset, dxsuflo, sram;
1603         int chip_version;
1604         char *chipname;
1605         struct net_device *dev;
1606         const struct pcnet32_access *a = NULL;
1607         u8 promaddr[ETH_ALEN];
1608         int ret = -ENODEV;
1609
1610         /* reset the chip */
1611         pcnet32_wio_reset(ioaddr);
1612
1613         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1614         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1615                 a = &pcnet32_wio;
1616         } else {
1617                 pcnet32_dwio_reset(ioaddr);
1618                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1619                     pcnet32_dwio_check(ioaddr)) {
1620                         a = &pcnet32_dwio;
1621                 } else {
1622                         if (pcnet32_debug & NETIF_MSG_PROBE)
1623                                 pr_err("No access methods\n");
1624                         goto err_release_region;
1625                 }
1626         }
1627
1628         chip_version =
1629             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1630         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1631                 pr_info("  PCnet chip version is %#x\n", chip_version);
1632         if ((chip_version & 0xfff) != 0x003) {
1633                 if (pcnet32_debug & NETIF_MSG_PROBE)
1634                         pr_info("Unsupported chip version\n");
1635                 goto err_release_region;
1636         }
1637
1638         /* initialize variables */
1639         fdx = mii = fset = dxsuflo = sram = 0;
1640         chip_version = (chip_version >> 12) & 0xffff;
1641
1642         switch (chip_version) {
1643         case 0x2420:
1644                 chipname = "PCnet/PCI 79C970";  /* PCI */
1645                 break;
1646         case 0x2430:
1647                 if (shared)
1648                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1649                 else
1650                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1651                 break;
1652         case 0x2621:
1653                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1654                 fdx = 1;
1655                 break;
1656         case 0x2623:
1657                 chipname = "PCnet/FAST 79C971"; /* PCI */
1658                 fdx = 1;
1659                 mii = 1;
1660                 fset = 1;
1661                 break;
1662         case 0x2624:
1663                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1664                 fdx = 1;
1665                 mii = 1;
1666                 fset = 1;
1667                 break;
1668         case 0x2625:
1669                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1670                 fdx = 1;
1671                 mii = 1;
1672                 sram = 1;
1673                 break;
1674         case 0x2626:
1675                 chipname = "PCnet/Home 79C978"; /* PCI */
1676                 fdx = 1;
1677                 /*
1678                  * This is based on specs published at www.amd.com.  This section
1679                  * assumes that a card with a 79C978 wants to go into standard
1680                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1681                  * and the module option homepna=1 can select this instead.
1682                  */
1683                 media = a->read_bcr(ioaddr, 49);
1684                 media &= ~3;    /* default to 10Mb ethernet */
1685                 if (cards_found < MAX_UNITS && homepna[cards_found])
1686                         media |= 1;     /* switch to home wiring mode */
1687                 if (pcnet32_debug & NETIF_MSG_PROBE)
1688                         printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1689                                (media & 1) ? "1" : "10");
1690                 a->write_bcr(ioaddr, 49, media);
1691                 break;
1692         case 0x2627:
1693                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1694                 fdx = 1;
1695                 mii = 1;
1696                 sram = 1;
1697                 break;
1698         case 0x2628:
1699                 chipname = "PCnet/PRO 79C976";
1700                 fdx = 1;
1701                 mii = 1;
1702                 break;
1703         default:
1704                 if (pcnet32_debug & NETIF_MSG_PROBE)
1705                         pr_info("PCnet version %#x, no PCnet32 chip\n",
1706                                 chip_version);
1707                 goto err_release_region;
1708         }
1709
1710         /*
1711          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1712          *  starting until the packet is loaded. Strike one for reliability, lose
1713          *  one for latency - although on PCI this isn't a big loss. Older chips
1714          *  have FIFO's smaller than a packet, so you can't do this.
1715          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1716          */
1717
1718         if (fset) {
1719                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1720                 a->write_csr(ioaddr, 80,
1721                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1722                 dxsuflo = 1;
1723         }
1724
1725         /*
1726          * The Am79C973/Am79C975 controllers come with 12K of SRAM
1727          * which we can use for the Tx/Rx buffers but most importantly,
1728          * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1729          * Tx fifo underflows.
1730          */
1731         if (sram) {
1732                 /*
1733                  * The SRAM is being configured in two steps. First we
1734                  * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1735                  * to the datasheet, each bit corresponds to a 512-byte
1736                  * page so we can have at most 24 pages. The SRAM_SIZE
1737                  * holds the value of the upper 8 bits of the 16-bit SRAM size.
1738                  * The low 8-bits start at 0x00 and end at 0xff. So the
1739                  * address range is from 0x0000 up to 0x17ff. Therefore,
1740                  * the SRAM_SIZE is set to 0x17. The next step is to set
1741                  * the BCR26:SRAM_BND midway through so the Tx and Rx
1742                  * buffers can share the SRAM equally.
1743                  */
1744                 a->write_bcr(ioaddr, 25, 0x17);
1745                 a->write_bcr(ioaddr, 26, 0xc);
1746                 /* And finally enable the NOUFLO bit */
1747                 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1748         }
1749
1750         dev = alloc_etherdev(sizeof(*lp));
1751         if (!dev) {
1752                 ret = -ENOMEM;
1753                 goto err_release_region;
1754         }
1755
1756         if (pdev)
1757                 SET_NETDEV_DEV(dev, &pdev->dev);
1758
1759         if (pcnet32_debug & NETIF_MSG_PROBE)
1760                 pr_info("%s at %#3lx,", chipname, ioaddr);
1761
1762         /* In most chips, after a chip reset, the ethernet address is read from the
1763          * station address PROM at the base address and programmed into the
1764          * "Physical Address Registers" CSR12-14.
1765          * As a precautionary measure, we read the PROM values and complain if
1766          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1767          * is valid, then the PROM addr is used.
1768          */
1769         for (i = 0; i < 3; i++) {
1770                 unsigned int val;
1771                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1772                 /* There may be endianness issues here. */
1773                 dev->dev_addr[2 * i] = val & 0x0ff;
1774                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1775         }
1776
1777         /* read PROM address and compare with CSR address */
1778         for (i = 0; i < ETH_ALEN; i++)
1779                 promaddr[i] = inb(ioaddr + i);
1780
1781         if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1782             !is_valid_ether_addr(dev->dev_addr)) {
1783                 if (is_valid_ether_addr(promaddr)) {
1784                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1785                                 pr_cont(" warning: CSR address invalid,\n");
1786                                 pr_info("    using instead PROM address of");
1787                         }
1788                         memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1789                 }
1790         }
1791
1792         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1793         if (!is_valid_ether_addr(dev->dev_addr))
1794                 eth_zero_addr(dev->dev_addr);
1795
1796         if (pcnet32_debug & NETIF_MSG_PROBE) {
1797                 pr_cont(" %pM", dev->dev_addr);
1798
1799                 /* Version 0x2623 and 0x2624 */
1800                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1801                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1802                         pr_info("    tx_start_pt(0x%04x):", i);
1803                         switch (i >> 10) {
1804                         case 0:
1805                                 pr_cont("  20 bytes,");
1806                                 break;
1807                         case 1:
1808                                 pr_cont("  64 bytes,");
1809                                 break;
1810                         case 2:
1811                                 pr_cont(" 128 bytes,");
1812                                 break;
1813                         case 3:
1814                                 pr_cont("~220 bytes,");
1815                                 break;
1816                         }
1817                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1818                         pr_cont(" BCR18(%x):", i & 0xffff);
1819                         if (i & (1 << 5))
1820                                 pr_cont("BurstWrEn ");
1821                         if (i & (1 << 6))
1822                                 pr_cont("BurstRdEn ");
1823                         if (i & (1 << 7))
1824                                 pr_cont("DWordIO ");
1825                         if (i & (1 << 11))
1826                                 pr_cont("NoUFlow ");
1827                         i = a->read_bcr(ioaddr, 25);
1828                         pr_info("    SRAMSIZE=0x%04x,", i << 8);
1829                         i = a->read_bcr(ioaddr, 26);
1830                         pr_cont(" SRAM_BND=0x%04x,", i << 8);
1831                         i = a->read_bcr(ioaddr, 27);
1832                         if (i & (1 << 14))
1833                                 pr_cont("LowLatRx");
1834                 }
1835         }
1836
1837         dev->base_addr = ioaddr;
1838         lp = netdev_priv(dev);
1839         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1840         lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1841                                               &lp->init_dma_addr);
1842         if (!lp->init_block) {
1843                 if (pcnet32_debug & NETIF_MSG_PROBE)
1844                         pr_err("Consistent memory allocation failed\n");
1845                 ret = -ENOMEM;
1846                 goto err_free_netdev;
1847         }
1848         lp->pci_dev = pdev;
1849
1850         lp->dev = dev;
1851
1852         spin_lock_init(&lp->lock);
1853
1854         lp->name = chipname;
1855         lp->shared_irq = shared;
1856         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1857         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1858         lp->tx_mod_mask = lp->tx_ring_size - 1;
1859         lp->rx_mod_mask = lp->rx_ring_size - 1;
1860         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1861         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1862         lp->mii_if.full_duplex = fdx;
1863         lp->mii_if.phy_id_mask = 0x1f;
1864         lp->mii_if.reg_num_mask = 0x1f;
1865         lp->dxsuflo = dxsuflo;
1866         lp->mii = mii;
1867         lp->chip_version = chip_version;
1868         lp->msg_enable = pcnet32_debug;
1869         if ((cards_found >= MAX_UNITS) ||
1870             (options[cards_found] >= sizeof(options_mapping)))
1871                 lp->options = PCNET32_PORT_ASEL;
1872         else
1873                 lp->options = options_mapping[options[cards_found]];
1874         /* force default port to TP on 79C970A so link detection can work */
1875         if (lp->chip_version == PCNET32_79C970A)
1876                 lp->options = PCNET32_PORT_10BT;
1877         lp->mii_if.dev = dev;
1878         lp->mii_if.mdio_read = mdio_read;
1879         lp->mii_if.mdio_write = mdio_write;
1880
1881         /* napi.weight is used in both the napi and non-napi cases */
1882         lp->napi.weight = lp->rx_ring_size / 2;
1883
1884         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1885
1886         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1887             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1888                 lp->options |= PCNET32_PORT_FD;
1889
1890         lp->a = a;
1891
1892         /* prior to register_netdev, dev->name is not yet correct */
1893         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1894                 ret = -ENOMEM;
1895                 goto err_free_ring;
1896         }
1897         /* detect special T1/E1 WAN card by checking for MAC address */
1898         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1899             dev->dev_addr[2] == 0x75)
1900                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1901
1902         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1903         lp->init_block->tlen_rlen =
1904             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1905         for (i = 0; i < 6; i++)
1906                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1907         lp->init_block->filter[0] = 0x00000000;
1908         lp->init_block->filter[1] = 0x00000000;
1909         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1910         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1911
1912         /* switch pcnet32 to 32bit mode */
1913         a->write_bcr(ioaddr, 20, 2);
1914
1915         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1916         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1917
1918         if (pdev) {             /* use the IRQ provided by PCI */
1919                 dev->irq = pdev->irq;
1920                 if (pcnet32_debug & NETIF_MSG_PROBE)
1921                         pr_cont(" assigned IRQ %d\n", dev->irq);
1922         } else {
1923                 unsigned long irq_mask = probe_irq_on();
1924
1925                 /*
1926                  * To auto-IRQ we enable the initialization-done and DMA error
1927                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1928                  * boards will work.
1929                  */
1930                 /* Trigger an initialization just for the interrupt. */
1931                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1932                 mdelay(1);
1933
1934                 dev->irq = probe_irq_off(irq_mask);
1935                 if (!dev->irq) {
1936                         if (pcnet32_debug & NETIF_MSG_PROBE)
1937                                 pr_cont(", failed to detect IRQ line\n");
1938                         ret = -ENODEV;
1939                         goto err_free_ring;
1940                 }
1941                 if (pcnet32_debug & NETIF_MSG_PROBE)
1942                         pr_cont(", probed IRQ %d\n", dev->irq);
1943         }
1944
1945         /* Set the mii phy_id so that we can query the link state */
1946         if (lp->mii) {
1947                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1948
1949                 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1950                 /* scan for PHYs */
1951                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1952                         unsigned short id1, id2;
1953
1954                         id1 = mdio_read(dev, i, MII_PHYSID1);
1955                         if (id1 == 0xffff)
1956                                 continue;
1957                         id2 = mdio_read(dev, i, MII_PHYSID2);
1958                         if (id2 == 0xffff)
1959                                 continue;
1960                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1961                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1962                         lp->phycount++;
1963                         lp->phymask |= (1 << i);
1964                         lp->mii_if.phy_id = i;
1965                         if (pcnet32_debug & NETIF_MSG_PROBE)
1966                                 pr_info("Found PHY %04x:%04x at address %d\n",
1967                                         id1, id2, i);
1968                 }
1969                 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1970                 if (lp->phycount > 1)
1971                         lp->options |= PCNET32_PORT_MII;
1972         }
1973
1974         init_timer(&lp->watchdog_timer);
1975         lp->watchdog_timer.data = (unsigned long)dev;
1976         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1977
1978         /* The PCNET32-specific entries in the device structure. */
1979         dev->netdev_ops = &pcnet32_netdev_ops;
1980         dev->ethtool_ops = &pcnet32_ethtool_ops;
1981         dev->watchdog_timeo = (5 * HZ);
1982
1983         /* Fill in the generic fields of the device structure. */
1984         if (register_netdev(dev))
1985                 goto err_free_ring;
1986
1987         if (pdev) {
1988                 pci_set_drvdata(pdev, dev);
1989         } else {
1990                 lp->next = pcnet32_dev;
1991                 pcnet32_dev = dev;
1992         }
1993
1994         if (pcnet32_debug & NETIF_MSG_PROBE)
1995                 pr_info("%s: registered as %s\n", dev->name, lp->name);
1996         cards_found++;
1997
1998         /* enable LED writes */
1999         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
2000
2001         return 0;
2002
2003 err_free_ring:
2004         pcnet32_free_ring(dev);
2005         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2006                             lp->init_block, lp->init_dma_addr);
2007 err_free_netdev:
2008         free_netdev(dev);
2009 err_release_region:
2010         release_region(ioaddr, PCNET32_TOTAL_SIZE);
2011         return ret;
2012 }
2013
2014 /* if any allocation fails, caller must also call pcnet32_free_ring */
2015 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
2016 {
2017         struct pcnet32_private *lp = netdev_priv(dev);
2018
2019         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2020                                            sizeof(struct pcnet32_tx_head) *
2021                                            lp->tx_ring_size,
2022                                            &lp->tx_ring_dma_addr);
2023         if (lp->tx_ring == NULL) {
2024                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
2025                 return -ENOMEM;
2026         }
2027
2028         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2029                                            sizeof(struct pcnet32_rx_head) *
2030                                            lp->rx_ring_size,
2031                                            &lp->rx_ring_dma_addr);
2032         if (lp->rx_ring == NULL) {
2033                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
2034                 return -ENOMEM;
2035         }
2036
2037         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2038                                   GFP_ATOMIC);
2039         if (!lp->tx_dma_addr)
2040                 return -ENOMEM;
2041
2042         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2043                                   GFP_ATOMIC);
2044         if (!lp->rx_dma_addr)
2045                 return -ENOMEM;
2046
2047         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2048                                 GFP_ATOMIC);
2049         if (!lp->tx_skbuff)
2050                 return -ENOMEM;
2051
2052         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2053                                 GFP_ATOMIC);
2054         if (!lp->rx_skbuff)
2055                 return -ENOMEM;
2056
2057         return 0;
2058 }
2059
2060 static void pcnet32_free_ring(struct net_device *dev)
2061 {
2062         struct pcnet32_private *lp = netdev_priv(dev);
2063
2064         kfree(lp->tx_skbuff);
2065         lp->tx_skbuff = NULL;
2066
2067         kfree(lp->rx_skbuff);
2068         lp->rx_skbuff = NULL;
2069
2070         kfree(lp->tx_dma_addr);
2071         lp->tx_dma_addr = NULL;
2072
2073         kfree(lp->rx_dma_addr);
2074         lp->rx_dma_addr = NULL;
2075
2076         if (lp->tx_ring) {
2077                 pci_free_consistent(lp->pci_dev,
2078                                     sizeof(struct pcnet32_tx_head) *
2079                                     lp->tx_ring_size, lp->tx_ring,
2080                                     lp->tx_ring_dma_addr);
2081                 lp->tx_ring = NULL;
2082         }
2083
2084         if (lp->rx_ring) {
2085                 pci_free_consistent(lp->pci_dev,
2086                                     sizeof(struct pcnet32_rx_head) *
2087                                     lp->rx_ring_size, lp->rx_ring,
2088                                     lp->rx_ring_dma_addr);
2089                 lp->rx_ring = NULL;
2090         }
2091 }
2092
2093 static int pcnet32_open(struct net_device *dev)
2094 {
2095         struct pcnet32_private *lp = netdev_priv(dev);
2096         struct pci_dev *pdev = lp->pci_dev;
2097         unsigned long ioaddr = dev->base_addr;
2098         u16 val;
2099         int i;
2100         int rc;
2101         unsigned long flags;
2102
2103         if (request_irq(dev->irq, pcnet32_interrupt,
2104                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2105                         (void *)dev)) {
2106                 return -EAGAIN;
2107         }
2108
2109         spin_lock_irqsave(&lp->lock, flags);
2110         /* Check for a valid station address */
2111         if (!is_valid_ether_addr(dev->dev_addr)) {
2112                 rc = -EINVAL;
2113                 goto err_free_irq;
2114         }
2115
2116         /* Reset the PCNET32 */
2117         lp->a->reset(ioaddr);
2118
2119         /* switch pcnet32 to 32bit mode */
2120         lp->a->write_bcr(ioaddr, 20, 2);
2121
2122         netif_printk(lp, ifup, KERN_DEBUG, dev,
2123                      "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2124                      __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2125                      (u32) (lp->rx_ring_dma_addr),
2126                      (u32) (lp->init_dma_addr));
2127
2128         lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL);
2129         lp->port_tp = !!(lp->options & PCNET32_PORT_10BT);
2130         lp->fdx = !!(lp->options & PCNET32_PORT_FD);
2131
2132         /* set/reset autoselect bit */
2133         val = lp->a->read_bcr(ioaddr, 2) & ~2;
2134         if (lp->options & PCNET32_PORT_ASEL)
2135                 val |= 2;
2136         lp->a->write_bcr(ioaddr, 2, val);
2137
2138         /* handle full duplex setting */
2139         if (lp->mii_if.full_duplex) {
2140                 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2141                 if (lp->options & PCNET32_PORT_FD) {
2142                         val |= 1;
2143                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2144                                 val |= 2;
2145                 } else if (lp->options & PCNET32_PORT_ASEL) {
2146                         /* workaround of xSeries250, turn on for 79C975 only */
2147                         if (lp->chip_version == 0x2627)
2148                                 val |= 3;
2149                 }
2150                 lp->a->write_bcr(ioaddr, 9, val);
2151         }
2152
2153         /* set/reset GPSI bit in test register */
2154         val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2155         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2156                 val |= 0x10;
2157         lp->a->write_csr(ioaddr, 124, val);
2158
2159         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2160         if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2161             (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2162              pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2163                 if (lp->options & PCNET32_PORT_ASEL) {
2164                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2165                         netif_printk(lp, link, KERN_DEBUG, dev,
2166                                      "Setting 100Mb-Full Duplex\n");
2167                 }
2168         }
2169         if (lp->phycount < 2) {
2170                 /*
2171                  * 24 Jun 2004 according AMD, in order to change the PHY,
2172                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2173                  * duplex, and/or enable auto negotiation, and clear DANAS
2174                  */
2175                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2176                         lp->a->write_bcr(ioaddr, 32,
2177                                         lp->a->read_bcr(ioaddr, 32) | 0x0080);
2178                         /* disable Auto Negotiation, set 10Mpbs, HD */
2179                         val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2180                         if (lp->options & PCNET32_PORT_FD)
2181                                 val |= 0x10;
2182                         if (lp->options & PCNET32_PORT_100)
2183                                 val |= 0x08;
2184                         lp->a->write_bcr(ioaddr, 32, val);
2185                 } else {
2186                         if (lp->options & PCNET32_PORT_ASEL) {
2187                                 lp->a->write_bcr(ioaddr, 32,
2188                                                 lp->a->read_bcr(ioaddr,
2189                                                                32) | 0x0080);
2190                                 /* enable auto negotiate, setup, disable fd */
2191                                 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2192                                 val |= 0x20;
2193                                 lp->a->write_bcr(ioaddr, 32, val);
2194                         }
2195                 }
2196         } else {
2197                 int first_phy = -1;
2198                 u16 bmcr;
2199                 u32 bcr9;
2200                 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2201
2202                 /*
2203                  * There is really no good other way to handle multiple PHYs
2204                  * other than turning off all automatics
2205                  */
2206                 val = lp->a->read_bcr(ioaddr, 2);
2207                 lp->a->write_bcr(ioaddr, 2, val & ~2);
2208                 val = lp->a->read_bcr(ioaddr, 32);
2209                 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7));  /* stop MII manager */
2210
2211                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2212                         /* setup ecmd */
2213                         ecmd.port = PORT_MII;
2214                         ecmd.transceiver = XCVR_INTERNAL;
2215                         ecmd.autoneg = AUTONEG_DISABLE;
2216                         ethtool_cmd_speed_set(&ecmd,
2217                                               (lp->options & PCNET32_PORT_100) ?
2218                                               SPEED_100 : SPEED_10);
2219                         bcr9 = lp->a->read_bcr(ioaddr, 9);
2220
2221                         if (lp->options & PCNET32_PORT_FD) {
2222                                 ecmd.duplex = DUPLEX_FULL;
2223                                 bcr9 |= (1 << 0);
2224                         } else {
2225                                 ecmd.duplex = DUPLEX_HALF;
2226                                 bcr9 |= ~(1 << 0);
2227                         }
2228                         lp->a->write_bcr(ioaddr, 9, bcr9);
2229                 }
2230
2231                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2232                         if (lp->phymask & (1 << i)) {
2233                                 /* isolate all but the first PHY */
2234                                 bmcr = mdio_read(dev, i, MII_BMCR);
2235                                 if (first_phy == -1) {
2236                                         first_phy = i;
2237                                         mdio_write(dev, i, MII_BMCR,
2238                                                    bmcr & ~BMCR_ISOLATE);
2239                                 } else {
2240                                         mdio_write(dev, i, MII_BMCR,
2241                                                    bmcr | BMCR_ISOLATE);
2242                                 }
2243                                 /* use mii_ethtool_sset to setup PHY */
2244                                 lp->mii_if.phy_id = i;
2245                                 ecmd.phy_address = i;
2246                                 if (lp->options & PCNET32_PORT_ASEL) {
2247                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2248                                         ecmd.autoneg = AUTONEG_ENABLE;
2249                                 }
2250                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2251                         }
2252                 }
2253                 lp->mii_if.phy_id = first_phy;
2254                 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2255         }
2256
2257 #ifdef DO_DXSUFLO
2258         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2259                 val = lp->a->read_csr(ioaddr, CSR3);
2260                 val |= 0x40;
2261                 lp->a->write_csr(ioaddr, CSR3, val);
2262         }
2263 #endif
2264
2265         lp->init_block->mode =
2266             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2267         pcnet32_load_multicast(dev);
2268
2269         if (pcnet32_init_ring(dev)) {
2270                 rc = -ENOMEM;
2271                 goto err_free_ring;
2272         }
2273
2274         napi_enable(&lp->napi);
2275
2276         /* Re-initialize the PCNET32, and start it when done. */
2277         lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2278         lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2279
2280         lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2281         lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2282
2283         netif_start_queue(dev);
2284
2285         if (lp->chip_version >= PCNET32_79C970A) {
2286                 /* Print the link status and start the watchdog */
2287                 pcnet32_check_media(dev, 1);
2288                 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2289         }
2290
2291         i = 0;
2292         while (i++ < 100)
2293                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2294                         break;
2295         /*
2296          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2297          * reports that doing so triggers a bug in the '974.
2298          */
2299         lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2300
2301         netif_printk(lp, ifup, KERN_DEBUG, dev,
2302                      "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2303                      i,
2304                      (u32) (lp->init_dma_addr),
2305                      lp->a->read_csr(ioaddr, CSR0));
2306
2307         spin_unlock_irqrestore(&lp->lock, flags);
2308
2309         return 0;               /* Always succeed */
2310
2311 err_free_ring:
2312         /* free any allocated skbuffs */
2313         pcnet32_purge_rx_ring(dev);
2314
2315         /*
2316          * Switch back to 16bit mode to avoid problems with dumb
2317          * DOS packet driver after a warm reboot
2318          */
2319         lp->a->write_bcr(ioaddr, 20, 4);
2320
2321 err_free_irq:
2322         spin_unlock_irqrestore(&lp->lock, flags);
2323         free_irq(dev->irq, dev);
2324         return rc;
2325 }
2326
2327 /*
2328  * The LANCE has been halted for one reason or another (busmaster memory
2329  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2330  * etc.).  Modern LANCE variants always reload their ring-buffer
2331  * configuration when restarted, so we must reinitialize our ring
2332  * context before restarting.  As part of this reinitialization,
2333  * find all packets still on the Tx ring and pretend that they had been
2334  * sent (in effect, drop the packets on the floor) - the higher-level
2335  * protocols will time out and retransmit.  It'd be better to shuffle
2336  * these skbs to a temp list and then actually re-Tx them after
2337  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2338  */
2339
2340 static void pcnet32_purge_tx_ring(struct net_device *dev)
2341 {
2342         struct pcnet32_private *lp = netdev_priv(dev);
2343         int i;
2344
2345         for (i = 0; i < lp->tx_ring_size; i++) {
2346                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2347                 wmb();          /* Make sure adapter sees owner change */
2348                 if (lp->tx_skbuff[i]) {
2349                         if (!pci_dma_mapping_error(lp->pci_dev,
2350                                                    lp->tx_dma_addr[i]))
2351                                 pci_unmap_single(lp->pci_dev,
2352                                                  lp->tx_dma_addr[i],
2353                                                  lp->tx_skbuff[i]->len,
2354                                                  PCI_DMA_TODEVICE);
2355                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2356                 }
2357                 lp->tx_skbuff[i] = NULL;
2358                 lp->tx_dma_addr[i] = 0;
2359         }
2360 }
2361
2362 /* Initialize the PCNET32 Rx and Tx rings. */
2363 static int pcnet32_init_ring(struct net_device *dev)
2364 {
2365         struct pcnet32_private *lp = netdev_priv(dev);
2366         int i;
2367
2368         lp->tx_full = 0;
2369         lp->cur_rx = lp->cur_tx = 0;
2370         lp->dirty_rx = lp->dirty_tx = 0;
2371
2372         for (i = 0; i < lp->rx_ring_size; i++) {
2373                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2374                 if (rx_skbuff == NULL) {
2375                         lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2376                         rx_skbuff = lp->rx_skbuff[i];
2377                         if (!rx_skbuff) {
2378                                 /* there is not much we can do at this point */
2379                                 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2380                                           __func__);
2381                                 return -1;
2382                         }
2383                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2384                 }
2385
2386                 rmb();
2387                 if (lp->rx_dma_addr[i] == 0) {
2388                         lp->rx_dma_addr[i] =
2389                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2390                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2391                         if (pci_dma_mapping_error(lp->pci_dev,
2392                                                   lp->rx_dma_addr[i])) {
2393                                 /* there is not much we can do at this point */
2394                                 netif_err(lp, drv, dev,
2395                                           "%s pci dma mapping error\n",
2396                                           __func__);
2397                                 return -1;
2398                         }
2399                 }
2400                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2401                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2402                 wmb();          /* Make sure owner changes after all others are visible */
2403                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2404         }
2405         /* The Tx buffer address is filled in as needed, but we do need to clear
2406          * the upper ownership bit. */
2407         for (i = 0; i < lp->tx_ring_size; i++) {
2408                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2409                 wmb();          /* Make sure adapter sees owner change */
2410                 lp->tx_ring[i].base = 0;
2411                 lp->tx_dma_addr[i] = 0;
2412         }
2413
2414         lp->init_block->tlen_rlen =
2415             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2416         for (i = 0; i < 6; i++)
2417                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2418         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2419         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2420         wmb();                  /* Make sure all changes are visible */
2421         return 0;
2422 }
2423
2424 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2425  * then flush the pending transmit operations, re-initialize the ring,
2426  * and tell the chip to initialize.
2427  */
2428 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2429 {
2430         struct pcnet32_private *lp = netdev_priv(dev);
2431         unsigned long ioaddr = dev->base_addr;
2432         int i;
2433
2434         /* wait for stop */
2435         for (i = 0; i < 100; i++)
2436                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2437                         break;
2438
2439         if (i >= 100)
2440                 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2441                           __func__);
2442
2443         pcnet32_purge_tx_ring(dev);
2444         if (pcnet32_init_ring(dev))
2445                 return;
2446
2447         /* ReInit Ring */
2448         lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2449         i = 0;
2450         while (i++ < 1000)
2451                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2452                         break;
2453
2454         lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2455 }
2456
2457 static void pcnet32_tx_timeout(struct net_device *dev)
2458 {
2459         struct pcnet32_private *lp = netdev_priv(dev);
2460         unsigned long ioaddr = dev->base_addr, flags;
2461
2462         spin_lock_irqsave(&lp->lock, flags);
2463         /* Transmitter timeout, serious problems. */
2464         if (pcnet32_debug & NETIF_MSG_DRV)
2465                 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2466                        dev->name, lp->a->read_csr(ioaddr, CSR0));
2467         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2468         dev->stats.tx_errors++;
2469         if (netif_msg_tx_err(lp)) {
2470                 int i;
2471                 printk(KERN_DEBUG
2472                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2473                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2474                        lp->cur_rx);
2475                 for (i = 0; i < lp->rx_ring_size; i++)
2476                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2477                                le32_to_cpu(lp->rx_ring[i].base),
2478                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2479                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2480                                le16_to_cpu(lp->rx_ring[i].status));
2481                 for (i = 0; i < lp->tx_ring_size; i++)
2482                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2483                                le32_to_cpu(lp->tx_ring[i].base),
2484                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2485                                le32_to_cpu(lp->tx_ring[i].misc),
2486                                le16_to_cpu(lp->tx_ring[i].status));
2487                 printk("\n");
2488         }
2489         pcnet32_restart(dev, CSR0_NORMAL);
2490
2491         netif_trans_update(dev); /* prevent tx timeout */
2492         netif_wake_queue(dev);
2493
2494         spin_unlock_irqrestore(&lp->lock, flags);
2495 }
2496
2497 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2498                                       struct net_device *dev)
2499 {
2500         struct pcnet32_private *lp = netdev_priv(dev);
2501         unsigned long ioaddr = dev->base_addr;
2502         u16 status;
2503         int entry;
2504         unsigned long flags;
2505
2506         spin_lock_irqsave(&lp->lock, flags);
2507
2508         netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2509                      "%s() called, csr0 %4.4x\n",
2510                      __func__, lp->a->read_csr(ioaddr, CSR0));
2511
2512         /* Default status -- will not enable Successful-TxDone
2513          * interrupt when that option is available to us.
2514          */
2515         status = 0x8300;
2516
2517         /* Fill in a Tx ring entry */
2518
2519         /* Mask to ring buffer boundary. */
2520         entry = lp->cur_tx & lp->tx_mod_mask;
2521
2522         /* Caution: the write order is important here, set the status
2523          * with the "ownership" bits last. */
2524
2525         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2526
2527         lp->tx_ring[entry].misc = 0x00000000;
2528
2529         lp->tx_dma_addr[entry] =
2530             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2531         if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[entry])) {
2532                 dev_kfree_skb_any(skb);
2533                 dev->stats.tx_dropped++;
2534                 goto drop_packet;
2535         }
2536         lp->tx_skbuff[entry] = skb;
2537         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2538         wmb();                  /* Make sure owner changes after all others are visible */
2539         lp->tx_ring[entry].status = cpu_to_le16(status);
2540
2541         lp->cur_tx++;
2542         dev->stats.tx_bytes += skb->len;
2543
2544         /* Trigger an immediate send poll. */
2545         lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2546
2547         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2548                 lp->tx_full = 1;
2549                 netif_stop_queue(dev);
2550         }
2551 drop_packet:
2552         spin_unlock_irqrestore(&lp->lock, flags);
2553         return NETDEV_TX_OK;
2554 }
2555
2556 /* The PCNET32 interrupt handler. */
2557 static irqreturn_t
2558 pcnet32_interrupt(int irq, void *dev_id)
2559 {
2560         struct net_device *dev = dev_id;
2561         struct pcnet32_private *lp;
2562         unsigned long ioaddr;
2563         u16 csr0;
2564         int boguscnt = max_interrupt_work;
2565
2566         ioaddr = dev->base_addr;
2567         lp = netdev_priv(dev);
2568
2569         spin_lock(&lp->lock);
2570
2571         csr0 = lp->a->read_csr(ioaddr, CSR0);
2572         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2573                 if (csr0 == 0xffff)
2574                         break;  /* PCMCIA remove happened */
2575                 /* Acknowledge all of the current interrupt sources ASAP. */
2576                 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2577
2578                 netif_printk(lp, intr, KERN_DEBUG, dev,
2579                              "interrupt  csr0=%#2.2x new csr=%#2.2x\n",
2580                              csr0, lp->a->read_csr(ioaddr, CSR0));
2581
2582                 /* Log misc errors. */
2583                 if (csr0 & 0x4000)
2584                         dev->stats.tx_errors++; /* Tx babble. */
2585                 if (csr0 & 0x1000) {
2586                         /*
2587                          * This happens when our receive ring is full. This
2588                          * shouldn't be a problem as we will see normal rx
2589                          * interrupts for the frames in the receive ring.  But
2590                          * there are some PCI chipsets (I can reproduce this
2591                          * on SP3G with Intel saturn chipset) which have
2592                          * sometimes problems and will fill up the receive
2593                          * ring with error descriptors.  In this situation we
2594                          * don't get a rx interrupt, but a missed frame
2595                          * interrupt sooner or later.
2596                          */
2597                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2598                 }
2599                 if (csr0 & 0x0800) {
2600                         netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2601                                   csr0);
2602                         /* unlike for the lance, there is no restart needed */
2603                 }
2604                 if (napi_schedule_prep(&lp->napi)) {
2605                         u16 val;
2606                         /* set interrupt masks */
2607                         val = lp->a->read_csr(ioaddr, CSR3);
2608                         val |= 0x5f00;
2609                         lp->a->write_csr(ioaddr, CSR3, val);
2610
2611                         __napi_schedule(&lp->napi);
2612                         break;
2613                 }
2614                 csr0 = lp->a->read_csr(ioaddr, CSR0);
2615         }
2616
2617         netif_printk(lp, intr, KERN_DEBUG, dev,
2618                      "exiting interrupt, csr0=%#4.4x\n",
2619                      lp->a->read_csr(ioaddr, CSR0));
2620
2621         spin_unlock(&lp->lock);
2622
2623         return IRQ_HANDLED;
2624 }
2625
2626 static int pcnet32_close(struct net_device *dev)
2627 {
2628         unsigned long ioaddr = dev->base_addr;
2629         struct pcnet32_private *lp = netdev_priv(dev);
2630         unsigned long flags;
2631
2632         del_timer_sync(&lp->watchdog_timer);
2633
2634         netif_stop_queue(dev);
2635         napi_disable(&lp->napi);
2636
2637         spin_lock_irqsave(&lp->lock, flags);
2638
2639         dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2640
2641         netif_printk(lp, ifdown, KERN_DEBUG, dev,
2642                      "Shutting down ethercard, status was %2.2x\n",
2643                      lp->a->read_csr(ioaddr, CSR0));
2644
2645         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2646         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2647
2648         /*
2649          * Switch back to 16bit mode to avoid problems with dumb
2650          * DOS packet driver after a warm reboot
2651          */
2652         lp->a->write_bcr(ioaddr, 20, 4);
2653
2654         spin_unlock_irqrestore(&lp->lock, flags);
2655
2656         free_irq(dev->irq, dev);
2657
2658         spin_lock_irqsave(&lp->lock, flags);
2659
2660         pcnet32_purge_rx_ring(dev);
2661         pcnet32_purge_tx_ring(dev);
2662
2663         spin_unlock_irqrestore(&lp->lock, flags);
2664
2665         return 0;
2666 }
2667
2668 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2669 {
2670         struct pcnet32_private *lp = netdev_priv(dev);
2671         unsigned long ioaddr = dev->base_addr;
2672         unsigned long flags;
2673
2674         spin_lock_irqsave(&lp->lock, flags);
2675         dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2676         spin_unlock_irqrestore(&lp->lock, flags);
2677
2678         return &dev->stats;
2679 }
2680
2681 /* taken from the sunlance driver, which it took from the depca driver */
2682 static void pcnet32_load_multicast(struct net_device *dev)
2683 {
2684         struct pcnet32_private *lp = netdev_priv(dev);
2685         volatile struct pcnet32_init_block *ib = lp->init_block;
2686         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2687         struct netdev_hw_addr *ha;
2688         unsigned long ioaddr = dev->base_addr;
2689         int i;
2690         u32 crc;
2691
2692         /* set all multicast bits */
2693         if (dev->flags & IFF_ALLMULTI) {
2694                 ib->filter[0] = cpu_to_le32(~0U);
2695                 ib->filter[1] = cpu_to_le32(~0U);
2696                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2697                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2698                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2699                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2700                 return;
2701         }
2702         /* clear the multicast filter */
2703         ib->filter[0] = 0;
2704         ib->filter[1] = 0;
2705
2706         /* Add addresses */
2707         netdev_for_each_mc_addr(ha, dev) {
2708                 crc = ether_crc_le(6, ha->addr);
2709                 crc = crc >> 26;
2710                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2711         }
2712         for (i = 0; i < 4; i++)
2713                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2714                                 le16_to_cpu(mcast_table[i]));
2715 }
2716
2717 /*
2718  * Set or clear the multicast filter for this adaptor.
2719  */
2720 static void pcnet32_set_multicast_list(struct net_device *dev)
2721 {
2722         unsigned long ioaddr = dev->base_addr, flags;
2723         struct pcnet32_private *lp = netdev_priv(dev);
2724         int csr15, suspended;
2725
2726         spin_lock_irqsave(&lp->lock, flags);
2727         suspended = pcnet32_suspend(dev, &flags, 0);
2728         csr15 = lp->a->read_csr(ioaddr, CSR15);
2729         if (dev->flags & IFF_PROMISC) {
2730                 /* Log any net taps. */
2731                 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2732                 lp->init_block->mode =
2733                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2734                                 7);
2735                 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2736         } else {
2737                 lp->init_block->mode =
2738                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2739                 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2740                 pcnet32_load_multicast(dev);
2741         }
2742
2743         if (suspended) {
2744                 pcnet32_clr_suspend(lp, ioaddr);
2745         } else {
2746                 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2747                 pcnet32_restart(dev, CSR0_NORMAL);
2748                 netif_wake_queue(dev);
2749         }
2750
2751         spin_unlock_irqrestore(&lp->lock, flags);
2752 }
2753
2754 /* This routine assumes that the lp->lock is held */
2755 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2756 {
2757         struct pcnet32_private *lp = netdev_priv(dev);
2758         unsigned long ioaddr = dev->base_addr;
2759         u16 val_out;
2760
2761         if (!lp->mii)
2762                 return 0;
2763
2764         lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2765         val_out = lp->a->read_bcr(ioaddr, 34);
2766
2767         return val_out;
2768 }
2769
2770 /* This routine assumes that the lp->lock is held */
2771 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2772 {
2773         struct pcnet32_private *lp = netdev_priv(dev);
2774         unsigned long ioaddr = dev->base_addr;
2775
2776         if (!lp->mii)
2777                 return;
2778
2779         lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2780         lp->a->write_bcr(ioaddr, 34, val);
2781 }
2782
2783 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2784 {
2785         struct pcnet32_private *lp = netdev_priv(dev);
2786         int rc;
2787         unsigned long flags;
2788
2789         /* SIOC[GS]MIIxxx ioctls */
2790         if (lp->mii) {
2791                 spin_lock_irqsave(&lp->lock, flags);
2792                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2793                 spin_unlock_irqrestore(&lp->lock, flags);
2794         } else {
2795                 rc = -EOPNOTSUPP;
2796         }
2797
2798         return rc;
2799 }
2800
2801 static int pcnet32_check_otherphy(struct net_device *dev)
2802 {
2803         struct pcnet32_private *lp = netdev_priv(dev);
2804         struct mii_if_info mii = lp->mii_if;
2805         u16 bmcr;
2806         int i;
2807
2808         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2809                 if (i == lp->mii_if.phy_id)
2810                         continue;       /* skip active phy */
2811                 if (lp->phymask & (1 << i)) {
2812                         mii.phy_id = i;
2813                         if (mii_link_ok(&mii)) {
2814                                 /* found PHY with active link */
2815                                 netif_info(lp, link, dev, "Using PHY number %d\n",
2816                                            i);
2817
2818                                 /* isolate inactive phy */
2819                                 bmcr =
2820                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2821                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2822                                            bmcr | BMCR_ISOLATE);
2823
2824                                 /* de-isolate new phy */
2825                                 bmcr = mdio_read(dev, i, MII_BMCR);
2826                                 mdio_write(dev, i, MII_BMCR,
2827                                            bmcr & ~BMCR_ISOLATE);
2828
2829                                 /* set new phy address */
2830                                 lp->mii_if.phy_id = i;
2831                                 return 1;
2832                         }
2833                 }
2834         }
2835         return 0;
2836 }
2837
2838 /*
2839  * Show the status of the media.  Similar to mii_check_media however it
2840  * correctly shows the link speed for all (tested) pcnet32 variants.
2841  * Devices with no mii just report link state without speed.
2842  *
2843  * Caller is assumed to hold and release the lp->lock.
2844  */
2845
2846 static void pcnet32_check_media(struct net_device *dev, int verbose)
2847 {
2848         struct pcnet32_private *lp = netdev_priv(dev);
2849         int curr_link;
2850         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2851         u32 bcr9;
2852
2853         if (lp->mii) {
2854                 curr_link = mii_link_ok(&lp->mii_if);
2855         } else if (lp->chip_version == PCNET32_79C970A) {
2856                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2857                 /* only read link if port is set to TP */
2858                 if (!lp->autoneg && lp->port_tp)
2859                         curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2860                 else /* link always up for AUI port or port auto select */
2861                         curr_link = 1;
2862         } else {
2863                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2864                 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2865         }
2866         if (!curr_link) {
2867                 if (prev_link || verbose) {
2868                         netif_carrier_off(dev);
2869                         netif_info(lp, link, dev, "link down\n");
2870                 }
2871                 if (lp->phycount > 1) {
2872                         curr_link = pcnet32_check_otherphy(dev);
2873                         prev_link = 0;
2874                 }
2875         } else if (verbose || !prev_link) {
2876                 netif_carrier_on(dev);
2877                 if (lp->mii) {
2878                         if (netif_msg_link(lp)) {
2879                                 struct ethtool_cmd ecmd = {
2880                                         .cmd = ETHTOOL_GSET };
2881                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2882                                 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2883                                             ethtool_cmd_speed(&ecmd),
2884                                             (ecmd.duplex == DUPLEX_FULL)
2885                                             ? "full" : "half");
2886                         }
2887                         bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2888                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2889                                 if (lp->mii_if.full_duplex)
2890                                         bcr9 |= (1 << 0);
2891                                 else
2892                                         bcr9 &= ~(1 << 0);
2893                                 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2894                         }
2895                 } else {
2896                         netif_info(lp, link, dev, "link up\n");
2897                 }
2898         }
2899 }
2900
2901 /*
2902  * Check for loss of link and link establishment.
2903  * Could possibly be changed to use mii_check_media instead.
2904  */
2905
2906 static void pcnet32_watchdog(struct net_device *dev)
2907 {
2908         struct pcnet32_private *lp = netdev_priv(dev);
2909         unsigned long flags;
2910
2911         /* Print the link status if it has changed */
2912         spin_lock_irqsave(&lp->lock, flags);
2913         pcnet32_check_media(dev, 0);
2914         spin_unlock_irqrestore(&lp->lock, flags);
2915
2916         mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2917 }
2918
2919 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2920 {
2921         struct net_device *dev = pci_get_drvdata(pdev);
2922
2923         if (netif_running(dev)) {
2924                 netif_device_detach(dev);
2925                 pcnet32_close(dev);
2926         }
2927         pci_save_state(pdev);
2928         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2929         return 0;
2930 }
2931
2932 static int pcnet32_pm_resume(struct pci_dev *pdev)
2933 {
2934         struct net_device *dev = pci_get_drvdata(pdev);
2935
2936         pci_set_power_state(pdev, PCI_D0);
2937         pci_restore_state(pdev);
2938
2939         if (netif_running(dev)) {
2940                 pcnet32_open(dev);
2941                 netif_device_attach(dev);
2942         }
2943         return 0;
2944 }
2945
2946 static void pcnet32_remove_one(struct pci_dev *pdev)
2947 {
2948         struct net_device *dev = pci_get_drvdata(pdev);
2949
2950         if (dev) {
2951                 struct pcnet32_private *lp = netdev_priv(dev);
2952
2953                 unregister_netdev(dev);
2954                 pcnet32_free_ring(dev);
2955                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2956                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2957                                     lp->init_block, lp->init_dma_addr);
2958                 free_netdev(dev);
2959                 pci_disable_device(pdev);
2960         }
2961 }
2962
2963 static struct pci_driver pcnet32_driver = {
2964         .name = DRV_NAME,
2965         .probe = pcnet32_probe_pci,
2966         .remove = pcnet32_remove_one,
2967         .id_table = pcnet32_pci_tbl,
2968         .suspend = pcnet32_pm_suspend,
2969         .resume = pcnet32_pm_resume,
2970 };
2971
2972 /* An additional parameter that may be passed in... */
2973 static int debug = -1;
2974 static int tx_start_pt = -1;
2975 static int pcnet32_have_pci;
2976
2977 module_param(debug, int, 0);
2978 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2979 module_param(max_interrupt_work, int, 0);
2980 MODULE_PARM_DESC(max_interrupt_work,
2981                  DRV_NAME " maximum events handled per interrupt");
2982 module_param(rx_copybreak, int, 0);
2983 MODULE_PARM_DESC(rx_copybreak,
2984                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2985 module_param(tx_start_pt, int, 0);
2986 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2987 module_param(pcnet32vlb, int, 0);
2988 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2989 module_param_array(options, int, NULL, 0);
2990 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2991 module_param_array(full_duplex, int, NULL, 0);
2992 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2993 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2994 module_param_array(homepna, int, NULL, 0);
2995 MODULE_PARM_DESC(homepna,
2996                  DRV_NAME
2997                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2998
2999 MODULE_AUTHOR("Thomas Bogendoerfer");
3000 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3001 MODULE_LICENSE("GPL");
3002
3003 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3004
3005 static int __init pcnet32_init_module(void)
3006 {
3007         pr_info("%s", version);
3008
3009         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3010
3011         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3012                 tx_start = tx_start_pt;
3013
3014         /* find the PCI devices */
3015         if (!pci_register_driver(&pcnet32_driver))
3016                 pcnet32_have_pci = 1;
3017
3018         /* should we find any remaining VLbus devices ? */
3019         if (pcnet32vlb)
3020                 pcnet32_probe_vlbus(pcnet32_portlist);
3021
3022         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3023                 pr_info("%d cards_found\n", cards_found);
3024
3025         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3026 }
3027
3028 static void __exit pcnet32_cleanup_module(void)
3029 {
3030         struct net_device *next_dev;
3031
3032         while (pcnet32_dev) {
3033                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3034                 next_dev = lp->next;
3035                 unregister_netdev(pcnet32_dev);
3036                 pcnet32_free_ring(pcnet32_dev);
3037                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3038                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3039                                     lp->init_block, lp->init_dma_addr);
3040                 free_netdev(pcnet32_dev);
3041                 pcnet32_dev = next_dev;
3042         }
3043
3044         if (pcnet32_have_pci)
3045                 pci_unregister_driver(&pcnet32_driver);
3046 }
3047
3048 module_init(pcnet32_init_module);
3049 module_exit(pcnet32_cleanup_module);
3050
3051 /*
3052  * Local variables:
3053  *  c-indent-level: 4
3054  *  tab-width: 8
3055  * End:
3056  */